diff --git a/common_modules/inc/txm_module.h b/common_modules/inc/txm_module.h new file mode 100644 index 00000000..8625cf40 --- /dev/null +++ b/common_modules/inc/txm_module.h @@ -0,0 +1,684 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Interface (API) */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* txm_module.h PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the basic module constants, interface structures, */ +/* and function prototypes. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TXM_MODULE_H +#define TXM_MODULE_H + + +/* Include the standard ThreadX API file. */ + +#include "tx_api.h" + +/* Include the module port specific file. */ + +#include "txm_module_port.h" + + +/* Include any supported external component include files. */ + +#ifdef TXM_MODULE_ENABLE_FILEX +#include "txm_module_filex.h" +#endif + +#ifdef TXM_MODULE_ENABLE_GUIX +#include "txm_module_guix.h" +#endif + +#ifdef TXM_MODULE_ENABLE_NETX +#include "txm_module_netx.h" +#endif + +#ifdef TXM_MODULE_ENABLE_NETXDUO +#include "txm_module_netxduo.h" +#endif + +#ifdef TXM_MODULE_ENABLE_USBX +#include "txm_module_usbx.h" +#endif + + +#ifdef FX_FILEX_PRESENT +#include "fx_api.h" +#endif + + +/* Determine if a C++ compiler is being used. If so, ensure that standard + C is used to process the API information. */ + +#ifdef __cplusplus + +/* Yes, C++ compiler is present. Use standard C. */ +extern "C" { + +#endif + + +/* Define the Module ID, which is used to indicate a module is valid. */ + +#define TXM_MODULE_ID 0x4D4F4455 + + +/* Define valid module states. */ + +#define TXM_MODULE_LOADED 1 +#define TXM_MODULE_STARTED 2 +#define TXM_MODULE_STOPPING 3 +#define TXM_MODULE_STOPPED 4 +#define TXM_MODULE_UNLOADED 5 + + +/* Define module manager error codes. */ + +#define TXM_MODULE_ALIGNMENT_ERROR 0xF0 +#define TXM_MODULE_ALREADY_LOADED 0xF1 +#define TXM_MODULE_INVALID 0xF2 +#define TXM_MODULE_INVALID_PROPERTIES 0xF3 +#define TXM_MODULE_INVALID_MEMORY 0xF4 +#define TXM_MODULE_INVALID_CALLBACK 0xF5 +#define TXM_MODULE_INVALID_STACK_SIZE 0xF6 +#define TXM_MODULE_FILEX_INVALID_BYTES_READ 0xF7 +#define TXM_MODULE_MATH_OVERFLOW 0xF8 + + +/* Define the data area alignment mask, must be a power of 2. */ + +#ifndef TXM_MODULE_DATA_ALIGNMENT +#define TXM_MODULE_DATA_ALIGNMENT 4 +#endif + + +/* Define the code area alignment mask, must be a power of 2. */ + +#ifndef TXM_MODULE_CODE_ALIGNMENT +#define TXM_MODULE_CODE_ALIGNMENT 4 +#endif + + +/* Define module timeout for waiting for module to finish. */ + +#ifndef TXM_MODULE_TIMEOUT +#define TXM_MODULE_TIMEOUT 100 +#endif + + +/* Define module thread time-slice default. */ + +#ifndef TXM_MODULE_TIME_SLICE +#define TXM_MODULE_TIME_SLICE 4 +#endif + + +/* Define each module's callback queue depth. This is used to queue up incoming call back requests. */ + +#ifndef TXM_MODULE_CALLBACKS_QUEUE_DEPTH +#define TXM_MODULE_CALLBACKS_QUEUE_DEPTH 8 /* Number queued callback requests. */ +#endif + + +/* Define the module manager thread's stack size. */ + +#ifndef TXM_MODULE_MANAGER_THREAD_STACK_SIZE +#define TXM_MODULE_MANAGER_THREAD_STACK_SIZE 1024 +#endif + + +/* Define the module manager thread's priority. */ + +#ifndef TXM_MODULE_MANAGER_THREAD_PRIORITY +#define TXM_MODULE_MANAGER_THREAD_PRIORITY 1 +#endif + + +/* Define the module's callback handler thread's stack size. */ + +#ifndef TXM_MODULE_CALLBACK_THREAD_STACK_SIZE +#define TXM_MODULE_CALLBACK_THREAD_STACK_SIZE 1024 +#endif + + +/* Define the default port-specific macro for resetting the thread. */ + +#ifndef TXM_MODULE_MANAGER_THREAD_RESET_PORT_COMPLETION +#define TXM_MODULE_MANAGER_THREAD_RESET_PORT_COMPLETION(thread_ptr, module_instance) +#endif + + +/* Define object types for object search requests. */ + +#define TXM_BLOCK_POOL_OBJECT 1 +#define TXM_BYTE_POOL_OBJECT 2 +#define TXM_EVENT_FLAGS_OBJECT 3 +#define TXM_MUTEX_OBJECT 4 +#define TXM_QUEUE_OBJECT 5 +#define TXM_SEMAPHORE_OBJECT 6 +#define TXM_THREAD_OBJECT 7 +#define TXM_TIMER_OBJECT 8 +#define TXM_THREAD_KERNEL_STACK_OBJECT 77 +#define TXM_FILEX_OBJECTS_START 100 +#define TXM_FILEX_OBJECTS_END 199 +#define TXM_NETX_OBJECTS_START 200 +#define TXM_NETX_OBJECTS_END 299 +#define TXM_NETXDUO_OBJECTS_START 300 +#define TXM_NETXDUO_OBJECTS_END 399 +#define TXM_USBX_OBJECTS_START 400 +#define TXM_USBX_OBJECTS_END 499 +#define TXM_GUIX_OBJECTS_START 500 +#define TXM_GUIX_OBJECT_END 599 + + +/* Define callback types. */ +#define TXM_THREADX_CALLBACKS_START 0 +#define TXM_THREADX_CALLBACKS_END 99 +#define TXM_FILEX_CALLBACKS_START 100 +#define TXM_FILEX_CALLBACKS_END 199 +#define TXM_NETX_CALLBACKS_START 200 +#define TXM_NETX_CALLBACKS_END 299 +#define TXM_NETXDUO_CALLBACKS_START 300 +#define TXM_NETXDUO_CALLBACKS_END 399 +#define TXM_USBX_CALLBACKS_START 400 +#define TXM_USBX_CALLBACKS_END 499 +#define TXM_GUIX_CALLBACKS_START 500 +#define TXM_GUIX_CALLBACKS_END 599 + +#define TXM_TIMER_CALLBACK 0 +#define TXM_EVENTS_SET_CALLBACK 1 +#define TXM_QUEUE_SEND_CALLBACK 2 +#define TXM_SEMAPHORE_PUT_CALLBACK 3 +#define TXM_THREAD_ENTRY_EXIT_CALLBACK 4 + + +/* Determine the ThreadX kernel API call IDs. */ + +#define TXM_BLOCK_ALLOCATE_CALL 1 +#define TXM_BLOCK_POOL_CREATE_CALL 2 +#define TXM_BLOCK_POOL_DELETE_CALL 3 +#define TXM_BLOCK_POOL_INFO_GET_CALL 4 +#define TXM_BLOCK_POOL_PERFORMANCE_INFO_GET_CALL 5 +#define TXM_BLOCK_POOL_PERFORMANCE_SYSTEM_INFO_GET_CALL 6 +#define TXM_BLOCK_POOL_PRIORITIZE_CALL 7 +#define TXM_BLOCK_RELEASE_CALL 8 +#define TXM_BYTE_ALLOCATE_CALL 9 +#define TXM_BYTE_POOL_CREATE_CALL 10 +#define TXM_BYTE_POOL_DELETE_CALL 11 +#define TXM_BYTE_POOL_INFO_GET_CALL 12 +#define TXM_BYTE_POOL_PERFORMANCE_INFO_GET_CALL 13 +#define TXM_BYTE_POOL_PERFORMANCE_SYSTEM_INFO_GET_CALL 14 +#define TXM_BYTE_POOL_PRIORITIZE_CALL 15 +#define TXM_BYTE_RELEASE_CALL 16 +#define TXM_EVENT_FLAGS_CREATE_CALL 17 +#define TXM_EVENT_FLAGS_DELETE_CALL 18 +#define TXM_EVENT_FLAGS_GET_CALL 19 +#define TXM_EVENT_FLAGS_INFO_GET_CALL 20 +#define TXM_EVENT_FLAGS_PERFORMANCE_INFO_GET_CALL 21 +#define TXM_EVENT_FLAGS_PERFORMANCE_SYSTEM_INFO_GET_CALL 22 +#define TXM_EVENT_FLAGS_SET_CALL 23 +#define TXM_EVENT_FLAGS_SET_NOTIFY_CALL 24 +#define TXM_THREAD_INTERRUPT_CONTROL_CALL 25 +#define TXM_MUTEX_CREATE_CALL 26 +#define TXM_MUTEX_DELETE_CALL 27 +#define TXM_MUTEX_GET_CALL 28 +#define TXM_MUTEX_INFO_GET_CALL 29 +#define TXM_MUTEX_PERFORMANCE_INFO_GET_CALL 30 +#define TXM_MUTEX_PERFORMANCE_SYSTEM_INFO_GET_CALL 31 +#define TXM_MUTEX_PRIORITIZE_CALL 32 +#define TXM_MUTEX_PUT_CALL 33 +#define TXM_QUEUE_CREATE_CALL 34 +#define TXM_QUEUE_DELETE_CALL 35 +#define TXM_QUEUE_FLUSH_CALL 36 +#define TXM_QUEUE_FRONT_SEND_CALL 37 +#define TXM_QUEUE_INFO_GET_CALL 38 +#define TXM_QUEUE_PERFORMANCE_INFO_GET_CALL 39 +#define TXM_QUEUE_PERFORMANCE_SYSTEM_INFO_GET_CALL 40 +#define TXM_QUEUE_PRIORITIZE_CALL 41 +#define TXM_QUEUE_RECEIVE_CALL 42 +#define TXM_QUEUE_SEND_CALL 43 +#define TXM_QUEUE_SEND_NOTIFY_CALL 44 +#define TXM_SEMAPHORE_CEILING_PUT_CALL 45 +#define TXM_SEMAPHORE_CREATE_CALL 46 +#define TXM_SEMAPHORE_DELETE_CALL 47 +#define TXM_SEMAPHORE_GET_CALL 48 +#define TXM_SEMAPHORE_INFO_GET_CALL 49 +#define TXM_SEMAPHORE_PERFORMANCE_INFO_GET_CALL 50 +#define TXM_SEMAPHORE_PERFORMANCE_SYSTEM_INFO_GET_CALL 51 +#define TXM_SEMAPHORE_PRIORITIZE_CALL 52 +#define TXM_SEMAPHORE_PUT_CALL 53 +#define TXM_SEMAPHORE_PUT_NOTIFY_CALL 54 +#define TXM_THREAD_CREATE_CALL 55 +#define TXM_THREAD_DELETE_CALL 56 +#define TXM_THREAD_ENTRY_EXIT_NOTIFY_CALL 57 +#define TXM_THREAD_IDENTIFY_CALL 58 +#define TXM_THREAD_INFO_GET_CALL 59 +#define TXM_THREAD_PERFORMANCE_INFO_GET_CALL 60 +#define TXM_THREAD_PERFORMANCE_SYSTEM_INFO_GET_CALL 61 +#define TXM_THREAD_PREEMPTION_CHANGE_CALL 62 +#define TXM_THREAD_PRIORITY_CHANGE_CALL 63 +#define TXM_THREAD_RELINQUISH_CALL 64 +#define TXM_THREAD_RESET_CALL 65 +#define TXM_THREAD_RESUME_CALL 66 +#define TXM_THREAD_SLEEP_CALL 67 +#define TXM_THREAD_STACK_ERROR_NOTIFY_CALL 68 +#define TXM_THREAD_SUSPEND_CALL 69 +#define TXM_THREAD_TERMINATE_CALL 70 +#define TXM_THREAD_TIME_SLICE_CHANGE_CALL 71 +#define TXM_THREAD_WAIT_ABORT_CALL 72 +#define TXM_TIME_GET_CALL 73 +#define TXM_TIME_SET_CALL 74 +#define TXM_TIMER_ACTIVATE_CALL 75 +#define TXM_TIMER_CHANGE_CALL 76 +#define TXM_TIMER_CREATE_CALL 77 +#define TXM_TIMER_DEACTIVATE_CALL 78 +#define TXM_TIMER_DELETE_CALL 79 +#define TXM_TIMER_INFO_GET_CALL 80 +#define TXM_TIMER_PERFORMANCE_INFO_GET_CALL 81 +#define TXM_TIMER_PERFORMANCE_SYSTEM_INFO_GET_CALL 82 +#define TXM_TRACE_ENABLE_CALL 83 +#define TXM_TRACE_EVENT_FILTER_CALL 84 +#define TXM_TRACE_EVENT_UNFILTER_CALL 85 +#define TXM_TRACE_DISABLE_CALL 86 +#define TXM_TRACE_INTERRUPT_CONTROL_CALL 87 +#define TXM_TRACE_ISR_ENTER_INSERT_CALL 88 +#define TXM_TRACE_ISR_EXIT_INSERT_CALL 89 +#define TXM_TRACE_BUFFER_FULL_NOTIFY_CALL 90 +#define TXM_TRACE_USER_EVENT_INSERT_CALL 91 +#define TXM_THREAD_SYSTEM_SUSPEND_CALL 92 +#define TXM_MODULE_OBJECT_POINTER_GET_CALL 93 +#define TXM_MODULE_OBJECT_POINTER_GET_EXTENDED_CALL 94 +#define TXM_MODULE_OBJECT_ALLOCATE_CALL 95 +#define TXM_MODULE_OBJECT_DEALLOCATE_CALL 96 + + +/* Determine the API call IDs for other components. */ + +#define TXM_FILEX_API_ID_START 1000 +#define TXM_FILEX_API_ID_END 1999 +#define TXM_NETX_API_ID_START 2000 +#define TXM_NETX_API_ID_END 2999 +#define TXM_NETXDUO_API_ID_START 3000 +#define TXM_NETXDUO_API_ID_END 3999 +#define TXM_USBX_API_ID_START 4000 +#define TXM_USBX_API_ID_END 4999 +#define TXM_GUIX_API_ID_START 5000 +#define TXM_GUIX_API_ID_END 5999 + + +/* Determine the application's IDs for calling application code in the resident area. */ + +#define TXM_APPLICATION_REQUEST_ID_BASE 0x10000 + + +/* Define the overlay for the module's preamble. */ + +typedef struct TXM_MODULE_PREAMBLE_STRUCT +{ + /* Meaning */ + ULONG txm_module_preamble_id; /* Download Module ID (0x54584D44) */ + ULONG txm_module_preamble_version_major; /* Major Version ID */ + ULONG txm_module_preamble_version_minor; /* Minor Version ID */ + ULONG txm_module_preamble_preamble_size; /* Module Preamble Size, in 32-bit words */ + ULONG txm_module_preamble_application_module_id; /* Module ID (application defined) */ + ULONG txm_module_preamble_property_flags; /* Properties Bit Map */ + ULONG txm_module_preamble_shell_entry_function; /* Module shell Entry Function */ + ULONG txm_module_preamble_start_function; /* Module Thread Start Function */ + ULONG txm_module_preamble_stop_function; /* Module Thread Stop Function */ + ULONG txm_module_preamble_start_stop_priority; /* Module Start/Stop Thread Priority */ + ULONG txm_module_preamble_start_stop_stack_size; /* Module Start/Stop Thread Priority */ + ULONG txm_module_preamble_callback_function; /* Module Callback Thread Function */ + ULONG txm_module_preamble_callback_priority; /* Module Callback Thread Priority */ + ULONG txm_module_preamble_callback_stack_size; /* Module Callback Thread Stack Size */ + ULONG txm_module_preamble_code_size; /* Module Instruction Area Size */ + ULONG txm_module_preamble_data_size; /* Module Data Area Size */ + ULONG txm_module_preamble_reserved_0; /* Reserved */ + ULONG txm_module_preamble_reserved_1; /* Reserved */ + ULONG txm_module_preamble_reserved_2; /* Reserved */ + ULONG txm_module_preamble_reserved_3; /* Reserved */ + ULONG txm_module_preamble_reserved_4; /* Reserved */ + ULONG txm_module_preamble_reserved_5; /* Reserved */ + ULONG txm_module_preamble_reserved_6; /* Reserved */ + ULONG txm_module_preamble_reserved_7; /* Reserved */ + ULONG txm_module_preamble_reserved_8; /* Reserved */ + ULONG txm_module_preamble_reserved_9; /* Reserved */ + ULONG txm_module_preamble_reserved_10; /* Reserved */ + ULONG txm_module_preamble_reserved_11; /* Reserved */ + ULONG txm_module_preamble_reserved_12; /* Reserved */ + ULONG txm_module_preamble_reserved_13; /* Reserved */ + ULONG txm_module_preamble_reserved_14; /* Reserved */ + ULONG txm_module_preamble_checksum; /* Module Instruction Area Checksum [Optional] */ + +} TXM_MODULE_PREAMBLE; + + +struct TXM_MODULE_ALLOCATED_OBJECT_STRUCT; + + +/* Define the callback notification structure used to communicate between the module's callback handling thread + and the module manager. */ + +typedef struct TXM_MODULE_CALLBACK_MESSAGE_STRUCT +{ + ULONG txm_module_callback_message_type; + ULONG txm_module_callback_message_activation_count; + VOID (*txm_module_callback_message_application_function)(VOID); + ALIGN_TYPE txm_module_callback_message_param_1; + ALIGN_TYPE txm_module_callback_message_param_2; + ALIGN_TYPE txm_module_callback_message_param_3; + ALIGN_TYPE txm_module_callback_message_param_4; + ALIGN_TYPE txm_module_callback_message_param_5; + ALIGN_TYPE txm_module_callback_message_param_6; + ALIGN_TYPE txm_module_callback_message_param_7; + ALIGN_TYPE txm_module_callback_message_param_8; + ALIGN_TYPE txm_module_callback_message_reserved1; + ALIGN_TYPE txm_module_callback_message_reserved2; +} TXM_MODULE_CALLBACK_MESSAGE; + + +/* Define the module's instance for the manager. */ + +typedef struct TXM_MODULE_INSTANCE_STRUCT +{ + ULONG txm_module_instance_id; + CHAR *txm_module_instance_name; + ULONG txm_module_instance_state; + ULONG txm_module_instance_property_flags; + VOID *txm_module_instance_code_allocation_ptr; + ULONG txm_module_instance_code_allocation_size; + VOID *txm_module_instance_code_start; + VOID *txm_module_instance_code_end; + ULONG txm_module_instance_code_size; + VOID *txm_module_instance_data_allocation_ptr; + ULONG txm_module_instance_data_allocation_size; + VOID *txm_module_instance_data_start; + VOID *txm_module_instance_data_end; + VOID *txm_module_instance_module_data_base_address; + ULONG txm_module_instance_data_size; + ULONG txm_module_instance_total_ram_usage; + VOID *txm_module_instance_start_stop_stack_start_address; + VOID *txm_module_instance_start_stop_stack_end_address; + VOID *txm_module_instance_callback_stack_start_address; + VOID *txm_module_instance_callback_stack_end_address; + TXM_MODULE_PREAMBLE *txm_module_instance_preamble_ptr; + VOID (*txm_module_instance_shell_entry_function)(TX_THREAD *, struct TXM_MODULE_INSTANCE_STRUCT *); + VOID (*txm_module_instance_start_thread_entry)(ULONG); + VOID (*txm_module_instance_stop_thread_entry)(ULONG); + VOID (*txm_module_instance_callback_request_thread_entry)(ULONG); + + /* Define the port extention to the module manager structure. */ + TXM_MODULE_MANAGER_PORT_EXTENSION + + TX_THREAD txm_module_instance_start_stop_thread; + TX_THREAD txm_module_instance_callback_request_thread; + TX_QUEUE txm_module_instance_callback_request_queue; + ULONG txm_module_instance_callback_request_queue_area[TXM_MODULE_CALLBACKS_QUEUE_DEPTH * (sizeof(TXM_MODULE_CALLBACK_MESSAGE)/sizeof(ULONG))]; + ULONG txm_module_instance_start_stop_stack_size; + ULONG txm_module_instance_start_stop_priority; + ULONG txm_module_instance_callback_stack_size; + ULONG txm_module_instance_callback_priority; + ULONG txm_module_instance_application_module_id; + UINT txm_module_instance_maximum_priority; + + /* Define the head pointer of the list of objects allocated by the module. */ + struct TXM_MODULE_ALLOCATED_OBJECT_STRUCT + *txm_module_instance_object_list_head; + ULONG txm_module_instance_object_list_count; + + struct TXM_MODULE_INSTANCE_STRUCT + *txm_module_instance_loaded_next, + *txm_module_instance_loaded_previous; +} TXM_MODULE_INSTANCE; + + +/* Determine if the thread entry info control block has an extension defined. If not, define the extension to + whitespace. */ + +#ifndef TXM_MODULE_THREAD_ENTRY_INFO_USER_EXTENSION +#define TXM_MODULE_THREAD_ENTRY_INFO_USER_EXTENSION +#endif + + +/* Define the thread entry information structure. This structure is placed on the thread's stack such that the + module's _txm_thread_shell_entry function does not need to access anything in the thread control block. */ + +typedef struct TXM_MODULE_THREAD_ENTRY_INFO_STRUCT +{ + TX_THREAD *txm_module_thread_entry_info_thread; + TXM_MODULE_INSTANCE *txm_module_thread_entry_info_module; + VOID *txm_module_thread_entry_info_data_base_address; /* Don't move this, referenced in stack build to setup module data base register. */ + VOID *txm_module_thread_entry_info_code_base_address; + VOID (*txm_module_thread_entry_info_entry)(ULONG); + ULONG txm_module_thread_entry_info_parameter; + VOID (*txm_module_thread_entry_info_exit_notify)(struct TX_THREAD_STRUCT *, UINT); + UINT txm_module_thread_entry_info_start_thread; + TX_THREAD *txm_module_thread_entry_info_callback_request_thread; + TX_QUEUE *txm_module_thread_entry_info_callback_request_queue; + VOID *txm_module_thread_entry_info_reserved; + ALIGN_TYPE (*txm_module_thread_entry_info_kernel_call_dispatcher)(ULONG kernel_request, ALIGN_TYPE param_1, ALIGN_TYPE param_2, ALIGN_TYPE param_3); + TXM_MODULE_THREAD_ENTRY_INFO_USER_EXTENSION +} TXM_MODULE_THREAD_ENTRY_INFO; + + +/* Define the linked-list structure used to maintain the module's object allocation. */ + +typedef struct TXM_MODULE_ALLOCATED_OBJECT_STRUCT +{ + + TXM_MODULE_INSTANCE *txm_module_allocated_object_module_instance; + struct TXM_MODULE_ALLOCATED_OBJECT_STRUCT + *txm_module_allocated_object_next, + *txm_module_allocated_object_previous; + ULONG txm_module_object_size; +} TXM_MODULE_ALLOCATED_OBJECT; + + +/* Determine if module code is being compiled. If so, remap the ThreadX API to + the module shell functions that will go through the module <-> module manager + interface. */ + +#ifdef TXM_MODULE + + +/* Define the external reference to the module manager kernel dispatcher function pointer. This is supplied to the module by the module + manager when the module is created and started. */ + +extern ALIGN_TYPE (*_txm_module_kernel_call_dispatcher)(ULONG type, ALIGN_TYPE param_1, ALIGN_TYPE param_2, ALIGN_TYPE param3); + + +/* Define specific module function prototypes. */ + +#define txm_module_application_request _txm_module_application_request +#define txm_module_object_allocate _txm_module_object_allocate +#define txm_module_object_deallocate _txm_module_object_deallocate +#define txm_module_object_pointer_get _txm_module_object_pointer_get +#define txm_module_object_pointer_get_extended _txm_module_object_pointer_get_extended + +VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info); +UINT _txm_module_thread_system_suspend(TX_THREAD *thread_ptr); + +UINT _txm_module_application_request(ULONG request, ALIGN_TYPE param_1, ALIGN_TYPE param_2, ALIGN_TYPE param_3); +UINT _txm_module_object_allocate(VOID **object_ptr, ULONG object_size); +UINT _txm_module_object_deallocate(VOID *object_ptr); +UINT _txm_module_object_pointer_get(UINT object_type, CHAR *name, VOID **object_ptr); +UINT _txm_module_object_pointer_get_extended(UINT object_type, CHAR *name, UINT name_length, VOID **object_ptr); + +/* Module callback functions. */ + +#ifdef TXM_MODULE_ENABLE_NETX +VOID _txm_module_netx_callback_request(TXM_MODULE_CALLBACK_MESSAGE *callback_message); +#endif +#ifdef TXM_MODULE_ENABLE_NETXDUO +VOID _txm_module_netxduo_callback_request(TXM_MODULE_CALLBACK_MESSAGE *callback_message); +#endif +#ifdef TXM_MODULE_ENABLE_FILEX +VOID _txm_module_filex_callback_request(TXM_MODULE_CALLBACK_MESSAGE *callback_message); +#endif +#ifdef TXM_MODULE_ENABLE_GUIX +VOID _txm_module_guix_duo_callback_request(TXM_MODULE_CALLBACK_MESSAGE *callback_message); +#endif +#ifdef TXM_MODULE_ENABLE_USBX +VOID _txm_module_usbx_duo_callback_request(TXM_MODULE_CALLBACK_MESSAGE *callback_message); +#endif + +/* Define the module's thread shell entry function macros. */ + +#define TXM_THREAD_COMPLETED_EXTENSION(a) +#define TXM_THREAD_STATE_CHANGE(a, b) + +#else + + +/* Map the module manager APIs just in case this is being included from the module manager in the + resident portion of the application. */ + +#define txm_module_manager_initialize _txm_module_manager_initialize +#define txm_module_manager_in_place_load _txm_module_manager_in_place_load +#define txm_module_manager_file_load _txm_module_manager_file_load +#define txm_module_manager_memory_load _txm_module_manager_memory_load +#define txm_module_manager_object_pointer_get _txm_module_manager_object_pointer_get +#define txm_module_manager_object_pointer_get_extended _txm_module_manager_object_pointer_get_extended +#define txm_module_manager_object_pool_create _txm_module_manager_object_pool_create +#define txm_module_manager_properties_get _txm_module_manager_properties_get +#define txm_module_manager_start _txm_module_manager_start +#define txm_module_manager_stop _txm_module_manager_stop +#define txm_module_manager_unload _txm_module_manager_unload +#define txm_module_manager_maximum_module_priority_set _txm_module_manager_maximum_module_priority_set +#define txm_module_manager_external_memory_enable _txm_module_manager_external_memory_enable + +/* Define external variables used by module manager functions. */ + +#ifndef TX_MODULE_MANAGER_INIT +extern ULONG _txm_module_manager_properties_supported; +extern ULONG _txm_module_manager_properties_required; +extern TX_BYTE_POOL _txm_module_manager_byte_pool; +extern TX_BYTE_POOL _txm_module_manager_object_pool; +extern UINT _txm_module_manager_object_pool_created; +extern TXM_MODULE_INSTANCE *_txm_module_manager_loaded_list_ptr; +extern ULONG _txm_module_manger_loaded_count; +extern UINT _txm_module_manager_ready; +extern TX_MUTEX _txm_module_manager_mutex; +extern ULONG _txm_module_manager_callback_total_count; +extern ULONG _txm_module_manager_callback_error_count; +#endif + +/* Define internal module manager function prototypes. */ + +UINT _txm_module_manager_application_request(ULONG request, ALIGN_TYPE param_1, ALIGN_TYPE param_2, ALIGN_TYPE param_3); +#ifdef FX_FILEX_PRESENT +UINT _txm_module_manager_file_load(TXM_MODULE_INSTANCE *module_instance, CHAR *module_name, FX_MEDIA *media_ptr, CHAR *file_name); +#endif +UINT _txm_module_manager_initialize(VOID *module_memory_start, ULONG module_memory_size); +UINT _txm_module_manager_in_place_load(TXM_MODULE_INSTANCE *module_instance, CHAR *name, VOID *module_location); +UINT _txm_module_manager_internal_load(TXM_MODULE_INSTANCE *module_instance, CHAR *name, VOID *module_location, + ULONG code_size, VOID *code_allocation_ptr, ULONG code_allocation_size); +ALIGN_TYPE _txm_module_manager_kernel_dispatch(ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2); +UINT _txm_module_manager_object_allocate(VOID **object_ptr_ptr, ULONG object_size, TXM_MODULE_INSTANCE *module_instance); +UINT _txm_module_manager_object_deallocate(VOID *object_ptr); +UINT _txm_module_manager_object_pointer_get(UINT object_type, CHAR *name, VOID **object_ptr); +UINT _txm_module_manager_object_pointer_get_extended(UINT object_type, CHAR *name, UINT name_length, VOID **object_ptr); +UINT _txm_module_manager_object_pool_create(VOID *object_memory, ULONG object_memory_size); +VOID _txm_module_manager_object_type_set(ULONG object_ptr, ULONG object_size, ULONG object_type); +UINT _txm_module_manager_memory_load(TXM_MODULE_INSTANCE *module_instance, CHAR *module_name, VOID *module_location); +UINT _txm_module_manager_properties_get(TXM_MODULE_INSTANCE *module_instance, ULONG *module_properties_ptr); +UINT _txm_module_manager_start(TXM_MODULE_INSTANCE *module_instance); +UINT _txm_module_manager_stop(TXM_MODULE_INSTANCE *module_instance); +UINT _txm_module_manager_thread_create(TX_THREAD *thread_ptr, CHAR *name, VOID (*shell_function)(TX_THREAD *, TXM_MODULE_INSTANCE *), + VOID (*entry_function)(ULONG), ULONG entry_input, + VOID *stack_start, ULONG stack_size, UINT priority, UINT preempt_threshold, + ULONG time_slice, UINT auto_start, UINT thread_control_block_size, TXM_MODULE_INSTANCE *module_instance); +UINT _txm_module_manager_thread_reset(TX_THREAD *thread_ptr); +VOID _txm_module_manager_name_build(CHAR *module_name, CHAR *thread_name, CHAR *combined_name); +VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*shell_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)); +UINT _txm_module_manager_unload(TXM_MODULE_INSTANCE *module_instance); +ALIGN_TYPE _txm_module_manager_user_mode_entry(ULONG kernel_request, ALIGN_TYPE param_1, ALIGN_TYPE param_2, ALIGN_TYPE param_3); +UINT _txm_module_manager_maximum_module_priority_set(TXM_MODULE_INSTANCE *module_instance, UINT priority); +UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, VOID *start_address, ULONG length, UINT attributes); + +#ifdef TXM_MODULE_ENABLE_NETX +ULONG _txm_module_manager_netx_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param_3); +UINT _txm_module_manager_netx_object_pointer_get(UINT object_type, CHAR *name, UINT name_length, VOID **object_ptr); +#endif + +#ifdef TXM_MODULE_ENABLE_NETXDUO +ALIGN_TYPE _txm_module_manager_netxduo_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_1, ALIGN_TYPE param_2, ALIGN_TYPE param_3); +UINT _txm_module_manager_netxduo_object_pointer_get(UINT object_type, CHAR *name, UINT name_length, VOID **object_ptr); +#endif + +#ifdef TXM_MODULE_ENABLE_FILEX +ALIGN_TYPE _txm_module_manager_filex_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2); +UINT _txm_module_manager_filex_object_pointer_get(UINT object_type, CHAR *name, UINT name_length, VOID **object_ptr); +#endif + +#ifdef TXM_MODULE_ENABLE_GUIX +ULONG _txm_module_manager_guix_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param_3); +UINT _txm_module_manager_guix_object_pointer_get(UINT object_type, CHAR *name, UINT name_length, VOID **object_ptr); +#endif + +#ifdef TXM_MODULE_ENABLE_USBX +ULONG _txm_module_manager_usbx_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param_3); +UINT _txm_module_manager_usbx_object_pointer_get(UINT object_type, CHAR *name, UINT name_length, VOID **object_ptr); +#endif + +/* Define the callback deferred processing routines necessary for executing callbacks in the module code. */ + +VOID _txm_module_manager_callback_request(TX_QUEUE *module_callback_queue, TXM_MODULE_CALLBACK_MESSAGE *callback_request); +VOID _txm_module_manager_event_flags_notify_trampoline(TX_EVENT_FLAGS_GROUP *group_ptr); +VOID _txm_module_manager_queue_notify_trampoline(TX_QUEUE *queue_ptr); +VOID _txm_module_manager_semaphore_notify_trampoline(TX_SEMAPHORE *semaphore_ptr); +VOID _txm_module_manager_thread_notify_trampoline(TX_THREAD *thread_ptr, UINT type); +VOID _txm_module_manager_timer_notify_trampoline(ULONG id); + + +/* Define port specific module manager prototypes. */ + +TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES + +#endif + + +/* Determine if a C++ compiler is being used. If so, complete the standard + C conditional started above. */ +#ifdef __cplusplus + } +#endif + +#endif diff --git a/common_modules/inc/txm_module_user.h b/common_modules/inc/txm_module_user.h new file mode 100644 index 00000000..b6cf1788 --- /dev/null +++ b/common_modules/inc/txm_module_user.h @@ -0,0 +1,60 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** User Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* txm_module_user.h PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains user defines for configuring the Module Manager */ +/* in specific ways. This file will have an effect only if the Module */ +/* Manager library is built with TXM_MODULE_INCLUDE_USER_DEFINE_FILE */ +/* defined. Note that all the defines in this file may also be made on */ +/* the command line when building Modules library and application */ +/* objects. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TXM_MODULE_USER_H +#define TXM_MODULE_USER_H + +/* Defines the kernel stack size for a module thread. The default is 512, which is + sufficient for applications only using ThreadX, however, if other libraries are + used i.e. FileX, NetX, etc., then this value will most likely need to be increased. */ + +/* #define TXM_MODULE_KERNEL_STACK_SIZE 2048 */ + +#endif diff --git a/common_modules/module_lib/src/txm_block_allocate.c b/common_modules/module_lib/src/txm_block_allocate.c new file mode 100644 index 00000000..9c1e1054 --- /dev/null +++ b/common_modules/module_lib/src/txm_block_allocate.c @@ -0,0 +1,80 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_block_allocate PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the allocate block memory */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* pool_ptr Pointer to pool control block */ +/* block_ptr Pointer to place allocated block */ +/* pointer */ +/* wait_option Suspension option */ +/* */ +/* OUTPUT */ +/* */ +/* TX_POOL_ERROR Invalid pool pointer */ +/* TX_PTR_ERROR Invalid destination pointer */ +/* TX_WAIT_ERROR Invalid wait option */ +/* status Actual Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_block_allocate(TX_BLOCK_POOL *pool_ptr, VOID **block_ptr, ULONG wait_option) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_BLOCK_ALLOCATE_CALL, (ALIGN_TYPE) pool_ptr, (ALIGN_TYPE) block_ptr, (ALIGN_TYPE) wait_option); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_block_pool_create.c b/common_modules/module_lib/src/txm_block_pool_create.c new file mode 100644 index 00000000..897a863e --- /dev/null +++ b/common_modules/module_lib/src/txm_block_pool_create.c @@ -0,0 +1,89 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_block_pool_create PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the create block memory pool */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* pool_ptr Pointer to pool control block */ +/* name_ptr Pointer to block pool name */ +/* block_size Number of bytes in each block */ +/* pool_start Address of beginning of pool area */ +/* pool_size Number of bytes in the block pool */ +/* pool_control_block_size Size of block pool control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_POOL_ERROR Invalid pool pointer */ +/* TX_PTR_ERROR Invalid starting address */ +/* TX_SIZE_ERROR Invalid pool size */ +/* TX_CALLER_ERROR Invalid caller of pool */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_block_pool_create(TX_BLOCK_POOL *pool_ptr, CHAR *name_ptr, ULONG block_size, VOID *pool_start, ULONG pool_size, UINT pool_control_block_size) +{ + +UINT return_value; +ALIGN_TYPE extra_parameters[4]; + + extra_parameters[0] = (ALIGN_TYPE) block_size; + extra_parameters[1] = (ALIGN_TYPE) pool_start; + extra_parameters[2] = (ALIGN_TYPE) pool_size; + extra_parameters[3] = (ALIGN_TYPE) pool_control_block_size; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_BLOCK_POOL_CREATE_CALL, (ALIGN_TYPE) pool_ptr, (ALIGN_TYPE) name_ptr, (ALIGN_TYPE) extra_parameters); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_block_pool_delete.c b/common_modules/module_lib/src/txm_block_pool_delete.c new file mode 100644 index 00000000..9b0436eb --- /dev/null +++ b/common_modules/module_lib/src/txm_block_pool_delete.c @@ -0,0 +1,76 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_block_pool_delete PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the delete block pool memory */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* pool_ptr Pointer to pool control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_POOL_ERROR Invalid memory block pool pointer */ +/* TX_CALLER_ERROR Invalid caller of this function */ +/* status Actual delete function status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_block_pool_delete(TX_BLOCK_POOL *pool_ptr) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_BLOCK_POOL_DELETE_CALL, (ALIGN_TYPE) pool_ptr, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_block_pool_info_get.c b/common_modules/module_lib/src/txm_block_pool_info_get.c new file mode 100644 index 00000000..40489186 --- /dev/null +++ b/common_modules/module_lib/src/txm_block_pool_info_get.c @@ -0,0 +1,90 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_block_pool_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the block pool information get */ +/* service. */ +/* */ +/* INPUT */ +/* */ +/* pool_ptr Pointer to block pool control blk */ +/* name Destination for the pool name */ +/* available_blocks Number of free blocks in pool */ +/* total_blocks Total number of blocks in pool */ +/* first_suspended Destination for pointer of first */ +/* thread suspended on block pool */ +/* suspended_count Destination for suspended count */ +/* next_pool Destination for pointer to next */ +/* block pool on the created list */ +/* */ +/* OUTPUT */ +/* */ +/* TX_POOL_ERROR Invalid block pool pointer */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_block_pool_info_get(TX_BLOCK_POOL *pool_ptr, CHAR **name, ULONG *available_blocks, ULONG *total_blocks, TX_THREAD **first_suspended, ULONG *suspended_count, TX_BLOCK_POOL **next_pool) +{ + +UINT return_value; +ALIGN_TYPE extra_parameters[5]; + + extra_parameters[0] = (ALIGN_TYPE) available_blocks; + extra_parameters[1] = (ALIGN_TYPE) total_blocks; + extra_parameters[2] = (ALIGN_TYPE) first_suspended; + extra_parameters[3] = (ALIGN_TYPE) suspended_count; + extra_parameters[4] = (ALIGN_TYPE) next_pool; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_BLOCK_POOL_INFO_GET_CALL, (ALIGN_TYPE) pool_ptr, (ALIGN_TYPE) name, (ALIGN_TYPE) extra_parameters); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_block_pool_performance_info_get.c b/common_modules/module_lib/src/txm_block_pool_performance_info_get.c new file mode 100644 index 00000000..7441e4aa --- /dev/null +++ b/common_modules/module_lib/src/txm_block_pool_performance_info_get.c @@ -0,0 +1,87 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_block_pool_performance_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves performance information from the specified */ +/* block pool. */ +/* */ +/* INPUT */ +/* */ +/* pool_ptr Pointer to block pool control blk */ +/* allocates Destination for the number of */ +/* allocations from this pool */ +/* releases Destination for the number of */ +/* blocks released back to pool */ +/* suspensions Destination for number of */ +/* suspensions on this pool */ +/* timeouts Destination for number of timeouts*/ +/* on this pool */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_block_pool_performance_info_get(TX_BLOCK_POOL *pool_ptr, ULONG *allocates, ULONG *releases, ULONG *suspensions, ULONG *timeouts) +{ + +UINT return_value; +ALIGN_TYPE extra_parameters[3]; + + extra_parameters[0] = (ALIGN_TYPE) releases; + extra_parameters[1] = (ALIGN_TYPE) suspensions; + extra_parameters[2] = (ALIGN_TYPE) timeouts; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_BLOCK_POOL_PERFORMANCE_INFO_GET_CALL, (ALIGN_TYPE) pool_ptr, (ALIGN_TYPE) allocates, (ALIGN_TYPE) extra_parameters); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_block_pool_performance_system_info_get.c b/common_modules/module_lib/src/txm_block_pool_performance_system_info_get.c new file mode 100644 index 00000000..d37da4e8 --- /dev/null +++ b/common_modules/module_lib/src/txm_block_pool_performance_system_info_get.c @@ -0,0 +1,84 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_block_pool_performance_system_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves block pool performance information. */ +/* */ +/* INPUT */ +/* */ +/* allocates Destination for the total number */ +/* of block allocations */ +/* releases Destination for the total number */ +/* of blocks released */ +/* suspensions Destination for the total number */ +/* of suspensions */ +/* timeouts Destination for total number of */ +/* timeouts */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_block_pool_performance_system_info_get(ULONG *allocates, ULONG *releases, ULONG *suspensions, ULONG *timeouts) +{ + +UINT return_value; +ALIGN_TYPE extra_parameters[2]; + + extra_parameters[0] = (ALIGN_TYPE) suspensions; + extra_parameters[1] = (ALIGN_TYPE) timeouts; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_BLOCK_POOL_PERFORMANCE_SYSTEM_INFO_GET_CALL, (ALIGN_TYPE) allocates, (ALIGN_TYPE) releases, (ALIGN_TYPE) extra_parameters); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_block_pool_prioritize.c b/common_modules/module_lib/src/txm_block_pool_prioritize.c new file mode 100644 index 00000000..05c2bbd8 --- /dev/null +++ b/common_modules/module_lib/src/txm_block_pool_prioritize.c @@ -0,0 +1,73 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_block_pool_prioritize PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the block pool prioritize call. */ +/* */ +/* INPUT */ +/* */ +/* pool_ptr Pointer to pool control block */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_block_pool_prioritize(TX_BLOCK_POOL *pool_ptr) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_BLOCK_POOL_PRIORITIZE_CALL, (ALIGN_TYPE) pool_ptr, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_block_release.c b/common_modules/module_lib/src/txm_block_release.c new file mode 100644 index 00000000..2b644943 --- /dev/null +++ b/common_modules/module_lib/src/txm_block_release.c @@ -0,0 +1,74 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_block_release PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the block release function call. */ +/* */ +/* INPUT */ +/* */ +/* block_ptr Pointer to memory block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_PTR_ERROR Invalid memory block pointer */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_block_release(VOID *block_ptr) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_BLOCK_RELEASE_CALL, (ALIGN_TYPE) block_ptr, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_byte_allocate.c b/common_modules/module_lib/src/txm_byte_allocate.c new file mode 100644 index 00000000..bf9da24d --- /dev/null +++ b/common_modules/module_lib/src/txm_byte_allocate.c @@ -0,0 +1,86 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_byte_allocate PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in allocate bytes function call. */ +/* */ +/* INPUT */ +/* */ +/* pool_ptr Pointer to pool control block */ +/* memory_ptr Pointer to place allocated bytes */ +/* pointer */ +/* memory_size Number of bytes to allocate */ +/* wait_option Suspension option */ +/* */ +/* OUTPUT */ +/* */ +/* TX_POOL_ERROR Invalid memory pool pointer */ +/* TX_PTR_ERROR Invalid destination pointer */ +/* TX_WAIT_ERROR Invalid wait option */ +/* TX_CALLER_ERROR Invalid caller of this function */ +/* TX_SIZE_ERROR Invalid size of memory request */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_byte_allocate(TX_BYTE_POOL *pool_ptr, VOID **memory_ptr, ULONG memory_size, ULONG wait_option) +{ + +UINT return_value; +ALIGN_TYPE extra_parameters[2]; + + extra_parameters[0] = (ALIGN_TYPE) memory_size; + extra_parameters[1] = (ALIGN_TYPE) wait_option; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_BYTE_ALLOCATE_CALL, (ALIGN_TYPE) pool_ptr, (ALIGN_TYPE) memory_ptr, (ALIGN_TYPE) extra_parameters); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_byte_pool_create.c b/common_modules/module_lib/src/txm_byte_pool_create.c new file mode 100644 index 00000000..c2b02c0b --- /dev/null +++ b/common_modules/module_lib/src/txm_byte_pool_create.c @@ -0,0 +1,87 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_byte_pool_create PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the create byte pool memory */ +/* function. */ +/* */ +/* INPUT */ +/* */ +/* pool_ptr Pointer to pool control block */ +/* name_ptr Pointer to byte pool name */ +/* pool_start Address of beginning of pool area */ +/* pool_size Number of bytes in the byte pool */ +/* pool_control_block_size Size of byte pool control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_POOL_ERROR Invalid byte pool pointer */ +/* TX_PTR_ERROR Invalid pool starting address */ +/* TX_SIZE_ERROR Invalid pool size */ +/* TX_CALLER_ERROR Invalid caller of this function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_byte_pool_create(TX_BYTE_POOL *pool_ptr, CHAR *name_ptr, VOID *pool_start, ULONG pool_size, UINT pool_control_block_size) +{ + +UINT return_value; +ALIGN_TYPE extra_parameters[3]; + + extra_parameters[0] = (ALIGN_TYPE) pool_start; + extra_parameters[1] = (ALIGN_TYPE) pool_size; + extra_parameters[2] = (ALIGN_TYPE) pool_control_block_size; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_BYTE_POOL_CREATE_CALL, (ALIGN_TYPE) pool_ptr, (ALIGN_TYPE) name_ptr, (ALIGN_TYPE) extra_parameters); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_byte_pool_delete.c b/common_modules/module_lib/src/txm_byte_pool_delete.c new file mode 100644 index 00000000..5616cfb4 --- /dev/null +++ b/common_modules/module_lib/src/txm_byte_pool_delete.c @@ -0,0 +1,76 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_byte_pool_delete PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the delete byte pool function */ +/* call. */ +/* */ +/* INPUT */ +/* */ +/* pool_ptr Pointer to pool control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_POOL_ERROR Invalid pool pointer */ +/* TX_CALLER_ERROR Invalid caller of this function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_byte_pool_delete(TX_BYTE_POOL *pool_ptr) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_BYTE_POOL_DELETE_CALL, (ALIGN_TYPE) pool_ptr, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_byte_pool_info_get.c b/common_modules/module_lib/src/txm_byte_pool_info_get.c new file mode 100644 index 00000000..2ff97682 --- /dev/null +++ b/common_modules/module_lib/src/txm_byte_pool_info_get.c @@ -0,0 +1,90 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_byte_pool_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the byte pool information get */ +/* service. */ +/* */ +/* INPUT */ +/* */ +/* pool_ptr Pointer to byte pool control block*/ +/* name Destination for the pool name */ +/* available_bytes Number of free bytes in byte pool */ +/* fragments Number of fragments in byte pool */ +/* first_suspended Destination for pointer of first */ +/* thread suspended on byte pool */ +/* suspended_count Destination for suspended count */ +/* next_pool Destination for pointer to next */ +/* byte pool on the created list */ +/* */ +/* OUTPUT */ +/* */ +/* TX_POOL_ERROR Invalid byte pool pointer */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_byte_pool_info_get(TX_BYTE_POOL *pool_ptr, CHAR **name, ULONG *available_bytes, ULONG *fragments, TX_THREAD **first_suspended, ULONG *suspended_count, TX_BYTE_POOL **next_pool) +{ + +UINT return_value; +ALIGN_TYPE extra_parameters[5]; + + extra_parameters[0] = (ALIGN_TYPE) available_bytes; + extra_parameters[1] = (ALIGN_TYPE) fragments; + extra_parameters[2] = (ALIGN_TYPE) first_suspended; + extra_parameters[3] = (ALIGN_TYPE) suspended_count; + extra_parameters[4] = (ALIGN_TYPE) next_pool; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_BYTE_POOL_INFO_GET_CALL, (ALIGN_TYPE) pool_ptr, (ALIGN_TYPE) name, (ALIGN_TYPE) extra_parameters); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_byte_pool_performance_info_get.c b/common_modules/module_lib/src/txm_byte_pool_performance_info_get.c new file mode 100644 index 00000000..2ac466b7 --- /dev/null +++ b/common_modules/module_lib/src/txm_byte_pool_performance_info_get.c @@ -0,0 +1,98 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_byte_pool_performance_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves performance information from the specified */ +/* byte pool. */ +/* */ +/* INPUT */ +/* */ +/* pool_ptr Pointer to byte pool control block*/ +/* allocates Destination for number of */ +/* allocates on this pool */ +/* releases Destination for number of */ +/* releases on this pool */ +/* fragments_searched Destination for number of */ +/* fragments searched during */ +/* allocation */ +/* merges Destination for number of adjacent*/ +/* free fragments merged */ +/* splits Destination for number of */ +/* fragments split during */ +/* allocation */ +/* suspensions Destination for number of */ +/* suspensions on this pool */ +/* timeouts Destination for number of timeouts*/ +/* on this byte pool */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_byte_pool_performance_info_get(TX_BYTE_POOL *pool_ptr, ULONG *allocates, ULONG *releases, ULONG *fragments_searched, ULONG *merges, ULONG *splits, ULONG *suspensions, ULONG *timeouts) +{ + +UINT return_value; +ALIGN_TYPE extra_parameters[6]; + + extra_parameters[0] = (ALIGN_TYPE) releases; + extra_parameters[1] = (ALIGN_TYPE) fragments_searched; + extra_parameters[2] = (ALIGN_TYPE) merges; + extra_parameters[3] = (ALIGN_TYPE) splits; + extra_parameters[4] = (ALIGN_TYPE) suspensions; + extra_parameters[5] = (ALIGN_TYPE) timeouts; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_BYTE_POOL_PERFORMANCE_INFO_GET_CALL, (ALIGN_TYPE) pool_ptr, (ALIGN_TYPE) allocates, (ALIGN_TYPE) extra_parameters); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_byte_pool_performance_system_info_get.c b/common_modules/module_lib/src/txm_byte_pool_performance_system_info_get.c new file mode 100644 index 00000000..3b3b8b59 --- /dev/null +++ b/common_modules/module_lib/src/txm_byte_pool_performance_system_info_get.c @@ -0,0 +1,95 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_byte_pool_performance_system_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves byte pool performance information. */ +/* */ +/* INPUT */ +/* */ +/* allocates Destination for total number of */ +/* allocates */ +/* releases Destination for total number of */ +/* releases */ +/* fragments_searched Destination for total number of */ +/* fragments searched during */ +/* allocation */ +/* merges Destination for total number of */ +/* adjacent free fragments merged */ +/* splits Destination for total number of */ +/* fragments split during */ +/* allocation */ +/* suspensions Destination for total number of */ +/* suspensions */ +/* timeouts Destination for total number of */ +/* timeouts */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_byte_pool_performance_system_info_get(ULONG *allocates, ULONG *releases, ULONG *fragments_searched, ULONG *merges, ULONG *splits, ULONG *suspensions, ULONG *timeouts) +{ + +UINT return_value; +ALIGN_TYPE extra_parameters[5]; + + extra_parameters[0] = (ALIGN_TYPE) fragments_searched; + extra_parameters[1] = (ALIGN_TYPE) merges; + extra_parameters[2] = (ALIGN_TYPE) splits; + extra_parameters[3] = (ALIGN_TYPE) suspensions; + extra_parameters[4] = (ALIGN_TYPE) timeouts; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_BYTE_POOL_PERFORMANCE_SYSTEM_INFO_GET_CALL, (ALIGN_TYPE) allocates, (ALIGN_TYPE) releases, (ALIGN_TYPE) extra_parameters); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_byte_pool_prioritize.c b/common_modules/module_lib/src/txm_byte_pool_prioritize.c new file mode 100644 index 00000000..94dfa607 --- /dev/null +++ b/common_modules/module_lib/src/txm_byte_pool_prioritize.c @@ -0,0 +1,73 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_byte_pool_prioritize PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the byte pool prioritize call. */ +/* */ +/* INPUT */ +/* */ +/* pool_ptr Pointer to pool control block */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_byte_pool_prioritize(TX_BYTE_POOL *pool_ptr) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_BYTE_POOL_PRIORITIZE_CALL, (ALIGN_TYPE) pool_ptr, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_byte_release.c b/common_modules/module_lib/src/txm_byte_release.c new file mode 100644 index 00000000..31b32848 --- /dev/null +++ b/common_modules/module_lib/src/txm_byte_release.c @@ -0,0 +1,75 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_byte_release PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the release byte function call. */ +/* */ +/* INPUT */ +/* */ +/* memory_ptr Pointer to allocated memory */ +/* */ +/* OUTPUT */ +/* */ +/* TX_PTR_ERROR Invalid memory pointer */ +/* TX_CALLER_ERROR Invalid caller of this function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_byte_release(VOID *memory_ptr) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_BYTE_RELEASE_CALL, (ALIGN_TYPE) memory_ptr, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_event_flags_create.c b/common_modules/module_lib/src/txm_event_flags_create.c new file mode 100644 index 00000000..a0ae4eb6 --- /dev/null +++ b/common_modules/module_lib/src/txm_event_flags_create.c @@ -0,0 +1,79 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_event_flags_create PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the event flag creation function */ +/* call. */ +/* */ +/* INPUT */ +/* */ +/* group_ptr Pointer to event flags group */ +/* control block */ +/* name_ptr Pointer to event flags name */ +/* event_control_block_size Size of event flags control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_GROUP_ERROR Invalid event flag group pointer */ +/* TX_CALLER_ERROR Invalid calling function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_event_flags_create(TX_EVENT_FLAGS_GROUP *group_ptr, CHAR *name_ptr, UINT event_control_block_size) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_EVENT_FLAGS_CREATE_CALL, (ALIGN_TYPE) group_ptr, (ALIGN_TYPE) name_ptr, (ALIGN_TYPE) event_control_block_size); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_event_flags_delete.c b/common_modules/module_lib/src/txm_event_flags_delete.c new file mode 100644 index 00000000..fccb74b0 --- /dev/null +++ b/common_modules/module_lib/src/txm_event_flags_delete.c @@ -0,0 +1,76 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_event_flags_delete PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the delete event flags group */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* group_ptr Pointer to group control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_GROUP_ERROR Invalid event flag group pointer */ +/* TX_CALLER_ERROR Invalid caller of this function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_event_flags_delete(TX_EVENT_FLAGS_GROUP *group_ptr) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_EVENT_FLAGS_DELETE_CALL, (ALIGN_TYPE) group_ptr, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_event_flags_get.c b/common_modules/module_lib/src/txm_event_flags_get.c new file mode 100644 index 00000000..792826d5 --- /dev/null +++ b/common_modules/module_lib/src/txm_event_flags_get.c @@ -0,0 +1,89 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_event_flags_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the event flags get function */ +/* call. */ +/* */ +/* INPUT */ +/* */ +/* group_ptr Pointer to group control block */ +/* requested_event_flags Event flags requested */ +/* get_option Specifies and/or and clear options*/ +/* actual_flags_ptr Pointer to place the actual flags */ +/* the service retrieved */ +/* wait_option Suspension option */ +/* */ +/* OUTPUT */ +/* */ +/* TX_GROUP_ERROR Invalid event flags group pointer */ +/* TX_PTR_ERROR Invalid actual flags pointer */ +/* TX_WAIT_ERROR Invalid wait option */ +/* TX_OPTION_ERROR Invalid get option */ +/* TX_CALLER_ERROR Invalid caller of this function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_event_flags_get(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG requested_flags, UINT get_option, ULONG *actual_flags_ptr, ULONG wait_option) +{ + +UINT return_value; +ALIGN_TYPE extra_parameters[3]; + + extra_parameters[0] = (ALIGN_TYPE) get_option; + extra_parameters[1] = (ALIGN_TYPE) actual_flags_ptr; + extra_parameters[2] = (ALIGN_TYPE) wait_option; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_EVENT_FLAGS_GET_CALL, (ALIGN_TYPE) group_ptr, (ALIGN_TYPE) requested_flags, (ALIGN_TYPE) extra_parameters); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_event_flags_info_get.c b/common_modules/module_lib/src/txm_event_flags_info_get.c new file mode 100644 index 00000000..5242503e --- /dev/null +++ b/common_modules/module_lib/src/txm_event_flags_info_get.c @@ -0,0 +1,90 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_event_flags_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the event flag information get */ +/* service. */ +/* */ +/* INPUT */ +/* */ +/* group_ptr Pointer to event flag group */ +/* name Destination for the event flags */ +/* group name */ +/* current_flags Current event flags */ +/* first_suspended Destination for pointer of first */ +/* thread suspended on event flags */ +/* suspended_count Destination for suspended count */ +/* next_group Destination for pointer to next */ +/* event flag group on the created */ +/* list */ +/* */ +/* OUTPUT */ +/* */ +/* TX_GROUP_ERROR Invalid event flag group pointer */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_event_flags_info_get(TX_EVENT_FLAGS_GROUP *group_ptr, CHAR **name, ULONG *current_flags, TX_THREAD **first_suspended, ULONG *suspended_count, TX_EVENT_FLAGS_GROUP **next_group) +{ + +UINT return_value; +ALIGN_TYPE extra_parameters[4]; + + extra_parameters[0] = (ALIGN_TYPE) current_flags; + extra_parameters[1] = (ALIGN_TYPE) first_suspended; + extra_parameters[2] = (ALIGN_TYPE) suspended_count; + extra_parameters[3] = (ALIGN_TYPE) next_group; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_EVENT_FLAGS_INFO_GET_CALL, (ALIGN_TYPE) group_ptr, (ALIGN_TYPE) name, (ALIGN_TYPE) extra_parameters); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_event_flags_performance_info_get.c b/common_modules/module_lib/src/txm_event_flags_performance_info_get.c new file mode 100644 index 00000000..dfc6b0fa --- /dev/null +++ b/common_modules/module_lib/src/txm_event_flags_performance_info_get.c @@ -0,0 +1,88 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_event_flags_performance_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves performance information from the specified */ +/* event flag group. */ +/* */ +/* INPUT */ +/* */ +/* group_ptr Pointer to event flag group */ +/* sets Destination for the number of */ +/* event flag sets on this group */ +/* gets Destination for the number of */ +/* event flag gets on this group */ +/* suspensions Destination for the number of */ +/* event flag suspensions on this */ +/* group */ +/* timeouts Destination for number of timeouts*/ +/* on this event flag group */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_event_flags_performance_info_get(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG *sets, ULONG *gets, ULONG *suspensions, ULONG *timeouts) +{ + +UINT return_value; +ALIGN_TYPE extra_parameters[3]; + + extra_parameters[0] = (ALIGN_TYPE) gets; + extra_parameters[1] = (ALIGN_TYPE) suspensions; + extra_parameters[2] = (ALIGN_TYPE) timeouts; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_EVENT_FLAGS_PERFORMANCE_INFO_GET_CALL, (ALIGN_TYPE) group_ptr, (ALIGN_TYPE) sets, (ALIGN_TYPE) extra_parameters); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_event_flags_performance_system_info_get.c b/common_modules/module_lib/src/txm_event_flags_performance_system_info_get.c new file mode 100644 index 00000000..840f2d00 --- /dev/null +++ b/common_modules/module_lib/src/txm_event_flags_performance_system_info_get.c @@ -0,0 +1,84 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_event_flags_performance_system_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves system event flag performance information. */ +/* */ +/* INPUT */ +/* */ +/* sets Destination for total number of */ +/* event flag sets */ +/* gets Destination for total number of */ +/* event flag gets */ +/* suspensions Destination for total number of */ +/* event flag suspensions */ +/* timeouts Destination for total number of */ +/* timeouts */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_event_flags_performance_system_info_get(ULONG *sets, ULONG *gets, ULONG *suspensions, ULONG *timeouts) +{ + +UINT return_value; +ALIGN_TYPE extra_parameters[2]; + + extra_parameters[0] = (ALIGN_TYPE) suspensions; + extra_parameters[1] = (ALIGN_TYPE) timeouts; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_EVENT_FLAGS_PERFORMANCE_SYSTEM_INFO_GET_CALL, (ALIGN_TYPE) sets, (ALIGN_TYPE) gets, (ALIGN_TYPE) extra_parameters); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_event_flags_set.c b/common_modules/module_lib/src/txm_event_flags_set.c new file mode 100644 index 00000000..182e4eed --- /dev/null +++ b/common_modules/module_lib/src/txm_event_flags_set.c @@ -0,0 +1,79 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_event_flags_set PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the set event flags function */ +/* call. */ +/* */ +/* INPUT */ +/* */ +/* group_ptr Pointer to group control block */ +/* flags_to_set Event flags to set */ +/* set_option Specified either AND or OR */ +/* operation on the event flags */ +/* */ +/* OUTPUT */ +/* */ +/* TX_GROUP_ERROR Invalid event flags group pointer */ +/* TX_OPTION_ERROR Invalid set option */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_event_flags_set(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG flags_to_set, UINT set_option) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_EVENT_FLAGS_SET_CALL, (ALIGN_TYPE) group_ptr, (ALIGN_TYPE) flags_to_set, (ALIGN_TYPE) set_option); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_event_flags_set_notify.c b/common_modules/module_lib/src/txm_event_flags_set_notify.c new file mode 100644 index 00000000..99816859 --- /dev/null +++ b/common_modules/module_lib/src/txm_event_flags_set_notify.c @@ -0,0 +1,76 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_event_flags_set_notify PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the event flags set notify */ +/* callback function call. */ +/* */ +/* INPUT */ +/* */ +/* group_ptr Pointer to group control block*/ +/* group_put_notify Application callback function */ +/* (TX_NULL disables notify) */ +/* */ +/* OUTPUT */ +/* */ +/* status Service return status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_event_flags_set_notify(TX_EVENT_FLAGS_GROUP *group_ptr, VOID (*events_set_notify)(TX_EVENT_FLAGS_GROUP *)) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_EVENT_FLAGS_SET_NOTIFY_CALL, (ALIGN_TYPE) group_ptr, (ALIGN_TYPE) events_set_notify, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_module_application_request.c b/common_modules/module_lib/src/txm_module_application_request.c new file mode 100644 index 00000000..8e397c89 --- /dev/null +++ b/common_modules/module_lib/src/txm_module_application_request.c @@ -0,0 +1,78 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* txm_module_application_request PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sends an application-specific request to the resident */ +/* code. */ +/* */ +/* INPUT */ +/* */ +/* request Request ID (application defined) */ +/* param_1 First parameter */ +/* param_2 Second parameter */ +/* param_3 Third parameter */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT txm_module_application_request(ULONG request, ALIGN_TYPE param_1, ALIGN_TYPE param_2, ALIGN_TYPE param_3) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT)(_txm_module_kernel_call_dispatcher)(TXM_APPLICATION_REQUEST_ID_BASE+request, param_1, param_2, param_3); + + /* Return value to the caller. */ + return(return_value); +} + diff --git a/common_modules/module_lib/src/txm_module_callback_request_thread_entry.c b/common_modules/module_lib/src/txm_module_callback_request_thread_entry.c new file mode 100644 index 00000000..e8ba684d --- /dev/null +++ b/common_modules/module_lib/src/txm_module_callback_request_thread_entry.c @@ -0,0 +1,244 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#ifndef TXM_MODULE +#define TXM_MODULE +#endif + +#ifndef TX_SOURCE_CODE +#define TX_SOURCE_CODE +#endif + + +/* Include necessary system files. */ + +#include "txm_module.h" +#include "tx_queue.h" + + +/* Define the global module entry pointer from the start thread of the module. + This structure contains the pointer to the request queue as well as the + pointer to the callback response queue. */ + +extern TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_callback_request_thread_entry PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes all module callback requests, transferred */ +/* by the resident code via the callback queue. When the callback is */ +/* complete, the response is sent back to the resident code to */ +/* acknowledge it. */ +/* */ +/* INPUT */ +/* */ +/* id Module thread ID */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* tx_queue_receive Receive callback request */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_callback_request_thread_entry(ULONG id) +{ + +TX_QUEUE *request_queue; +TXM_MODULE_CALLBACK_MESSAGE callback_message; +ULONG activation_count; +VOID (*timer_callback)(ULONG); +VOID (*events_set_notify)(TX_EVENT_FLAGS_GROUP *); +VOID (*semaphore_put_notify)(TX_SEMAPHORE *); +VOID (*queue_send_notify)(TX_QUEUE *); +VOID (*thread_entry_exit_notify)(TX_THREAD *, UINT); +UINT status; + + + /* Pickup pointer to the request queue. */ + request_queue = _txm_module_entry_info -> txm_module_thread_entry_info_callback_request_queue; + + /* Loop to process callback messages from the module manager. */ + while(1) + { + + /* Wait for the callback request for the module. */ + status = _txe_queue_receive(request_queue, (VOID *) &callback_message, TX_WAIT_FOREVER); + + /* Check to see if a request was received. */ + if (status != TX_SUCCESS) + { + + /* This should not happen - get out of the loop. */ + break; + } + + /* Pickup the activation count in the message. */ + activation_count = callback_message.txm_module_callback_message_activation_count; + + /* Loop to call the callback function the correct number of times. */ + while (activation_count) + { + + /* Decrement the activation count. */ + activation_count--; + + /* Now dispatch the callback function. */ + switch (callback_message.txm_module_callback_message_type) + { + + case TXM_TIMER_CALLBACK: + + /* Setup timer callback pointer. */ + timer_callback = (void (*)(ULONG)) callback_message.txm_module_callback_message_application_function; + + /* Call application's timer callback. */ + (timer_callback)((ULONG) callback_message.txm_module_callback_message_param_1); + + break; + + case TXM_EVENTS_SET_CALLBACK: + + /* Setup events set callback pointer. */ + events_set_notify = (void (*)(TX_EVENT_FLAGS_GROUP *)) callback_message.txm_module_callback_message_application_function; + + /* Call events set notify callback. */ + (events_set_notify)((TX_EVENT_FLAGS_GROUP *) callback_message.txm_module_callback_message_param_1); + + break; + + case TXM_QUEUE_SEND_CALLBACK: + + /* Setup queue send callback pointer. */ + queue_send_notify = (void (*)(TX_QUEUE *)) callback_message.txm_module_callback_message_application_function; + + /* Call queue send notify callback. */ + (queue_send_notify)((TX_QUEUE *) callback_message.txm_module_callback_message_param_1); + + break; + + case TXM_SEMAPHORE_PUT_CALLBACK: + + /* Setup semaphore put callback pointer. */ + semaphore_put_notify = (void (*)(TX_SEMAPHORE *)) callback_message.txm_module_callback_message_application_function; + + /* Call semaphore put notify callback. */ + (semaphore_put_notify)((TX_SEMAPHORE *) callback_message.txm_module_callback_message_param_1); + + break; + + case TXM_THREAD_ENTRY_EXIT_CALLBACK: + + /* Setup thread entry/exit callback pointer. */ + thread_entry_exit_notify = (void (*)(TX_THREAD *, UINT)) callback_message.txm_module_callback_message_application_function; + + /* Call thread entry/exit notify callback. */ + (thread_entry_exit_notify)((TX_THREAD *) callback_message.txm_module_callback_message_param_1, (UINT) callback_message.txm_module_callback_message_param_2); + + break; + + default: + +#ifdef TXM_MODULE_ENABLE_NETX + + /* Determine if there is a NetX callback. */ + if ((callback_message.txm_module_callback_message_type >= TXM_NETX_CALLBACKS_START) && (callback_message.txm_module_callback_message_type < TXM_NETX_CALLBACKS_END)) + { + + /* Call the NetX module callback function. */ + _txm_module_netx_callback_request(&callback_message); + } +#endif + +#ifdef TXM_MODULE_ENABLE_NETXDUO + + /* Determine if there is a NetX Duo callback. */ + if ((callback_message.txm_module_callback_message_type >= TXM_NETXDUO_CALLBACKS_START) && (callback_message.txm_module_callback_message_type < TXM_NETXDUO_CALLBACKS_END)) + { + + /* Call the NetX Duo module callback function. */ + _txm_module_netxduo_callback_request(&callback_message); + } +#endif + +#ifdef TXM_MODULE_ENABLE_FILEX + + /* Determine if there is a FileX callback. */ + if ((callback_message.txm_module_callback_message_type >= TXM_FILEX_CALLBACKS_START) && (callback_message.txm_module_callback_message_type < TXM_FILEX_CALLBACKS_END)) + { + + /* Call the FileX module callback function. */ + _txm_module_filex_callback_request(&callback_message); + } +#endif + +#ifdef TXM_MODULE_ENABLE_GUIX + + /* Determine if there is a GUIX callback. */ + if ((callback_message.txm_module_callback_message_type >= TXM_GUIX_CALLBACKS_START) && (callback_message.txm_module_callback_message_type < TXM_GUIX_CALLBACKS_END)) + { + + /* Call the GUIX module callback function. */ + _txm_module_guix_callback_request(&callback_message); + } +#endif + +#ifdef TXM_MODULE_ENABLE_USBX + + /* Determine if there is a USBX callback. */ + if ((callback_message.txm_module_callback_message_type >= TXM_USBX_CALLBACKS_START) && (callback_message.txm_module_callback_message_type < TXM_USBX_CALLBACKS_END)) + { + + /* Call the USBX callback function. */ + _txm_module_usbx_callback_request(&callback_message); + } +#endif + + break; + } + } + } +} + + diff --git a/common_modules/module_lib/src/txm_module_object_allocate.c b/common_modules/module_lib/src/txm_module_object_allocate.c new file mode 100644 index 00000000..3ae4c91f --- /dev/null +++ b/common_modules/module_lib/src/txm_module_object_allocate.c @@ -0,0 +1,79 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_object_allocate PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function allocates memory for an object from the memory pool */ +/* supplied to txm_module_manager_initialize. */ +/* */ +/* INPUT */ +/* */ +/* object_ptr Destination of object pointer on */ +/* successful allocation */ +/* object_size Size in bytes of the object to be */ +/* allocated */ +/* module_instance The module instance that the */ +/* object belongs to */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_object_allocate(VOID **object_ptr, ULONG object_size) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_MODULE_OBJECT_ALLOCATE_CALL, (ALIGN_TYPE) object_ptr, (ALIGN_TYPE) object_size, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_module_object_deallocate.c b/common_modules/module_lib/src/txm_module_object_deallocate.c new file mode 100644 index 00000000..e3e39bb8 --- /dev/null +++ b/common_modules/module_lib/src/txm_module_object_deallocate.c @@ -0,0 +1,73 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_object_deallocate PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function deallocates a previously allocated object. */ +/* */ +/* INPUT */ +/* */ +/* object_ptr Object pointer to deallocate */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_object_deallocate(VOID *object_ptr) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_MODULE_OBJECT_DEALLOCATE_CALL, (ALIGN_TYPE) object_ptr, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_module_object_pointer_get.c b/common_modules/module_lib/src/txm_module_object_pointer_get.c new file mode 100644 index 00000000..81e5fd9b --- /dev/null +++ b/common_modules/module_lib/src/txm_module_object_pointer_get.c @@ -0,0 +1,89 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_object_pointer_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is deprecated and calls the secure version of this */ +/* function (_txm_module_manager_object_pointer_get_extended) with the */ +/* maximum possible name length since none was passed. */ +/* */ +/* INPUT */ +/* */ +/* object_type Type of object, as follows: */ +/* */ +/* TXM_BLOCK_POOL_OBJECT */ +/* TXM_BYTE_POOL_OBJECT */ +/* TXM_EVENT_FLAGS_OBJECT */ +/* TXM_MUTEX_OBJECT */ +/* TXM_QUEUE_OBJECT */ +/* TXM_SEMAPHORE_OBJECT */ +/* TXM_THREAD_OBJECT */ +/* TXM_TIMER_OBJECT */ +/* name Name to search for */ +/* object_ptr Pointer to the object */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SUCCESS Successful completion */ +/* TX_PTR_ERROR Invalid name or object ptr */ +/* TX_OPTION_ERROR Invalid option type */ +/* TX_NO_INSTANCE Object not found */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_object_pointer_get(UINT object_type, CHAR *name, VOID **object_ptr) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_MODULE_OBJECT_POINTER_GET_CALL, (ALIGN_TYPE) object_type, (ALIGN_TYPE) name, (ALIGN_TYPE) object_ptr); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_module_object_pointer_get_extended.c b/common_modules/module_lib/src/txm_module_object_pointer_get_extended.c new file mode 100644 index 00000000..987de28a --- /dev/null +++ b/common_modules/module_lib/src/txm_module_object_pointer_get_extended.c @@ -0,0 +1,96 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_object_pointer_get_extended PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves the object pointer of a particular type */ +/* with a particular name. If the object is not found, an error is */ +/* returned. Otherwise, if the object is found, the address of that */ +/* object is placed in object_ptr. */ +/* */ +/* INPUT */ +/* */ +/* object_type Type of object, as follows: */ +/* */ +/* TXM_BLOCK_POOL_OBJECT */ +/* TXM_BYTE_POOL_OBJECT */ +/* TXM_EVENT_FLAGS_OBJECT */ +/* TXM_MUTEX_OBJECT */ +/* TXM_QUEUE_OBJECT */ +/* TXM_SEMAPHORE_OBJECT */ +/* TXM_THREAD_OBJECT */ +/* TXM_TIMER_OBJECT */ +/* name Name to search for */ +/* name_length Length of the name excluding */ +/* null-terminator */ +/* object_ptr Pointer to the object */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SUCCESS Successful completion */ +/* TX_PTR_ERROR Invalid name or object ptr */ +/* TX_OPTION_ERROR Invalid option type */ +/* TX_NO_INSTANCE Object not found */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_object_pointer_get_extended(UINT object_type, CHAR *name, UINT name_length, VOID **object_ptr) +{ + +UINT return_value; +ALIGN_TYPE extra_parameters[2]; + + extra_parameters[0] = (ALIGN_TYPE) name_length; + extra_parameters[1] = (ALIGN_TYPE) object_ptr; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_MODULE_OBJECT_POINTER_GET_EXTENDED_CALL, (ALIGN_TYPE) object_type, (ALIGN_TYPE) name, (ALIGN_TYPE) extra_parameters); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_module_thread_system_suspend.c b/common_modules/module_lib/src/txm_module_thread_system_suspend.c new file mode 100644 index 00000000..a94d3863 --- /dev/null +++ b/common_modules/module_lib/src/txm_module_thread_system_suspend.c @@ -0,0 +1,81 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_suspend PORTABLE C */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function suspends the specified thread and changes the thread */ +/* state to the value specified. Note: delayed suspension processing */ +/* is handled outside of this routine. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread to suspend */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_priority_change Thread priority change */ +/* _tx_thread_shell_entry Thread shell function */ +/* _tx_thread_sleep Thread sleep */ +/* _tx_thread_suspend Application thread suspend */ +/* _tx_thread_terminate Thread terminate */ +/* Other ThreadX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_thread_system_suspend(TX_THREAD *thread_ptr) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_THREAD_SYSTEM_SUSPEND_CALL, (ALIGN_TYPE) thread_ptr, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_mutex_create.c b/common_modules/module_lib/src/txm_mutex_create.c new file mode 100644 index 00000000..458b964e --- /dev/null +++ b/common_modules/module_lib/src/txm_mutex_create.c @@ -0,0 +1,84 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_mutex_create PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the create mutex function */ +/* call. */ +/* */ +/* INPUT */ +/* */ +/* mutex_ptr Pointer to mutex control block */ +/* name_ptr Pointer to mutex name */ +/* inherit Initial mutex count */ +/* mutex_control_block_size Size of mutex control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_MUTEX_ERROR Invalid mutex pointer */ +/* TX_CALLER_ERROR Invalid caller of this function */ +/* TX_INHERIT_ERROR Invalid inherit option */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_mutex_create(TX_MUTEX *mutex_ptr, CHAR *name_ptr, UINT inherit, UINT mutex_control_block_size) +{ + +UINT return_value; +ALIGN_TYPE extra_parameters[2]; + + extra_parameters[0] = (ALIGN_TYPE) inherit; + extra_parameters[1] = (ALIGN_TYPE) mutex_control_block_size; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_MUTEX_CREATE_CALL, (ALIGN_TYPE) mutex_ptr, (ALIGN_TYPE) name_ptr, (ALIGN_TYPE) extra_parameters); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_mutex_delete.c b/common_modules/module_lib/src/txm_mutex_delete.c new file mode 100644 index 00000000..4773c9c1 --- /dev/null +++ b/common_modules/module_lib/src/txm_mutex_delete.c @@ -0,0 +1,76 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_mutex_delete PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the mutex delete function */ +/* call. */ +/* */ +/* INPUT */ +/* */ +/* mutex_ptr Pointer to mutex control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_MUTEX_ERROR Invalid mutex pointer */ +/* TX_CALLER_ERROR Invalid caller of this function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_mutex_delete(TX_MUTEX *mutex_ptr) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_MUTEX_DELETE_CALL, (ALIGN_TYPE) mutex_ptr, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_mutex_get.c b/common_modules/module_lib/src/txm_mutex_get.c new file mode 100644 index 00000000..2c48dacd --- /dev/null +++ b/common_modules/module_lib/src/txm_mutex_get.c @@ -0,0 +1,76 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_mutex_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the mutex get function call. */ +/* */ +/* INPUT */ +/* */ +/* mutex_ptr Pointer to mutex control block */ +/* wait_option Suspension option */ +/* */ +/* OUTPUT */ +/* */ +/* TX_MUTEX_ERROR Invalid mutex pointer */ +/* TX_WAIT_ERROR Invalid wait option */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_mutex_get(TX_MUTEX *mutex_ptr, ULONG wait_option) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_MUTEX_GET_CALL, (ALIGN_TYPE) mutex_ptr, (ALIGN_TYPE) wait_option, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_mutex_info_get.c b/common_modules/module_lib/src/txm_mutex_info_get.c new file mode 100644 index 00000000..9f9c45f9 --- /dev/null +++ b/common_modules/module_lib/src/txm_mutex_info_get.c @@ -0,0 +1,91 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_mutex_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the mutex information get */ +/* service. */ +/* */ +/* INPUT */ +/* */ +/* mutex_ptr Pointer to mutex control block */ +/* name Destination for the mutex name */ +/* count Destination for the owner count */ +/* owner Destination for the owner's */ +/* thread control block pointer */ +/* first_suspended Destination for pointer of first */ +/* thread suspended on the mutex */ +/* suspended_count Destination for suspended count */ +/* next_mutex Destination for pointer to next */ +/* mutex on the created list */ +/* */ +/* OUTPUT */ +/* */ +/* TX_MUTEX_ERROR Invalid mutex pointer */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_mutex_info_get(TX_MUTEX *mutex_ptr, CHAR **name, ULONG *count, TX_THREAD **owner, TX_THREAD **first_suspended, ULONG *suspended_count, TX_MUTEX **next_mutex) +{ + +UINT return_value; +ALIGN_TYPE extra_parameters[5]; + + extra_parameters[0] = (ALIGN_TYPE) count; + extra_parameters[1] = (ALIGN_TYPE) owner; + extra_parameters[2] = (ALIGN_TYPE) first_suspended; + extra_parameters[3] = (ALIGN_TYPE) suspended_count; + extra_parameters[4] = (ALIGN_TYPE) next_mutex; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_MUTEX_INFO_GET_CALL, (ALIGN_TYPE) mutex_ptr, (ALIGN_TYPE) name, (ALIGN_TYPE) extra_parameters); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_mutex_performance_info_get.c b/common_modules/module_lib/src/txm_mutex_performance_info_get.c new file mode 100644 index 00000000..4a7c518b --- /dev/null +++ b/common_modules/module_lib/src/txm_mutex_performance_info_get.c @@ -0,0 +1,93 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_mutex_performance_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves performance information from the specified */ +/* mutex. */ +/* */ +/* INPUT */ +/* */ +/* mutex_ptr Pointer to mutex control block */ +/* puts Destination for the number of */ +/* puts on to this mutex */ +/* gets Destination for the number of */ +/* gets on this mutex */ +/* suspensions Destination for the number of */ +/* suspensions on this mutex */ +/* timeouts Destination for number of timeouts*/ +/* on this mutex */ +/* inversions Destination for number of priority*/ +/* inversions on this mutex */ +/* inheritances Destination for number of priority*/ +/* inheritances on this mutex */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_mutex_performance_info_get(TX_MUTEX *mutex_ptr, ULONG *puts, ULONG *gets, ULONG *suspensions, ULONG *timeouts, ULONG *inversions, ULONG *inheritances) +{ + +UINT return_value; +ALIGN_TYPE extra_parameters[5]; + + extra_parameters[0] = (ALIGN_TYPE) gets; + extra_parameters[1] = (ALIGN_TYPE) suspensions; + extra_parameters[2] = (ALIGN_TYPE) timeouts; + extra_parameters[3] = (ALIGN_TYPE) inversions; + extra_parameters[4] = (ALIGN_TYPE) inheritances; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_MUTEX_PERFORMANCE_INFO_GET_CALL, (ALIGN_TYPE) mutex_ptr, (ALIGN_TYPE) puts, (ALIGN_TYPE) extra_parameters); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_mutex_performance_system_info_get.c b/common_modules/module_lib/src/txm_mutex_performance_system_info_get.c new file mode 100644 index 00000000..09df71e3 --- /dev/null +++ b/common_modules/module_lib/src/txm_mutex_performance_system_info_get.c @@ -0,0 +1,90 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_mutex_performance_system_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves system mutex performance information. */ +/* */ +/* INPUT */ +/* */ +/* puts Destination for total number of */ +/* mutex puts */ +/* gets Destination for total number of */ +/* mutex gets */ +/* suspensions Destination for total number of */ +/* mutex suspensions */ +/* timeouts Destination for total number of */ +/* mutex timeouts */ +/* inversions Destination for total number of */ +/* mutex priority inversions */ +/* inheritances Destination for total number of */ +/* mutex priority inheritances */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_mutex_performance_system_info_get(ULONG *puts, ULONG *gets, ULONG *suspensions, ULONG *timeouts, ULONG *inversions, ULONG *inheritances) +{ + +UINT return_value; +ALIGN_TYPE extra_parameters[4]; + + extra_parameters[0] = (ALIGN_TYPE) suspensions; + extra_parameters[1] = (ALIGN_TYPE) timeouts; + extra_parameters[2] = (ALIGN_TYPE) inversions; + extra_parameters[3] = (ALIGN_TYPE) inheritances; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_MUTEX_PERFORMANCE_SYSTEM_INFO_GET_CALL, (ALIGN_TYPE) puts, (ALIGN_TYPE) gets, (ALIGN_TYPE) extra_parameters); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_mutex_prioritize.c b/common_modules/module_lib/src/txm_mutex_prioritize.c new file mode 100644 index 00000000..a499ecfb --- /dev/null +++ b/common_modules/module_lib/src/txm_mutex_prioritize.c @@ -0,0 +1,73 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_mutex_prioritize PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the mutex prioritize call. */ +/* */ +/* INPUT */ +/* */ +/* mutex_ptr Pointer to mutex control block */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_mutex_prioritize(TX_MUTEX *mutex_ptr) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_MUTEX_PRIORITIZE_CALL, (ALIGN_TYPE) mutex_ptr, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_mutex_put.c b/common_modules/module_lib/src/txm_mutex_put.c new file mode 100644 index 00000000..b49a5ed5 --- /dev/null +++ b/common_modules/module_lib/src/txm_mutex_put.c @@ -0,0 +1,74 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_mutex_put PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the mutex put function call. */ +/* */ +/* INPUT */ +/* */ +/* mutex_ptr Pointer to mutex control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_MUTEX_ERROR Invalid mutex pointer */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_mutex_put(TX_MUTEX *mutex_ptr) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_MUTEX_PUT_CALL, (ALIGN_TYPE) mutex_ptr, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_queue_create.c b/common_modules/module_lib/src/txm_queue_create.c new file mode 100644 index 00000000..ea61f29c --- /dev/null +++ b/common_modules/module_lib/src/txm_queue_create.c @@ -0,0 +1,87 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_queue_create PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the queue create function call. */ +/* */ +/* INPUT */ +/* */ +/* queue_ptr Pointer to queue control block */ +/* name_ptr Pointer to queue name */ +/* message_size Size of each queue message */ +/* queue_start Starting address of the queue area*/ +/* queue_size Number of bytes in the queue */ +/* queue_control_block_size Size of queue control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_QUEUE_ERROR Invalid queue pointer */ +/* TX_PTR_ERROR Invalid starting address of queue */ +/* TX_SIZE_ERROR Invalid message queue size */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_queue_create(TX_QUEUE *queue_ptr, CHAR *name_ptr, UINT message_size, VOID *queue_start, ULONG queue_size, UINT queue_control_block_size) +{ + +UINT return_value; +ALIGN_TYPE extra_parameters[4]; + + extra_parameters[0] = (ALIGN_TYPE) message_size; + extra_parameters[1] = (ALIGN_TYPE) queue_start; + extra_parameters[2] = (ALIGN_TYPE) queue_size; + extra_parameters[3] = (ALIGN_TYPE) queue_control_block_size; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_QUEUE_CREATE_CALL, (ALIGN_TYPE) queue_ptr, (ALIGN_TYPE) name_ptr, (ALIGN_TYPE) extra_parameters); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_queue_delete.c b/common_modules/module_lib/src/txm_queue_delete.c new file mode 100644 index 00000000..d277e3c0 --- /dev/null +++ b/common_modules/module_lib/src/txm_queue_delete.c @@ -0,0 +1,75 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_queue_delete PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the queue delete function call. */ +/* */ +/* INPUT */ +/* */ +/* queue_ptr Pointer to queue control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_QUEUE_ERROR Invalid queue pointer */ +/* TX_CALLER_ERROR Invalid caller of this function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_queue_delete(TX_QUEUE *queue_ptr) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_QUEUE_DELETE_CALL, (ALIGN_TYPE) queue_ptr, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_queue_flush.c b/common_modules/module_lib/src/txm_queue_flush.c new file mode 100644 index 00000000..22ba4f48 --- /dev/null +++ b/common_modules/module_lib/src/txm_queue_flush.c @@ -0,0 +1,75 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_queue_flush PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the queue flush function call. */ +/* */ +/* INPUT */ +/* */ +/* queue_ptr Pointer to queue control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_QUEUE_ERROR Invalid queue pointer */ +/* TX_CALLER_ERROR Invalid caller of this function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_queue_flush(TX_QUEUE *queue_ptr) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_QUEUE_FLUSH_CALL, (ALIGN_TYPE) queue_ptr, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_queue_front_send.c b/common_modules/module_lib/src/txm_queue_front_send.c new file mode 100644 index 00000000..88b847ff --- /dev/null +++ b/common_modules/module_lib/src/txm_queue_front_send.c @@ -0,0 +1,78 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_queue_front_send PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the queue send function call. */ +/* */ +/* INPUT */ +/* */ +/* queue_ptr Pointer to queue control block */ +/* source_ptr Pointer to message source */ +/* wait_option Suspension option */ +/* */ +/* OUTPUT */ +/* */ +/* TX_QUEUE_ERROR Invalid queue pointer */ +/* TX_PTR_ERROR Invalid source pointer - NULL */ +/* TX_WAIT_ERROR Invalid wait option - non thread */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_queue_front_send(TX_QUEUE *queue_ptr, VOID *source_ptr, ULONG wait_option) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_QUEUE_FRONT_SEND_CALL, (ALIGN_TYPE) queue_ptr, (ALIGN_TYPE) source_ptr, (ALIGN_TYPE) wait_option); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_queue_info_get.c b/common_modules/module_lib/src/txm_queue_info_get.c new file mode 100644 index 00000000..5c4147a9 --- /dev/null +++ b/common_modules/module_lib/src/txm_queue_info_get.c @@ -0,0 +1,90 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_queue_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the queue information get */ +/* service. */ +/* */ +/* INPUT */ +/* */ +/* queue_ptr Pointer to queue control block */ +/* name Destination for the queue name */ +/* enqueued Destination for enqueued count */ +/* available_storage Destination for available storage */ +/* first_suspended Destination for pointer of first */ +/* thread suspended on this queue */ +/* suspended_count Destination for suspended count */ +/* next_queue Destination for pointer to next */ +/* queue on the created list */ +/* */ +/* OUTPUT */ +/* */ +/* TX_QUEUE_ERROR Invalid queue pointer */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_queue_info_get(TX_QUEUE *queue_ptr, CHAR **name, ULONG *enqueued, ULONG *available_storage, TX_THREAD **first_suspended, ULONG *suspended_count, TX_QUEUE **next_queue) +{ + +UINT return_value; +ALIGN_TYPE extra_parameters[5]; + + extra_parameters[0] = (ALIGN_TYPE) enqueued; + extra_parameters[1] = (ALIGN_TYPE) available_storage; + extra_parameters[2] = (ALIGN_TYPE) first_suspended; + extra_parameters[3] = (ALIGN_TYPE) suspended_count; + extra_parameters[4] = (ALIGN_TYPE) next_queue; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_QUEUE_INFO_GET_CALL, (ALIGN_TYPE) queue_ptr, (ALIGN_TYPE) name, (ALIGN_TYPE) extra_parameters); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_queue_performance_info_get.c b/common_modules/module_lib/src/txm_queue_performance_info_get.c new file mode 100644 index 00000000..ace108b6 --- /dev/null +++ b/common_modules/module_lib/src/txm_queue_performance_info_get.c @@ -0,0 +1,91 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_queue_performance_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves performance information from the specified */ +/* queue. */ +/* */ +/* INPUT */ +/* */ +/* queue_ptr Pointer to queue control block */ +/* messages_sent Destination for messages sent */ +/* messages_received Destination for messages received */ +/* empty_suspensions Destination for number of empty */ +/* queue suspensions */ +/* full_suspensions Destination for number of full */ +/* queue suspensions */ +/* full_errors Destination for queue full errors */ +/* returned - no suspension */ +/* timeouts Destination for number of timeouts*/ +/* on this queue */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_queue_performance_info_get(TX_QUEUE *queue_ptr, ULONG *messages_sent, ULONG *messages_received, ULONG *empty_suspensions, ULONG *full_suspensions, ULONG *full_errors, ULONG *timeouts) +{ + +UINT return_value; +ALIGN_TYPE extra_parameters[5]; + + extra_parameters[0] = (ALIGN_TYPE) messages_received; + extra_parameters[1] = (ALIGN_TYPE) empty_suspensions; + extra_parameters[2] = (ALIGN_TYPE) full_suspensions; + extra_parameters[3] = (ALIGN_TYPE) full_errors; + extra_parameters[4] = (ALIGN_TYPE) timeouts; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_QUEUE_PERFORMANCE_INFO_GET_CALL, (ALIGN_TYPE) queue_ptr, (ALIGN_TYPE) messages_sent, (ALIGN_TYPE) extra_parameters); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_queue_performance_system_info_get.c b/common_modules/module_lib/src/txm_queue_performance_system_info_get.c new file mode 100644 index 00000000..78840480 --- /dev/null +++ b/common_modules/module_lib/src/txm_queue_performance_system_info_get.c @@ -0,0 +1,90 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_queue_performance_system_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves queue system performance information. */ +/* */ +/* INPUT */ +/* */ +/* messages_sent Destination for total messages */ +/* sent */ +/* messages_received Destination for total messages */ +/* received */ +/* empty_suspensions Destination for total empty */ +/* queue suspensions */ +/* full_suspensions Destination for total full */ +/* queue suspensions */ +/* full_errors Destination for total queue full */ +/* errors returned - no suspension */ +/* timeouts Destination for total number of */ +/* timeouts */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_queue_performance_system_info_get(ULONG *messages_sent, ULONG *messages_received, ULONG *empty_suspensions, ULONG *full_suspensions, ULONG *full_errors, ULONG *timeouts) +{ + +UINT return_value; +ALIGN_TYPE extra_parameters[4]; + + extra_parameters[0] = (ALIGN_TYPE) empty_suspensions; + extra_parameters[1] = (ALIGN_TYPE) full_suspensions; + extra_parameters[2] = (ALIGN_TYPE) full_errors; + extra_parameters[3] = (ALIGN_TYPE) timeouts; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_QUEUE_PERFORMANCE_SYSTEM_INFO_GET_CALL, (ALIGN_TYPE) messages_sent, (ALIGN_TYPE) messages_received, (ALIGN_TYPE) extra_parameters); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_queue_prioritize.c b/common_modules/module_lib/src/txm_queue_prioritize.c new file mode 100644 index 00000000..8d368808 --- /dev/null +++ b/common_modules/module_lib/src/txm_queue_prioritize.c @@ -0,0 +1,73 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_queue_prioritize PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the queue prioritize call. */ +/* */ +/* INPUT */ +/* */ +/* queue_ptr Pointer to queue control block */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_queue_prioritize(TX_QUEUE *queue_ptr) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_QUEUE_PRIORITIZE_CALL, (ALIGN_TYPE) queue_ptr, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_queue_receive.c b/common_modules/module_lib/src/txm_queue_receive.c new file mode 100644 index 00000000..dea6bfcd --- /dev/null +++ b/common_modules/module_lib/src/txm_queue_receive.c @@ -0,0 +1,80 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_queue_receive PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the queue receive function call. */ +/* */ +/* INPUT */ +/* */ +/* queue_ptr Pointer to queue control block */ +/* destination_ptr Pointer to message destination */ +/* **** MUST BE LARGE ENOUGH TO */ +/* HOLD MESSAGE **** */ +/* wait_option Suspension option */ +/* */ +/* OUTPUT */ +/* */ +/* TX_QUEUE_ERROR Invalid queue pointer */ +/* TX_PTR_ERROR Invalid destination pointer (NULL)*/ +/* TX_WAIT_ERROR Invalid wait option */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_queue_receive(TX_QUEUE *queue_ptr, VOID *destination_ptr, ULONG wait_option) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_QUEUE_RECEIVE_CALL, (ALIGN_TYPE) queue_ptr, (ALIGN_TYPE) destination_ptr, (ALIGN_TYPE) wait_option); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_queue_send.c b/common_modules/module_lib/src/txm_queue_send.c new file mode 100644 index 00000000..00f9b344 --- /dev/null +++ b/common_modules/module_lib/src/txm_queue_send.c @@ -0,0 +1,78 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_queue_send PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the queue send function call. */ +/* */ +/* INPUT */ +/* */ +/* queue_ptr Pointer to queue control block */ +/* source_ptr Pointer to message source */ +/* wait_option Suspension option */ +/* */ +/* OUTPUT */ +/* */ +/* TX_QUEUE_ERROR Invalid queue pointer */ +/* TX_PTR_ERROR Invalid source pointer - NULL */ +/* TX_WAIT_ERROR Invalid wait option */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_queue_send(TX_QUEUE *queue_ptr, VOID *source_ptr, ULONG wait_option) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_QUEUE_SEND_CALL, (ALIGN_TYPE) queue_ptr, (ALIGN_TYPE) source_ptr, (ALIGN_TYPE) wait_option); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_queue_send_notify.c b/common_modules/module_lib/src/txm_queue_send_notify.c new file mode 100644 index 00000000..c4be8e51 --- /dev/null +++ b/common_modules/module_lib/src/txm_queue_send_notify.c @@ -0,0 +1,76 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_queue_send_notify PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the queue send notify */ +/* callback function call. */ +/* */ +/* INPUT */ +/* */ +/* queue_ptr Pointer to queue control block*/ +/* queue_send_notify Application callback function */ +/* (TX_NULL disables notify) */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_queue_send_notify(TX_QUEUE *queue_ptr, VOID (*queue_send_notify)(TX_QUEUE *notify_queue_ptr)) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_QUEUE_SEND_NOTIFY_CALL, (ALIGN_TYPE) queue_ptr, (ALIGN_TYPE) queue_send_notify, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_semaphore_ceiling_put.c b/common_modules/module_lib/src/txm_semaphore_ceiling_put.c new file mode 100644 index 00000000..1c7c5967 --- /dev/null +++ b/common_modules/module_lib/src/txm_semaphore_ceiling_put.c @@ -0,0 +1,77 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_semaphore_ceiling_put PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the semaphore ceiling put */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* semaphore_ptr Pointer to semaphore */ +/* ceiling Maximum value of semaphore */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SEMAPHORE_ERROR Invalid semaphore pointer */ +/* TX_INVALID_CEILING Invalid semaphore ceiling */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_semaphore_ceiling_put(TX_SEMAPHORE *semaphore_ptr, ULONG ceiling) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_SEMAPHORE_CEILING_PUT_CALL, (ALIGN_TYPE) semaphore_ptr, (ALIGN_TYPE) ceiling, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_semaphore_create.c b/common_modules/module_lib/src/txm_semaphore_create.c new file mode 100644 index 00000000..31ae876a --- /dev/null +++ b/common_modules/module_lib/src/txm_semaphore_create.c @@ -0,0 +1,83 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_semaphore_create PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the create semaphore function */ +/* call. */ +/* */ +/* INPUT */ +/* */ +/* semaphore_ptr Pointer to semaphore control block*/ +/* name_ptr Pointer to semaphore name */ +/* initial_count Initial semaphore count */ +/* semaphore_control_block_size Size of semaphore control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SEMAPHORE_ERROR Invalid semaphore pointer */ +/* TX_CALLER_ERROR Invalid caller of this function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_semaphore_create(TX_SEMAPHORE *semaphore_ptr, CHAR *name_ptr, ULONG initial_count, UINT semaphore_control_block_size) +{ + +UINT return_value; +ALIGN_TYPE extra_parameters[2]; + + extra_parameters[0] = (ALIGN_TYPE) initial_count; + extra_parameters[1] = (ALIGN_TYPE) semaphore_control_block_size; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_SEMAPHORE_CREATE_CALL, (ALIGN_TYPE) semaphore_ptr, (ALIGN_TYPE) name_ptr, (ALIGN_TYPE) extra_parameters); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_semaphore_delete.c b/common_modules/module_lib/src/txm_semaphore_delete.c new file mode 100644 index 00000000..7180584a --- /dev/null +++ b/common_modules/module_lib/src/txm_semaphore_delete.c @@ -0,0 +1,76 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_semaphore_delete PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the semaphore delete function */ +/* call. */ +/* */ +/* INPUT */ +/* */ +/* semaphore_ptr Pointer to semaphore control block*/ +/* */ +/* OUTPUT */ +/* */ +/* TX_SEMAPHORE_ERROR Invalid semaphore pointer */ +/* TX_CALLER_ERROR Invalid caller of this function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_semaphore_delete(TX_SEMAPHORE *semaphore_ptr) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_SEMAPHORE_DELETE_CALL, (ALIGN_TYPE) semaphore_ptr, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_semaphore_get.c b/common_modules/module_lib/src/txm_semaphore_get.c new file mode 100644 index 00000000..b447d32f --- /dev/null +++ b/common_modules/module_lib/src/txm_semaphore_get.c @@ -0,0 +1,76 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_semaphore_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the semaphore get function call. */ +/* */ +/* INPUT */ +/* */ +/* semaphore_ptr Pointer to semaphore control block*/ +/* wait_option Suspension option */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SEMAPHORE_ERROR Invalid semaphore pointer */ +/* TX_WAIT_ERROR Invalid wait option */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_semaphore_get(TX_SEMAPHORE *semaphore_ptr, ULONG wait_option) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_SEMAPHORE_GET_CALL, (ALIGN_TYPE) semaphore_ptr, (ALIGN_TYPE) wait_option, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_semaphore_info_get.c b/common_modules/module_lib/src/txm_semaphore_info_get.c new file mode 100644 index 00000000..7c82c619 --- /dev/null +++ b/common_modules/module_lib/src/txm_semaphore_info_get.c @@ -0,0 +1,89 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_semaphore_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the semaphore information get */ +/* service. */ +/* */ +/* INPUT */ +/* */ +/* semaphore_ptr Pointer to semaphore control block*/ +/* name Destination for the semaphore name*/ +/* current_value Destination for current value of */ +/* the semaphore */ +/* first_suspended Destination for pointer of first */ +/* thread suspended on semaphore */ +/* suspended_count Destination for suspended count */ +/* next_semaphore Destination for pointer to next */ +/* semaphore on the created list */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SEMAPHORE_ERROR Invalid semaphore pointer */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_semaphore_info_get(TX_SEMAPHORE *semaphore_ptr, CHAR **name, ULONG *current_value, TX_THREAD **first_suspended, ULONG *suspended_count, TX_SEMAPHORE **next_semaphore) +{ + +UINT return_value; +ALIGN_TYPE extra_parameters[4]; + + extra_parameters[0] = (ALIGN_TYPE) current_value; + extra_parameters[1] = (ALIGN_TYPE) first_suspended; + extra_parameters[2] = (ALIGN_TYPE) suspended_count; + extra_parameters[3] = (ALIGN_TYPE) next_semaphore; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_SEMAPHORE_INFO_GET_CALL, (ALIGN_TYPE) semaphore_ptr, (ALIGN_TYPE) name, (ALIGN_TYPE) extra_parameters); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_semaphore_performance_info_get.c b/common_modules/module_lib/src/txm_semaphore_performance_info_get.c new file mode 100644 index 00000000..f845afe0 --- /dev/null +++ b/common_modules/module_lib/src/txm_semaphore_performance_info_get.c @@ -0,0 +1,87 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_semaphore_performance_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves performance information from the specified */ +/* semaphore. */ +/* */ +/* INPUT */ +/* */ +/* semaphore_ptr Pointer to semaphore control block*/ +/* puts Destination for the number of */ +/* puts on to this semaphore */ +/* gets Destination for the number of */ +/* gets on this semaphore */ +/* suspensions Destination for the number of */ +/* suspensions on this semaphore */ +/* timeouts Destination for number of timeouts*/ +/* on this semaphore */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_semaphore_performance_info_get(TX_SEMAPHORE *semaphore_ptr, ULONG *puts, ULONG *gets, ULONG *suspensions, ULONG *timeouts) +{ + +UINT return_value; +ALIGN_TYPE extra_parameters[3]; + + extra_parameters[0] = (ALIGN_TYPE) gets; + extra_parameters[1] = (ALIGN_TYPE) suspensions; + extra_parameters[2] = (ALIGN_TYPE) timeouts; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_SEMAPHORE_PERFORMANCE_INFO_GET_CALL, (ALIGN_TYPE) semaphore_ptr, (ALIGN_TYPE) puts, (ALIGN_TYPE) extra_parameters); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_semaphore_performance_system_info_get.c b/common_modules/module_lib/src/txm_semaphore_performance_system_info_get.c new file mode 100644 index 00000000..f2db0a7c --- /dev/null +++ b/common_modules/module_lib/src/txm_semaphore_performance_system_info_get.c @@ -0,0 +1,84 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_semaphore_performance_system_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves system semaphore performance information. */ +/* */ +/* INPUT */ +/* */ +/* puts Destination for total number of */ +/* semaphore puts */ +/* gets Destination for total number of */ +/* semaphore gets */ +/* suspensions Destination for total number of */ +/* semaphore suspensions */ +/* timeouts Destination for total number of */ +/* timeouts */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_semaphore_performance_system_info_get(ULONG *puts, ULONG *gets, ULONG *suspensions, ULONG *timeouts) +{ + +UINT return_value; +ALIGN_TYPE extra_parameters[2]; + + extra_parameters[0] = (ALIGN_TYPE) suspensions; + extra_parameters[1] = (ALIGN_TYPE) timeouts; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_SEMAPHORE_PERFORMANCE_SYSTEM_INFO_GET_CALL, (ALIGN_TYPE) puts, (ALIGN_TYPE) gets, (ALIGN_TYPE) extra_parameters); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_semaphore_prioritize.c b/common_modules/module_lib/src/txm_semaphore_prioritize.c new file mode 100644 index 00000000..505937d1 --- /dev/null +++ b/common_modules/module_lib/src/txm_semaphore_prioritize.c @@ -0,0 +1,73 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_semaphore_prioritize PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the semaphore prioritize call. */ +/* */ +/* INPUT */ +/* */ +/* semaphore_ptr Pointer to semaphore control block*/ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_semaphore_prioritize(TX_SEMAPHORE *semaphore_ptr) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_SEMAPHORE_PRIORITIZE_CALL, (ALIGN_TYPE) semaphore_ptr, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_semaphore_put.c b/common_modules/module_lib/src/txm_semaphore_put.c new file mode 100644 index 00000000..0233b166 --- /dev/null +++ b/common_modules/module_lib/src/txm_semaphore_put.c @@ -0,0 +1,74 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_semaphore_put PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the semaphore put function call. */ +/* */ +/* INPUT */ +/* */ +/* semaphore_ptr Pointer to semaphore control block*/ +/* */ +/* OUTPUT */ +/* */ +/* TX_SEMAPHORE_ERROR Invalid semaphore pointer */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_semaphore_put(TX_SEMAPHORE *semaphore_ptr) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_SEMAPHORE_PUT_CALL, (ALIGN_TYPE) semaphore_ptr, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_semaphore_put_notify.c b/common_modules/module_lib/src/txm_semaphore_put_notify.c new file mode 100644 index 00000000..7a884677 --- /dev/null +++ b/common_modules/module_lib/src/txm_semaphore_put_notify.c @@ -0,0 +1,76 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_semaphore_put_notify PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the semaphore put notify */ +/* callback function call. */ +/* */ +/* INPUT */ +/* */ +/* semaphore_ptr Pointer to semaphore */ +/* semaphore_put_notify Application callback function */ +/* (TX_NULL disables notify) */ +/* */ +/* OUTPUT */ +/* */ +/* status Service return status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_semaphore_put_notify(TX_SEMAPHORE *semaphore_ptr, VOID (*semaphore_put_notify)(TX_SEMAPHORE *notify_semaphore_ptr)) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_SEMAPHORE_PUT_NOTIFY_CALL, (ALIGN_TYPE) semaphore_ptr, (ALIGN_TYPE) semaphore_put_notify, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_thread_create.c b/common_modules/module_lib/src/txm_thread_create.c new file mode 100644 index 00000000..1a756ea7 --- /dev/null +++ b/common_modules/module_lib/src/txm_thread_create.c @@ -0,0 +1,100 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_create PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the thread create function call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* name Pointer to thread name string */ +/* entry_function Entry function of the thread */ +/* entry_input 32-bit input value to thread */ +/* stack_start Pointer to start of stack */ +/* stack_size Stack size in bytes */ +/* priority Priority of thread (0-31) */ +/* preempt_threshold Preemption threshold */ +/* time_slice Thread time-slice value */ +/* auto_start Automatic start selection */ +/* thread_control_block_size Size of thread control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_PTR_ERROR Invalid entry point or stack */ +/* address */ +/* TX_SIZE_ERROR Invalid stack size -too small */ +/* TX_PRIORITY_ERROR Invalid thread priority */ +/* TX_THRESH_ERROR Invalid preemption threshold */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_create(TX_THREAD *thread_ptr, CHAR *name_ptr, VOID (*entry_function)(ULONG entry_input), ULONG entry_input, VOID *stack_start, ULONG stack_size, UINT priority, UINT preempt_threshold, ULONG time_slice, UINT auto_start, UINT thread_control_block_size) +{ + +UINT return_value; +ALIGN_TYPE extra_parameters[9]; + + extra_parameters[0] = (ALIGN_TYPE) entry_function; + extra_parameters[1] = (ALIGN_TYPE) entry_input; + extra_parameters[2] = (ALIGN_TYPE) stack_start; + extra_parameters[3] = (ALIGN_TYPE) stack_size; + extra_parameters[4] = (ALIGN_TYPE) priority; + extra_parameters[5] = (ALIGN_TYPE) preempt_threshold; + extra_parameters[6] = (ALIGN_TYPE) time_slice; + extra_parameters[7] = (ALIGN_TYPE) auto_start; + extra_parameters[8] = (ALIGN_TYPE) thread_control_block_size; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_THREAD_CREATE_CALL, (ALIGN_TYPE) thread_ptr, (ALIGN_TYPE) name_ptr, (ALIGN_TYPE) extra_parameters); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_thread_delete.c b/common_modules/module_lib/src/txm_thread_delete.c new file mode 100644 index 00000000..d8812755 --- /dev/null +++ b/common_modules/module_lib/src/txm_thread_delete.c @@ -0,0 +1,75 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_delete PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the thread delete function call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread to suspend */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_delete(TX_THREAD *thread_ptr) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_THREAD_DELETE_CALL, (ALIGN_TYPE) thread_ptr, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_thread_entry_exit_notify.c b/common_modules/module_lib/src/txm_thread_entry_exit_notify.c new file mode 100644 index 00000000..163b666f --- /dev/null +++ b/common_modules/module_lib/src/txm_thread_entry_exit_notify.c @@ -0,0 +1,76 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_entry_exit_notify PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the thread entry/exit notify */ +/* callback function call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread */ +/* thread_entry_exit_notify Pointer to notify callback */ +/* function, TX_NULL to disable*/ +/* */ +/* OUTPUT */ +/* */ +/* status Service return status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_entry_exit_notify(TX_THREAD *thread_ptr, VOID (*thread_entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT type)) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_THREAD_ENTRY_EXIT_NOTIFY_CALL, (ALIGN_TYPE) thread_ptr, (ALIGN_TYPE) thread_entry_exit_notify, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_thread_identify.c b/common_modules/module_lib/src/txm_thread_identify.c new file mode 100644 index 00000000..b2c5eb10 --- /dev/null +++ b/common_modules/module_lib/src/txm_thread_identify.c @@ -0,0 +1,76 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_identify PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function returns the control block pointer of the currently */ +/* executing thread. If the return value is NULL, no thread is */ +/* executing. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD * Pointer to control block of */ +/* currently executing thread */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +TX_THREAD *_tx_thread_identify(VOID) +{ + +TX_THREAD *return_value; + + /* Call module manager dispatcher. */ + return_value = (TX_THREAD *) (_txm_module_kernel_call_dispatcher)(TXM_THREAD_IDENTIFY_CALL, 0, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_thread_info_get.c b/common_modules/module_lib/src/txm_thread_info_get.c new file mode 100644 index 00000000..a8ecc93c --- /dev/null +++ b/common_modules/module_lib/src/txm_thread_info_get.c @@ -0,0 +1,95 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the thread information get */ +/* service. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control block */ +/* name Destination for the thread name */ +/* state Destination for thread state */ +/* run_count Destination for thread run count */ +/* priority Destination for thread priority */ +/* preemption_threshold Destination for thread preemption-*/ +/* threshold */ +/* time_slice Destination for thread time-slice */ +/* next_thread Destination for next created */ +/* thread */ +/* next_suspended_thread Destination for next suspended */ +/* thread */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_info_get(TX_THREAD *thread_ptr, CHAR **name, UINT *state, ULONG *run_count, UINT *priority, UINT *preemption_threshold, ULONG *time_slice, TX_THREAD **next_thread, TX_THREAD **next_suspended_thread) +{ + +UINT return_value; +ALIGN_TYPE extra_parameters[7]; + + extra_parameters[0] = (ALIGN_TYPE) state; + extra_parameters[1] = (ALIGN_TYPE) run_count; + extra_parameters[2] = (ALIGN_TYPE) priority; + extra_parameters[3] = (ALIGN_TYPE) preemption_threshold; + extra_parameters[4] = (ALIGN_TYPE) time_slice; + extra_parameters[5] = (ALIGN_TYPE) next_thread; + extra_parameters[6] = (ALIGN_TYPE) next_suspended_thread; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_THREAD_INFO_GET_CALL, (ALIGN_TYPE) thread_ptr, (ALIGN_TYPE) name, (ALIGN_TYPE) extra_parameters); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_thread_interrupt_control.c b/common_modules/module_lib/src/txm_thread_interrupt_control.c new file mode 100644 index 00000000..a3df15ed --- /dev/null +++ b/common_modules/module_lib/src/txm_thread_interrupt_control.c @@ -0,0 +1,76 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* status | old_posture Return status if feature not */ +/* enabled, old interrupt lockout */ +/* posture if feature enabled. */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_thread_interrupt_control(UINT new_posture) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_THREAD_INTERRUPT_CONTROL_CALL, (ALIGN_TYPE) new_posture, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_thread_performance_info_get.c b/common_modules/module_lib/src/txm_thread_performance_info_get.c new file mode 100644 index 00000000..af58f66f --- /dev/null +++ b/common_modules/module_lib/src/txm_thread_performance_info_get.c @@ -0,0 +1,110 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_performance_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves performance information from the specified */ +/* thread. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control block */ +/* resumptions Destination for number of times */ +/* thread was resumed */ +/* suspensions Destination for number of times */ +/* thread was suspended */ +/* solicited_preemptions Destination for number of times */ +/* thread called another service */ +/* that resulted in preemption */ +/* interrupt_preemptions Destination for number of times */ +/* thread was preempted by another */ +/* thread made ready in Interrupt */ +/* Service Routine (ISR) */ +/* priority_inversions Destination for number of times */ +/* a priority inversion was */ +/* detected for this thread */ +/* time_slices Destination for number of times */ +/* thread was time-sliced */ +/* relinquishes Destination for number of thread */ +/* relinquishes */ +/* timeouts Destination for number of timeouts*/ +/* for thread */ +/* wait_aborts Destination for number of wait */ +/* aborts for thread */ +/* last_preempted_by Destination for pointer of the */ +/* thread that last preempted this */ +/* thread */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_thread_performance_info_get(TX_THREAD *thread_ptr, ULONG *resumptions, ULONG *suspensions, ULONG *solicited_preemptions, ULONG *interrupt_preemptions, ULONG *priority_inversions, ULONG *time_slices, ULONG *relinquishes, ULONG *timeouts, ULONG *wait_aborts, TX_THREAD **last_preempted_by) +{ + +UINT return_value; +ALIGN_TYPE extra_parameters[9]; + + extra_parameters[0] = (ALIGN_TYPE) suspensions; + extra_parameters[1] = (ALIGN_TYPE) solicited_preemptions; + extra_parameters[2] = (ALIGN_TYPE) interrupt_preemptions; + extra_parameters[3] = (ALIGN_TYPE) priority_inversions; + extra_parameters[4] = (ALIGN_TYPE) time_slices; + extra_parameters[5] = (ALIGN_TYPE) relinquishes; + extra_parameters[6] = (ALIGN_TYPE) timeouts; + extra_parameters[7] = (ALIGN_TYPE) wait_aborts; + extra_parameters[8] = (ALIGN_TYPE) last_preempted_by; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_THREAD_PERFORMANCE_INFO_GET_CALL, (ALIGN_TYPE) thread_ptr, (ALIGN_TYPE) resumptions, (ALIGN_TYPE) extra_parameters); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_thread_performance_system_info_get.c b/common_modules/module_lib/src/txm_thread_performance_system_info_get.c new file mode 100644 index 00000000..a696f74c --- /dev/null +++ b/common_modules/module_lib/src/txm_thread_performance_system_info_get.c @@ -0,0 +1,110 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_performance_system_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves thread system performance information. */ +/* */ +/* INPUT */ +/* */ +/* resumptions Destination for total number of */ +/* thread resumptions */ +/* suspensions Destination for total number of */ +/* thread suspensions */ +/* solicited_preemptions Destination for total number of */ +/* thread preemption from thread */ +/* API calls */ +/* interrupt_preemptions Destination for total number of */ +/* thread preemptions as a result */ +/* of threads made ready inside of */ +/* Interrupt Service Routines */ +/* priority_inversions Destination for total number of */ +/* priority inversions */ +/* time_slices Destination for total number of */ +/* time-slices */ +/* relinquishes Destination for total number of */ +/* relinquishes */ +/* timeouts Destination for total number of */ +/* timeouts */ +/* wait_aborts Destination for total number of */ +/* wait aborts */ +/* non_idle_returns Destination for total number of */ +/* times threads return when */ +/* another thread is ready */ +/* idle_returns Destination for total number of */ +/* times threads return when no */ +/* other thread is ready */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_thread_performance_system_info_get(ULONG *resumptions, ULONG *suspensions, ULONG *solicited_preemptions, ULONG *interrupt_preemptions, ULONG *priority_inversions, ULONG *time_slices, ULONG *relinquishes, ULONG *timeouts, ULONG *wait_aborts, ULONG *non_idle_returns, ULONG *idle_returns) +{ + +UINT return_value; +ALIGN_TYPE extra_parameters[9]; + + extra_parameters[0] = (ALIGN_TYPE) solicited_preemptions; + extra_parameters[1] = (ALIGN_TYPE) interrupt_preemptions; + extra_parameters[2] = (ALIGN_TYPE) priority_inversions; + extra_parameters[3] = (ALIGN_TYPE) time_slices; + extra_parameters[4] = (ALIGN_TYPE) relinquishes; + extra_parameters[5] = (ALIGN_TYPE) timeouts; + extra_parameters[6] = (ALIGN_TYPE) wait_aborts; + extra_parameters[7] = (ALIGN_TYPE) non_idle_returns; + extra_parameters[8] = (ALIGN_TYPE) idle_returns; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_THREAD_PERFORMANCE_SYSTEM_INFO_GET_CALL, (ALIGN_TYPE) resumptions, (ALIGN_TYPE) suspensions, (ALIGN_TYPE) extra_parameters); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_thread_preemption_change.c b/common_modules/module_lib/src/txm_thread_preemption_change.c new file mode 100644 index 00000000..ef9195ef --- /dev/null +++ b/common_modules/module_lib/src/txm_thread_preemption_change.c @@ -0,0 +1,79 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_preemption_change PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the preemption threshold change */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread */ +/* new_threshold New preemption threshold */ +/* old_threshold Old preemption threshold */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_PTR_ERROR Invalid old threshold pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_preemption_change(TX_THREAD *thread_ptr, UINT new_threshold, UINT *old_threshold) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_THREAD_PREEMPTION_CHANGE_CALL, (ALIGN_TYPE) thread_ptr, (ALIGN_TYPE) new_threshold, (ALIGN_TYPE) old_threshold); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_thread_priority_change.c b/common_modules/module_lib/src/txm_thread_priority_change.c new file mode 100644 index 00000000..08da0b00 --- /dev/null +++ b/common_modules/module_lib/src/txm_thread_priority_change.c @@ -0,0 +1,79 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_priority_change PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the change priority function */ +/* call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread to suspend */ +/* new_priority New thread priority */ +/* old_priority Old thread priority */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_PTR_ERROR Invalid old priority pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_priority_change(TX_THREAD *thread_ptr, UINT new_priority, UINT *old_priority) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_THREAD_PRIORITY_CHANGE_CALL, (ALIGN_TYPE) thread_ptr, (ALIGN_TYPE) new_priority, (ALIGN_TYPE) old_priority); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_thread_relinquish.c b/common_modules/module_lib/src/txm_thread_relinquish.c new file mode 100644 index 00000000..cc7acc9a --- /dev/null +++ b/common_modules/module_lib/src/txm_thread_relinquish.c @@ -0,0 +1,70 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_relinquish PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks to make sure a thread is executing before the */ +/* relinquish is executed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _txe_thread_relinquish(VOID) +{ + + + /* Call module manager dispatcher. */ + (_txm_module_kernel_call_dispatcher)(TXM_THREAD_RELINQUISH_CALL, 0, 0, 0); +} diff --git a/common_modules/module_lib/src/txm_thread_reset.c b/common_modules/module_lib/src/txm_thread_reset.c new file mode 100644 index 00000000..b907f30d --- /dev/null +++ b/common_modules/module_lib/src/txm_thread_reset.c @@ -0,0 +1,75 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_reset PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the thread reset function call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread to reset */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Service return status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_reset(TX_THREAD *thread_ptr) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_THREAD_RESET_CALL, (ALIGN_TYPE) thread_ptr, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_thread_resume.c b/common_modules/module_lib/src/txm_thread_resume.c new file mode 100644 index 00000000..8738f346 --- /dev/null +++ b/common_modules/module_lib/src/txm_thread_resume.c @@ -0,0 +1,74 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_resume PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the resume thread function call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread to resume */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_resume(TX_THREAD *thread_ptr) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_THREAD_RESUME_CALL, (ALIGN_TYPE) thread_ptr, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_thread_sleep.c b/common_modules/module_lib/src/txm_thread_sleep.c new file mode 100644 index 00000000..f9e9a291 --- /dev/null +++ b/common_modules/module_lib/src/txm_thread_sleep.c @@ -0,0 +1,74 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_sleep PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles application thread sleep requests. If the */ +/* sleep request was called from a non-thread, an error is returned. */ +/* */ +/* INPUT */ +/* */ +/* timer_ticks Number of timer ticks to sleep*/ +/* */ +/* OUTPUT */ +/* */ +/* status Return completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_thread_sleep(ULONG timer_ticks) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_THREAD_SLEEP_CALL, (ALIGN_TYPE) timer_ticks, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_thread_stack_error_notify.c b/common_modules/module_lib/src/txm_thread_stack_error_notify.c new file mode 100644 index 00000000..f982ed29 --- /dev/null +++ b/common_modules/module_lib/src/txm_thread_stack_error_notify.c @@ -0,0 +1,78 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_error_notify PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application stack error handler. If */ +/* ThreadX detects a stack error, this application handler is called. */ +/* */ +/* Note: stack checking must be enabled for this routine to serve any */ +/* purpose via the TX_ENABLE_STACK_CHECKING define. */ +/* */ +/* INPUT */ +/* */ +/* stack_error_handler Pointer to stack error */ +/* handler, TX_NULL to disable */ +/* */ +/* OUTPUT */ +/* */ +/* status Service return status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr)) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_THREAD_STACK_ERROR_NOTIFY_CALL, (ALIGN_TYPE) stack_error_handler, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_thread_suspend.c b/common_modules/module_lib/src/txm_thread_suspend.c new file mode 100644 index 00000000..a1a496da --- /dev/null +++ b/common_modules/module_lib/src/txm_thread_suspend.c @@ -0,0 +1,76 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_suspend PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the thread suspend function */ +/* call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread to suspend */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_suspend(TX_THREAD *thread_ptr) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_THREAD_SUSPEND_CALL, (ALIGN_TYPE) thread_ptr, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_thread_terminate.c b/common_modules/module_lib/src/txm_thread_terminate.c new file mode 100644 index 00000000..a082e45b --- /dev/null +++ b/common_modules/module_lib/src/txm_thread_terminate.c @@ -0,0 +1,76 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_terminate PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the thread terminate function */ +/* call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread to suspend */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_terminate(TX_THREAD *thread_ptr) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_THREAD_TERMINATE_CALL, (ALIGN_TYPE) thread_ptr, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_thread_time_slice_change.c b/common_modules/module_lib/src/txm_thread_time_slice_change.c new file mode 100644 index 00000000..8fbb892e --- /dev/null +++ b/common_modules/module_lib/src/txm_thread_time_slice_change.c @@ -0,0 +1,78 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_time_slice_change PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the time slice change function */ +/* call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread */ +/* new_time_slice New time slice */ +/* old_time_slice Old time slice */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_time_slice_change(TX_THREAD *thread_ptr, ULONG new_time_slice, ULONG *old_time_slice) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_THREAD_TIME_SLICE_CHANGE_CALL, (ALIGN_TYPE) thread_ptr, (ALIGN_TYPE) new_time_slice, (ALIGN_TYPE) old_time_slice); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_thread_wait_abort.c b/common_modules/module_lib/src/txm_thread_wait_abort.c new file mode 100644 index 00000000..ba2da979 --- /dev/null +++ b/common_modules/module_lib/src/txm_thread_wait_abort.c @@ -0,0 +1,74 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_wait_abort PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the thread wait abort function */ +/* call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread to abort the wait on */ +/* */ +/* OUTPUT */ +/* */ +/* status Return completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_wait_abort(TX_THREAD *thread_ptr) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_THREAD_WAIT_ABORT_CALL, (ALIGN_TYPE) thread_ptr, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_time_get.c b/common_modules/module_lib/src/txm_time_get.c new file mode 100644 index 00000000..679acaca --- /dev/null +++ b/common_modules/module_lib/src/txm_time_get.c @@ -0,0 +1,74 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_time_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves the internal, free-running, system clock */ +/* and returns it to the caller. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* _tx_timer_system_clock Returns the system clock value */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +ULONG _tx_time_get(VOID) +{ + +ULONG return_value; + + /* Call module manager dispatcher. */ + return_value = (ULONG) (_txm_module_kernel_call_dispatcher)(TXM_TIME_GET_CALL, 0, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_time_set.c b/common_modules/module_lib/src/txm_time_set.c new file mode 100644 index 00000000..6e081b5a --- /dev/null +++ b/common_modules/module_lib/src/txm_time_set.c @@ -0,0 +1,70 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_time_set PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function modifies the internal, free-running, system clock */ +/* as specified by the caller. */ +/* */ +/* INPUT */ +/* */ +/* new_time New time value */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_time_set(ULONG new_time) +{ + + + /* Call module manager dispatcher. */ + (_txm_module_kernel_call_dispatcher)(TXM_TIME_SET_CALL, (ALIGN_TYPE) new_time, 0, 0); +} diff --git a/common_modules/module_lib/src/txm_timer_activate.c b/common_modules/module_lib/src/txm_timer_activate.c new file mode 100644 index 00000000..cf13e61d --- /dev/null +++ b/common_modules/module_lib/src/txm_timer_activate.c @@ -0,0 +1,76 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_timer_activate PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the activate application timer */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* timer_ptr Pointer to timer control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_TIMER_ERROR Invalid application timer */ +/* TX_ACTIVATE_ERROR Application timer already active */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_timer_activate(TX_TIMER *timer_ptr) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_TIMER_ACTIVATE_CALL, (ALIGN_TYPE) timer_ptr, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_timer_change.c b/common_modules/module_lib/src/txm_timer_change.c new file mode 100644 index 00000000..31da4ac9 --- /dev/null +++ b/common_modules/module_lib/src/txm_timer_change.c @@ -0,0 +1,79 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_timer_change PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the application timer change */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* timer_ptr Pointer to timer control block */ +/* initial_ticks Initial expiration ticks */ +/* reschedule_ticks Reschedule ticks */ +/* */ +/* OUTPUT */ +/* */ +/* TX_TIMER_ERROR Invalid application timer pointer */ +/* TX_TICK_ERROR Invalid initial tick value of 0 */ +/* TX_CALLER_ERROR Invalid caller of this function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_timer_change(TX_TIMER *timer_ptr, ULONG initial_ticks, ULONG reschedule_ticks) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_TIMER_CHANGE_CALL, (ALIGN_TYPE) timer_ptr, (ALIGN_TYPE) initial_ticks, (ALIGN_TYPE) reschedule_ticks); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_timer_create.c b/common_modules/module_lib/src/txm_timer_create.c new file mode 100644 index 00000000..b70abd0a --- /dev/null +++ b/common_modules/module_lib/src/txm_timer_create.c @@ -0,0 +1,92 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_timer_create PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the create application timer */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* timer_ptr Pointer to timer control block */ +/* name_ptr Pointer to timer name */ +/* expiration_function Application expiration function */ +/* initial_ticks Initial expiration ticks */ +/* reschedule_ticks Reschedule ticks */ +/* auto_activate Automatic activation flag */ +/* timer_control_block_size Size of timer control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_TIMER_ERROR Invalid timer control block */ +/* TX_TICK_ERROR Invalid initial expiration count */ +/* TX_ACTIVATE_ERROR Invalid timer activation option */ +/* TX_CALLER_ERROR Invalid caller of this function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_timer_create(TX_TIMER *timer_ptr, CHAR *name_ptr, VOID (*expiration_function)(ULONG), ULONG expiration_input, ULONG initial_ticks, ULONG reschedule_ticks, UINT auto_activate, UINT timer_control_block_size) +{ + +UINT return_value; +ALIGN_TYPE extra_parameters[6]; + + extra_parameters[0] = (ALIGN_TYPE) expiration_function; + extra_parameters[1] = (ALIGN_TYPE) expiration_input; + extra_parameters[2] = (ALIGN_TYPE) initial_ticks; + extra_parameters[3] = (ALIGN_TYPE) reschedule_ticks; + extra_parameters[4] = (ALIGN_TYPE) auto_activate; + extra_parameters[5] = (ALIGN_TYPE) timer_control_block_size; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_TIMER_CREATE_CALL, (ALIGN_TYPE) timer_ptr, (ALIGN_TYPE) name_ptr, (ALIGN_TYPE) extra_parameters); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_timer_deactivate.c b/common_modules/module_lib/src/txm_timer_deactivate.c new file mode 100644 index 00000000..7f74bc5c --- /dev/null +++ b/common_modules/module_lib/src/txm_timer_deactivate.c @@ -0,0 +1,75 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_timer_deactivate PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the deactivate application timer */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* timer_ptr Pointer to timer control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_TIMER_ERROR Invalid application timer pointer */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_timer_deactivate(TX_TIMER *timer_ptr) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_TIMER_DEACTIVATE_CALL, (ALIGN_TYPE) timer_ptr, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_timer_delete.c b/common_modules/module_lib/src/txm_timer_delete.c new file mode 100644 index 00000000..df7421bc --- /dev/null +++ b/common_modules/module_lib/src/txm_timer_delete.c @@ -0,0 +1,76 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_timer_delete PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the delete application timer */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* timer_ptr Pointer to timer control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_TIMER_ERROR Invalid application timer pointer */ +/* TX_CALLER_ERROR Invalid caller of this function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_timer_delete(TX_TIMER *timer_ptr) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_TIMER_DELETE_CALL, (ALIGN_TYPE) timer_ptr, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_timer_info_get.c b/common_modules/module_lib/src/txm_timer_info_get.c new file mode 100644 index 00000000..890df7f5 --- /dev/null +++ b/common_modules/module_lib/src/txm_timer_info_get.c @@ -0,0 +1,88 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_timer_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the timer information get */ +/* service. */ +/* */ +/* INPUT */ +/* */ +/* timer_ptr Pointer to timer control block */ +/* name Destination for the timer name */ +/* active Destination for active flag */ +/* remaining_ticks Destination for remaining ticks */ +/* before expiration */ +/* reschedule_ticks Destination for reschedule ticks */ +/* next_timer Destination for next timer on the */ +/* created list */ +/* */ +/* OUTPUT */ +/* */ +/* TX_TIMER_ERROR Invalid timer pointer */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_timer_info_get(TX_TIMER *timer_ptr, CHAR **name, UINT *active, ULONG *remaining_ticks, ULONG *reschedule_ticks, TX_TIMER **next_timer) +{ + +UINT return_value; +ALIGN_TYPE extra_parameters[4]; + + extra_parameters[0] = (ALIGN_TYPE) active; + extra_parameters[1] = (ALIGN_TYPE) remaining_ticks; + extra_parameters[2] = (ALIGN_TYPE) reschedule_ticks; + extra_parameters[3] = (ALIGN_TYPE) next_timer; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_TIMER_INFO_GET_CALL, (ALIGN_TYPE) timer_ptr, (ALIGN_TYPE) name, (ALIGN_TYPE) extra_parameters); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_timer_performance_info_get.c b/common_modules/module_lib/src/txm_timer_performance_info_get.c new file mode 100644 index 00000000..1896f344 --- /dev/null +++ b/common_modules/module_lib/src/txm_timer_performance_info_get.c @@ -0,0 +1,91 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_performance_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves performance information from the specified */ +/* timer. */ +/* */ +/* INPUT */ +/* */ +/* timer_ptr Pointer to timer control block */ +/* activates Destination for the number of */ +/* activations of this timer */ +/* reactivates Destination for the number of */ +/* reactivations of this timer */ +/* deactivates Destination for the number of */ +/* deactivations of this timer */ +/* expirations Destination for the number of */ +/* expirations of this timer */ +/* expiration_adjusts Destination for the number of */ +/* expiration adjustments of this */ +/* timer */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_timer_performance_info_get(TX_TIMER *timer_ptr, ULONG *activates, ULONG *reactivates, ULONG *deactivates, ULONG *expirations, ULONG *expiration_adjusts) +{ + +UINT return_value; +ALIGN_TYPE extra_parameters[4]; + + extra_parameters[0] = (ALIGN_TYPE) reactivates; + extra_parameters[1] = (ALIGN_TYPE) deactivates; + extra_parameters[2] = (ALIGN_TYPE) expirations; + extra_parameters[3] = (ALIGN_TYPE) expiration_adjusts; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_TIMER_PERFORMANCE_INFO_GET_CALL, (ALIGN_TYPE) timer_ptr, (ALIGN_TYPE) activates, (ALIGN_TYPE) extra_parameters); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_timer_performance_system_info_get.c b/common_modules/module_lib/src/txm_timer_performance_system_info_get.c new file mode 100644 index 00000000..43a00acf --- /dev/null +++ b/common_modules/module_lib/src/txm_timer_performance_system_info_get.c @@ -0,0 +1,87 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_performance_system_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves timer performance information. */ +/* */ +/* INPUT */ +/* */ +/* activates Destination for total number of */ +/* activations */ +/* reactivates Destination for total number of */ +/* reactivations */ +/* deactivates Destination for total number of */ +/* deactivations */ +/* expirations Destination for total number of */ +/* expirations */ +/* expiration_adjusts Destination for total number of */ +/* expiration adjustments */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_timer_performance_system_info_get(ULONG *activates, ULONG *reactivates, ULONG *deactivates, ULONG *expirations, ULONG *expiration_adjusts) +{ + +UINT return_value; +ALIGN_TYPE extra_parameters[3]; + + extra_parameters[0] = (ALIGN_TYPE) deactivates; + extra_parameters[1] = (ALIGN_TYPE) expirations; + extra_parameters[2] = (ALIGN_TYPE) expiration_adjusts; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_TIMER_PERFORMANCE_SYSTEM_INFO_GET_CALL, (ALIGN_TYPE) activates, (ALIGN_TYPE) reactivates, (ALIGN_TYPE) extra_parameters); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_trace_buffer_full_notify.c b/common_modules/module_lib/src/txm_trace_buffer_full_notify.c new file mode 100644 index 00000000..703cade7 --- /dev/null +++ b/common_modules/module_lib/src/txm_trace_buffer_full_notify.c @@ -0,0 +1,77 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_trace_buffer_full_notify PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets up the application callback function that is */ +/* called whenever the trace buffer becomes full. The application */ +/* can then swap to a new trace buffer in order not to lose any */ +/* events. */ +/* */ +/* INPUT */ +/* */ +/* full_buffer_callback Full trace buffer processing */ +/* function */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_trace_buffer_full_notify(VOID (*full_buffer_callback)(VOID *buffer)) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_TRACE_BUFFER_FULL_NOTIFY_CALL, (ALIGN_TYPE) full_buffer_callback, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_trace_disable.c b/common_modules/module_lib/src/txm_trace_disable.c new file mode 100644 index 00000000..9e5ab99b --- /dev/null +++ b/common_modules/module_lib/src/txm_trace_disable.c @@ -0,0 +1,73 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_trace_disable PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function disables trace inside of ThreadX. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_trace_disable(VOID) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_TRACE_DISABLE_CALL, 0, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_trace_enable.c b/common_modules/module_lib/src/txm_trace_enable.c new file mode 100644 index 00000000..2e14265c --- /dev/null +++ b/common_modules/module_lib/src/txm_trace_enable.c @@ -0,0 +1,77 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_trace_enable PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes the ThreadX trace buffer and the */ +/* associated control variables, enabling it for operation. */ +/* */ +/* INPUT */ +/* */ +/* trace_buffer_start Start of trace buffer */ +/* trace_buffer_size Size (bytes) of trace buffer */ +/* registry_entries Number of object registry */ +/* entries. */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_trace_enable(VOID *trace_buffer_start, ULONG trace_buffer_size, ULONG registry_entries) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_TRACE_ENABLE_CALL, (ALIGN_TYPE) trace_buffer_start, (ALIGN_TYPE) trace_buffer_size, (ALIGN_TYPE) registry_entries); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_trace_event_filter.c b/common_modules/module_lib/src/txm_trace_event_filter.c new file mode 100644 index 00000000..dda12e36 --- /dev/null +++ b/common_modules/module_lib/src/txm_trace_event_filter.c @@ -0,0 +1,74 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_trace_event_filter PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets up the event filter, which allows the */ +/* application to filter various trace events during run-time. */ +/* */ +/* INPUT */ +/* */ +/* event_filter_bits Trace filter event bit(s) */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_trace_event_filter(ULONG event_filter_bits) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_TRACE_EVENT_FILTER_CALL, (ALIGN_TYPE) event_filter_bits, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_trace_event_unfilter.c b/common_modules/module_lib/src/txm_trace_event_unfilter.c new file mode 100644 index 00000000..fcff4a38 --- /dev/null +++ b/common_modules/module_lib/src/txm_trace_event_unfilter.c @@ -0,0 +1,74 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_trace_event_unfilter PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function removes the event filter, which allows the */ +/* application to un-filter various trace events during run-time. */ +/* */ +/* INPUT */ +/* */ +/* event_unfilter_bits Trace un-filter event bit(s) */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_trace_event_unfilter(ULONG event_unfilter_bits) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_TRACE_EVENT_UNFILTER_CALL, (ALIGN_TYPE) event_unfilter_bits, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_trace_interrupt_control.c b/common_modules/module_lib/src/txm_trace_interrupt_control.c new file mode 100644 index 00000000..76cb7ebb --- /dev/null +++ b/common_modules/module_lib/src/txm_trace_interrupt_control.c @@ -0,0 +1,74 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_trace_interrupt_control PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function provides a shell for the tx_interrupt_control */ +/* function so that a trace event can be logged for its use. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt posture */ +/* */ +/* OUTPUT */ +/* */ +/* Previous Interrupt Posture */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_trace_interrupt_control(UINT new_posture) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_TRACE_INTERRUPT_CONTROL_CALL, (ALIGN_TYPE) new_posture, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_lib/src/txm_trace_isr_enter_insert.c b/common_modules/module_lib/src/txm_trace_isr_enter_insert.c new file mode 100644 index 00000000..734aaa61 --- /dev/null +++ b/common_modules/module_lib/src/txm_trace_isr_enter_insert.c @@ -0,0 +1,70 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_trace_isr_enter_insert PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function provides inserts an ISR entry event into the trace */ +/* buffer. */ +/* */ +/* INPUT */ +/* */ +/* isr_id User defined ISR ID */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_trace_isr_enter_insert(ULONG isr_id) +{ + + + /* Call module manager dispatcher. */ + (_txm_module_kernel_call_dispatcher)(TXM_TRACE_ISR_ENTER_INSERT_CALL, (ALIGN_TYPE) isr_id, 0, 0); +} diff --git a/common_modules/module_lib/src/txm_trace_isr_exit_insert.c b/common_modules/module_lib/src/txm_trace_isr_exit_insert.c new file mode 100644 index 00000000..9d79c1e4 --- /dev/null +++ b/common_modules/module_lib/src/txm_trace_isr_exit_insert.c @@ -0,0 +1,70 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_trace_isr_exit_insert PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function provides inserts an ISR exit event into the trace */ +/* buffer. */ +/* */ +/* INPUT */ +/* */ +/* isr_id User defined ISR ID */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_trace_isr_exit_insert(ULONG isr_id) +{ + + + /* Call module manager dispatcher. */ + (_txm_module_kernel_call_dispatcher)(TXM_TRACE_ISR_EXIT_INSERT_CALL, (ALIGN_TYPE) isr_id, 0, 0); +} diff --git a/common_modules/module_lib/src/txm_trace_user_event_insert.c b/common_modules/module_lib/src/txm_trace_user_event_insert.c new file mode 100644 index 00000000..156d0b94 --- /dev/null +++ b/common_modules/module_lib/src/txm_trace_user_event_insert.c @@ -0,0 +1,82 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_trace_user_event_insert PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function inserts a user-defined event into the trace buffer. */ +/* */ +/* INPUT */ +/* */ +/* event_id User Event ID */ +/* info_field_1 First information field */ +/* info_field_2 First information field */ +/* info_field_3 First information field */ +/* info_field_4 First information field */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_trace_user_event_insert(ULONG event_id, ULONG info_field_1, ULONG info_field_2, ULONG info_field_3, ULONG info_field_4) +{ + +UINT return_value; +ALIGN_TYPE extra_parameters[3]; + + extra_parameters[0] = (ALIGN_TYPE) info_field_2; + extra_parameters[1] = (ALIGN_TYPE) info_field_3; + extra_parameters[2] = (ALIGN_TYPE) info_field_4; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_TRACE_USER_EVENT_INSERT_CALL, (ALIGN_TYPE) event_id, (ALIGN_TYPE) info_field_1, (ALIGN_TYPE) extra_parameters); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/common_modules/module_manager/inc/txm_module_manager_dispatch.h b/common_modules/module_manager/inc/txm_module_manager_dispatch.h new file mode 100644 index 00000000..42aa1bab --- /dev/null +++ b/common_modules/module_manager/inc/txm_module_manager_dispatch.h @@ -0,0 +1,3029 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* UINT _txe_block_allocate( + TX_BLOCK_POOL *pool_ptr, -> param_0 + VOID **block_ptr, -> param_1 + ULONG wait_option -> param_2 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_block_allocate_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_BLOCK_POOL))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(VOID *))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_block_allocate( + (TX_BLOCK_POOL *) param_0, + (VOID **) param_1, + (ULONG) param_2 + ); + return(return_value); +} + +/* UINT _txe_block_pool_create( + TX_BLOCK_POOL *pool_ptr, -> param_0 + CHAR *name_ptr, -> param_1 + ULONG block_size, -> extra_parameters[0] + VOID *pool_start, -> extra_parameters[1] + ULONG pool_size, -> extra_parameters[2] + UINT pool_control_block_size -> extra_parameters[3] + ); */ +static ALIGN_TYPE _txm_module_manager_tx_block_pool_create_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_CREATION(module_instance, param_0, sizeof(TX_BLOCK_POOL))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_DEREFERENCE_STRING(module_instance, param_1)) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[1], extra_parameters[2])) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_block_pool_create( + (TX_BLOCK_POOL *) param_0, + (CHAR *) param_1, + (ULONG) extra_parameters[0], + (VOID *) extra_parameters[1], + (ULONG) extra_parameters[2], + (UINT) extra_parameters[3] + ); + return(return_value); +} + +/* UINT _txe_block_pool_delete( + TX_BLOCK_POOL *pool_ptr -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_block_pool_delete_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_BLOCK_POOL))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_block_pool_delete( + (TX_BLOCK_POOL *) param_0 + ); + + /* Deallocate object memory. */ + if (return_value == TX_SUCCESS) + { + return_value = _txm_module_manager_object_deallocate((VOID *) param_0); + } + return(return_value); +} + +/* UINT _txe_block_pool_info_get( + TX_BLOCK_POOL *pool_ptr, -> param_0 + CHAR **name, -> param_1 + ULONG *available_blocks, -> extra_parameters[0] + ULONG *total_blocks, -> extra_parameters[1] + TX_THREAD **first_suspended, -> extra_parameters[2] + ULONG *suspended_count, -> extra_parameters[3] + TX_BLOCK_POOL **next_pool -> extra_parameters[4] + ); */ +static ALIGN_TYPE _txm_module_manager_tx_block_pool_info_get_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_BLOCK_POOL))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(CHAR *))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[1], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[2], sizeof(TX_THREAD *))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[3], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[4], sizeof(TX_BLOCK_POOL *))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_block_pool_info_get( + (TX_BLOCK_POOL *) param_0, + (CHAR **) param_1, + (ULONG *) extra_parameters[0], + (ULONG *) extra_parameters[1], + (TX_THREAD **) extra_parameters[2], + (ULONG *) extra_parameters[3], + (TX_BLOCK_POOL **) extra_parameters[4] + ); + return(return_value); +} + +/* UINT _tx_block_pool_performance_info_get( + TX_BLOCK_POOL *pool_ptr, -> param_0 + ULONG *allocates, -> param_1 + ULONG *releases, -> extra_parameters[0] + ULONG *suspensions, -> extra_parameters[1] + ULONG *timeouts -> extra_parameters[2] + ); */ +static ALIGN_TYPE _txm_module_manager_tx_block_pool_performance_info_get_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_BLOCK_POOL))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[1], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[2], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _tx_block_pool_performance_info_get( + (TX_BLOCK_POOL *) param_0, + (ULONG *) param_1, + (ULONG *) extra_parameters[0], + (ULONG *) extra_parameters[1], + (ULONG *) extra_parameters[2] + ); + return(return_value); +} + +/* UINT _tx_block_pool_performance_system_info_get( + ULONG *allocates, -> param_0 + ULONG *releases, -> param_1 + ULONG *suspensions, -> extra_parameters[0] + ULONG *timeouts -> extra_parameters[1] + ); */ +static ALIGN_TYPE _txm_module_manager_tx_block_pool_performance_system_info_get_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_0, sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[1], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _tx_block_pool_performance_system_info_get( + (ULONG *) param_0, + (ULONG *) param_1, + (ULONG *) extra_parameters[0], + (ULONG *) extra_parameters[1] + ); + return(return_value); +} + +/* UINT _txe_block_pool_prioritize( + TX_BLOCK_POOL *pool_ptr -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_block_pool_prioritize_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_BLOCK_POOL))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_block_pool_prioritize( + (TX_BLOCK_POOL *) param_0 + ); + return(return_value); +} + +/* UINT _txe_block_release( + VOID *block_ptr -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_block_release_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + +ALIGN_TYPE return_value; +ALIGN_TYPE block_header_start; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + /* Is the pointer non-null? */ + if ((void *) param_0 != TX_NULL) + { + + /* Calculate the beginning of the header info for this block (the header + consists of 1 pointers. */ + block_header_start = param_0 - sizeof(ALIGN_TYPE); + + if (/* Did we underflow when doing the subtract? */ + (block_header_start > param_0) || + /* Ensure the pointer is inside the module's data. Note that we only + check the pointer in the header because only that pointer is + dereferenced during the pointer's validity check in _tx_block_release. */ + (!TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, block_header_start, sizeof(ALIGN_TYPE)))) + { + + /* Invalid pointer. */ + return(TXM_MODULE_INVALID_MEMORY); + } + } + } + + return_value = (ALIGN_TYPE) _txe_block_release( + (VOID *) param_0 + ); + return(return_value); +} + +/* UINT _txe_byte_allocate( + TX_BYTE_POOL *pool_ptr, -> param_0 + VOID **memory_ptr, -> param_1 + ULONG memory_size, -> extra_parameters[0] + ULONG wait_option -> extra_parameters[1] + ); */ +static ALIGN_TYPE _txm_module_manager_tx_byte_allocate_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_BYTE_POOL))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(VOID *))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_byte_allocate( + (TX_BYTE_POOL *) param_0, + (VOID **) param_1, + (ULONG) extra_parameters[0], + (ULONG) extra_parameters[1] + ); + return(return_value); +} + +/* UINT _txe_byte_pool_create( + TX_BYTE_POOL *pool_ptr, -> param_0 + CHAR *name_ptr, -> param_1 + VOID *pool_start, -> extra_parameters[0] + ULONG pool_size, -> extra_parameters[1] + UINT pool_control_block_size -> extra_parameters[2] + ); */ +static ALIGN_TYPE _txm_module_manager_tx_byte_pool_create_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_CREATION(module_instance, param_0, sizeof(TX_BYTE_POOL))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_DEREFERENCE_STRING(module_instance, param_1)) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], extra_parameters[1])) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_byte_pool_create( + (TX_BYTE_POOL *) param_0, + (CHAR *) param_1, + (VOID *) extra_parameters[0], + (ULONG) extra_parameters[1], + (UINT) extra_parameters[2] + ); + return(return_value); +} + +/* UINT _txe_byte_pool_delete( + TX_BYTE_POOL *pool_ptr -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_byte_pool_delete_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_BYTE_POOL))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_byte_pool_delete( + (TX_BYTE_POOL *) param_0 + ); + + /* Deallocate object memory. */ + if (return_value == TX_SUCCESS) + { + return_value = _txm_module_manager_object_deallocate((VOID *) param_0); + } + return(return_value); +} + +/* UINT _txe_byte_pool_info_get( + TX_BYTE_POOL *pool_ptr, -> param_0 + CHAR **name, -> param_1 + ULONG *available_bytes, -> extra_parameters[0] + ULONG *fragments, -> extra_parameters[1] + TX_THREAD **first_suspended, -> extra_parameters[2] + ULONG *suspended_count, -> extra_parameters[3] + TX_BYTE_POOL **next_pool -> extra_parameters[4] + ); */ +static ALIGN_TYPE _txm_module_manager_tx_byte_pool_info_get_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_BYTE_POOL))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(CHAR *))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[1], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[2], sizeof(TX_THREAD *))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[3], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[4], sizeof(TX_BYTE_POOL *))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_byte_pool_info_get( + (TX_BYTE_POOL *) param_0, + (CHAR **) param_1, + (ULONG *) extra_parameters[0], + (ULONG *) extra_parameters[1], + (TX_THREAD **) extra_parameters[2], + (ULONG *) extra_parameters[3], + (TX_BYTE_POOL **) extra_parameters[4] + ); + return(return_value); +} + +/* UINT _tx_byte_pool_performance_info_get( + TX_BYTE_POOL *pool_ptr, -> param_0 + ULONG *allocates, -> param_1 + ULONG *releases, -> extra_parameters[0] + ULONG *fragments_searched, -> extra_parameters[1] + ULONG *merges, -> extra_parameters[2] + ULONG *splits, -> extra_parameters[3] + ULONG *suspensions, -> extra_parameters[4] + ULONG *timeouts -> extra_parameters[5] + ); */ +static ALIGN_TYPE _txm_module_manager_tx_byte_pool_performance_info_get_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_BYTE_POOL))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[1], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[2], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[3], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[4], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[5], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _tx_byte_pool_performance_info_get( + (TX_BYTE_POOL *) param_0, + (ULONG *) param_1, + (ULONG *) extra_parameters[0], + (ULONG *) extra_parameters[1], + (ULONG *) extra_parameters[2], + (ULONG *) extra_parameters[3], + (ULONG *) extra_parameters[4], + (ULONG *) extra_parameters[5] + ); + return(return_value); +} + +/* UINT _tx_byte_pool_performance_system_info_get( + ULONG *allocates, -> param_0 + ULONG *releases, -> param_1 + ULONG *fragments_searched, -> extra_parameters[0] + ULONG *merges, -> extra_parameters[1] + ULONG *splits, -> extra_parameters[2] + ULONG *suspensions, -> extra_parameters[3] + ULONG *timeouts -> extra_parameters[4] + ); */ +static ALIGN_TYPE _txm_module_manager_tx_byte_pool_performance_system_info_get_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_0, sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[1], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[2], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[3], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[4], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _tx_byte_pool_performance_system_info_get( + (ULONG *) param_0, + (ULONG *) param_1, + (ULONG *) extra_parameters[0], + (ULONG *) extra_parameters[1], + (ULONG *) extra_parameters[2], + (ULONG *) extra_parameters[3], + (ULONG *) extra_parameters[4] + ); + return(return_value); +} + +/* UINT _txe_byte_pool_prioritize( + TX_BYTE_POOL *pool_ptr -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_byte_pool_prioritize_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_BYTE_POOL))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_byte_pool_prioritize( + (TX_BYTE_POOL *) param_0 + ); + return(return_value); +} + +/* UINT _txe_byte_release( + VOID *memory_ptr -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_byte_release_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + +ALIGN_TYPE return_value; +ALIGN_TYPE block_header_start; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + /* Is the pointer non-null? */ + if ((void *) param_0 != TX_NULL) + { + + /* Calculate the beginning of the header info for this block (the header + consists of 2 pointers). */ + block_header_start = param_0 - 2*sizeof(ALIGN_TYPE); + + if (/* Did we underflow when doing the subtract? */ + (block_header_start > param_0) || + /* Ensure the pointer is inside the module's data. Note that we only + check the pointers in the header because only those two are + dereferenced during the pointer's validity check in _tx_byte_release. */ + (!TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, block_header_start, 2*sizeof(ALIGN_TYPE)))) + { + + /* Invalid pointer. */ + return(TXM_MODULE_INVALID_MEMORY); + } + } + } + + return_value = (ALIGN_TYPE) _txe_byte_release( + (VOID *) param_0 + ); + return(return_value); +} + +/* UINT _txe_event_flags_create( + TX_EVENT_FLAGS_GROUP *group_ptr, -> param_0 + CHAR *name_ptr, -> param_1 + UINT event_control_block_size -> param_2 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_event_flags_create_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_CREATION(module_instance, param_0, sizeof(TX_EVENT_FLAGS_GROUP))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_DEREFERENCE_STRING(module_instance, param_1)) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_event_flags_create( + (TX_EVENT_FLAGS_GROUP *) param_0, + (CHAR *) param_1, + (UINT) param_2 + ); + return(return_value); +} + +/* UINT _txe_event_flags_delete( + TX_EVENT_FLAGS_GROUP *group_ptr -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_event_flags_delete_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_EVENT_FLAGS_GROUP))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_event_flags_delete( + (TX_EVENT_FLAGS_GROUP *) param_0 + ); + + /* Deallocate object memory. */ + if (return_value == TX_SUCCESS) + { + return_value = _txm_module_manager_object_deallocate((VOID *) param_0); + } + return(return_value); +} + +/* UINT _txe_event_flags_get( + TX_EVENT_FLAGS_GROUP *group_ptr, -> param_0 + ULONG requested_flags, -> param_1 + UINT get_option, -> extra_parameters[0] + ULONG *actual_flags_ptr, -> extra_parameters[1] + ULONG wait_option -> extra_parameters[2] + ); */ +static ALIGN_TYPE _txm_module_manager_tx_event_flags_get_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_EVENT_FLAGS_GROUP))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[1], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_event_flags_get( + (TX_EVENT_FLAGS_GROUP *) param_0, + (ULONG) param_1, + (UINT) extra_parameters[0], + (ULONG *) extra_parameters[1], + (ULONG) extra_parameters[2] + ); + return(return_value); +} + +/* UINT _txe_event_flags_info_get( + TX_EVENT_FLAGS_GROUP *group_ptr, -> param_0 + CHAR **name, -> param_1 + ULONG *current_flags, -> extra_parameters[0] + TX_THREAD **first_suspended, -> extra_parameters[1] + ULONG *suspended_count, -> extra_parameters[2] + TX_EVENT_FLAGS_GROUP **next_group -> extra_parameters[3] + ); */ +static ALIGN_TYPE _txm_module_manager_tx_event_flags_info_get_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_EVENT_FLAGS_GROUP))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(CHAR *))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[1], sizeof(TX_THREAD *))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[2], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[3], sizeof(TX_EVENT_FLAGS_GROUP *))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_event_flags_info_get( + (TX_EVENT_FLAGS_GROUP *) param_0, + (CHAR **) param_1, + (ULONG *) extra_parameters[0], + (TX_THREAD **) extra_parameters[1], + (ULONG *) extra_parameters[2], + (TX_EVENT_FLAGS_GROUP **) extra_parameters[3] + ); + return(return_value); +} + +/* UINT _tx_event_flags_performance_info_get( + TX_EVENT_FLAGS_GROUP *group_ptr, -> param_0 + ULONG *sets, -> param_1 + ULONG *gets, -> extra_parameters[0] + ULONG *suspensions, -> extra_parameters[1] + ULONG *timeouts -> extra_parameters[2] + ); */ +static ALIGN_TYPE _txm_module_manager_tx_event_flags_performance_info_get_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_EVENT_FLAGS_GROUP))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[1], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[2], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _tx_event_flags_performance_info_get( + (TX_EVENT_FLAGS_GROUP *) param_0, + (ULONG *) param_1, + (ULONG *) extra_parameters[0], + (ULONG *) extra_parameters[1], + (ULONG *) extra_parameters[2] + ); + return(return_value); +} + +/* UINT _tx_event_flags_performance_system_info_get( + ULONG *sets, -> param_0 + ULONG *gets, -> param_1 + ULONG *suspensions, -> extra_parameters[0] + ULONG *timeouts -> extra_parameters[1] + ); */ +static ALIGN_TYPE _txm_module_manager_tx_event_flags_performance_system_info_get_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_0, sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[1], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _tx_event_flags_performance_system_info_get( + (ULONG *) param_0, + (ULONG *) param_1, + (ULONG *) extra_parameters[0], + (ULONG *) extra_parameters[1] + ); + return(return_value); +} + +/* UINT _txe_event_flags_set( + TX_EVENT_FLAGS_GROUP *group_ptr, -> param_0 + ULONG flags_to_set, -> param_1 + UINT set_option -> param_2 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_event_flags_set_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_EVENT_FLAGS_GROUP))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_event_flags_set( + (TX_EVENT_FLAGS_GROUP *) param_0, + (ULONG) param_1, + (UINT) param_2 + ); + return(return_value); +} + +/* UINT _txe_event_flags_set_notify( + TX_EVENT_FLAGS_GROUP *group_ptr, -> param_0 + VOID (*events_set_notify)(TX_EVENT_FLAGS_GROUP *) -> param_1 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_event_flags_set_notify_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1) +{ + +ALIGN_TYPE return_value; +TX_EVENT_FLAGS_GROUP *event_flags_ptr = (TX_EVENT_FLAGS_GROUP *)param_0; +VOID (*events_set_notify)(TX_EVENT_FLAGS_GROUP *); + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_EVENT_FLAGS_GROUP))) + return(TXM_MODULE_INVALID_MEMORY); + + /* Since we need to write to the object, ensure it's valid. */ + if ((event_flags_ptr == TX_NULL) || (event_flags_ptr -> tx_event_flags_group_id != TX_EVENT_FLAGS_ID)) + return(TX_GROUP_ERROR); + } + + /* Is it a disable request? */ + if ((void *) param_1 == TX_NULL) + { + + /* Clear the callback. */ + events_set_notify = (VOID (*)(TX_EVENT_FLAGS_GROUP *)) TX_NULL; + } + else + { + + /* Setup trampoline values. */ + event_flags_ptr -> tx_event_flags_group_module_instance = (VOID *) module_instance; + event_flags_ptr -> tx_event_flags_group_set_module_notify = (VOID (*)(TX_EVENT_FLAGS_GROUP *)) param_1; + events_set_notify = _txm_module_manager_event_flags_notify_trampoline; + } + + return_value = (ALIGN_TYPE) _txe_event_flags_set_notify( + (TX_EVENT_FLAGS_GROUP *) param_0, + (VOID (*)(TX_EVENT_FLAGS_GROUP *)) events_set_notify + ); + return(return_value); +} + +/* UINT _txe_mutex_create( + TX_MUTEX *mutex_ptr, -> param_0 + CHAR *name_ptr, -> param_1 + UINT inherit, -> extra_parameters[0] + UINT mutex_control_block_size -> extra_parameters[1] + ); */ +static ALIGN_TYPE _txm_module_manager_tx_mutex_create_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_CREATION(module_instance, param_0, sizeof(TX_MUTEX))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_DEREFERENCE_STRING(module_instance, param_1)) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_mutex_create( + (TX_MUTEX *) param_0, + (CHAR *) param_1, + (UINT) extra_parameters[0], + (UINT) extra_parameters[1] + ); + return(return_value); +} + +/* UINT _txe_mutex_delete( + TX_MUTEX *mutex_ptr -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_mutex_delete_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_MUTEX))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_mutex_delete( + (TX_MUTEX *) param_0 + ); + + /* Deallocate object memory. */ + if (return_value == TX_SUCCESS) + { + return_value = _txm_module_manager_object_deallocate((VOID *) param_0); + } + return(return_value); +} + +/* UINT _txe_mutex_get( + TX_MUTEX *mutex_ptr, -> param_0 + ULONG wait_option -> param_1 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_mutex_get_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_MUTEX))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_mutex_get( + (TX_MUTEX *) param_0, + (ULONG) param_1 + ); + return(return_value); +} + +/* UINT _txe_mutex_info_get( + TX_MUTEX *mutex_ptr, -> param_0 + CHAR **name, -> param_1 + ULONG *count, -> extra_parameters[0] + TX_THREAD **owner, -> extra_parameters[1] + TX_THREAD **first_suspended, -> extra_parameters[2] + ULONG *suspended_count, -> extra_parameters[3] + TX_MUTEX **next_mutex -> extra_parameters[4] + ); */ +static ALIGN_TYPE _txm_module_manager_tx_mutex_info_get_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_MUTEX))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(CHAR *))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[1], sizeof(TX_THREAD *))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[2], sizeof(TX_THREAD *))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[3], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[4], sizeof(TX_MUTEX *))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_mutex_info_get( + (TX_MUTEX *) param_0, + (CHAR **) param_1, + (ULONG *) extra_parameters[0], + (TX_THREAD **) extra_parameters[1], + (TX_THREAD **) extra_parameters[2], + (ULONG *) extra_parameters[3], + (TX_MUTEX **) extra_parameters[4] + ); + return(return_value); +} + +/* UINT _tx_mutex_performance_info_get( + TX_MUTEX *mutex_ptr, -> param_0 + ULONG *puts, -> param_1 + ULONG *gets, -> extra_parameters[0] + ULONG *suspensions, -> extra_parameters[1] + ULONG *timeouts, -> extra_parameters[2] + ULONG *inversions, -> extra_parameters[3] + ULONG *inheritances -> extra_parameters[4] + ); */ +static ALIGN_TYPE _txm_module_manager_tx_mutex_performance_info_get_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_MUTEX))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[1], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[2], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[3], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[4], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _tx_mutex_performance_info_get( + (TX_MUTEX *) param_0, + (ULONG *) param_1, + (ULONG *) extra_parameters[0], + (ULONG *) extra_parameters[1], + (ULONG *) extra_parameters[2], + (ULONG *) extra_parameters[3], + (ULONG *) extra_parameters[4] + ); + return(return_value); +} + +/* UINT _tx_mutex_performance_system_info_get( + ULONG *puts, -> param_0 + ULONG *gets, -> param_1 + ULONG *suspensions, -> extra_parameters[0] + ULONG *timeouts, -> extra_parameters[1] + ULONG *inversions, -> extra_parameters[2] + ULONG *inheritances -> extra_parameters[3] + ); */ +static ALIGN_TYPE _txm_module_manager_tx_mutex_performance_system_info_get_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_0, sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[1], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[2], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[3], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _tx_mutex_performance_system_info_get( + (ULONG *) param_0, + (ULONG *) param_1, + (ULONG *) extra_parameters[0], + (ULONG *) extra_parameters[1], + (ULONG *) extra_parameters[2], + (ULONG *) extra_parameters[3] + ); + return(return_value); +} + +/* UINT _txe_mutex_prioritize( + TX_MUTEX *mutex_ptr -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_mutex_prioritize_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_MUTEX))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_mutex_prioritize( + (TX_MUTEX *) param_0 + ); + return(return_value); +} + +/* UINT _txe_mutex_put( + TX_MUTEX *mutex_ptr -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_mutex_put_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_MUTEX))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_mutex_put( + (TX_MUTEX *) param_0 + ); + return(return_value); +} + +/* UINT _txe_queue_create( + TX_QUEUE *queue_ptr, -> param_0 + CHAR *name_ptr, -> param_1 + UINT message_size, -> extra_parameters[0] + VOID *queue_start, -> extra_parameters[1] + ULONG queue_size, -> extra_parameters[2] + UINT queue_control_block_size -> extra_parameters[3] + ); */ +static ALIGN_TYPE _txm_module_manager_tx_queue_create_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_CREATION(module_instance, param_0, sizeof(TX_QUEUE))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_DEREFERENCE_STRING(module_instance, param_1)) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[1], extra_parameters[2])) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_queue_create( + (TX_QUEUE *) param_0, + (CHAR *) param_1, + (UINT) extra_parameters[0], + (VOID *) extra_parameters[1], + (ULONG) extra_parameters[2], + (UINT) extra_parameters[3] + ); + return(return_value); +} + +/* UINT _txe_queue_delete( + TX_QUEUE *queue_ptr -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_queue_delete_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_QUEUE))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_queue_delete( + (TX_QUEUE *) param_0 + ); + + /* Deallocate object memory. */ + if (return_value == TX_SUCCESS) + { + return_value = _txm_module_manager_object_deallocate((VOID *) param_0); + } + return(return_value); +} + +/* UINT _txe_queue_flush( + TX_QUEUE *queue_ptr -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_queue_flush_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_QUEUE))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_queue_flush( + (TX_QUEUE *) param_0 + ); + return(return_value); +} + +/* UINT _txe_queue_front_send( + TX_QUEUE *queue_ptr, -> param_0 + VOID *source_ptr, -> param_1 + ULONG wait_option -> param_2 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_queue_front_send_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) +{ + +ALIGN_TYPE return_value; +TX_QUEUE *queue_ptr; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_QUEUE))) + return(TXM_MODULE_INVALID_MEMORY); + + /* We need to get the size of the message from the queue. */ + queue_ptr = (TX_QUEUE *) param_0; + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_READ(module_instance, param_1, queue_ptr -> tx_queue_message_size)) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_queue_front_send( + (TX_QUEUE *) param_0, + (VOID *) param_1, + (ULONG) param_2 + ); + return(return_value); +} + +/* UINT _txe_queue_info_get( + TX_QUEUE *queue_ptr, -> param_0 + CHAR **name, -> param_1 + ULONG *enqueued, -> extra_parameters[0] + ULONG *available_storage, -> extra_parameters[1] + TX_THREAD **first_suspended, -> extra_parameters[2] + ULONG *suspended_count, -> extra_parameters[3] + TX_QUEUE **next_queue -> extra_parameters[4] + ); */ +static ALIGN_TYPE _txm_module_manager_tx_queue_info_get_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_QUEUE))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(CHAR *))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[1], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[2], sizeof(TX_THREAD *))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[3], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[4], sizeof(TX_QUEUE *))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_queue_info_get( + (TX_QUEUE *) param_0, + (CHAR **) param_1, + (ULONG *) extra_parameters[0], + (ULONG *) extra_parameters[1], + (TX_THREAD **) extra_parameters[2], + (ULONG *) extra_parameters[3], + (TX_QUEUE **) extra_parameters[4] + ); + return(return_value); +} + +/* UINT _tx_queue_performance_info_get( + TX_QUEUE *queue_ptr, -> param_0 + ULONG *messages_sent, -> param_1 + ULONG *messages_received, -> extra_parameters[0] + ULONG *empty_suspensions, -> extra_parameters[1] + ULONG *full_suspensions, -> extra_parameters[2] + ULONG *full_errors, -> extra_parameters[3] + ULONG *timeouts -> extra_parameters[4] + ); */ +static ALIGN_TYPE _txm_module_manager_tx_queue_performance_info_get_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_QUEUE))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[1], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[2], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[3], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[4], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _tx_queue_performance_info_get( + (TX_QUEUE *) param_0, + (ULONG *) param_1, + (ULONG *) extra_parameters[0], + (ULONG *) extra_parameters[1], + (ULONG *) extra_parameters[2], + (ULONG *) extra_parameters[3], + (ULONG *) extra_parameters[4] + ); + return(return_value); +} + +/* UINT _tx_queue_performance_system_info_get( + ULONG *messages_sent, -> param_0 + ULONG *messages_received, -> param_1 + ULONG *empty_suspensions, -> extra_parameters[0] + ULONG *full_suspensions, -> extra_parameters[1] + ULONG *full_errors, -> extra_parameters[2] + ULONG *timeouts -> extra_parameters[3] + ); */ +static ALIGN_TYPE _txm_module_manager_tx_queue_performance_system_info_get_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_0, sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[1], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[2], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[3], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _tx_queue_performance_system_info_get( + (ULONG *) param_0, + (ULONG *) param_1, + (ULONG *) extra_parameters[0], + (ULONG *) extra_parameters[1], + (ULONG *) extra_parameters[2], + (ULONG *) extra_parameters[3] + ); + return(return_value); +} + +/* UINT _txe_queue_prioritize( + TX_QUEUE *queue_ptr -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_queue_prioritize_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_QUEUE))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_queue_prioritize( + (TX_QUEUE *) param_0 + ); + return(return_value); +} + +/* UINT _txe_queue_receive( + TX_QUEUE *queue_ptr, -> param_0 + VOID *destination_ptr, -> param_1 + ULONG wait_option -> param_2 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_queue_receive_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) +{ + +ALIGN_TYPE return_value; +TX_QUEUE *queue_ptr; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_QUEUE))) + return(TXM_MODULE_INVALID_MEMORY); + + /* We need to get the max size of the buffer from the queue. */ + queue_ptr = (TX_QUEUE *) param_0; + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(ULONG)*queue_ptr -> tx_queue_message_size)) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_queue_receive( + (TX_QUEUE *) param_0, + (VOID *) param_1, + (ULONG) param_2 + ); + return(return_value); +} + +/* UINT _txe_queue_send( + TX_QUEUE *queue_ptr, -> param_0 + VOID *source_ptr, -> param_1 + ULONG wait_option -> param_2 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_queue_send_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) +{ + +ALIGN_TYPE return_value; +TX_QUEUE *queue_ptr; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_QUEUE))) + return(TXM_MODULE_INVALID_MEMORY); + + /* We need to get the size of the message from the queue. */ + queue_ptr = (TX_QUEUE *) param_0; + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_READ(module_instance, param_1, sizeof(ULONG)*queue_ptr -> tx_queue_message_size)) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_queue_send( + (TX_QUEUE *) param_0, + (VOID *) param_1, + (ULONG) param_2 + ); + return(return_value); +} + +/* UINT _txe_queue_send_notify( + TX_QUEUE *queue_ptr, -> param_0 + VOID (*queue_send_notify)(TX_QUEUE *notify_queue_ptr) -> param_1 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_queue_send_notify_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1) +{ + +ALIGN_TYPE return_value; +TX_QUEUE *queue_ptr = (TX_QUEUE *) param_0; +VOID (*queue_send_notify)(TX_QUEUE *); + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_QUEUE))) + return(TXM_MODULE_INVALID_MEMORY); + + /* Since we need to write to the object, ensure it's valid. */ + if ((queue_ptr == TX_NULL) || (queue_ptr -> tx_queue_id != TX_QUEUE_ID)) + return(TX_QUEUE_ERROR); + } + + /* Is it a disable request? */ + if ((void *) param_1 == TX_NULL) + { + + /* Clear the callback. */ + queue_send_notify = (VOID (*)(TX_QUEUE *)) TX_NULL; + } + else + { + + /* Setup trampoline values. */ + queue_ptr -> tx_queue_module_instance = (VOID *) module_instance; + queue_ptr -> tx_queue_send_module_notify = (VOID (*)(TX_QUEUE *)) param_1; + queue_send_notify = _txm_module_manager_queue_notify_trampoline; + } + + return_value = (ALIGN_TYPE) _txe_queue_send_notify( + (TX_QUEUE *) param_0, + (VOID (*)(TX_QUEUE *notify_queue_ptr)) queue_send_notify + ); + return(return_value); +} + +/* UINT _txe_semaphore_ceiling_put( + TX_SEMAPHORE *semaphore_ptr, -> param_0 + ULONG ceiling -> param_1 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_semaphore_ceiling_put_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_SEMAPHORE))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_semaphore_ceiling_put( + (TX_SEMAPHORE *) param_0, + (ULONG) param_1 + ); + return(return_value); +} + +/* UINT _txe_semaphore_create( + TX_SEMAPHORE *semaphore_ptr, -> param_0 + CHAR *name_ptr, -> param_1 + ULONG initial_count, -> extra_parameters[0] + UINT semaphore_control_block_size -> extra_parameters[1] + ); */ +static ALIGN_TYPE _txm_module_manager_tx_semaphore_create_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_CREATION(module_instance, param_0, sizeof(TX_SEMAPHORE))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_DEREFERENCE_STRING(module_instance, param_1)) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_semaphore_create( + (TX_SEMAPHORE *) param_0, + (CHAR *) param_1, + (ULONG) extra_parameters[0], + (UINT) extra_parameters[1] + ); + return(return_value); +} + +/* UINT _txe_semaphore_delete( + TX_SEMAPHORE *semaphore_ptr -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_semaphore_delete_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_SEMAPHORE))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_semaphore_delete( + (TX_SEMAPHORE *) param_0 + ); + + /* Deallocate object memory. */ + if (return_value == TX_SUCCESS) + { + return_value = _txm_module_manager_object_deallocate((VOID *) param_0); + } + return(return_value); +} + +/* UINT _txe_semaphore_get( + TX_SEMAPHORE *semaphore_ptr, -> param_0 + ULONG wait_option -> param_1 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_semaphore_get_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_SEMAPHORE))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_semaphore_get( + (TX_SEMAPHORE *) param_0, + (ULONG) param_1 + ); + return(return_value); +} + +/* UINT _txe_semaphore_info_get( + TX_SEMAPHORE *semaphore_ptr, -> param_0 + CHAR **name, -> param_1 + ULONG *current_value, -> extra_parameters[0] + TX_THREAD **first_suspended, -> extra_parameters[1] + ULONG *suspended_count, -> extra_parameters[2] + TX_SEMAPHORE **next_semaphore -> extra_parameters[3] + ); */ +static ALIGN_TYPE _txm_module_manager_tx_semaphore_info_get_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_SEMAPHORE))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(CHAR *))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[1], sizeof(TX_THREAD *))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[2], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[3], sizeof(TX_SEMAPHORE *))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_semaphore_info_get( + (TX_SEMAPHORE *) param_0, + (CHAR **) param_1, + (ULONG *) extra_parameters[0], + (TX_THREAD **) extra_parameters[1], + (ULONG *) extra_parameters[2], + (TX_SEMAPHORE **) extra_parameters[3] + ); + return(return_value); +} + +/* UINT _tx_semaphore_performance_info_get( + TX_SEMAPHORE *semaphore_ptr, -> param_0 + ULONG *puts, -> param_1 + ULONG *gets, -> extra_parameters[0] + ULONG *suspensions, -> extra_parameters[1] + ULONG *timeouts -> extra_parameters[2] + ); */ +static ALIGN_TYPE _txm_module_manager_tx_semaphore_performance_info_get_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_SEMAPHORE))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[1], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[2], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _tx_semaphore_performance_info_get( + (TX_SEMAPHORE *) param_0, + (ULONG *) param_1, + (ULONG *) extra_parameters[0], + (ULONG *) extra_parameters[1], + (ULONG *) extra_parameters[2] + ); + return(return_value); +} + +/* UINT _tx_semaphore_performance_system_info_get( + ULONG *puts, -> param_0 + ULONG *gets, -> param_1 + ULONG *suspensions, -> extra_parameters[0] + ULONG *timeouts -> extra_parameters[1] + ); */ +static ALIGN_TYPE _txm_module_manager_tx_semaphore_performance_system_info_get_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_0, sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[1], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _tx_semaphore_performance_system_info_get( + (ULONG *) param_0, + (ULONG *) param_1, + (ULONG *) extra_parameters[0], + (ULONG *) extra_parameters[1] + ); + return(return_value); +} + +/* UINT _txe_semaphore_prioritize( + TX_SEMAPHORE *semaphore_ptr -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_semaphore_prioritize_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_SEMAPHORE))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_semaphore_prioritize( + (TX_SEMAPHORE *) param_0 + ); + return(return_value); +} + +/* UINT _txe_semaphore_put( + TX_SEMAPHORE *semaphore_ptr -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_semaphore_put_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_SEMAPHORE))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_semaphore_put( + (TX_SEMAPHORE *) param_0 + ); + return(return_value); +} + +/* UINT _txe_semaphore_put_notify( + TX_SEMAPHORE *semaphore_ptr, -> param_0 + VOID (*semaphore_put_notify)(TX_SEMAPHORE *notify_semaphore_ptr) -> param_1 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_semaphore_put_notify_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1) +{ + +ALIGN_TYPE return_value; +TX_SEMAPHORE *semaphore_ptr = (TX_SEMAPHORE *) param_0; +VOID (*semaphore_put_notify)(TX_SEMAPHORE *); + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_SEMAPHORE))) + return(TXM_MODULE_INVALID_MEMORY); + + /* Since we need to write to the object, ensure it's valid. */ + if ((semaphore_ptr == TX_NULL) || (semaphore_ptr -> tx_semaphore_id != TX_SEMAPHORE_ID)) + return(TX_SEMAPHORE_ERROR); + } + + /* Is it a disable request? */ + if ((void *) param_1 == TX_NULL) + { + + /* Clear the callback. */ + semaphore_put_notify = (VOID (*)(TX_SEMAPHORE *)) TX_NULL; + } + else + { + + /* Setup trampoline values. */ + semaphore_ptr -> tx_semaphore_module_instance = (VOID *) module_instance; + semaphore_ptr -> tx_semaphore_put_module_notify = (VOID (*)(TX_SEMAPHORE *)) param_1; + semaphore_put_notify = _txm_module_manager_semaphore_notify_trampoline; + } + + return_value = (ALIGN_TYPE) _txe_semaphore_put_notify( + (TX_SEMAPHORE *) param_0, + (VOID (*)(TX_SEMAPHORE *notify_semaphore_ptr)) semaphore_put_notify + ); + return(return_value); +} + +/* UINT _txe_thread_create( + TX_THREAD *thread_ptr, -> param_0 + CHAR *name_ptr, -> param_1 + VOID (*entry_function)(ULONG entry_input), -> extra_parameters[0] + ULONG entry_input, -> extra_parameters[1] + VOID *stack_start, -> extra_parameters[2] + ULONG stack_size, -> extra_parameters[3] + UINT priority, -> extra_parameters[4] + UINT preempt_threshold, -> extra_parameters[5] + ULONG time_slice, -> extra_parameters[6] + UINT auto_start, -> extra_parameters[7] + UINT thread_control_block_size -> extra_parameters[8] + ); */ +static ALIGN_TYPE _txm_module_manager_tx_thread_create_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_CREATION(module_instance, param_0, sizeof(TX_THREAD))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_DEREFERENCE_STRING(module_instance, param_1)) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[2], extra_parameters[3])) + return(TXM_MODULE_INVALID_MEMORY); + + if (extra_parameters[4] < module_instance -> txm_module_instance_maximum_priority) + return(TX_PRIORITY_ERROR); + + if (extra_parameters[5] < module_instance -> txm_module_instance_maximum_priority) + return(TX_THRESH_ERROR); + } + + return_value = (ALIGN_TYPE) _txm_module_manager_thread_create( + (TX_THREAD *) param_0, + (CHAR *) param_1, + module_instance -> txm_module_instance_shell_entry_function, + (VOID (*)(ULONG entry_input)) extra_parameters[0], + (ULONG) extra_parameters[1], + (VOID *) extra_parameters[2], + (ULONG) extra_parameters[3], + (UINT) extra_parameters[4], + (UINT) extra_parameters[5], + (ULONG) extra_parameters[6], + (UINT) extra_parameters[7], + (UINT) extra_parameters[8], + module_instance + ); + return(return_value); +} + +/* UINT _txe_thread_delete( + TX_THREAD *thread_ptr -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_thread_delete_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_THREAD))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_thread_delete( + (TX_THREAD *) param_0 + ); + + /* Deallocate object memory. */ + if (return_value == TX_SUCCESS) + { + return_value = _txm_module_manager_object_deallocate((VOID *) param_0); + } + return(return_value); +} + +/* UINT _txe_thread_entry_exit_notify( + TX_THREAD *thread_ptr, -> param_0 + VOID (*thread_entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT type) -> param_1 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_thread_entry_exit_notify_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1) +{ + +ALIGN_TYPE return_value; +TX_THREAD *thread_ptr = (TX_THREAD *) param_0; +TXM_MODULE_THREAD_ENTRY_INFO *thread_entry_info_ptr; +VOID (*thread_entry_exit_notify)(TX_THREAD *, UINT); + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_THREAD))) + return(TXM_MODULE_INVALID_MEMORY); + + /* Since we need to write to the object, ensure it's valid. */ + if ((thread_ptr == TX_NULL) || (thread_ptr -> tx_thread_id != TX_THREAD_ID)) + return(TX_THREAD_ERROR); + + /* Ensure this thread is from the module trying to set the callback. */ + if (thread_ptr -> tx_thread_module_instance_ptr != module_instance) + return(TXM_MODULE_INVALID); + } + + /* Is it a disable request? */ + if ((void *) param_1 == TX_NULL) + { + + /* Clear the callback. */ + thread_entry_exit_notify = (VOID (*)(TX_THREAD *, UINT)) TX_NULL; + } + else + { + + /* Setup trampoline values. */ + thread_entry_info_ptr = (TXM_MODULE_THREAD_ENTRY_INFO *) thread_ptr -> tx_thread_module_entry_info_ptr; + thread_entry_info_ptr -> txm_module_thread_entry_info_exit_notify = (VOID (*)(TX_THREAD *, UINT)) param_1; + thread_entry_exit_notify = _txm_module_manager_thread_notify_trampoline; + } + + return_value = (ALIGN_TYPE) _txe_thread_entry_exit_notify( + (TX_THREAD *) param_0, + (VOID (*)(TX_THREAD *notify_thread_ptr, UINT type)) thread_entry_exit_notify + ); + return(return_value); +} + +/* TX_THREAD *_tx_thread_identify(); */ +static ALIGN_TYPE _txm_module_manager_tx_thread_identify_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + +ALIGN_TYPE return_value; + + return_value = (ALIGN_TYPE) _tx_thread_identify(); + return(return_value); +} + +/* UINT _txe_thread_info_get( + TX_THREAD *thread_ptr, -> param_0 + CHAR **name, -> param_1 + UINT *state, -> extra_parameters[0] + ULONG *run_count, -> extra_parameters[1] + UINT *priority, -> extra_parameters[2] + UINT *preemption_threshold, -> extra_parameters[3] + ULONG *time_slice, -> extra_parameters[4] + TX_THREAD **next_thread, -> extra_parameters[5] + TX_THREAD **next_suspended_thread -> extra_parameters[6] + ); */ +static ALIGN_TYPE _txm_module_manager_tx_thread_info_get_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_THREAD))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(CHAR *))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(UINT))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[1], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[2], sizeof(UINT))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[3], sizeof(UINT))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[4], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[5], sizeof(TX_THREAD *))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[6], sizeof(TX_THREAD *))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_thread_info_get( + (TX_THREAD *) param_0, + (CHAR **) param_1, + (UINT *) extra_parameters[0], + (ULONG *) extra_parameters[1], + (UINT *) extra_parameters[2], + (UINT *) extra_parameters[3], + (ULONG *) extra_parameters[4], + (TX_THREAD **) extra_parameters[5], + (TX_THREAD **) extra_parameters[6] + ); + return(return_value); +} + +/* UINT _tx_thread_interrupt_control( + UINT new_posture -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_thread_interrupt_control_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE) + return(TXM_MODULE_INVALID_PROPERTIES); + + return_value = (ALIGN_TYPE) _tx_thread_interrupt_control( + (UINT) param_0 + ); + return(return_value); +} + +/* UINT _tx_thread_performance_info_get( + TX_THREAD *thread_ptr, -> param_0 + ULONG *resumptions, -> param_1 + ULONG *suspensions, -> extra_parameters[0] + ULONG *solicited_preemptions, -> extra_parameters[1] + ULONG *interrupt_preemptions, -> extra_parameters[2] + ULONG *priority_inversions, -> extra_parameters[3] + ULONG *time_slices, -> extra_parameters[4] + ULONG *relinquishes, -> extra_parameters[5] + ULONG *timeouts, -> extra_parameters[6] + ULONG *wait_aborts, -> extra_parameters[7] + TX_THREAD **last_preempted_by -> extra_parameters[8] + ); */ +static ALIGN_TYPE _txm_module_manager_tx_thread_performance_info_get_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_THREAD))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[1], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[2], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[3], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[4], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[5], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[6], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[7], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[8], sizeof(TX_THREAD *))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _tx_thread_performance_info_get( + (TX_THREAD *) param_0, + (ULONG *) param_1, + (ULONG *) extra_parameters[0], + (ULONG *) extra_parameters[1], + (ULONG *) extra_parameters[2], + (ULONG *) extra_parameters[3], + (ULONG *) extra_parameters[4], + (ULONG *) extra_parameters[5], + (ULONG *) extra_parameters[6], + (ULONG *) extra_parameters[7], + (TX_THREAD **) extra_parameters[8] + ); + return(return_value); +} + +/* UINT _tx_thread_performance_system_info_get( + ULONG *resumptions, -> param_0 + ULONG *suspensions, -> param_1 + ULONG *solicited_preemptions, -> extra_parameters[0] + ULONG *interrupt_preemptions, -> extra_parameters[1] + ULONG *priority_inversions, -> extra_parameters[2] + ULONG *time_slices, -> extra_parameters[3] + ULONG *relinquishes, -> extra_parameters[4] + ULONG *timeouts, -> extra_parameters[5] + ULONG *wait_aborts, -> extra_parameters[6] + ULONG *non_idle_returns, -> extra_parameters[7] + ULONG *idle_returns -> extra_parameters[8] + ); */ +static ALIGN_TYPE _txm_module_manager_tx_thread_performance_system_info_get_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_0, sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[1], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[2], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[3], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[4], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[5], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[6], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[7], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[8], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _tx_thread_performance_system_info_get( + (ULONG *) param_0, + (ULONG *) param_1, + (ULONG *) extra_parameters[0], + (ULONG *) extra_parameters[1], + (ULONG *) extra_parameters[2], + (ULONG *) extra_parameters[3], + (ULONG *) extra_parameters[4], + (ULONG *) extra_parameters[5], + (ULONG *) extra_parameters[6], + (ULONG *) extra_parameters[7], + (ULONG *) extra_parameters[8] + ); + return(return_value); +} + +/* UINT _txe_thread_preemption_change( + TX_THREAD *thread_ptr, -> param_0 + UINT new_threshold, -> param_1 + UINT *old_threshold -> param_2 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_thread_preemption_change_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_THREAD))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_2, sizeof(UINT))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_thread_preemption_change( + (TX_THREAD *) param_0, + (UINT) param_1, + (UINT *) param_2 + ); + return(return_value); +} + +/* UINT _txe_thread_priority_change( + TX_THREAD *thread_ptr, -> param_0 + UINT new_priority, -> param_1 + UINT *old_priority -> param_2 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_thread_priority_change_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_THREAD))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_2, sizeof(UINT))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_thread_priority_change( + (TX_THREAD *) param_0, + (UINT) param_1, + (UINT *) param_2 + ); + return(return_value); +} + +/* VOID _txe_thread_relinquish(); */ +static ALIGN_TYPE _txm_module_manager_tx_thread_relinquish_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + + _txe_thread_relinquish(); + return(TX_SUCCESS); +} + +/* UINT _txe_thread_reset( + TX_THREAD *thread_ptr -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_thread_reset_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_THREAD))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txm_module_manager_thread_reset( + (TX_THREAD *) param_0 + ); + return(return_value); +} + +/* UINT _txe_thread_resume( + TX_THREAD *thread_ptr -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_thread_resume_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_THREAD))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_thread_resume( + (TX_THREAD *) param_0 + ); + return(return_value); +} + +/* UINT _tx_thread_sleep( + ULONG timer_ticks -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_thread_sleep_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + +ALIGN_TYPE return_value; + + return_value = (ALIGN_TYPE) _tx_thread_sleep( + (ULONG) param_0 + ); + return(return_value); +} + +/* UINT _tx_thread_stack_error_notify( + VOID (*stack_error_handler)(TX_THREAD *thread_ptr) -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_thread_stack_error_notify_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE) + return(TXM_MODULE_INVALID_PROPERTIES); + + return_value = (ALIGN_TYPE) _tx_thread_stack_error_notify( + (VOID (*)(TX_THREAD *thread_ptr)) param_0 + ); + return(return_value); +} + +/* UINT _txe_thread_suspend( + TX_THREAD *thread_ptr -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_thread_suspend_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_THREAD))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_thread_suspend( + (TX_THREAD *) param_0 + ); + return(return_value); +} + +/* VOID _tx_thread_system_suspend( + TX_THREAD *thread_ptr -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_thread_system_suspend_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_THREAD *thread_ptr; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + /* Ensure the thread is suspending itself. */ + if (((TX_THREAD *) param_0) != _tx_thread_current_ptr) + { + return(TXM_MODULE_INVALID_MEMORY); + } + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_THREAD))) + return(TXM_MODULE_INVALID_MEMORY); + } + + /* Get the thread pointer. */ + thread_ptr = (TX_THREAD *) param_0; + + /* Disable interrupts temporarily. */ + TX_DISABLE + + /* Set the status to suspending, in order to indicate the suspension + is in progress. */ + thread_ptr -> tx_thread_state = TX_COMPLETED; + + /* Thread state change. */ + TX_THREAD_STATE_CHANGE(thread_ptr, TX_COMPLETED) + + /* Set the suspending flag. */ + thread_ptr -> tx_thread_suspending = TX_TRUE; + + /* Setup for no timeout period. */ + thread_ptr -> tx_thread_timer.tx_timer_internal_remaining_ticks = 0; + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Perform any additional activities for tool or user purpose. */ + TX_THREAD_COMPLETED_EXTENSION(thread_ptr); + + _tx_thread_system_suspend( + (TX_THREAD *) param_0 + ); + return(TX_SUCCESS); +} + +/* UINT _txe_thread_terminate( + TX_THREAD *thread_ptr -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_thread_terminate_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_THREAD))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_thread_terminate( + (TX_THREAD *) param_0 + ); + return(return_value); +} + +/* UINT _txe_thread_time_slice_change( + TX_THREAD *thread_ptr, -> param_0 + ULONG new_time_slice, -> param_1 + ULONG *old_time_slice -> param_2 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_thread_time_slice_change_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_THREAD))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_2, sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_thread_time_slice_change( + (TX_THREAD *) param_0, + (ULONG) param_1, + (ULONG *) param_2 + ); + return(return_value); +} + +/* UINT _txe_thread_wait_abort( + TX_THREAD *thread_ptr -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_thread_wait_abort_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_THREAD))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_thread_wait_abort( + (TX_THREAD *) param_0 + ); + return(return_value); +} + +/* ULONG _tx_time_get(); */ +static ALIGN_TYPE _txm_module_manager_tx_time_get_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + +ALIGN_TYPE return_value; + + return_value = (ALIGN_TYPE) _tx_time_get(); + return(return_value); +} + +/* VOID _tx_time_set( + ULONG new_time -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_time_set_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + + _tx_time_set( + (ULONG) param_0 + ); + return(TX_SUCCESS); +} + +/* UINT _txe_timer_activate( + TX_TIMER *timer_ptr -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_timer_activate_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_TIMER))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_timer_activate( + (TX_TIMER *) param_0 + ); + return(return_value); +} + +/* UINT _txe_timer_change( + TX_TIMER *timer_ptr, -> param_0 + ULONG initial_ticks, -> param_1 + ULONG reschedule_ticks -> param_2 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_timer_change_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_TIMER))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_timer_change( + (TX_TIMER *) param_0, + (ULONG) param_1, + (ULONG) param_2 + ); + return(return_value); +} + +/* UINT _txe_timer_create( + TX_TIMER *timer_ptr, -> param_0 + CHAR *name_ptr, -> param_1 + VOID (*expiration_function)(ULONG), -> extra_parameters[0] + ULONG expiration_input, -> extra_parameters[1] + ULONG initial_ticks, -> extra_parameters[2] + ULONG reschedule_ticks, -> extra_parameters[3] + UINT auto_activate, -> extra_parameters[4] + UINT timer_control_block_size -> extra_parameters[5] + ); */ +static ALIGN_TYPE _txm_module_manager_tx_timer_create_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + +ALIGN_TYPE return_value; +TX_TIMER *timer_ptr; +VOID (*expiration_function)(ULONG); + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_CREATION(module_instance, param_0, sizeof(TX_TIMER))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_DEREFERENCE_STRING(module_instance, param_1)) + return(TXM_MODULE_INVALID_MEMORY); + } + + /* Is it a disable request? */ + if ((void *) extra_parameters[0] == TX_NULL) + { + + /* Clear the callback. */ + expiration_function = (VOID (*)(ULONG)) TX_NULL; + } + else + { + + /* Set trampoline callback. */ + expiration_function = _txm_module_manager_timer_notify_trampoline; + } + + return_value = (ALIGN_TYPE) _txe_timer_create( + (TX_TIMER *) param_0, + (CHAR *) param_1, + (VOID (*)(ULONG)) expiration_function, + (ULONG) extra_parameters[1], + (ULONG) extra_parameters[2], + (ULONG) extra_parameters[3], + (UINT) extra_parameters[4], + (UINT) extra_parameters[5] + ); + + if (return_value == TX_SUCCESS) + { + + /* Get the object pointer. */ + timer_ptr = (TX_TIMER *) param_0; + + /* Setup trampoline values. */ + if ((void *) extra_parameters[0] != TX_NULL) + { + + timer_ptr -> tx_timer_module_instance = (VOID *) module_instance; + timer_ptr -> tx_timer_module_expiration_function = (VOID (*)(ULONG)) extra_parameters[0]; + } + } + return(return_value); +} + +/* UINT _txe_timer_deactivate( + TX_TIMER *timer_ptr -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_timer_deactivate_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_TIMER))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_timer_deactivate( + (TX_TIMER *) param_0 + ); + return(return_value); +} + +/* UINT _txe_timer_delete( + TX_TIMER *timer_ptr -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_timer_delete_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_TIMER))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_timer_delete( + (TX_TIMER *) param_0 + ); + + /* Deallocate object memory. */ + if (return_value == TX_SUCCESS) + { + return_value = _txm_module_manager_object_deallocate((VOID *) param_0); + } + return(return_value); +} + +/* UINT _txe_timer_info_get( + TX_TIMER *timer_ptr, -> param_0 + CHAR **name, -> param_1 + UINT *active, -> extra_parameters[0] + ULONG *remaining_ticks, -> extra_parameters[1] + ULONG *reschedule_ticks, -> extra_parameters[2] + TX_TIMER **next_timer -> extra_parameters[3] + ); */ +static ALIGN_TYPE _txm_module_manager_tx_timer_info_get_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_TIMER))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(CHAR *))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(UINT))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[1], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[2], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[3], sizeof(TX_TIMER *))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_timer_info_get( + (TX_TIMER *) param_0, + (CHAR **) param_1, + (UINT *) extra_parameters[0], + (ULONG *) extra_parameters[1], + (ULONG *) extra_parameters[2], + (TX_TIMER **) extra_parameters[3] + ); + return(return_value); +} + +/* UINT _tx_timer_performance_info_get( + TX_TIMER *timer_ptr, -> param_0 + ULONG *activates, -> param_1 + ULONG *reactivates, -> extra_parameters[0] + ULONG *deactivates, -> extra_parameters[1] + ULONG *expirations, -> extra_parameters[2] + ULONG *expiration_adjusts -> extra_parameters[3] + ); */ +static ALIGN_TYPE _txm_module_manager_tx_timer_performance_info_get_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_TIMER))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[1], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[2], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[3], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _tx_timer_performance_info_get( + (TX_TIMER *) param_0, + (ULONG *) param_1, + (ULONG *) extra_parameters[0], + (ULONG *) extra_parameters[1], + (ULONG *) extra_parameters[2], + (ULONG *) extra_parameters[3] + ); + return(return_value); +} + +/* UINT _tx_timer_performance_system_info_get( + ULONG *activates, -> param_0 + ULONG *reactivates, -> param_1 + ULONG *deactivates, -> extra_parameters[0] + ULONG *expirations, -> extra_parameters[1] + ULONG *expiration_adjusts -> extra_parameters[2] + ); */ +static ALIGN_TYPE _txm_module_manager_tx_timer_performance_system_info_get_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_0, sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[1], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[2], sizeof(ULONG))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _tx_timer_performance_system_info_get( + (ULONG *) param_0, + (ULONG *) param_1, + (ULONG *) extra_parameters[0], + (ULONG *) extra_parameters[1], + (ULONG *) extra_parameters[2] + ); + return(return_value); +} + +/* UINT _tx_trace_buffer_full_notify( + VOID (*full_buffer_callback)(VOID *buffer) -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_trace_buffer_full_notify_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + +ALIGN_TYPE return_value; + + return_value = (ALIGN_TYPE) _tx_trace_buffer_full_notify( + (VOID (*)(VOID *buffer)) param_0 + ); + return(return_value); +} + +/* UINT _tx_trace_disable(); */ +static ALIGN_TYPE _txm_module_manager_tx_trace_disable_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE) + return(TXM_MODULE_INVALID_PROPERTIES); + + return_value = (ALIGN_TYPE) _tx_trace_disable(); + return(return_value); +} + +/* UINT _tx_trace_enable( + VOID *trace_buffer_start, -> param_0 + ULONG trace_buffer_size, -> param_1 + ULONG registry_entries -> param_2 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_trace_enable_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE) + return(TXM_MODULE_INVALID_PROPERTIES); + + return_value = (ALIGN_TYPE) _tx_trace_enable( + (VOID *) param_0, + (ULONG) param_1, + (ULONG) param_2 + ); + return(return_value); +} + +/* UINT _tx_trace_event_filter( + ULONG event_filter_bits -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_trace_event_filter_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + +ALIGN_TYPE return_value; + + return_value = (ALIGN_TYPE) _tx_trace_event_filter( + (ULONG) param_0 + ); + return(return_value); +} + +/* UINT _tx_trace_event_unfilter( + ULONG event_unfilter_bits -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_trace_event_unfilter_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + +ALIGN_TYPE return_value; + + return_value = (ALIGN_TYPE) _tx_trace_event_unfilter( + (ULONG) param_0 + ); + return(return_value); +} + +/* UINT _tx_trace_interrupt_control( + UINT new_posture -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_trace_interrupt_control_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE) + return(TXM_MODULE_INVALID_PROPERTIES); + + return_value = (ALIGN_TYPE) _tx_trace_interrupt_control( + (UINT) param_0 + ); + return(return_value); +} + +/* VOID _tx_trace_isr_enter_insert( + ULONG isr_id -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_trace_isr_enter_insert_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE) + return(TXM_MODULE_INVALID_PROPERTIES); + + _tx_trace_isr_enter_insert( + (ULONG) param_0 + ); + return(TX_SUCCESS); +} + +/* VOID _tx_trace_isr_exit_insert( + ULONG isr_id -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_trace_isr_exit_insert_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE) + return(TXM_MODULE_INVALID_PROPERTIES); + + _tx_trace_isr_exit_insert( + (ULONG) param_0 + ); + return(TX_SUCCESS); +} + +/* UINT _tx_trace_user_event_insert( + ULONG event_id, -> param_0 + ULONG info_field_1, -> param_1 + ULONG info_field_2, -> extra_parameters[0] + ULONG info_field_3, -> extra_parameters[1] + ULONG info_field_4 -> extra_parameters[2] + ); */ +static ALIGN_TYPE _txm_module_manager_tx_trace_user_event_insert_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + +ALIGN_TYPE return_value; + + return_value = (ALIGN_TYPE) _tx_trace_user_event_insert( + (ULONG) param_0, + (ULONG) param_1, + (ULONG) extra_parameters[0], + (ULONG) extra_parameters[1], + (ULONG) extra_parameters[2] + ); + return(return_value); +} + +/* UINT _txm_module_object_allocate( + VOID **object_ptr, -> param_0 + ULONG object_size -> param_1 + ); */ +static ALIGN_TYPE _txm_module_manager_txm_module_object_allocate_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_0, sizeof(VOID *))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txm_module_manager_object_allocate( + (VOID **) param_0, + (ULONG) param_1, + module_instance + ); + return(return_value); +} + +/* UINT _txm_module_object_deallocate( + VOID *object_ptr -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_txm_module_object_deallocate_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + +ALIGN_TYPE return_value; +TXM_MODULE_ALLOCATED_OBJECT *object_ptr; +ALIGN_TYPE object_end; +ALIGN_TYPE object_pool_end; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + /* Is the object pool created? */ + if (_txm_module_manager_object_pool_created == TX_TRUE) + { + + /* Get the module allocated object. */ + object_ptr = ((TXM_MODULE_ALLOCATED_OBJECT *) param_0) - 1; + + /* Get the end address of the object pool. */ + object_pool_end = (ALIGN_TYPE) (_txm_module_manager_object_pool.tx_byte_pool_start + _txm_module_manager_object_pool.tx_byte_pool_size); + + /* Check that the pointer is in the object pool. */ + if ((ALIGN_TYPE) object_ptr < (ALIGN_TYPE) _txm_module_manager_object_pool.tx_byte_pool_start || + (ALIGN_TYPE) object_ptr >= (ALIGN_TYPE) object_pool_end) + { + /* Pointer is outside of the object pool. */ + return(TXM_MODULE_INVALID_MEMORY); + } + + /* Get the end addresses of the object. */ + object_end = ((ALIGN_TYPE) object_ptr) + sizeof(TXM_MODULE_ALLOCATED_OBJECT) + object_ptr -> txm_module_object_size; + + /* Check that the object is in the object pool. */ + if (object_end >= object_pool_end) + { + /* Object is outside of the object pool. */ + return(TXM_MODULE_INVALID_MEMORY); + } + } + } + + return_value = (ALIGN_TYPE) _txm_module_manager_object_deallocate( + (VOID *) param_0 + ); + return(return_value); +} + +/* UINT _txm_module_object_pointer_get( + UINT object_type, -> param_0 + CHAR *name, -> param_1 + VOID **object_ptr -> param_2 + ); */ +static ALIGN_TYPE _txm_module_manager_txm_module_object_pointer_get_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_DEREFERENCE_STRING(module_instance, param_1)) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_2, sizeof(VOID *))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txm_module_manager_object_pointer_get( + (UINT) param_0, + (CHAR *) param_1, + (VOID **) param_2 + ); + return(return_value); +} + +/* UINT _txm_module_object_pointer_get_extended( + UINT object_type, -> param_0 + CHAR *name, -> param_1 + UINT name_length, -> extra_parameters[0] + VOID **object_ptr -> extra_parameters[1] + ); */ +static ALIGN_TYPE _txm_module_manager_txm_module_object_pointer_get_extended_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE *extra_parameters) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_DEREFERENCE_STRING(module_instance, param_1)) + return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[1], sizeof(VOID *))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txm_module_manager_object_pointer_get_extended( + (UINT) param_0, + (CHAR *) param_1, + (UINT) extra_parameters[0], + (VOID **) extra_parameters[1] + ); + return(return_value); +} diff --git a/common_modules/module_manager/inc/txm_module_manager_util.h b/common_modules/module_manager/inc/txm_module_manager_util.h new file mode 100644 index 00000000..05543294 --- /dev/null +++ b/common_modules/module_manager/inc/txm_module_manager_util.h @@ -0,0 +1,188 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* txm_module_manager_util.h PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file declares prototypes of utility functions used by the */ +/* module manager. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TXM_MODULE_MANAGER_UTIL_H +#define TXM_MODULE_MANAGER_UTIL_H + +/* Define utility macros. */ + +/* Define inside/outside check macros. The _INCLUSIVE/_EXCLUSIVE suffix applies only to range_end. */ + +#define TXM_MODULE_MANAGER_CHECK_OUTSIDE_RANGE_INCLUSIVE(range_start, range_end, obj_start, obj_size) \ + ((obj_start) > (ALIGN_TYPE) (range_end) || \ + ((obj_start) + (obj_size)) <= (ALIGN_TYPE) (range_start)) + +#define TXM_MODULE_MANAGER_CHECK_OUTSIDE_RANGE_EXCLUSIVE(range_start, range_end, obj_start, obj_size) \ + ((obj_start) >= (ALIGN_TYPE) (range_end) || \ + ((obj_start) + (obj_size)) <= (ALIGN_TYPE) (range_start)) + +#define TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_INCLUSIVE(range_start, range_end, obj_start, obj_size) \ + (((obj_start) >= (ALIGN_TYPE) (range_start)) && \ + (((obj_start) + (obj_size)) <= (ALIGN_TYPE) (range_end) + 1)) + +#define TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_INCLUSIVE_BYTE(range_start, range_end, byte_ptr) \ + (((byte_ptr) >= (ALIGN_TYPE) (range_start)) && \ + ((byte_ptr) <= (ALIGN_TYPE) (range_end))) + +#define TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_EXCLUSIVE(range_start, range_end, obj_start, obj_size) \ + (((obj_start) >= (ALIGN_TYPE) (range_start)) && \ + (((obj_start) + (obj_size)) <= (ALIGN_TYPE) (range_end))) + +#define TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_EXCLUSIVE_BYTE(range_start, range_end, byte_ptr) \ + (((byte_ptr) >= (ALIGN_TYPE) (range_start)) && \ + ((byte_ptr) < (ALIGN_TYPE) (range_end))) + +/* Define check macros for modules. */ + +#define TXM_MODULE_MANAGER_CHECK_OUTSIDE_DATA(module_instance, obj_ptr, obj_size) \ + TXM_MODULE_MANAGER_CHECK_OUTSIDE_RANGE_INCLUSIVE(module_instance -> txm_module_instance_data_start, \ + module_instance -> txm_module_instance_data_end, \ + obj_ptr, obj_size) + +#define TXM_MODULE_MANAGER_CHECK_OUTSIDE_CODE(module_instance, obj_ptr, obj_size) \ + TXM_MODULE_MANAGER_CHECK_OUTSIDE_RANGE_INCLUSIVE(module_instance -> txm_module_instance_code_start, \ + module_instance -> txm_module_instance_code_end, \ + obj_ptr, obj_size) + +#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_INCLUSIVE(module_instance -> txm_module_instance_data_start, \ + module_instance -> txm_module_instance_data_end, \ + obj_ptr, obj_size) + +#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA_BYTE(module_instance, byte_ptr) \ + TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_INCLUSIVE_BYTE(module_instance -> txm_module_instance_data_start, \ + module_instance -> txm_module_instance_data_end, \ + byte_ptr) + +#define TXM_MODULE_MANAGER_CHECK_INSIDE_CODE(module_instance, obj_ptr, obj_size) \ + TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_INCLUSIVE(module_instance -> txm_module_instance_code_start, \ + module_instance -> txm_module_instance_code_end, \ + obj_ptr, obj_size) + +#define TXM_MODULE_MANAGER_CHECK_INSIDE_CODE_BYTE(module_instance, byte_ptr) \ + TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_INCLUSIVE_BYTE(module_instance -> txm_module_instance_code_start, \ + module_instance -> txm_module_instance_code_end, \ + byte_ptr) + +#define TXM_MODULE_MANAGER_CHECK_INSIDE_OBJ_POOL(module_instance, obj_ptr, obj_size) \ + ((_txm_module_manager_object_pool_created == TX_TRUE) && \ + TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_EXCLUSIVE(_txm_module_manager_object_pool.tx_byte_pool_start, \ + _txm_module_manager_object_pool.tx_byte_pool_start + _txm_module_manager_object_pool.tx_byte_pool_size, \ + obj_ptr, obj_size)) + +/* Define macros for module. */ + +#define TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE(module_instance, obj_ptr, obj_size) \ + (TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) || \ + _txm_module_manager_shared_memory_check_inside(module_instance, (ALIGN_TYPE) obj_ptr, obj_size) || \ + TXM_MODULE_MANAGER_CHECK_INSIDE_CODE(module_instance, obj_ptr, obj_size)) + +#define TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_BYTE(module_instance, byte_ptr) \ + (TXM_MODULE_MANAGER_CHECK_INSIDE_DATA_BYTE(module_instance, byte_ptr) || \ + _txm_module_manager_shared_memory_check_inside_byte(module_instance, (ALIGN_TYPE) byte_ptr) || \ + TXM_MODULE_MANAGER_CHECK_INSIDE_CODE_BYTE(module_instance, byte_ptr)) + +#define TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, obj_ptr, obj_size) \ + (TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) || \ + _txm_module_manager_shared_memory_check_inside(module_instance, (ALIGN_TYPE) obj_ptr, obj_size)) + +#define TXM_MODULE_MANAGER_ENSURE_OUTSIDE_MODULE(module_instance, obj_ptr, obj_size) \ + (TXM_MODULE_MANAGER_CHECK_OUTSIDE_DATA(module_instance, obj_ptr, obj_size) && \ + _txm_module_manager_shared_memory_check_outside(module_instance, (ALIGN_TYPE) obj_ptr, obj_size) && \ + TXM_MODULE_MANAGER_CHECK_OUTSIDE_CODE(module_instance, obj_ptr, obj_size)) + +#define TXM_MODULE_MANAGER_ENSURE_INSIDE_OBJ_POOL(module_instance, obj_ptr, obj_size) \ + (TXM_MODULE_MANAGER_CHECK_INSIDE_OBJ_POOL(module_instance, obj_ptr, obj_size)) + +/* Define macros for parameter types. */ + +/* Buffers we read from can be in RW/RO/Shared areas. */ +#define TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_READ(module_instance, buffer_ptr, buffer_size) \ + (((void *) (buffer_ptr) == TX_NULL) || \ + (TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE(module_instance, buffer_ptr, buffer_size))) + +/* Buffers we write to can only be in RW/Shared areas. */ +#define TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, buffer_ptr, buffer_size) \ + (((void *) (buffer_ptr) == TX_NULL) || \ + (TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, buffer_ptr, buffer_size))) + +/* Kernel objects should be outside the module at the very least. */ +#define TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, obj_ptr, obj_size) \ + (((void *) (obj_ptr) == TX_NULL) || \ + (TXM_MODULE_MANAGER_ENSURE_OUTSIDE_MODULE(module_instance, obj_ptr, obj_size))) + +/* When creating an object, the object must be inside the object pool. */ +#define TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_CREATION(module_instance, obj_ptr, obj_size) \ + (((void *) (obj_ptr) == TX_NULL) || \ + (TXM_MODULE_MANAGER_ENSURE_INSIDE_OBJ_POOL(module_instance, obj_ptr, obj_size) && \ + (_txm_module_manager_object_size_check(obj_ptr, obj_size) == TX_SUCCESS))) + +/* Strings we dereference can be in RW/RO/Shared areas. */ +#define TXM_MODULE_MANAGER_PARAM_CHECK_DEREFERENCE_STRING(module_instance, string_ptr) \ + (((void *) (string_ptr) == TX_NULL) || \ + (TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_BYTE(module_instance, string_ptr))) + +#define TXM_MODULE_MANAGER_UTIL_MAX_VALUE_OF_TYPE_UNSIGNED(type) ((1ULL << (sizeof(type) * 8)) - 1) + +#define TXM_MODULE_MANAGER_UTIL_MATH_ADD_ULONG(augend, addend, result) \ + if ((ULONG)-1 - (augend) < (addend)) \ + { \ + return(TXM_MODULE_MATH_OVERFLOW); \ + } \ + else \ + { \ + (result) = (augend) + (addend); \ + } + +/* Define utility functions. */ + +UINT _txm_module_manager_object_memory_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE object_ptr, ULONG object_size); +UINT _txm_module_manager_object_size_check(ALIGN_TYPE object_ptr, ULONG object_size); +UINT _txm_module_manager_object_name_compare(CHAR *object_name1, UINT object_name1_length, CHAR *object_name2); +UCHAR _txm_module_manager_created_object_check(TXM_MODULE_INSTANCE *module_instance, void *object_ptr); +UINT _txm_module_manager_util_code_allocation_size_and_alignment_get(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_alignment_dest, ULONG *code_allocation_size_dest); + +#endif diff --git a/common_modules/module_manager/src/txm_module_manager_application_request.c b/common_modules/module_manager/src/txm_module_manager_application_request.c new file mode 100644 index 00000000..af7db561 --- /dev/null +++ b/common_modules/module_manager/src/txm_module_manager_application_request.c @@ -0,0 +1,79 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_application_request PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the application-specific module request. */ +/* The entire contents of the request structure is application */ +/* specific and thus the processing in this file is left to the */ +/* application to define. */ +/* */ +/* INPUT */ +/* */ +/* request_id Module request ID */ +/* param_1 First parameter */ +/* param_2 Second parameter */ +/* param_3 Third parameter */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_kernel_dispatch Kernel dispatch function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_application_request(ULONG request_id, ALIGN_TYPE param_1, ALIGN_TYPE param_2, ALIGN_TYPE param_3) +{ + + /* By default, simply return the status of not available. */ + return(TX_NOT_AVAILABLE); +} + diff --git a/common_modules/module_manager/src/txm_module_manager_callback_request.c b/common_modules/module_manager/src/txm_module_manager_callback_request.c new file mode 100644 index 00000000..ae7e8f15 --- /dev/null +++ b/common_modules/module_manager/src/txm_module_manager_callback_request.c @@ -0,0 +1,176 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_queue.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_callback_request PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sends a notification callback function request to */ +/* the associated module. */ +/* */ +/* INPUT */ +/* */ +/* module_callback_queue Module callback request queue */ +/* callback_request Callback request */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* tx_queue_send Send module callback request */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_callback_request(TX_QUEUE *module_callback_queue, TXM_MODULE_CALLBACK_MESSAGE *callback_message) +{ + +TX_INTERRUPT_SAVE_AREA + +TXM_MODULE_CALLBACK_MESSAGE *queued_message; +UINT enqueued; +UINT found; +UINT status; + + + /* Lockout interrupts. */ + TX_DISABLE + + /* Determine if the queue is valid. */ + if ((module_callback_queue) && (module_callback_queue -> tx_queue_id == TX_QUEUE_ID)) + { + + /* Yes, the queue is valid. */ + + /* Pickup the current callback request in the queue. */ + queued_message = (TXM_MODULE_CALLBACK_MESSAGE *) module_callback_queue -> tx_queue_read; + + /* Pickup the number of items enqueued. */ + enqueued = module_callback_queue -> tx_queue_enqueued; + + /* Set the found flag to false. */ + found = TX_FALSE; + + /* Loop to look for duplicates in the queue. */ + while (enqueued != 0) + { + + /* Does this entry match the new callback message? */ + if ((queued_message -> txm_module_callback_message_application_function == callback_message -> txm_module_callback_message_application_function) && + (queued_message -> txm_module_callback_message_param_1 == callback_message -> txm_module_callback_message_param_1) && + (queued_message -> txm_module_callback_message_param_2 == callback_message -> txm_module_callback_message_param_2) && + (queued_message -> txm_module_callback_message_param_3 == callback_message -> txm_module_callback_message_param_3) && + (queued_message -> txm_module_callback_message_param_4 == callback_message -> txm_module_callback_message_param_4) && + (queued_message -> txm_module_callback_message_param_5 == callback_message -> txm_module_callback_message_param_5) && + (queued_message -> txm_module_callback_message_param_6 == callback_message -> txm_module_callback_message_param_6) && + (queued_message -> txm_module_callback_message_param_7 == callback_message -> txm_module_callback_message_param_7) && + (queued_message -> txm_module_callback_message_param_8 == callback_message -> txm_module_callback_message_param_8) && + (queued_message -> txm_module_callback_message_reserved1 == callback_message -> txm_module_callback_message_reserved1) && + (queued_message -> txm_module_callback_message_reserved2 == callback_message -> txm_module_callback_message_reserved2)) + { + + /* Update the activation count in the queued request. */ + queued_message -> txm_module_callback_message_activation_count++; + + /* Set the found flag to true. */ + found = TX_TRUE; + + /* Get out of the loop. */ + break; + } + + /* Decrease the number of messages to examine. */ + enqueued--; + + /* Move the callback message to the next message. */ + queued_message++; + + /* Check for wrap? */ + if (((ULONG *) queued_message) >= module_callback_queue -> tx_queue_end) + { + + /* Yes, set the queued message to the beginning of the queue. */ + queued_message = (TXM_MODULE_CALLBACK_MESSAGE *) module_callback_queue -> tx_queue_start; + } + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Determine if we need to send the new callback request. */ + if (found == TX_FALSE) + { + + /* Yes, send the message. */ + status = _tx_queue_send(module_callback_queue, (VOID *) callback_message, TX_NO_WAIT); + + /* Determine if an error was detected. */ + if (status != TX_SUCCESS) + { + + /* Error, increment the error counter and return. */ + _txm_module_manager_callback_error_count++; + } + } + + /* Increment the total number of callbacks. */ + _txm_module_manager_callback_total_count++; + } + else + { + + /* Module instance is not valid. */ + + /* Error, increment the error counter and return. */ + _txm_module_manager_callback_error_count++; + + /* Restore interrupts. */ + TX_RESTORE + } +} + diff --git a/common_modules/module_manager/src/txm_module_manager_event_flags_notify_trampoline.c b/common_modules/module_manager/src/txm_module_manager_event_flags_notify_trampoline.c new file mode 100644 index 00000000..afaa9480 --- /dev/null +++ b/common_modules/module_manager/src/txm_module_manager_event_flags_notify_trampoline.c @@ -0,0 +1,133 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +#include "tx_api.h" +#include "tx_event_flags.h" +#include "tx_thread.h" +#include "txm_module.h" + + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_event_flags_notify_trampoline PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the event flags set notification call from */ +/* ThreadX. */ +/* */ +/* INPUT */ +/* */ +/* group_ptr Event flags group pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_manager_callback_request Send module callback request */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_event_flags_notify_trampoline(TX_EVENT_FLAGS_GROUP *group_ptr) +{ + +TX_INTERRUPT_SAVE_AREA + +TXM_MODULE_INSTANCE *module_instance; +TXM_MODULE_CALLBACK_MESSAGE callback_message; +TX_QUEUE *module_callback_queue; + + + /* We now know the callback is for a module. */ + + /* Disable interrupts. */ + TX_DISABLE + + /* Pickup the module instance pointer. */ + module_instance = (TXM_MODULE_INSTANCE *) group_ptr -> tx_event_flags_group_module_instance; + + /* Determine if this module is still valid. */ + if ((module_instance) && (module_instance -> txm_module_instance_id == TXM_MODULE_ID) && + (module_instance -> txm_module_instance_state == TXM_MODULE_STARTED)) + { + + /* Yes, the module is still valid. */ + + /* Pickup the module's callback message queue. */ + module_callback_queue = &(module_instance -> txm_module_instance_callback_request_queue); + + /* Build the queue notification message. */ + callback_message.txm_module_callback_message_type = TXM_EVENTS_SET_CALLBACK; + callback_message.txm_module_callback_message_activation_count = 1; + callback_message.txm_module_callback_message_application_function = (VOID (*)(VOID)) group_ptr -> tx_event_flags_group_set_module_notify; + callback_message.txm_module_callback_message_param_1 = (ALIGN_TYPE) group_ptr; + callback_message.txm_module_callback_message_param_2 = 0; + callback_message.txm_module_callback_message_param_3 = 0; + callback_message.txm_module_callback_message_param_4 = 0; + callback_message.txm_module_callback_message_param_5 = 0; + callback_message.txm_module_callback_message_param_6 = 0; + callback_message.txm_module_callback_message_param_7 = 0; + callback_message.txm_module_callback_message_param_8 = 0; + callback_message.txm_module_callback_message_reserved1 = 0; + callback_message.txm_module_callback_message_reserved2 = 0; + + /* Restore interrupts. */ + TX_RESTORE + + /* Call the general processing that will place the callback on the + module's callback request queue. */ + _txm_module_manager_callback_request(module_callback_queue, &callback_message); + } + else + { + + /* Module no longer valid. */ + + /* Error, increment the error counter and return. */ + _txm_module_manager_callback_error_count++; + + /* Restore interrupts. */ + TX_RESTORE + } +} +#endif diff --git a/common_modules/module_manager/src/txm_module_manager_file_load.c b/common_modules/module_manager/src/txm_module_manager_file_load.c new file mode 100644 index 00000000..4508ec6c --- /dev/null +++ b/common_modules/module_manager/src/txm_module_manager_file_load.c @@ -0,0 +1,217 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#ifdef FX_FILEX_PRESENT + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_mutex.h" +#include "tx_thread.h" +#include "tx_byte_pool.h" +#include "fx_api.h" +#include "txm_module.h" +#include "txm_module_manager_util.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_file_load PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function reads the module preamble, allocates memory for */ +/* module code, loads the module code from the file, and calls */ +/* _txm_module_manager_internal_load to load the data and prepare the */ +/* module for execution. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* module_name Name of module */ +/* media_ptr FileX media pointer */ +/* file_name Name of module binary file */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* fx_file_close Close file */ +/* fx_file_open Open file */ +/* fx_file_read File read */ +/* fx_file_seek File seek */ +/* _tx_byte_allocate Allocate data area */ +/* _txm_module_manager_internal_load Load data and prepare module for */ +/* execution */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_file_load(TXM_MODULE_INSTANCE *module_instance, CHAR *module_name, FX_MEDIA *media_ptr, CHAR *file_name) +{ + + +TXM_MODULE_PREAMBLE *module_preamble; +FX_FILE module_file; +TXM_MODULE_PREAMBLE preamble; +ULONG code_start; +ULONG code_size; +ULONG code_alignment; +ULONG code_allocation_size; +CHAR *code_memory_ptr; +UCHAR *destination_ptr; +ULONG actual_size; +UINT status; + + + /* Attempt to open the file. */ + status = fx_file_open(media_ptr, &module_file, file_name, FX_OPEN_FOR_READ); + + /* Check the file open status. */ + if (status == FX_SUCCESS) + { + + /* Read the preamble of the module. */ + status = fx_file_read(&module_file, (VOID *) &preamble, sizeof(TXM_MODULE_PREAMBLE), &actual_size); + + /* Check the file read status. */ + if (status == FX_SUCCESS) + { + + /* Check the number of bytes read. */ + if (actual_size == sizeof(TXM_MODULE_PREAMBLE)) + { + + /* Pickup the module's information. */ + module_preamble = (TXM_MODULE_PREAMBLE *) &preamble; + + /* Pickup the module code size. */ + code_size = module_preamble -> txm_module_preamble_code_size; + + /* Check for valid sizes. */ + if (code_size != 0) + { + + /* Initialize module control block to all zeros. */ + TX_MEMSET(module_instance, 0, sizeof(TXM_MODULE_INSTANCE)); + + /* Get the amount of the bytes we need to allocate for the module's code as well as the required alignment. */ + status = _txm_module_manager_util_code_allocation_size_and_alignment_get(module_preamble, &code_alignment, &code_allocation_size); + if (status == TX_SUCCESS) + { + + /* Allocate code memory for the module. */ + status = _tx_byte_allocate(&_txm_module_manager_byte_pool, (VOID **) &code_memory_ptr, code_allocation_size, TX_NO_WAIT); + + /* Determine if the module's code memory allocation was successful. */ + if (status == TX_SUCCESS) + { + + /* Prepare to read the module code into memory. */ + code_start = (ULONG) code_memory_ptr; + code_start = (code_start + (code_alignment - 1)) & ~(code_alignment - 1); + destination_ptr = (UCHAR *) code_start; + + /* Seek back to the beginning of the file. */ + status = fx_file_seek(&module_file, 0); + if (status == FX_SUCCESS) + { + + /* Read the module into memory. */ + status = fx_file_read(&module_file, (VOID *) destination_ptr, code_size, &actual_size); + if (status == FX_SUCCESS) + { + + /* Check the actual size read. */ + if (actual_size == code_size) + { + + /* At this point, the module's instruction area is now in the RAM code area. */ + + /* Now load it in-place. */ + status = _txm_module_manager_internal_load(module_instance, module_name, (VOID *) code_start, + code_size, code_memory_ptr, code_allocation_size); + if (status == TX_SUCCESS) + { + + /* Close the file. */ + fx_file_close(&module_file); + + /* Return success. */ + return(TX_SUCCESS); + } + } + else + { + + /* Invalid number of bytes read. */ + status = TXM_MODULE_FILEX_INVALID_BYTES_READ; + } + } + } + + /* Release the memory. */ + _tx_byte_release(code_memory_ptr); + } + } + } + else + { + + /* Invalid module preamble. */ + status = TXM_MODULE_INVALID; + } + } + else + { + + /* Invalid number of bytes read. */ + status = TXM_MODULE_FILEX_INVALID_BYTES_READ; + } + } + + /* Close the file. */ + fx_file_close(&module_file); + } + + /* Return success. */ + return(status); +} + +#endif diff --git a/common_modules/module_manager/src/txm_module_manager_in_place_load.c b/common_modules/module_manager/src/txm_module_manager_in_place_load.c new file mode 100644 index 00000000..d5ee4b55 --- /dev/null +++ b/common_modules/module_manager/src/txm_module_manager_in_place_load.c @@ -0,0 +1,120 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_mutex.h" +#include "tx_thread.h" +#include "tx_byte_pool.h" +#include "txm_module.h" +#include "txm_module_manager_util.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_in_place_load PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function ensures the code-related parts of the module preamble */ +/* are valid and calls _txm_module_manager_internal_load to load the */ +/* data and prepare the module for execution. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* module_name Module name pointer */ +/* module_location Module code location */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_manager_internal_load Load data and prepare module for */ +/* execution */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_in_place_load(TXM_MODULE_INSTANCE *module_instance, CHAR *module_name, VOID *module_location) +{ + +TXM_MODULE_PREAMBLE *module_preamble; +ULONG code_size; +ULONG code_alignment; +ULONG code_allocation_size_ignored; +UINT status; + + + /* Pickup the module's information. */ + module_preamble = (TXM_MODULE_PREAMBLE *) module_location; + + /* Pickup the basic module sizes. */ + code_size = module_preamble -> txm_module_preamble_code_size; + + /* Check for valid sizes. */ + if (code_size == 0) + { + + /* Invalid module preamble. */ + return(TXM_MODULE_INVALID); + } + + /* Get the amount of the bytes we need to allocate for the module's code + as well as the required alignment. Note that because this is an in-place + load, we only want the code alignment so we can check it. */ + status = _txm_module_manager_util_code_allocation_size_and_alignment_get(module_preamble, &code_alignment, &code_allocation_size_ignored); + if (status != TX_SUCCESS) + { + + /* Math overflow error occurred. */ + return(status); + } + + /* Since this is an in-place load, check the alignment of the module's instruction area (code). */ + TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment) + + /* Now load the module in-place. */ + status = _txm_module_manager_internal_load(module_instance, module_name, module_location, + code_size, TX_NULL, 0); + + /* Return status. */ + return(status); +} diff --git a/common_modules/module_manager/src/txm_module_manager_initialize.c b/common_modules/module_manager/src/txm_module_manager_initialize.c new file mode 100644 index 00000000..1d9f19ab --- /dev/null +++ b/common_modules/module_manager/src/txm_module_manager_initialize.c @@ -0,0 +1,186 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_MODULE_MANAGER_INIT + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_byte_pool.h" +#include "tx_queue.h" +#include "tx_mutex.h" +#include "txm_module.h" + + +TXM_MODULE_MANAGER_VERSION_ID + + +/* Define global variables associated with the module manager. */ + + +/* Define the module properties supported by this module manager. */ + +ULONG _txm_module_manager_properties_supported; + + +/* Define the module properties required by this module manager. */ + +ULONG _txm_module_manager_properties_required; + + +/* Define byte pool that will be used for allocating module data areas. */ + +TX_BYTE_POOL _txm_module_manager_byte_pool; + + +/* Define byte pool that will be used for allocating external memory for module objects. */ + +TX_BYTE_POOL _txm_module_manager_object_pool; + + +/* Define the flag indicating that the module manager byte pool is created. */ + +UINT _txm_module_manager_object_pool_created; + + +/* Define module manager protection mutex. */ + +TX_MUTEX _txm_module_manager_mutex; + + +/* Define the loaded modules list, which keeps track of all loaded modules. */ + +TXM_MODULE_INSTANCE *_txm_module_manager_loaded_list_ptr; + + +/* Define the count of loaded modules. */ + +ULONG _txm_module_manger_loaded_count; + + +/* Define the ready flag, which is checked by other module manager APIs + to make sure the manager has been initialized. */ + +UINT _txm_module_manager_ready; + + +/* Define the total callback activation count. This is simply incremented on every + callback activation. */ + +ULONG _txm_module_manager_callback_total_count; + + +/* Define the callback activation error count. This occurs when the available callback + structures have been exhausted. */ + +ULONG _txm_module_manager_callback_error_count; + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_initialize PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes the module manager. */ +/* */ +/* INPUT */ +/* */ +/* module_memory_start Start of module area */ +/* module_memory_size Size in bytes of module area */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_byte_pool_create Create module memory byte pool */ +/* _tx_mutex_create Create module manager */ +/* protection mutex */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_initialize(VOID *module_memory_start, ULONG module_memory_size) +{ + + /* Check for interrupt call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != 0) + { + + /* Now, make sure the call is from an interrupt and not initialization. */ + if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS) + { + + /* Invalid caller of this function, return appropriate error code. */ + return(TX_CALLER_ERROR); + } + } + + /* Setup the module properties supported by this module manager. */ + _txm_module_manager_properties_supported = TXM_MODULE_MANAGER_SUPPORTED_OPTIONS; + + /* Setup the module properties required by this module manager. */ + _txm_module_manager_properties_required = TXM_MODULE_MANAGER_REQUIRED_OPTIONS; + + /* Clear the module manager ready flag. */ + _txm_module_manager_ready = TX_FALSE; + + /* Initialize the empty module list. */ + _txm_module_manager_loaded_list_ptr = TX_NULL; + + /* Clear the number of loaded modules. */ + _txm_module_manger_loaded_count = 0; + + /* Create the module manager protection mutex. */ + _tx_mutex_create(&_txm_module_manager_mutex, "Module Manager Protection Mutex", TX_NO_INHERIT); + + /* Create a byte pool for allocating RAM areas for modules. */ + _tx_byte_pool_create(&_txm_module_manager_byte_pool, "Module Manager Byte Pool", module_memory_start, module_memory_size); + + /* Indicate the module manager object pool has not been created. */ + _txm_module_manager_object_pool_created = TX_FALSE; + + /* Mark the module manager as ready! */ + _txm_module_manager_ready = TX_TRUE; + + /* Return success. */ + return(TX_SUCCESS); +} + diff --git a/common_modules/module_manager/src/txm_module_manager_internal_load.c b/common_modules/module_manager/src/txm_module_manager_internal_load.c new file mode 100644 index 00000000..3ba46d82 --- /dev/null +++ b/common_modules/module_manager/src/txm_module_manager_internal_load.c @@ -0,0 +1,424 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_mutex.h" +#include "tx_thread.h" +#include "tx_byte_pool.h" +#include "txm_module.h" +#include "txm_module_manager_util.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_internal_load PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function allocates data memory for module and prepares the */ +/* module for execution from the supplied code location. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* module_name Module name pointer */ +/* module_location Module code location */ +/* code_size Module code size */ +/* code_allocation_ptr Allocated code location */ +/* code_allocation_size Allocated code size */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_byte_allocate Allocate data area */ +/* _tx_mutex_get Get protection mutex */ +/* _tx_mutex_put Release protection mutex */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_internal_load(TXM_MODULE_INSTANCE *module_instance, CHAR *module_name, VOID *module_location, + ULONG code_size, VOID *code_allocation_ptr, ULONG code_allocation_size) +{ + +TX_INTERRUPT_SAVE_AREA + +TXM_MODULE_PREAMBLE *module_preamble; +TXM_MODULE_INSTANCE *next_module, *previous_module; +ULONG shell_function_adjust; +ULONG start_function_adjust; +ULONG stop_function_adjust; +ULONG callback_function_adjust; +ULONG start_stop_stack_size; +ULONG callback_stack_size; +ULONG code_size_ignored; +ULONG code_alignment_ignored; +ALIGN_TYPE data_start; +ULONG data_size; +ULONG data_alignment; +ULONG data_allocation_size; +ULONG module_properties; +CHAR *memory_ptr; +UINT status; + + + /* Check for interrupt call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != 0) + { + + /* Now, make sure the call is from an interrupt and not initialization. */ + if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS) + { + + /* Invalid caller of this function, return appropriate error code. */ + return(TX_CALLER_ERROR); + } + } + + /* Determine if the module manager has not been initialized yet. */ + if (_txm_module_manager_ready != TX_TRUE) + { + + /* Module manager has not been initialized. */ + return(TX_NOT_AVAILABLE); + } + + /* Determine if the module is valid. */ + if (module_instance == TX_NULL) + { + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Get module manager protection mutex. */ + _tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER); + + /* Determine if the module is already valid. */ + if (module_instance -> txm_module_instance_id == TXM_MODULE_ID) + { + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Module already loaded. */ + return(TXM_MODULE_ALREADY_LOADED); + } + + /* Pickup the module's information. */ + module_preamble = (TXM_MODULE_PREAMBLE *) module_location; + + /* Check to make sure there is a valid module to load. */ + if (module_preamble -> txm_module_preamble_id != TXM_MODULE_ID) + { + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Invalid module preamble. */ + return(TXM_MODULE_INVALID); + } + + /* Check the properties of this module. */ + module_properties = module_preamble -> txm_module_preamble_property_flags & TXM_MODULE_OPTIONS_MASK; + if (/* Ensure the requested properties are supported. */ + ((module_properties & _txm_module_manager_properties_supported) != module_properties) || + /* Ensure the required properties are there. */ + ((_txm_module_manager_properties_required & module_properties) != _txm_module_manager_properties_required) || + /* If memory protection is enabled, then so must user mode. */ + ((module_properties & TXM_MODULE_MEMORY_PROTECTION) && !(module_properties & TXM_MODULE_USER_MODE)) + ) + { + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Invalid properties. Return error. */ + return(TXM_MODULE_INVALID_PROPERTIES); + } + + /* Check for valid module entry offsets. */ + if ((module_preamble -> txm_module_preamble_shell_entry_function == 0) || + (module_preamble -> txm_module_preamble_start_function == 0)) + { + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Invalid module preamble. */ + return(TXM_MODULE_INVALID); + } + + /* Check for valid sizes. */ + if ((module_preamble -> txm_module_preamble_code_size == 0) || + (module_preamble -> txm_module_preamble_data_size == 0) || + (module_preamble -> txm_module_preamble_start_stop_stack_size == 0) || + (module_preamble -> txm_module_preamble_callback_stack_size == 0)) + { + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Invalid module preamble. */ + return(TXM_MODULE_INVALID); + } + + /* Initialize module control block to all zeros. */ + TX_MEMSET(module_instance, 0, sizeof(TXM_MODULE_INSTANCE)); + + /* Pickup the basic module sizes. */ + data_size = module_preamble -> txm_module_preamble_data_size; + start_stop_stack_size = module_preamble -> txm_module_preamble_start_stop_stack_size; + callback_stack_size = module_preamble -> txm_module_preamble_callback_stack_size; + + /* Adjust the size of the module elements to be aligned to the default alignment. We do this + so that when we partition the allocated memory, we can simply place these regions right beside + each other without having to align their pointers. Note this only works when they all have + the same alignment. */ + + TXM_MODULE_MANAGER_UTIL_MATH_ADD_ULONG(data_size, TXM_MODULE_DATA_ALIGNMENT, data_size); + data_size = ((data_size - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + TXM_MODULE_MANAGER_UTIL_MATH_ADD_ULONG(start_stop_stack_size, TXM_MODULE_DATA_ALIGNMENT, start_stop_stack_size); + start_stop_stack_size = ((start_stop_stack_size - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + TXM_MODULE_MANAGER_UTIL_MATH_ADD_ULONG(callback_stack_size, TXM_MODULE_DATA_ALIGNMENT, callback_stack_size); + callback_stack_size = ((callback_stack_size - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + /* Update the data size to account for the default thread stacks. */ + TXM_MODULE_MANAGER_UTIL_MATH_ADD_ULONG(data_size, start_stop_stack_size, data_size); + TXM_MODULE_MANAGER_UTIL_MATH_ADD_ULONG(data_size, callback_stack_size, data_size); + + /* Setup the default code and data alignments. */ + data_alignment = (ULONG) TXM_MODULE_DATA_ALIGNMENT; + + /* Get the port-specific alignment for the data size. Note we only want data + so we pass values of 1 for code (to avoid any possible div by 0 errors). */ + code_size_ignored = 1; + code_alignment_ignored = 1; + TXM_MODULE_MANAGER_ALIGNMENT_ADJUST(module_preamble, code_size_ignored, code_alignment_ignored, data_size, data_alignment) + + /* Calculate the module's total RAM memory requirement. This entire area is allocated from the module + manager's byte pool. The general layout is defined as follows: + + Lowest Address: Start of start/stop thread stack + ... [note: thread entry info is embedded near end of stack areas] + End of start/stop thread stack + + Start of callback thread stack + ... [note: thread entry info is embedded near end of stack areas] + End of callback thread stack + + Module's Data Area + ... + End of Module's Data Area + Highest Address: */ + + /* Add an extra alignment increment so we can align the pointer after allocation. */ + TXM_MODULE_MANAGER_UTIL_MATH_ADD_ULONG(data_size, data_alignment, data_allocation_size); + + /* Allocate memory for the module. */ + status = _tx_byte_allocate(&_txm_module_manager_byte_pool, (VOID **) &memory_ptr, data_allocation_size, TX_NO_WAIT); + + /* Determine if the module memory allocation was successful. */ + if (status) + { + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* No memory, return an error. */ + return(TX_NO_MEMORY); + } + + /* Clear the allocated memory. */ + TX_MEMSET(memory_ptr, ((UCHAR) 0), data_allocation_size); + + /* Disable interrupts. */ + TX_DISABLE + + /* Setup the module instance structure. */ + module_instance -> txm_module_instance_id = TXM_MODULE_ID; + + /* Save the module name. */ + module_instance -> txm_module_instance_name = module_name; + + /* Save the module properties. */ + module_instance -> txm_module_instance_property_flags = module_preamble -> txm_module_preamble_property_flags; + + /* Set the module data memory allocation. This is the address released + when the module is unloaded. */ + module_instance -> txm_module_instance_data_allocation_ptr = (VOID *) memory_ptr; + + /* Save the data allocation size. */ + module_instance -> txm_module_instance_data_allocation_size = data_allocation_size; + + /* Calculate the actual start of the data area. This needs to be adjusted based on the alignment. */ + data_start = (ALIGN_TYPE) memory_ptr; + data_start = (data_start + (((ALIGN_TYPE)data_alignment) - 1)) & ~(((ALIGN_TYPE)data_alignment) - 1); + memory_ptr = (CHAR *) data_start; + module_instance -> txm_module_instance_data_start = (VOID *) memory_ptr; + + /* Compute the end of the data memory allocation. */ + module_instance -> txm_module_instance_data_end = (VOID *) (memory_ptr + (data_size - 1)); + + /* Save the size of the data area. */ + module_instance -> txm_module_instance_data_size = data_size; + + /* Set the module code memory allocation. This is the address released + when the module is unloaded. */ + module_instance -> txm_module_instance_code_allocation_ptr = (VOID *) code_allocation_ptr; + + /* Save the code allocation size. */ + module_instance -> txm_module_instance_code_allocation_size = code_allocation_size; + + /* Setup the code pointers. Since the code was loaded in-place, this is effectively just the values supplied in the API call. */ + module_instance -> txm_module_instance_code_start = (VOID *) module_location; + module_instance -> txm_module_instance_code_end = (VOID *) (((CHAR *) module_location) + (code_size - 1)); + + /* Setup the code size. */ + module_instance -> txm_module_instance_code_size = code_size; + + /* Save the module's total memory usage. */ + module_instance -> txm_module_instance_total_ram_usage = data_allocation_size + code_allocation_size; + + /* Set the module state to started. */ + module_instance -> txm_module_instance_state = TXM_MODULE_LOADED; + + /* Save the preamble pointer. */ + module_instance -> txm_module_instance_preamble_ptr = module_preamble; + + /* Save the module application ID in the module instance. */ + module_instance -> txm_module_instance_application_module_id = module_preamble -> txm_module_preamble_application_module_id; + + /* Setup the module's start/stop thread stack area. */ + module_instance -> txm_module_instance_start_stop_stack_start_address = (VOID *) (memory_ptr); + module_instance -> txm_module_instance_start_stop_stack_size = start_stop_stack_size; + module_instance -> txm_module_instance_start_stop_stack_end_address = (VOID *) (memory_ptr + (start_stop_stack_size - 1)); + + /* Move the memory pointer forward. */ + memory_ptr = memory_ptr + start_stop_stack_size; + + /* Save the start/stop thread priority. */ + module_instance -> txm_module_instance_start_stop_priority = module_preamble -> txm_module_preamble_start_stop_priority; + + /* Setup the module's callback thread stack area. */ + module_instance -> txm_module_instance_callback_stack_start_address = (VOID *) (memory_ptr); + module_instance -> txm_module_instance_callback_stack_size = callback_stack_size; + module_instance -> txm_module_instance_callback_stack_end_address = (VOID *) (memory_ptr + (callback_stack_size - 1)); + + /* Move the memory pointer forward. */ + memory_ptr = memory_ptr + callback_stack_size; + + /* Save the callback thread priority. */ + module_instance -> txm_module_instance_callback_priority = module_preamble -> txm_module_preamble_callback_priority; + + /* Setup the start of the module data section. */ + module_instance -> txm_module_instance_module_data_base_address = (VOID *) (memory_ptr); + + /* Calculate the function adjustments based on the specific implementation of the module manager/module. */ + TXM_MODULE_MANAGER_CALCULATE_ADJUSTMENTS(module_preamble -> txm_module_preamble_property_flags, shell_function_adjust, start_function_adjust, stop_function_adjust, callback_function_adjust) + + /* Build actual addresses based on load... Setup all the function pointers. Any adjustments needed to shell entry, start function, and callback function are defined in the + module preamble. */ + module_instance -> txm_module_instance_shell_entry_function = (VOID (*)(TX_THREAD *, TXM_MODULE_INSTANCE *)) (((CHAR *) module_instance -> txm_module_instance_code_start) + + (module_preamble -> txm_module_preamble_shell_entry_function) + + (shell_function_adjust)); + module_instance -> txm_module_instance_start_thread_entry = (VOID (*)(ULONG)) (((CHAR *) module_instance -> txm_module_instance_code_start) + + (module_preamble -> txm_module_preamble_start_function) + + (start_function_adjust)); + module_instance -> txm_module_instance_callback_request_thread_entry = (VOID (*)(ULONG)) (((CHAR *) module_instance -> txm_module_instance_code_start) + + (module_preamble -> txm_module_preamble_callback_function) + + (callback_function_adjust)); + /* Determine if there is a stop function for this module. */ + if (module_preamble -> txm_module_preamble_stop_function) + { + + /* Yes, there is a stop function, build the address. */ + module_instance -> txm_module_instance_stop_thread_entry = (VOID (*)(ULONG)) (((CHAR *) module_instance -> txm_module_instance_code_start) + + (module_preamble -> txm_module_preamble_stop_function) + + (stop_function_adjust)); + } + else + { + + /* No, there is no stop function. Just set the pointer to NULL. */ + module_instance -> txm_module_instance_stop_thread_entry = TX_NULL; + } + + /* Load the module control block with port-specific information. */ + TXM_MODULE_MANAGER_MODULE_SETUP(module_instance); + + /* Now add the module to the linked list of created modules. */ + if (_txm_module_manger_loaded_count++ == 0) + { + + /* The loaded module list is empty. Add module to empty list. */ + _txm_module_manager_loaded_list_ptr = module_instance; + module_instance -> txm_module_instance_loaded_next = module_instance; + module_instance -> txm_module_instance_loaded_previous = module_instance; + } + else + { + + /* This list is not NULL, add to the end of the list. */ + next_module = _txm_module_manager_loaded_list_ptr; + previous_module = next_module -> txm_module_instance_loaded_previous; + + /* Place the new module in the list. */ + next_module -> txm_module_instance_loaded_previous = module_instance; + previous_module -> txm_module_instance_loaded_next = module_instance; + + /* Setup this module's created links. */ + module_instance -> txm_module_instance_loaded_previous = previous_module; + module_instance -> txm_module_instance_loaded_next = next_module; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/common_modules/module_manager/src/txm_module_manager_kernel_dispatch.c b/common_modules/module_manager/src/txm_module_manager_kernel_dispatch.c new file mode 100644 index 00000000..08761e17 --- /dev/null +++ b/common_modules/module_manager/src/txm_module_manager_kernel_dispatch.c @@ -0,0 +1,741 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_block_pool.h" +#include "tx_byte_pool.h" +#include "tx_event_flags.h" +#include "tx_queue.h" +#include "tx_mutex.h" +#include "tx_semaphore.h" +#include "tx_thread.h" +#include "tx_timer.h" +#include "tx_trace.h" +#include "txm_module.h" +#include "txm_module_manager_util.h" +#include "txm_module_manager_dispatch.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_kernel_dispatch PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function dispatches the module's kernel request based upon the */ +/* ID and parameters specified in the request. */ +/* */ +/* INPUT */ +/* */ +/* kernel_request Module's kernel request */ +/* param_1 First parameter */ +/* param_2 Second parameter */ +/* param_3 Third parameter */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_manager_application_request Application-specific req */ +/* _txm_module_manager_object_pointer_get Find object pointer */ +/* _txm_module_manager_thread_create Module thread create */ +/* [_txm_module_manager_*_dispatch] Optional external */ +/* component dispatch */ +/* ThreadX API Calls */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +ALIGN_TYPE _txm_module_manager_kernel_dispatch(ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) +{ + +ALIGN_TYPE return_value = TX_NOT_AVAILABLE; +TXM_MODULE_INSTANCE *module_instance; + + + /* Get the module instance. */ + module_instance = _tx_thread_current_ptr -> tx_thread_module_instance_ptr; + + /* Sanity-check for a valid module instance. */ + if (module_instance == TX_NULL) + { + /* Just return! */ + return(TXM_MODULE_INVALID); + } + + switch (kernel_request) + { + case TXM_BLOCK_ALLOCATE_CALL: + { + return_value = _txm_module_manager_tx_block_allocate_dispatch(module_instance, param_0, param_1, param_2); + break; + } + + case TXM_BLOCK_POOL_CREATE_CALL: + { + return_value = _txm_module_manager_tx_block_pool_create_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + case TXM_BLOCK_POOL_DELETE_CALL: + { + return_value = _txm_module_manager_tx_block_pool_delete_dispatch(module_instance, param_0); + break; + } + + case TXM_BLOCK_POOL_INFO_GET_CALL: + { + return_value = _txm_module_manager_tx_block_pool_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + case TXM_BLOCK_POOL_PERFORMANCE_INFO_GET_CALL: + { + return_value = _txm_module_manager_tx_block_pool_performance_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + case TXM_BLOCK_POOL_PERFORMANCE_SYSTEM_INFO_GET_CALL: + { + return_value = _txm_module_manager_tx_block_pool_performance_system_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + case TXM_BLOCK_POOL_PRIORITIZE_CALL: + { + return_value = _txm_module_manager_tx_block_pool_prioritize_dispatch(module_instance, param_0); + break; + } + + case TXM_BLOCK_RELEASE_CALL: + { + return_value = _txm_module_manager_tx_block_release_dispatch(module_instance, param_0); + break; + } + + case TXM_BYTE_ALLOCATE_CALL: + { + return_value = _txm_module_manager_tx_byte_allocate_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + case TXM_BYTE_POOL_CREATE_CALL: + { + return_value = _txm_module_manager_tx_byte_pool_create_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + case TXM_BYTE_POOL_DELETE_CALL: + { + return_value = _txm_module_manager_tx_byte_pool_delete_dispatch(module_instance, param_0); + break; + } + + case TXM_BYTE_POOL_INFO_GET_CALL: + { + return_value = _txm_module_manager_tx_byte_pool_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + case TXM_BYTE_POOL_PERFORMANCE_INFO_GET_CALL: + { + return_value = _txm_module_manager_tx_byte_pool_performance_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + case TXM_BYTE_POOL_PERFORMANCE_SYSTEM_INFO_GET_CALL: + { + return_value = _txm_module_manager_tx_byte_pool_performance_system_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + case TXM_BYTE_POOL_PRIORITIZE_CALL: + { + return_value = _txm_module_manager_tx_byte_pool_prioritize_dispatch(module_instance, param_0); + break; + } + + case TXM_BYTE_RELEASE_CALL: + { + return_value = _txm_module_manager_tx_byte_release_dispatch(module_instance, param_0); + break; + } + + case TXM_EVENT_FLAGS_CREATE_CALL: + { + return_value = _txm_module_manager_tx_event_flags_create_dispatch(module_instance, param_0, param_1, param_2); + break; + } + + case TXM_EVENT_FLAGS_DELETE_CALL: + { + return_value = _txm_module_manager_tx_event_flags_delete_dispatch(module_instance, param_0); + break; + } + + case TXM_EVENT_FLAGS_GET_CALL: + { + return_value = _txm_module_manager_tx_event_flags_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + case TXM_EVENT_FLAGS_INFO_GET_CALL: + { + return_value = _txm_module_manager_tx_event_flags_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + case TXM_EVENT_FLAGS_PERFORMANCE_INFO_GET_CALL: + { + return_value = _txm_module_manager_tx_event_flags_performance_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + case TXM_EVENT_FLAGS_PERFORMANCE_SYSTEM_INFO_GET_CALL: + { + return_value = _txm_module_manager_tx_event_flags_performance_system_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + case TXM_EVENT_FLAGS_SET_CALL: + { + return_value = _txm_module_manager_tx_event_flags_set_dispatch(module_instance, param_0, param_1, param_2); + break; + } + + case TXM_EVENT_FLAGS_SET_NOTIFY_CALL: + { + return_value = _txm_module_manager_tx_event_flags_set_notify_dispatch(module_instance, param_0, param_1); + break; + } + + case TXM_MUTEX_CREATE_CALL: + { + return_value = _txm_module_manager_tx_mutex_create_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + case TXM_MUTEX_DELETE_CALL: + { + return_value = _txm_module_manager_tx_mutex_delete_dispatch(module_instance, param_0); + break; + } + + case TXM_MUTEX_GET_CALL: + { + return_value = _txm_module_manager_tx_mutex_get_dispatch(module_instance, param_0, param_1); + break; + } + + case TXM_MUTEX_INFO_GET_CALL: + { + return_value = _txm_module_manager_tx_mutex_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + case TXM_MUTEX_PERFORMANCE_INFO_GET_CALL: + { + return_value = _txm_module_manager_tx_mutex_performance_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + case TXM_MUTEX_PERFORMANCE_SYSTEM_INFO_GET_CALL: + { + return_value = _txm_module_manager_tx_mutex_performance_system_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + case TXM_MUTEX_PRIORITIZE_CALL: + { + return_value = _txm_module_manager_tx_mutex_prioritize_dispatch(module_instance, param_0); + break; + } + + case TXM_MUTEX_PUT_CALL: + { + return_value = _txm_module_manager_tx_mutex_put_dispatch(module_instance, param_0); + break; + } + + case TXM_QUEUE_CREATE_CALL: + { + return_value = _txm_module_manager_tx_queue_create_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + case TXM_QUEUE_DELETE_CALL: + { + return_value = _txm_module_manager_tx_queue_delete_dispatch(module_instance, param_0); + break; + } + + case TXM_QUEUE_FLUSH_CALL: + { + return_value = _txm_module_manager_tx_queue_flush_dispatch(module_instance, param_0); + break; + } + + case TXM_QUEUE_FRONT_SEND_CALL: + { + return_value = _txm_module_manager_tx_queue_front_send_dispatch(module_instance, param_0, param_1, param_2); + break; + } + + case TXM_QUEUE_INFO_GET_CALL: + { + return_value = _txm_module_manager_tx_queue_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + case TXM_QUEUE_PERFORMANCE_INFO_GET_CALL: + { + return_value = _txm_module_manager_tx_queue_performance_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + case TXM_QUEUE_PERFORMANCE_SYSTEM_INFO_GET_CALL: + { + return_value = _txm_module_manager_tx_queue_performance_system_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + case TXM_QUEUE_PRIORITIZE_CALL: + { + return_value = _txm_module_manager_tx_queue_prioritize_dispatch(module_instance, param_0); + break; + } + + case TXM_QUEUE_RECEIVE_CALL: + { + return_value = _txm_module_manager_tx_queue_receive_dispatch(module_instance, param_0, param_1, param_2); + break; + } + + case TXM_QUEUE_SEND_CALL: + { + return_value = _txm_module_manager_tx_queue_send_dispatch(module_instance, param_0, param_1, param_2); + break; + } + + case TXM_QUEUE_SEND_NOTIFY_CALL: + { + return_value = _txm_module_manager_tx_queue_send_notify_dispatch(module_instance, param_0, param_1); + break; + } + + case TXM_SEMAPHORE_CEILING_PUT_CALL: + { + return_value = _txm_module_manager_tx_semaphore_ceiling_put_dispatch(module_instance, param_0, param_1); + break; + } + + case TXM_SEMAPHORE_CREATE_CALL: + { + return_value = _txm_module_manager_tx_semaphore_create_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + case TXM_SEMAPHORE_DELETE_CALL: + { + return_value = _txm_module_manager_tx_semaphore_delete_dispatch(module_instance, param_0); + break; + } + + case TXM_SEMAPHORE_GET_CALL: + { + return_value = _txm_module_manager_tx_semaphore_get_dispatch(module_instance, param_0, param_1); + break; + } + + case TXM_SEMAPHORE_INFO_GET_CALL: + { + return_value = _txm_module_manager_tx_semaphore_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + case TXM_SEMAPHORE_PERFORMANCE_INFO_GET_CALL: + { + return_value = _txm_module_manager_tx_semaphore_performance_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + case TXM_SEMAPHORE_PERFORMANCE_SYSTEM_INFO_GET_CALL: + { + return_value = _txm_module_manager_tx_semaphore_performance_system_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + case TXM_SEMAPHORE_PRIORITIZE_CALL: + { + return_value = _txm_module_manager_tx_semaphore_prioritize_dispatch(module_instance, param_0); + break; + } + + case TXM_SEMAPHORE_PUT_CALL: + { + return_value = _txm_module_manager_tx_semaphore_put_dispatch(module_instance, param_0); + break; + } + + case TXM_SEMAPHORE_PUT_NOTIFY_CALL: + { + return_value = _txm_module_manager_tx_semaphore_put_notify_dispatch(module_instance, param_0, param_1); + break; + } + + case TXM_THREAD_CREATE_CALL: + { + return_value = _txm_module_manager_tx_thread_create_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + case TXM_THREAD_DELETE_CALL: + { + return_value = _txm_module_manager_tx_thread_delete_dispatch(module_instance, param_0); + break; + } + + case TXM_THREAD_ENTRY_EXIT_NOTIFY_CALL: + { + return_value = _txm_module_manager_tx_thread_entry_exit_notify_dispatch(module_instance, param_0, param_1); + break; + } + + case TXM_THREAD_IDENTIFY_CALL: + { + return_value = _txm_module_manager_tx_thread_identify_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + case TXM_THREAD_INFO_GET_CALL: + { + return_value = _txm_module_manager_tx_thread_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + case TXM_THREAD_INTERRUPT_CONTROL_CALL: + { + return_value = _txm_module_manager_tx_thread_interrupt_control_dispatch(module_instance, param_0); + break; + } + + case TXM_THREAD_PERFORMANCE_INFO_GET_CALL: + { + return_value = _txm_module_manager_tx_thread_performance_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + case TXM_THREAD_PERFORMANCE_SYSTEM_INFO_GET_CALL: + { + return_value = _txm_module_manager_tx_thread_performance_system_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + case TXM_THREAD_PREEMPTION_CHANGE_CALL: + { + return_value = _txm_module_manager_tx_thread_preemption_change_dispatch(module_instance, param_0, param_1, param_2); + break; + } + + case TXM_THREAD_PRIORITY_CHANGE_CALL: + { + return_value = _txm_module_manager_tx_thread_priority_change_dispatch(module_instance, param_0, param_1, param_2); + break; + } + + case TXM_THREAD_RELINQUISH_CALL: + { + return_value = _txm_module_manager_tx_thread_relinquish_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + case TXM_THREAD_RESET_CALL: + { + return_value = _txm_module_manager_tx_thread_reset_dispatch(module_instance, param_0); + break; + } + + case TXM_THREAD_RESUME_CALL: + { + return_value = _txm_module_manager_tx_thread_resume_dispatch(module_instance, param_0); + break; + } + + case TXM_THREAD_SLEEP_CALL: + { + return_value = _txm_module_manager_tx_thread_sleep_dispatch(module_instance, param_0); + break; + } + + case TXM_THREAD_STACK_ERROR_NOTIFY_CALL: + { + return_value = _txm_module_manager_tx_thread_stack_error_notify_dispatch(module_instance, param_0); + break; + } + + case TXM_THREAD_SUSPEND_CALL: + { + return_value = _txm_module_manager_tx_thread_suspend_dispatch(module_instance, param_0); + break; + } + + case TXM_THREAD_SYSTEM_SUSPEND_CALL: + { + return_value = _txm_module_manager_tx_thread_system_suspend_dispatch(module_instance, param_0); + break; + } + + case TXM_THREAD_TERMINATE_CALL: + { + return_value = _txm_module_manager_tx_thread_terminate_dispatch(module_instance, param_0); + break; + } + + case TXM_THREAD_TIME_SLICE_CHANGE_CALL: + { + return_value = _txm_module_manager_tx_thread_time_slice_change_dispatch(module_instance, param_0, param_1, param_2); + break; + } + + case TXM_THREAD_WAIT_ABORT_CALL: + { + return_value = _txm_module_manager_tx_thread_wait_abort_dispatch(module_instance, param_0); + break; + } + + case TXM_TIME_GET_CALL: + { + return_value = _txm_module_manager_tx_time_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + case TXM_TIME_SET_CALL: + { + return_value = _txm_module_manager_tx_time_set_dispatch(module_instance, param_0); + break; + } + + case TXM_TIMER_ACTIVATE_CALL: + { + return_value = _txm_module_manager_tx_timer_activate_dispatch(module_instance, param_0); + break; + } + + case TXM_TIMER_CHANGE_CALL: + { + return_value = _txm_module_manager_tx_timer_change_dispatch(module_instance, param_0, param_1, param_2); + break; + } + + case TXM_TIMER_CREATE_CALL: + { + return_value = _txm_module_manager_tx_timer_create_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + case TXM_TIMER_DEACTIVATE_CALL: + { + return_value = _txm_module_manager_tx_timer_deactivate_dispatch(module_instance, param_0); + break; + } + + case TXM_TIMER_DELETE_CALL: + { + return_value = _txm_module_manager_tx_timer_delete_dispatch(module_instance, param_0); + break; + } + + case TXM_TIMER_INFO_GET_CALL: + { + return_value = _txm_module_manager_tx_timer_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + case TXM_TIMER_PERFORMANCE_INFO_GET_CALL: + { + return_value = _txm_module_manager_tx_timer_performance_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + case TXM_TIMER_PERFORMANCE_SYSTEM_INFO_GET_CALL: + { + return_value = _txm_module_manager_tx_timer_performance_system_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + case TXM_TRACE_BUFFER_FULL_NOTIFY_CALL: + { + return_value = _txm_module_manager_tx_trace_buffer_full_notify_dispatch(module_instance, param_0); + break; + } + + case TXM_TRACE_DISABLE_CALL: + { + return_value = _txm_module_manager_tx_trace_disable_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + case TXM_TRACE_ENABLE_CALL: + { + return_value = _txm_module_manager_tx_trace_enable_dispatch(module_instance, param_0, param_1, param_2); + break; + } + + case TXM_TRACE_EVENT_FILTER_CALL: + { + return_value = _txm_module_manager_tx_trace_event_filter_dispatch(module_instance, param_0); + break; + } + + case TXM_TRACE_EVENT_UNFILTER_CALL: + { + return_value = _txm_module_manager_tx_trace_event_unfilter_dispatch(module_instance, param_0); + break; + } + + case TXM_TRACE_INTERRUPT_CONTROL_CALL: + { + return_value = _txm_module_manager_tx_trace_interrupt_control_dispatch(module_instance, param_0); + break; + } + + case TXM_TRACE_ISR_ENTER_INSERT_CALL: + { + return_value = _txm_module_manager_tx_trace_isr_enter_insert_dispatch(module_instance, param_0); + break; + } + + case TXM_TRACE_ISR_EXIT_INSERT_CALL: + { + return_value = _txm_module_manager_tx_trace_isr_exit_insert_dispatch(module_instance, param_0); + break; + } + + case TXM_TRACE_USER_EVENT_INSERT_CALL: + { + return_value = _txm_module_manager_tx_trace_user_event_insert_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + case TXM_MODULE_OBJECT_ALLOCATE_CALL: + { + return_value = _txm_module_manager_txm_module_object_allocate_dispatch(module_instance, param_0, param_1); + break; + } + + case TXM_MODULE_OBJECT_DEALLOCATE_CALL: + { + return_value = _txm_module_manager_txm_module_object_deallocate_dispatch(module_instance, param_0); + break; + } + + case TXM_MODULE_OBJECT_POINTER_GET_CALL: + { + return_value = _txm_module_manager_txm_module_object_pointer_get_dispatch(module_instance, param_0, param_1, param_2); + break; + } + + case TXM_MODULE_OBJECT_POINTER_GET_EXTENDED_CALL: + { + return_value = _txm_module_manager_txm_module_object_pointer_get_extended_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); + break; + } + + default: + { + /* Determine if an application request is present. */ + if (kernel_request >= TXM_APPLICATION_REQUEST_ID_BASE) + { + /* Yes, call the module manager function that the application defines in order to + support application-specific requests. */ + return_value = (ALIGN_TYPE) _txm_module_manager_application_request(kernel_request-TXM_APPLICATION_REQUEST_ID_BASE, param_0, param_1, param_2); + } + +#ifdef TXM_MODULE_ENABLE_NETX + /* Determine if there is a NetX request. */ + else if ((kernel_request >= TXM_NETX_API_ID_START) && (kernel_request < TXM_NETX_API_ID_END)) + { + /* Call the NetX module dispatch function. */ + return_value = _txm_module_manager_netx_dispatch(module_instance, kernel_request, param_0, param_1, param_2); + } +#endif + +#ifdef TXM_MODULE_ENABLE_NETXDUO + /* Determine if there is a NetX Duo request. */ + else if ((kernel_request >= TXM_NETXDUO_API_ID_START) && (kernel_request < TXM_NETXDUO_API_ID_END)) + { + /* Call the NetX Duo module dispatch function. */ + return_value = _txm_module_manager_netxduo_dispatch(module_instance, kernel_request, param_0, param_1, param_2); + } +#endif + +#ifdef TXM_MODULE_ENABLE_FILEX + /* Determine if there is a FileX request. */ + else if ((kernel_request >= TXM_FILEX_API_ID_START) && (kernel_request < TXM_FILEX_API_ID_END)) + { + /* Call the FileX module dispatch function. */ + return_value = _txm_module_manager_filex_dispatch(module_instance, kernel_request, param_0, param_1, param_2); + } +#endif + +#ifdef TXM_MODULE_ENABLE_GUIX + /* Determine if there is a GUIX request. */ + else if ((kernel_request >= TXM_GUIX_API_ID_START) && (kernel_request < TXM_GUIX_API_ID_END)) + { + /* Call the GUIX module dispatch function. */ + return_value = _txm_module_manager_guix_dispatch(module_instance, kernel_request, param_0, param_1, param_2); + } +#endif + +#ifdef TXM_MODULE_ENABLE_USBX + /* Determine if there is a USBX request. */ + else if ((kernel_request >= TXM_USBX_API_ID_START) && (kernel_request < TXM_USBX_API_ID_END)) + { + /* Call the USBX dispatch function. */ + return_value = _txm_module_manager_usbx_dispatch(module_instance, kernel_request, param_0, param_1, param_2); + } +#endif + + /* Unhandled kernel request, return an error! */ + break; + } + } + + return(return_value); +} diff --git a/common_modules/module_manager/src/txm_module_manager_maximum_module_priority_set.c b/common_modules/module_manager/src/txm_module_manager_maximum_module_priority_set.c new file mode 100644 index 00000000..dff40f9d --- /dev/null +++ b/common_modules/module_manager/src/txm_module_manager_maximum_module_priority_set.c @@ -0,0 +1,116 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_mutex.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_maximum_module_priority_set PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets the maximum thread priority allowed in a module. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* priority Maximum thread priority */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_mutex_get Get protection mutex */ +/* _tx_mutex_put Release protection mutex */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_maximum_module_priority_set(TXM_MODULE_INSTANCE *module_instance, UINT priority) +{ + /* Determine if the module manager has not been initialized yet. */ + if (_txm_module_manager_ready != TX_TRUE) + { + /* Module manager has not been initialized. */ + return(TX_NOT_AVAILABLE); + } + + /* Determine if the module is valid. */ + if (module_instance == TX_NULL) + { + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Get module manager protection mutex. */ + _tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER); + + /* Determine if the module instance is valid. */ + if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Determine if the module instance is in the loaded state. */ + if ((module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) && (module_instance -> txm_module_instance_state != TXM_MODULE_STOPPED)) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not ready. */ + return(TX_START_ERROR); + } + + + /* Set module's maximum priority. */ + module_instance->txm_module_instance_maximum_priority = priority; + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + return(TX_SUCCESS); +} diff --git a/common_modules/module_manager/src/txm_module_manager_memory_load.c b/common_modules/module_manager/src/txm_module_manager_memory_load.c new file mode 100644 index 00000000..dba896e7 --- /dev/null +++ b/common_modules/module_manager/src/txm_module_manager_memory_load.c @@ -0,0 +1,162 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_mutex.h" +#include "tx_thread.h" +#include "tx_byte_pool.h" +#include "txm_module.h" +#include "txm_module_manager_util.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_load PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function allocates memory for module code and and calls */ +/* _txm_module_manager_internal_load to load the data and prepare the */ +/* module for execution. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* module_name Module name pointer */ +/* module_location Module code location */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_byte_allocate Allocate data area */ +/* _txm_module_manager_internal_load Load data and prepare module for */ +/* execution */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_memory_load(TXM_MODULE_INSTANCE *module_instance, CHAR *module_name, VOID *module_location) +{ + + +TXM_MODULE_PREAMBLE *module_preamble; +ALIGN_TYPE code_start; +ULONG code_size; +ULONG code_alignment; +ULONG code_allocation_size; +CHAR *code_memory_ptr; +UCHAR *source_ptr; +UCHAR *destination_ptr; +ULONG copy_size; +ULONG i; +UINT status; + + + /* Pickup the module's information. */ + module_preamble = (TXM_MODULE_PREAMBLE *) module_location; + + /* Pickup the basic module sizes. */ + code_size = module_preamble -> txm_module_preamble_code_size; + + /* Check for valid sizes. */ + if (code_size == 0) + { + + /* Invalid module preamble. */ + return(TXM_MODULE_INVALID); + } + + /* Get the amount of the bytes we need to allocate for the module's code as well as the required alignment. */ + status = _txm_module_manager_util_code_allocation_size_and_alignment_get(module_preamble, &code_alignment, &code_allocation_size); + if (status != TX_SUCCESS) + { + + /* Math overflow error occurred. */ + return(status); + } + + /* Allocate code memory for the module. */ + status = _tx_byte_allocate(&_txm_module_manager_byte_pool, (VOID **) &code_memory_ptr, code_allocation_size, TX_NO_WAIT); + + /* Determine if the module's code memory allocation was successful. */ + if (status != TX_SUCCESS) + { + + /* No memory, return an error. */ + return(TX_NO_MEMORY); + } + + /* Copy the module code into memory. */ + source_ptr = (UCHAR *) module_location; + code_start = (ALIGN_TYPE) code_memory_ptr; + code_start = (code_start + (code_alignment - 1)) & ~(code_alignment - 1); + destination_ptr = (UCHAR *) code_start; + + /* Calculate the size. */ + copy_size = module_preamble -> txm_module_preamble_code_size; + + /* Loop to copy the code to RAM. */ + for (i = 0; i < copy_size; i++) + { + + /* Copy one byte at a time. */ + *destination_ptr++ = *source_ptr++; + } + + /* At this point, the module's instruction area is now in the RAM code area. */ + + /* Now load it in-place. */ + status = _txm_module_manager_internal_load(module_instance, module_name, (VOID *) code_start, + code_size, code_memory_ptr, code_allocation_size); + if (status != TX_SUCCESS) + { + + /* Release code memory. */ + _tx_byte_release(code_memory_ptr); + + /* Return error. */ + return(status); + } + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/common_modules/module_manager/src/txm_module_manager_object_allocate.c b/common_modules/module_manager/src/txm_module_manager_object_allocate.c new file mode 100644 index 00000000..8b7dfadf --- /dev/null +++ b/common_modules/module_manager/src/txm_module_manager_object_allocate.c @@ -0,0 +1,155 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_object_allocate PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function allocates memory for an object from the memory pool */ +/* supplied to txm_module_manager_initialize. */ +/* */ +/* INPUT */ +/* */ +/* object_ptr Destination of object pointer on */ +/* successful allocation */ +/* object_size Size in bytes of the object to be */ +/* allocated */ +/* module_instance The module instance that the */ +/* object belongs to */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txe_mutex_get Get module instance mutex */ +/* _txe_mutex_put Release module instance mutex */ +/* _txe_byte_allocate Allocate object from pool */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_object_allocate(VOID **object_ptr_ptr, ULONG object_size, TXM_MODULE_INSTANCE *module_instance) +{ + +TXM_MODULE_ALLOCATED_OBJECT *object_ptr; +UINT return_value; + + + /* Ensure the object pointer pointer is valid. */ + if (object_ptr_ptr == (VOID **) TX_NULL) + { + + /* The object pointer pointer is invalid, return an error. */ + return(TXM_MODULE_INVALID_MEMORY); + } + + /* Initialize the return pointer to NULL. */ + *((VOID **) object_ptr_ptr) = TX_NULL; + + /* Get module manager protection mutex. */ + _txe_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER); + + /* Determine if an object pool was created. */ + if (_txm_module_manager_object_pool_created) + { + + TXM_MODULE_ALLOCATED_OBJECT *next_object, *previous_object; + + /* Allocate the object requested by the module - adding an extra ULONG in order to + store the module instance pointer. */ + return_value = (ULONG) _txe_byte_allocate(&_txm_module_manager_object_pool, (VOID **) &object_ptr, + (ULONG) (object_size + sizeof(TXM_MODULE_ALLOCATED_OBJECT)), TX_NO_WAIT); + + /* Determine if the request was successful. */ + if (return_value == TX_SUCCESS) + { + /* Yes, now store the module instance in the allocated memory block. */ + + /* Link the allocated memory to the module instance. */ + if (module_instance -> txm_module_instance_object_list_count++ == 0) + { + /* The allocated object list is empty. Add object to empty list. */ + module_instance -> txm_module_instance_object_list_head = object_ptr; + object_ptr -> txm_module_allocated_object_next = object_ptr; + object_ptr -> txm_module_allocated_object_previous = object_ptr; + } + else + { + /* This list is not NULL, add to the end of the list. */ + next_object = module_instance -> txm_module_instance_object_list_head; + previous_object = next_object -> txm_module_allocated_object_previous; + + /* Place the new object in the list. */ + next_object -> txm_module_allocated_object_previous = object_ptr; + previous_object -> txm_module_allocated_object_next = object_ptr; + + /* Setup this object's allocated links. */ + object_ptr -> txm_module_allocated_object_previous = previous_object; + object_ptr -> txm_module_allocated_object_next = next_object; + } + + /* Setup the module instance pointer in the allocated object. */ + object_ptr -> txm_module_allocated_object_module_instance = module_instance; + + /* Set the object size. */ + object_ptr -> txm_module_object_size = object_size; + + /* Move the object pointer forward. This is what the module is given. */ + object_ptr++; + + /* Return this pointer to the application. */ + *((VOID **) object_ptr_ptr) = object_ptr; + } + } + else + { + /* Set return value to not enabled. */ + return_value = TX_NOT_AVAILABLE; + } + + /* Release the protection mutex. */ + _txe_mutex_put(&_txm_module_manager_mutex); + + return(return_value); +} diff --git a/common_modules/module_manager/src/txm_module_manager_object_deallocate.c b/common_modules/module_manager/src/txm_module_manager_object_deallocate.c new file mode 100644 index 00000000..c2a40185 --- /dev/null +++ b/common_modules/module_manager/src/txm_module_manager_object_deallocate.c @@ -0,0 +1,138 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_object_deallocate PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function deallocates a previously allocated object. */ +/* */ +/* INPUT */ +/* */ +/* object_ptr Object pointer to deallocate */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txe_mutex_get Get module instance mutex */ +/* _txe_mutex_put Release module instance mutex */ +/* _txe_byte_release Release object back to pool */ +/* */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_object_deallocate(VOID *object_ptr) +{ +TXM_MODULE_INSTANCE *module_instance; +TXM_MODULE_ALLOCATED_OBJECT *module_allocated_object_ptr; +UINT return_value; + + /* Get module manager protection mutex. */ + _txe_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER); + + /* Determine if an object pool was created. */ + if (_txm_module_manager_object_pool_created) + { + + TXM_MODULE_ALLOCATED_OBJECT *next_object, *previous_object; + + /* Pickup module instance pointer. */ + module_instance = _tx_thread_current_ptr -> tx_thread_module_instance_ptr; + + /* Setup the memory pointer. */ + module_allocated_object_ptr = (TXM_MODULE_ALLOCATED_OBJECT *) object_ptr; + + /* Position the object pointer backwards to position back to the module manager information. */ + previous_object = module_allocated_object_ptr--; + + /* Make sure the object is valid. */ + if ((module_allocated_object_ptr == TX_NULL) || (module_allocated_object_ptr -> txm_module_allocated_object_module_instance != module_instance) || (module_instance -> txm_module_instance_object_list_count == 0)) + { + /* Set return value to invalid pointer. */ + return_value = TX_PTR_ERROR; + } + else + { + + /* Unlink the node. */ + if ((--module_instance -> txm_module_instance_object_list_count) == 0) + { + /* Only allocated object, just set the allocated list to NULL. */ + module_instance -> txm_module_instance_object_list_head = TX_NULL; + } + else + { + /* Otherwise, not the only allocated object, link-up the neighbors. */ + next_object = module_allocated_object_ptr -> txm_module_allocated_object_next; + previous_object = module_allocated_object_ptr -> txm_module_allocated_object_previous; + next_object -> txm_module_allocated_object_previous = previous_object; + previous_object -> txm_module_allocated_object_next = next_object; + + /* See if we have to update the allocated object list head pointer. */ + if (module_instance -> txm_module_instance_object_list_head == module_allocated_object_ptr) + { + /* Yes, move the head pointer to the next link. */ + module_instance -> txm_module_instance_object_list_head = next_object; + } + } + + /* Release the object memory. */ + return_value = (ULONG) _txe_byte_release((VOID *) module_allocated_object_ptr); + } + } + else + { + /* Set return value to not enabled. */ + return_value = TX_NOT_AVAILABLE; + } + + /* Release the protection mutex. */ + _txe_mutex_put(&_txm_module_manager_mutex); + + return(return_value); +} diff --git a/common_modules/module_manager/src/txm_module_manager_object_pointer_get.c b/common_modules/module_manager/src/txm_module_manager_object_pointer_get.c new file mode 100644 index 00000000..c1a95599 --- /dev/null +++ b/common_modules/module_manager/src/txm_module_manager_object_pointer_get.c @@ -0,0 +1,91 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "txm_module.h" +#include "txm_module_manager_util.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_object_pointer_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is deprecated and calls the secure version of this */ +/* function (_txm_module_manager_object_pointer_get_extended) with the */ +/* maximum possible name length since none was passed. */ +/* */ +/* INPUT */ +/* */ +/* object_type Type of object, as follows: */ +/* */ +/* TXM_BLOCK_POOL_OBJECT */ +/* TXM_BYTE_POOL_OBJECT */ +/* TXM_EVENT_FLAGS_OBJECT */ +/* TXM_MUTEX_OBJECT */ +/* TXM_QUEUE_OBJECT */ +/* TXM_SEMAPHORE_OBJECT */ +/* TXM_THREAD_OBJECT */ +/* TXM_TIMER_OBJECT */ +/* name Name to search for */ +/* object_ptr Pointer to the object */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SUCCESS Successful completion */ +/* TX_PTR_ERROR Invalid name or object ptr */ +/* TX_OPTION_ERROR Invalid option type */ +/* TX_NO_INSTANCE Object not found */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_manager_object_pointer_get_extended */ +/* Secure version of this function */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_object_pointer_get(UINT object_type, CHAR *name, VOID **object_ptr) +{ + +UINT status; + + /* Call the secure version of this function with the maximum length + possible since none was passed. */ + status = _txm_module_manager_object_pointer_get_extended(object_type, name, TXM_MODULE_MANAGER_UTIL_MAX_VALUE_OF_TYPE_UNSIGNED(UINT), object_ptr); + return(status); +} diff --git a/common_modules/module_manager/src/txm_module_manager_object_pointer_get_extended.c b/common_modules/module_manager/src/txm_module_manager_object_pointer_get_extended.c new file mode 100644 index 00000000..08583450 --- /dev/null +++ b/common_modules/module_manager/src/txm_module_manager_object_pointer_get_extended.c @@ -0,0 +1,506 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_timer.h" +#include "tx_queue.h" +#include "tx_event_flags.h" +#include "tx_semaphore.h" +#include "tx_mutex.h" +#include "tx_block_pool.h" +#include "tx_byte_pool.h" +#include "txm_module.h" +#include "txm_module_manager_util.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_object_pointer_get_extended PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves the object pointer of a particular type */ +/* with a particular name. If the object is not found, an error is */ +/* returned. Otherwise, if the object is found, the address of that */ +/* object is placed in object_ptr. */ +/* */ +/* INPUT */ +/* */ +/* object_type Type of object, as follows: */ +/* */ +/* TXM_BLOCK_POOL_OBJECT */ +/* TXM_BYTE_POOL_OBJECT */ +/* TXM_EVENT_FLAGS_OBJECT */ +/* TXM_MUTEX_OBJECT */ +/* TXM_QUEUE_OBJECT */ +/* TXM_SEMAPHORE_OBJECT */ +/* TXM_THREAD_OBJECT */ +/* TXM_TIMER_OBJECT */ +/* search_name Name to search for */ +/* search_name_length Length of the name excluding */ +/* null-terminator */ +/* object_ptr Pointer to the object */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SUCCESS Successful completion */ +/* TX_PTR_ERROR Invalid name or object ptr */ +/* TX_OPTION_ERROR Invalid option type */ +/* TX_NO_INSTANCE Object not found */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_manager_object_name_compare */ +/* String compare routine */ +/* [_txm_module_manager_*_object_pointer_get] */ +/* Optional external component */ +/* object pointer get */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_object_pointer_get_extended(UINT object_type, CHAR *search_name, UINT search_name_length, VOID **object_ptr) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_THREAD *thread_ptr; +TX_TIMER *timer_ptr; +TX_QUEUE *queue_ptr; +TX_EVENT_FLAGS_GROUP *events_ptr; +TX_SEMAPHORE *semaphore_ptr; +TX_MUTEX *mutex_ptr; +TX_BLOCK_POOL *block_pool_ptr; +TX_BYTE_POOL *byte_pool_ptr; +ULONG i; +UINT status; +TXM_MODULE_INSTANCE *module_instance; + + + /* Determine if the name or object pointer are NULL. */ + if ((search_name == TX_NULL) || (object_ptr == TX_NULL)) + { + + /* Return error! */ + return(TX_PTR_ERROR); + } + + /* Default status to not found. */ + status = TX_NO_INSTANCE; + + /* Set the return value to NULL. */ + *object_ptr = TX_NULL; + + /* Disable interrupts. */ + TX_DISABLE + + /* Temporarily disable preemption. This will keep other threads from creating and deleting threads. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Process relative to the object type. */ + switch(object_type) + { + + /* Determine if a thread object is requested. */ + case TXM_THREAD_OBJECT: + { + + /* Loop to find the first matching thread. */ + i = 0; + thread_ptr = _tx_thread_created_ptr; + while (i < _tx_thread_created_count) + { + + /* Do we have a match? */ + if (_txm_module_manager_object_name_compare(search_name, search_name_length, thread_ptr -> tx_thread_name)) + { + + /* Yes, we found it - return the necessary info! */ + *object_ptr = (VOID *) thread_ptr; + + /* Set the the status to success! */ + status = TX_SUCCESS; + break; + } + + /* Increment the counter. */ + i++; + + /* Move to next thread. */ + thread_ptr = thread_ptr -> tx_thread_created_next; + } + break; + } + + /* Determine if a timer object is requested. */ + case TXM_TIMER_OBJECT: + { + + /* Loop to find the first matching timer. */ + i = 0; + timer_ptr = _tx_timer_created_ptr; + while (i < _tx_timer_created_count) + { + + /* Do we have a match? */ + if (_txm_module_manager_object_name_compare(search_name, search_name_length, timer_ptr -> tx_timer_name)) + { + + /* Yes, we found it - return the necessary info! */ + *object_ptr = (VOID *) timer_ptr; + + /* Set the the status to success! */ + status = TX_SUCCESS; + break; + } + + /* Increment the counter. */ + i++; + + /* Move to next timer. */ + timer_ptr = timer_ptr -> tx_timer_created_next; + } + break; + } + + /* Determine if a queue object is requested. */ + case TXM_QUEUE_OBJECT: + { + + /* Loop to find the first matching queue. */ + i = 0; + queue_ptr = _tx_queue_created_ptr; + while (i < _tx_queue_created_count) + { + + /* Do we have a match? */ + if (_txm_module_manager_object_name_compare(search_name, search_name_length, queue_ptr -> tx_queue_name)) + { + + /* Yes, we found it - return the necessary info! */ + *object_ptr = (VOID *) queue_ptr; + + /* Set the the status to success! */ + status = TX_SUCCESS; + break; + } + + /* Increment the counter. */ + i++; + + /* Move to next queue. */ + queue_ptr = queue_ptr -> tx_queue_created_next; + } + break; + } + + /* Determine if a event flags object is requested. */ + case TXM_EVENT_FLAGS_OBJECT: + { + + /* Loop to find the first matching event flags group. */ + i = 0; + events_ptr = _tx_event_flags_created_ptr; + while (i < _tx_event_flags_created_count) + { + + /* Do we have a match? */ + if (_txm_module_manager_object_name_compare(search_name, search_name_length, events_ptr -> tx_event_flags_group_name)) + { + + /* Yes, we found it - return the necessary info! */ + *object_ptr = (VOID *) events_ptr; + + /* Set the the status to success! */ + status = TX_SUCCESS; + break; + } + + /* Increment the counter. */ + i++; + + /* Move to next event flags group. */ + events_ptr = events_ptr -> tx_event_flags_group_created_next; + } + break; + } + + /* Determine if a semaphore object is requested. */ + case TXM_SEMAPHORE_OBJECT: + { + + /* Loop to find the first matching semaphore. */ + i = 0; + semaphore_ptr = _tx_semaphore_created_ptr; + while (i < _tx_semaphore_created_count) + { + + /* Do we have a match? */ + if (_txm_module_manager_object_name_compare(search_name, search_name_length, semaphore_ptr -> tx_semaphore_name)) + { + + /* Yes, we found it - return the necessary info! */ + *object_ptr = (VOID *) semaphore_ptr; + + /* Set the the status to success! */ + status = TX_SUCCESS; + break; + } + + /* Increment the counter. */ + i++; + + /* Move to next semaphore. */ + semaphore_ptr = semaphore_ptr -> tx_semaphore_created_next; + } + break; + } + + /* Determine if a mutex object is requested. */ + case TXM_MUTEX_OBJECT: + { + + /* Loop to find the first matching mutex. */ + i = 0; + mutex_ptr = _tx_mutex_created_ptr; + while (i < _tx_mutex_created_count) + { + + /* Do we have a match? */ + if (_txm_module_manager_object_name_compare(search_name, search_name_length, mutex_ptr -> tx_mutex_name)) + { + + /* Yes, we found it - return the necessary info! */ + *object_ptr = (VOID *) mutex_ptr; + + /* Set the the status to success! */ + status = TX_SUCCESS; + break; + } + + /* Increment the counter. */ + i++; + + /* Move to next mutex. */ + mutex_ptr = mutex_ptr -> tx_mutex_created_next; + } + break; + } + + /* Determine if a block pool object is requested. */ + case TXM_BLOCK_POOL_OBJECT: + { + + /* Get the module instance. */ + module_instance = _tx_thread_current_ptr -> tx_thread_module_instance_ptr; + + /* Is a module making this request? */ + if (module_instance != TX_NULL) + { + + /* Is memory protection enabled? */ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + + /* Modules with memory protection can only access block pools they created. */ + status = TXM_MODULE_INVALID; + break; + } + } + + /* Loop to find the first matching block pool. */ + i = 0; + block_pool_ptr = _tx_block_pool_created_ptr; + while (i < _tx_block_pool_created_count) + { + + /* Do we have a match? */ + if (_txm_module_manager_object_name_compare(search_name, search_name_length, block_pool_ptr -> tx_block_pool_name)) + { + + /* Yes, we found it - return the necessary info! */ + *object_ptr = (VOID *) block_pool_ptr; + + /* Set the the status to success! */ + status = TX_SUCCESS; + break; + } + + /* Increment the counter. */ + i++; + + /* Move to next block pool. */ + block_pool_ptr = block_pool_ptr -> tx_block_pool_created_next; + } + break; + } + + /* Determine if a byte pool object is requested. */ + case TXM_BYTE_POOL_OBJECT: + { + + /* Get the module instance. */ + module_instance = _tx_thread_current_ptr -> tx_thread_module_instance_ptr; + + /* Is a module making this request? */ + if (module_instance != TX_NULL) + { + + /* Is memory protection enabled? */ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + + /* Modules with memory protection can only access block pools they created. */ + status = TXM_MODULE_INVALID; + break; + } + } + + /* Loop to find the first matching byte pool. */ + i = 0; + byte_pool_ptr = _tx_byte_pool_created_ptr; + while (i < _tx_byte_pool_created_count) + { + + /* Do we have a match? */ + if (_txm_module_manager_object_name_compare(search_name, search_name_length, byte_pool_ptr -> tx_byte_pool_name)) + { + + /* Yes, we found it - return the necessary info! */ + *object_ptr = (VOID *) byte_pool_ptr; + + /* Set the the status to success! */ + status = TX_SUCCESS; + break; + } + + /* Increment the counter. */ + i++; + + /* Move to next byte pool. */ + byte_pool_ptr = byte_pool_ptr -> tx_byte_pool_created_next; + } + break; + } + + default: + + /* Invalid object ID. */ + status = TX_OPTION_ERROR; + + /* External Object pointer get. */ + +#ifdef TXM_MODULE_ENABLE_NETX + + /* Determine if there is a NetX object get request. */ + if ((object_type >= TXM_NETX_OBJECTS_START) && (object_type < TXM_NETX_OBJECTS_END)) + { + + /* Call the NetX module object get function. */ + status = _txm_module_manager_netx_object_pointer_get(object_type, search_name, search_name_length, object_ptr); + } +#endif + +#ifdef TXM_MODULE_ENABLE_NETXDUO + + /* Determine if there is a NetX Duo object get request. */ + if ((object_type >= TXM_NETXDUO_OBJECTS_START) && (object_type < TXM_NETXDUO_OBJECTS_END)) + { + + /* Call the NetX Duo module object get function. */ + status = _txm_module_manager_netxduo_object_pointer_get(object_type, search_name, search_name_length, object_ptr); + } +#endif + +#ifdef TXM_MODULE_ENABLE_FILEX + + /* Determine if there is a FileX object get request. */ + if ((object_type >= TXM_FILEX_OBJECTS_START) && (object_type < TXM_FILEX_OBJECTS_END)) + { + + /* Call the FileX module object get function. */ + status = _txm_module_manager_filex_object_pointer_get(object_type, search_name, search_name_length, object_ptr); + } +#endif + + +#ifdef TXM_MODULE_ENABLE_GUIX + + /* Determine if there is a GUIX object get request. */ + if ((object_type >= TXM_GUIX_OBJECTS_START) && (object_type < TXM_GUIX_OBJECTS_END)) + { + + /* Call the GUIX module object get function. */ + status = _txm_module_manager_guix_object_pointer_get(object_type, search_name, search_name_length, object_ptr); + } +#endif + +#ifdef TXM_MODULE_ENABLE_USBX + + /* Determine if there is a USBX object get request. */ + if ((object_type >= TXM_USBX_OBJECTS_START) && (object_type < TXM_USBX_OBJECTS_END)) + { + + /* Call the USBX object get function. */ + status = _txm_module_manager_usbx_object_pointer_get(object_type, search_name, search_name_length, object_ptr); + } +#endif + + break; + } + + /* Disable interrupts. */ + TX_DISABLE + + /* Enable preemption again. */ + _tx_thread_preempt_disable--; + + /* Restore interrupts. */ + TX_RESTORE + + /* Check for preemption. */ + _tx_thread_system_preempt_check(); + + /* Return success. */ + return(status); +} diff --git a/common_modules/module_manager/src/txm_module_manager_object_pool_create.c b/common_modules/module_manager/src/txm_module_manager_object_pool_create.c new file mode 100644 index 00000000..9794ec98 --- /dev/null +++ b/common_modules/module_manager/src/txm_module_manager_object_pool_create.c @@ -0,0 +1,82 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" +#include "tx_byte_pool.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* txm_module_manager_object_pool_create PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates an object pool for the module manager, */ +/* which is used by modules to allocate system resources outside */ +/* the memory area of the module. This is especially useful in */ +/* memory protection. */ +/* */ +/* INPUT */ +/* */ +/* object_memory Object memory address */ +/* object_memory_size Size in bytes of memory area */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_byte_pool_create Create module memory byte pool */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_object_pool_create(VOID *object_memory, ULONG object_memory_size) +{ + + /* Create a byte pool for allocating RAM areas for modules. */ + _tx_byte_pool_create(&_txm_module_manager_object_pool, "Module Manager Object Pool", object_memory, object_memory_size); + + /* Indicate the module manager object pool has been created. */ + _txm_module_manager_object_pool_created = TX_TRUE; + + /* Return success. */ + return(TX_SUCCESS); +} + diff --git a/common_modules/module_manager/src/txm_module_manager_properties_get.c b/common_modules/module_manager/src/txm_module_manager_properties_get.c new file mode 100644 index 00000000..f2f803c5 --- /dev/null +++ b/common_modules/module_manager/src/txm_module_manager_properties_get.c @@ -0,0 +1,106 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_properties_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function returns the properties of the specified module so they*/ +/* may be checked before executing the module. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_properties_get(TXM_MODULE_INSTANCE *module_instance, ULONG *module_properties_ptr) +{ + + /* Determine if the module manager has not been initialized yet. */ + if (_txm_module_manager_ready != TX_TRUE) + { + + /* Module manager has not been initialized. */ + return(TX_NOT_AVAILABLE); + } + + /* Determine if the module is valid. */ + if (module_instance == TX_NULL) + { + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Check the module ID. */ + if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) + { + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Check for non-null buffer. */ + if (module_properties_ptr == TX_NULL) + { + + /* Invalid buffer pointer. */ + return(TX_PTR_ERROR); + } + + /* Simply return the property bitmap. */ + *module_properties_ptr = module_instance -> txm_module_instance_property_flags; + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/common_modules/module_manager/src/txm_module_manager_queue_notify_trampoline.c b/common_modules/module_manager/src/txm_module_manager_queue_notify_trampoline.c new file mode 100644 index 00000000..50166517 --- /dev/null +++ b/common_modules/module_manager/src/txm_module_manager_queue_notify_trampoline.c @@ -0,0 +1,132 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_queue.h" +#include "tx_thread.h" +#include "txm_module.h" + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_queue_notify_trampoline PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the queue notification call from ThreadX. */ +/* */ +/* INPUT */ +/* */ +/* queue_ptr Queue pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_manager_callback_request Send module callback request */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_queue_notify_trampoline(TX_QUEUE *queue_ptr) +{ + +TX_INTERRUPT_SAVE_AREA + +TXM_MODULE_INSTANCE *module_instance; +TXM_MODULE_CALLBACK_MESSAGE callback_message; +TX_QUEUE *module_callback_queue; + + + /* We now know the callback is for a module. */ + + /* Disable interrupts. */ + TX_DISABLE + + /* Pickup the module instance pointer. */ + module_instance = (TXM_MODULE_INSTANCE *) queue_ptr -> tx_queue_module_instance; + + /* Determine if this module is still valid. */ + if ((module_instance) && (module_instance -> txm_module_instance_id == TXM_MODULE_ID) && + (module_instance -> txm_module_instance_state == TXM_MODULE_STARTED)) + { + + /* Yes, the module is still valid. */ + + /* Pickup the module's callback message queue. */ + module_callback_queue = &(module_instance -> txm_module_instance_callback_request_queue); + + /* Build the queue notification message. */ + callback_message.txm_module_callback_message_type = TXM_QUEUE_SEND_CALLBACK; + callback_message.txm_module_callback_message_activation_count = 1; + callback_message.txm_module_callback_message_application_function = (VOID (*)(VOID)) queue_ptr -> tx_queue_send_module_notify; + callback_message.txm_module_callback_message_param_1 = (ALIGN_TYPE) queue_ptr; + callback_message.txm_module_callback_message_param_2 = 0; + callback_message.txm_module_callback_message_param_3 = 0; + callback_message.txm_module_callback_message_param_4 = 0; + callback_message.txm_module_callback_message_param_5 = 0; + callback_message.txm_module_callback_message_param_6 = 0; + callback_message.txm_module_callback_message_param_7 = 0; + callback_message.txm_module_callback_message_param_8 = 0; + callback_message.txm_module_callback_message_reserved1 = 0; + callback_message.txm_module_callback_message_reserved2 = 0; + + /* Restore interrupts. */ + TX_RESTORE + + /* Call the general processing that will place the callback on the + module's callback request queue. */ + _txm_module_manager_callback_request(module_callback_queue, &callback_message); + } + else + { + + /* Module no longer valid. */ + + /* Error, increment the error counter and return. */ + _txm_module_manager_callback_error_count++; + + /* Restore interrupts. */ + TX_RESTORE + } +} +#endif + + diff --git a/common_modules/module_manager/src/txm_module_manager_semaphore_notify_trampoline.c b/common_modules/module_manager/src/txm_module_manager_semaphore_notify_trampoline.c new file mode 100644 index 00000000..78f6f157 --- /dev/null +++ b/common_modules/module_manager/src/txm_module_manager_semaphore_notify_trampoline.c @@ -0,0 +1,131 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_queue.h" +#include "tx_thread.h" +#include "txm_module.h" + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_semaphore_notify_trampoline PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the semaphore put notification call from */ +/* ThreadX. */ +/* */ +/* INPUT */ +/* */ +/* semaphore_ptr Semaphore pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_manager_callback_request Send module callback request */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_semaphore_notify_trampoline(TX_SEMAPHORE *semaphore_ptr) +{ + +TX_INTERRUPT_SAVE_AREA + +TXM_MODULE_INSTANCE *module_instance; +TXM_MODULE_CALLBACK_MESSAGE callback_message; +TX_QUEUE *module_callback_queue; + + + /* We now know the callback is for a module. */ + + /* Disable interrupts. */ + TX_DISABLE + + /* Pickup the module instance pointer. */ + module_instance = (TXM_MODULE_INSTANCE *) semaphore_ptr -> tx_semaphore_module_instance; + + /* Determine if this module is still valid. */ + if ((module_instance) && (module_instance -> txm_module_instance_id == TXM_MODULE_ID) && + (module_instance -> txm_module_instance_state == TXM_MODULE_STARTED)) + { + + /* Yes, the module is still valid. */ + + /* Pickup the module's callback message queue. */ + module_callback_queue = &(module_instance -> txm_module_instance_callback_request_queue); + + /* Build the queue notification message. */ + callback_message.txm_module_callback_message_type = TXM_SEMAPHORE_PUT_CALLBACK; + callback_message.txm_module_callback_message_activation_count = 1; + callback_message.txm_module_callback_message_application_function = (VOID (*)(VOID)) semaphore_ptr -> tx_semaphore_put_module_notify; + callback_message.txm_module_callback_message_param_1 = (ALIGN_TYPE) semaphore_ptr; + callback_message.txm_module_callback_message_param_2 = 0; + callback_message.txm_module_callback_message_param_3 = 0; + callback_message.txm_module_callback_message_param_4 = 0; + callback_message.txm_module_callback_message_param_5 = 0; + callback_message.txm_module_callback_message_param_6 = 0; + callback_message.txm_module_callback_message_param_7 = 0; + callback_message.txm_module_callback_message_param_8 = 0; + callback_message.txm_module_callback_message_reserved1 = 0; + callback_message.txm_module_callback_message_reserved2 = 0; + + /* Restore interrupts. */ + TX_RESTORE + + /* Call the general processing that will place the callback on the + module's callback request queue. */ + _txm_module_manager_callback_request(module_callback_queue, &callback_message); + } + else + { + + /* Module no longer valid. */ + + /* Error, increment the error counter and return. */ + _txm_module_manager_callback_error_count++; + + /* Restore interrupts. */ + TX_RESTORE + } +} +#endif diff --git a/common_modules/module_manager/src/txm_module_manager_start.c b/common_modules/module_manager/src/txm_module_manager_start.c new file mode 100644 index 00000000..df689247 --- /dev/null +++ b/common_modules/module_manager/src/txm_module_manager_start.c @@ -0,0 +1,226 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_mutex.h" +#include "tx_queue.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_start PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function starts execution of the specified module. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_manager_name_build Build module:thread name */ +/* _txm_module_manager_thread_create Module thread create */ +/* _tx_mutex_get Get protection mutex */ +/* _tx_mutex_put Release protection mutex */ +/* _tx_queue_create Create module callback queue */ +/* _tx_queue_delete Delete module callback queue */ +/* _tx_thread_resume Resume start thread */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_start(TXM_MODULE_INSTANCE *module_instance) +{ + +UINT status; + + + /* Determine if the module manager has not been initialized yet. */ + if (_txm_module_manager_ready != TX_TRUE) + { + + /* Module manager has not been initialized. */ + return(TX_NOT_AVAILABLE); + } + + /* Determine if the module is valid. */ + if (module_instance == TX_NULL) + { + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Get module manager protection mutex. */ + _tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER); + + /* Determine if the module instance is valid. */ + if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) + { + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Determine if the module instance is in the loaded state. */ + if ((module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) && (module_instance -> txm_module_instance_state != TXM_MODULE_STOPPED)) + { + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not ready. */ + return(TX_START_ERROR); + } + + /* Check the priorities of the start/stop and callback request threads. */ + if (module_instance -> txm_module_instance_start_stop_priority < module_instance -> txm_module_instance_maximum_priority || + module_instance -> txm_module_instance_callback_priority < module_instance -> txm_module_instance_maximum_priority) + { + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* At least one thread has an invalid priority. */ + return(TX_PRIORITY_ERROR); + } + + /* Create the module's callback request queue. */ + status = _tx_queue_create(&(module_instance -> txm_module_instance_callback_request_queue), "Module Callback Request Queue", (sizeof(TXM_MODULE_CALLBACK_MESSAGE)/sizeof(ULONG)), + module_instance -> txm_module_instance_callback_request_queue_area, sizeof(module_instance -> txm_module_instance_callback_request_queue_area)); + + /* Determine if there was an error. */ + if (status) + { + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not ready. */ + return(TX_START_ERROR); + } + + /* Create the module start thread. */ + status = _txm_module_manager_thread_create(&(module_instance -> txm_module_instance_start_stop_thread), + "Module Start Thread", + module_instance -> txm_module_instance_shell_entry_function, + module_instance -> txm_module_instance_start_thread_entry, + module_instance -> txm_module_instance_application_module_id, + module_instance -> txm_module_instance_start_stop_stack_start_address, + module_instance -> txm_module_instance_start_stop_stack_size, + (UINT) module_instance -> txm_module_instance_start_stop_priority, + (UINT) module_instance -> txm_module_instance_start_stop_priority, + TXM_MODULE_TIME_SLICE, + TX_DONT_START, + sizeof(TX_THREAD), + module_instance); + + /* Determine if the thread create was successful. */ + if (status != TX_SUCCESS) + { + + /* Delete the callback notification queue. */ + _tx_queue_delete(&(module_instance -> txm_module_instance_callback_request_queue)); + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return the error status. */ + return(status); + } + + /* Create the module callback thread. */ + status = _txm_module_manager_thread_create(&(module_instance -> txm_module_instance_callback_request_thread), + "Module Callback Request Thread", + module_instance -> txm_module_instance_shell_entry_function, + module_instance -> txm_module_instance_callback_request_thread_entry, + module_instance -> txm_module_instance_application_module_id, + module_instance -> txm_module_instance_callback_stack_start_address, + module_instance -> txm_module_instance_callback_stack_size, + (UINT) module_instance -> txm_module_instance_callback_priority, + (UINT) module_instance -> txm_module_instance_callback_priority, + TX_NO_TIME_SLICE, + TX_DONT_START, + sizeof(TX_THREAD), + module_instance); + + /* Determine if the thread create was successful. */ + if (status != TX_SUCCESS) + { + + /* Terminate the start thread. */ + _tx_thread_terminate(&(module_instance -> txm_module_instance_start_stop_thread)); + + /* Delete the start thread. */ + _tx_thread_delete(&(module_instance -> txm_module_instance_start_stop_thread)); + + /* Delete the callback notification queue. */ + _tx_queue_delete(&(module_instance -> txm_module_instance_callback_request_queue)); + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return the error status. */ + return(status); + } + + + /* Set the module state to started. */ + module_instance -> txm_module_instance_state = TXM_MODULE_STARTED; + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Resume the module's start thread. */ + _tx_thread_resume(&(module_instance -> txm_module_instance_start_stop_thread)); + + /* Return success. */ + return(TX_SUCCESS); +} + diff --git a/common_modules/module_manager/src/txm_module_manager_stop.c b/common_modules/module_manager/src/txm_module_manager_stop.c new file mode 100644 index 00000000..b9682a1d --- /dev/null +++ b/common_modules/module_manager/src/txm_module_manager_stop.c @@ -0,0 +1,571 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_timer.h" +#include "tx_queue.h" +#include "tx_event_flags.h" +#include "tx_semaphore.h" +#include "tx_mutex.h" +#include "tx_block_pool.h" +#include "tx_byte_pool.h" +#include "txm_module.h" +#include "txm_module_manager_util.h" + +#ifdef TXM_MODULE_ENABLE_FILEX +extern UINT _txm_module_manager_filex_stop(TXM_MODULE_INSTANCE *module_instance); +#endif + +#ifdef TXM_MODULE_ENABLE_NETX +extern UINT _txm_module_manager_netx_stop(TXM_MODULE_INSTANCE *module_instance); +#endif + +#ifdef TXM_MODULE_ENABLE_NETXDUO +extern UINT _txm_module_manager_netxduo_stop(TXM_MODULE_INSTANCE *module_instance); +#endif + +#ifdef TXM_MODULE_ENABLE_GUIX +extern UINT _txm_module_manager_guix_stop(TXM_MODULE_INSTANCE *module_instance); +#endif + +#ifdef TXM_MODULE_ENABLE_USBX +extern UINT _txm_module_manager_usbx_stop(TXM_MODULE_INSTANCE *module_instance); +#endif + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_stop PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function stops execution of the specified module. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_block_pool_delete Block pool delete */ +/* _tx_byte_pool_delete Byte pool delete */ +/* _tx_event_flags_delete Event flags delete */ +/* _tx_mutex_delete Mutex delete */ +/* _tx_mutex_get Get protection mutex */ +/* _tx_mutex_put Release protection mutex */ +/* _tx_queue_delete Queue delete */ +/* _tx_semaphore_delete Semaphore delete */ +/* _tx_thread_delete Thread delete */ +/* _tx_thread_sleep Thread sleep */ +/* _tx_thread_system_preempt_check Check for preemption */ +/* _tx_thread_terminate Thread terminate */ +/* _tx_timer_delete Timer delete */ +/* _txm_module_manager_callback_deactivate */ +/* Deactivate callback */ +/* _txm_module_manager_object_search Search for object in module's */ +/* allocated object list */ +/* _txm_module_manager_thread_create Module thread create */ +/* [_txm_module_manager_*_stop] Optional external component */ +/* stop functions */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_stop(TXM_MODULE_INSTANCE *module_instance) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_THREAD *thread_ptr, *next_thread_ptr; +TX_TIMER *timer_ptr, *next_timer_ptr; +TX_QUEUE *queue_ptr, *next_queue_ptr; +TX_EVENT_FLAGS_GROUP *events_ptr, *next_events_ptr; +TX_SEMAPHORE *semaphore_ptr, *next_semaphore_ptr; +TX_MUTEX *mutex_ptr, *next_mutex_ptr; +TX_BLOCK_POOL *block_pool_ptr, *next_block_pool_ptr; +TX_BYTE_POOL *byte_pool_ptr, *next_byte_pool_ptr; +UCHAR created_by_module; +ULONG i; +TXM_MODULE_ALLOCATED_OBJECT *object_ptr; + + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr) + + /* Determine if this is a legal request. */ + + /* Is there a current thread? */ + if (thread_ptr == TX_NULL) + { + + /* Illegal caller of this service. */ + return(TX_CALLER_ERROR); + } + + /* Is the caller an ISR or Initialization? */ + if (TX_THREAD_GET_SYSTEM_STATE() != 0) + { + + /* Illegal caller of this service. */ + return(TX_CALLER_ERROR); + } + +#ifndef TX_TIMER_PROCESS_IN_ISR + + /* Check for invalid caller of this function. First check for a calling thread. */ + if (thread_ptr == &_tx_timer_thread) + { + + /* Invalid caller of this function, return appropriate error code. */ + return(TX_CALLER_ERROR); + } +#endif + + /* Determine if the module manager has not been initialized yet. */ + if (_txm_module_manager_ready != TX_TRUE) + { + + /* Module manager has not been initialized. */ + return(TX_NOT_AVAILABLE); + } + + /* Determine if the module is valid. */ + if (module_instance == TX_NULL) + { + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Get module manager protection mutex. */ + _tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER); + + /* Determine if the module instance is valid. */ + if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) + { + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Determine if the module instance is in the loaded state. */ + if (module_instance -> txm_module_instance_state != TXM_MODULE_STARTED) + { + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not ready. */ + return(TX_START_ERROR); + } + + /* Set the module state to indicate the module is stopping. */ + module_instance -> txm_module_instance_state = TXM_MODULE_STOPPING; + + /* This thread was previously used as the start thread. So first, make sure it is terminated and deleted before doing anything else. */ + _tx_thread_terminate(&(module_instance -> txm_module_instance_start_stop_thread)); + _tx_thread_delete(&(module_instance -> txm_module_instance_start_stop_thread)); + + /* Determine if there is a module stop function. */ + if (module_instance -> txm_module_instance_stop_thread_entry) + { + + /* Yes, there is a stop function. Build a thread for executing the module stop function. */ + + /* Create the module stop thread. */ + _txm_module_manager_thread_create(&(module_instance -> txm_module_instance_start_stop_thread), + "Module Stop Thread", + module_instance -> txm_module_instance_shell_entry_function, + module_instance -> txm_module_instance_stop_thread_entry, + module_instance -> txm_module_instance_application_module_id, + module_instance -> txm_module_instance_start_stop_stack_start_address, + module_instance -> txm_module_instance_start_stop_stack_size, + (UINT) module_instance -> txm_module_instance_start_stop_priority, + (UINT) module_instance -> txm_module_instance_start_stop_priority, + TXM_MODULE_TIME_SLICE, + TX_AUTO_START, + sizeof(TX_THREAD), + module_instance); + + /* Wait for the stop thread to complete. */ + i = 0; + while ((i < TXM_MODULE_TIMEOUT) && (module_instance -> txm_module_instance_start_stop_thread.tx_thread_state != TX_COMPLETED)) + { + + /* Sleep to let the module stop thread run. */ + _tx_thread_sleep(1); + + /* Increment the counter. */ + i++; + } + + /* At this point, we need to terminate and delete the stop thread. */ + _tx_thread_terminate(&(module_instance -> txm_module_instance_start_stop_thread)); + _tx_thread_delete(&(module_instance -> txm_module_instance_start_stop_thread)); + } + + /* Delete the module's callback thread and queue for the callback thread. */ + _tx_thread_terminate(&(module_instance -> txm_module_instance_callback_request_thread)); + _tx_thread_delete(&(module_instance -> txm_module_instance_callback_request_thread)); + _tx_queue_delete(&(module_instance -> txm_module_instance_callback_request_queue)); + + /* Disable interrupts. */ + TX_DISABLE + + /* Temporarily disable preemption. This will keep other threads from creating and deleting threads. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Determine if any external component stop functions have been registered and + if so, call them to cleanup any module objects in that component. */ + +#ifdef TXM_MODULE_ENABLE_FILEX + + /* Call the FileX stop function. */ + _txm_module_manager_filex_stop(module_instance); +#endif + +#ifdef TXM_MODULE_ENABLE_NETX + + /* Call the NetX stop function. */ + _txm_module_manager_netx_stop(module_instance); +#endif + +#ifdef TXM_MODULE_ENABLE_NETXDUO + + /* Call the NetX Duo stop function. */ + _txm_module_manager_netxduo_stop(module_instance); +#endif + +#ifdef TXM_MODULE_ENABLE_GUIX + + /* Call the GUIX stop function. */ + _txm_module_manager_guix_stop(module_instance); +#endif + +#ifdef TXM_MODULE_ENABLE_USBX + + /* Call the USBX stop function. */ + _txm_module_manager_usbx_stop(module_instance); +#endif + + /* Loop to delete any and all threads created by the module. */ + i = _tx_thread_created_count; + thread_ptr = _tx_thread_created_ptr; + while (i--) + { + + /* Pickup the next thread pointer. */ + next_thread_ptr = thread_ptr -> tx_thread_created_next; + + /* Determine if the thread control block is inside the module. */ + if ( (((CHAR *) thread_ptr) >= ((CHAR *) module_instance -> txm_module_instance_data_start)) && + (((CHAR *) thread_ptr) < ((CHAR *) module_instance -> txm_module_instance_data_end))) + { + + /* Terminate and delete this thread, since it is part of this module. */ + _tx_thread_terminate(thread_ptr); + _tx_thread_delete(thread_ptr); + } + + /* Is this thread part of the module? */ + else if (thread_ptr -> tx_thread_module_instance_ptr == module_instance) + { + + /* Terminate and delete this thread, since it is part of this module. */ + _tx_thread_terminate(thread_ptr); + _tx_thread_delete(thread_ptr); + } + + /* Move to next thread. */ + thread_ptr = next_thread_ptr; + } + + /* Loop to delete any and all timers created by the module. */ + i = _tx_timer_created_count; + timer_ptr = _tx_timer_created_ptr; + while (i--) + { + + /* Pickup the next timer pointer. */ + next_timer_ptr = timer_ptr -> tx_timer_created_next; + + /* Check if this module created this timer. */ + created_by_module = _txm_module_manager_created_object_check(module_instance, (VOID *) timer_ptr); + if (created_by_module == TX_TRUE) + { + + /* Delete this timer, since it is part of this module. */ + _tx_timer_delete(timer_ptr); + } + + /* Move to next timer. */ + timer_ptr = next_timer_ptr; + } + + /* Loop to delete any and all queues created by the module. */ + i = _tx_queue_created_count; + queue_ptr = _tx_queue_created_ptr; + while (i--) + { + + /* Pickup the next queue pointer. */ + next_queue_ptr = queue_ptr -> tx_queue_created_next; + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Determine if the queue callback function is associated with this module. */ + if ((queue_ptr -> tx_queue_module_instance == module_instance) && + (queue_ptr -> tx_queue_send_notify == _txm_module_manager_queue_notify_trampoline)) + { + + /* Clear the callback notification for this queue since it is no longer valid. */ + queue_ptr -> tx_queue_send_notify = TX_NULL; + } +#endif + + /* Check if this module created this queue. */ + created_by_module = _txm_module_manager_created_object_check(module_instance, (VOID *) queue_ptr); + if (created_by_module == TX_TRUE) + { + + /* Delete this queue, since it is part of this module. */ + _tx_queue_delete(queue_ptr); + } + + /* Move to next queue. */ + queue_ptr = next_queue_ptr; + } + + /* Loop to delete any and all event flag groups created by the module. */ + i = _tx_event_flags_created_count; + events_ptr = _tx_event_flags_created_ptr; + while (i--) + { + + /* Pickup the next event flags group pointer. */ + next_events_ptr = events_ptr -> tx_event_flags_group_created_next; + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Determine if the event flags callback function is associated with this module. */ + if ((events_ptr -> tx_event_flags_group_module_instance == module_instance) && + (events_ptr -> tx_event_flags_group_set_notify == _txm_module_manager_event_flags_notify_trampoline)) + { + + /* Clear the callback notification for this event flag group since it is no longer valid. */ + events_ptr -> tx_event_flags_group_set_notify = TX_NULL; + } +#endif + + /* Check if this module created this event flags. */ + created_by_module = _txm_module_manager_created_object_check(module_instance, (VOID *) events_ptr); + if (created_by_module == TX_TRUE) + { + + /* Delete this event flags group, since it is part of this module. */ + _tx_event_flags_delete(events_ptr); + } + + /* Move to next event flags group. */ + events_ptr = next_events_ptr; + } + + /* Loop to delete any and all semaphores created by the module. */ + i = _tx_semaphore_created_count; + semaphore_ptr = _tx_semaphore_created_ptr; + while (i--) + { + + /* Pickup the next semaphore pointer. */ + next_semaphore_ptr = semaphore_ptr -> tx_semaphore_created_next; + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Determine if the semaphore callback function is associated with this module. */ + if ((semaphore_ptr -> tx_semaphore_module_instance == module_instance) && + (semaphore_ptr -> tx_semaphore_put_notify == _txm_module_manager_semaphore_notify_trampoline)) + { + + /* Clear the callback notification for this semaphore since it is no longer valid. */ + semaphore_ptr -> tx_semaphore_put_notify = TX_NULL; + } +#endif + + /* Check if this module created this semaphore. */ + created_by_module = _txm_module_manager_created_object_check(module_instance, (VOID *) semaphore_ptr); + if (created_by_module == TX_TRUE) + { + + /* Delete this semaphore, since it is part of this module. */ + _tx_semaphore_delete(semaphore_ptr); + } + + /* Move to next semaphore. */ + semaphore_ptr = next_semaphore_ptr; + } + + /* Loop to delete any and all mutexes created by the module. */ + i = _tx_mutex_created_count; + mutex_ptr = _tx_mutex_created_ptr; + while (i--) + { + + /* Pickup the next mutex pointer. */ + next_mutex_ptr = mutex_ptr -> tx_mutex_created_next; + + /* Check if this module created this mutex. */ + created_by_module = _txm_module_manager_created_object_check(module_instance, (VOID *) mutex_ptr); + if (created_by_module == TX_TRUE) + { + + /* Delete this mutex, since it is part of this module. */ + _tx_mutex_delete(mutex_ptr); + } + + /* Move to next mutex. */ + mutex_ptr = next_mutex_ptr; + } + + /* Loop to delete any and all block pools created by the module. */ + i = _tx_block_pool_created_count; + block_pool_ptr = _tx_block_pool_created_ptr; + while (i--) + { + + /* Pickup the next block pool pointer. */ + next_block_pool_ptr = block_pool_ptr -> tx_block_pool_created_next; + + /* Check if this module created this block pool. */ + created_by_module = _txm_module_manager_created_object_check(module_instance, (VOID *) block_pool_ptr); + if (created_by_module == TX_TRUE) + { + + /* Delete this block pool, since it is part of this module. */ + _tx_block_pool_delete(block_pool_ptr); + } + + /* Move to next block pool. */ + block_pool_ptr = next_block_pool_ptr; + } + + /* Loop to delete any and all byte pools created by the module. */ + i = _tx_byte_pool_created_count; + byte_pool_ptr = _tx_byte_pool_created_ptr; + while (i--) + { + + /* Pickup the next byte pool pointer. */ + next_byte_pool_ptr = byte_pool_ptr -> tx_byte_pool_created_next; + + /* Check if this module created this byte pool. */ + created_by_module = _txm_module_manager_created_object_check(module_instance, (VOID *) byte_pool_ptr); + if (created_by_module == TX_TRUE) + { + + /* Delete this byte pool, since it is part of this module. */ + _tx_byte_pool_delete(byte_pool_ptr); + } + + /* Move to next byte pool. */ + byte_pool_ptr = next_byte_pool_ptr; + } + +#ifdef TX_ENABLE_EVENT_TRACE + /* Has trace been enabled? */ + if (_tx_trace_buffer_current_ptr != TX_NULL) + { + + /* Is the trace buffer located inside the module? */ + if ((ULONG) _tx_trace_header_ptr -> tx_trace_header_buffer_start_pointer >= (ULONG) module_instance -> txm_module_instance_data_start && + (ULONG) _tx_trace_header_ptr -> tx_trace_header_buffer_start_pointer < (ULONG) module_instance -> txm_module_instance_data_end) + { + _tx_trace_disable(); + } + } +#endif + + /* Delete the allocated objects for this module. */ + while (module_instance -> txm_module_instance_object_list_count--) + { + + /* Pickup the current object pointer. */ + object_ptr = module_instance -> txm_module_instance_object_list_head; + + /* Move the head pointer forward. */ + module_instance -> txm_module_instance_object_list_head = object_ptr -> txm_module_allocated_object_next; + + /* Release the object. */ + _tx_byte_release((VOID *) object_ptr); + } + + /* Set the allocated list head pointer to NULL. */ + module_instance -> txm_module_instance_object_list_head = TX_NULL; + + /* Disable interrupts. */ + TX_DISABLE + + /* Enable preemption again. */ + _tx_thread_preempt_disable--; + + /* Set the module state to indicate the module is stopped. */ + module_instance -> txm_module_instance_state = TXM_MODULE_STOPPED; + + /* Restore interrupts. */ + TX_RESTORE + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Check for preemption. */ + _tx_thread_system_preempt_check(); + + /* Return success. */ + return(TX_SUCCESS); +} + diff --git a/common_modules/module_manager/src/txm_module_manager_thread_create.c b/common_modules/module_manager/src/txm_module_manager_thread_create.c new file mode 100644 index 00000000..52dae4a5 --- /dev/null +++ b/common_modules/module_manager/src/txm_module_manager_thread_create.c @@ -0,0 +1,585 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_timer.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_thread_create PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates a thread and places it on the list of created */ +/* threads. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* name Pointer to thread name string */ +/* shell_function Shell function of the thread */ +/* entry_function Entry function of the thread */ +/* entry_input 32-bit input value to thread */ +/* stack_start Pointer to start of stack */ +/* stack_size Stack size in bytes */ +/* priority Priority of thread */ +/* (default 0-31) */ +/* preempt_threshold Preemption threshold */ +/* time_slice Thread time-slice value */ +/* auto_start Automatic start selection */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_manager_thread_stack_build Build initial thread stack */ +/* _tx_thread_system_resume Resume automatic start thread */ +/* _tx_thread_system_ni_resume Noninterruptable resume thread*/ +/* _tx_thread_system_preempt_check Check for preemption */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_start Initiate module's start thread*/ +/* _txm_module_manager_stop Initiate module's stop thread */ +/* _txm_module_manager_kernel_dispatch Kernel dispatch function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_thread_create(TX_THREAD *thread_ptr, CHAR *name, VOID (*shell_function)(TX_THREAD *, TXM_MODULE_INSTANCE *), + VOID (*entry_function)(ULONG), ULONG entry_input, + VOID *stack_start, ULONG stack_size, UINT priority, UINT preempt_threshold, + ULONG time_slice, UINT auto_start, UINT thread_control_block_size, TXM_MODULE_INSTANCE *module_instance) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_THREAD *next_thread; +TX_THREAD *previous_thread; +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD +TX_THREAD *saved_thread_ptr; +UINT saved_threshold = 0; +#endif +#ifdef TX_ENABLE_STACK_CHECKING +ULONG new_stack_start; +#endif +TXM_MODULE_THREAD_ENTRY_INFO *thread_entry_info; +VOID *stack_end; +ULONG i; +#ifndef TX_TIMER_PROCESS_IN_ISR +TX_THREAD *current_thread; +#endif +#if TXM_MODULE_MEMORY_PROTECTION +ULONG status; +#endif + + /* First, check for an invalid thread pointer. */ + if (thread_ptr == TX_NULL) + { + + /* Thread pointer is invalid, return appropriate error code. */ + return(TX_THREAD_ERROR); + } + + /* Now check for invalid thread control block size. */ + else if (thread_control_block_size != (sizeof(TX_THREAD))) + { + + /* Thread pointer is invalid, return appropriate error code. */ + return(TX_THREAD_ERROR); + } + + /* Disable interrupts. */ + TX_DISABLE + + /* Increment the preempt disable flag. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Next see if it is already in the created list. */ + next_thread = _tx_thread_created_ptr; + stack_end = (VOID *) (((UCHAR *) ((VOID *) stack_start)) + (stack_size - 1)); + for (i = 0; i < _tx_thread_created_count; i++) + { + + /* Determine if this thread matches the thread in the list. */ + if (thread_ptr == next_thread) + { + + break; + } + + /* Check the stack pointer to see if it overlaps with this thread's stack. */ + + /*lint -e{946} suppress pointer comparison, since this is necessary. */ + if (((UCHAR *) ((VOID *) stack_start)) >= ((UCHAR *) ((VOID *) next_thread -> tx_thread_stack_start))) + { + + /*lint -e{946} suppress pointer comparison, since this is necessary. */ + if (((UCHAR *) ((VOID *) stack_start)) < ((UCHAR *) ((VOID *) next_thread -> tx_thread_stack_end))) + { + + /* This stack overlaps with an existing thread, clear the stack pointer to + force a stack error below. */ + stack_start = TX_NULL; + break; + } + } + + /* Check the end of the stack to see if it is inside this thread's stack area as well. */ + + /*lint -e{946} suppress pointer comparison, since this is necessary. */ + if (((UCHAR *) ((VOID *) stack_end)) >= ((UCHAR *) ((VOID *) next_thread -> tx_thread_stack_start))) + { + + /*lint -e{946} suppress pointer comparison, since this is necessary. */ + if (((UCHAR *) ((VOID *) stack_end)) < ((UCHAR *) ((VOID *) next_thread -> tx_thread_stack_end))) + { + + /* This stack overlaps with an existing thread, clear the stack pointer to + force a stack error below. */ + stack_start = TX_NULL; + break; + } + } + + /* Move to the next thread. */ + next_thread = next_thread -> tx_thread_created_next; + } + + /* Disable interrupts. */ + TX_DISABLE + + /* Decrement the preempt disable flag. */ + _tx_thread_preempt_disable--; + + /* Restore interrupts. */ + TX_RESTORE + + /* Check for preemption. */ + _tx_thread_system_preempt_check(); + + /* At this point, check to see if there is a duplicate thread. */ + if (thread_ptr == next_thread) + { + + /* Thread is already created, return appropriate error code. */ + return(TX_THREAD_ERROR); + } + + /* Check for invalid starting address of stack. */ + if (stack_start == TX_NULL) + { + + /* Invalid stack or entry point, return appropriate error code. */ + return(TX_PTR_ERROR); + } + + /* Check for invalid thread entry point. */ + if (entry_function == TX_NULL) + { + + /* Invalid stack or entry point, return appropriate error code. */ + return(TX_PTR_ERROR); + } + + /* Check the stack size. */ + if (stack_size < TX_MINIMUM_STACK) + { + + /* Stack is not big enough, return appropriate error code. */ + return(TX_SIZE_ERROR); + } + + /* Check the priority specified. */ + if (priority >= TX_MAX_PRIORITIES) + { + + /* Invalid priority selected, return appropriate error code. */ + return(TX_PRIORITY_ERROR); + } + + /* Check preemption threshold. */ + if (preempt_threshold > priority) + { + + /* Invalid preempt threshold, return appropriate error code. */ + return(TX_THRESH_ERROR); + } + + /* Check the start selection. */ + if (auto_start > TX_AUTO_START) + { + + /* Invalid auto start selection, return appropriate error code. */ + return(TX_START_ERROR); + } + +#ifndef TX_TIMER_PROCESS_IN_ISR + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(current_thread) + + /* Check for invalid caller of this function. First check for a calling thread. */ + if (current_thread == &_tx_timer_thread) + { + + /* Invalid caller of this function, return appropriate error code. */ + return(TX_CALLER_ERROR); + } +#endif + + /* Check for interrupt call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != 0) + { + + /* Now, make sure the call is from an interrupt and not initialization. */ + if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS) + { + + /* Invalid caller of this function, return appropriate error code. */ + return(TX_CALLER_ERROR); + } + } + +#ifndef TX_DISABLE_STACK_FILLING + + /* Set the thread stack to a pattern prior to creating the initial + stack frame. This pattern is used by the stack checking routines + to see how much has been used. */ + TX_MEMSET(stack_start, ((UCHAR) TX_STACK_FILL), stack_size); +#endif + +#ifdef TX_ENABLE_STACK_CHECKING + + /* Ensure that there are two ULONG of 0xEF patterns at the top and + bottom of the thread's stack. This will be used to check for stack + overflow conditions during run-time. */ + stack_size = ((stack_size/sizeof(ULONG)) * sizeof(ULONG)) - sizeof(ULONG); + + /* Ensure the starting stack address is evenly aligned. */ + new_stack_start = ((((ULONG) stack_start) + (sizeof(ULONG) - 1) ) & (~(sizeof(ULONG) - 1))); + + /* Determine if the starting stack address is different. */ + if (new_stack_start != ((ULONG) stack_start)) + { + + /* Yes, subtract another ULONG from the size to avoid going past the stack area. */ + stack_size = stack_size - sizeof(ULONG); + } + + /* Update the starting stack pointer. */ + stack_start = (VOID *) new_stack_start; +#endif + + /* Allocate the thread entry information at the top of thread's stack - Leaving one + ULONG worth of 0xEF pattern between the actual stack and the entry info structure. */ + stack_size = stack_size - (sizeof(TXM_MODULE_THREAD_ENTRY_INFO) + (3*sizeof(ULONG))); + + /* Prepare the thread control block prior to placing it on the created + list. */ + + /* Initialize thread control block to all zeros. */ + TX_MEMSET(thread_ptr, 0, sizeof(TX_THREAD)); + +#if TXM_MODULE_MEMORY_PROTECTION + /* If this is a memory protected module, allocate a kernel stack. */ + if((module_instance -> txm_module_instance_property_flags) & TXM_MODULE_MEMORY_PROTECTION) + { + /* Allocate kernel stack space. */ + status = _txm_module_manager_object_allocate((VOID **) &(thread_ptr -> tx_thread_module_kernel_stack_start), TXM_MODULE_KERNEL_STACK_SIZE, module_instance); + if(status) + { + return(status); + } + +#ifndef TX_DISABLE_STACK_FILLING + /* Set the thread stack to a pattern prior to creating the initial + stack frame. This pattern is used by the stack checking routines + to see how much has been used. */ + TX_MEMSET(thread_ptr -> tx_thread_module_kernel_stack_start, ((UCHAR) TX_STACK_FILL), TXM_MODULE_KERNEL_STACK_SIZE); +#endif + + /* Align kernel stack pointer. */ + thread_ptr -> tx_thread_module_kernel_stack_end = (VOID *) (((ALIGN_TYPE)(thread_ptr -> tx_thread_module_kernel_stack_start) + TXM_MODULE_KERNEL_STACK_SIZE) & ~0x07); + + /* Set kernel stack size. */ + thread_ptr -> tx_thread_module_kernel_stack_size = TXM_MODULE_KERNEL_STACK_SIZE; + } + + /* Place the stack parameters into the thread's control block. */ + thread_ptr -> tx_thread_module_stack_start = stack_start; + thread_ptr -> tx_thread_module_stack_size = stack_size; +#endif + + /* Place the supplied parameters into the thread's control block. */ + thread_ptr -> tx_thread_name = name; + thread_ptr -> tx_thread_entry = entry_function; + thread_ptr -> tx_thread_entry_parameter = entry_input; + thread_ptr -> tx_thread_stack_start = stack_start; + thread_ptr -> tx_thread_stack_size = stack_size; + thread_ptr -> tx_thread_stack_end = (VOID *) (((UCHAR *) stack_start) + (stack_size-1)); +#if TXM_MODULE_MEMORY_PROTECTION + thread_ptr -> tx_thread_module_stack_end = thread_ptr -> tx_thread_stack_end; +#endif + thread_ptr -> tx_thread_priority = priority; + thread_ptr -> tx_thread_user_priority = priority; + thread_ptr -> tx_thread_time_slice = time_slice; + thread_ptr -> tx_thread_new_time_slice = time_slice; + thread_ptr -> tx_thread_inherit_priority = TX_MAX_PRIORITIES; + +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD + + /* Preemption-threshold is enabled, setup accordingly. */ + thread_ptr -> tx_thread_preempt_threshold = preempt_threshold; + thread_ptr -> tx_thread_user_preempt_threshold = preempt_threshold; +#else + + /* Preemption-threshold is disabled, determine if preemption-threshold was required. */ + if (priority != preempt_threshold) + { + + /* Preemption-threshold specified. Since specific preemption-threshold is not supported, + disable all preemption. */ + thread_ptr -> tx_thread_preempt_threshold = 0; + thread_ptr -> tx_thread_user_preempt_threshold = 0; + } + else + { + + /* Preemption-threshold is not specified, just setup with the priority. */ + thread_ptr -> tx_thread_preempt_threshold = priority; + thread_ptr -> tx_thread_user_preempt_threshold = priority; + } +#endif + + /* Now fill in the values that are required for thread initialization. */ + thread_ptr -> tx_thread_state = TX_SUSPENDED; + + /* Setup the necessary fields in the thread timer block. */ + TX_THREAD_CREATE_TIMEOUT_SETUP(thread_ptr) + + /* Setup pointer to the thread entry information structure, which will live at the top of each + module thread's stack. This will allow the module thread entry function to avoid direct + access to the actual thread control block. */ + thread_entry_info = (TXM_MODULE_THREAD_ENTRY_INFO *) (((UCHAR *) thread_ptr -> tx_thread_stack_end) + (2*sizeof(ULONG)) + 1); + thread_entry_info = (TXM_MODULE_THREAD_ENTRY_INFO *) (((ALIGN_TYPE)(thread_entry_info)) & (~0x3)); + + /* Build the thread entry information structure. */ + thread_entry_info -> txm_module_thread_entry_info_thread = thread_ptr; + thread_entry_info -> txm_module_thread_entry_info_module = module_instance; + thread_entry_info -> txm_module_thread_entry_info_data_base_address = module_instance -> txm_module_instance_module_data_base_address; + thread_entry_info -> txm_module_thread_entry_info_code_base_address = module_instance -> txm_module_instance_code_start; + thread_entry_info -> txm_module_thread_entry_info_entry = thread_ptr -> tx_thread_entry; + thread_entry_info -> txm_module_thread_entry_info_parameter = thread_ptr -> tx_thread_entry_parameter; + thread_entry_info -> txm_module_thread_entry_info_callback_request_queue = &(module_instance -> txm_module_instance_callback_request_queue); + thread_entry_info -> txm_module_thread_entry_info_callback_request_thread = &(module_instance -> txm_module_instance_callback_request_thread); + + /* Populate thread control block with some stock information from the module. */ + TXM_MODULE_MANAGER_THREAD_SETUP(thread_ptr, module_instance) + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + thread_entry_info -> txm_module_thread_entry_info_exit_notify = thread_ptr -> tx_thread_entry_exit_notify; +#else + thread_entry_info -> txm_module_thread_entry_info_exit_notify = TX_NULL; +#endif + if (thread_ptr -> tx_thread_entry == module_instance -> txm_module_instance_start_thread_entry) + thread_entry_info -> txm_module_thread_entry_info_start_thread = TX_TRUE; + else + thread_entry_info -> txm_module_thread_entry_info_start_thread = TX_FALSE; + + /* Place pointers to the thread info and module instance in the thread control block. */ + thread_ptr -> tx_thread_module_instance_ptr = (VOID *) module_instance; + thread_ptr -> tx_thread_module_entry_info_ptr = (VOID *) thread_entry_info; + + /* Place the thread entry information pointer in the thread control block so it can be picked up + in the following stack build function. This is supplied to the module's shell entry function + to avoid direct access to the actual thread control block. Note that this is overwritten + with the actual stack pointer at the end of stack build. */ + thread_ptr -> tx_thread_stack_ptr = (VOID *) thread_entry_info; + + /* Call the target specific stack frame building routine to build the + thread's initial stack and to setup the actual stack pointer in the + control block. */ + _txm_module_manager_thread_stack_build(thread_ptr, shell_function); + +#ifdef TX_ENABLE_STACK_CHECKING + + /* Setup the highest usage stack pointer. */ + thread_ptr -> tx_thread_stack_highest_ptr = thread_ptr -> tx_thread_stack_ptr; +#endif + + /* Prepare to make this thread a member of the created thread list. */ + TX_DISABLE + + /* Load the thread ID field in the thread control block. */ + thread_ptr -> tx_thread_id = TX_THREAD_ID; + + /* Place the thread on the list of created threads. First, + check for an empty list. */ + if (_tx_thread_created_count++ == 0) + { + + /* The created thread list is empty. Add thread to empty list. */ + _tx_thread_created_ptr = thread_ptr; + thread_ptr -> tx_thread_created_next = thread_ptr; + thread_ptr -> tx_thread_created_previous = thread_ptr; + } + else + { + + /* This list is not NULL, add to the end of the list. */ + next_thread = _tx_thread_created_ptr; + previous_thread = next_thread -> tx_thread_created_previous; + + /* Place the new thread in the list. */ + next_thread -> tx_thread_created_previous = thread_ptr; + previous_thread -> tx_thread_created_next = thread_ptr; + + /* Setup this thread's created links. */ + thread_ptr -> tx_thread_created_previous = previous_thread; + thread_ptr -> tx_thread_created_next = next_thread; + } + + /* If trace is enabled, register this object. */ + TX_TRACE_OBJECT_REGISTER(TX_TRACE_OBJECT_TYPE_THREAD, thread_ptr, name, stack_start, stack_size) + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_CREATE, thread_ptr, priority, stack_start, stack_size, TX_TRACE_THREAD_EVENTS) + + /* Register thread in the thread array structure. */ + TX_EL_THREAD_REGISTER(thread_ptr) + + /* Log this kernel call. */ + TX_EL_THREAD_CREATE_INSERT + + /* Determine if an automatic start was requested. If so, call the resume + thread function and then check for a preemption condition. */ + if (auto_start == TX_AUTO_START) + { + +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD + + /* Determine if the create call is being called from initialization. */ + if (TX_THREAD_GET_SYSTEM_STATE() >= TX_INITIALIZE_IN_PROGRESS) + { + + /* Yes, this create call was made from initialization. */ + + /* Pickup the current thread execute pointer, which corresponds to the + highest priority thread ready to execute. Interrupt lockout is + not required, since interrupts are assumed to be disabled during + initialization. */ + saved_thread_ptr = _tx_thread_execute_ptr; + + /* Determine if there is thread ready for execution. */ + if (saved_thread_ptr != TX_NULL) + { + + /* Yes, a thread is ready for execution when initialization completes. */ + + /* Save the current preemption-threshold. */ + saved_threshold = saved_thread_ptr -> tx_thread_preempt_threshold; + + /* For initialization, temporarily set the preemption-threshold to the + priority level to make sure the highest-priority thread runs once + initialization is complete. */ + saved_thread_ptr -> tx_thread_preempt_threshold = saved_thread_ptr -> tx_thread_priority; + } + } + else + { + + /* Simply set the saved thread pointer to NULL. */ + saved_thread_ptr = TX_NULL; + } +#endif + +#ifdef TX_NOT_INTERRUPTABLE + + /* Perform any additional activities for tool or user purpose. */ + TX_THREAD_CREATE_EXTENSION(thread_ptr) + + /* Resume the thread! */ + _tx_thread_system_ni_resume(thread_ptr); + + /* Restore previous interrupt posture. */ + TX_RESTORE +#else + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Restore previous interrupt posture. */ + TX_RESTORE + + /* Perform any additional activities for tool or user purpose. */ + TX_THREAD_CREATE_EXTENSION(thread_ptr) + + /* Call the resume thread function to make this thread ready. */ + _tx_thread_system_resume(thread_ptr); +#endif + +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD + + /* Determine if the thread's preemption-threshold needs to be restored. */ + if (saved_thread_ptr != TX_NULL) + { + + /* Yes, restore the previous highest-priority thread's preemption-threshold. This + can only happen if this routine is called from initialization. */ + saved_thread_ptr -> tx_thread_preempt_threshold = saved_threshold; + } +#endif + + /* Interrupts are already restored, simply return success. */ + return(TX_SUCCESS); + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return success. */ + return(TX_SUCCESS); +} + diff --git a/common_modules/module_manager/src/txm_module_manager_thread_notify_trampoline.c b/common_modules/module_manager/src/txm_module_manager_thread_notify_trampoline.c new file mode 100644 index 00000000..569d03f5 --- /dev/null +++ b/common_modules/module_manager/src/txm_module_manager_thread_notify_trampoline.c @@ -0,0 +1,153 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_queue.h" +#include "tx_thread.h" +#include "txm_module.h" + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_thread_notify_trampoline PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the thread entry/exit notification call */ +/* from ThreadX. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread pointer */ +/* type Entry or exit type */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_manager_callback_request Send module callback request */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_thread_notify_trampoline(TX_THREAD *thread_ptr, UINT type) +{ + +TX_INTERRUPT_SAVE_AREA + +TXM_MODULE_INSTANCE *module_instance; +TXM_MODULE_CALLBACK_MESSAGE callback_message; +TX_QUEUE *module_callback_queue; +TXM_MODULE_THREAD_ENTRY_INFO *thread_info; + + + /* We now know the callback is for a module. */ + + /* Disable interrupts. */ + TX_DISABLE + + /* Determine if the thread is valid. */ + if ((thread_ptr) && (thread_ptr -> tx_thread_id == TX_THREAD_ID)) + { + + /* Pickup the module instance pointer. */ + module_instance = (TXM_MODULE_INSTANCE *) thread_ptr -> tx_thread_module_instance_ptr; + + /* Pickup the module's thread pointer. */ + thread_info = (TXM_MODULE_THREAD_ENTRY_INFO *) thread_ptr -> tx_thread_module_entry_info_ptr; + + /* Determine if this module is still valid. */ + if ((module_instance) && (module_instance -> txm_module_instance_id == TXM_MODULE_ID) && + (module_instance -> txm_module_instance_state == TXM_MODULE_STARTED)) + { + + /* Yes, the module is still valid. */ + + /* Pickup the module's callback message queue. */ + module_callback_queue = &(module_instance -> txm_module_instance_callback_request_queue); + + /* Build the queue notification message. */ + callback_message.txm_module_callback_message_type = TXM_THREAD_ENTRY_EXIT_CALLBACK; + callback_message.txm_module_callback_message_activation_count = 1; + callback_message.txm_module_callback_message_application_function = (VOID (*)(VOID)) thread_info -> txm_module_thread_entry_info_exit_notify; + callback_message.txm_module_callback_message_param_1 = (ALIGN_TYPE) thread_ptr; + callback_message.txm_module_callback_message_param_2 = (ALIGN_TYPE) type; + callback_message.txm_module_callback_message_param_3 = 0; + callback_message.txm_module_callback_message_param_4 = 0; + callback_message.txm_module_callback_message_param_5 = 0; + callback_message.txm_module_callback_message_param_6 = 0; + callback_message.txm_module_callback_message_param_7 = 0; + callback_message.txm_module_callback_message_param_8 = 0; + callback_message.txm_module_callback_message_reserved1 = 0; + callback_message.txm_module_callback_message_reserved2 = 0; + + /* Restore interrupts. */ + TX_RESTORE + + /* Call the general processing that will place the callback on the + module's callback request queue. */ + _txm_module_manager_callback_request(module_callback_queue, &callback_message); + } + else + { + + /* Module no longer valid. */ + + /* Error, increment the error counter and return. */ + _txm_module_manager_callback_error_count++; + + /* Restore interrupts. */ + TX_RESTORE + } + } + else + { + + /* Thread pointer is not valid. */ + + /* Error, increment the error counter and return. */ + _txm_module_manager_callback_error_count++; + + /* Restore interrupts. */ + TX_RESTORE + } +} +#endif + diff --git a/common_modules/module_manager/src/txm_module_manager_thread_reset.c b/common_modules/module_manager/src/txm_module_manager_thread_reset.c new file mode 100644 index 00000000..c75be7b6 --- /dev/null +++ b/common_modules/module_manager/src/txm_module_manager_thread_reset.c @@ -0,0 +1,180 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_thread.h" +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_thread_reset PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function prepares the thread to run again from the entry */ +/* point specified during thread creation. The application must */ +/* call tx_thread_resume after this call completes for the thread */ +/* to actually run. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread to reset */ +/* */ +/* OUTPUT */ +/* */ +/* status Service return status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_manager_thread_stack_build Build initial thread */ +/* stack */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_kernel_dispatch Kernel dispatch function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_thread_reset(TX_THREAD *thread_ptr) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_THREAD *current_thread; +UINT status; +TXM_MODULE_INSTANCE *module_instance; +TXM_MODULE_THREAD_ENTRY_INFO *thread_entry_info; + + /* Default a successful completion status. */ + status = TX_SUCCESS; + + /* Disable interrupts. */ + TX_DISABLE + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(current_thread) + + /* Check for a call from the current thread, which is not allowed! */ + if (current_thread == thread_ptr) + { + + /* Restore interrupts. */ + TX_RESTORE + + /* Thread not completed or terminated - return an error! */ + status = TX_NOT_DONE; + } + else + { + + /* Check for proper status of this thread to reset. */ + if (thread_ptr -> tx_thread_state != TX_COMPLETED) + { + + /* Now check for terminated state. */ + if (thread_ptr -> tx_thread_state != TX_TERMINATED) + { + + /* Thread not completed or terminated - return an error! */ + status = TX_NOT_DONE; + } + } + } + + /* Is the request valid? */ + if (status == TX_SUCCESS) + { + + /* Modify the thread status to prevent additional reset calls. */ + thread_ptr -> tx_thread_state = TX_NOT_DONE; + + /* Get the module instance. */ + module_instance = thread_ptr -> tx_thread_module_instance_ptr; + + /* Execute Port-Specific completion processing. If needed, it is typically defined in txm_module_port.h. */ + TXM_MODULE_MANAGER_THREAD_RESET_PORT_COMPLETION(thread_ptr, module_instance) + + /* Restore interrupts. */ + TX_RESTORE + +#ifndef TX_DISABLE_STACK_FILLING + + /* Set the thread stack to a pattern prior to creating the initial + stack frame. This pattern is used by the stack checking routines + to see how much has been used. */ + TX_MEMSET(thread_ptr -> tx_thread_stack_start, ((UCHAR) TX_STACK_FILL), thread_ptr -> tx_thread_stack_size); +#endif + + /* Setup pointer to the thread entry information structure, which will live at the top of each + module thread's stack. This will allow the module thread entry function to avoid direct + access to the actual thread control block. */ + thread_entry_info = (TXM_MODULE_THREAD_ENTRY_INFO *) (((UCHAR *) thread_ptr -> tx_thread_stack_end) + (2*sizeof(ULONG)) + 1); + thread_entry_info = (TXM_MODULE_THREAD_ENTRY_INFO *) (((ALIGN_TYPE)(thread_entry_info)) & (~0x3)); + + /* Place the thread entry information pointer in the thread control block so it can be picked up + in the following stack build function. This is supplied to the module's shell entry function + to avoid direct access to the actual thread control block. Note that this is overwritten + with the actual stack pointer at the end of stack build. */ + thread_ptr -> tx_thread_stack_ptr = (VOID *) thread_entry_info; + + /* Call the target specific stack frame building routine to build the + thread's initial stack and to setup the actual stack pointer in the + control block. */ + _txm_module_manager_thread_stack_build(thread_ptr, module_instance -> txm_module_instance_shell_entry_function); + + /* Disable interrupts. */ + TX_DISABLE + + /* Finally, move into a suspended state to allow for the thread to be resumed. */ + thread_ptr -> tx_thread_state = TX_SUSPENDED; + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_RESET, thread_ptr, thread_ptr -> tx_thread_state, 0, 0, TX_TRACE_THREAD_EVENTS) + + /* Log this kernel call. */ + TX_EL_THREAD_RESET_INSERT + + /* Log the thread status change. */ + TX_EL_THREAD_STATUS_CHANGE_INSERT(thread_ptr, TX_SUSPENDED) + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return completion status to caller. */ + return(status); +} + diff --git a/common_modules/module_manager/src/txm_module_manager_timer_notify_trampoline.c b/common_modules/module_manager/src/txm_module_manager_timer_notify_trampoline.c new file mode 100644 index 00000000..2a11f146 --- /dev/null +++ b/common_modules/module_manager/src/txm_module_manager_timer_notify_trampoline.c @@ -0,0 +1,141 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_timer_notify_trampoline PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the timer expirations from ThreadX. */ +/* */ +/* INPUT */ +/* */ +/* id Timer ID */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_manager_callback_request Send module callback request */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_timer_notify_trampoline(ULONG id) +{ + +TX_INTERRUPT_SAVE_AREA + +TXM_MODULE_INSTANCE *module_instance; +TXM_MODULE_CALLBACK_MESSAGE callback_message; +TX_QUEUE *module_callback_queue; +TX_TIMER *timer_ptr; +CHAR *internal_ptr; + + + /* We now know the callback is for a module. */ + + /* Disable interrupts. */ + TX_DISABLE + + /* Our expired timer pointer points to the internal timer, + * we need to get to the full timer pointer. */ + /* Pickup the current internal timer pointer. */ + internal_ptr = (CHAR *) _tx_timer_expired_timer_ptr; + + /* Get the timer pointer from the internal pointer. */ + TX_USER_TIMER_POINTER_GET((TX_TIMER_INTERNAL *) internal_ptr, timer_ptr); + + /* Pickup the module instance pointer. */ + module_instance = (TXM_MODULE_INSTANCE *) timer_ptr -> tx_timer_module_instance; + + /* Determine if this module is still valid. */ + if ((module_instance) && (module_instance -> txm_module_instance_id == TXM_MODULE_ID) && + (module_instance -> txm_module_instance_state == TXM_MODULE_STARTED)) + { + + /* Yes, the module is still valid. */ + + /* Pickup the module's callback message queue. */ + module_callback_queue = &(module_instance -> txm_module_instance_callback_request_queue); + + /* Build the queue notification message. */ + callback_message.txm_module_callback_message_type = TXM_TIMER_CALLBACK; + callback_message.txm_module_callback_message_activation_count = 1; + callback_message.txm_module_callback_message_application_function = (VOID (*)(VOID)) timer_ptr -> tx_timer_module_expiration_function; + callback_message.txm_module_callback_message_param_1 = (ULONG) id; + callback_message.txm_module_callback_message_param_2 = 0; + callback_message.txm_module_callback_message_param_3 = 0; + callback_message.txm_module_callback_message_param_4 = 0; + callback_message.txm_module_callback_message_param_5 = 0; + callback_message.txm_module_callback_message_param_6 = 0; + callback_message.txm_module_callback_message_param_7 = 0; + callback_message.txm_module_callback_message_param_8 = 0; + callback_message.txm_module_callback_message_reserved1 = 0; + callback_message.txm_module_callback_message_reserved2 = 0; + + /* Restore interrupts. */ + TX_RESTORE + + /* Call the general processing that will place the callback on the + module's callback request queue. */ + _txm_module_manager_callback_request(module_callback_queue, &callback_message); + } + else + { + + /* Module no longer valid. */ + + /* Error, increment the error counter and return. */ + _txm_module_manager_callback_error_count++; + + /* Restore interrupts. */ + TX_RESTORE + } +} + diff --git a/common_modules/module_manager/src/txm_module_manager_unload.c b/common_modules/module_manager/src/txm_module_manager_unload.c new file mode 100644 index 00000000..3689afd4 --- /dev/null +++ b/common_modules/module_manager/src/txm_module_manager_unload.c @@ -0,0 +1,197 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_byte_pool.h" +#include "tx_initialize.h" +#include "tx_mutex.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_unload PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function unloads a previously loaded module. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_byte_release Release data area */ +/* _tx_mutex_get Get protection mutex */ +/* _tx_mutex_put Release protection mutex */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_unload(TXM_MODULE_INSTANCE *module_instance) +{ + +TX_INTERRUPT_SAVE_AREA + +TXM_MODULE_INSTANCE *next_module, *previous_module; +CHAR *memory_ptr; + + + /* Check for interrupt call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != 0) + { + + /* Now, make sure the call is from an interrupt and not initialization. */ + if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS) + { + + /* Invalid caller of this function, return appropriate error code. */ + return(TX_CALLER_ERROR); + } + } + + /* Determine if the module manager has not been initialized yet. */ + if (_txm_module_manager_ready != TX_TRUE) + { + + /* Module manager has not been initialized. */ + return(TX_NOT_AVAILABLE); + } + + /* Determine if the module is valid. */ + if (module_instance == TX_NULL) + { + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Get module manager protection mutex. */ + _tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER); + + /* Determine if the module is already valid. */ + if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) + { + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Determine if the module instance is in the state. */ + if ((module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) && (module_instance -> txm_module_instance_state != TXM_MODULE_STOPPED)) + { + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not ready. */ + return(TX_NOT_DONE); + } + + /* Pickup the module data memory allocation address. */ + memory_ptr = module_instance -> txm_module_instance_data_allocation_ptr; + + /* Release the module's data memory. */ + _tx_byte_release(memory_ptr); + + /* Determine if there was memory allocated for the code. */ + if (module_instance -> txm_module_instance_code_allocation_ptr) + { + + /* Yes, release the module's code memory. */ + memory_ptr = module_instance -> txm_module_instance_code_allocation_ptr; + + /* Release the module's data memory. */ + _tx_byte_release(memory_ptr); + } + + /* Temporarily disable interrupts. */ + TX_DISABLE + + /* Clear some of the module information. */ + module_instance -> txm_module_instance_id = 0; + module_instance -> txm_module_instance_state = TXM_MODULE_UNLOADED; + + /* Call port-specific unload function. */ + TXM_MODULE_MANAGER_MODULE_UNLOAD(module_instance); + + /* Remove the module from the linked list of loaded modules. */ + + /* See if the module is the only one on the list. */ + if ((--_txm_module_manger_loaded_count) == 0) + { + + /* Only created module, just set the created list to NULL. */ + _txm_module_manager_loaded_list_ptr = TX_NULL; + } + else + { + + /* Otherwise, not the only created module, link-up the neighbors. */ + next_module = module_instance -> txm_module_instance_loaded_next; + previous_module = module_instance -> txm_module_instance_loaded_previous; + next_module -> txm_module_instance_loaded_previous = previous_module; + previous_module -> txm_module_instance_loaded_next = next_module; + + /* See if we have to update the created list head pointer. */ + if (_txm_module_manager_loaded_list_ptr == module_instance) + { + + /* Yes, move the head pointer to the next link. */ + _txm_module_manager_loaded_list_ptr = next_module; + } + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/common_modules/module_manager/src/txm_module_manager_util.c b/common_modules/module_manager/src/txm_module_manager_util.c new file mode 100644 index 00000000..e2f5bb44 --- /dev/null +++ b/common_modules/module_manager/src/txm_module_manager_util.c @@ -0,0 +1,417 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define TX_SOURCE_CODE + +#include "txm_module.h" +#include "txm_module_manager_util.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_object_memory_check PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks if the object is inside a module's object pool */ +/* or, if it's a privileged module, inside the module's data area. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance that the object */ +/* belongs to */ +/* object_ptr Pointer to object to check */ +/* object_size Size of the object to check */ +/* */ +/* OUTPUT */ +/* */ +/* status Whether the object resides in a */ +/* valid location */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_kernel_dispatch Kernel dispatch function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_object_memory_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE object_ptr, ULONG object_size) +{ + + /* Is the object pointer from the module manager's object pool? */ + if ((_txm_module_manager_object_pool_created == TX_TRUE) && + (object_ptr >= (ALIGN_TYPE) _txm_module_manager_object_pool.tx_byte_pool_start) && + ((object_ptr+object_size) <= (ALIGN_TYPE) (_txm_module_manager_object_pool.tx_byte_pool_start + _txm_module_manager_object_pool.tx_byte_pool_size))) + { + /* Object is from manager object pool. */ + return(TX_SUCCESS); + } + + /* If memory protection is not required, check if object is in module data. */ + else if (!(module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION)) + { + if ((object_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && + ((object_ptr+object_size) <= (ALIGN_TYPE) module_instance -> txm_module_instance_data_end)) + { + /* Object is from the local module memory. */ + return(TX_SUCCESS); + } + } + + /* Object is from invalid memory. */ + return(TXM_MODULE_INVALID_MEMORY); + +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_created_object_check PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This functions checks if the specified object was created by the */ +/* specified module */ +/* */ +/* INPUT */ +/* */ +/* module_instance The module instance to check */ +/* object_ptr The object to check */ +/* */ +/* OUTPUT */ +/* */ +/* status Whether the module created the */ +/* object */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* txm_module_manager*_stop Module manager stop functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UCHAR _txm_module_manager_created_object_check(TXM_MODULE_INSTANCE *module_instance, VOID *object_ptr) +{ + +TXM_MODULE_ALLOCATED_OBJECT *allocated_object_ptr; + + /* Determine if the socket control block is inside the module. */ + if ( (((CHAR *) object_ptr) >= ((CHAR *) module_instance -> txm_module_instance_data_start)) && + (((CHAR *) object_ptr) < ((CHAR *) module_instance -> txm_module_instance_data_end))) + { + return TX_TRUE; + } + + /* Determine if this object control block was allocated by this module instance. */ + else if (_txm_module_manager_object_pool_created) + { + + /* Determine if the current object is from the pool of dynamically allocated objects. */ + if ((((UCHAR *) object_ptr) >= _txm_module_manager_object_pool.tx_byte_pool_start) && + (((UCHAR *) object_ptr) < (_txm_module_manager_object_pool.tx_byte_pool_start + _txm_module_manager_object_pool.tx_byte_pool_size))) + { + + /* Pickup object pointer. */ + allocated_object_ptr = (TXM_MODULE_ALLOCATED_OBJECT *) object_ptr; + + /* Move back to get the header information. */ + allocated_object_ptr--; + + /* Now determine if this object belongs to this module. */ + if (allocated_object_ptr -> txm_module_allocated_object_module_instance == module_instance) + { + return TX_TRUE; + } + } + } + + return TX_FALSE; +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_object_size_check PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks if the specified object's size matches what is */ +/* inside the object pool. */ +/* */ +/* INPUT */ +/* */ +/* object_ptr Pointer to object to check */ +/* object_size Size of the object to check */ +/* */ +/* OUTPUT */ +/* */ +/* status Whether the object's size matches */ +/* what's inside the object pool */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_kernel_dispatch Kernel dispatch function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_object_size_check(ALIGN_TYPE object_ptr, ULONG object_size) +{ +TXM_MODULE_ALLOCATED_OBJECT *module_allocated_object_ptr; +UINT return_value; + + /* Pickup the allocated object pointer. */ + module_allocated_object_ptr = ((TXM_MODULE_ALLOCATED_OBJECT *) object_ptr) - 1; + + /* Does the allocated memory match the expected object size? */ + if (module_allocated_object_ptr -> txm_module_object_size == object_size) + return_value = TX_SUCCESS; + else + return_value = TXM_MODULE_INVALID_MEMORY; + + return(return_value); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_name_compare PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function compares the specified object names. */ +/* */ +/* INPUT */ +/* */ +/* search_name String pointer to the object's */ +/* name being searched for */ +/* search_name_length Length of search_name */ +/* object_name String pointer to an object's name*/ +/* to compare the search name to */ +/* */ +/* OUTPUT */ +/* */ +/* status Whether the names are equal */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* *_object_pointer_get Kernel dispatch function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_object_name_compare(CHAR *search_name, UINT search_name_length, CHAR *object_name) +{ + +CHAR search_name_char; +CHAR object_name_char; + + + /* Is the object name null? Note that the search name has already been checked + by the caller. */ + if (object_name == TX_NULL) + { + + /* The strings can't match. */ + return(TX_FALSE); + } + + /* Loop through the names. */ + while (1) + { + + /* Get the current characters from each name. */ + search_name_char = *search_name; + object_name_char = *object_name; + + /* Check for match. */ + if (search_name_char == object_name_char) + { + + /* Are they null-terminators? */ + if (search_name_char == '\0') + { + + /* The strings match. */ + return(TX_TRUE); + } + } + else + { + + /* The strings don't match. */ + return(TX_FALSE); + } + + /* Are we at the end of the search name? */ + if (search_name_length == 0) + { + + /* The strings don't match. */ + return(TX_FALSE); + } + + /* Move to next character. */ + search_name++; + object_name++; + search_name_length--; + } +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_util_code_allocation_size_and_alignment_get */ +/* PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function returns the required alignment and allocation size */ +/* for a module's code area. */ +/* */ +/* INPUT */ +/* */ +/* module_preamble Preamble of module to return code */ +/* values for */ +/* code_alignment_dest Address to return code alignment */ +/* code_allocation_size_desk Address to return code allocation */ +/* size */ +/* */ +/* OUTPUT */ +/* */ +/* status Success if no math overflow */ +/* occurred during calculation */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* txm_module_manager_*_load Module load functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_util_code_allocation_size_and_alignment_get(TXM_MODULE_PREAMBLE *module_preamble, + ULONG *code_alignment_dest, ULONG *code_allocation_size_dest) +{ + +ULONG code_size; +ULONG code_alignment; +ULONG data_size_ignored; +ULONG data_alignment_ignored; + + + /* Pickup the module code size. */ + code_size = module_preamble -> txm_module_preamble_code_size; + + /* Adjust the size of the module elements to be aligned to the default alignment. */ + TXM_MODULE_MANAGER_UTIL_MATH_ADD_ULONG(code_size, TXM_MODULE_CODE_ALIGNMENT, code_size); + code_size = ((code_size - 1)/TXM_MODULE_CODE_ALIGNMENT) * TXM_MODULE_CODE_ALIGNMENT; + + /* Setup the default code and data alignments. */ + code_alignment = (ULONG) TXM_MODULE_CODE_ALIGNMENT; + + /* Get the port-specific alignment for the code size. Note we only want code so we pass 'null' values for data. */ + data_size_ignored = 1; + data_alignment_ignored = 1; + TXM_MODULE_MANAGER_ALIGNMENT_ADJUST(module_preamble, code_size, code_alignment, data_size_ignored, data_alignment_ignored) + + /* Calculate the code memory allocation size. */ + TXM_MODULE_MANAGER_UTIL_MATH_ADD_ULONG(code_size, code_alignment, *code_allocation_size_dest); + + /* Write the alignment result into the caller's destination address. */ + *code_alignment_dest = code_alignment; + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/common_smp/inc/tx_api.h b/common_smp/inc/tx_api.h new file mode 100644 index 00000000..b6994109 --- /dev/null +++ b/common_smp/inc/tx_api.h @@ -0,0 +1,2212 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Application Interface (API) */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* tx_api.h PORTABLE SMP */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the basic Application Interface (API) to the */ +/* high-performance ThreadX real-time kernel. All service prototypes */ +/* and data structure definitions are defined in this file. */ +/* Please note that basic data type definitions and other architecture-*/ +/* specific information is contained in the file tx_port.h. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_API_H +#define TX_API_H + + +/* Determine if a C++ compiler is being used. If so, ensure that standard + C is used to process the API information. */ + +#ifdef __cplusplus + +/* Yes, C++ compiler is present. Use standard C. */ +extern "C" { + +#endif + + +/* Include the port-specific data type file. */ + +#include "tx_port.h" + + +/* If not defined by tx_port.h, default the port-specific memory synchronization macro to whitespace. */ + +#ifndef TX_PORT_SPECIFIC_MEMORY_SYNCHRONIZATION +#define TX_PORT_SPECIFIC_MEMORY_SYNCHRONIZATION +#endif + + +/* Define basic constants for the ThreadX kernel. */ + + +/* Define the major/minor version information that can be used by the application + and the ThreadX source as well. */ + +#define EL_PRODUCT_THREADX +#define THREADX_MAJOR_VERSION 5 +#define THREADX_MINOR_VERSION 9 + + +/* API input parameters and general constants. */ + +#define TX_NO_WAIT ((ULONG) 0) +#define TX_WAIT_FOREVER ((ULONG) 0xFFFFFFFFUL) +#define TX_AND ((UINT) 2) +#define TX_AND_CLEAR ((UINT) 3) +#define TX_OR ((UINT) 0) +#define TX_OR_CLEAR ((UINT) 1) +#define TX_1_ULONG ((UINT) 1) +#define TX_2_ULONG ((UINT) 2) +#define TX_4_ULONG ((UINT) 4) +#define TX_8_ULONG ((UINT) 8) +#define TX_16_ULONG ((UINT) 16) +#define TX_NO_TIME_SLICE ((ULONG) 0) +#define TX_AUTO_START ((UINT) 1) +#define TX_DONT_START ((UINT) 0) +#define TX_AUTO_ACTIVATE ((UINT) 1) +#define TX_NO_ACTIVATE ((UINT) 0) +#define TX_TRUE ((UINT) 1) +#define TX_FALSE ((UINT) 0) +#define TX_NULL ((void *) 0) +#define TX_INHERIT ((UINT) 1) +#define TX_NO_INHERIT ((UINT) 0) +#define TX_THREAD_ENTRY ((UINT) 0) +#define TX_THREAD_EXIT ((UINT) 1) +#define TX_NO_SUSPENSIONS ((UINT) 0) +#define TX_NO_MESSAGES ((UINT) 0) +#define TX_EMPTY ((ULONG) 0) +#define TX_CLEAR_ID ((ULONG) 0) +#define TX_STACK_FILL ((ULONG) 0xEFEFEFEFUL) + + +/* Thread execution state values. */ + +#define TX_READY ((UINT) 0) +#define TX_COMPLETED ((UINT) 1) +#define TX_TERMINATED ((UINT) 2) +#define TX_SUSPENDED ((UINT) 3) +#define TX_SLEEP ((UINT) 4) +#define TX_QUEUE_SUSP ((UINT) 5) +#define TX_SEMAPHORE_SUSP ((UINT) 6) +#define TX_EVENT_FLAG ((UINT) 7) +#define TX_BLOCK_MEMORY ((UINT) 8) +#define TX_BYTE_MEMORY ((UINT) 9) +#define TX_IO_DRIVER ((UINT) 10) +#define TX_FILE ((UINT) 11) +#define TX_TCP_IP ((UINT) 12) +#define TX_MUTEX_SUSP ((UINT) 13) + + +/* API return values. */ + +#define TX_SUCCESS ((UINT) 0x00) +#define TX_DELETED ((UINT) 0x01) +#define TX_NO_MEMORY ((UINT) 0x10) +#define TX_POOL_ERROR ((UINT) 0x02) +#define TX_PTR_ERROR ((UINT) 0x03) +#define TX_WAIT_ERROR ((UINT) 0x04) +#define TX_SIZE_ERROR ((UINT) 0x05) +#define TX_GROUP_ERROR ((UINT) 0x06) +#define TX_NO_EVENTS ((UINT) 0x07) +#define TX_OPTION_ERROR ((UINT) 0x08) +#define TX_QUEUE_ERROR ((UINT) 0x09) +#define TX_QUEUE_EMPTY ((UINT) 0x0A) +#define TX_QUEUE_FULL ((UINT) 0x0B) +#define TX_SEMAPHORE_ERROR ((UINT) 0x0C) +#define TX_NO_INSTANCE ((UINT) 0x0D) +#define TX_THREAD_ERROR ((UINT) 0x0E) +#define TX_PRIORITY_ERROR ((UINT) 0x0F) +#define TX_START_ERROR ((UINT) 0x10) +#define TX_DELETE_ERROR ((UINT) 0x11) +#define TX_RESUME_ERROR ((UINT) 0x12) +#define TX_CALLER_ERROR ((UINT) 0x13) +#define TX_SUSPEND_ERROR ((UINT) 0x14) +#define TX_TIMER_ERROR ((UINT) 0x15) +#define TX_TICK_ERROR ((UINT) 0x16) +#define TX_ACTIVATE_ERROR ((UINT) 0x17) +#define TX_THRESH_ERROR ((UINT) 0x18) +#define TX_SUSPEND_LIFTED ((UINT) 0x19) +#define TX_WAIT_ABORTED ((UINT) 0x1A) +#define TX_WAIT_ABORT_ERROR ((UINT) 0x1B) +#define TX_MUTEX_ERROR ((UINT) 0x1C) +#define TX_NOT_AVAILABLE ((UINT) 0x1D) +#define TX_NOT_OWNED ((UINT) 0x1E) +#define TX_INHERIT_ERROR ((UINT) 0x1F) +#define TX_NOT_DONE ((UINT) 0x20) +#define TX_CEILING_EXCEEDED ((UINT) 0x21) +#define TX_INVALID_CEILING ((UINT) 0x22) +#define TX_FEATURE_NOT_ENABLED ((UINT) 0xFF) + + +/* Define the common timer tick reference for use by other middleware components. The default + value is 10ms, but may be replaced by a port specific version in tx_port.h or by the user + as a compilation option. */ + +#ifndef TX_TIMER_TICKS_PER_SECOND +#define TX_TIMER_TICKS_PER_SECOND ((ULONG) 100) +#endif + + +/* Event numbers 0 through 4095 are reserved by Express Logic. Specific event assignments are: + + ThreadX events: 1-199 + FileX events: 200-299 + NetX events: 300-599 + USBX events: 600-999 + GUIX events: 1000-1500 + + User-defined event numbers start at 4096 and continue through 65535, as defined by the constants + TX_TRACE_USER_EVENT_START and TX_TRACE_USER_EVENT_END, respectively. User events should be based + on these constants in case the user event number assignment is changed in future releases. */ + +#define TX_TRACE_USER_EVENT_START 4096 /* I1, I2, I3, I4 are user defined */ +#define TX_TRACE_USER_EVENT_END 65535 /* I1, I2, I3, I4 are user defined */ + + +/* Define event filters that can be used to selectively disable certain events or groups of events. */ + +#define TX_TRACE_ALL_EVENTS 0x000007FF /* All ThreadX events */ +#define TX_TRACE_INTERNAL_EVENTS 0x00000001 /* ThreadX internal events */ +#define TX_TRACE_BLOCK_POOL_EVENTS 0x00000002 /* ThreadX Block Pool events */ +#define TX_TRACE_BYTE_POOL_EVENTS 0x00000004 /* ThreadX Byte Pool events */ +#define TX_TRACE_EVENT_FLAGS_EVENTS 0x00000008 /* ThreadX Event Flags events */ +#define TX_TRACE_INTERRUPT_CONTROL_EVENT 0x00000010 /* ThreadX Interrupt Control events */ +#define TX_TRACE_MUTEX_EVENTS 0x00000020 /* ThreadX Mutex events */ +#define TX_TRACE_QUEUE_EVENTS 0x00000040 /* ThreadX Queue events */ +#define TX_TRACE_SEMAPHORE_EVENTS 0x00000080 /* ThreadX Semaphore events */ +#define TX_TRACE_THREAD_EVENTS 0x00000100 /* ThreadX Thread events */ +#define TX_TRACE_TIME_EVENTS 0x00000200 /* ThreadX Time events */ +#define TX_TRACE_TIMER_EVENTS 0x00000400 /* ThreadX Timer events */ +#define TX_TRACE_USER_EVENTS 0x80000000UL /* ThreadX User Events */ + + +/* Define basic alignment type used in block and byte pool operations. This data type must + be at least 32-bits in size and also be large enough to hold a pointer type. */ + +#ifndef ALIGN_TYPE_DEFINED +#define ALIGN_TYPE ULONG +#endif + + +/* Define the control block definitions for all system objects. */ + + +/* Define the basic timer management structures. These are the structures + used to manage thread sleep, timeout, and user timer requests. */ + +/* Determine if the internal timer control block has an extension defined. If not, + define the extension to whitespace. */ + +#ifndef TX_TIMER_INTERNAL_EXTENSION +#define TX_TIMER_INTERNAL_EXTENSION +#endif + + +/* Define the common internal timer control block. */ + +typedef struct TX_TIMER_INTERNAL_STRUCT +{ + + /* Define the remaining ticks and re-initialization tick values. */ + ULONG tx_timer_internal_remaining_ticks; + ULONG tx_timer_internal_re_initialize_ticks; + + /* Define the timeout function and timeout function parameter. */ + VOID (*tx_timer_internal_timeout_function)(ULONG id); + ULONG tx_timer_internal_timeout_param; + + + /* Define the next and previous internal link pointers for active + internal timers. */ + struct TX_TIMER_INTERNAL_STRUCT + *tx_timer_internal_active_next, + *tx_timer_internal_active_previous; + + /* Keep track of the pointer to the head of this list as well. */ + struct TX_TIMER_INTERNAL_STRUCT + **tx_timer_internal_list_head; + + /************* Define ThreadX SMP timer control block extensions. *************/ + + /* Define the timer SMP core exclusion for timer callback. */ + ULONG tx_timer_internal_smp_cores_excluded; + + /************* End of ThreadX SMP timer control block extensions. *************/ + + /* Define optional extension to internal timer control block. */ + TX_TIMER_INTERNAL_EXTENSION + +} TX_TIMER_INTERNAL; + + +/* Determine if the timer control block has an extension defined. If not, + define the extension to whitespace. */ + +#ifndef TX_TIMER_EXTENSION +#define TX_TIMER_EXTENSION +#endif + + +/* Define the timer structure utilized by the application. */ + +typedef struct TX_TIMER_STRUCT +{ + + /* Define the timer ID used for error checking. */ + ULONG tx_timer_id; + + /* Define the timer's name. */ + CHAR *tx_timer_name; + + /* Define the actual contents of the timer. This is the block that + is used in the actual timer expiration processing. */ + TX_TIMER_INTERNAL tx_timer_internal; + + /* Define the pointers for the created list. */ + struct TX_TIMER_STRUCT + *tx_timer_created_next, + *tx_timer_created_previous; + + /* Define optional extension to timer control block. */ + TX_TIMER_EXTENSION + +#ifdef TX_TIMER_ENABLE_PERFORMANCE_INFO + + /* Define the number of timer activations. */ + ULONG tx_timer_performance_activate_count; + + /* Define the number of timer reactivations. */ + ULONG tx_timer_performance_reactivate_count; + + /* Define the number of timer deactivations. */ + ULONG tx_timer_performance_deactivate_count; + + /* Define the number of timer expirations. */ + ULONG tx_timer_performance_expiration_count; + + /* Define the total number of timer expiration adjustments. */ + ULONG tx_timer_performance__expiration_adjust_count; +#endif + +} TX_TIMER; + + +/* Determine if the thread priority change extension is defined. If not, define the + extension to whitespace. */ + +#ifndef TX_THREAD_PRIORITY_CHANGE_EXTENSION +#define TX_THREAD_PRIORITY_CHANGE_EXTENSION +#endif + + +/* ThreadX thread control block structure follows. Additional fields + can be added providing they are added after the information that is + referenced in the port-specific assembly code. */ + +typedef struct TX_THREAD_STRUCT +{ + /* The first section of the control block contains critical + information that is referenced by the port-specific + assembly language code. Any changes in this section could + necessitate changes in the assembly language. */ + + ULONG tx_thread_id; /* Control block ID */ + ULONG tx_thread_run_count; /* Thread's run counter */ + VOID *tx_thread_stack_ptr; /* Thread's stack pointer */ + VOID *tx_thread_stack_start; /* Stack starting address */ + VOID *tx_thread_stack_end; /* Stack ending address */ + ULONG tx_thread_stack_size; /* Stack size */ + ULONG tx_thread_time_slice; /* Current time-slice */ + ULONG tx_thread_new_time_slice; /* New time-slice */ + + /* Define pointers to the next and previous ready threads. */ + struct TX_THREAD_STRUCT + *tx_thread_ready_next, + *tx_thread_ready_previous; + + /***************************************************************/ + + /* Define the first port extension in the thread control block. This + is typically defined to whitespace or a pointer type in tx_port.h. */ + TX_THREAD_EXTENSION_0 + + CHAR *tx_thread_name; /* Pointer to thread's name */ + UINT tx_thread_priority; /* Priority of thread (0-1023) */ + UINT tx_thread_state; /* Thread's execution state */ + UINT tx_thread_delayed_suspend; /* Delayed suspend flag */ + UINT tx_thread_suspending; /* Thread suspending flag */ + UINT tx_thread_preempt_threshold; /* Preemption threshold */ + + /* Define the thread schedule hook. The usage of this is port/application specific, + but when used, the function pointer designated is called whenever the thread is + scheduled and unscheduled. */ + VOID (*tx_thread_schedule_hook)(struct TX_THREAD_STRUCT *thread_ptr, ULONG id); + + /* Nothing after this point is referenced by the target-specific + assembly language. Hence, information after this point can + be added to the control block providing the complete system + is recompiled. */ + + /* Define the thread's entry point and input parameter. */ + VOID (*tx_thread_entry)(ULONG id); + ULONG tx_thread_entry_parameter; + + /* Define the thread's timer block. This is used for thread + sleep and timeout requests. */ + TX_TIMER_INTERNAL tx_thread_timer; + + /* Define the thread's cleanup function and associated data. This + is used to cleanup various data structures when a thread + suspension is lifted or terminated either by the user or + a timeout. */ + VOID (*tx_thread_suspend_cleanup)(struct TX_THREAD_STRUCT *thread_ptr, ULONG suspension_sequence); + VOID *tx_thread_suspend_control_block; + struct TX_THREAD_STRUCT + *tx_thread_suspended_next, + *tx_thread_suspended_previous; + ULONG tx_thread_suspend_info; + VOID *tx_thread_additional_suspend_info; + UINT tx_thread_suspend_option; + UINT tx_thread_suspend_status; + + /* Define the second port extension in the thread control block. This + is typically defined to whitespace or a pointer type in tx_port.h. */ + TX_THREAD_EXTENSION_1 + + /* Define pointers to the next and previous threads in the + created list. */ + struct TX_THREAD_STRUCT + *tx_thread_created_next, + *tx_thread_created_previous; + + /************* Define ThreadX SMP thread control block extensions. *************/ + + UINT tx_thread_smp_core_mapped; + ULONG tx_thread_smp_core_control; + UINT tx_thread_smp_core_executing; + + /************* End of ThreadX SMP thread control block extensions. *************/ + + /* Define the third port extension in the thread control block. This + is typically defined to whitespace in tx_port.h. */ + TX_THREAD_EXTENSION_2 + + /************* Define ThreadX SMP thread control block extensions. *************/ + + ULONG tx_thread_smp_cores_excluded; + ULONG tx_thread_smp_cores_allowed; + ULONG tx_thread_smp_lock_ready_bit; + + /************* End of ThreadX SMP thread control block extensions. *************/ + + /* Define a pointer type for FileX extensions. */ + VOID *tx_thread_filex_ptr; + + /* Define the priority inheritance variables. These will be used + to manage priority inheritance changes applied to this thread + as a result of mutex get operations. */ + UINT tx_thread_user_priority; + UINT tx_thread_user_preempt_threshold; + UINT tx_thread_inherit_priority; + + /* Define the owned mutex count and list head pointer. */ + UINT tx_thread_owned_mutex_count; + struct TX_MUTEX_STRUCT + *tx_thread_owned_mutex_list; + +#ifdef TX_THREAD_ENABLE_PERFORMANCE_INFO + + /* Define the number of times this thread is resumed. */ + ULONG tx_thread_performance_resume_count; + + /* Define the number of times this thread suspends. */ + ULONG tx_thread_performance_suspend_count; + + /* Define the number of times this thread is preempted by calling + a ThreadX API service. */ + ULONG tx_thread_performance_solicited_preemption_count; + + /* Define the number of times this thread is preempted by an + ISR calling a ThreadX API service. */ + ULONG tx_thread_performance_interrupt_preemption_count; + + /* Define the number of priority inversions for this thread. */ + ULONG tx_thread_performance_priority_inversion_count; + + /* Define the last thread pointer to preempt this thread. */ + struct TX_THREAD_STRUCT + *tx_thread_performance_last_preempting_thread; + + /* Define the total number of times this thread was time-sliced. */ + ULONG tx_thread_performance_time_slice_count; + + /* Define the total number of times this thread relinquishes. */ + ULONG tx_thread_performance_relinquish_count; + + /* Define the total number of times this thread had a timeout. */ + ULONG tx_thread_performance_timeout_count; + + /* Define the total number of times this thread had suspension lifted + because of the tx_thread_wait_abort service. */ + ULONG tx_thread_performance_wait_abort_count; +#endif + + /* Define the highest stack pointer variable. */ + VOID *tx_thread_stack_highest_ptr; /* Stack highest usage pointer */ + + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Define the application callback routine used to notify the application when + the thread is entered or exits. */ + VOID (*tx_thread_entry_exit_notify)(struct TX_THREAD_STRUCT *thread_ptr, UINT type); +#endif + + /* Define the fourth port extension in the thread control block. This + is typically defined to whitespace in tx_port.h. */ + TX_THREAD_EXTENSION_3 + + /* Define suspension sequence number. This is used to ensure suspension is still valid when + cleanup routine executes. */ + ULONG tx_thread_suspension_sequence; + + /* Define the user extension field. This typically is defined + to white space, but some ports of ThreadX may need to have + additional fields in the thread control block. This is + defined in the file tx_port.h. */ + TX_THREAD_USER_EXTENSION + +} TX_THREAD; + + +/* Define the block memory pool structure utilized by the application. */ + +typedef struct TX_BLOCK_POOL_STRUCT +{ + + /* Define the block pool ID used for error checking. */ + ULONG tx_block_pool_id; + + /* Define the block pool's name. */ + CHAR *tx_block_pool_name; + + /* Define the number of available memory blocks in the pool. */ + UINT tx_block_pool_available; + + /* Save the initial number of blocks. */ + UINT tx_block_pool_total; + + /* Define the head pointer of the available block pool. */ + UCHAR *tx_block_pool_available_list; + + /* Save the start address of the block pool's memory area. */ + UCHAR *tx_block_pool_start; + + /* Save the block pool's size in bytes. */ + ULONG tx_block_pool_size; + + /* Save the individual memory block size - rounded for alignment. */ + UINT tx_block_pool_block_size; + + /* Define the block pool suspension list head along with a count of + how many threads are suspended. */ + struct TX_THREAD_STRUCT + *tx_block_pool_suspension_list; + UINT tx_block_pool_suspended_count; + + /* Define the created list next and previous pointers. */ + struct TX_BLOCK_POOL_STRUCT + *tx_block_pool_created_next, + *tx_block_pool_created_previous; + +#ifdef TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO + + /* Define the number of block allocates. */ + ULONG tx_block_pool_performance_allocate_count; + + /* Define the number of block releases. */ + ULONG tx_block_pool_performance_release_count; + + /* Define the number of block pool suspensions. */ + ULONG tx_block_pool_performance_suspension_count; + + /* Define the number of block pool timeouts. */ + ULONG tx_block_pool_performance_timeout_count; +#endif + + /* Define the port extension in the block pool control block. This + is typically defined to whitespace in tx_port.h. */ + TX_BLOCK_POOL_EXTENSION + +} TX_BLOCK_POOL; + + +/* Determine if the byte allocate extension is defined. If not, define the + extension to whitespace. */ + +#ifndef TX_BYTE_ALLOCATE_EXTENSION +#define TX_BYTE_ALLOCATE_EXTENSION +#endif + + +/* Determine if the byte release extension is defined. If not, define the + extension to whitespace. */ + +#ifndef TX_BYTE_RELEASE_EXTENSION +#define TX_BYTE_RELEASE_EXTENSION +#endif + + +/* Define the byte memory pool structure utilized by the application. */ + +typedef struct TX_BYTE_POOL_STRUCT +{ + + /* Define the byte pool ID used for error checking. */ + ULONG tx_byte_pool_id; + + /* Define the byte pool's name. */ + CHAR *tx_byte_pool_name; + + /* Define the number of available bytes in the pool. */ + ULONG tx_byte_pool_available; + + /* Define the number of fragments in the pool. */ + UINT tx_byte_pool_fragments; + + /* Define the head pointer of byte pool. */ + UCHAR *tx_byte_pool_list; + + /* Define the search pointer used for initial searching for memory + in a byte pool. */ + UCHAR *tx_byte_pool_search; + + /* Save the start address of the byte pool's memory area. */ + UCHAR *tx_byte_pool_start; + + /* Save the byte pool's size in bytes. */ + ULONG tx_byte_pool_size; + + /* This is used to mark the owner of the byte memory pool during + a search. If this value changes during the search, the local search + pointer must be reset. */ + struct TX_THREAD_STRUCT + *tx_byte_pool_owner; + + /* Define the byte pool suspension list head along with a count of + how many threads are suspended. */ + struct TX_THREAD_STRUCT + *tx_byte_pool_suspension_list; + UINT tx_byte_pool_suspended_count; + + /* Define the created list next and previous pointers. */ + struct TX_BYTE_POOL_STRUCT + *tx_byte_pool_created_next, + *tx_byte_pool_created_previous; + +#ifdef TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO + + /* Define the number of allocates. */ + ULONG tx_byte_pool_performance_allocate_count; + + /* Define the number of releases. */ + ULONG tx_byte_pool_performance_release_count; + + /* Define the number of adjacent memory fragment merges. */ + ULONG tx_byte_pool_performance_merge_count; + + /* Define the number of memory fragment splits. */ + ULONG tx_byte_pool_performance_split_count; + + /* Define the number of memory fragments searched that either were not free or could not satisfy the + request. */ + ULONG tx_byte_pool_performance_search_count; + + /* Define the number of byte pool suspensions. */ + ULONG tx_byte_pool_performance_suspension_count; + + /* Define the number of byte pool timeouts. */ + ULONG tx_byte_pool_performance_timeout_count; +#endif + + /* Define the port extension in the byte pool control block. This + is typically defined to whitespace in tx_port.h. */ + TX_BYTE_POOL_EXTENSION + +} TX_BYTE_POOL; + + +/* Define the event flags group structure utilized by the application. */ + +typedef struct TX_EVENT_FLAGS_GROUP_STRUCT +{ + + /* Define the event flags group ID used for error checking. */ + ULONG tx_event_flags_group_id; + + /* Define the event flags group's name. */ + CHAR *tx_event_flags_group_name; + + /* Define the actual current event flags in this group. A zero in a + particular bit indicates the event flag is not set. */ + ULONG tx_event_flags_group_current; + + /* Define the reset search flag that is set when an ISR sets flags during + the search of the suspended threads list. */ + UINT tx_event_flags_group_reset_search; + + /* Define the event flags group suspension list head along with a count of + how many threads are suspended. */ + struct TX_THREAD_STRUCT + *tx_event_flags_group_suspension_list; + UINT tx_event_flags_group_suspended_count; + + /* Define the created list next and previous pointers. */ + struct TX_EVENT_FLAGS_GROUP_STRUCT + *tx_event_flags_group_created_next, + *tx_event_flags_group_created_previous; + + /* Define the delayed clearing event flags. */ + ULONG tx_event_flags_group_delayed_clear; + +#ifdef TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO + + /* Define the number of event flag sets. */ + ULONG tx_event_flags_group_performance_set_count; + + /* Define the number of event flag gets. */ + ULONG tx_event_flags_group__performance_get_count; + + /* Define the number of event flag suspensions. */ + ULONG tx_event_flags_group___performance_suspension_count; + + /* Define the number of event flag timeouts. */ + ULONG tx_event_flags_group____performance_timeout_count; +#endif + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Define the application callback routine used to notify the application when + an event flag is set. */ + VOID (*tx_event_flags_group_set_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); +#endif + + /* Define the port extension in the event flags group control block. This + is typically defined to whitespace in tx_port.h. */ + TX_EVENT_FLAGS_GROUP_EXTENSION + +} TX_EVENT_FLAGS_GROUP; + + +/* Determine if the mutex put extension 1 is defined. If not, define the + extension to whitespace. */ + +#ifndef TX_MUTEX_PUT_EXTENSION_1 +#define TX_MUTEX_PUT_EXTENSION_1 +#endif + + +/* Determine if the mutex put extension 2 is defined. If not, define the + extension to whitespace. */ + +#ifndef TX_MUTEX_PUT_EXTENSION_2 +#define TX_MUTEX_PUT_EXTENSION_2 +#endif + + +/* Determine if the mutex priority change extension is defined. If not, define the + extension to whitespace. */ + +#ifndef TX_MUTEX_PRIORITY_CHANGE_EXTENSION +#define TX_MUTEX_PRIORITY_CHANGE_EXTENSION +#endif + + +/* Define the mutex structure utilized by the application. */ + +typedef struct TX_MUTEX_STRUCT +{ + + /* Define the mutex ID used for error checking. */ + ULONG tx_mutex_id; + + /* Define the mutex's name. */ + CHAR *tx_mutex_name; + + /* Define the mutex ownership count. */ + UINT tx_mutex_ownership_count; + + /* Define the mutex ownership pointer. This pointer points to the + the thread that owns the mutex. */ + TX_THREAD *tx_mutex_owner; + + /* Define the priority inheritance flag. If this flag is set, priority + inheritance will be in effect. */ + UINT tx_mutex_inherit; + + /* Define the save area for the owning thread's original priority. */ + UINT tx_mutex_original_priority; + + /* Define the mutex suspension list head along with a count of + how many threads are suspended. */ + struct TX_THREAD_STRUCT + *tx_mutex_suspension_list; + UINT tx_mutex_suspended_count; + + /* Define the created list next and previous pointers. */ + struct TX_MUTEX_STRUCT + *tx_mutex_created_next, + *tx_mutex_created_previous; + + /* Define the priority of the highest priority thread waiting for + this mutex. */ + UINT tx_mutex_highest_priority_waiting; + + /* Define the owned list next and previous pointers. */ + struct TX_MUTEX_STRUCT + *tx_mutex_owned_next, + *tx_mutex_owned_previous; + +#ifdef TX_MUTEX_ENABLE_PERFORMANCE_INFO + + /* Define the number of mutex puts. */ + ULONG tx_mutex_performance_put_count; + + /* Define the total number of mutex gets. */ + ULONG tx_mutex_performance_get_count; + + /* Define the total number of mutex suspensions. */ + ULONG tx_mutex_performance_suspension_count; + + /* Define the total number of mutex timeouts. */ + ULONG tx_mutex_performance_timeout_count; + + /* Define the total number of priority inversions. */ + ULONG tx_mutex_performance_priority_inversion_count; + + /* Define the total number of priority inheritance conditions. */ + ULONG tx_mutex_performance__priority_inheritance_count; +#endif + + /* Define the port extension in the mutex control block. This + is typically defined to whitespace in tx_port.h. */ + TX_MUTEX_EXTENSION + +} TX_MUTEX; + + +/* Define the queue structure utilized by the application. */ + +typedef struct TX_QUEUE_STRUCT +{ + + /* Define the queue ID used for error checking. */ + ULONG tx_queue_id; + + /* Define the queue's name. */ + CHAR *tx_queue_name; + + /* Define the message size that was specified in queue creation. */ + UINT tx_queue_message_size; + + /* Define the total number of messages in the queue. */ + UINT tx_queue_capacity; + + /* Define the current number of messages enqueued and the available + queue storage space. */ + UINT tx_queue_enqueued; + UINT tx_queue_available_storage; + + /* Define pointers that represent the start and end for the queue's + message area. */ + ULONG *tx_queue_start; + ULONG *tx_queue_end; + + /* Define the queue read and write pointers. Send requests use the write + pointer while receive requests use the read pointer. */ + ULONG *tx_queue_read; + ULONG *tx_queue_write; + + /* Define the queue suspension list head along with a count of + how many threads are suspended. */ + struct TX_THREAD_STRUCT + *tx_queue_suspension_list; + UINT tx_queue_suspended_count; + + /* Define the created list next and previous pointers. */ + struct TX_QUEUE_STRUCT + *tx_queue_created_next, + *tx_queue_created_previous; + +#ifdef TX_QUEUE_ENABLE_PERFORMANCE_INFO + + /* Define the number of messages sent to this queue. */ + ULONG tx_queue_performance_messages_sent_count; + + /* Define the number of messages received from this queue. */ + ULONG tx_queue_performance_messages_received_count; + + /* Define the number of empty suspensions on this queue. */ + ULONG tx_queue_performance_empty_suspension_count; + + /* Define the number of full suspensions on this queue. */ + ULONG tx_queue_performance_full_suspension_count; + + /* Define the number of full non-suspensions on this queue. These + messages are rejected with an appropriate error code. */ + ULONG tx_queue_performance_full_error_count; + + /* Define the number of queue timeouts. */ + ULONG tx_queue_performance_timeout_count; +#endif + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Define the application callback routine used to notify the application when + the a message is sent to the queue. */ + VOID (*tx_queue_send_notify)(struct TX_QUEUE_STRUCT *queue_ptr); +#endif + + /* Define the port extension in the queue control block. This + is typically defined to whitespace in tx_port.h. */ + TX_QUEUE_EXTENSION + +} TX_QUEUE; + + +/* Define the semaphore structure utilized by the application. */ + +typedef struct TX_SEMAPHORE_STRUCT +{ + + /* Define the semaphore ID used for error checking. */ + ULONG tx_semaphore_id; + + /* Define the semaphore's name. */ + CHAR *tx_semaphore_name; + + /* Define the actual semaphore count. A zero means that no semaphore + instance is available. */ + ULONG tx_semaphore_count; + + /* Define the semaphore suspension list head along with a count of + how many threads are suspended. */ + struct TX_THREAD_STRUCT + *tx_semaphore_suspension_list; + UINT tx_semaphore_suspended_count; + + /* Define the created list next and previous pointers. */ + struct TX_SEMAPHORE_STRUCT + *tx_semaphore_created_next, + *tx_semaphore_created_previous; + +#ifdef TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO + + /* Define the number of semaphore puts. */ + ULONG tx_semaphore_performance_put_count; + + /* Define the number of semaphore gets. */ + ULONG tx_semaphore_performance_get_count; + + /* Define the number of semaphore suspensions. */ + ULONG tx_semaphore_performance_suspension_count; + + /* Define the number of semaphore timeouts. */ + ULONG tx_semaphore_performance_timeout_count; +#endif + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Define the application callback routine used to notify the application when + the a semaphore is put. */ + VOID (*tx_semaphore_put_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); +#endif + + /* Define the port extension in the semaphore control block. This + is typically defined to whitespace in tx_port.h. */ + TX_SEMAPHORE_EXTENSION + +} TX_SEMAPHORE; + + +/************* Define ThreadX SMP function prototypes and remapping. *************/ + +/* Re-map user API to internal API for SMP routines. */ + +#ifndef TX_SOURCE_CODE +#define tx_thread_smp_core_exclude _tx_thread_smp_core_exclude +#define tx_thread_smp_core_exclude_get _tx_thread_smp_core_exclude_get +#define tx_thread_smp_core_get _tx_thread_smp_core_get +#define tx_timer_smp_core_exclude _tx_timer_smp_core_exclude +#define tx_timer_smp_core_exclude_get _tx_timer_smp_core_exclude_get +#endif + + +#ifndef TX_MISRA_ENABLE + +/* Define external data references for SMP. */ +#ifndef TX_SOURCE_CODE +extern ULONG volatile _tx_timer_system_clock; +#endif +#endif + + +/* Define all SMP prototypes for calling from C. */ + +UINT _tx_thread_smp_core_exclude(TX_THREAD *thread_ptr, ULONG exclusion_map); +UINT _tx_thread_smp_core_exclude_get(TX_THREAD *thread_ptr, ULONG *exclusion_map_ptr); +UINT _tx_thread_smp_core_get(void); +UINT _tx_timer_smp_core_exclude(TX_TIMER *timer_ptr, ULONG exclusion_map); +UINT _tx_timer_smp_core_exclude_get(TX_TIMER *timer_ptr, ULONG *exclusion_map_ptr); + +/* Define ThreadX SMP low-level assembly routines. */ + +TX_THREAD *_tx_thread_smp_current_thread_get(void); +UINT _tx_thread_smp_protect(void); +void _tx_thread_smp_unprotect(UINT interrupt_save); +ULONG _tx_thread_smp_current_state_get(void); +ULONG _tx_thread_smp_time_get(void); + + +/* Determine if SMP Debug is selected. If so, the function prototype is setup. Otherwise, the debug call is + simply mapped to whitespace. */ + +#ifdef TX_THREAD_SMP_DEBUG_ENABLE +void _tx_thread_smp_debug_entry_insert(ULONG id, ULONG suspend, VOID *thread_ptr); +#endif + + +/* Define the get thread macro. */ + +#define TX_THREAD_GET_CURRENT(a) (a) = (TX_THREAD *) _tx_thread_smp_current_thread_get(); + + +/* Define the get core ID macro. */ + +#define TX_SMP_CORE_ID _tx_thread_smp_core_get() + + +/************* End of ThreadX SMP function prototypes and remapping. *************/ + + +/* Define the system API mappings based on the error checking + selected by the user. Note: this section is only applicable to + application source code, hence the conditional that turns off this + stuff when the include file is processed by the ThreadX source. */ + +#ifndef TX_SOURCE_CODE + + +/* Determine if error checking is desired. If so, map API functions + to the appropriate error checking front-ends. Otherwise, map API + functions to the core functions that actually perform the work. + Note: error checking is enabled by default. */ + +#ifdef TX_DISABLE_ERROR_CHECKING + + +/* Services without error checking. */ + +#define tx_kernel_enter _tx_initialize_kernel_enter + +#define tx_block_allocate _tx_block_allocate +#define tx_block_pool_create _tx_block_pool_create +#define tx_block_pool_delete _tx_block_pool_delete +#define tx_block_pool_info_get _tx_block_pool_info_get +#define tx_block_pool_performance_info_get _tx_block_pool_performance_info_get +#define tx_block_pool_performance_system_info_get _tx_block_pool_performance_system_info_get +#define tx_block_pool_prioritize _tx_block_pool_prioritize +#define tx_block_release _tx_block_release + +#define tx_byte_allocate _tx_byte_allocate +#define tx_byte_pool_create _tx_byte_pool_create +#define tx_byte_pool_delete _tx_byte_pool_delete +#define tx_byte_pool_info_get _tx_byte_pool_info_get +#define tx_byte_pool_performance_info_get _tx_byte_pool_performance_info_get +#define tx_byte_pool_performance_system_info_get _tx_byte_pool_performance_system_info_get +#define tx_byte_pool_prioritize _tx_byte_pool_prioritize +#define tx_byte_release _tx_byte_release + +#define tx_event_flags_create _tx_event_flags_create +#define tx_event_flags_delete _tx_event_flags_delete +#define tx_event_flags_get _tx_event_flags_get +#define tx_event_flags_info_get _tx_event_flags_info_get +#define tx_event_flags_performance_info_get _tx_event_flags_performance_info_get +#define tx_event_flags_performance_system_info_get _tx_event_flags_performance_system_info_get +#define tx_event_flags_set _tx_event_flags_set +#define tx_event_flags_set_notify _tx_event_flags_set_notify + +#ifdef TX_ENABLE_EVENT_LOGGING +UINT _tx_el_interrupt_control(UINT new_posture); +#define tx_interrupt_control _tx_el_interrupt_control +#else +#ifdef TX_ENABLE_EVENT_TRACE +#define tx_interrupt_control _tx_trace_interrupt_control +#else +#define tx_interrupt_control _tx_thread_interrupt_control +#endif +#endif + +#define tx_mutex_create _tx_mutex_create +#define tx_mutex_delete _tx_mutex_delete +#define tx_mutex_get _tx_mutex_get +#define tx_mutex_info_get _tx_mutex_info_get +#define tx_mutex_performance_info_get _tx_mutex_performance_info_get +#define tx_mutex_performance_system_info_get _tx_mutex_performance_system_info_get +#define tx_mutex_prioritize _tx_mutex_prioritize +#define tx_mutex_put _tx_mutex_put + +#define tx_queue_create _tx_queue_create +#define tx_queue_delete _tx_queue_delete +#define tx_queue_flush _tx_queue_flush +#define tx_queue_info_get _tx_queue_info_get +#define tx_queue_performance_info_get _tx_queue_performance_info_get +#define tx_queue_performance_system_info_get _tx_queue_performance_system_info_get +#define tx_queue_receive _tx_queue_receive +#define tx_queue_send _tx_queue_send +#define tx_queue_send_notify _tx_queue_send_notify +#define tx_queue_front_send _tx_queue_front_send +#define tx_queue_prioritize _tx_queue_prioritize + +#define tx_semaphore_ceiling_put _tx_semaphore_ceiling_put +#define tx_semaphore_create _tx_semaphore_create +#define tx_semaphore_delete _tx_semaphore_delete +#define tx_semaphore_get _tx_semaphore_get +#define tx_semaphore_info_get _tx_semaphore_info_get +#define tx_semaphore_performance_info_get _tx_semaphore_performance_info_get +#define tx_semaphore_performance_system_info_get _tx_semaphore_performance_system_info_get +#define tx_semaphore_prioritize _tx_semaphore_prioritize +#define tx_semaphore_put _tx_semaphore_put +#define tx_semaphore_put_notify _tx_semaphore_put_notify + +#define tx_thread_create _tx_thread_create +#define tx_thread_delete _tx_thread_delete +#define tx_thread_entry_exit_notify _tx_thread_entry_exit_notify +#define tx_thread_identify _tx_thread_identify +#define tx_thread_info_get _tx_thread_info_get +#define tx_thread_performance_info_get _tx_thread_performance_info_get +#define tx_thread_performance_system_info_get _tx_thread_performance_system_info_get +#define tx_thread_preemption_change _tx_thread_preemption_change +#define tx_thread_priority_change _tx_thread_priority_change +#define tx_thread_relinquish _tx_thread_relinquish +#define tx_thread_reset _tx_thread_reset +#define tx_thread_resume _tx_thread_resume +#define tx_thread_sleep _tx_thread_sleep +#define tx_thread_stack_error_notify _tx_thread_stack_error_notify +#define tx_thread_suspend _tx_thread_suspend +#define tx_thread_terminate _tx_thread_terminate +#define tx_thread_time_slice_change _tx_thread_time_slice_change +#define tx_thread_wait_abort _tx_thread_wait_abort + +/************* Define ThreadX SMP remapping of tx_time_get. *************/ +#ifndef TX_MISRA_ENABLE +#define tx_time_get() (_tx_timer_system_clock) +#else +#define tx_time_get _tx_time_get +#endif +/************* End ThreadX SMP remapping of tx_time_get. *************/ +#define tx_time_set _tx_time_set +#define tx_timer_activate _tx_timer_activate +#define tx_timer_change _tx_timer_change +#define tx_timer_create _tx_timer_create +#define tx_timer_deactivate _tx_timer_deactivate +#define tx_timer_delete _tx_timer_delete +#define tx_timer_info_get _tx_timer_info_get +#define tx_timer_performance_info_get _tx_timer_performance_info_get +#define tx_timer_performance_system_info_get _tx_timer_performance_system_info_get + +#define tx_trace_enable _tx_trace_enable +#define tx_trace_event_filter _tx_trace_event_filter +#define tx_trace_event_unfilter _tx_trace_event_unfilter +#define tx_trace_disable _tx_trace_disable +#define tx_trace_isr_enter_insert _tx_trace_isr_enter_insert +#define tx_trace_isr_exit_insert _tx_trace_isr_exit_insert +#define tx_trace_buffer_full_notify _tx_trace_buffer_full_notify +#define tx_trace_user_event_insert _tx_trace_user_event_insert + +#else + +/* Services with error checking. */ + +#define tx_kernel_enter _tx_initialize_kernel_enter + +/* Define the system API mappings depending on the runtime error + checking behavior selected by the user. */ + +#ifdef TX_ENABLE_MULTI_ERROR_CHECKING + + +/* Services with MULTI runtime error checking ThreadX. */ + +#define tx_block_allocate _txr_block_allocate +#define tx_block_pool_create(p,n,b,s,l) _txr_block_pool_create((p),(n),(b),(s),(l),(sizeof(TX_BLOCK_POOL))) +#define tx_block_pool_delete _txr_block_pool_delete +#define tx_block_pool_info_get _txr_block_pool_info_get +#define tx_block_pool_performance_info_get _tx_block_pool_performance_info_get +#define tx_block_pool_performance_system_info_get _tx_block_pool_performance_system_info_get +#define tx_block_pool_prioritize _txr_block_pool_prioritize +#define tx_block_release _txr_block_release + +#define tx_byte_allocate _txr_byte_allocate +#define tx_byte_pool_create(p,n,s,l) _txr_byte_pool_create((p),(n),(s),(l),(sizeof(TX_BYTE_POOL))) +#define tx_byte_pool_delete _txr_byte_pool_delete +#define tx_byte_pool_info_get _txr_byte_pool_info_get +#define tx_byte_pool_performance_info_get _tx_byte_pool_performance_info_get +#define tx_byte_pool_performance_system_info_get _tx_byte_pool_performance_system_info_get +#define tx_byte_pool_prioritize _txr_byte_pool_prioritize +#define tx_byte_release _txr_byte_release + +#define tx_event_flags_create(g,n) _txr_event_flags_create((g),(n),(sizeof(TX_EVENT_FLAGS_GROUP))) +#define tx_event_flags_delete _txr_event_flags_delete +#define tx_event_flags_get _txr_event_flags_get +#define tx_event_flags_info_get _txr_event_flags_info_get +#define tx_event_flags_performance_info_get _tx_event_flags_performance_info_get +#define tx_event_flags_performance_system_info_get _tx_event_flags_performance_system_info_get +#define tx_event_flags_set _txr_event_flags_set +#define tx_event_flags_set_notify _txr_event_flags_set_notify + +#ifdef TX_ENABLE_EVENT_LOGGING +UINT _tx_el_interrupt_control(UINT new_posture); +#define tx_interrupt_control _tx_el_interrupt_control +#else +#ifdef TX_ENABLE_EVENT_TRACE +#define tx_interrupt_control _tx_trace_interrupt_control +#else +#define tx_interrupt_control _tx_thread_interrupt_control +#endif +#endif + +#define tx_mutex_create(m,n,i) _txr_mutex_create((m),(n),(i),(sizeof(TX_MUTEX))) +#define tx_mutex_delete _txr_mutex_delete +#define tx_mutex_get _txr_mutex_get +#define tx_mutex_info_get _txr_mutex_info_get +#define tx_mutex_performance_info_get _tx_mutex_performance_info_get +#define tx_mutex_performance_system_info_get _tx_mutex_performance_system_info_get +#define tx_mutex_prioritize _txr_mutex_prioritize +#define tx_mutex_put _txr_mutex_put + +#define tx_queue_create(q,n,m,s,l) _txr_queue_create((q),(n),(m),(s),(l),(sizeof(TX_QUEUE))) +#define tx_queue_delete _txr_queue_delete +#define tx_queue_flush _txr_queue_flush +#define tx_queue_info_get _txr_queue_info_get +#define tx_queue_performance_info_get _tx_queue_performance_info_get +#define tx_queue_performance_system_info_get _tx_queue_performance_system_info_get +#define tx_queue_receive _txr_queue_receive +#define tx_queue_send _txr_queue_send +#define tx_queue_send_notify _txr_queue_send_notify +#define tx_queue_front_send _txr_queue_front_send +#define tx_queue_prioritize _txr_queue_prioritize + +#define tx_semaphore_ceiling_put _txr_semaphore_ceiling_put +#define tx_semaphore_create(s,n,i) _txr_semaphore_create((s),(n),(i),(sizeof(TX_SEMAPHORE))) +#define tx_semaphore_delete _txr_semaphore_delete +#define tx_semaphore_get _txr_semaphore_get +#define tx_semaphore_info_get _txr_semaphore_info_get +#define tx_semaphore_performance_info_get _tx_semaphore_performance_info_get +#define tx_semaphore_performance_system_info_get _tx_semaphore_performance_system_info_get +#define tx_semaphore_prioritize _txr_semaphore_prioritize +#define tx_semaphore_put _txr_semaphore_put +#define tx_semaphore_put_notify _txr_semaphore_put_notify + +#define tx_thread_create(t,n,e,i,s,l,p,r,c,a) _txr_thread_create((t),(n),(e),(i),(s),(l),(p),(r),(c),(a),(sizeof(TX_THREAD))) +#define tx_thread_delete _txr_thread_delete +#define tx_thread_entry_exit_notify _txr_thread_entry_exit_notify +#define tx_thread_identify _tx_thread_identify +#define tx_thread_info_get _txr_thread_info_get +#define tx_thread_performance_info_get _tx_thread_performance_info_get +#define tx_thread_performance_system_info_get _tx_thread_performance_system_info_get +#define tx_thread_preemption_change _txr_thread_preemption_change +#define tx_thread_priority_change _txr_thread_priority_change +#define tx_thread_relinquish _txe_thread_relinquish +#define tx_thread_reset _txr_thread_reset +#define tx_thread_resume _txr_thread_resume +#define tx_thread_sleep _tx_thread_sleep +#define tx_thread_stack_error_notify _tx_thread_stack_error_notify +#define tx_thread_suspend _txr_thread_suspend +#define tx_thread_terminate _txr_thread_terminate +#define tx_thread_time_slice_change _txr_thread_time_slice_change +#define tx_thread_wait_abort _txr_thread_wait_abort + +/************* Define ThreadX SMP remapping of tx_time_get. *************/ +#ifndef TX_MISRA_ENABLE +#define tx_time_get() (_tx_timer_system_clock) +#else +#define tx_time_get _tx_time_get +#endif +/************* End ThreadX SMP remapping of tx_time_get. *************/ +#define tx_time_set _tx_time_set +#define tx_timer_activate _txr_timer_activate +#define tx_timer_change _txr_timer_change +#define tx_timer_create(t,n,e,i,c,r,a) _txr_timer_create((t),(n),(e),(i),(c),(r),(a),(sizeof(TX_TIMER))) +#define tx_timer_deactivate _txr_timer_deactivate +#define tx_timer_delete _txr_timer_delete +#define tx_timer_info_get _txr_timer_info_get +#define tx_timer_performance_info_get _tx_timer_performance_info_get +#define tx_timer_performance_system_info_get _tx_timer_performance_system_info_get + +#define tx_trace_enable _tx_trace_enable +#define tx_trace_event_filter _tx_trace_event_filter +#define tx_trace_event_unfilter _tx_trace_event_unfilter +#define tx_trace_disable _tx_trace_disable +#define tx_trace_isr_enter_insert _tx_trace_isr_enter_insert +#define tx_trace_isr_exit_insert _tx_trace_isr_exit_insert +#define tx_trace_buffer_full_notify _tx_trace_buffer_full_notify +#define tx_trace_user_event_insert _tx_trace_user_event_insert + +#else + +#define tx_block_allocate _txe_block_allocate +#define tx_block_pool_create(p,n,b,s,l) _txe_block_pool_create((p),(n),(b),(s),(l),(sizeof(TX_BLOCK_POOL))) +#define tx_block_pool_delete _txe_block_pool_delete +#define tx_block_pool_info_get _txe_block_pool_info_get +#define tx_block_pool_performance_info_get _tx_block_pool_performance_info_get +#define tx_block_pool_performance_system_info_get _tx_block_pool_performance_system_info_get +#define tx_block_pool_prioritize _txe_block_pool_prioritize +#define tx_block_release _txe_block_release + +#define tx_byte_allocate _txe_byte_allocate +#define tx_byte_pool_create(p,n,s,l) _txe_byte_pool_create((p),(n),(s),(l),(sizeof(TX_BYTE_POOL))) +#define tx_byte_pool_delete _txe_byte_pool_delete +#define tx_byte_pool_info_get _txe_byte_pool_info_get +#define tx_byte_pool_performance_info_get _tx_byte_pool_performance_info_get +#define tx_byte_pool_performance_system_info_get _tx_byte_pool_performance_system_info_get +#define tx_byte_pool_prioritize _txe_byte_pool_prioritize +#define tx_byte_release _txe_byte_release + +#define tx_event_flags_create(g,n) _txe_event_flags_create((g),(n),(sizeof(TX_EVENT_FLAGS_GROUP))) +#define tx_event_flags_delete _txe_event_flags_delete +#define tx_event_flags_get _txe_event_flags_get +#define tx_event_flags_info_get _txe_event_flags_info_get +#define tx_event_flags_performance_info_get _tx_event_flags_performance_info_get +#define tx_event_flags_performance_system_info_get _tx_event_flags_performance_system_info_get +#define tx_event_flags_set _txe_event_flags_set +#define tx_event_flags_set_notify _txe_event_flags_set_notify + +#ifdef TX_ENABLE_EVENT_LOGGING +UINT _tx_el_interrupt_control(UINT new_posture); +#define tx_interrupt_control _tx_el_interrupt_control +#else +#ifdef TX_ENABLE_EVENT_TRACE +#define tx_interrupt_control _tx_trace_interrupt_control +#else +#define tx_interrupt_control _tx_thread_interrupt_control +#endif +#endif + +#define tx_mutex_create(m,n,i) _txe_mutex_create((m),(n),(i),(sizeof(TX_MUTEX))) +#define tx_mutex_delete _txe_mutex_delete +#define tx_mutex_get _txe_mutex_get +#define tx_mutex_info_get _txe_mutex_info_get +#define tx_mutex_performance_info_get _tx_mutex_performance_info_get +#define tx_mutex_performance_system_info_get _tx_mutex_performance_system_info_get +#define tx_mutex_prioritize _txe_mutex_prioritize +#define tx_mutex_put _txe_mutex_put + +#define tx_queue_create(q,n,m,s,l) _txe_queue_create((q),(n),(m),(s),(l),(sizeof(TX_QUEUE))) +#define tx_queue_delete _txe_queue_delete +#define tx_queue_flush _txe_queue_flush +#define tx_queue_info_get _txe_queue_info_get +#define tx_queue_performance_info_get _tx_queue_performance_info_get +#define tx_queue_performance_system_info_get _tx_queue_performance_system_info_get +#define tx_queue_receive _txe_queue_receive +#define tx_queue_send _txe_queue_send +#define tx_queue_send_notify _txe_queue_send_notify +#define tx_queue_front_send _txe_queue_front_send +#define tx_queue_prioritize _txe_queue_prioritize + +#define tx_semaphore_ceiling_put _txe_semaphore_ceiling_put +#define tx_semaphore_create(s,n,i) _txe_semaphore_create((s),(n),(i),(sizeof(TX_SEMAPHORE))) +#define tx_semaphore_delete _txe_semaphore_delete +#define tx_semaphore_get _txe_semaphore_get +#define tx_semaphore_info_get _txe_semaphore_info_get +#define tx_semaphore_performance_info_get _tx_semaphore_performance_info_get +#define tx_semaphore_performance_system_info_get _tx_semaphore_performance_system_info_get +#define tx_semaphore_prioritize _txe_semaphore_prioritize +#define tx_semaphore_put _txe_semaphore_put +#define tx_semaphore_put_notify _txe_semaphore_put_notify + +#define tx_thread_create(t,n,e,i,s,l,p,r,c,a) _txe_thread_create((t),(n),(e),(i),(s),(l),(p),(r),(c),(a),(sizeof(TX_THREAD))) +#define tx_thread_delete _txe_thread_delete +#define tx_thread_entry_exit_notify _txe_thread_entry_exit_notify +#define tx_thread_identify _tx_thread_identify +#define tx_thread_info_get _txe_thread_info_get +#define tx_thread_performance_info_get _tx_thread_performance_info_get +#define tx_thread_performance_system_info_get _tx_thread_performance_system_info_get +#define tx_thread_preemption_change _txe_thread_preemption_change +#define tx_thread_priority_change _txe_thread_priority_change +#define tx_thread_relinquish _txe_thread_relinquish +#define tx_thread_reset _txe_thread_reset +#define tx_thread_resume _txe_thread_resume +#define tx_thread_sleep _tx_thread_sleep +#define tx_thread_stack_error_notify _tx_thread_stack_error_notify +#define tx_thread_suspend _txe_thread_suspend +#define tx_thread_terminate _txe_thread_terminate +#define tx_thread_time_slice_change _txe_thread_time_slice_change +#define tx_thread_wait_abort _txe_thread_wait_abort + +/************* Define ThreadX SMP remapping of tx_time_get. *************/ +#ifndef TX_MISRA_ENABLE +#define tx_time_get() (_tx_timer_system_clock) +#else +#define tx_time_get _tx_time_get +#endif +/************* End ThreadX SMP remapping of tx_time_get. *************/ +#define tx_time_set _tx_time_set +#define tx_timer_activate _txe_timer_activate +#define tx_timer_change _txe_timer_change +#define tx_timer_create(t,n,e,i,c,r,a) _txe_timer_create((t),(n),(e),(i),(c),(r),(a),(sizeof(TX_TIMER))) +#define tx_timer_deactivate _txe_timer_deactivate +#define tx_timer_delete _txe_timer_delete +#define tx_timer_info_get _txe_timer_info_get +#define tx_timer_performance_info_get _tx_timer_performance_info_get +#define tx_timer_performance_system_info_get _tx_timer_performance_system_info_get + +#define tx_trace_enable _tx_trace_enable +#define tx_trace_event_filter _tx_trace_event_filter +#define tx_trace_event_unfilter _tx_trace_event_unfilter +#define tx_trace_disable _tx_trace_disable +#define tx_trace_isr_enter_insert _tx_trace_isr_enter_insert +#define tx_trace_isr_exit_insert _tx_trace_isr_exit_insert +#define tx_trace_buffer_full_notify _tx_trace_buffer_full_notify +#define tx_trace_user_event_insert _tx_trace_user_event_insert + +#endif +#endif + +#endif + + +/* Declare the tx_application_define function as having C linkage. */ + +VOID tx_application_define(VOID *first_unused_memory); + + +/* Define the function prototypes of the ThreadX API. */ + + +/* Define block memory pool management function prototypes. */ + +UINT _tx_block_allocate(TX_BLOCK_POOL *pool_ptr, VOID **block_ptr, ULONG wait_option); +UINT _tx_block_pool_create(TX_BLOCK_POOL *pool_ptr, CHAR *name_ptr, ULONG block_size, + VOID *pool_start, ULONG pool_size); +UINT _tx_block_pool_delete(TX_BLOCK_POOL *pool_ptr); +UINT _tx_block_pool_info_get(TX_BLOCK_POOL *pool_ptr, CHAR **name, ULONG *available_blocks, + ULONG *total_blocks, TX_THREAD **first_suspended, + ULONG *suspended_count, TX_BLOCK_POOL **next_pool); +UINT _tx_block_pool_performance_info_get(TX_BLOCK_POOL *pool_ptr, ULONG *allocates, ULONG *releases, + ULONG *suspensions, ULONG *timeouts); +UINT _tx_block_pool_performance_system_info_get(ULONG *allocates, ULONG *releases, + ULONG *suspensions, ULONG *timeouts); +UINT _tx_block_pool_prioritize(TX_BLOCK_POOL *pool_ptr); +UINT _tx_block_release(VOID *block_ptr); + + +/* Define error checking shells for API services. These are only referenced by the + application. */ + +UINT _txe_block_allocate(TX_BLOCK_POOL *pool_ptr, VOID **block_ptr, ULONG wait_option); +UINT _txe_block_pool_create(TX_BLOCK_POOL *pool_ptr, CHAR *name_ptr, ULONG block_size, + VOID *pool_start, ULONG pool_size, UINT pool_control_block_size); +UINT _txe_block_pool_delete(TX_BLOCK_POOL *pool_ptr); +UINT _txe_block_pool_info_get(TX_BLOCK_POOL *pool_ptr, CHAR **name, ULONG *available_blocks, + ULONG *total_blocks, TX_THREAD **first_suspended, + ULONG *suspended_count, TX_BLOCK_POOL **next_pool); +UINT _txe_block_pool_prioritize(TX_BLOCK_POOL *pool_ptr); +UINT _txe_block_release(VOID *block_ptr); + + +/* Define byte memory pool management function prototypes. */ + +UINT _tx_byte_allocate(TX_BYTE_POOL *pool_ptr, VOID **memory_ptr, ULONG memory_size, + ULONG wait_option); +UINT _tx_byte_pool_create(TX_BYTE_POOL *pool_ptr, CHAR *name_ptr, VOID *pool_start, + ULONG pool_size); +UINT _tx_byte_pool_delete(TX_BYTE_POOL *pool_ptr); +UINT _tx_byte_pool_info_get(TX_BYTE_POOL *pool_ptr, CHAR **name, ULONG *available_bytes, + ULONG *fragments, TX_THREAD **first_suspended, + ULONG *suspended_count, TX_BYTE_POOL **next_pool); +UINT _tx_byte_pool_performance_info_get(TX_BYTE_POOL *pool_ptr, ULONG *allocates, ULONG *releases, + ULONG *fragments_searched, ULONG *merges, ULONG *splits, ULONG *suspensions, ULONG *timeouts); +UINT _tx_byte_pool_performance_system_info_get(ULONG *allocates, ULONG *releases, + ULONG *fragments_searched, ULONG *merges, ULONG *splits, ULONG *suspensions, ULONG *timeouts); +UINT _tx_byte_pool_prioritize(TX_BYTE_POOL *pool_ptr); +UINT _tx_byte_release(VOID *memory_ptr); + + +/* Define error checking shells for API services. These are only referenced by the + application. */ + +UINT _txe_byte_allocate(TX_BYTE_POOL *pool_ptr, VOID **memory_ptr, ULONG memory_size, + ULONG wait_option); +UINT _txe_byte_pool_create(TX_BYTE_POOL *pool_ptr, CHAR *name_ptr, VOID *pool_start, + ULONG pool_size, UINT pool_control_block_size); +UINT _txe_byte_pool_delete(TX_BYTE_POOL *pool_ptr); +UINT _txe_byte_pool_info_get(TX_BYTE_POOL *pool_ptr, CHAR **name, ULONG *available_bytes, + ULONG *fragments, TX_THREAD **first_suspended, + ULONG *suspended_count, TX_BYTE_POOL **next_pool); +UINT _txe_byte_pool_prioritize(TX_BYTE_POOL *pool_ptr); +UINT _txe_byte_release(VOID *memory_ptr); + + +/* Define event flags management function prototypes. */ + +UINT _tx_event_flags_create(TX_EVENT_FLAGS_GROUP *group_ptr, CHAR *name_ptr); +UINT _tx_event_flags_delete(TX_EVENT_FLAGS_GROUP *group_ptr); +UINT _tx_event_flags_get(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG requested_flags, + UINT get_option, ULONG *actual_flags_ptr, ULONG wait_option); +UINT _tx_event_flags_info_get(TX_EVENT_FLAGS_GROUP *group_ptr, CHAR **name, ULONG *current_flags, + TX_THREAD **first_suspended, ULONG *suspended_count, + TX_EVENT_FLAGS_GROUP **next_group); +UINT _tx_event_flags_performance_info_get(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG *sets, ULONG *gets, + ULONG *suspensions, ULONG *timeouts); +UINT _tx_event_flags_performance_system_info_get(ULONG *sets, ULONG *gets, + ULONG *suspensions, ULONG *timeouts); +UINT _tx_event_flags_set(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG flags_to_set, + UINT set_option); +UINT _tx_event_flags_set_notify(TX_EVENT_FLAGS_GROUP *group_ptr, VOID (*events_set_notify)(TX_EVENT_FLAGS_GROUP *notify_group_ptr)); + + +/* Define error checking shells for API services. These are only referenced by the + application. */ + +UINT _txe_event_flags_create(TX_EVENT_FLAGS_GROUP *group_ptr, CHAR *name_ptr, UINT event_control_block_size); +UINT _txe_event_flags_delete(TX_EVENT_FLAGS_GROUP *group_ptr); +UINT _txe_event_flags_get(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG requested_flags, + UINT get_option, ULONG *actual_flags_ptr, ULONG wait_option); +UINT _txe_event_flags_info_get(TX_EVENT_FLAGS_GROUP *group_ptr, CHAR **name, ULONG *current_flags, + TX_THREAD **first_suspended, ULONG *suspended_count, + TX_EVENT_FLAGS_GROUP **next_group); +UINT _txe_event_flags_set(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG flags_to_set, + UINT set_option); +UINT _txe_event_flags_set_notify(TX_EVENT_FLAGS_GROUP *group_ptr, VOID (*events_set_notify)(TX_EVENT_FLAGS_GROUP *notify_group_ptr)); + + +/* Define initialization function prototypes. */ + +VOID _tx_initialize_kernel_enter(VOID); + + +/* Define mutex management function prototypes. */ + +UINT _tx_mutex_create(TX_MUTEX *mutex_ptr, CHAR *name_ptr, UINT inherit); +UINT _tx_mutex_delete(TX_MUTEX *mutex_ptr); +UINT _tx_mutex_get(TX_MUTEX *mutex_ptr, ULONG wait_option); +UINT _tx_mutex_info_get(TX_MUTEX *mutex_ptr, CHAR **name, ULONG *count, TX_THREAD **owner, + TX_THREAD **first_suspended, ULONG *suspended_count, + TX_MUTEX **next_mutex); +UINT _tx_mutex_performance_info_get(TX_MUTEX *mutex_ptr, ULONG *puts, ULONG *gets, + ULONG *suspensions, ULONG *timeouts, ULONG *inversions, ULONG *inheritances); +UINT _tx_mutex_performance_system_info_get(ULONG *puts, ULONG *gets, ULONG *suspensions, ULONG *timeouts, + ULONG *inversions, ULONG *inheritances); +UINT _tx_mutex_prioritize(TX_MUTEX *mutex_ptr); +UINT _tx_mutex_put(TX_MUTEX *mutex_ptr); + + +/* Define error checking shells for API services. These are only referenced by the + application. */ + +UINT _txe_mutex_create(TX_MUTEX *mutex_ptr, CHAR *name_ptr, UINT inherit, UINT mutex_control_block_size); +UINT _txe_mutex_delete(TX_MUTEX *mutex_ptr); +UINT _txe_mutex_get(TX_MUTEX *mutex_ptr, ULONG wait_option); +UINT _txe_mutex_info_get(TX_MUTEX *mutex_ptr, CHAR **name, ULONG *count, TX_THREAD **owner, + TX_THREAD **first_suspended, ULONG *suspended_count, + TX_MUTEX **next_mutex); +UINT _txe_mutex_prioritize(TX_MUTEX *mutex_ptr); +UINT _txe_mutex_put(TX_MUTEX *mutex_ptr); + + +/* Define queue management function prototypes. */ + +UINT _tx_queue_create(TX_QUEUE *queue_ptr, CHAR *name_ptr, UINT message_size, + VOID *queue_start, ULONG queue_size); +UINT _tx_queue_delete(TX_QUEUE *queue_ptr); +UINT _tx_queue_flush(TX_QUEUE *queue_ptr); +UINT _tx_queue_info_get(TX_QUEUE *queue_ptr, CHAR **name, ULONG *enqueued, ULONG *available_storage, + TX_THREAD **first_suspended, ULONG *suspended_count, TX_QUEUE **next_queue); +UINT _tx_queue_performance_info_get(TX_QUEUE *queue_ptr, ULONG *messages_sent, ULONG *messages_received, + ULONG *empty_suspensions, ULONG *full_suspensions, ULONG *full_errors, ULONG *timeouts); +UINT _tx_queue_performance_system_info_get(ULONG *messages_sent, ULONG *messages_received, + ULONG *empty_suspensions, ULONG *full_suspensions, ULONG *full_errors, ULONG *timeouts); +UINT _tx_queue_prioritize(TX_QUEUE *queue_ptr); +UINT _tx_queue_receive(TX_QUEUE *queue_ptr, VOID *destination_ptr, ULONG wait_option); +UINT _tx_queue_send(TX_QUEUE *queue_ptr, VOID *source_ptr, ULONG wait_option); +UINT _tx_queue_send_notify(TX_QUEUE *queue_ptr, VOID (*queue_send_notify)(TX_QUEUE *notify_queue_ptr)); +UINT _tx_queue_front_send(TX_QUEUE *queue_ptr, VOID *source_ptr, ULONG wait_option); + + +/* Define error checking shells for API services. These are only referenced by the + application. */ + +UINT _txe_queue_create(TX_QUEUE *queue_ptr, CHAR *name_ptr, UINT message_size, + VOID *queue_start, ULONG queue_size, UINT queue_control_block_size); +UINT _txe_queue_delete(TX_QUEUE *queue_ptr); +UINT _txe_queue_flush(TX_QUEUE *queue_ptr); +UINT _txe_queue_info_get(TX_QUEUE *queue_ptr, CHAR **name, ULONG *enqueued, ULONG *available_storage, + TX_THREAD **first_suspended, ULONG *suspended_count, TX_QUEUE **next_queue); +UINT _txe_queue_prioritize(TX_QUEUE *queue_ptr); +UINT _txe_queue_receive(TX_QUEUE *queue_ptr, VOID *destination_ptr, ULONG wait_option); +UINT _txe_queue_send(TX_QUEUE *queue_ptr, VOID *source_ptr, ULONG wait_option); +UINT _txe_queue_send_notify(TX_QUEUE *queue_ptr, VOID (*queue_send_notify)(TX_QUEUE *notify_queue_ptr)); +UINT _txe_queue_front_send(TX_QUEUE *queue_ptr, VOID *source_ptr, ULONG wait_option); + + +/* Define semaphore management function prototypes. */ + +UINT _tx_semaphore_ceiling_put(TX_SEMAPHORE *semaphore_ptr, ULONG ceiling); +UINT _tx_semaphore_create(TX_SEMAPHORE *semaphore_ptr, CHAR *name_ptr, ULONG initial_count); +UINT _tx_semaphore_delete(TX_SEMAPHORE *semaphore_ptr); +UINT _tx_semaphore_get(TX_SEMAPHORE *semaphore_ptr, ULONG wait_option); +UINT _tx_semaphore_info_get(TX_SEMAPHORE *semaphore_ptr, CHAR **name, ULONG *current_value, + TX_THREAD **first_suspended, ULONG *suspended_count, + TX_SEMAPHORE **next_semaphore); +UINT _tx_semaphore_performance_info_get(TX_SEMAPHORE *semaphore_ptr, ULONG *puts, ULONG *gets, + ULONG *suspensions, ULONG *timeouts); +UINT _tx_semaphore_performance_system_info_get(ULONG *puts, ULONG *gets, ULONG *suspensions, ULONG *timeouts); +UINT _tx_semaphore_prioritize(TX_SEMAPHORE *semaphore_ptr); +UINT _tx_semaphore_put(TX_SEMAPHORE *semaphore_ptr); +UINT _tx_semaphore_put_notify(TX_SEMAPHORE *semaphore_ptr, VOID (*semaphore_put_notify)(TX_SEMAPHORE *notify_semaphore_ptr)); + + +/* Define error checking shells for API services. These are only referenced by the + application. */ + +UINT _txe_semaphore_ceiling_put(TX_SEMAPHORE *semaphore_ptr, ULONG ceiling); +UINT _txe_semaphore_create(TX_SEMAPHORE *semaphore_ptr, CHAR *name_ptr, ULONG initial_count, UINT semaphore_control_block_size); +UINT _txe_semaphore_delete(TX_SEMAPHORE *semaphore_ptr); +UINT _txe_semaphore_get(TX_SEMAPHORE *semaphore_ptr, ULONG wait_option); +UINT _txe_semaphore_info_get(TX_SEMAPHORE *semaphore_ptr, CHAR **name, ULONG *current_value, + TX_THREAD **first_suspended, ULONG *suspended_count, + TX_SEMAPHORE **next_semaphore); +UINT _txe_semaphore_prioritize(TX_SEMAPHORE *semaphore_ptr); +UINT _txe_semaphore_put(TX_SEMAPHORE *semaphore_ptr); +UINT _txe_semaphore_put_notify(TX_SEMAPHORE *semaphore_ptr, VOID (*semaphore_put_notify)(TX_SEMAPHORE *notify_semaphore_ptr)); + + +/* Define thread control function prototypes. */ + +VOID _tx_thread_context_save(VOID); +VOID _tx_thread_context_restore(VOID); +UINT _tx_thread_create(TX_THREAD *thread_ptr, CHAR *name_ptr, + VOID (*entry_function)(ULONG entry_input), ULONG entry_input, + VOID *stack_start, ULONG stack_size, + UINT priority, UINT preempt_threshold, + ULONG time_slice, UINT auto_start); +UINT _tx_thread_delete(TX_THREAD *thread_ptr); +UINT _tx_thread_entry_exit_notify(TX_THREAD *thread_ptr, VOID (*thread_entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT type)); +TX_THREAD *_tx_thread_identify(VOID); +UINT _tx_thread_info_get(TX_THREAD *thread_ptr, CHAR **name, UINT *state, ULONG *run_count, + UINT *priority, UINT *preemption_threshold, ULONG *time_slice, + TX_THREAD **next_thread, TX_THREAD **next_suspended_thread); +UINT _tx_thread_interrupt_control(UINT new_posture); +UINT _tx_thread_performance_info_get(TX_THREAD *thread_ptr, ULONG *resumptions, ULONG *suspensions, + ULONG *solicited_preemptions, ULONG *interrupt_preemptions, ULONG *priority_inversions, + ULONG *time_slices, ULONG *relinquishes, ULONG *timeouts, ULONG *wait_aborts, TX_THREAD **last_preempted_by); +UINT _tx_thread_performance_system_info_get(ULONG *resumptions, ULONG *suspensions, + ULONG *solicited_preemptions, ULONG *interrupt_preemptions, ULONG *priority_inversions, + ULONG *time_slices, ULONG *relinquishes, ULONG *timeouts, ULONG *wait_aborts, + ULONG *non_idle_returns, ULONG *idle_returns); +UINT _tx_thread_preemption_change(TX_THREAD *thread_ptr, UINT new_threshold, + UINT *old_threshold); +UINT _tx_thread_priority_change(TX_THREAD *thread_ptr, UINT new_priority, + UINT *old_priority); +VOID _tx_thread_relinquish(VOID); +UINT _tx_thread_reset(TX_THREAD *thread_ptr); +UINT _tx_thread_resume(TX_THREAD *thread_ptr); +UINT _tx_thread_sleep(ULONG timer_ticks); +UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr)); +UINT _tx_thread_suspend(TX_THREAD *thread_ptr); +UINT _tx_thread_terminate(TX_THREAD *thread_ptr); +UINT _tx_thread_time_slice_change(TX_THREAD *thread_ptr, ULONG new_time_slice, ULONG *old_time_slice); +UINT _tx_thread_wait_abort(TX_THREAD *thread_ptr); + + +/* Define error checking shells for API services. These are only referenced by the + application. */ + +UINT _txe_thread_create(TX_THREAD *thread_ptr, CHAR *name_ptr, + VOID (*entry_function)(ULONG entry_input), ULONG entry_input, + VOID *stack_start, ULONG stack_size, + UINT priority, UINT preempt_threshold, + ULONG time_slice, UINT auto_start, UINT thread_control_block_size); +UINT _txe_thread_delete(TX_THREAD *thread_ptr); +UINT _txe_thread_entry_exit_notify(TX_THREAD *thread_ptr, VOID (*thread_entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT type)); +UINT _txe_thread_info_get(TX_THREAD *thread_ptr, CHAR **name, UINT *state, ULONG *run_count, + UINT *priority, UINT *preemption_threshold, ULONG *time_slice, + TX_THREAD **next_thread, TX_THREAD **next_suspended_thread); +UINT _txe_thread_preemption_change(TX_THREAD *thread_ptr, UINT new_threshold, + UINT *old_threshold); +UINT _txe_thread_priority_change(TX_THREAD *thread_ptr, UINT new_priority, + UINT *old_priority); +VOID _txe_thread_relinquish(VOID); +UINT _txe_thread_reset(TX_THREAD *thread_ptr); +UINT _txe_thread_resume(TX_THREAD *thread_ptr); +UINT _txe_thread_suspend(TX_THREAD *thread_ptr); +UINT _txe_thread_terminate(TX_THREAD *thread_ptr); +UINT _txe_thread_time_slice_change(TX_THREAD *thread_ptr, ULONG new_time_slice, ULONG *old_time_slice); +UINT _txe_thread_wait_abort(TX_THREAD *thread_ptr); + + +/* Define timer management function prototypes. */ + +UINT _tx_timer_activate(TX_TIMER *timer_ptr); +UINT _tx_timer_change(TX_TIMER *timer_ptr, ULONG initial_ticks, ULONG reschedule_ticks); +UINT _tx_timer_create(TX_TIMER *timer_ptr, CHAR *name_ptr, + VOID (*expiration_function)(ULONG input), ULONG expiration_input, + ULONG initial_ticks, ULONG reschedule_ticks, UINT auto_activate); +UINT _tx_timer_deactivate(TX_TIMER *timer_ptr); +UINT _tx_timer_delete(TX_TIMER *timer_ptr); +UINT _tx_timer_info_get(TX_TIMER *timer_ptr, CHAR **name, UINT *active, ULONG *remaining_ticks, + ULONG *reschedule_ticks, TX_TIMER **next_timer); +UINT _tx_timer_performance_info_get(TX_TIMER *timer_ptr, ULONG *activates, ULONG *reactivates, + ULONG *deactivates, ULONG *expirations, ULONG *expiration_adjusts); +UINT _tx_timer_performance_system_info_get(ULONG *activates, ULONG *reactivates, + ULONG *deactivates, ULONG *expirations, ULONG *expiration_adjusts); + +ULONG _tx_time_get(VOID); +VOID _tx_time_set(ULONG new_time); + + +/* Define error checking shells for API services. These are only referenced by the + application. */ + +UINT _txe_timer_activate(TX_TIMER *timer_ptr); +UINT _txe_timer_change(TX_TIMER *timer_ptr, ULONG initial_ticks, ULONG reschedule_ticks); +UINT _txe_timer_create(TX_TIMER *timer_ptr, CHAR *name_ptr, + VOID (*expiration_function)(ULONG input), ULONG expiration_input, + ULONG initial_ticks, ULONG reschedule_ticks, UINT auto_activate, UINT timer_control_block_size); +UINT _txe_timer_deactivate(TX_TIMER *timer_ptr); +UINT _txe_timer_delete(TX_TIMER *timer_ptr); +UINT _txe_timer_info_get(TX_TIMER *timer_ptr, CHAR **name, UINT *active, ULONG *remaining_ticks, + ULONG *reschedule_ticks, TX_TIMER **next_timer); + + +/* Define trace API function prototypes. */ + +UINT _tx_trace_enable(VOID *trace_buffer_start, ULONG trace_buffer_size, ULONG registry_entries); +UINT _tx_trace_event_filter(ULONG event_filter_bits); +UINT _tx_trace_event_unfilter(ULONG event_unfilter_bits); +UINT _tx_trace_disable(VOID); +VOID _tx_trace_isr_enter_insert(ULONG isr_id); +VOID _tx_trace_isr_exit_insert(ULONG isr_id); +UINT _tx_trace_buffer_full_notify(VOID (*full_buffer_callback)(VOID *buffer)); +UINT _tx_trace_user_event_insert(ULONG event_id, ULONG info_field_1, ULONG info_field_2, ULONG info_field_3, ULONG info_field_4); +UINT _tx_trace_interrupt_control(UINT new_posture); + + + +/* Add a default macro that can be re-defined in tx_port.h to add default processing when a thread starts. Common usage + would be for enabling floating point for a thread by default, however, the additional processing could be anything + defined in tx_port.h. */ + +#ifndef TX_THREAD_STARTED_EXTENSION +#define TX_THREAD_STARTED_EXTENSION(thread_ptr) +#endif + + +/* Add a default macro that can be re-defined in tx_port.h to add processing to the thread stack analyze function. + By default, this is simply defined as whitespace. */ + +#ifndef TX_THREAD_STACK_ANALYZE_EXTENSION +#define TX_THREAD_STACK_ANALYZE_EXTENSION +#endif + + +/* Add a default macro that can be re-defined in tx_port.h to add processing to the initialize kernel enter function. + By default, this is simply defined as whitespace. */ + +#ifndef TX_INITIALIZE_KERNEL_ENTER_EXTENSION +#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION +#endif + + +/* Check for MISRA compliance requirements. */ + +#ifdef TX_MISRA_ENABLE + +/* Define MISRA-specific routines. */ + +VOID _tx_misra_memset(VOID *ptr, UINT value, UINT size); +UCHAR *_tx_misra_uchar_pointer_add(UCHAR *ptr, ULONG amount); +UCHAR *_tx_misra_uchar_pointer_sub(UCHAR *ptr, ULONG amount); +ULONG _tx_misra_uchar_pointer_dif(UCHAR *ptr1, UCHAR *ptr2); +ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); +ULONG *_tx_misra_ulong_pointer_add(ULONG *ptr, ULONG amount); +ULONG *_tx_misra_ulong_pointer_sub(ULONG *ptr, ULONG amount); +ULONG _tx_misra_ulong_pointer_dif(ULONG *ptr1, ULONG *ptr2); +VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); +VOID _tx_misra_message_copy(ULONG **source, ULONG **destination, UINT size); +ULONG _tx_misra_timer_pointer_dif(TX_TIMER_INTERNAL **ptr1, TX_TIMER_INTERNAL **ptr2); +TX_TIMER_INTERNAL **_tx_misra_timer_pointer_add(TX_TIMER_INTERNAL **ptr1, ULONG size); +VOID _tx_misra_user_timer_pointer_get(TX_TIMER_INTERNAL *internal_timer, TX_TIMER **user_timer); +VOID _tx_misra_thread_stack_check(TX_THREAD *thread_ptr, VOID **highest_stack); +VOID _tx_misra_trace_event_insert(ULONG event_id, VOID *info_field_1, ULONG info_field_2, ULONG info_field_3, ULONG info_field_4, ULONG filter, ULONG time_stamp); +UINT _tx_misra_always_true(void); +UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **pointer); +UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); +UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); +TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); +UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); +TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); +UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); +TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); +UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); +ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); +TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); +TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); +ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); +TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); +UINT _tx_misra_status_get(UINT status); +TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); +TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); +VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); +TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); +VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); +CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); +TX_THREAD *_tx_misra_void_to_thread_pointer_convert(VOID *pointer); +UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); +VOID _tx_misra_event_flags_group_not_used(TX_EVENT_FLAGS_GROUP *group_ptr); +VOID _tx_misra_event_flags_set_notify_not_used(VOID (*events_set_notify)(TX_EVENT_FLAGS_GROUP *notify_group_ptr)); +VOID _tx_misra_queue_not_used(TX_QUEUE *queue_ptr); +VOID _tx_misra_queue_send_notify_not_used(VOID (*queue_send_notify)(TX_QUEUE *notify_queue_ptr)); +VOID _tx_misra_semaphore_not_used(TX_SEMAPHORE *semaphore_ptr); +VOID _tx_misra_semaphore_put_notify_not_used(VOID (*semaphore_put_notify)(TX_SEMAPHORE *notify_semaphore_ptr)); +VOID _tx_misra_thread_not_used(TX_THREAD *thread_ptr); +VOID _tx_misra_thread_entry_exit_notify_not_used(VOID (*thread_entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT id)); + +#define TX_MEMSET(a,b,c) _tx_misra_memset((a), (UINT) (b), (UINT) (c)) +#define TX_UCHAR_POINTER_ADD(a,b) _tx_misra_uchar_pointer_add((UCHAR *) (a), (ULONG) (b)) +#define TX_UCHAR_POINTER_SUB(a,b) _tx_misra_uchar_pointer_sub((UCHAR *) (a), (ULONG) (b)) +#define TX_UCHAR_POINTER_DIF(a,b) _tx_misra_uchar_pointer_dif((UCHAR *) (a), (UCHAR *) (b)) +#define TX_ULONG_POINTER_ADD(a,b) _tx_misra_ulong_pointer_add((ULONG *) (a), (ULONG) (b)) +#define TX_ULONG_POINTER_SUB(a,b) _tx_misra_ulong_pointer_sub((ULONG *) (a), (ULONG) (b)) +#define TX_ULONG_POINTER_DIF(a,b) _tx_misra_ulong_pointer_dif((ULONG *) (a), (ULONG *) (b)) +#define TX_POINTER_TO_ULONG_CONVERT(a) _tx_misra_pointer_to_ulong_convert((VOID *) (a)) +#define TX_ULONG_TO_POINTER_CONVERT(a) _tx_misra_ulong_to_pointer_convert((ULONG) (a)) +#define TX_QUEUE_MESSAGE_COPY(s,d,z) _tx_misra_message_copy(&(s), &(d), (z)); +#define TX_TIMER_POINTER_DIF(a,b) _tx_misra_timer_pointer_dif((TX_TIMER_INTERNAL **) (a), (TX_TIMER_INTERNAL **) (b)) +#define TX_TIMER_POINTER_ADD(a,b) _tx_misra_timer_pointer_add((TX_TIMER_INTERNAL **) (a), (ULONG) (b)) +#define TX_USER_TIMER_POINTER_GET(a,b) _tx_misra_user_timer_pointer_get((TX_TIMER_INTERNAL *) (a), (TX_TIMER **) &(b)); +#define TX_THREAD_STACK_CHECK(a) _tx_misra_thread_stack_check((a), &((a)->tx_thread_stack_highest_ptr)); +#ifdef TX_ENABLE_EVENT_TRACE +#define TX_TRACE_IN_LINE_INSERT(i,a,b,c,d,e) _tx_misra_trace_event_insert((ULONG) (i), (VOID *) (a), (ULONG) (b), (ULONG) (c), (ULONG) (d), (ULONG) (e), ((ULONG) TX_TRACE_TIME_SOURCE)); +#endif +#define TX_LOOP_FOREVER (_tx_misra_always_true() == TX_TRUE) +#define TX_INDIRECT_VOID_TO_UCHAR_POINTER_CONVERT(a) _tx_misra_indirect_void_to_uchar_pointer_convert((a)) +#define TX_UCHAR_TO_INDIRECT_UCHAR_POINTER_CONVERT(a) _tx_misra_uchar_to_indirect_uchar_pointer_convert((a)) +#define TX_BLOCK_POOL_TO_UCHAR_POINTER_CONVERT(a) _tx_misra_block_pool_to_uchar_pointer_convert((a)) +#define TX_VOID_TO_BLOCK_POOL_POINTER_CONVERT(a) _tx_misra_void_to_block_pool_pointer_convert((a)) +#define TX_VOID_TO_UCHAR_POINTER_CONVERT(a) _tx_misra_void_to_uchar_pointer_convert((a)) +#define TX_UCHAR_TO_BLOCK_POOL_POINTER_CONVERT(a) _tx_misra_uchar_to_block_pool_pointer_convert((a)) +#define TX_VOID_TO_INDIRECT_UCHAR_POINTER_CONVERT(a) _tx_misra_void_to_indirect_uchar_pointer_convert((a)) +#define TX_VOID_TO_BYTE_POOL_POINTER_CONVERT(a) _tx_misra_void_to_byte_pool_pointer_convert((a)) +#define TX_BYTE_POOL_TO_UCHAR_POINTER_CONVERT(a) _tx_misra_byte_pool_to_uchar_pointer_convert((a)) +#define TX_UCHAR_TO_ALIGN_TYPE_POINTER_CONVERT(a) _tx_misra_uchar_to_align_type_pointer_convert((a)) +#define TX_UCHAR_TO_INDIRECT_BYTE_POOL_POINTER(a) _tx_misra_uchar_to_indirect_byte_pool_pointer_convert((a)) +#define TX_VOID_TO_EVENT_FLAGS_POINTER_CONVERT(a) _tx_misra_void_to_event_flags_pointer_convert((a)) +#define TX_VOID_TO_ULONG_POINTER_CONVERT(a) _tx_misra_void_to_ulong_pointer_convert((a)) +#define TX_VOID_TO_MUTEX_POINTER_CONVERT(a) _tx_misra_void_to_mutex_pointer_convert((a)) +#define TX_MUTEX_PRIORITIZE_MISRA_EXTENSION(a) _tx_misra_status_get((a)) +#define TX_VOID_TO_QUEUE_POINTER_CONVERT(a) _tx_misra_void_to_queue_pointer_convert((a)) +#define TX_VOID_TO_SEMAPHORE_POINTER_CONVERT(a) _tx_misra_void_to_semaphore_pointer_convert((a)) +#define TX_UCHAR_TO_VOID_POINTER_CONVERT(a) _tx_misra_uchar_to_void_pointer_convert((a)) +#define TX_ULONG_TO_THREAD_POINTER_CONVERT(a) _tx_misra_ulong_to_thread_pointer_convert((a)) +#define TX_TIMER_INDIRECT_TO_VOID_POINTER_CONVERT(a) _tx_misra_timer_indirect_to_void_pointer_convert((a)) +#ifndef TX_TIMER_INITIALIZE_EXTENSION +#define TX_TIMER_INITIALIZE_EXTENSION(a) status = _tx_misra_status_get((a)); +#endif +#define TX_CONST_CHAR_TO_CHAR_POINTER_CONVERT(a) _tx_misra_const_char_to_char_pointer_convert((a)) +#define TX_VOID_TO_THREAD_POINTER_CONVERT(a) _tx_misra_void_to_thread_pointer_convert((a)) +#define TX_CHAR_TO_UCHAR_POINTER_CONVERT(a) _tx_misra_char_to_uchar_pointer_convert((a)) +#define TX_EVENT_FLAGS_GROUP_NOT_USED(a) _tx_misra_event_flags_group_not_used((a)) +#define TX_EVENT_FLAGS_SET_NOTIFY_NOT_USED(a) _tx_misra_event_flags_set_notify_not_used((a)) +#define TX_QUEUE_NOT_USED(a) _tx_misra_queue_not_used((a)) +#define TX_QUEUE_SEND_NOTIFY_NOT_USED(a) _tx_misra_queue_send_notify_not_used((a)) +#define TX_SEMAPHORE_NOT_USED(a) _tx_misra_semaphore_not_used((a)) +#define TX_SEMAPHORE_PUT_NOTIFY_NOT_USED(a) _tx_misra_semaphore_put_notify_not_used((a)) +#define TX_THREAD_NOT_USED(a) _tx_misra_thread_not_used((a)) +#define TX_THREAD_ENTRY_EXIT_NOTIFY_NOT_USED(a) _tx_misra_thread_entry_exit_notify_not_used((a)) + +#else + +/* Define the TX_MEMSET macro to the standard library function, if not already defined. */ + +#ifndef TX_MEMSET +#define TX_MEMSET(a,b,c) memset((a),(b),(c)) +#endif + +#define TX_UCHAR_POINTER_ADD(a,b) (((UCHAR *) (a)) + ((UINT) (b))) +#define TX_UCHAR_POINTER_SUB(a,b) (((UCHAR *) (a)) - ((UINT) (b))) +#define TX_UCHAR_POINTER_DIF(a,b) ((ULONG)(((UCHAR *) (a)) - ((UCHAR *) (b)))) +#define TX_ULONG_POINTER_ADD(a,b) (((ULONG *) (a)) + ((UINT) (b))) +#define TX_ULONG_POINTER_SUB(a,b) (((ULONG *) (a)) - ((UINT) (b))) +#define TX_ULONG_POINTER_DIF(a,b) ((ULONG)(((ULONG *) (a)) - ((ULONG *) (b)))) +#define TX_POINTER_TO_ULONG_CONVERT(a) ((ULONG) ((VOID *) (a))) +#define TX_ULONG_TO_POINTER_CONVERT(a) ((VOID *) ((ULONG) (a))) +#define TX_TIMER_POINTER_DIF(a,b) ((ULONG)(((TX_TIMER_INTERNAL **) (a)) - ((TX_TIMER_INTERNAL **) (b)))) +#define TX_TIMER_POINTER_ADD(a,b) (((TX_TIMER_INTERNAL **) (a)) + ((ULONG) (b))) +#define TX_USER_TIMER_POINTER_GET(a,b) { \ + UCHAR *working_ptr; \ + working_ptr = (UCHAR *) (a); \ + (b) = (TX_TIMER *) working_ptr; \ + working_ptr = working_ptr - (((UCHAR *) &(b) -> tx_timer_internal) - ((UCHAR *) &(b) -> tx_timer_id)); \ + (b) = (TX_TIMER *) working_ptr; \ + } +#define TX_LOOP_FOREVER ((UINT) 1) +#define TX_INDIRECT_VOID_TO_UCHAR_POINTER_CONVERT(a) ((UCHAR **) ((VOID *) (a))) +#define TX_UCHAR_TO_INDIRECT_UCHAR_POINTER_CONVERT(a) ((UCHAR **) ((VOID *) (a))) +#define TX_BLOCK_POOL_TO_UCHAR_POINTER_CONVERT(a) ((UCHAR *) ((VOID *) (a))) +#define TX_VOID_TO_BLOCK_POOL_POINTER_CONVERT(a) ((TX_BLOCK_POOL *) ((VOID *) (a))) +#define TX_VOID_TO_UCHAR_POINTER_CONVERT(a) ((UCHAR *) ((VOID *) (a))) +#define TX_UCHAR_TO_BLOCK_POOL_POINTER_CONVERT(a) ((TX_BLOCK_POOL *) ((VOID *) (a))) +#define TX_VOID_TO_INDIRECT_UCHAR_POINTER_CONVERT(a) ((UCHAR **) ((VOID *) (a))) +#define TX_VOID_TO_BYTE_POOL_POINTER_CONVERT(a) ((TX_BYTE_POOL *) ((VOID *) (a))) +#define TX_BYTE_POOL_TO_UCHAR_POINTER_CONVERT(a) ((UCHAR *) ((VOID *) (a))) +#ifndef TX_UCHAR_TO_ALIGN_TYPE_POINTER_CONVERT +#define TX_UCHAR_TO_ALIGN_TYPE_POINTER_CONVERT(a) ((ALIGN_TYPE *) ((VOID *) (a))) +#endif +#define TX_UCHAR_TO_INDIRECT_BYTE_POOL_POINTER(a) ((TX_BYTE_POOL **) ((VOID *) (a))) +#define TX_VOID_TO_EVENT_FLAGS_POINTER_CONVERT(a) ((TX_EVENT_FLAGS_GROUP *) ((VOID *) (a))) +#define TX_VOID_TO_ULONG_POINTER_CONVERT(a) ((ULONG *) ((VOID *) (a))) +#define TX_VOID_TO_MUTEX_POINTER_CONVERT(a) ((TX_MUTEX *) ((VOID *) (a))) +#define TX_VOID_TO_QUEUE_POINTER_CONVERT(a) ((TX_QUEUE *) ((VOID *) (a))) +#define TX_VOID_TO_SEMAPHORE_POINTER_CONVERT(a) ((TX_SEMAPHORE *) ((VOID *) (a))) +#define TX_UCHAR_TO_VOID_POINTER_CONVERT(a) ((VOID *) (a)) +#define TX_ULONG_TO_THREAD_POINTER_CONVERT(a) ((TX_THREAD *) ((VOID *) (a))) +#ifndef TX_TIMER_INDIRECT_TO_VOID_POINTER_CONVERT +#define TX_TIMER_INDIRECT_TO_VOID_POINTER_CONVERT(a) ((VOID *) (a)) +#endif +#ifndef TX_TIMER_INITIALIZE_EXTENSION +#define TX_TIMER_INITIALIZE_EXTENSION(a) +#endif +#define TX_CONST_CHAR_TO_CHAR_POINTER_CONVERT(a) ((CHAR *) ((VOID *) (a))) +#define TX_VOID_TO_THREAD_POINTER_CONVERT(a) ((TX_THREAD *) ((VOID *) (a))) +#define TX_CHAR_TO_UCHAR_POINTER_CONVERT(a) ((UCHAR *) ((VOID *) (a))) +#ifndef TX_EVENT_FLAGS_GROUP_NOT_USED +#define TX_EVENT_FLAGS_GROUP_NOT_USED(a) ((void)(a)) +#endif +#ifndef TX_EVENT_FLAGS_SET_NOTIFY_NOT_USED +#define TX_EVENT_FLAGS_SET_NOTIFY_NOT_USED(a) ((void)(a)) +#endif +#ifndef TX_QUEUE_NOT_USED +#define TX_QUEUE_NOT_USED(a) ((void)(a)) +#endif +#ifndef TX_QUEUE_SEND_NOTIFY_NOT_USED +#define TX_QUEUE_SEND_NOTIFY_NOT_USED(a) ((void)(a)) +#endif +#ifndef TX_SEMAPHORE_NOT_USED +#define TX_SEMAPHORE_NOT_USED(a) ((void)(a)) +#endif +#ifndef TX_SEMAPHORE_PUT_NOTIFY_NOT_USED +#define TX_SEMAPHORE_PUT_NOTIFY_NOT_USED(a) ((void)(a)) +#endif +#ifndef TX_THREAD_NOT_USED +#define TX_THREAD_NOT_USED(a) ((void)(a)) +#endif +#ifndef TX_THREAD_ENTRY_EXIT_NOTIFY_NOT_USED +#define TX_THREAD_ENTRY_EXIT_NOTIFY_NOT_USED(a) ((void)(a)) +#endif + +#endif + + +/* Determine if there is an tx_api.h extension file to include. */ + +#ifdef TX_THREAD_API_EXTENSION + +/* Yes, bring in the tx_api.h extension file. */ +#include "tx_api_extension.h" + +#endif + + +/* Define safety critical configuration and exception handling. */ + +#ifdef TX_SAFETY_CRITICAL + +/* Ensure the maximum number of priorities is defined in safety critical mode. */ +#ifndef TX_MAX_PRIORITIES +#error "tx_port.h: TX_MAX_PRIORITIES not defined." +#endif + +/* Ensure the maximum number of priorities is a multiple of 32. */ +#if (TX_MAX_PRIORITIES %32) != 0 +#error "tx_port.h: TX_MAX_PRIORITIES must be a multiple of 32." +#endif + +/* Ensure error checking is enabled. */ +#ifdef TX_DISABLE_ERROR_CHECKING +#error "TX_DISABLE_ERROR_CHECKING must not be defined." +#endif + +/* Ensure timer ISR processing is not defined. */ +#ifdef TX_TIMER_PROCESS_IN_ISR +#error "TX_TIMER_PROCESS_IN_ISR must not be defined." +#endif + +/* Ensure timer reactivation in-line is not defined. */ +#ifdef TX_REACTIVATE_INLINE +#error "TX_REACTIVATE_INLINE must not be defined." +#endif + +/* Ensure disable stack filling is not defined. */ +#ifdef TX_DISABLE_STACK_FILLING +#error "TX_DISABLE_STACK_FILLING must not be defined." +#endif + +/* Ensure enable stack checking is not defined. */ +#ifdef TX_ENABLE_STACK_CHECKING +#error "TX_ENABLE_STACK_CHECKING must not be defined." +#endif + +/* Ensure disable preemption-threshold is not defined. */ +#ifdef TX_DISABLE_PREEMPTION_THRESHOLD +#error "TX_DISABLE_PREEMPTION_THRESHOLD must not be defined." +#endif + +/* Ensure disable redundant clearing is not defined. */ +#ifdef TX_DISABLE_REDUNDANT_CLEARING +#error "TX_DISABLE_REDUNDANT_CLEARING must not be defined." +#endif + +/* Ensure no timer is not defined. */ +#ifdef TX_NO_TIMER +#error "TX_NO_TIMER must not be defined." +#endif + +/* Ensure disable notify callbacks is not defined. */ +#ifdef TX_DISABLE_NOTIFY_CALLBACKS +#error "TX_DISABLE_NOTIFY_CALLBACKS must not be defined." +#endif + +/* Ensure in-line thread suspend/resume is not defined. */ +#ifdef TX_INLINE_THREAD_RESUME_SUSPEND +#error "TX_INLINE_THREAD_RESUME_SUSPEND must not be defined." +#endif + +/* Ensure not interruptable is not defined. */ +#ifdef TX_NOT_INTERRUPTABLE +#error "TX_NOT_INTERRUPTABLE must not be defined." +#endif + +/* Ensure event trace enable is not defined. */ +#ifdef TX_ENABLE_EVENT_TRACE +#error "TX_ENABLE_EVENT_TRACE must not be defined." +#endif + +/* Ensure block pool performance info enable is not defined. */ +#ifdef TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO +#error "TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO must not be defined." +#endif + +/* Ensure byte pool performance info enable is not defined. */ +#ifdef TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO +#error "TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO must not be defined." +#endif + +/* Ensure event flag performance info enable is not defined. */ +#ifdef TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO +#error "TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO must not be defined." +#endif + +/* Ensure mutex performance info enable is not defined. */ +#ifdef TX_MUTEX_ENABLE_PERFORMANCE_INFO +#error "TX_MUTEX_ENABLE_PERFORMANCE_INFO must not be defined." +#endif + +/* Ensure queue performance info enable is not defined. */ +#ifdef TX_QUEUE_ENABLE_PERFORMANCE_INFO +#error "TX_QUEUE_ENABLE_PERFORMANCE_INFO must not be defined." +#endif + +/* Ensure semaphore performance info enable is not defined. */ +#ifdef TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO +#error "TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO must not be defined." +#endif + +/* Ensure thread performance info enable is not defined. */ +#ifdef TX_THREAD_ENABLE_PERFORMANCE_INFO +#error "TX_THREAD_ENABLE_PERFORMANCE_INFO must not be defined." +#endif + +/* Ensure timer performance info enable is not defined. */ +#ifdef TX_TIMER_ENABLE_PERFORMANCE_INFO +#error "TX_TIMER_ENABLE_PERFORMANCE_INFO must not be defined." +#endif + + +/* Now define the safety critical exception handler. */ + +VOID _tx_safety_critical_exception_handler(CHAR *file_name, INT line_number, UINT status); + + +#ifndef TX_SAFETY_CRITICAL_EXCEPTION +#define TX_SAFETY_CRITICAL_EXCEPTION(a, b, c) _tx_safety_critical_exception_handler(a, b, c); +#endif + +#ifndef TX_SAFETY_CRITICAL_EXCEPTION_HANDLER +#define TX_SAFETY_CRITICAL_EXCEPTION_HANDLER VOID _tx_safety_critical_exception_handler(CHAR *file_name, INT line_number, UINT status) \ + { \ + while(1) \ + { \ + } \ + } +#endif +#endif + + +#ifdef TX_ENABLE_MULTI_ERROR_CHECKING + +/* Define ThreadX API MULTI run-time error checking function. */ +void __ghs_rnerr(char *errMsg, int stackLevels, int stackTraceDisplay, void *hexVal); + +#endif + +/* Bring in the event logging constants and prototypes. Note that + TX_ENABLE_EVENT_LOGGING must be defined when building the ThreadX + library components in order to enable event logging. */ + +#ifdef TX_ENABLE_EVENT_LOGGING +#include "tx_el.h" +#else +#ifndef TX_SOURCE_CODE +#ifndef TX_MISRA_ENABLE +#define _tx_el_user_event_insert(a,b,c,d,e) +#endif +#endif +#define TX_EL_INITIALIZE +#define TX_EL_THREAD_REGISTER(a) +#define TX_EL_THREAD_UNREGISTER(a) +#define TX_EL_THREAD_STATUS_CHANGE_INSERT(a, b) +#define TX_EL_BYTE_ALLOCATE_INSERT +#define TX_EL_BYTE_POOL_CREATE_INSERT +#define TX_EL_BYTE_POOL_DELETE_INSERT +#define TX_EL_BYTE_RELEASE_INSERT +#define TX_EL_BLOCK_ALLOCATE_INSERT +#define TX_EL_BLOCK_POOL_CREATE_INSERT +#define TX_EL_BLOCK_POOL_DELETE_INSERT +#define TX_EL_BLOCK_RELEASE_INSERT +#define TX_EL_EVENT_FLAGS_CREATE_INSERT +#define TX_EL_EVENT_FLAGS_DELETE_INSERT +#define TX_EL_EVENT_FLAGS_GET_INSERT +#define TX_EL_EVENT_FLAGS_SET_INSERT +#define TX_EL_INTERRUPT_CONTROL_INSERT +#define TX_EL_QUEUE_CREATE_INSERT +#define TX_EL_QUEUE_DELETE_INSERT +#define TX_EL_QUEUE_FLUSH_INSERT +#define TX_EL_QUEUE_RECEIVE_INSERT +#define TX_EL_QUEUE_SEND_INSERT +#define TX_EL_SEMAPHORE_CREATE_INSERT +#define TX_EL_SEMAPHORE_DELETE_INSERT +#define TX_EL_SEMAPHORE_GET_INSERT +#define TX_EL_SEMAPHORE_PUT_INSERT +#define TX_EL_THREAD_CREATE_INSERT +#define TX_EL_THREAD_DELETE_INSERT +#define TX_EL_THREAD_IDENTIFY_INSERT +#define TX_EL_THREAD_PREEMPTION_CHANGE_INSERT +#define TX_EL_THREAD_PRIORITY_CHANGE_INSERT +#define TX_EL_THREAD_RELINQUISH_INSERT +#define TX_EL_THREAD_RESUME_INSERT +#define TX_EL_THREAD_SLEEP_INSERT +#define TX_EL_THREAD_SUSPEND_INSERT +#define TX_EL_THREAD_TERMINATE_INSERT +#define TX_EL_THREAD_TIME_SLICE_CHANGE_INSERT +#define TX_EL_TIME_GET_INSERT +#define TX_EL_TIME_SET_INSERT +#define TX_EL_TIMER_ACTIVATE_INSERT +#define TX_EL_TIMER_CHANGE_INSERT +#define TX_EL_TIMER_CREATE_INSERT +#define TX_EL_TIMER_DEACTIVATE_INSERT +#define TX_EL_TIMER_DELETE_INSERT +#define TX_EL_BLOCK_POOL_INFO_GET_INSERT +#define TX_EL_BLOCK_POOL_PRIORITIZE_INSERT +#define TX_EL_BYTE_POOL_INFO_GET_INSERT +#define TX_EL_BYTE_POOL_PRIORITIZE_INSERT +#define TX_EL_EVENT_FLAGS_INFO_GET_INSERT +#define TX_EL_MUTEX_CREATE_INSERT +#define TX_EL_MUTEX_DELETE_INSERT +#define TX_EL_MUTEX_GET_INSERT +#define TX_EL_MUTEX_INFO_GET_INSERT +#define TX_EL_MUTEX_PRIORITIZE_INSERT +#define TX_EL_MUTEX_PUT_INSERT +#define TX_EL_QUEUE_INFO_GET_INSERT +#define TX_EL_QUEUE_FRONT_SEND_INSERT +#define TX_EL_QUEUE_PRIORITIZE_INSERT +#define TX_EL_SEMAPHORE_INFO_GET_INSERT +#define TX_EL_SEMAPHORE_PRIORITIZE_INSERT +#define TX_EL_THREAD_INFO_GET_INSERT +#define TX_EL_THREAD_WAIT_ABORT_INSERT +#define TX_EL_TIMER_INFO_GET_INSERT +#define TX_EL_BLOCK_POOL_PERFORMANCE_INFO_GET_INSERT +#define TX_EL_BLOCK_POOL_PERFORMANCE_SYSTEM_INFO_GET_INSERT +#define TX_EL_BYTE_POOL_PERFORMANCE_INFO_GET_INSERT +#define TX_EL_BYTE_POOL_PERFORMANCE_SYSTEM_INFO_GET_INSERT +#define TX_EL_EVENT_FLAGS_PERFORMANCE_INFO_GET_INSERT +#define TX_EL_EVENT_FLAGS__PERFORMANCE_SYSTEM_INFO_GET_INSERT +#define TX_EL_EVENT_FLAGS_SET_NOTIFY_INSERT +#define TX_EL_MUTEX_PERFORMANCE_INFO_GET_INSERT +#define TX_EL_MUTEX_PERFORMANCE_SYSTEM_INFO_GET_INSERT +#define TX_EL_QUEUE_PERFORMANCE_INFO_GET_INSERT +#define TX_EL_QUEUE_PERFORMANCE_SYSTEM_INFO_GET_INSERT +#define TX_EL_QUEUE_SEND_NOTIFY_INSERT +#define TX_EL_SEMAPHORE_CEILING_PUT_INSERT +#define TX_EL_SEMAPHORE_PERFORMANCE_INFO_GET_INSERT +#define TX_EL_SEMAPHORE_PERFORMANCE_SYSTEM_INFO_GET_INSERT +#define TX_EL_SEMAPHORE_PUT_NOTIFY_INSERT +#define TX_EL_THREAD_ENTRY_EXIT_NOTIFY_INSERT +#define TX_EL_THREAD_RESET_INSERT +#define TX_EL_THREAD_PERFORMANCE_INFO_GET_INSERT +#define TX_EL_THREAD_PERFORMANCE_SYSTEM_INFO_GET_INSERT +#define TX_EL_THREAD_STACK_ERROR_NOTIFY_INSERT +#define TX_EL_TIMER_PERFORMANCE_INFO_GET_INSERT +#define TX_EL_TIMER_PERFORMANCE_SYSTEM_INFO_GET_INSERT + +#endif + + + +/* Determine if a C++ compiler is being used. If so, complete the standard + C conditional started above. */ +#ifdef __cplusplus + } +#endif + +#endif + diff --git a/common_smp/inc/tx_block_pool.h b/common_smp/inc/tx_block_pool.h new file mode 100644 index 00000000..698a2937 --- /dev/null +++ b/common_smp/inc/tx_block_pool.h @@ -0,0 +1,146 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Block Memory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* tx_block_pool.h PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the ThreadX block memory management component, */ +/* including all data types and external references. It is assumed */ +/* that tx_api.h and tx_port.h have already been included. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_BLOCK_POOL_H +#define TX_BLOCK_POOL_H + + +/* Define block memory control specific data definitions. */ + +#define TX_BLOCK_POOL_ID ((ULONG) 0x424C4F43) + + +/* Determine if in-line component initialization is supported by the + caller. */ + +#ifdef TX_INVOKE_INLINE_INITIALIZATION + +/* Yes, in-line initialization is supported, remap the block memory pool + initialization function. */ + +#ifndef TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO +#define _tx_block_pool_initialize() \ + _tx_block_pool_created_ptr = TX_NULL; \ + _tx_block_pool_created_count = TX_EMPTY +#else +#define _tx_block_pool_initialize() \ + _tx_block_pool_created_ptr = TX_NULL; \ + _tx_block_pool_created_count = TX_EMPTY; \ + _tx_block_pool_performance_allocate_count = ((ULONG) 0); \ + _tx_block_pool_performance_release_count = ((ULONG) 0); \ + _tx_block_pool_performance_suspension_count = ((ULONG) 0); \ + _tx_block_pool_performance_timeout_count = ((ULONG) 0) +#endif +#define TX_BLOCK_POOL_INIT +#else + +/* No in-line initialization is supported, use standard function call. */ +VOID _tx_block_pool_initialize(VOID); +#endif + + +/* Define internal block memory pool management function prototypes. */ + +VOID _tx_block_pool_cleanup(TX_THREAD *thread_ptr, ULONG suspension_sequence); + + +/* Block pool management component data declarations follow. */ + +/* Determine if the initialization function of this component is including + this file. If so, make the data definitions really happen. Otherwise, + make them extern so other functions in the component can access them. */ + +#ifdef TX_BLOCK_POOL_INIT +#define BLOCK_POOL_DECLARE +#else +#define BLOCK_POOL_DECLARE extern +#endif + + +/* Define the head pointer of the created block pool list. */ + +BLOCK_POOL_DECLARE TX_BLOCK_POOL * _tx_block_pool_created_ptr; + + +/* Define the variable that holds the number of created block pools. */ + +BLOCK_POOL_DECLARE ULONG _tx_block_pool_created_count; + + +#ifdef TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO + +/* Define the total number of block allocates. */ + +BLOCK_POOL_DECLARE ULONG _tx_block_pool_performance_allocate_count; + + +/* Define the total number of block releases. */ + +BLOCK_POOL_DECLARE ULONG _tx_block_pool_performance_release_count; + + +/* Define the total number of block pool suspensions. */ + +BLOCK_POOL_DECLARE ULONG _tx_block_pool_performance_suspension_count; + + +/* Define the total number of block pool timeouts. */ + +BLOCK_POOL_DECLARE ULONG _tx_block_pool_performance_timeout_count; + + +#endif + + +/* Define default post block pool delete macro to whitespace, if it hasn't been defined previously (typically in tx_port.h). */ + +#ifndef TX_BLOCK_POOL_DELETE_PORT_COMPLETION +#define TX_BLOCK_POOL_DELETE_PORT_COMPLETION(p) +#endif + + +#endif diff --git a/common_smp/inc/tx_byte_pool.h b/common_smp/inc/tx_byte_pool.h new file mode 100644 index 00000000..e3b4047c --- /dev/null +++ b/common_smp/inc/tx_byte_pool.h @@ -0,0 +1,177 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Byte Memory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* tx_byte_pool.h PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the ThreadX byte memory management component, */ +/* including all data types and external references. It is assumed */ +/* that tx_api.h and tx_port.h have already been included. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_BYTE_POOL_H +#define TX_BYTE_POOL_H + + +/* Define byte memory control specific data definitions. */ + +#define TX_BYTE_POOL_ID ((ULONG) 0x42595445) + +#ifndef TX_BYTE_BLOCK_FREE +#define TX_BYTE_BLOCK_FREE ((ULONG) 0xFFFFEEEEUL) +#endif + +#ifndef TX_BYTE_BLOCK_MIN +#define TX_BYTE_BLOCK_MIN ((ULONG) 20) +#endif + +#ifndef TX_BYTE_POOL_MIN +#define TX_BYTE_POOL_MIN ((ULONG) 100) +#endif + + +/* Determine if in-line component initialization is supported by the + caller. */ + +#ifdef TX_INVOKE_INLINE_INITIALIZATION + +/* Yes, in-line initialization is supported, remap the byte memory pool + initialization function. */ + +#ifndef TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO +#define _tx_byte_pool_initialize() \ + _tx_byte_pool_created_ptr = TX_NULL; \ + _tx_byte_pool_created_count = TX_EMPTY +#else +#define _tx_byte_pool_initialize() \ + _tx_byte_pool_created_ptr = TX_NULL; \ + _tx_byte_pool_created_count = TX_EMPTY; \ + _tx_byte_pool_performance_allocate_count = ((ULONG) 0); \ + _tx_byte_pool_performance_release_count = ((ULONG) 0); \ + _tx_byte_pool_performance_merge_count = ((ULONG) 0); \ + _tx_byte_pool_performance_split_count = ((ULONG) 0); \ + _tx_byte_pool_performance_search_count = ((ULONG) 0); \ + _tx_byte_pool_performance_suspension_count = ((ULONG) 0); \ + _tx_byte_pool_performance_timeout_count = ((ULONG) 0) +#endif +#define TX_BYTE_POOL_INIT +#else + +/* No in-line initialization is supported, use standard function call. */ +VOID _tx_byte_pool_initialize(VOID); +#endif + + +/* Define internal byte memory pool management function prototypes. */ + +UCHAR *_tx_byte_pool_search(TX_BYTE_POOL *pool_ptr, ULONG memory_size); +VOID _tx_byte_pool_cleanup(TX_THREAD *thread_ptr, ULONG suspension_sequence); + + +/* Byte pool management component data declarations follow. */ + +/* Determine if the initialization function of this component is including + this file. If so, make the data definitions really happen. Otherwise, + make them extern so other functions in the component can access them. */ + +#ifdef TX_BYTE_POOL_INIT +#define BYTE_POOL_DECLARE +#else +#define BYTE_POOL_DECLARE extern +#endif + + +/* Define the head pointer of the created byte pool list. */ + +BYTE_POOL_DECLARE TX_BYTE_POOL * _tx_byte_pool_created_ptr; + + +/* Define the variable that holds the number of created byte pools. */ + +BYTE_POOL_DECLARE ULONG _tx_byte_pool_created_count; + + +#ifdef TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO + +/* Define the total number of allocates. */ + +BYTE_POOL_DECLARE ULONG _tx_byte_pool_performance_allocate_count; + + +/* Define the total number of releases. */ + +BYTE_POOL_DECLARE ULONG _tx_byte_pool_performance_release_count; + + +/* Define the total number of adjacent memory fragment merges. */ + +BYTE_POOL_DECLARE ULONG _tx_byte_pool_performance_merge_count; + + +/* Define the total number of memory fragment splits. */ + +BYTE_POOL_DECLARE ULONG _tx_byte_pool_performance_split_count; + + +/* Define the total number of memory fragments searched during allocation. */ + +BYTE_POOL_DECLARE ULONG _tx_byte_pool_performance_search_count; + + +/* Define the total number of byte pool suspensions. */ + +BYTE_POOL_DECLARE ULONG _tx_byte_pool_performance_suspension_count; + + +/* Define the total number of byte pool timeouts. */ + +BYTE_POOL_DECLARE ULONG _tx_byte_pool_performance_timeout_count; + + +#endif + + +/* Define default post byte pool delete macro to whitespace, if it hasn't been defined previously (typically in tx_port.h). */ + +#ifndef TX_BYTE_POOL_DELETE_PORT_COMPLETION +#define TX_BYTE_POOL_DELETE_PORT_COMPLETION(p) +#endif + + +#endif diff --git a/common_smp/inc/tx_event_flags.h b/common_smp/inc/tx_event_flags.h new file mode 100644 index 00000000..f663d7d8 --- /dev/null +++ b/common_smp/inc/tx_event_flags.h @@ -0,0 +1,147 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Event Flags */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* tx_event_flags.h PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the ThreadX event flags management component, */ +/* including all data types and external references. It is assumed */ +/* that tx_api.h and tx_port.h have already been included. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_EVENT_FLAGS_H +#define TX_EVENT_FLAGS_H + + +/* Define event flags control specific data definitions. */ + +#define TX_EVENT_FLAGS_ID ((ULONG) 0x4456444E) +#define TX_EVENT_FLAGS_AND_MASK ((UINT) 0x2) +#define TX_EVENT_FLAGS_CLEAR_MASK ((UINT) 0x1) + + +/* Determine if in-line component initialization is supported by the + caller. */ +#ifdef TX_INVOKE_INLINE_INITIALIZATION + +/* Yes, in-line initialization is supported, remap the event flag initialization + function. */ + +#ifndef TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO +#define _tx_event_flags_initialize() \ + _tx_event_flags_created_ptr = TX_NULL; \ + _tx_event_flags_created_count = TX_EMPTY +#else +#define _tx_event_flags_initialize() \ + _tx_event_flags_created_ptr = TX_NULL; \ + _tx_event_flags_created_count = TX_EMPTY; \ + _tx_event_flags_performance_set_count = ((ULONG) 0); \ + _tx_event_flags_performance_get_count = ((ULONG) 0); \ + _tx_event_flags_performance_suspension_count = ((ULONG) 0); \ + _tx_event_flags_performance_timeout_count = ((ULONG) 0) +#endif +#define TX_EVENT_FLAGS_INIT +#else + +/* No in-line initialization is supported, use standard function call. */ +VOID _tx_event_flags_initialize(VOID); +#endif + + +/* Define internal event flags management function prototypes. */ + +VOID _tx_event_flags_cleanup(TX_THREAD *thread_ptr, ULONG suspension_sequence); + + +/* Event flags management component data declarations follow. */ + +/* Determine if the initialization function of this component is including + this file. If so, make the data definitions really happen. Otherwise, + make them extern so other functions in the component can access them. */ + +#ifdef TX_EVENT_FLAGS_INIT +#define EVENT_FLAGS_DECLARE +#else +#define EVENT_FLAGS_DECLARE extern +#endif + + +/* Define the head pointer of the created event flags list. */ + +EVENT_FLAGS_DECLARE TX_EVENT_FLAGS_GROUP * _tx_event_flags_created_ptr; + + +/* Define the variable that holds the number of created event flag groups. */ + +EVENT_FLAGS_DECLARE ULONG _tx_event_flags_created_count; + + +#ifdef TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO + +/* Define the total number of event flag sets. */ + +EVENT_FLAGS_DECLARE ULONG _tx_event_flags_performance_set_count; + + +/* Define the total number of event flag gets. */ + +EVENT_FLAGS_DECLARE ULONG _tx_event_flags_performance_get_count; + + +/* Define the total number of event flag suspensions. */ + +EVENT_FLAGS_DECLARE ULONG _tx_event_flags_performance_suspension_count; + + +/* Define the total number of event flag timeouts. */ + +EVENT_FLAGS_DECLARE ULONG _tx_event_flags_performance_timeout_count; + + +#endif + +/* Define default post event flag group delete macro to whitespace, if it hasn't been defined previously (typically in tx_port.h). */ + +#ifndef TX_EVENT_FLAGS_GROUP_DELETE_PORT_COMPLETION +#define TX_EVENT_FLAGS_GROUP_DELETE_PORT_COMPLETION(g) +#endif + + +#endif + diff --git a/common_smp/inc/tx_initialize.h b/common_smp/inc/tx_initialize.h new file mode 100644 index 00000000..ddc1c7d8 --- /dev/null +++ b/common_smp/inc/tx_initialize.h @@ -0,0 +1,111 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* tx_initialize.h PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the ThreadX initialization component, including */ +/* data types and external references. It is assumed that tx_api.h */ +/* and tx_port.h have already been included. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_INITIALIZE_H +#define TX_INITIALIZE_H + + +/* Define constants that indicate initialization is in progress. */ + +#define TX_INITIALIZE_IN_PROGRESS ((ULONG) 0xF0F0F0F0UL) +#define TX_INITIALIZE_ALMOST_DONE ((ULONG) 0xF0F0F0F1UL) +#define TX_INITIALIZE_IS_FINISHED ((ULONG) 0x00000000UL) + + +/* Define internal initialization function prototypes. */ + +VOID _tx_initialize_high_level(VOID); +VOID _tx_initialize_kernel_setup(VOID); +VOID _tx_initialize_low_level(VOID); + + +/* Define the macro for adding additional port-specific global data. This macro is defined + as white space, unless defined by tx_port.h. */ + +#ifndef TX_PORT_SPECIFIC_DATA +#define TX_PORT_SPECIFIC_DATA +#endif + + +/* Define the macro for adding additional port-specific pre and post initialization processing. + These macros is defined as white space, unless defined by tx_port.h. */ + +#ifndef TX_PORT_SPECIFIC_PRE_INITIALIZATION +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION +#endif + +#ifndef TX_PORT_SPECIFIC_POST_INITIALIZATION +#define TX_PORT_SPECIFIC_POST_INITIALIZATION +#endif + +#ifndef TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION +#endif + + +/* Initialization component data declarations follow. */ + +/* Determine if the initialization function of this component is including + this file. If so, make the data definitions really happen. Otherwise, + make them extern so other functions in the component can access them. */ + +#ifdef TX_INITIALIZE_INIT +#define INITIALIZE_DECLARE +#else +#define INITIALIZE_DECLARE extern +#endif + + +/* Define the unused memory pointer. The value of the first available + memory address is placed in this variable in the low-level + initialization function. The content of this variable is passed + to the application's system definition function. */ + +INITIALIZE_DECLARE VOID *_tx_initialize_unused_memory; + + +#endif diff --git a/common_smp/inc/tx_mutex.h b/common_smp/inc/tx_mutex.h new file mode 100644 index 00000000..17592e66 --- /dev/null +++ b/common_smp/inc/tx_mutex.h @@ -0,0 +1,160 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Mutex */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* tx_mutex.h PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the ThreadX mutex management component, */ +/* including all data types and external references. It is assumed */ +/* that tx_api.h and tx_port.h have already been included. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_MUTEX_H +#define TX_MUTEX_H + + +/* Define mutex control specific data definitions. */ + +#define TX_MUTEX_ID ((ULONG) 0x4D555445) + + +/* Determine if in-line component initialization is supported by the + caller. */ + +#ifdef TX_INVOKE_INLINE_INITIALIZATION + +/* Yes, in-line initialization is supported, remap the mutex initialization + function. */ + +#ifndef TX_MUTEX_ENABLE_PERFORMANCE_INFO +#define _tx_mutex_initialize() \ + _tx_mutex_created_ptr = TX_NULL; \ + _tx_mutex_created_count = TX_EMPTY +#else +#define _tx_mutex_initialize() \ + _tx_mutex_created_ptr = TX_NULL; \ + _tx_mutex_created_count = TX_EMPTY; \ + _tx_mutex_performance_put_count = ((ULONG) 0); \ + _tx_mutex_performance_get_count = ((ULONG) 0); \ + _tx_mutex_performance_suspension_count = ((ULONG) 0); \ + _tx_mutex_performance_timeout_count = ((ULONG) 0); \ + _tx_mutex_performance_priority_inversion_count = ((ULONG) 0); \ + _tx_mutex_performance__priority_inheritance_count = ((ULONG) 0) +#endif +#define TX_MUTEX_INIT +#else + +/* No in-line initialization is supported, use standard function call. */ +VOID _tx_mutex_initialize(VOID); +#endif + + +/* Define internal mutex management function prototypes. */ + +VOID _tx_mutex_cleanup(TX_THREAD *thread_ptr, ULONG suspension_sequence); +VOID _tx_mutex_thread_release(TX_THREAD *thread_ptr); +VOID _tx_mutex_priority_change(TX_THREAD *thread_ptr, UINT new_priority); + + +/* Mutex management component data declarations follow. */ + +/* Determine if the initialization function of this component is including + this file. If so, make the data definitions really happen. Otherwise, + make them extern so other functions in the component can access them. */ + +#ifdef TX_MUTEX_INIT +#define MUTEX_DECLARE +#else +#define MUTEX_DECLARE extern +#endif + + +/* Define the head pointer of the created mutex list. */ + +MUTEX_DECLARE TX_MUTEX * _tx_mutex_created_ptr; + + +/* Define the variable that holds the number of created mutexes. */ + +MUTEX_DECLARE ULONG _tx_mutex_created_count; + + +#ifdef TX_MUTEX_ENABLE_PERFORMANCE_INFO + +/* Define the total number of mutex puts. */ + +MUTEX_DECLARE ULONG _tx_mutex_performance_put_count; + + +/* Define the total number of mutex gets. */ + +MUTEX_DECLARE ULONG _tx_mutex_performance_get_count; + + +/* Define the total number of mutex suspensions. */ + +MUTEX_DECLARE ULONG _tx_mutex_performance_suspension_count; + + +/* Define the total number of mutex timeouts. */ + +MUTEX_DECLARE ULONG _tx_mutex_performance_timeout_count; + + +/* Define the total number of priority inversions. */ + +MUTEX_DECLARE ULONG _tx_mutex_performance_priority_inversion_count; + + +/* Define the total number of priority inheritance conditions. */ + +MUTEX_DECLARE ULONG _tx_mutex_performance__priority_inheritance_count; + + +#endif + + +/* Define default post mutex delete macro to whitespace, if it hasn't been defined previously (typically in tx_port.h). */ + +#ifndef TX_MUTEX_DELETE_PORT_COMPLETION +#define TX_MUTEX_DELETE_PORT_COMPLETION(m) +#endif + + +#endif diff --git a/common_smp/inc/tx_queue.h b/common_smp/inc/tx_queue.h new file mode 100644 index 00000000..c5d0868a --- /dev/null +++ b/common_smp/inc/tx_queue.h @@ -0,0 +1,173 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Queue */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* tx_queue.h PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the ThreadX queue management component, */ +/* including all data types and external references. It is assumed */ +/* that tx_api.h and tx_port.h have already been included. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_QUEUE_H +#define TX_QUEUE_H + + +/* Define queue control specific data definitions. */ + +#define TX_QUEUE_ID ((ULONG) 0x51554555) + + +/* Determine if in-line component initialization is supported by the + caller. */ +#ifdef TX_INVOKE_INLINE_INITIALIZATION + +/* Yes, in-line initialization is supported, remap the queue initialization + function. */ + +#ifndef TX_QUEUE_ENABLE_PERFORMANCE_INFO +#define _tx_queue_initialize() \ + _tx_queue_created_ptr = TX_NULL; \ + _tx_queue_created_count = TX_EMPTY +#else +#define _tx_queue_initialize() \ + _tx_queue_created_ptr = TX_NULL; \ + _tx_queue_created_count = TX_EMPTY; \ + _tx_queue_performance_messages_sent_count = ((ULONG) 0); \ + _tx_queue_performance__messages_received_count = ((ULONG) 0); \ + _tx_queue_performance_empty_suspension_count = ((ULONG) 0); \ + _tx_queue_performance_full_suspension_count = ((ULONG) 0); \ + _tx_queue_performance_timeout_count = ((ULONG) 0) +#endif +#define TX_QUEUE_INIT +#else + +/* No in-line initialization is supported, use standard function call. */ +VOID _tx_queue_initialize(VOID); +#endif + + +/* Define the message copy macro. Note that the source and destination + pointers must be modified since they are used subsequently. */ + +#ifndef TX_QUEUE_MESSAGE_COPY +#define TX_QUEUE_MESSAGE_COPY(s, d, z) \ + *(d)++ = *(s)++; \ + if ((z) > ((UINT) 1)) \ + { \ + while (--(z)) \ + { \ + *(d)++ = *(s)++; \ + } \ + } +#endif + + +/* Define internal queue management function prototypes. */ + +VOID _tx_queue_cleanup(TX_THREAD *thread_ptr, ULONG suspension_sequence); + + +/* Queue management component data declarations follow. */ + +/* Determine if the initialization function of this component is including + this file. If so, make the data definitions really happen. Otherwise, + make them extern so other functions in the component can access them. */ + +#ifdef TX_QUEUE_INIT +#define QUEUE_DECLARE +#else +#define QUEUE_DECLARE extern +#endif + + +/* Define the head pointer of the created queue list. */ + +QUEUE_DECLARE TX_QUEUE * _tx_queue_created_ptr; + + +/* Define the variable that holds the number of created queues. */ + +QUEUE_DECLARE ULONG _tx_queue_created_count; + + +#ifdef TX_QUEUE_ENABLE_PERFORMANCE_INFO + +/* Define the total number of messages sent. */ + +QUEUE_DECLARE ULONG _tx_queue_performance_messages_sent_count; + + +/* Define the total number of messages received. */ + +QUEUE_DECLARE ULONG _tx_queue_performance__messages_received_count; + + +/* Define the total number of queue empty suspensions. */ + +QUEUE_DECLARE ULONG _tx_queue_performance_empty_suspension_count; + + +/* Define the total number of queue full suspensions. */ + +QUEUE_DECLARE ULONG _tx_queue_performance_full_suspension_count; + + +/* Define the total number of queue full errors. */ + +QUEUE_DECLARE ULONG _tx_queue_performance_full_error_count; + + +/* Define the total number of queue timeouts. */ + +QUEUE_DECLARE ULONG _tx_queue_performance_timeout_count; + + +#endif + + +/* Define default post queue delete macro to whitespace, if it hasn't been defined previously (typically in tx_port.h). */ + +#ifndef TX_QUEUE_DELETE_PORT_COMPLETION +#define TX_QUEUE_DELETE_PORT_COMPLETION(q) +#endif + + +#endif + diff --git a/common_smp/inc/tx_semaphore.h b/common_smp/inc/tx_semaphore.h new file mode 100644 index 00000000..4a5a3e43 --- /dev/null +++ b/common_smp/inc/tx_semaphore.h @@ -0,0 +1,144 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Semaphore */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* tx_semaphore.h PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the ThreadX semaphore management component, */ +/* including all data types and external references. It is assumed */ +/* that tx_api.h and tx_port.h have already been included. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_SEMAPHORE_H +#define TX_SEMAPHORE_H + + +/* Define semaphore control specific data definitions. */ + +#define TX_SEMAPHORE_ID ((ULONG) 0x53454D41) + + +/* Determine if in-line component initialization is supported by the + caller. */ +#ifdef TX_INVOKE_INLINE_INITIALIZATION + /* Yes, in-line initialization is supported, remap the + semaphore initialization function. */ +#ifndef TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO +#define _tx_semaphore_initialize() \ + _tx_semaphore_created_ptr = TX_NULL; \ + _tx_semaphore_created_count = TX_EMPTY +#else +#define _tx_semaphore_initialize() \ + _tx_semaphore_created_ptr = TX_NULL; \ + _tx_semaphore_created_count = TX_EMPTY; \ + _tx_semaphore_performance_put_count = ((ULONG) 0); \ + _tx_semaphore_performance_get_count = ((ULONG) 0); \ + _tx_semaphore_performance_suspension_count = ((ULONG) 0); \ + _tx_semaphore_performance_timeout_count = ((ULONG) 0) +#endif +#define TX_SEMAPHORE_INIT +#else + /* No in-line initialization is supported, use standard + function call. */ +VOID _tx_semaphore_initialize(VOID); +#endif + + +/* Define internal semaphore management function prototypes. */ + +VOID _tx_semaphore_cleanup(TX_THREAD *thread_ptr, ULONG suspension_sequence); + + +/* Semaphore management component data declarations follow. */ + +/* Determine if the initialization function of this component is including + this file. If so, make the data definitions really happen. Otherwise, + make them extern so other functions in the component can access them. */ + +#ifdef TX_SEMAPHORE_INIT +#define SEMAPHORE_DECLARE +#else +#define SEMAPHORE_DECLARE extern +#endif + + +/* Define the head pointer of the created semaphore list. */ + +SEMAPHORE_DECLARE TX_SEMAPHORE * _tx_semaphore_created_ptr; + + +/* Define the variable that holds the number of created semaphores. */ + +SEMAPHORE_DECLARE ULONG _tx_semaphore_created_count; + + +#ifdef TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO + +/* Define the total number of semaphore puts. */ + +SEMAPHORE_DECLARE ULONG _tx_semaphore_performance_put_count; + + +/* Define the total number of semaphore gets. */ + +SEMAPHORE_DECLARE ULONG _tx_semaphore_performance_get_count; + + +/* Define the total number of semaphore suspensions. */ + +SEMAPHORE_DECLARE ULONG _tx_semaphore_performance_suspension_count; + + +/* Define the total number of semaphore timeouts. */ + +SEMAPHORE_DECLARE ULONG _tx_semaphore_performance_timeout_count; + + +#endif + + +/* Define default post semaphore delete macro to whitespace, if it hasn't been defined previously (typically in tx_port.h). */ + +#ifndef TX_SEMAPHORE_DELETE_PORT_COMPLETION +#define TX_SEMAPHORE_DELETE_PORT_COMPLETION(s) +#endif + + +#endif + diff --git a/common_smp/inc/tx_thread.h b/common_smp/inc/tx_thread.h new file mode 100644 index 00000000..b38b0f6d --- /dev/null +++ b/common_smp/inc/tx_thread.h @@ -0,0 +1,1680 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* tx_thread.h PORTABLE SMP */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the ThreadX thread control component, including */ +/* data types and external references. It is assumed that tx_api.h */ +/* and tx_port.h have already been included. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_THREAD_H +#define TX_THREAD_H + + +/* Add include files needed for in-line macros. */ + +#include "tx_initialize.h" + + +/* Define thread control specific data definitions. */ + +#define TX_THREAD_ID ((ULONG) 0x54485244) +#define TX_THREAD_MAX_BYTE_VALUES 256 +#define TX_THREAD_PRIORITY_GROUP_MASK ((ULONG) 0xFF) +#define TX_THREAD_PRIORITY_GROUP_SIZE 8 +#define TX_THREAD_EXECUTE_LOG_SIZE ((UINT) 8) +#define TX_THREAD_SMP_PROTECT_WAIT_LIST_SIZE (TX_THREAD_SMP_MAX_CORES + 1) + + +/* Define the default thread stack checking. This can be overridden by + a particular port, which is necessary if the stack growth is from + low address to high address (the default logic is for stacks that + grow from high address to low address. */ + +#ifndef TX_THREAD_STACK_CHECK +#define TX_THREAD_STACK_CHECK(thread_ptr) \ + { \ + TX_INTERRUPT_SAVE_AREA \ + TX_DISABLE \ + if (((thread_ptr)) && ((thread_ptr) -> tx_thread_id == TX_THREAD_ID)) \ + { \ + if (((ULONG *) (thread_ptr) -> tx_thread_stack_ptr) < ((ULONG *) (thread_ptr) -> tx_thread_stack_highest_ptr)) \ + { \ + (thread_ptr) -> tx_thread_stack_highest_ptr = (thread_ptr) -> tx_thread_stack_ptr; \ + } \ + if ((*((ULONG *) (thread_ptr) -> tx_thread_stack_start) != TX_STACK_FILL) || \ + (*((ULONG *) (((UCHAR *) (thread_ptr) -> tx_thread_stack_end) + 1)) != TX_STACK_FILL) || \ + (((ULONG *) (thread_ptr) -> tx_thread_stack_highest_ptr) < ((ULONG *) (thread_ptr) -> tx_thread_stack_start))) \ + { \ + TX_RESTORE \ + _tx_thread_stack_error_handler((thread_ptr)); \ + TX_DISABLE \ + } \ + if (*(((ULONG *) (thread_ptr) -> tx_thread_stack_highest_ptr) - 1) != TX_STACK_FILL) \ + { \ + TX_RESTORE \ + _tx_thread_stack_analyze((thread_ptr)); \ + TX_DISABLE \ + } \ + } \ + TX_RESTORE \ + } +#endif + + +/* Define default post thread delete macro to whitespace, if it hasn't been defined previously (typically in tx_port.h). */ + +#ifndef TX_THREAD_DELETE_PORT_COMPLETION +#define TX_THREAD_DELETE_PORT_COMPLETION(t) +#endif + + +/* Define default post thread reset macro to whitespace, if it hasn't been defined previously (typically in tx_port.h). */ + +#ifndef TX_THREAD_RESET_PORT_COMPLETION +#define TX_THREAD_RESET_PORT_COMPLETION(t) +#endif + + +/* Define the thread create internal extension macro to whitespace, if it hasn't been defined previously (typically in tx_port.h). */ + +#ifndef TX_THREAD_CREATE_INTERNAL_EXTENSION +#define TX_THREAD_CREATE_INTERNAL_EXTENSION(t) +#endif + + +/* Define internal thread control function prototypes. */ + +VOID _tx_thread_initialize(VOID); +VOID _tx_thread_schedule(VOID); +VOID _tx_thread_shell_entry(VOID); +VOID _tx_thread_stack_analyze(TX_THREAD *thread_ptr); +VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)); +VOID _tx_thread_stack_error(TX_THREAD *thread_ptr); +VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr); +VOID _tx_thread_system_preempt_check(VOID); +VOID _tx_thread_system_resume(TX_THREAD *thread_ptr); +VOID _tx_thread_system_ni_resume(TX_THREAD *thread_ptr); +VOID _tx_thread_system_return(VOID); +VOID _tx_thread_system_suspend(TX_THREAD *thread_ptr); +VOID _tx_thread_system_ni_suspend(TX_THREAD *thread_ptr, ULONG timeout); +VOID _tx_thread_time_slice(VOID); +VOID _tx_thread_timeout(ULONG timeout_input); + + +/* Define all internal SMP prototypes. */ + +void _tx_thread_smp_current_state_set(ULONG new_state); +UINT _tx_thread_smp_find_next_priority(UINT priority); +void _tx_thread_smp_high_level_initialize(void); +void _tx_thread_smp_rebalance_execute_list(UINT core_index); + + +/* Define all internal ThreadX SMP low-level assembly routines. */ + +VOID _tx_thread_smp_core_wait(void); +void _tx_thread_smp_initialize_wait(void); +void _tx_thread_smp_low_level_initialize(UINT number_of_cores); +void _tx_thread_smp_core_preempt(UINT core); + + +/* Thread control component external data declarations follow. */ + +#define THREAD_DECLARE extern + + +/* Define the pointer that contains the system stack pointer. This is + utilized when control returns from a thread to the system to reset the + current stack. This is setup in the low-level initialization function. */ + +THREAD_DECLARE VOID * _tx_thread_system_stack_ptr[TX_THREAD_SMP_MAX_CORES]; + + +/* Define the current thread pointer. This variable points to the currently + executing thread. If this variable is NULL, no thread is executing. */ + +THREAD_DECLARE TX_THREAD * _tx_thread_current_ptr[TX_THREAD_SMP_MAX_CORES]; + + +/* Define the variable that holds the next thread to execute. It is important + to remember that this is not necessarily equal to the current thread + pointer. */ + +THREAD_DECLARE TX_THREAD * _tx_thread_execute_ptr[TX_THREAD_SMP_MAX_CORES]; + + +/* Define the ThreadX SMP scheduling and mapping data structures. */ + +THREAD_DECLARE TX_THREAD * _tx_thread_smp_schedule_list[TX_THREAD_SMP_MAX_CORES]; +THREAD_DECLARE ULONG _tx_thread_smp_reschedule_pending; +THREAD_DECLARE TX_THREAD_SMP_PROTECT _tx_thread_smp_protection; +THREAD_DECLARE volatile ULONG _tx_thread_smp_release_cores_flag; +THREAD_DECLARE ULONG _tx_thread_smp_system_error; +THREAD_DECLARE ULONG _tx_thread_smp_inter_core_interrupts[TX_THREAD_SMP_MAX_CORES]; + +THREAD_DECLARE ULONG _tx_thread_smp_protect_wait_list_size; +THREAD_DECLARE ULONG _tx_thread_smp_protect_wait_list[TX_THREAD_SMP_PROTECT_WAIT_LIST_SIZE]; +THREAD_DECLARE ULONG _tx_thread_smp_protect_wait_counts[TX_THREAD_SMP_MAX_CORES]; +THREAD_DECLARE ULONG _tx_thread_smp_protect_wait_list_lock_protect_in_force; +THREAD_DECLARE ULONG _tx_thread_smp_protect_wait_list_tail; +THREAD_DECLARE ULONG _tx_thread_smp_protect_wait_list_head; + + +/* Define logic for conditional dynamic maximum number of cores. */ + +#ifdef TX_THREAD_SMP_DYNAMIC_CORE_MAX + +THREAD_DECLARE ULONG _tx_thread_smp_max_cores; +THREAD_DECLARE ULONG _tx_thread_smp_detected_cores; + +#endif + + + +/* Define the head pointer of the created thread list. */ + +THREAD_DECLARE TX_THREAD * _tx_thread_created_ptr; + + +/* Define the variable that holds the number of created threads. */ + +THREAD_DECLARE ULONG _tx_thread_created_count; + + +/* Define the current state variable. When this value is 0, a thread + is executing or the system is idle. Other values indicate that + interrupt or initialization processing is active. This variable is + initialized to TX_INITIALIZE_IN_PROGRESS to indicate initialization is + active. */ + +THREAD_DECLARE volatile ULONG _tx_thread_system_state[TX_THREAD_SMP_MAX_CORES]; + + +/* Determine if we need to remap system state to a function call. */ + +#ifndef TX_THREAD_SMP_SOURCE_CODE + + +/* Yes, remap system state to a function call so we can get the system state for the current core. */ + +#define _tx_thread_system_state _tx_thread_smp_current_state_get() + + +/* Yes, remap get current thread to a function call so we can get the current thread for the current core. */ + +#define _tx_thread_current_ptr _tx_thread_smp_current_thread_get() + +#endif + + +/* Define the 32-bit priority bit-maps. There is one priority bit map for each + 32 priority levels supported. If only 32 priorities are supported there is + only one bit map. Each bit within a priority bit map represents that one + or more threads at the associated thread priority are ready. */ + +THREAD_DECLARE ULONG _tx_thread_priority_maps[TX_MAX_PRIORITIES/32]; + + +/* Define the priority map active bit map that specifies which of the previously + defined priority maps have something set. This is only necessary if more than + 32 priorities are supported. */ + +#if TX_MAX_PRIORITIES > 32 +THREAD_DECLARE ULONG _tx_thread_priority_map_active; +#endif + + +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD + +/* Define the 32-bit preempt priority bit maps. There is one preempt bit map + for each 32 priority levels supported. If only 32 priorities are supported + there is only one bit map. Each set set bit corresponds to a preempted priority + level that had preemption-threshold active to protect against preemption of a + range of relatively higher priority threads. */ + +THREAD_DECLARE ULONG _tx_thread_preempted_maps[TX_MAX_PRIORITIES/32]; + + +/* Define the preempt map active bit map that specifies which of the previously + defined preempt maps have something set. This is only necessary if more than + 32 priorities are supported. */ + +#if TX_MAX_PRIORITIES > 32 +THREAD_DECLARE ULONG _tx_thread_preempted_map_active; +#endif + + +/* Define the array that contains the thread at each priority level that was scheduled with + preemption-threshold enabled. This will be useful when returning from a nested + preemption-threshold condition. */ + +THREAD_DECLARE TX_THREAD *_tx_thread_preemption_threshold_list[TX_MAX_PRIORITIES]; + + +#endif + + +/* Define the last thread scheduled with preemption-threshold. When preemption-threshold is + disabled, a thread with preemption-threshold set disables all other threads from running. + Effectively, its preemption-threshold is 0. */ + +THREAD_DECLARE TX_THREAD *_tx_thread_preemption__threshold_scheduled; + + +/* Define the array of thread pointers. Each entry represents the threads that + are ready at that priority group. For example, index 10 in this array + represents the first thread ready at priority 10. If this entry is NULL, + no threads are ready at that priority. */ + +THREAD_DECLARE TX_THREAD * _tx_thread_priority_list[TX_MAX_PRIORITIES]; + + +/* Define the global preempt disable variable. If this is non-zero, preemption is + disabled. It is used internally by ThreadX to prevent preemption of a thread in + the middle of a service that is resuming or suspending another thread. */ + +THREAD_DECLARE volatile UINT _tx_thread_preempt_disable; + + +/* Define the global function pointer for mutex cleanup on thread completion or + termination. This pointer is setup during mutex initialization. */ + +THREAD_DECLARE VOID (*_tx_thread_mutex_release)(TX_THREAD *thread_ptr); + + +/* Define the global build options variable. This contains a bit map representing + how the ThreadX library was built. The following are the bit field definitions: + + Bit(s) Meaning + + 31 Reserved + 30 TX_NOT_INTERRUPTABLE defined + 29-24 Priority groups 1 -> 32 priorities + 2 -> 64 priorities + 3 -> 96 priorities + + ... + + 32 -> 1024 priorities + 23 TX_TIMER_PROCESS_IN_ISR defined + 22 TX_REACTIVATE_INLINE defined + 21 TX_DISABLE_STACK_FILLING defined + 20 TX_ENABLE_STACK_CHECKING defined + 19 TX_DISABLE_PREEMPTION_THRESHOLD defined + 18 TX_DISABLE_REDUNDANT_CLEARING defined + 17 TX_DISABLE_NOTIFY_CALLBACKS defined + 16 TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO defined + 15 TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO defined + 14 TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO defined + 13 TX_MUTEX_ENABLE_PERFORMANCE_INFO defined + 12 TX_QUEUE_ENABLE_PERFORMANCE_INFO defined + 11 TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO defined + 10 TX_THREAD_ENABLE_PERFORMANCE_INFO defined + 9 TX_TIMER_ENABLE_PERFORMANCE_INFO defined + 8 TX_ENABLE_EVENT_TRACE | TX_ENABLE_EVENT_LOGGING defined + 7 Reserved + 6 Reserved + 5 Reserved + 4 Reserved + 3 Reserved + 2 Reserved + 1 64-bit FPU Enabled + 0 Reserved */ + +THREAD_DECLARE ULONG _tx_build_options; + + +#ifdef TX_ENABLE_STACK_CHECKING + +/* Define the global function pointer for stack error handling. If a stack error is + detected and the application has registered a stack error handler, it will be + called via this function pointer. */ + +THREAD_DECLARE VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); + +#endif + +#ifdef TX_THREAD_ENABLE_PERFORMANCE_INFO + +/* Define the total number of thread resumptions. Each time a thread enters the + ready state this variable is incremented. */ + +THREAD_DECLARE ULONG _tx_thread_performance_resume_count; + + +/* Define the total number of thread suspensions. Each time a thread enters a + suspended state this variable is incremented. */ + +THREAD_DECLARE ULONG _tx_thread_performance_suspend_count; + + +/* Define the total number of solicited thread preemptions. Each time a thread is + preempted by directly calling a ThreadX service, this variable is incremented. */ + +THREAD_DECLARE ULONG _tx_thread_performance_solicited_preemption_count; + + +/* Define the total number of interrupt thread preemptions. Each time a thread is + preempted as a result of an ISR calling a ThreadX service, this variable is + incremented. */ + +THREAD_DECLARE ULONG _tx_thread_performance_interrupt_preemption_count; + + +/* Define the total number of priority inversions. Each time a thread is blocked by + a mutex owned by a lower-priority thread, this variable is incremented. */ + +THREAD_DECLARE ULONG _tx_thread_performance_priority_inversion_count; + + +/* Define the total number of time-slices. Each time a time-slice operation is + actually performed (another thread is setup for running) this variable is + incremented. */ + +THREAD_DECLARE ULONG _tx_thread_performance_time_slice_count; + + +/* Define the total number of thread relinquish operations. Each time a thread + relinquish operation is actually performed (another thread is setup for running) + this variable is incremented. */ + +THREAD_DECLARE ULONG _tx_thread_performance_relinquish_count; + + +/* Define the total number of thread timeouts. Each time a thread has a + timeout this variable is incremented. */ + +THREAD_DECLARE ULONG _tx_thread_performance_timeout_count; + + +/* Define the total number of thread wait aborts. Each time a thread's suspension + is lifted by the tx_thread_wait_abort call this variable is incremented. */ + +THREAD_DECLARE ULONG _tx_thread_performance_wait_abort_count; + + +/* Define the total number of idle system thread returns. Each time a thread returns to + an idle system (no other thread is ready to run) this variable is incremented. */ + +THREAD_DECLARE ULONG _tx_thread_performance_idle_return_count; + + +/* Define the total number of non-idle system thread returns. Each time a thread returns to + a non-idle system (another thread is ready to run) this variable is incremented. */ + +THREAD_DECLARE ULONG _tx_thread_performance_non_idle_return_count; + +#endif + + +/* Define macros and helper functions. */ + +/* Define the MOD32 bit set macro that is used to set/clear a priority bit within a specific + priority group. */ + +#if TX_MAX_PRIORITIES > 32 +#define MAP_INDEX (map_index) +#ifndef TX_MOD32_BIT_SET +#define TX_MOD32_BIT_SET(a,b) (b) = (((ULONG) 1) << ((a)%((UINT) 32))); +#endif +#else +#define MAP_INDEX (0) +#ifndef TX_MOD32_BIT_SET +#define TX_MOD32_BIT_SET(a,b) (b) = (((ULONG) 1) << ((a))); +#endif +#endif + + +/* Define the DIV32 bit set macro that is used to set/clear a priority group bit and is + only necessary when using priorities greater than 32. */ + +#if TX_MAX_PRIORITIES > 32 +#ifndef TX_DIV32_BIT_SET +#define TX_DIV32_BIT_SET(a,b) (b) = (((ULONG) 1) << ((a)/((UINT) 32))); +#endif +#endif + + +/* Define state change macro that can be used by run-mode debug agents to keep track of thread + state changes. By default, it is mapped to white space. */ + +#ifndef TX_THREAD_STATE_CHANGE +#define TX_THREAD_STATE_CHANGE(a, b) +#endif + + +/* Define the macro to set the current thread pointer. This is particularly useful in SMP + versions of ThreadX to add additional processing. The default implementation is to simply + access the global current thread pointer directly. */ + +#ifndef TX_THREAD_SET_CURRENT +#define TX_THREAD_SET_CURRENT(a) TX_MEMSET(&_tx_thread_current_ptr[0], (a), sizeof(_tx_thread_current_ptr)); +#endif + + +/* Define the get system state macro. By default, it is mapped to white space. */ + +#ifndef TX_THREAD_GET_SYSTEM_STATE +#define TX_THREAD_GET_SYSTEM_STATE() _tx_thread_smp_current_state_get() +#endif + + +/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value + indicates that _tx_thread_system_return should not be called. */ + +#ifndef TX_THREAD_SYSTEM_RETURN_CHECK +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = (ULONG) _tx_thread_preempt_disable; (c) = (c) | TX_THREAD_GET_SYSTEM_STATE(); +#endif + + +/* Define the timeout setup macro used in _tx_thread_create. */ + +#ifndef TX_THREAD_CREATE_TIMEOUT_SETUP +#define TX_THREAD_CREATE_TIMEOUT_SETUP(t) (t) -> tx_thread_timer.tx_timer_internal_timeout_function = &(_tx_thread_timeout); \ + (t) -> tx_thread_timer.tx_timer_internal_timeout_param = TX_POINTER_TO_ULONG_CONVERT((t)); +#endif + + +/* Define the thread timeout pointer setup macro used in _tx_thread_timeout. */ + +#ifndef TX_THREAD_TIMEOUT_POINTER_SETUP +#define TX_THREAD_TIMEOUT_POINTER_SETUP(t) (t) = TX_ULONG_TO_THREAD_POINTER_CONVERT(timeout_input); +#endif + + +#ifdef TX_THREAD_SMP_SOURCE_CODE + + +/* Determine if the in-line capability has been disabled. */ + +#ifndef TX_DISABLE_INLINE + + +/* Define the inline option, which is compiler specific. If not defined, it will be resolved as + "inline". */ + +#ifndef INLINE_DECLARE +#define INLINE_DECLARE inline +#endif + + +/* Define the lowest bit set macro. Note, that this may be overridden + by a port specific definition if there is supporting assembly language + instructions in the architecture. */ + +#ifndef TX_LOWEST_SET_BIT_CALCULATE + +static INLINE_DECLARE UINT _tx_thread_lowest_set_bit_calculate(ULONG map) +{ +UINT bit_set; + + if ((map & ((ULONG) 0x1)) != ((ULONG) 0)) + { + bit_set = ((UINT) 0); + } + else + { + map = map & (ULONG) ((~map) + ((ULONG) 1)); + if (map < ((ULONG) 0x100)) + { + bit_set = ((UINT) 1); + } + else if (map < ((ULONG) 0x10000)) + { + bit_set = ((UINT) 9); + map = map >> ((UINT) 8); + } + else if (map < ((ULONG) 0x01000000)) + { + bit_set = ((UINT) 17); + map = map >> ((UINT) 16); + } + else + { + bit_set = ((UINT) 25); + map = map >> ((UINT) 24); + } + if (map >= ((ULONG) 0x10)) + { + map = map >> ((UINT) 4); + bit_set = bit_set + ((UINT) 4); + } + if (map >= ((ULONG) 0x4)) + { + map = map >> ((UINT) 2); + bit_set = bit_set + ((UINT) 2); + } + bit_set = bit_set - (UINT) (map & (ULONG) 0x1); + } + + return(bit_set); +} + + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = _tx_thread_lowest_set_bit_calculate((m)); + +#endif + + +/* Define the next priority macro. Note, that this may be overridden + by a port specific definition. */ + +#ifndef TX_NEXT_PRIORITY_FIND +#if TX_MAX_PRIORITIES > 32 +static INLINE_DECLARE UINT _tx_thread_smp_next_priority_find(UINT priority) +{ +ULONG map_index; +ULONG local_priority_map_active; +ULONG local_priority_map; +ULONG priority_bit; +ULONG first_bit_set; +ULONG found_priority; + + found_priority = ((UINT) TX_MAX_PRIORITIES); + if (priority < ((UINT) TX_MAX_PRIORITIES)) + { + map_index = priority/((UINT) 32); + local_priority_map = _tx_thread_priority_maps[map_index]; + priority_bit = (((ULONG) 1) << (priority % ((UINT) 32))); + local_priority_map = local_priority_map & ~(priority_bit - ((UINT)1)); + if (local_priority_map != ((ULONG) 0)) + { + TX_LOWEST_SET_BIT_CALCULATE(local_priority_map, first_bit_set) + found_priority = (map_index * ((UINT) 32)) + first_bit_set; + } + else + { + /* Move to next map index. */ + map_index++; + if (map_index < (((UINT) TX_MAX_PRIORITIES)/((UINT) 32))) + { + priority_bit = (((ULONG) 1) << (map_index)); + local_priority_map_active = _tx_thread_priority_map_active & ~(priority_bit - ((UINT) 1)); + if (local_priority_map_active != ((ULONG) 0)) + { + TX_LOWEST_SET_BIT_CALCULATE(local_priority_map_active, map_index) + local_priority_map = _tx_thread_priority_maps[map_index]; + TX_LOWEST_SET_BIT_CALCULATE(local_priority_map, first_bit_set) + found_priority = (map_index * ((UINT) 32)) + first_bit_set; + } + } + } + } + return(found_priority); +} +#else + +static INLINE_DECLARE UINT _tx_thread_smp_next_priority_find(UINT priority) +{ +UINT first_bit_set; +ULONG local_priority_map; +UINT next_priority; + + local_priority_map = _tx_thread_priority_maps[0]; + local_priority_map = local_priority_map >> priority; + next_priority = priority; + if (local_priority_map == ((ULONG) 0)) + { + next_priority = ((UINT) TX_MAX_PRIORITIES); + } + else + { + if (next_priority >= ((UINT) TX_MAX_PRIORITIES)) + { + next_priority = ((UINT) TX_MAX_PRIORITIES); + } + else + { + TX_LOWEST_SET_BIT_CALCULATE(local_priority_map, first_bit_set) + next_priority = priority + first_bit_set; + } + } + + return(next_priority); +} +#endif +#endif + +static INLINE_DECLARE void _tx_thread_smp_schedule_list_clear(void) +{ +#if TX_THREAD_SMP_MAX_CORES > 6 +UINT i; +#endif + + + /* Clear the schedule list. */ + _tx_thread_smp_schedule_list[0] = TX_NULL; +#if TX_THREAD_SMP_MAX_CORES > 1 + _tx_thread_smp_schedule_list[1] = TX_NULL; +#if TX_THREAD_SMP_MAX_CORES > 2 + _tx_thread_smp_schedule_list[2] = TX_NULL; +#if TX_THREAD_SMP_MAX_CORES > 3 + _tx_thread_smp_schedule_list[3] = TX_NULL; +#if TX_THREAD_SMP_MAX_CORES > 4 + _tx_thread_smp_schedule_list[4] = TX_NULL; +#if TX_THREAD_SMP_MAX_CORES > 5 + _tx_thread_smp_schedule_list[5] = TX_NULL; +#if TX_THREAD_SMP_MAX_CORES > 6 + + /* Loop to clear the remainder of the schedule list. */ + i = ((UINT) 6); + +#ifndef TX_THREAD_SMP_DYNAMIC_CORE_MAX + + while (i < ((UINT) TX_THREAD_SMP_MAX_CORES)) +#else + + while (i < _tx_thread_smp_max_cores) +#endif + { + /* Clear entry in schedule list. */ + _tx_thread_smp_schedule_list[i] = TX_NULL; + + /* Move to next index. */ + i++; + } +#endif +#endif +#endif +#endif +#endif +#endif +} + +static INLINE_DECLARE VOID _tx_thread_smp_execute_list_clear(void) +{ +#if TX_THREAD_SMP_MAX_CORES > 6 +UINT j; +#endif + + /* Clear the execute list. */ + _tx_thread_execute_ptr[0] = TX_NULL; +#if TX_THREAD_SMP_MAX_CORES > 1 + _tx_thread_execute_ptr[1] = TX_NULL; +#if TX_THREAD_SMP_MAX_CORES > 2 + _tx_thread_execute_ptr[2] = TX_NULL; +#if TX_THREAD_SMP_MAX_CORES > 3 + _tx_thread_execute_ptr[3] = TX_NULL; +#if TX_THREAD_SMP_MAX_CORES > 4 + _tx_thread_execute_ptr[4] = TX_NULL; +#if TX_THREAD_SMP_MAX_CORES > 5 + _tx_thread_execute_ptr[5] = TX_NULL; +#if TX_THREAD_SMP_MAX_CORES > 6 + + /* Loop to clear the remainder of the execute list. */ + j = ((UINT) 6); + +#ifndef TX_THREAD_SMP_DYNAMIC_CORE_MAX + + while (j < ((UINT) TX_THREAD_SMP_MAX_CORES)) +#else + + while (j < _tx_thread_smp_max_cores) +#endif + { + + /* Clear entry in execute list. */ + _tx_thread_execute_ptr[j] = TX_NULL; + + /* Move to next index. */ + j++; + } +#endif +#endif +#endif +#endif +#endif +#endif +} + + +static INLINE_DECLARE VOID _tx_thread_smp_schedule_list_setup(void) +{ +#if TX_THREAD_SMP_MAX_CORES > 6 +UINT j; +#endif + + _tx_thread_smp_schedule_list[0] = _tx_thread_execute_ptr[0]; +#if TX_THREAD_SMP_MAX_CORES > 1 + _tx_thread_smp_schedule_list[1] = _tx_thread_execute_ptr[1]; +#if TX_THREAD_SMP_MAX_CORES > 2 + _tx_thread_smp_schedule_list[2] = _tx_thread_execute_ptr[2]; +#if TX_THREAD_SMP_MAX_CORES > 3 + _tx_thread_smp_schedule_list[3] = _tx_thread_execute_ptr[3]; +#if TX_THREAD_SMP_MAX_CORES > 4 + _tx_thread_smp_schedule_list[4] = _tx_thread_execute_ptr[4]; +#if TX_THREAD_SMP_MAX_CORES > 5 + _tx_thread_smp_schedule_list[5] = _tx_thread_execute_ptr[5]; +#if TX_THREAD_SMP_MAX_CORES > 6 + + /* Loop to setup the remainder of the schedule list. */ + j = ((UINT) 6); + +#ifndef TX_THREAD_SMP_DYNAMIC_CORE_MAX + while (j < ((UINT) TX_THREAD_SMP_MAX_CORES)) +#else + + while (j < _tx_thread_smp_max_cores) +#endif + { + + /* Setup entry in schedule list. */ + _tx_thread_smp_schedule_list[j] = _tx_thread_execute_ptr[j]; + + /* Move to next index. */ + j++; + } +#endif +#endif +#endif +#endif +#endif +#endif +} + + +#ifdef TX_THREAD_SMP_INTER_CORE_INTERRUPT +static INLINE_DECLARE VOID _tx_thread_smp_core_interrupt(TX_THREAD *thread_ptr, UINT current_core, UINT target_core) +{ + +TX_THREAD *current_thread; + + + /* Make sure this is a different core, since there is no need to interrupt the current core for + a scheduling change. */ + if (current_core != target_core) + { + + /* Yes, a different core is present. */ + + /* Pickup the currently executing thread. */ + current_thread = _tx_thread_current_ptr[target_core]; + + /* Determine if they are the same. */ + if ((current_thread != TX_NULL) && (thread_ptr != current_thread)) + { + + /* Not the same and not NULL... determine if the core is running at thread level. */ + if (_tx_thread_system_state[target_core] < TX_INITIALIZE_IN_PROGRESS) + { + + /* Preempt the mapped thread. */ + _tx_thread_smp_core_preempt(target_core); + } + } + } +} +#else + +/* Define to whitespace. */ +#define _tx_thread_smp_core_interrupt(a,b,c) + +#endif + + +#ifdef TX_THREAD_SMP_WAKEUP_LOGIC +static INLINE_DECLARE VOID _tx_thread_smp_core_wakeup(UINT current_core, UINT target_core) +{ + + /* Determine if the core specified is not the current core - no need to wakeup the + current core. */ + if (target_core != current_core) + { + + /* Wakeup based on application's macro. */ + TX_THREAD_SMP_WAKEUP(target_core); + } +} +#else + +/* Define to whitespace. */ +#define _tx_thread_smp_core_wakeup(a,b) + +#endif + + +static INLINE_DECLARE VOID _tx_thread_smp_execute_list_setup(UINT core_index) +{ + +TX_THREAD *schedule_thread; +UINT i; + + + /* Loop to copy the schedule list into the execution list. */ + i = ((UINT) 0); +#ifndef TX_THREAD_SMP_DYNAMIC_CORE_MAX + + while (i < ((UINT) TX_THREAD_SMP_MAX_CORES)) +#else + + while (i < _tx_thread_smp_max_cores) +#endif + { + + /* Pickup the thread to schedule. */ + schedule_thread = _tx_thread_smp_schedule_list[i]; + + /* Copy the schedule list into the execution list. */ + _tx_thread_execute_ptr[i] = schedule_thread; + + /* If necessary, interrupt the core with the new thread to schedule. */ + _tx_thread_smp_core_interrupt(schedule_thread, core_index, i); + +#ifdef TX_THREAD_SMP_WAKEUP_LOGIC + + /* Does this need to be waked up? */ + if ((i != core_index) && (schedule_thread != TX_NULL)) + { + + /* Wakeup based on application's macro. */ + TX_THREAD_SMP_WAKEUP(i); + } +#endif + /* Move to next index. */ + i++; + } +} + + +static INLINE_DECLARE ULONG _tx_thread_smp_available_cores_get(void) +{ + +#if TX_THREAD_SMP_MAX_CORES > 6 +UINT j; +#endif +ULONG available_cores; + + available_cores = ((ULONG) 0); + if (_tx_thread_execute_ptr[0] == TX_NULL) + { + available_cores = ((ULONG) 1); + } +#if TX_THREAD_SMP_MAX_CORES > 1 + if (_tx_thread_execute_ptr[1] == TX_NULL) + { + available_cores = available_cores | ((ULONG) 2); + } +#if TX_THREAD_SMP_MAX_CORES > 2 + if (_tx_thread_execute_ptr[2] == TX_NULL) + { + available_cores = available_cores | ((ULONG) 4); + } +#if TX_THREAD_SMP_MAX_CORES > 3 + if (_tx_thread_execute_ptr[3] == TX_NULL) + { + available_cores = available_cores | ((ULONG) 8); + } +#if TX_THREAD_SMP_MAX_CORES > 4 + if (_tx_thread_execute_ptr[4] == TX_NULL) + { + available_cores = available_cores | ((ULONG) 0x10); + } +#if TX_THREAD_SMP_MAX_CORES > 5 + if (_tx_thread_execute_ptr[5] == TX_NULL) + { + available_cores = available_cores | ((ULONG) 0x20); + } +#if TX_THREAD_SMP_MAX_CORES > 6 + + /* Loop to setup the remainder of the schedule list. */ + j = ((UINT) 6); + +#ifndef TX_THREAD_SMP_DYNAMIC_CORE_MAX + while (j < ((UINT) TX_THREAD_SMP_MAX_CORES)) +#else + + while (j < _tx_thread_smp_max_cores) +#endif + { + + /* Determine if this core is available. */ + if (_tx_thread_execute_ptr[j] == TX_NULL) + { + available_cores = available_cores | (((ULONG) 1) << j); + } + + /* Move to next core. */ + j++; + } +#endif +#endif +#endif +#endif +#endif +#endif + return(available_cores); +} + + +static INLINE_DECLARE ULONG _tx_thread_smp_possible_cores_get(void) +{ + +#if TX_THREAD_SMP_MAX_CORES > 6 +UINT j; +#endif +ULONG possible_cores; +TX_THREAD *thread_ptr; + + possible_cores = ((ULONG) 0); + thread_ptr = _tx_thread_execute_ptr[0]; + if (thread_ptr != TX_NULL) + { + possible_cores = thread_ptr -> tx_thread_smp_cores_allowed; + } +#if TX_THREAD_SMP_MAX_CORES > 1 + thread_ptr = _tx_thread_execute_ptr[1]; + if (thread_ptr != TX_NULL) + { + possible_cores = possible_cores | thread_ptr -> tx_thread_smp_cores_allowed; + } +#if TX_THREAD_SMP_MAX_CORES > 2 + thread_ptr = _tx_thread_execute_ptr[2]; + if (thread_ptr != TX_NULL) + { + possible_cores = possible_cores | thread_ptr -> tx_thread_smp_cores_allowed; + } +#if TX_THREAD_SMP_MAX_CORES > 3 + thread_ptr = _tx_thread_execute_ptr[3]; + if (thread_ptr != TX_NULL) + { + possible_cores = possible_cores | thread_ptr -> tx_thread_smp_cores_allowed; + } +#if TX_THREAD_SMP_MAX_CORES > 4 + thread_ptr = _tx_thread_execute_ptr[4]; + if (thread_ptr != TX_NULL) + { + possible_cores = possible_cores | thread_ptr -> tx_thread_smp_cores_allowed; + } +#if TX_THREAD_SMP_MAX_CORES > 5 + thread_ptr = _tx_thread_execute_ptr[5]; + if (thread_ptr != TX_NULL) + { + possible_cores = possible_cores | thread_ptr -> tx_thread_smp_cores_allowed; + } +#if TX_THREAD_SMP_MAX_CORES > 6 + + /* Loop to setup the remainder of the schedule list. */ + j = ((UINT) 6); + +#ifndef TX_THREAD_SMP_DYNAMIC_CORE_MAX + while (j < ((UINT) TX_THREAD_SMP_MAX_CORES)) +#else + + while (j < _tx_thread_smp_max_cores) +#endif + { + + /* Determine if this core is available. */ + thread_ptr = _tx_thread_execute_ptr[j]; + if (thread_ptr != TX_NULL) + { + possible_cores = possible_cores | thread_ptr -> tx_thread_smp_cores_allowed; + } + + /* Move to next core. */ + j++; + } +#endif +#endif +#endif +#endif +#endif +#endif + return(possible_cores); +} + + +static INLINE_DECLARE UINT _tx_thread_smp_lowest_priority_get(void) +{ + +#if TX_THREAD_SMP_MAX_CORES > 6 +UINT j; +#endif +TX_THREAD *thread_ptr; +UINT lowest_priority; + + lowest_priority = ((UINT) 0); + thread_ptr = _tx_thread_execute_ptr[0]; + if (thread_ptr != TX_NULL) + { + if (thread_ptr -> tx_thread_priority > lowest_priority) + { + lowest_priority = thread_ptr -> tx_thread_priority; + } + } +#if TX_THREAD_SMP_MAX_CORES > 1 + thread_ptr = _tx_thread_execute_ptr[1]; + if (thread_ptr != TX_NULL) + { + if (thread_ptr -> tx_thread_priority > lowest_priority) + { + lowest_priority = thread_ptr -> tx_thread_priority; + } + } +#if TX_THREAD_SMP_MAX_CORES > 2 + thread_ptr = _tx_thread_execute_ptr[2]; + if (thread_ptr != TX_NULL) + { + if (thread_ptr -> tx_thread_priority > lowest_priority) + { + lowest_priority = thread_ptr -> tx_thread_priority; + } + } +#if TX_THREAD_SMP_MAX_CORES > 3 + thread_ptr = _tx_thread_execute_ptr[3]; + if (thread_ptr != TX_NULL) + { + if (thread_ptr -> tx_thread_priority > lowest_priority) + { + lowest_priority = thread_ptr -> tx_thread_priority; + } + } +#if TX_THREAD_SMP_MAX_CORES > 4 + thread_ptr = _tx_thread_execute_ptr[4]; + if (thread_ptr != TX_NULL) + { + if (thread_ptr -> tx_thread_priority > lowest_priority) + { + lowest_priority = thread_ptr -> tx_thread_priority; + } + } +#if TX_THREAD_SMP_MAX_CORES > 5 + thread_ptr = _tx_thread_execute_ptr[5]; + if (thread_ptr != TX_NULL) + { + if (thread_ptr -> tx_thread_priority > lowest_priority) + { + lowest_priority = thread_ptr -> tx_thread_priority; + } + } +#if TX_THREAD_SMP_MAX_CORES > 6 + + /* Loop to setup the remainder of the schedule list. */ + j = ((UINT) 6); + +#ifndef TX_THREAD_SMP_DYNAMIC_CORE_MAX + while (j < ((UINT) TX_THREAD_SMP_MAX_CORES)) +#else + + while (j < _tx_thread_smp_max_cores) +#endif + { + + /* Determine if this core has a thread scheduled. */ + thread_ptr = _tx_thread_execute_ptr[j]; + if (thread_ptr != TX_NULL) + { + + /* Is this the new lowest priority? */ + if (thread_ptr -> tx_thread_priority > lowest_priority) + { + lowest_priority = thread_ptr -> tx_thread_priority; + } + } + + /* Move to next core. */ + j++; + } +#endif +#endif +#endif +#endif +#endif +#endif + return(lowest_priority); +} + + +static INLINE_DECLARE UINT _tx_thread_smp_remap_solution_find(TX_THREAD *schedule_thread, ULONG available_cores, ULONG thread_possible_cores, ULONG test_possible_cores) +{ + +UINT core; +UINT previous_core; +ULONG test_cores; +ULONG last_thread_cores; +UINT queue_first, queue_last; +UINT core_queue[TX_THREAD_SMP_MAX_CORES-1]; +TX_THREAD *thread_ptr; +TX_THREAD *last_thread; +TX_THREAD *thread_remap_list[TX_THREAD_SMP_MAX_CORES]; + + + /* Clear the last thread cores in the search. */ + last_thread_cores = ((ULONG) 0); + + /* Set the last thread pointer to NULL. */ + last_thread = TX_NULL; + + /* Setup the core queue indices. */ + queue_first = ((UINT) 0); + queue_last = ((UINT) 0); + + /* Build a list of possible cores for this thread to execute on, starting + with the previously mapped core. */ + core = schedule_thread -> tx_thread_smp_core_mapped; + if ((thread_possible_cores & (((ULONG) 1) << core)) != ((ULONG) 0)) + { + + /* Remember this potential mapping. */ + thread_remap_list[core] = schedule_thread; + core_queue[queue_last] = core; + + /* Move to next slot. */ + queue_last++; + + /* Clear this core. */ + thread_possible_cores = thread_possible_cores & ~(((ULONG) 1) << core); + } + + /* Loop to add additional possible cores. */ + while (thread_possible_cores != ((ULONG) 0)) + { + + /* Determine the first possible core. */ + test_cores = thread_possible_cores; + TX_LOWEST_SET_BIT_CALCULATE(test_cores, core) + + /* Clear this core. */ + thread_possible_cores = thread_possible_cores & ~(((ULONG) 1) << core); + + /* Remember this potential mapping. */ + thread_remap_list[core] = schedule_thread; + core_queue[queue_last] = core; + + /* Move to next slot. */ + queue_last++; + } + + /* Loop to evaluate the potential thread mappings, against what is already mapped. */ + do + { + + /* Pickup the next entry. */ + core = core_queue[queue_first]; + + /* Move to next slot. */ + queue_first++; + + /* Retrieve the thread from the current mapping. */ + thread_ptr = _tx_thread_smp_schedule_list[core]; + + /* Determine if there is a thread currently mapped to this core. */ + if (thread_ptr != TX_NULL) + { + + /* Determine the cores available for this thread. */ + thread_possible_cores = thread_ptr -> tx_thread_smp_cores_allowed; + thread_possible_cores = test_possible_cores & thread_possible_cores; + + /* Are there any possible cores for this thread? */ + if (thread_possible_cores != ((ULONG) 0)) + { + + /* Determine if there are cores available for this thread. */ + if ((thread_possible_cores & available_cores) != ((ULONG) 0)) + { + + /* Yes, remember the final thread and cores that are valid for this thread. */ + last_thread_cores = thread_possible_cores & available_cores; + last_thread = thread_ptr; + + /* We are done - get out of the loop! */ + break; + } + else + { + + /* Remove cores that will be added to the list. */ + test_possible_cores = test_possible_cores & ~(thread_possible_cores); + + /* Loop to add this thread to the potential mapping list. */ + do + { + + /* Calculate the core. */ + test_cores = thread_possible_cores; + TX_LOWEST_SET_BIT_CALCULATE(test_cores, core) + + /* Clear this core. */ + thread_possible_cores = thread_possible_cores & ~(((ULONG) 1) << core); + + /* Remember this thread for remapping. */ + thread_remap_list[core] = thread_ptr; + + /* Remember this core. */ + core_queue[queue_last] = core; + + /* Move to next slot. */ + queue_last++; + + } while (thread_possible_cores != ((ULONG) 0)); + } + } + } + } while (queue_first != queue_last); + + /* Was a remapping solution found? */ + if (last_thread != TX_NULL) + { + + /* Pickup the core of the last thread to remap. */ + core = last_thread -> tx_thread_smp_core_mapped; + + /* Pickup the thread from the remapping list. */ + thread_ptr = thread_remap_list[core]; + + /* Loop until we arrive at the thread we have been trying to map. */ + while (thread_ptr != schedule_thread) + { + + /* Move this thread in the schedule list. */ + _tx_thread_smp_schedule_list[core] = thread_ptr; + + /* Remember the previous core. */ + previous_core = core; + + /* Pickup the core of thread to remap. */ + core = thread_ptr -> tx_thread_smp_core_mapped; + + /* Save the new core mapping for this thread. */ + thread_ptr -> tx_thread_smp_core_mapped = previous_core; + + /* Move the next thread. */ + thread_ptr = thread_remap_list[core]; + } + + /* Save the remaining thread in the updated schedule list. */ + _tx_thread_smp_schedule_list[core] = thread_ptr; + + /* Update this thread's core mapping. */ + thread_ptr -> tx_thread_smp_core_mapped = core; + + /* Finally, setup the last thread in the remapping solution. */ + test_cores = last_thread_cores; + TX_LOWEST_SET_BIT_CALCULATE(test_cores, core) + + /* Setup the last thread. */ + _tx_thread_smp_schedule_list[core] = last_thread; + + /* Remember the core mapping for this thread. */ + last_thread -> tx_thread_smp_core_mapped = core; + } + else + { + + /* Set core to the maximum value in order to signal a remapping solution was not found. */ + core = ((UINT) TX_THREAD_SMP_MAX_CORES); + } + + /* Return core to the caller. */ + return(core); +} + + +static INLINE_DECLARE ULONG _tx_thread_smp_preemptable_threads_get(UINT priority, TX_THREAD *possible_preemption_list[]) +{ + +UINT i, j, k; +TX_THREAD *thread_ptr; +TX_THREAD *next_thread; +TX_THREAD *search_thread; +TX_THREAD *list_head; +ULONG possible_cores = ((ULONG) 0); + + + /* Clear the possible preemption list. */ + possible_preemption_list[0] = TX_NULL; +#if TX_THREAD_SMP_MAX_CORES > 1 + possible_preemption_list[1] = TX_NULL; +#if TX_THREAD_SMP_MAX_CORES > 2 + possible_preemption_list[2] = TX_NULL; +#if TX_THREAD_SMP_MAX_CORES > 3 + possible_preemption_list[3] = TX_NULL; +#if TX_THREAD_SMP_MAX_CORES > 4 + possible_preemption_list[4] = TX_NULL; +#if TX_THREAD_SMP_MAX_CORES > 5 + possible_preemption_list[5] = TX_NULL; +#if TX_THREAD_SMP_MAX_CORES > 6 + + /* Loop to clear the remainder of the possible preemption list. */ + j = ((UINT) 6); + +#ifndef TX_THREAD_SMP_DYNAMIC_CORE_MAX + + while (j < ((UINT) TX_THREAD_SMP_MAX_CORES)) +#else + + while (j < _tx_thread_smp_max_cores) +#endif + { + + /* Clear entry in possible preemption list. */ + possible_preemption_list[j] = TX_NULL; + + /* Move to next core. */ + j++; + } +#endif +#endif +#endif +#endif +#endif +#endif + + /* Loop to build a list of threads of less priority. */ + i = ((UINT) 0); + j = ((UINT) 0); +#ifndef TX_THREAD_SMP_DYNAMIC_CORE_MAX + while (i < ((UINT) TX_THREAD_SMP_MAX_CORES)) +#else + + while (i < _tx_thread_smp_max_cores) +#endif + { + + /* Pickup the currently mapped thread. */ + thread_ptr = _tx_thread_execute_ptr[i]; + + /* Is there a thread scheduled for this core? */ + if (thread_ptr != TX_NULL) + { + + /* Update the possible cores bit map. */ + possible_cores = possible_cores | thread_ptr -> tx_thread_smp_cores_allowed; + + /* Can this thread be preempted? */ + if (priority < thread_ptr -> tx_thread_priority) + { + + /* Thread that can be added to the preemption possible list. */ + + /* Yes, this scheduled thread is lower priority, so add it to the preemption possible list. */ + possible_preemption_list[j] = thread_ptr; + + /* Move to next entry in preemption possible list. */ + j++; + } + } + + /* Move to next core. */ + i++; + } + + /* Check to see if there are more than 2 threads that can be preempted. */ + if (j > ((UINT) 1)) + { + + /* Yes, loop through the preemption possible list and sort by priority. */ + i = ((UINT) 0); + do + { + + /* Pickup preemptable thread. */ + thread_ptr = possible_preemption_list[i]; + + /* Initialize the search index. */ + k = i + ((UINT) 1); + + /* Loop to get the lowest priority thread at the front of the list. */ + while (k < j) + { + + /* Pickup the next thread to evaluate. */ + next_thread = possible_preemption_list[k]; + + /* Is this thread lower priority? */ + if (next_thread -> tx_thread_priority > thread_ptr -> tx_thread_priority) + { + + /* Yes, swap the threads. */ + possible_preemption_list[i] = next_thread; + possible_preemption_list[k] = thread_ptr; + thread_ptr = next_thread; + } + else + { + + /* Compare the thread priorities. */ + if (next_thread -> tx_thread_priority == thread_ptr -> tx_thread_priority) + { + + /* Equal priority threads... see which is in the ready list first. */ + search_thread = thread_ptr -> tx_thread_ready_next; + + /* Pickup the list head. */ + list_head = _tx_thread_priority_list[thread_ptr -> tx_thread_priority]; + + /* Now loop to see if the next thread is after the current thread preemption. */ + while (search_thread != list_head) + { + + /* Have we found the next thread? */ + if (search_thread == next_thread) + { + + /* Yes, swap the threads. */ + possible_preemption_list[i] = next_thread; + possible_preemption_list[k] = thread_ptr; + thread_ptr = next_thread; + break; + } + + /* Move to the next thread. */ + search_thread = search_thread -> tx_thread_ready_next; + } + } + + /* Move to examine the next possible preemptable thread. */ + k++; + } + } + + /* We have found the lowest priority thread to preempt, now find the next lowest. */ + i++; + } + while (i < (j-((UINT) 1))); + } + + /* Return the possible cores. */ + return(possible_cores); +} + +static INLINE_DECLARE VOID _tx_thread_smp_simple_priority_change(TX_THREAD *thread_ptr, UINT new_priority) +{ + +UINT priority; +ULONG priority_bit; +TX_THREAD *head_ptr; +TX_THREAD *tail_ptr; +#if TX_MAX_PRIORITIES > 32 +UINT map_index; +#endif + + /* Pickup the priority. */ + priority = thread_ptr -> tx_thread_priority; + + /* Determine if there are other threads at this priority that are + ready. */ + if (thread_ptr -> tx_thread_ready_next != thread_ptr) + { + + /* Yes, there are other threads at this priority ready. */ + + /* Just remove this thread from the priority list. */ + (thread_ptr -> tx_thread_ready_next) -> tx_thread_ready_previous = thread_ptr -> tx_thread_ready_previous; + (thread_ptr -> tx_thread_ready_previous) -> tx_thread_ready_next = thread_ptr -> tx_thread_ready_next; + + /* Determine if this is the head of the priority list. */ + if (_tx_thread_priority_list[priority] == thread_ptr) + { + + /* Update the head pointer of this priority list. */ + _tx_thread_priority_list[priority] = thread_ptr -> tx_thread_ready_next; + } + } + else + { + + /* This is the only thread at this priority ready to run. Set the head + pointer to NULL. */ + _tx_thread_priority_list[priority] = TX_NULL; + +#if TX_MAX_PRIORITIES > 32 + + /* Calculate the index into the bit map array. */ + map_index = priority/((UINT) 32); +#endif + + /* Clear this priority bit in the ready priority bit map. */ + TX_MOD32_BIT_SET(priority, priority_bit) + _tx_thread_priority_maps[MAP_INDEX] = _tx_thread_priority_maps[MAP_INDEX] & (~(priority_bit)); + +#if TX_MAX_PRIORITIES > 32 + + /* Determine if there are any other bits set in this priority map. */ + if (_tx_thread_priority_maps[MAP_INDEX] == ((ULONG) 0)) + { + + /* No, clear the active bit to signify this priority map has nothing set. */ + TX_DIV32_BIT_SET(priority, priority_bit) + _tx_thread_priority_map_active = _tx_thread_priority_map_active & (~(priority_bit)); + } +#endif + } + + /* Determine if the actual thread priority should be setup, which is the + case if the new priority is higher than the priority inheritance. */ + if (new_priority < thread_ptr -> tx_thread_inherit_priority) + { + + /* Change thread priority to the new user's priority. */ + thread_ptr -> tx_thread_priority = new_priority; + thread_ptr -> tx_thread_preempt_threshold = new_priority; + } + else + { + + /* Change thread priority to the priority inheritance. */ + thread_ptr -> tx_thread_priority = thread_ptr -> tx_thread_inherit_priority; + thread_ptr -> tx_thread_preempt_threshold = thread_ptr -> tx_thread_inherit_priority; + } + + /* Now, place the thread at the new priority level. */ + + /* Determine if there are other threads at this priority that are + ready. */ + head_ptr = _tx_thread_priority_list[new_priority]; + if (head_ptr != TX_NULL) + { + + /* Yes, there are other threads at this priority already ready. */ + + /* Just add this thread to the priority list. */ + tail_ptr = head_ptr -> tx_thread_ready_previous; + tail_ptr -> tx_thread_ready_next = thread_ptr; + head_ptr -> tx_thread_ready_previous = thread_ptr; + thread_ptr -> tx_thread_ready_previous = tail_ptr; + thread_ptr -> tx_thread_ready_next = head_ptr; + } + else + { + + /* First thread at this priority ready. Add to the front of the list. */ + _tx_thread_priority_list[new_priority] = thread_ptr; + thread_ptr -> tx_thread_ready_next = thread_ptr; + thread_ptr -> tx_thread_ready_previous = thread_ptr; + +#if TX_MAX_PRIORITIES > 32 + + /* Calculate the index into the bit map array. */ + map_index = new_priority/((UINT) 32); + + /* Set the active bit to remember that the priority map has something set. */ + TX_DIV32_BIT_SET(new_priority, priority_bit) + _tx_thread_priority_map_active = _tx_thread_priority_map_active | priority_bit; +#endif + + /* Or in the thread's priority bit. */ + TX_MOD32_BIT_SET(new_priority, priority_bit) + _tx_thread_priority_maps[MAP_INDEX] = _tx_thread_priority_maps[MAP_INDEX] | priority_bit; + } +} +#else + +/* In-line was disabled. All of the above helper fuctions must be defined as actual functions. */ + +UINT _tx_thread_lowest_set_bit_calculate(ULONG map); +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = _tx_thread_lowest_set_bit_calculate((m)); + +UINT _tx_thread_smp_next_priority_find(UINT priority); +VOID _tx_thread_smp_schedule_list_clear(void); +VOID _tx_thread_smp_execute_list_clear(void); +VOID _tx_thread_smp_schedule_list_setup(void); + +#ifdef TX_THREAD_SMP_INTER_CORE_INTERRUPT +VOID _tx_thread_smp_core_interrupt(TX_THREAD *thread_ptr, UINT current_core, UINT target_core); +#else +/* Define to whitespace. */ +#define _tx_thread_smp_core_interrupt(a,b,c) +#endif + +#ifdef TX_THREAD_SMP_WAKEUP_LOGIC +VOID _tx_thread_smp_core_wakeup(UINT current_core, UINT target_core); +#else +/* Define to whitespace. */ +#define _tx_thread_smp_core_wakeup(a,b) +#endif + +VOID _tx_thread_smp_execute_list_setup(UINT core_index); +ULONG _tx_thread_smp_available_cores_get(void); +ULONG _tx_thread_smp_possible_cores_get(void); +UINT _tx_thread_smp_lowest_priority_get(void); +UINT _tx_thread_smp_remap_solution_find(TX_THREAD *schedule_thread, ULONG available_cores, ULONG thread_possible_cores, ULONG test_possible_cores); +ULONG _tx_thread_smp_preemptable_threads_get(UINT priority, TX_THREAD *possible_preemption_list[]); +VOID _tx_thread_smp_simple_priority_change(TX_THREAD *thread_ptr, UINT new_priority); + +#endif + + +#endif + +#endif + diff --git a/common_smp/inc/tx_timer.h b/common_smp/inc/tx_timer.h new file mode 100644 index 00000000..eb531921 --- /dev/null +++ b/common_smp/inc/tx_timer.h @@ -0,0 +1,214 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* tx_timer.h PORTABLE SMP */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the ThreadX timer management component, including */ +/* data types and external references. It is assumed that tx_api.h */ +/* and tx_port.h have already been included. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_TIMER_H +#define TX_TIMER_H + + +/* Define timer management specific data definitions. */ + +#define TX_TIMER_ID ((ULONG) 0x4154494D) +#define TX_TIMER_ENTRIES ((ULONG) 32) + + +/* Define internal timer management function prototypes. */ + +VOID _tx_timer_expiration_process(VOID); +VOID _tx_timer_initialize(VOID); +VOID _tx_timer_system_activate(TX_TIMER_INTERNAL *timer_ptr); +VOID _tx_timer_system_deactivate(TX_TIMER_INTERNAL *timer_ptr); +VOID _tx_timer_thread_entry(ULONG timer_thread_input); + + +/* Timer management component data declarations follow. */ + +/* Determine if the initialization function of this component is including + this file. If so, make the data definitions really happen. Otherwise, + make them extern so other functions in the component can access them. */ + +#define TIMER_DECLARE extern + + +/* Define the system clock value that is continually incremented by the + periodic timer interrupt processing. */ + +TIMER_DECLARE volatile ULONG _tx_timer_system_clock; + + +/* Define the current time slice value. If non-zero, a time-slice is active. + Otherwise, the time_slice is not active. There is one of these entries + per core. */ + +TIMER_DECLARE ULONG _tx_timer_time_slice[TX_THREAD_SMP_MAX_CORES]; + + +/* Define count to detect when timer interrupt is active. */ + +TIMER_DECLARE ULONG _tx_timer_interrupt_active; + + +/* Define the time-slice expiration flag. This is used to indicate that a time-slice + has happened. */ + +TIMER_DECLARE UINT _tx_timer_expired_time_slice; + + +/* Define the thread and application timer entry list. This list provides a direct access + method for insertion of times less than TX_TIMER_ENTRIES. */ + +TIMER_DECLARE TX_TIMER_INTERNAL *_tx_timer_list[TX_TIMER_ENTRIES]; + + +/* Define the boundary pointers to the list. These are setup to easily manage + wrapping the list. */ + +TIMER_DECLARE TX_TIMER_INTERNAL **_tx_timer_list_start; +TIMER_DECLARE TX_TIMER_INTERNAL **_tx_timer_list_end; + + +/* Define the current timer pointer in the list. This pointer is moved sequentially + through the timer list by the timer interrupt handler. */ + +TIMER_DECLARE TX_TIMER_INTERNAL **_tx_timer_current_ptr; + + +/* Define the timer expiration flag. This is used to indicate that a timer + has expired. */ + +TIMER_DECLARE UINT _tx_timer_expired; + + +/* Define the created timer list head pointer. */ + +TIMER_DECLARE TX_TIMER *_tx_timer_created_ptr; + + +/* Define the created timer count. */ + +TIMER_DECLARE ULONG _tx_timer_created_count; + + +/* Define the pointer to the timer that has expired and is being processed. */ + +TIMER_DECLARE TX_TIMER_INTERNAL *_tx_timer_expired_timer_ptr; + + +#ifndef TX_TIMER_PROCESS_IN_ISR + +/* Define the timer thread's control block. */ + +TIMER_DECLARE TX_THREAD _tx_timer_thread; + + +/* Define the variable that holds the timer thread's starting stack address. */ + +TIMER_DECLARE VOID *_tx_timer_stack_start; + + +/* Define the variable that holds the timer thread's stack size. */ + +TIMER_DECLARE ULONG _tx_timer_stack_size; + + +/* Define the variable that holds the timer thread's priority. */ + +TIMER_DECLARE UINT _tx_timer_priority; + +/* Define the system timer thread's stack. The default size is defined + in tx_port.h. */ + +TIMER_DECLARE ULONG _tx_timer_thread_stack_area[(((UINT) TX_TIMER_THREAD_STACK_SIZE)+((sizeof(ULONG)) - ((UINT) 1)))/sizeof(ULONG)]; + +#else + + +/* Define the busy flag that will prevent nested timer ISR processing. */ + +TIMER_DECLARE UINT _tx_timer_processing_active; + +#endif + +#ifdef TX_TIMER_ENABLE_PERFORMANCE_INFO + +/* Define the total number of timer activations. */ + +TIMER_DECLARE ULONG _tx_timer_performance_activate_count; + + +/* Define the total number of timer reactivations. */ + +TIMER_DECLARE ULONG _tx_timer_performance_reactivate_count; + + +/* Define the total number of timer deactivations. */ + +TIMER_DECLARE ULONG _tx_timer_performance_deactivate_count; + + +/* Define the total number of timer expirations. */ + +TIMER_DECLARE ULONG _tx_timer_performance_expiration_count; + + +/* Define the total number of timer expiration adjustments. These are required + if the expiration time is greater than the size of the timer list. In such + cases, the timer is placed at the end of the list and then reactivated + as many times as necessary to finally achieve the resulting timeout. */ + +TIMER_DECLARE ULONG _tx_timer_performance__expiration_adjust_count; + +#endif + +/* Define default post timer delete macro to whitespace, if it hasn't been defined previously (typically in tx_port.h). */ + +#ifndef TX_TIMER_DELETE_PORT_COMPLETION +#define TX_TIMER_DELETE_PORT_COMPLETION(t) +#endif + + +#endif + diff --git a/common_smp/inc/tx_trace.h b/common_smp/inc/tx_trace.h new file mode 100644 index 00000000..8baf85cb --- /dev/null +++ b/common_smp/inc/tx_trace.h @@ -0,0 +1,561 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Trace */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* tx_trace.h PORTABLE SMP */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the ThreadX trace component, including constants */ +/* and structure definitions as well as external references. It is */ +/* assumed that tx_api.h and tx_port.h have already been included. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#ifndef TX_TRACE_H +#define TX_TRACE_H + + +/* Determine if tracing is enabled. If not, simply define the in-line trace + macros to whitespace. */ + +#ifndef TX_ENABLE_EVENT_TRACE +#define TX_TRACE_INITIALIZE +#define TX_TRACE_OBJECT_REGISTER(t,p,n,a,b) +#define TX_TRACE_OBJECT_UNREGISTER(o) +#define TX_TRACE_IN_LINE_INSERT(i,a,b,c,d,f) +#else + +/* Event tracing is enabled. */ + +/* Ensure that the thread component information is included. */ + +#include "tx_thread.h" + + +/* Define trace port-specfic extension to white space if it isn't defined + already. */ + +#ifndef TX_TRACE_PORT_EXTENSION +#define TX_TRACE_PORT_EXTENSION +#endif + + +/* Define the default clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the ID showing the event trace buffer is valid. */ + +#define TX_TRACE_VALID 0x54585442UL + + +/* ThreadX Trace Description. The ThreadX Trace feature is designed to capture + events in real-time in a circular event buffer. This buffer may be analyzed by other + tools. The high-level format of the Trace structure is: + + [Trace Control Header ] + [Trace Object Registry - Entry 0 ] + ... + [Trace Object Registry - Entry "n" ] + [Trace Buffer - Entry 0 ] + ... + [Trace Buffer - Entry "n" ] + +*/ + + +/* Trace Control Header. The Trace Control Header contains information that + defines the format of the Trace Object Registry as well as the location and + current entry of the Trace Buffer itself. The high-level format of the + Trace Control Header is: + + Entry Size Description + + [Trace ID] 4 This 4-byte field contains the ThreadX Trace + Identification. If the trace buffer is valid, the + contents are 0x54585442 (TXTB). Since it is written as + a 32-bit unsigned word, this value is also used to + determine if the event trace information is in + little or big endian format. + [Timer Valid Mask] 4 Mask of valid bits in the 32-bit time stamp. This + enables use of 32, 24, 16, or event 8-bit timers. + If the time source is 32-bits, the mask is + 0xFFFFFFFF. If the time source is 16-bits, the + mask is 0x0000FFFF. + [Trace Base Address] 4 The base address for all trace pointer. Subtracting + the pointer and this address will yield the proper + offset into the trace buffer. + [Trace Object Registry Start Pointer] 4 Pointer to the start of Trace Object Registry + [Reserved] 2 Reserved two bytes - should be 0x0000 + [Trace Object Object Name Size] 2 Number of bytes in object name + [Trace Object Registry End Pointer] 4 Pointer to the end of Trace Object Registry + [Trace Buffer Start Pointer] 4 Pointer to the start of the Trace Buffer Area + [Trace Buffer End Pointer] 4 Pointer to the end of the Trace Buffer Area + [Trace Buffer Current Pointer] 4 Pointer to the oldest entry in the Trace Buffer. + This entry will be overwritten on the next event and + incremented to the next event (wrapping to the top + if the buffer end pointer is exceeded). + [Reserved] 4 Reserved 4 bytes, should be 0xAAAAAAAA + [Reserved] 4 Reserved 4 bytes, should be 0xBBBBBBBB + [Reserved] 4 Reserved 4 bytes, should be 0xCCCCCCCC +*/ + + +/* Define the Trace Control Header. */ + +typedef struct TX_TRACE_HEADER_STRUCT +{ + + ULONG tx_trace_header_id; + ULONG tx_trace_header_timer_valid_mask; + ULONG tx_trace_header_trace_base_address; + ULONG tx_trace_header_registry_start_pointer; + USHORT tx_trace_header_reserved1; + USHORT tx_trace_header_object_name_size; + ULONG tx_trace_header_registry_end_pointer; + ULONG tx_trace_header_buffer_start_pointer; + ULONG tx_trace_header_buffer_end_pointer; + ULONG tx_trace_header_buffer_current_pointer; + ULONG tx_trace_header_reserved2; + ULONG tx_trace_header_reserved3; + ULONG tx_trace_header_reserved4; +} TX_TRACE_HEADER; + + +/* Trace Object Registry. The Trace Object Registry is used to map the object pointer in the trace buffer to + the application's name for the object (defined during object creation in ThreadX). */ + +#ifndef TX_TRACE_OBJECT_REGISTRY_NAME +#define TX_TRACE_OBJECT_REGISTRY_NAME 32 +#endif + + +/* Define the object name types as well as the contents of any additional parameters that might be useful in + trace analysis. */ + +#define TX_TRACE_OBJECT_TYPE_NOT_VALID ((UCHAR) 0) /* Object is not valid */ +#define TX_TRACE_OBJECT_TYPE_THREAD ((UCHAR) 1) /* P1 = stack start address, P2 = stack size */ +#define TX_TRACE_OBJECT_TYPE_TIMER ((UCHAR) 2) /* P1 = initial ticks, P2 = reschedule ticks */ +#define TX_TRACE_OBJECT_TYPE_QUEUE ((UCHAR) 3) /* P1 = queue size, P2 = message size */ +#define TX_TRACE_OBJECT_TYPE_SEMAPHORE ((UCHAR) 4) /* P1 = initial instances */ +#define TX_TRACE_OBJECT_TYPE_MUTEX ((UCHAR) 5) /* P1 = priority inheritance flag */ +#define TX_TRACE_OBJECT_TYPE_EVENT_FLAGS ((UCHAR) 6) /* none */ +#define TX_TRACE_OBJECT_TYPE_BLOCK_POOL ((UCHAR) 7) /* P1 = total blocks, P2 = block size */ +#define TX_TRACE_OBJECT_TYPE_BYTE_POOL ((UCHAR) 8) /* P1 = total bytes */ + + +typedef struct TX_TRACE_OBJECT_ENTRY_STRUCT +{ + + UCHAR tx_trace_object_entry_available; /* TX_TRUE -> available */ + UCHAR tx_trace_object_entry_type; /* Types defined above */ + UCHAR tx_trace_object_entry_reserved1; /* Should be zero - except for thread */ + UCHAR tx_trace_object_entry_reserved2; /* Should be zero - except for thread */ + ULONG tx_trace_object_entry_thread_pointer; /* ThreadX object pointer */ + ULONG tx_trace_object_entry_param_1; /* Parameter value defined */ + ULONG tx_trace_object_entry_param_2; /* according to type above */ + UCHAR tx_trace_object_entry_name[TX_TRACE_OBJECT_REGISTRY_NAME]; /* Object name */ +} TX_TRACE_OBJECT_ENTRY; + + +/* Trace Buffer Entry. The Trace Buffer Entry contains information about a particular + event in the system. The high-level format of the Trace Buffer Entry is: + + Entry Size Description + + [Thread Pointer] 4 This 4-byte field contains the pointer to the + ThreadX thread running that caused the event. + If this field is NULL, the entry hasn't been used + yet. If this field is 0xFFFFFFFF, the event occurred + from within an ISR. If this entry is 0xF0F0F0F0, the + event occurred during initialization. + [Thread Priority or 4 This 4-byte field contains the current thread pointer for interrupt + Current Thread events or the thread preemption-threshold/priority for thread events. + Preemption-Threshold/ + Priority] + [Event ID] 4 This 4-byte field contains the Event ID of the event. A value of + 0xFFFFFFFF indicates the event is invalid. All events are marked + as invalid during initialization. + [Time Stamp] 4 This 4-byte field contains the time stamp of the event. + [Information Field 1] 4 This 4-byte field contains the first 4-bytes of information + specific to the event. + [Information Field 2] 4 This 4-byte field contains the second 4-bytes of information + specific to the event. + [Information Field 3] 4 This 4-byte field contains the third 4-bytes of information + specific to the event. + [Information Field 4] 4 This 4-byte field contains the fourth 4-bytes of information + specific to the event. +*/ + +#define TX_TRACE_INVALID_EVENT 0xFFFFFFFFUL + + +/* Define ThreadX Trace Events, along with a brief description of the additional information fields, + where I1 -> Information Field 1, I2 -> Information Field 2, etc. */ + +/* Event numbers 0 through 4095 are reserved by Express Logic. Specific event assignments are: + + ThreadX events: 1-199 + FileX events: 200-299 + NetX events: 300-599 + USBX events: 600-999 + + User-defined event numbers start at 4096 and continue through 65535, as defined by the constants + TX_TRACE_USER_EVENT_START and TX_TRACE_USER_EVENT_END, respectively. User events should be based + on these constants in case the user event number assignment is changed in future releases. */ + +/* Define the basic ThreadX thread scheduling events first. */ + +#define TX_TRACE_THREAD_RESUME 1 /* I1 = thread ptr, I2 = previous_state, I3 = stack ptr, I4 = next thread */ +#define TX_TRACE_THREAD_SUSPEND 2 /* I1 = thread ptr, I2 = new_state, I3 = stack ptr I4 = next thread */ +#define TX_TRACE_ISR_ENTER 3 /* I1 = stack_ptr, I2 = ISR number, I3 = system state, I4 = preempt disable */ +#define TX_TRACE_ISR_EXIT 4 /* I1 = stack_ptr, I2 = ISR number, I3 = system state, I4 = preempt disable */ +#define TX_TRACE_TIME_SLICE 5 /* I1 = next thread ptr, I2 = system state, I3 = preempt disable, I4 = stack*/ +#define TX_TRACE_RUNNING 6 /* None */ + + +/* Define the rest of the ThreadX system events. */ + +#define TX_TRACE_BLOCK_ALLOCATE 10 /* I1 = pool ptr, I2 = memory ptr, I3 = wait option, I4 = remaining blocks */ +#define TX_TRACE_BLOCK_POOL_CREATE 11 /* I1 = pool ptr, I2 = pool_start, I3 = total blocks, I4 = block size */ +#define TX_TRACE_BLOCK_POOL_DELETE 12 /* I1 = pool ptr, I2 = stack ptr */ +#define TX_TRACE_BLOCK_POOL_INFO_GET 13 /* I1 = pool ptr */ +#define TX_TRACE_BLOCK_POOL_PERFORMANCE_INFO_GET 14 /* I1 = pool ptr */ +#define TX_TRACE_BLOCK_POOL__PERFORMANCE_SYSTEM_INFO_GET 15 /* None */ +#define TX_TRACE_BLOCK_POOL_PRIORITIZE 16 /* I1 = pool ptr, I2 = suspended count, I3 = stack ptr */ +#define TX_TRACE_BLOCK_RELEASE 17 /* I1 = pool ptr, I2 = memory ptr, I3 = suspended, I4 = stack ptr */ +#define TX_TRACE_BYTE_ALLOCATE 20 /* I1 = pool ptr, I2 = memory ptr, I3 = size requested, I4 = wait option */ +#define TX_TRACE_BYTE_POOL_CREATE 21 /* I1 = pool ptr, I2 = start ptr, I3 = pool size, I4 = stack ptr */ +#define TX_TRACE_BYTE_POOL_DELETE 22 /* I1 = pool ptr, I2 = stack ptr */ +#define TX_TRACE_BYTE_POOL_INFO_GET 23 /* I1 = pool ptr */ +#define TX_TRACE_BYTE_POOL_PERFORMANCE_INFO_GET 24 /* I1 = pool ptr */ +#define TX_TRACE_BYTE_POOL__PERFORMANCE_SYSTEM_INFO_GET 25 /* None */ +#define TX_TRACE_BYTE_POOL_PRIORITIZE 26 /* I1 = pool ptr, I2 = suspended count, I3 = stack ptr */ +#define TX_TRACE_BYTE_RELEASE 27 /* I1 = pool ptr, I2 = memory ptr, I3 = suspended, I4 = available bytes */ +#define TX_TRACE_EVENT_FLAGS_CREATE 30 /* I1 = group ptr, I2 = stack ptr */ +#define TX_TRACE_EVENT_FLAGS_DELETE 31 /* I1 = group ptr, I2 = stack ptr */ +#define TX_TRACE_EVENT_FLAGS_GET 32 /* I1 = group ptr, I2 = requested flags, I3 = current flags, I4 = get option*/ +#define TX_TRACE_EVENT_FLAGS_INFO_GET 33 /* I1 = group ptr */ +#define TX_TRACE_EVENT_FLAGS_PERFORMANCE_INFO_GET 34 /* I1 = group ptr */ +#define TX_TRACE_EVENT_FLAGS__PERFORMANCE_SYSTEM_INFO_GET 35 /* None */ +#define TX_TRACE_EVENT_FLAGS_SET 36 /* I1 = group ptr, I2 = flags to set, I3 = set option, I4= suspended count */ +#define TX_TRACE_EVENT_FLAGS_SET_NOTIFY 37 /* I1 = group ptr */ +#define TX_TRACE_INTERRUPT_CONTROL 40 /* I1 = new interrupt posture, I2 = stack ptr */ +#define TX_TRACE_MUTEX_CREATE 50 /* I1 = mutex ptr, I2 = inheritance, I3 = stack ptr */ +#define TX_TRACE_MUTEX_DELETE 51 /* I1 = mutex ptr, I2 = stack ptr */ +#define TX_TRACE_MUTEX_GET 52 /* I1 = mutex ptr, I2 = wait option, I3 = owning thread, I4 = own count */ +#define TX_TRACE_MUTEX_INFO_GET 53 /* I1 = mutex ptr */ +#define TX_TRACE_MUTEX_PERFORMANCE_INFO_GET 54 /* I1 = mutex ptr */ +#define TX_TRACE_MUTEX_PERFORMANCE_SYSTEM_INFO_GET 55 /* None */ +#define TX_TRACE_MUTEX_PRIORITIZE 56 /* I1 = mutex ptr, I2 = suspended count, I3 = stack ptr */ +#define TX_TRACE_MUTEX_PUT 57 /* I1 = mutex ptr, I2 = owning thread, I3 = own count, I4 = stack ptr */ +#define TX_TRACE_QUEUE_CREATE 60 /* I1 = queue ptr, I2 = message size, I3 = queue start, I4 = queue size */ +#define TX_TRACE_QUEUE_DELETE 61 /* I1 = queue ptr, I2 = stack ptr */ +#define TX_TRACE_QUEUE_FLUSH 62 /* I1 = queue ptr, I2 = stack ptr */ +#define TX_TRACE_QUEUE_FRONT_SEND 63 /* I1 = queue ptr, I2 = source ptr, I3 = wait option, I4 = enqueued */ +#define TX_TRACE_QUEUE_INFO_GET 64 /* I1 = queue ptr */ +#define TX_TRACE_QUEUE_PERFORMANCE_INFO_GET 65 /* I1 = queue ptr */ +#define TX_TRACE_QUEUE_PERFORMANCE_SYSTEM_INFO_GET 66 /* None */ +#define TX_TRACE_QUEUE_PRIORITIZE 67 /* I1 = queue ptr, I2 = suspended count, I3 = stack ptr */ +#define TX_TRACE_QUEUE_RECEIVE 68 /* I1 = queue ptr, I2 = destination ptr, I3 = wait option, I4 = enqueued */ +#define TX_TRACE_QUEUE_SEND 69 /* I1 = queue ptr, I2 = source ptr, I3 = wait option, I4 = enqueued */ +#define TX_TRACE_QUEUE_SEND_NOTIFY 70 /* I1 = queue ptr */ +#define TX_TRACE_SEMAPHORE_CEILING_PUT 80 /* I1 = semaphore ptr, I2 = current count, I3 = suspended count,I4 =ceiling */ +#define TX_TRACE_SEMAPHORE_CREATE 81 /* I1 = semaphore ptr, I2 = initial count, I3 = stack ptr */ +#define TX_TRACE_SEMAPHORE_DELETE 82 /* I1 = semaphore ptr, I2 = stack ptr */ +#define TX_TRACE_SEMAPHORE_GET 83 /* I1 = semaphore ptr, I2 = wait option, I3 = current count, I4 = stack ptr */ +#define TX_TRACE_SEMAPHORE_INFO_GET 84 /* I1 = semaphore ptr */ +#define TX_TRACE_SEMAPHORE_PERFORMANCE_INFO_GET 85 /* I1 = semaphore ptr */ +#define TX_TRACE_SEMAPHORE__PERFORMANCE_SYSTEM_INFO_GET 86 /* None */ +#define TX_TRACE_SEMAPHORE_PRIORITIZE 87 /* I1 = semaphore ptr, I2 = suspended count, I2 = stack ptr */ +#define TX_TRACE_SEMAPHORE_PUT 88 /* I1 = semaphore ptr, I2 = current count, I3 = suspended count,I4=stack ptr*/ +#define TX_TRACE_SEMAPHORE_PUT_NOTIFY 89 /* I1 = semaphore ptr */ +#define TX_TRACE_THREAD_CREATE 100 /* I1 = thread ptr, I2 = priority, I3 = stack ptr, I4 = stack_size */ +#define TX_TRACE_THREAD_DELETE 101 /* I1 = thread ptr, I2 = stack ptr */ +#define TX_TRACE_THREAD_ENTRY_EXIT_NOTIFY 102 /* I1 = thread ptr, I2 = thread state, I3 = stack ptr */ +#define TX_TRACE_THREAD_IDENTIFY 103 /* None */ +#define TX_TRACE_THREAD_INFO_GET 104 /* I1 = thread ptr, I2 = thread state */ +#define TX_TRACE_THREAD_PERFORMANCE_INFO_GET 105 /* I1 = thread ptr, I2 = thread state */ +#define TX_TRACE_THREAD_PERFORMANCE_SYSTEM_INFO_GET 106 /* None */ +#define TX_TRACE_THREAD_PREEMPTION_CHANGE 107 /* I1 = thread ptr, I2 = new threshold, I3 = old threshold, I4 =thread state*/ +#define TX_TRACE_THREAD_PRIORITY_CHANGE 108 /* I1 = thread ptr, I2 = new priority, I3 = old priority, I4 = thread state */ +#define TX_TRACE_THREAD_RELINQUISH 109 /* I1 = stack ptr, I2 = next thread ptr */ +#define TX_TRACE_THREAD_RESET 110 /* I1 = thread ptr, I2 = thread state */ +#define TX_TRACE_THREAD_RESUME_API 111 /* I1 = thread ptr, I2 = thread state, I3 = stack ptr */ +#define TX_TRACE_THREAD_SLEEP 112 /* I1 = sleep value, I2 = thread state, I3 = stack ptr */ +#define TX_TRACE_THREAD_STACK_ERROR_NOTIFY 113 /* None */ +#define TX_TRACE_THREAD_SUSPEND_API 114 /* I1 = thread ptr, I2 = thread state, I3 = stack ptr */ +#define TX_TRACE_THREAD_TERMINATE 115 /* I1 = thread ptr, I2 = thread state, I3 = stack ptr */ +#define TX_TRACE_THREAD_TIME_SLICE_CHANGE 116 /* I1 = thread ptr, I2 = new timeslice, I3 = old timeslice */ +#define TX_TRACE_THREAD_WAIT_ABORT 117 /* I1 = thread ptr, I2 = thread state, I3 = stack ptr */ +#define TX_TRACE_TIME_GET 120 /* I1 = current time, I2 = stack ptr */ +#define TX_TRACE_TIME_SET 121 /* I1 = new time */ +#define TX_TRACE_TIMER_ACTIVATE 122 /* I1 = timer ptr */ +#define TX_TRACE_TIMER_CHANGE 123 /* I1 = timer ptr, I2 = initial ticks, I3= reschedule ticks */ +#define TX_TRACE_TIMER_CREATE 124 /* I1 = timer ptr, I2 = initial ticks, I3= reschedule ticks, I4 = enable */ +#define TX_TRACE_TIMER_DEACTIVATE 125 /* I1 = timer ptr, I2 = stack ptr */ +#define TX_TRACE_TIMER_DELETE 126 /* I1 = timer ptr */ +#define TX_TRACE_TIMER_INFO_GET 127 /* I1 = timer ptr, I2 = stack ptr */ +#define TX_TRACE_TIMER_PERFORMANCE_INFO_GET 128 /* I1 = timer ptr */ +#define TX_TRACE_TIMER_PERFORMANCE_SYSTEM_INFO_GET 129 /* None */ + + +/* Define the an Trace Buffer Entry. */ + +typedef struct TX_TRACE_BUFFER_ENTRY_STRUCT +{ + + ULONG tx_trace_buffer_entry_thread_pointer; + ULONG tx_trace_buffer_entry_thread_priority; + ULONG tx_trace_buffer_entry_event_id; + ULONG tx_trace_buffer_entry_time_stamp; +#ifdef TX_MISRA_ENABLE + ULONG tx_trace_buffer_entry_info_1; + ULONG tx_trace_buffer_entry_info_2; + ULONG tx_trace_buffer_entry_info_3; + ULONG tx_trace_buffer_entry_info_4; +#else + ULONG tx_trace_buffer_entry_information_field_1; + ULONG tx_trace_buffer_entry_information_field_2; + ULONG tx_trace_buffer_entry_information_field_3; + ULONG tx_trace_buffer_entry_information_field_4; +#endif +} TX_TRACE_BUFFER_ENTRY; + + +/* Trace management component data declarations follow. */ + +/* Determine if the initialization function of this component is including + this file. If so, make the data definitions really happen. Otherwise, + make them extern so other functions in the component can access them. */ + +#ifdef TX_TRACE_INIT +#define TRACE_DECLARE +#else +#define TRACE_DECLARE extern +#endif + + +/* Define the pointer to the start of the trace buffer control structure. */ + +TRACE_DECLARE TX_TRACE_HEADER *_tx_trace_header_ptr; + + +/* Define the pointer to the start of the trace object registry area in the trace buffer. */ + +TRACE_DECLARE TX_TRACE_OBJECT_ENTRY *_tx_trace_registry_start_ptr; + + +/* Define the pointer to the end of the trace object registry area in the trace buffer. */ + +TRACE_DECLARE TX_TRACE_OBJECT_ENTRY *_tx_trace_registry_end_ptr; + + +/* Define the pointer to the starting entry of the actual trace event area of the trace buffer. */ + +TRACE_DECLARE TX_TRACE_BUFFER_ENTRY *_tx_trace_buffer_start_ptr; + + +/* Define the pointer to the ending entry of the actual trace event area of the trace buffer. */ + +TRACE_DECLARE TX_TRACE_BUFFER_ENTRY *_tx_trace_buffer_end_ptr; + + +/* Define the pointer to the current entry of the actual trace event area of the trace buffer. */ + +TRACE_DECLARE TX_TRACE_BUFFER_ENTRY *_tx_trace_buffer_current_ptr; + + +/* Define the trace event enable bits, where each bit represents a type of event that can be enabled + or disabled dynamically by the application. */ + +TRACE_DECLARE ULONG _tx_trace_event_enable_bits; + + +/* Define a counter that is used in environments that don't have a timer source. This counter + is incremented on each use giving each event a unique timestamp. */ + +TRACE_DECLARE ULONG _tx_trace_simulated_time; + + +/* Define the function pointer used to call the application when the trace buffer wraps. If NULL, + the application has not registered a callback function. */ + +TRACE_DECLARE VOID (*_tx_trace_full_notify_function)(VOID *buffer); + + +/* Define the total number of registry entries. */ + +TRACE_DECLARE ULONG _tx_trace_total_registry_entries; + + +/* Define a counter that is used to track the number of available registry entries. */ + +TRACE_DECLARE ULONG _tx_trace_available_registry_entries; + + +/* Define an index that represents the start of the registry search. */ + +TRACE_DECLARE ULONG _tx_trace_registry_search_start; + + +/* Define the event trace macros that are expanded in-line when event tracing is enabled. */ + +#ifdef TX_MISRA_ENABLE +#define TX_TRACE_INFO_FIELD_ASSIGNMENT(a,b,c,d) trace_event_ptr -> tx_trace_buffer_entry_info_1 = (ULONG) (a); trace_event_ptr -> tx_trace_buffer_entry_info_2 = (ULONG) (b); trace_event_ptr -> tx_trace_buffer_entry_info_3 = (ULONG) (c); trace_event_ptr -> tx_trace_buffer_entry_info_4 = (ULONG) (d); +#else +#define TX_TRACE_INFO_FIELD_ASSIGNMENT(a,b,c,d) trace_event_ptr -> tx_trace_buffer_entry_information_field_1 = (ULONG) (a); trace_event_ptr -> tx_trace_buffer_entry_information_field_2 = (ULONG) (b); trace_event_ptr -> tx_trace_buffer_entry_information_field_3 = (ULONG) (c); trace_event_ptr -> tx_trace_buffer_entry_information_field_4 = (ULONG) (d); +#endif + + +#define TX_TRACE_INITIALIZE _tx_trace_initialize(); +#define TX_TRACE_OBJECT_REGISTER(t,p,n,a,b) _tx_trace_object_register((UCHAR) (t), (VOID *) (p), (CHAR *) (n), (ULONG) (a), (ULONG) (b)); +#define TX_TRACE_OBJECT_UNREGISTER(o) _tx_trace_object_unregister((VOID *) (o)); +#ifndef TX_TRACE_IN_LINE_INSERT +#define TX_TRACE_IN_LINE_INSERT(i,a,b,c,d,e) \ + { \ + TX_TRACE_BUFFER_ENTRY *trace_event_ptr; \ + ULONG trace_system_state; \ + ULONG trace_priority; \ + TX_THREAD *trace_thread_ptr; \ + ULONG core; \ + trace_event_ptr = _tx_trace_buffer_current_ptr; \ + if ((trace_event_ptr) && (_tx_trace_event_enable_bits & ((ULONG) (e)))) \ + { \ + TX_TRACE_PORT_EXTENSION \ + trace_system_state = (ULONG) _tx_thread_smp_current_state_get(); \ + TX_THREAD_GET_CURRENT(trace_thread_ptr) \ + \ + if (trace_system_state == ((ULONG) 0)) \ + { \ + trace_priority = trace_thread_ptr -> tx_thread_priority; \ + trace_priority = trace_priority | 0x80000000UL | (trace_thread_ptr -> tx_thread_preempt_threshold << 16); \ + } \ + else if (trace_system_state < 0xF0F0F0F0UL) \ + { \ + trace_priority = (ULONG) trace_thread_ptr; \ + trace_thread_ptr = (TX_THREAD *) 0xFFFFFFFFUL; \ + } \ + else \ + { \ + trace_thread_ptr = (TX_THREAD *) 0xF0F0F0F0UL; \ + trace_priority = (ULONG) 0; \ + } \ + trace_event_ptr -> tx_trace_buffer_entry_thread_pointer = (ULONG) trace_thread_ptr; \ + trace_event_ptr -> tx_trace_buffer_entry_thread_priority = (ULONG) trace_priority; \ + core = _tx_thread_smp_core_get(); \ + trace_event_ptr -> tx_trace_buffer_entry_event_id = (ULONG) (core << 24) | (i); \ + trace_event_ptr -> tx_trace_buffer_entry_time_stamp = (ULONG) TX_TRACE_TIME_SOURCE; \ + TX_TRACE_INFO_FIELD_ASSIGNMENT((a),(b),(c),(d)) \ + trace_event_ptr++; \ + if (trace_event_ptr >= _tx_trace_buffer_end_ptr) \ + { \ + trace_event_ptr = _tx_trace_buffer_start_ptr; \ + _tx_trace_buffer_current_ptr = trace_event_ptr; \ + _tx_trace_header_ptr -> tx_trace_header_buffer_current_pointer = (ULONG) trace_event_ptr; \ + if (_tx_trace_full_notify_function) \ + (_tx_trace_full_notify_function)((VOID *) _tx_trace_header_ptr); \ + } \ + else \ + { \ + _tx_trace_buffer_current_ptr = trace_event_ptr; \ + _tx_trace_header_ptr -> tx_trace_header_buffer_current_pointer = (ULONG) trace_event_ptr; \ + } \ + } \ + } +#endif +#endif + + +#ifdef TX_SOURCE_CODE + +/* Define internal function prototypes of the trace component, only if compiling ThreadX source code. */ + +VOID _tx_trace_initialize(VOID); +VOID _tx_trace_object_register(UCHAR object_type, VOID *object_ptr, CHAR *object_name, ULONG parameter_1, ULONG parameter_2); +VOID _tx_trace_object_unregister(VOID *object_ptr); + +#ifdef TX_ENABLE_EVENT_TRACE + +/* Check for MISRA compliance requirements. */ + +#ifdef TX_MISRA_ENABLE + +/* Define MISRA-specific routines. */ + +UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); +TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); +TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); +TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); +UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); + + +#define TX_OBJECT_TO_UCHAR_POINTER_CONVERT(a) _tx_misra_object_to_uchar_pointer_convert((a)) +#define TX_UCHAR_TO_OBJECT_POINTER_CONVERT(a) _tx_misra_uchar_to_object_pointer_convert((a)) +#define TX_UCHAR_TO_HEADER_POINTER_CONVERT(a) _tx_misra_uchar_to_header_pointer_convert((a)) +#define TX_UCHAR_TO_ENTRY_POINTER_CONVERT(a) _tx_misra_uchar_to_entry_pointer_convert((a)) +#define TX_ENTRY_TO_UCHAR_POINTER_CONVERT(a) _tx_misra_entry_to_uchar_pointer_convert((a)) + +#else + +#define TX_OBJECT_TO_UCHAR_POINTER_CONVERT(a) ((UCHAR *) ((VOID *) (a))) +#define TX_UCHAR_TO_OBJECT_POINTER_CONVERT(a) ((TX_TRACE_OBJECT_ENTRY *) ((VOID *) (a))) +#define TX_UCHAR_TO_HEADER_POINTER_CONVERT(a) ((TX_TRACE_HEADER *) ((VOID *) (a))) +#define TX_UCHAR_TO_ENTRY_POINTER_CONVERT(a) ((TX_TRACE_BUFFER_ENTRY *) ((VOID *) (a))) +#define TX_ENTRY_TO_UCHAR_POINTER_CONVERT(a) ((UCHAR *) ((VOID *) (a))) + +#endif +#endif +#endif + +#endif + diff --git a/common_smp/inc/tx_user.h b/common_smp/inc/tx_user.h new file mode 100644 index 00000000..db17d428 --- /dev/null +++ b/common_smp/inc/tx_user.h @@ -0,0 +1,257 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** User Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_user.h PORTABLE C */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains user defines for configuring ThreadX in specific */ +/* ways. This file will have an effect only if the application and */ +/* ThreadX library are built with TX_INCLUDE_USER_DEFINE_FILE defined. */ +/* Note that all the defines in this file may also be made on the */ +/* command line when building ThreadX library and application objects. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_USER_H +#define TX_USER_H + + +/* Define various build options for the ThreadX port. The application should either make changes + here by commenting or un-commenting the conditional compilation defined OR supply the defines + though the compiler's equivalent of the -D option. + + For maximum speed, the following should be defined: + + TX_MAX_PRIORITIES 32 + TX_DISABLE_PREEMPTION_THRESHOLD + TX_DISABLE_REDUNDANT_CLEARING + TX_DISABLE_NOTIFY_CALLBACKS + TX_NOT_INTERRUPTABLE + TX_TIMER_PROCESS_IN_ISR + TX_REACTIVATE_INLINE + TX_DISABLE_STACK_FILLING + TX_INLINE_THREAD_RESUME_SUSPEND + + For minimum size, the following should be defined: + + TX_MAX_PRIORITIES 32 + TX_DISABLE_PREEMPTION_THRESHOLD + TX_DISABLE_REDUNDANT_CLEARING + TX_DISABLE_NOTIFY_CALLBACKS + TX_NOT_INTERRUPTABLE + TX_TIMER_PROCESS_IN_ISR + + Of course, many of these defines reduce functionality and/or change the behavior of the + system in ways that may not be worth the trade-off. For example, the TX_TIMER_PROCESS_IN_ISR + results in faster and smaller code, however, it increases the amount of processing in the ISR. + In addition, some services that are available in timers are not available from ISRs and will + therefore return an error if this option is used. This may or may not be desirable for a + given application. */ + + +/* Override various options with default values already assigned in tx_port.h. Please also refer + to tx_port.h for descriptions on each of these options. */ + +/* +#define TX_MAX_PRIORITIES 32 +#define TX_MINIMUM_STACK ???? +#define TX_THREAD_USER_EXTENSION ???? +#define TX_TIMER_THREAD_STACK_SIZE ???? +#define TX_TIMER_THREAD_PRIORITY ???? +*/ + +/* Determine if timer expirations (application timers, timeouts, and tx_thread_sleep calls + should be processed within the a system timer thread or directly in the timer ISR. + By default, the timer thread is used. When the following is defined, the timer expiration + processing is done directly from the timer ISR, thereby eliminating the timer thread control + block, stack, and context switching to activate it. */ + +/* +#define TX_TIMER_PROCESS_IN_ISR +*/ + +/* Determine if in-line timer reactivation should be used within the timer expiration processing. + By default, this is disabled and a function call is used. When the following is defined, + reactivating is performed in-line resulting in faster timer processing but slightly larger + code size. */ + +/* +#define TX_REACTIVATE_INLINE +*/ + +/* Determine is stack filling is enabled. By default, ThreadX stack filling is enabled, + which places an 0xEF pattern in each byte of each thread's stack. This is used by + debuggers with ThreadX-awareness and by the ThreadX run-time stack checking feature. */ + +/* +#define TX_DISABLE_STACK_FILLING +*/ + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +/* +#define TX_ENABLE_STACK_CHECKING +*/ + +/* Determine if preemption-threshold should be disabled. By default, preemption-threshold is + enabled. If the application does not use preemption-threshold, it may be disabled to reduce + code size and improve performance. */ + +/* +#define TX_DISABLE_PREEMPTION_THRESHOLD +*/ + +/* Determine if global ThreadX variables should be cleared. If the compiler startup code clears + the .bss section prior to ThreadX running, the define can be used to eliminate unnecessary + clearing of ThreadX global variables. */ + +/* +#define TX_DISABLE_REDUNDANT_CLEARING +*/ + +/* Determine if no timer processing is required. This option will help eliminate the timer + processing when not needed. The user will also have to comment out the call to + tx_timer_interrupt, which is typically made from assembly language in + tx_initialize_low_level. Note: if TX_NO_TIMER is used, the define TX_TIMER_PROCESS_IN_ISR + must also be used. */ + +/* +#define TX_NO_TIMER +#ifndef TX_TIMER_PROCESS_IN_ISR +#define TX_TIMER_PROCESS_IN_ISR +#endif +*/ + +/* Determine if the notify callback option should be disabled. By default, notify callbacks are + enabled. If the application does not use notify callbacks, they may be disabled to reduce + code size and improve performance. */ + +/* +#define TX_DISABLE_NOTIFY_CALLBACKS +*/ + + +/* Determine if the tx_thread_resume and tx_thread_suspend services should have their internal + code in-line. This results in a larger image, but improves the performance of the thread + resume and suspend services. */ + +/* +#define TX_INLINE_THREAD_RESUME_SUSPEND +*/ + + +/* Determine if the internal ThreadX code is non-interruptable. This results in smaller code + size and less processing overhead, but increases the interrupt lockout time. */ + +/* +#define TX_NOT_INTERRUPTABLE +*/ + + +/* Determine if the trace event logging code should be enabled. This causes slight increases in + code size and overhead, but provides the ability to generate system trace information which + is available for viewing in TraceX. */ + +/* +#define TX_ENABLE_EVENT_TRACE +*/ + + +/* Determine if block pool performance gathering is required by the application. When the following is + defined, ThreadX gathers various block pool performance information. */ + +/* +#define TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if byte pool performance gathering is required by the application. When the following is + defined, ThreadX gathers various byte pool performance information. */ + +/* +#define TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if event flags performance gathering is required by the application. When the following is + defined, ThreadX gathers various event flags performance information. */ + +/* +#define TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if mutex performance gathering is required by the application. When the following is + defined, ThreadX gathers various mutex performance information. */ + +/* +#define TX_MUTEX_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if queue performance gathering is required by the application. When the following is + defined, ThreadX gathers various queue performance information. */ + +/* +#define TX_QUEUE_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if semaphore performance gathering is required by the application. When the following is + defined, ThreadX gathers various semaphore performance information. */ + +/* +#define TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if thread performance gathering is required by the application. When the following is + defined, ThreadX gathers various thread performance information. */ + +/* +#define TX_THREAD_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if timer performance gathering is required by the application. When the following is + defined, ThreadX gathers various timer performance information. */ + +/* +#define TX_TIMER_ENABLE_PERFORMANCE_INFO +*/ + +#endif + diff --git a/common_smp/src/tx_block_allocate.c b/common_smp/src/tx_block_allocate.c new file mode 100644 index 00000000..63bd5313 --- /dev/null +++ b/common_smp/src/tx_block_allocate.c @@ -0,0 +1,372 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Block Pool */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#ifdef TX_ENABLE_EVENT_TRACE +#include "tx_trace.h" +#endif +#include "tx_thread.h" +#include "tx_block_pool.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_block_allocate PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function allocates a block from the specified memory block */ +/* pool. */ +/* */ +/* INPUT */ +/* */ +/* pool_ptr Pointer to pool control block */ +/* block_ptr Pointer to place allocated block */ +/* pointer */ +/* wait_option Suspension option */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_system_suspend Suspend thread */ +/* _tx_thread_system_ni_suspend Non-interruptable suspend thread */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_block_allocate(TX_BLOCK_POOL *pool_ptr, VOID **block_ptr, ULONG wait_option) +{ + +TX_INTERRUPT_SAVE_AREA + +UINT status; +TX_THREAD *thread_ptr; +UCHAR *work_ptr; +UCHAR *temp_ptr; +UCHAR **next_block_ptr; +UCHAR **return_ptr; +UINT suspended_count; +TX_THREAD *next_thread; +TX_THREAD *previous_thread; +#ifdef TX_ENABLE_EVENT_TRACE +TX_TRACE_BUFFER_ENTRY *entry_ptr; +ULONG time_stamp = ((ULONG) 0); +#endif +#ifdef TX_ENABLE_EVENT_LOGGING +UCHAR *log_entry_ptr; +ULONG upper_tbu; +ULONG lower_tbu; +#endif + + + /* Disable interrupts to get a block from the pool. */ + TX_DISABLE + +#ifdef TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO + + /* Increment the total allocations counter. */ + _tx_block_pool_performance_allocate_count++; + + /* Increment the number of allocations on this pool. */ + pool_ptr -> tx_block_pool_performance_allocate_count++; +#endif + +#ifdef TX_ENABLE_EVENT_TRACE + + /* If trace is enabled, save the current event pointer. */ + entry_ptr = _tx_trace_buffer_current_ptr; + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_BLOCK_ALLOCATE, pool_ptr, 0, wait_option, pool_ptr -> tx_block_pool_available, TX_TRACE_BLOCK_POOL_EVENTS) + + /* Save the time stamp for later comparison to verify that + the event hasn't been overwritten by the time the allocate + call succeeds. */ + if (entry_ptr != TX_NULL) + { + + time_stamp = entry_ptr -> tx_trace_buffer_entry_time_stamp; + } +#endif + +#ifdef TX_ENABLE_EVENT_LOGGING + log_entry_ptr = *(UCHAR **) _tx_el_current_event; + + /* Log this kernel call. */ + TX_EL_BLOCK_ALLOCATE_INSERT + + /* Store -1 in the third event slot. */ + *((ULONG *) (log_entry_ptr + TX_EL_EVENT_INFO_3_OFFSET)) = (ULONG) -1; + + /* Save the time stamp for later comparison to verify that + the event hasn't been overwritten by the time the allocate + call succeeds. */ + lower_tbu = *((ULONG *) (log_entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)); + upper_tbu = *((ULONG *) (log_entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)); +#endif + + /* Determine if there is an available block. */ + if (pool_ptr -> tx_block_pool_available != ((UINT) 0)) + { + + /* Yes, a block is available. Decrement the available count. */ + pool_ptr -> tx_block_pool_available--; + + /* Pickup the current block pointer. */ + work_ptr = pool_ptr -> tx_block_pool_available_list; + + /* Return the first available block to the caller. */ + temp_ptr = TX_UCHAR_POINTER_ADD(work_ptr, (sizeof(UCHAR *))); + return_ptr = TX_INDIRECT_VOID_TO_UCHAR_POINTER_CONVERT(block_ptr); + *return_ptr = temp_ptr; + + /* Modify the available list to point at the next block in the pool. */ + next_block_ptr = TX_UCHAR_TO_INDIRECT_UCHAR_POINTER_CONVERT(work_ptr); + pool_ptr -> tx_block_pool_available_list = *next_block_ptr; + + /* Save the pool's address in the block for when it is released! */ + temp_ptr = TX_BLOCK_POOL_TO_UCHAR_POINTER_CONVERT(pool_ptr); + *next_block_ptr = temp_ptr; + +#ifdef TX_ENABLE_EVENT_TRACE + + /* Check that the event time stamp is unchanged. A different + timestamp means that a later event wrote over the byte + allocate event. In that case, do nothing here. */ + if (entry_ptr != TX_NULL) + { + + /* Is the time stamp the same? */ + if (time_stamp == entry_ptr -> tx_trace_buffer_entry_time_stamp) + { + + /* Timestamp is the same, update the entry with the address. */ +#ifdef TX_MISRA_ENABLE + entry_ptr -> tx_trace_buffer_entry_info_2 = TX_POINTER_TO_ULONG_CONVERT(*block_ptr); +#else + entry_ptr -> tx_trace_buffer_entry_information_field_2 = TX_POINTER_TO_ULONG_CONVERT(*block_ptr); +#endif + } + } +#endif + +#ifdef TX_ENABLE_EVENT_LOGGING + /* Store the address of the allocated block. */ + *((ULONG *) (log_entry_ptr + TX_EL_EVENT_INFO_3_OFFSET)) = (ULONG) *block_ptr; +#endif + + /* Set status to success. */ + status = TX_SUCCESS; + + /* Restore interrupts. */ + TX_RESTORE + } + else + { + + /* Default the return pointer to NULL. */ + return_ptr = TX_INDIRECT_VOID_TO_UCHAR_POINTER_CONVERT(block_ptr); + *return_ptr = TX_NULL; + + /* Determine if the request specifies suspension. */ + if (wait_option != TX_NO_WAIT) + { + + /* Determine if the preempt disable flag is non-zero. */ + if (_tx_thread_preempt_disable != ((UINT) 0)) + { + + /* Suspension is not allowed if the preempt disable flag is non-zero at this point, return error completion. */ + status = TX_NO_MEMORY; + + /* Restore interrupts. */ + TX_RESTORE + } + else + { + + /* Prepare for suspension of this thread. */ + +#ifdef TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO + + /* Increment the total suspensions counter. */ + _tx_block_pool_performance_suspension_count++; + + /* Increment the number of suspensions on this pool. */ + pool_ptr -> tx_block_pool_performance_suspension_count++; +#endif + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr) + + /* Setup cleanup routine pointer. */ + thread_ptr -> tx_thread_suspend_cleanup = &(_tx_block_pool_cleanup); + + /* Setup cleanup information, i.e. this pool control + block. */ + thread_ptr -> tx_thread_suspend_control_block = (VOID *) pool_ptr; + + /* Save the return block pointer address as well. */ + thread_ptr -> tx_thread_additional_suspend_info = (VOID *) block_ptr; + +#ifndef TX_NOT_INTERRUPTABLE + + /* Increment the suspension sequence number, which is used to identify + this suspension event. */ + thread_ptr -> tx_thread_suspension_sequence++; +#endif + + /* Pickup the number of suspended threads. */ + suspended_count = (pool_ptr -> tx_block_pool_suspended_count); + + /* Increment the number of suspended threads. */ + (pool_ptr -> tx_block_pool_suspended_count)++; + + /* Setup suspension list. */ + if (suspended_count == TX_NO_SUSPENSIONS) + { + + /* No other threads are suspended. Setup the head pointer and + just setup this threads pointers to itself. */ + pool_ptr -> tx_block_pool_suspension_list = thread_ptr; + thread_ptr -> tx_thread_suspended_next = thread_ptr; + thread_ptr -> tx_thread_suspended_previous = thread_ptr; + } + else + { + + /* This list is not NULL, add current thread to the end. */ + next_thread = pool_ptr -> tx_block_pool_suspension_list; + thread_ptr -> tx_thread_suspended_next = next_thread; + previous_thread = next_thread -> tx_thread_suspended_previous; + thread_ptr -> tx_thread_suspended_previous = previous_thread; + previous_thread -> tx_thread_suspended_next = thread_ptr; + next_thread -> tx_thread_suspended_previous = thread_ptr; + } + + /* Set the state to suspended. */ + thread_ptr -> tx_thread_state = TX_BLOCK_MEMORY; + +#ifdef TX_NOT_INTERRUPTABLE + + /* Call actual non-interruptable thread suspension routine. */ + _tx_thread_system_ni_suspend(thread_ptr, wait_option); + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Set the suspending flag. */ + thread_ptr -> tx_thread_suspending = TX_TRUE; + + /* Setup the timeout period. */ + thread_ptr -> tx_thread_timer.tx_timer_internal_remaining_ticks = wait_option; + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Call actual thread suspension routine. */ + _tx_thread_system_suspend(thread_ptr); +#endif + +#ifdef TX_ENABLE_EVENT_TRACE + + /* Check that the event time stamp is unchanged. A different + timestamp means that a later event wrote over the byte + allocate event. In that case, do nothing here. */ + if (entry_ptr != TX_NULL) + { + + /* Is the time-stamp the same? */ + if (time_stamp == entry_ptr -> tx_trace_buffer_entry_time_stamp) + { + + /* Timestamp is the same, update the entry with the address. */ +#ifdef TX_MISRA_ENABLE + entry_ptr -> tx_trace_buffer_entry_info_2 = TX_POINTER_TO_ULONG_CONVERT(*block_ptr); +#else + entry_ptr -> tx_trace_buffer_entry_information_field_2 = TX_POINTER_TO_ULONG_CONVERT(*block_ptr); +#endif + } + } +#endif + +#ifdef TX_ENABLE_EVENT_LOGGING + /* Check that the event time stamp is unchanged and the call is about + to return success. A different timestamp means that a later event + wrote over the block allocate event. A return value other than + TX_SUCCESS indicates that no block was available. In those cases, + do nothing here. */ + if (lower_tbu == *((ULONG *) (log_entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) && + upper_tbu == *((ULONG *) (log_entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)) && + ((thread_ptr -> tx_thread_suspend_status) == TX_SUCCESS)) + { + + /* Store the address of the allocated block. */ + *((ULONG *) (log_entry_ptr + TX_EL_EVENT_INFO_3_OFFSET)) = (ULONG) *block_ptr; + } +#endif + + /* Return the completion status. */ + status = thread_ptr -> tx_thread_suspend_status; + } + } + else + { + + /* Immediate return, return error completion. */ + status = TX_NO_MEMORY; + + /* Restore interrupts. */ + TX_RESTORE + } + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/tx_block_pool_cleanup.c b/common_smp/src/tx_block_pool_cleanup.c new file mode 100644 index 00000000..ea18c8f9 --- /dev/null +++ b/common_smp/src/tx_block_pool_cleanup.c @@ -0,0 +1,213 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Block Pool */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_block_pool.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_block_pool_cleanup PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes block allocate timeout and thread terminate */ +/* actions that require the block pool data structures to be cleaned */ +/* up. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to suspended thread's */ +/* control block */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_system_resume Resume thread service */ +/* _tx_thread_system_ni_resume Non-interruptable resume thread */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_timeout Thread timeout processing */ +/* _tx_thread_terminate Thread terminate processing */ +/* _tx_thread_wait_abort Thread wait abort processing */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_block_pool_cleanup(TX_THREAD *thread_ptr, ULONG suspension_sequence) +{ + +#ifndef TX_NOT_INTERRUPTABLE +TX_INTERRUPT_SAVE_AREA +#endif + +TX_BLOCK_POOL *pool_ptr; +UINT suspended_count; +TX_THREAD *next_thread; +TX_THREAD *previous_thread; + + +#ifndef TX_NOT_INTERRUPTABLE + + /* Disable interrupts to remove the suspended thread from the block pool. */ + TX_DISABLE + + /* Determine if the cleanup is still required. */ + if (thread_ptr -> tx_thread_suspend_cleanup == &(_tx_block_pool_cleanup)) + { + + /* Check for valid suspension sequence. */ + if (suspension_sequence == thread_ptr -> tx_thread_suspension_sequence) + { + + /* Setup pointer to block pool control block. */ + pool_ptr = TX_VOID_TO_BLOCK_POOL_POINTER_CONVERT(thread_ptr -> tx_thread_suspend_control_block); + + /* Check for a NULL byte pool pointer. */ + if (pool_ptr != TX_NULL) + { + + /* Check for valid pool ID. */ + if (pool_ptr -> tx_block_pool_id == TX_BLOCK_POOL_ID) + { + + /* Determine if there are any thread suspensions. */ + if (pool_ptr -> tx_block_pool_suspended_count != TX_NO_SUSPENSIONS) + { +#else + + /* Setup pointer to block pool control block. */ + pool_ptr = TX_VOID_TO_BLOCK_POOL_POINTER_CONVERT(thread_ptr -> tx_thread_suspend_control_block); +#endif + + /* Yes, we still have thread suspension! */ + + /* Clear the suspension cleanup flag. */ + thread_ptr -> tx_thread_suspend_cleanup = TX_NULL; + + /* Decrement the suspended count. */ + pool_ptr -> tx_block_pool_suspended_count--; + + /* Pickup the suspended count. */ + suspended_count = pool_ptr -> tx_block_pool_suspended_count; + + /* Remove the suspended thread from the list. */ + + /* See if this is the only suspended thread on the list. */ + if (suspended_count == TX_NO_SUSPENSIONS) + { + + /* Yes, the only suspended thread. */ + + /* Update the head pointer. */ + pool_ptr -> tx_block_pool_suspension_list = TX_NULL; + } + else + { + + /* At least one more thread is on the same suspension list. */ + + /* Update the links of the adjacent threads. */ + next_thread = thread_ptr -> tx_thread_suspended_next; + previous_thread = thread_ptr -> tx_thread_suspended_previous; + next_thread -> tx_thread_suspended_previous = previous_thread; + previous_thread -> tx_thread_suspended_next = next_thread; + + /* Determine if we need to update the head pointer. */ + if (pool_ptr -> tx_block_pool_suspension_list == thread_ptr) + { + + /* Update the list head pointer. */ + pool_ptr -> tx_block_pool_suspension_list = next_thread; + } + } + + /* Now we need to determine if this cleanup is from a terminate, timeout, + or from a wait abort. */ + if (thread_ptr -> tx_thread_state == TX_BLOCK_MEMORY) + { + + /* Timeout condition and the thread still suspended on the block pool. + Setup return error status and resume the thread. */ + +#ifdef TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO + + /* Increment the total timeouts counter. */ + _tx_block_pool_performance_timeout_count++; + + /* Increment the number of timeouts on this block pool. */ + pool_ptr -> tx_block_pool_performance_timeout_count++; +#endif + + /* Setup return status. */ + thread_ptr -> tx_thread_suspend_status = TX_NO_MEMORY; + +#ifdef TX_NOT_INTERRUPTABLE + + /* Resume the thread! */ + _tx_thread_system_ni_resume(thread_ptr); +#else + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Resume the thread! */ + _tx_thread_system_resume(thread_ptr); + + /* Disable interrupts. */ + TX_DISABLE +#endif + } +#ifndef TX_NOT_INTERRUPTABLE + } + } + } + } + } + + /* Restore interrupts. */ + TX_RESTORE +#endif +} + diff --git a/common_smp/src/tx_block_pool_create.c b/common_smp/src/tx_block_pool_create.c new file mode 100644 index 00000000..4d9f1d91 --- /dev/null +++ b/common_smp/src/tx_block_pool_create.c @@ -0,0 +1,213 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Block Pool */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_block_pool.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_block_pool_create PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates a pool of fixed-size memory blocks in the */ +/* specified memory area. */ +/* */ +/* INPUT */ +/* */ +/* pool_ptr Pointer to pool control block */ +/* name_ptr Pointer to block pool name */ +/* block_size Number of bytes in each block */ +/* pool_start Address of beginning of pool area */ +/* pool_size Number of bytes in the block pool */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SUCCESS Successful completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_block_pool_create(TX_BLOCK_POOL *pool_ptr, CHAR *name_ptr, ULONG block_size, + VOID *pool_start, ULONG pool_size) +{ + +TX_INTERRUPT_SAVE_AREA + +UINT blocks; +UINT status; +ULONG total_blocks; +UCHAR *block_ptr; +UCHAR **block_link_ptr; +UCHAR *next_block_ptr; +TX_BLOCK_POOL *next_pool; +TX_BLOCK_POOL *previous_pool; + + + /* Initialize block pool control block to all zeros. */ + TX_MEMSET(pool_ptr, 0, (sizeof(TX_BLOCK_POOL))); + + /* Round the block size up to something that is evenly divisible by + an ALIGN_TYPE (typically this is a 32-bit ULONG). This helps guarantee proper alignment. */ + block_size = (((block_size + (sizeof(ALIGN_TYPE))) - ((ALIGN_TYPE) 1))/(sizeof(ALIGN_TYPE))) * (sizeof(ALIGN_TYPE)); + + /* Round the pool size down to something that is evenly divisible by + an ALIGN_TYPE (typically this is a 32-bit ULONG). */ + pool_size = (pool_size/(sizeof(ALIGN_TYPE))) * (sizeof(ALIGN_TYPE)); + + /* Setup the basic block pool fields. */ + pool_ptr -> tx_block_pool_name = name_ptr; + pool_ptr -> tx_block_pool_start = TX_VOID_TO_UCHAR_POINTER_CONVERT(pool_start); + pool_ptr -> tx_block_pool_size = pool_size; + pool_ptr -> tx_block_pool_block_size = (UINT) block_size; + + /* Calculate the total number of blocks. */ + total_blocks = pool_size/(block_size + (sizeof(UCHAR *))); + + /* Walk through the pool area, setting up the available block list. */ + blocks = ((UINT) 0); + block_ptr = TX_VOID_TO_UCHAR_POINTER_CONVERT(pool_start); + next_block_ptr = TX_UCHAR_POINTER_ADD(block_ptr, (block_size + (sizeof(UCHAR *)))); + while(blocks < (UINT) total_blocks) + { + + /* Yes, we have another block. Increment the block count. */ + blocks++; + + /* Setup the link to the next block. */ + block_link_ptr = TX_UCHAR_TO_INDIRECT_UCHAR_POINTER_CONVERT(block_ptr); + *block_link_ptr = next_block_ptr; + + /* Advance to the next block. */ + block_ptr = next_block_ptr; + + /* Update the next block pointer. */ + next_block_ptr = TX_UCHAR_POINTER_ADD(block_ptr, (block_size + (sizeof(UCHAR *)))); + } + + /* Save the remaining information in the pool control block. */ + pool_ptr -> tx_block_pool_available = blocks; + pool_ptr -> tx_block_pool_total = blocks; + + /* Quickly check to make sure at least one block is in the pool. */ + if (blocks != ((UINT) 0)) + { + + /* Backup to the last block in the pool. */ + block_ptr = TX_UCHAR_POINTER_SUB(block_ptr,(block_size + (sizeof(UCHAR *)))); + + /* Set the last block's forward pointer to NULL. */ + block_link_ptr = TX_UCHAR_TO_INDIRECT_UCHAR_POINTER_CONVERT(block_ptr); + *block_link_ptr = TX_NULL; + + /* Setup the starting pool address. */ + pool_ptr -> tx_block_pool_available_list = TX_VOID_TO_UCHAR_POINTER_CONVERT(pool_start); + + /* Disable interrupts to place the block pool on the created list. */ + TX_DISABLE + + /* Setup the block pool ID to make it valid. */ + pool_ptr -> tx_block_pool_id = TX_BLOCK_POOL_ID; + + /* Place the block pool on the list of created block pools. First, + check for an empty list. */ + if (_tx_block_pool_created_count == TX_EMPTY) + { + + /* The created block pool list is empty. Add block pool to empty list. */ + _tx_block_pool_created_ptr = pool_ptr; + pool_ptr -> tx_block_pool_created_next = pool_ptr; + pool_ptr -> tx_block_pool_created_previous = pool_ptr; + } + else + { + + /* This list is not NULL, add to the end of the list. */ + next_pool = _tx_block_pool_created_ptr; + previous_pool = next_pool -> tx_block_pool_created_previous; + + /* Place the new block pool in the list. */ + next_pool -> tx_block_pool_created_previous = pool_ptr; + previous_pool -> tx_block_pool_created_next = pool_ptr; + + /* Setup this block pool's created links. */ + pool_ptr -> tx_block_pool_created_previous = previous_pool; + pool_ptr -> tx_block_pool_created_next = next_pool; + } + + /* Increment the created count. */ + _tx_block_pool_created_count++; + + /* Optional block pool create extended processing. */ + TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) + + /* If trace is enabled, register this object. */ + TX_TRACE_OBJECT_REGISTER(TX_TRACE_OBJECT_TYPE_BLOCK_POOL, pool_ptr, name_ptr, pool_size, block_size) + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_BLOCK_POOL_CREATE, pool_ptr, TX_POINTER_TO_ULONG_CONVERT(pool_start), blocks, block_size, TX_TRACE_BLOCK_POOL_EVENTS) + + /* Log this kernel call. */ + TX_EL_BLOCK_POOL_CREATE_INSERT + + /* Restore interrupts. */ + TX_RESTORE + + /* Return successful status. */ + status = TX_SUCCESS; + } + else + { + + /* Not enough memory for one block, return appropriate error. */ + status = TX_SIZE_ERROR; + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/tx_block_pool_delete.c b/common_smp/src/tx_block_pool_delete.c new file mode 100644 index 00000000..27ac2c24 --- /dev/null +++ b/common_smp/src/tx_block_pool_delete.c @@ -0,0 +1,207 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Block Pool */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_thread.h" +#include "tx_block_pool.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_block_pool_delete PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function deletes the specified block pool. All threads */ +/* suspended on the block pool are resumed with the TX_DELETED status */ +/* code. */ +/* */ +/* INPUT */ +/* */ +/* pool_ptr Pointer to pool control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SUCCESS Successful completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_system_preempt_check Check for preemption */ +/* _tx_thread_system_resume Resume thread service */ +/* _tx_thread_system_ni_resume Non-interruptable resume thread */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_block_pool_delete(TX_BLOCK_POOL *pool_ptr) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_THREAD *thread_ptr; +TX_THREAD *next_thread; +UINT suspended_count; +TX_BLOCK_POOL *next_pool; +TX_BLOCK_POOL *previous_pool; + + + /* Disable interrupts to remove the block pool from the created list. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_BLOCK_POOL_DELETE, pool_ptr, TX_POINTER_TO_ULONG_CONVERT(&thread_ptr), 0, 0, TX_TRACE_BLOCK_POOL_EVENTS) + + /* Log this kernel call. */ + TX_EL_BLOCK_POOL_DELETE_INSERT + + /* Optional block pool delete extended processing. */ + TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) + + /* If trace is enabled, unregister this object. */ + TX_TRACE_OBJECT_UNREGISTER(pool_ptr) + + /* Clear the block pool ID to make it invalid. */ + pool_ptr -> tx_block_pool_id = TX_CLEAR_ID; + + /* Decrement the number of block pools. */ + _tx_block_pool_created_count--; + + /* See if the block pool is the only one on the list. */ + if (_tx_block_pool_created_count == TX_EMPTY) + { + + /* Only created block pool, just set the created list to NULL. */ + _tx_block_pool_created_ptr = TX_NULL; + } + else + { + + /* Link-up the neighbors. */ + next_pool = pool_ptr -> tx_block_pool_created_next; + previous_pool = pool_ptr -> tx_block_pool_created_previous; + next_pool -> tx_block_pool_created_previous = previous_pool; + previous_pool -> tx_block_pool_created_next = next_pool; + + /* See if we have to update the created list head pointer. */ + if (_tx_block_pool_created_ptr == pool_ptr) + { + + /* Yes, move the head pointer to the next link. */ + _tx_block_pool_created_ptr = next_pool; + } + } + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Pickup the suspension information. */ + thread_ptr = pool_ptr -> tx_block_pool_suspension_list; + pool_ptr -> tx_block_pool_suspension_list = TX_NULL; + suspended_count = pool_ptr -> tx_block_pool_suspended_count; + pool_ptr -> tx_block_pool_suspended_count = TX_NO_SUSPENSIONS; + + /* Restore interrupts. */ + TX_RESTORE + + /* Walk through the block pool suspension list to resume any and all threads suspended + on this block pool. */ + while (suspended_count != TX_NO_SUSPENSIONS) + { + + /* Decrement the suspension count. */ + suspended_count--; + + /* Lockout interrupts. */ + TX_DISABLE + + /* Clear the cleanup pointer, this prevents the timeout from doing + anything. */ + thread_ptr -> tx_thread_suspend_cleanup = TX_NULL; + + /* Set the return status in the thread to TX_DELETED. */ + thread_ptr -> tx_thread_suspend_status = TX_DELETED; + + /* Move the thread pointer ahead. */ + next_thread = thread_ptr -> tx_thread_suspended_next; + +#ifdef TX_NOT_INTERRUPTABLE + + /* Resume the thread! */ + _tx_thread_system_ni_resume(thread_ptr); + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Temporarily disable preemption again. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Resume the thread. */ + _tx_thread_system_resume(thread_ptr); +#endif + + /* Move to next thread. */ + thread_ptr = next_thread; + } + + /* Execute Port-Specific completion processing. If needed, it is typically defined in tx_port.h. */ + TX_BLOCK_POOL_DELETE_PORT_COMPLETION(pool_ptr) + + /* Disable interrupts. */ + TX_DISABLE + + /* Release previous preempt disable. */ + _tx_thread_preempt_disable--; + + /* Restore interrupts. */ + TX_RESTORE + + /* Check for preemption. */ + _tx_thread_system_preempt_check(); + + /* Return TX_SUCCESS. */ + return(TX_SUCCESS); +} + diff --git a/common_smp/src/tx_block_pool_info_get.c b/common_smp/src/tx_block_pool_info_get.c new file mode 100644 index 00000000..78930c36 --- /dev/null +++ b/common_smp/src/tx_block_pool_info_get.c @@ -0,0 +1,146 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Block Memory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_block_pool.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_block_pool_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves information from the specified block pool. */ +/* */ +/* INPUT */ +/* */ +/* pool_ptr Pointer to block pool control blk */ +/* name Destination for the pool name */ +/* available_blocks Number of free blocks in pool */ +/* total_blocks Total number of blocks in pool */ +/* first_suspended Destination for pointer of first */ +/* thread suspended on block pool */ +/* suspended_count Destination for suspended count */ +/* next_pool Destination for pointer to next */ +/* block pool on the created list */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_block_pool_info_get(TX_BLOCK_POOL *pool_ptr, CHAR **name, ULONG *available_blocks, + ULONG *total_blocks, TX_THREAD **first_suspended, + ULONG *suspended_count, TX_BLOCK_POOL **next_pool) +{ + +TX_INTERRUPT_SAVE_AREA + + + /* Disable interrupts. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_BLOCK_POOL_INFO_GET, pool_ptr, 0, 0, 0, TX_TRACE_BLOCK_POOL_EVENTS) + + /* Log this kernel call. */ + TX_EL_BLOCK_POOL_INFO_GET_INSERT + + /* Retrieve all the pertinent information and return it in the supplied + destinations. */ + + /* Retrieve the name of the block pool. */ + if (name != TX_NULL) + { + + *name = pool_ptr -> tx_block_pool_name; + } + + /* Retrieve the number of available blocks in the block pool. */ + if (available_blocks != TX_NULL) + { + + *available_blocks = (ULONG) pool_ptr -> tx_block_pool_available; + } + + /* Retrieve the total number of blocks in the block pool. */ + if (total_blocks != TX_NULL) + { + + *total_blocks = (ULONG) pool_ptr -> tx_block_pool_total; + } + + /* Retrieve the first thread suspended on this block pool. */ + if (first_suspended != TX_NULL) + { + + *first_suspended = pool_ptr -> tx_block_pool_suspension_list; + } + + /* Retrieve the number of threads suspended on this block pool. */ + if (suspended_count != TX_NULL) + { + + *suspended_count = (ULONG) pool_ptr -> tx_block_pool_suspended_count; + } + + /* Retrieve the pointer to the next block pool created. */ + if (next_pool != TX_NULL) + { + + *next_pool = pool_ptr -> tx_block_pool_created_next; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return completion status. */ + return(TX_SUCCESS); +} + diff --git a/common_smp/src/tx_block_pool_initialize.c b/common_smp/src/tx_block_pool_initialize.c new file mode 100644 index 00000000..0edb9786 --- /dev/null +++ b/common_smp/src/tx_block_pool_initialize.c @@ -0,0 +1,129 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Block Pool */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_block_pool.h" + + +#ifndef TX_INLINE_INITIALIZATION + +/* Locate block pool component data in this file. */ + +/* Define the head pointer of the created block pool list. */ + +TX_BLOCK_POOL * _tx_block_pool_created_ptr; + + +/* Define the variable that holds the number of created block pools. */ + +ULONG _tx_block_pool_created_count; + + +#ifdef TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO + +/* Define the total number of block allocates. */ + +ULONG _tx_block_pool_performance_allocate_count; + + +/* Define the total number of block releases. */ + +ULONG _tx_block_pool_performance_release_count; + + +/* Define the total number of block pool suspensions. */ + +ULONG _tx_block_pool_performance_suspension_count; + + +/* Define the total number of block pool timeouts. */ + +ULONG _tx_block_pool_performance_timeout_count; + +#endif +#endif + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_block pool_initialize PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes the various control data structures for */ +/* the block pool component. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_high_level High level initialization */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_block_pool_initialize(VOID) +{ + +#ifndef TX_DISABLE_REDUNDANT_CLEARING + + /* Initialize the head pointer of the created block pools list and the + number of block pools created. */ + _tx_block_pool_created_ptr = TX_NULL; + _tx_block_pool_created_count = TX_EMPTY; + +#ifdef TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO + + /* Initialize block pool performance counters. */ + _tx_block_pool_performance_allocate_count = ((ULONG) 0); + _tx_block_pool_performance_release_count = ((ULONG) 0); + _tx_block_pool_performance_suspension_count = ((ULONG) 0); + _tx_block_pool_performance_timeout_count = ((ULONG) 0); +#endif +#endif +} + diff --git a/common_smp/src/tx_block_pool_performance_info_get.c b/common_smp/src/tx_block_pool_performance_info_get.c new file mode 100644 index 00000000..65a31e0b --- /dev/null +++ b/common_smp/src/tx_block_pool_performance_info_get.c @@ -0,0 +1,201 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Block Memory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_block_pool.h" +#ifdef TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO +#include "tx_trace.h" +#endif + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_block_pool_performance_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves performance information from the specified */ +/* block pool. */ +/* */ +/* INPUT */ +/* */ +/* pool_ptr Pointer to block pool control blk */ +/* allocates Destination for the number of */ +/* allocations from this pool */ +/* releases Destination for the number of */ +/* blocks released back to pool */ +/* suspensions Destination for number of */ +/* suspensions on this pool */ +/* timeouts Destination for number of timeouts*/ +/* on this pool */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_block_pool_performance_info_get(TX_BLOCK_POOL *pool_ptr, ULONG *allocates, ULONG *releases, + ULONG *suspensions, ULONG *timeouts) +{ + +#ifdef TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO + +TX_INTERRUPT_SAVE_AREA +UINT status; + + + /* Determine if this is a legal request. */ + if (pool_ptr == TX_NULL) + { + + /* Block pool pointer is illegal, return error. */ + status = TX_PTR_ERROR; + } + + /* Determine if the pool ID is invalid. */ + else if (pool_ptr -> tx_block_pool_id != TX_BLOCK_POOL_ID) + { + + /* Block pool pointer is illegal, return error. */ + status = TX_PTR_ERROR; + } + else + { + + /* Disable interrupts. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_BLOCK_POOL_PERFORMANCE_INFO_GET, pool_ptr, 0, 0, 0, TX_TRACE_BLOCK_POOL_EVENTS) + + /* Log this kernel call. */ + TX_EL_BLOCK_POOL_PERFORMANCE_INFO_GET_INSERT + + /* Retrieve all the pertinent information and return it in the supplied + destinations. */ + + /* Retrieve the number of allocations from this block pool. */ + if (allocates != TX_NULL) + { + + *allocates = pool_ptr -> tx_block_pool_performance_allocate_count; + } + + /* Retrieve the number of blocks released to this block pool. */ + if (releases != TX_NULL) + { + + *releases = pool_ptr -> tx_block_pool_performance_release_count; + } + + /* Retrieve the number of thread suspensions on this block pool. */ + if (suspensions != TX_NULL) + { + + *suspensions = pool_ptr -> tx_block_pool_performance_suspension_count; + } + + /* Retrieve the number of thread timeouts on this block pool. */ + if (timeouts != TX_NULL) + { + + *timeouts = pool_ptr -> tx_block_pool_performance_timeout_count; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return successful completion. */ + status = TX_SUCCESS; + } +#else +UINT status; + + + /* Access input arguments just for the sake of lint, MISRA, etc. */ + if (pool_ptr != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (allocates != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (releases != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (suspensions != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (timeouts != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } +#endif + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/tx_block_pool_performance_system_info_get.c b/common_smp/src/tx_block_pool_performance_system_info_get.c new file mode 100644 index 00000000..383f91ba --- /dev/null +++ b/common_smp/src/tx_block_pool_performance_system_info_get.c @@ -0,0 +1,173 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Block Memory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_block_pool.h" +#ifdef TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO +#include "tx_trace.h" +#endif + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_block_pool_performance_system_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves block pool performance information. */ +/* */ +/* INPUT */ +/* */ +/* allocates Destination for the total number */ +/* of block allocations */ +/* releases Destination for the total number */ +/* of blocks released */ +/* suspensions Destination for the total number */ +/* of suspensions */ +/* timeouts Destination for total number of */ +/* timeouts */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_block_pool_performance_system_info_get(ULONG *allocates, ULONG *releases, ULONG *suspensions, ULONG *timeouts) +{ + +#ifdef TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO + +TX_INTERRUPT_SAVE_AREA + + + /* Disable interrupts. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_BLOCK_POOL__PERFORMANCE_SYSTEM_INFO_GET, 0, 0, 0, 0, TX_TRACE_BLOCK_POOL_EVENTS) + + /* Log this kernel call. */ + TX_EL_BLOCK_POOL_PERFORMANCE_SYSTEM_INFO_GET_INSERT + + /* Retrieve all the pertinent information and return it in the supplied + destinations. */ + + /* Retrieve the total number of block allocations. */ + if (allocates != TX_NULL) + { + + *allocates = _tx_block_pool_performance_allocate_count; + } + + /* Retrieve the total number of blocks released. */ + if (releases != TX_NULL) + { + + *releases = _tx_block_pool_performance_release_count; + } + + /* Retrieve the total number of block pool thread suspensions. */ + if (suspensions != TX_NULL) + { + + *suspensions = _tx_block_pool_performance_suspension_count; + } + + /* Retrieve the total number of block pool thread timeouts. */ + if (timeouts != TX_NULL) + { + + *timeouts = _tx_block_pool_performance_timeout_count; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return completion status. */ + return(TX_SUCCESS); + +#else + +UINT status; + + + /* Access input arguments just for the sake of lint, MISRA, etc. */ + if (allocates != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (releases != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (suspensions != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (timeouts != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + + /* Return completion status. */ + return(status); +#endif +} + diff --git a/common_smp/src/tx_block_pool_prioritize.c b/common_smp/src/tx_block_pool_prioritize.c new file mode 100644 index 00000000..e51932b1 --- /dev/null +++ b/common_smp/src/tx_block_pool_prioritize.c @@ -0,0 +1,249 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Block Pool */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_thread.h" +#include "tx_block_pool.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_block_pool_prioritize PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function places the highest priority suspended thread at the */ +/* front of the suspension list. All other threads remain in the same */ +/* FIFO suspension order. */ +/* */ +/* INPUT */ +/* */ +/* pool_ptr Pointer to pool control block */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_system_preempt_check Check for preemption */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_block_pool_prioritize(TX_BLOCK_POOL *pool_ptr) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_THREAD *thread_ptr; +TX_THREAD *priority_thread_ptr; +TX_THREAD *head_ptr; +UINT suspended_count; +TX_THREAD *next_thread; +TX_THREAD *previous_thread; +UINT list_changed; + + + /* Disable interrupts. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_BLOCK_POOL_PRIORITIZE, pool_ptr, pool_ptr -> tx_block_pool_suspended_count, TX_POINTER_TO_ULONG_CONVERT(&suspended_count), 0, TX_TRACE_BLOCK_POOL_EVENTS) + + /* Log this kernel call. */ + TX_EL_BLOCK_POOL_PRIORITIZE_INSERT + + /* Pickup the suspended count. */ + suspended_count = pool_ptr -> tx_block_pool_suspended_count; + + /* Determine if there are fewer than 2 suspended threads. */ + if (suspended_count < ((UINT) 2)) + { + + /* Restore interrupts. */ + TX_RESTORE + } + + /* Determine if there how many threads are suspended on this block memory pool. */ + else if (suspended_count == ((UINT) 2)) + { + + /* Pickup the head pointer and the next pointer. */ + head_ptr = pool_ptr -> tx_block_pool_suspension_list; + next_thread = head_ptr -> tx_thread_suspended_next; + + /* Determine if the next suspended thread has a higher priority. */ + if ((next_thread -> tx_thread_priority) < (head_ptr -> tx_thread_priority)) + { + + /* Yes, move the list head to the next thread. */ + pool_ptr -> tx_block_pool_suspension_list = next_thread; + } + + /* Restore interrupts. */ + TX_RESTORE + } + else + { + + /* Remember the suspension count and head pointer. */ + head_ptr = pool_ptr -> tx_block_pool_suspension_list; + + /* Default the highest priority thread to the thread at the front of the list. */ + priority_thread_ptr = head_ptr; + + /* Setup search pointer. */ + thread_ptr = priority_thread_ptr -> tx_thread_suspended_next; + + /* Disable preemption. */ + _tx_thread_preempt_disable++; + + /* Set the list changed flag to false. */ + list_changed = TX_FALSE; + + /* Search through the list to find the highest priority thread. */ + do + { + + /* Is the current thread higher priority? */ + if (thread_ptr -> tx_thread_priority < priority_thread_ptr -> tx_thread_priority) + { + + /* Yes, remember that this thread is the highest priority. */ + priority_thread_ptr = thread_ptr; + } + + /* Restore interrupts temporarily. */ + TX_RESTORE + + /* Disable interrupts again. */ + TX_DISABLE + + /* Determine if any changes to the list have occurred while + interrupts were enabled. */ + + /* Is the list head the same? */ + if (head_ptr != pool_ptr -> tx_block_pool_suspension_list) + { + + /* The list head has changed, set the list changed flag. */ + list_changed = TX_TRUE; + } + else + { + + /* Is the suspended count the same? */ + if (suspended_count != pool_ptr -> tx_block_pool_suspended_count) + { + + /* The list head has changed, set the list changed flag. */ + list_changed = TX_TRUE; + } + } + + /* Determine if the list has changed. */ + if (list_changed == TX_FALSE) + { + + /* Move the thread pointer to the next thread. */ + thread_ptr = thread_ptr -> tx_thread_suspended_next; + } + else + { + + /* Remember the suspension count and head pointer. */ + head_ptr = pool_ptr -> tx_block_pool_suspension_list; + suspended_count = pool_ptr -> tx_block_pool_suspended_count; + + /* Default the highest priority thread to the thread at the front of the list. */ + priority_thread_ptr = head_ptr; + + /* Setup search pointer. */ + thread_ptr = priority_thread_ptr -> tx_thread_suspended_next; + + /* Reset the list changed flag. */ + list_changed = TX_FALSE; + } + + } while (thread_ptr != head_ptr); + + /* Release preemption. */ + _tx_thread_preempt_disable--; + + /* Now determine if the highest priority thread is at the front + of the list. */ + if (priority_thread_ptr != head_ptr) + { + + /* No, we need to move the highest priority suspended thread to the + front of the list. */ + + /* First, remove the highest priority thread by updating the + adjacent suspended threads. */ + next_thread = priority_thread_ptr -> tx_thread_suspended_next; + previous_thread = priority_thread_ptr -> tx_thread_suspended_previous; + next_thread -> tx_thread_suspended_previous = previous_thread; + previous_thread -> tx_thread_suspended_next = next_thread; + + /* Now, link the highest priority thread at the front of the list. */ + previous_thread = head_ptr -> tx_thread_suspended_previous; + priority_thread_ptr -> tx_thread_suspended_next = head_ptr; + priority_thread_ptr -> tx_thread_suspended_previous = previous_thread; + previous_thread -> tx_thread_suspended_next = priority_thread_ptr; + head_ptr -> tx_thread_suspended_previous = priority_thread_ptr; + + /* Move the list head pointer to the highest priority suspended thread. */ + pool_ptr -> tx_block_pool_suspension_list = priority_thread_ptr; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Check for preemption. */ + _tx_thread_system_preempt_check(); + } + + /* Return successful status. */ + return(TX_SUCCESS); +} + diff --git a/common_smp/src/tx_block_release.c b/common_smp/src/tx_block_release.c new file mode 100644 index 00000000..69e1d442 --- /dev/null +++ b/common_smp/src/tx_block_release.c @@ -0,0 +1,204 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Block Pool */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_thread.h" +#include "tx_block_pool.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_block_release PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function returns a previously allocated block to its */ +/* associated memory block pool. */ +/* */ +/* INPUT */ +/* */ +/* block_ptr Pointer to memory block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SUCCESS Successful completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_system_resume Resume thread service */ +/* _tx_thread_system_ni_resume Non-interruptable resume thread */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_block_release(VOID *block_ptr) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_BLOCK_POOL *pool_ptr; +TX_THREAD *thread_ptr; +UCHAR *work_ptr; +UCHAR **return_block_ptr; +UCHAR **next_block_ptr; +UINT suspended_count; +TX_THREAD *next_thread; +TX_THREAD *previous_thread; + + + /* Disable interrupts to put this block back in the pool. */ + TX_DISABLE + + /* Pickup the pool pointer which is just previous to the starting + address of the block that the caller sees. */ + work_ptr = TX_VOID_TO_UCHAR_POINTER_CONVERT(block_ptr); + work_ptr = TX_UCHAR_POINTER_SUB(work_ptr, (sizeof(UCHAR *))); + next_block_ptr = TX_UCHAR_TO_INDIRECT_UCHAR_POINTER_CONVERT(work_ptr); + pool_ptr = TX_UCHAR_TO_BLOCK_POOL_POINTER_CONVERT((*next_block_ptr)); + +#ifdef TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO + + /* Increment the total releases counter. */ + _tx_block_pool_performance_release_count++; + + /* Increment the number of releases on this pool. */ + pool_ptr -> tx_block_pool_performance_release_count++; +#endif + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_BLOCK_RELEASE, pool_ptr, TX_POINTER_TO_ULONG_CONVERT(block_ptr), pool_ptr -> tx_block_pool_suspended_count, TX_POINTER_TO_ULONG_CONVERT(&work_ptr), TX_TRACE_BLOCK_POOL_EVENTS) + + /* Log this kernel call. */ + TX_EL_BLOCK_RELEASE_INSERT + + /* Determine if there are any threads suspended on the block pool. */ + thread_ptr = pool_ptr -> tx_block_pool_suspension_list; + if (thread_ptr != TX_NULL) + { + + /* Remove the suspended thread from the list. */ + + /* Decrement the number of threads suspended. */ + (pool_ptr -> tx_block_pool_suspended_count)--; + + /* Pickup the suspended count. */ + suspended_count = (pool_ptr -> tx_block_pool_suspended_count); + + /* See if this is the only suspended thread on the list. */ + if (suspended_count == TX_NO_SUSPENSIONS) + { + + /* Yes, the only suspended thread. */ + + /* Update the head pointer. */ + pool_ptr -> tx_block_pool_suspension_list = TX_NULL; + } + else + { + + /* At least one more thread is on the same expiration list. */ + + /* Update the list head pointer. */ + next_thread = thread_ptr -> tx_thread_suspended_next; + pool_ptr -> tx_block_pool_suspension_list = next_thread; + + /* Update the links of the adjacent threads. */ + previous_thread = thread_ptr -> tx_thread_suspended_previous; + next_thread -> tx_thread_suspended_previous = previous_thread; + previous_thread -> tx_thread_suspended_next = next_thread; + } + + /* Prepare for resumption of the first thread. */ + + /* Clear cleanup routine to avoid timeout. */ + thread_ptr -> tx_thread_suspend_cleanup = TX_NULL; + + /* Return this block pointer to the suspended thread waiting for + a block. */ + return_block_ptr = TX_VOID_TO_INDIRECT_UCHAR_POINTER_CONVERT(thread_ptr -> tx_thread_additional_suspend_info); + work_ptr = TX_VOID_TO_UCHAR_POINTER_CONVERT(block_ptr); + *return_block_ptr = work_ptr; + + /* Put return status into the thread control block. */ + thread_ptr -> tx_thread_suspend_status = TX_SUCCESS; + +#ifdef TX_NOT_INTERRUPTABLE + + /* Resume the thread! */ + _tx_thread_system_ni_resume(thread_ptr); + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Resume thread. */ + _tx_thread_system_resume(thread_ptr); +#endif + } + else + { + + /* No thread is suspended for a memory block. */ + + /* Put the block back in the available list. */ + *next_block_ptr = pool_ptr -> tx_block_pool_available_list; + + /* Adjust the head pointer. */ + pool_ptr -> tx_block_pool_available_list = work_ptr; + + /* Increment the count of available blocks. */ + pool_ptr -> tx_block_pool_available++; + + /* Restore interrupts. */ + TX_RESTORE + } + + /* Return successful completion status. */ + return(TX_SUCCESS); +} + diff --git a/common_smp/src/tx_byte_allocate.c b/common_smp/src/tx_byte_allocate.c new file mode 100644 index 00000000..a4cbadf4 --- /dev/null +++ b/common_smp/src/tx_byte_allocate.c @@ -0,0 +1,409 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Byte Memory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#ifdef TX_ENABLE_EVENT_TRACE +#include "tx_trace.h" +#endif +#include "tx_thread.h" +#include "tx_byte_pool.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_byte_allocate PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function allocates bytes from the specified memory byte */ +/* pool. */ +/* */ +/* INPUT */ +/* */ +/* pool_ptr Pointer to pool control block */ +/* memory_ptr Pointer to place allocated bytes */ +/* pointer */ +/* memory_size Number of bytes to allocate */ +/* wait_option Suspension option */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_system_suspend Suspend thread service */ +/* _tx_thread_system_ni_suspend Non-interruptable suspend thread */ +/* _tx_byte_pool_search Search byte pool for memory */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_byte_allocate(TX_BYTE_POOL *pool_ptr, VOID **memory_ptr, ULONG memory_size, ULONG wait_option) +{ + +TX_INTERRUPT_SAVE_AREA + +UINT status; +TX_THREAD *thread_ptr; +UCHAR *work_ptr; +UINT suspended_count; +TX_THREAD *next_thread; +TX_THREAD *previous_thread; +UINT finished; +#ifdef TX_ENABLE_EVENT_TRACE +TX_TRACE_BUFFER_ENTRY *entry_ptr; +ULONG time_stamp = ((ULONG) 0); +#endif +#ifdef TX_ENABLE_EVENT_LOGGING +UCHAR *log_entry_ptr; +ULONG upper_tbu; +ULONG lower_tbu; +#endif + + + /* Round the memory size up to the next size that is evenly divisible by + an ALIGN_TYPE (this is typically a 32-bit ULONG). This guarantees proper alignment. */ + memory_size = (((memory_size + (sizeof(ALIGN_TYPE)))-((ALIGN_TYPE) 1))/(sizeof(ALIGN_TYPE))) * (sizeof(ALIGN_TYPE)); + + /* Disable interrupts. */ + TX_DISABLE + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr) + +#ifdef TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO + + /* Increment the total allocations counter. */ + _tx_byte_pool_performance_allocate_count++; + + /* Increment the number of allocations on this pool. */ + pool_ptr -> tx_byte_pool_performance_allocate_count++; +#endif + +#ifdef TX_ENABLE_EVENT_TRACE + + /* If trace is enabled, save the current event pointer. */ + entry_ptr = _tx_trace_buffer_current_ptr; + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_BYTE_ALLOCATE, pool_ptr, 0, memory_size, wait_option, TX_TRACE_BYTE_POOL_EVENTS) + + /* Save the time stamp for later comparison to verify that + the event hasn't been overwritten by the time the allocate + call succeeds. */ + if (entry_ptr != TX_NULL) + { + + time_stamp = entry_ptr -> tx_trace_buffer_entry_time_stamp; + } +#endif + +#ifdef TX_ENABLE_EVENT_LOGGING + log_entry_ptr = *(UCHAR **) _tx_el_current_event; + + /* Log this kernel call. */ + TX_EL_BYTE_ALLOCATE_INSERT + + /* Store -1 in the fourth event slot. */ + *((ULONG *) (log_entry_ptr + TX_EL_EVENT_INFO_4_OFFSET)) = (ULONG) -1; + + /* Save the time stamp for later comparison to verify that + the event hasn't been overwritten by the time the allocate + call succeeds. */ + lower_tbu = *((ULONG *) (log_entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)); + upper_tbu = *((ULONG *) (log_entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET)); +#endif + + /* Set the search finished flag to false. */ + finished = TX_FALSE; + + /* Loop to handle cases where the owner of the pool changed. */ + do + { + + /* Indicate that this thread is the current owner. */ + pool_ptr -> tx_byte_pool_owner = thread_ptr; + + /* Restore interrupts. */ + TX_RESTORE + + /* At this point, the executing thread owns the pool and can perform a search + for free memory. */ + work_ptr = _tx_byte_pool_search(pool_ptr, memory_size); + + /* Optional processing extension. */ + TX_BYTE_ALLOCATE_EXTENSION + + /* Lockout interrupts. */ + TX_DISABLE + + /* Determine if we are finished. */ + if (work_ptr != TX_NULL) + { + + /* Yes, we have found a block the search is finished. */ + finished = TX_TRUE; + } + else + { + + /* No block was found, does this thread still own the pool? */ + if (pool_ptr -> tx_byte_pool_owner == thread_ptr) + { + + /* Yes, then we have looked through the entire pool and haven't found the memory. */ + finished = TX_TRUE; + } + } + + } while (finished == TX_FALSE); + + /* Copy the pointer into the return destination. */ + *memory_ptr = (VOID *) work_ptr; + + /* Determine if memory was found. */ + if (work_ptr != TX_NULL) + { + +#ifdef TX_ENABLE_EVENT_TRACE + + /* Check that the event time stamp is unchanged. A different + timestamp means that a later event wrote over the byte + allocate event. In that case, do nothing here. */ + if (entry_ptr != TX_NULL) + { + + /* Is the timestamp the same? */ + if (time_stamp == entry_ptr -> tx_trace_buffer_entry_time_stamp) + { + + /* Timestamp is the same, update the entry with the address. */ +#ifdef TX_MISRA_ENABLE + entry_ptr -> tx_trace_buffer_entry_info_2 = TX_POINTER_TO_ULONG_CONVERT(*memory_ptr); +#else + entry_ptr -> tx_trace_buffer_entry_information_field_2 = TX_POINTER_TO_ULONG_CONVERT(*memory_ptr); +#endif + } + } +#endif + +#ifdef TX_ENABLE_EVENT_LOGGING + /* Check that the event time stamp is unchanged. A different + timestamp means that a later event wrote over the byte + allocate event. In that case, do nothing here. */ + if (lower_tbu == *((ULONG *) (log_entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) && + upper_tbu == *((ULONG *) (log_entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET))) + { + /* Store the address of the allocated fragment. */ + *((ULONG *) (log_entry_ptr + TX_EL_EVENT_INFO_4_OFFSET)) = (ULONG) *memory_ptr; + } +#endif + + /* Restore interrupts. */ + TX_RESTORE + + /* Set the status to success. */ + status = TX_SUCCESS; + } + else + { + + /* No memory of sufficient size was found... */ + + /* Determine if the request specifies suspension. */ + if (wait_option != TX_NO_WAIT) + { + + /* Determine if the preempt disable flag is non-zero. */ + if (_tx_thread_preempt_disable != ((UINT) 0)) + { + + /* Suspension is not allowed if the preempt disable flag is non-zero at this point - return error completion. */ + status = TX_NO_MEMORY; + + /* Restore interrupts. */ + TX_RESTORE + } + else + { + + /* Prepare for suspension of this thread. */ + +#ifdef TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO + + /* Increment the total suspensions counter. */ + _tx_byte_pool_performance_suspension_count++; + + /* Increment the number of suspensions on this pool. */ + pool_ptr -> tx_byte_pool_performance_suspension_count++; +#endif + + /* Setup cleanup routine pointer. */ + thread_ptr -> tx_thread_suspend_cleanup = &(_tx_byte_pool_cleanup); + + /* Setup cleanup information, i.e. this pool control + block. */ + thread_ptr -> tx_thread_suspend_control_block = (VOID *) pool_ptr; + + /* Save the return memory pointer address as well. */ + thread_ptr -> tx_thread_additional_suspend_info = (VOID *) memory_ptr; + + /* Save the byte size requested. */ + thread_ptr -> tx_thread_suspend_info = memory_size; + +#ifndef TX_NOT_INTERRUPTABLE + + /* Increment the suspension sequence number, which is used to identify + this suspension event. */ + thread_ptr -> tx_thread_suspension_sequence++; +#endif + + /* Pickup the number of suspended threads. */ + suspended_count = pool_ptr -> tx_byte_pool_suspended_count; + + /* Increment the suspension count. */ + (pool_ptr -> tx_byte_pool_suspended_count)++; + + /* Setup suspension list. */ + if (suspended_count == TX_NO_SUSPENSIONS) + { + + /* No other threads are suspended. Setup the head pointer and + just setup this threads pointers to itself. */ + pool_ptr -> tx_byte_pool_suspension_list = thread_ptr; + thread_ptr -> tx_thread_suspended_next = thread_ptr; + thread_ptr -> tx_thread_suspended_previous = thread_ptr; + } + else + { + + /* This list is not NULL, add current thread to the end. */ + next_thread = pool_ptr -> tx_byte_pool_suspension_list; + thread_ptr -> tx_thread_suspended_next = next_thread; + previous_thread = next_thread -> tx_thread_suspended_previous; + thread_ptr -> tx_thread_suspended_previous = previous_thread; + previous_thread -> tx_thread_suspended_next = thread_ptr; + next_thread -> tx_thread_suspended_previous = thread_ptr; + } + + /* Set the state to suspended. */ + thread_ptr -> tx_thread_state = TX_BYTE_MEMORY; + +#ifdef TX_NOT_INTERRUPTABLE + + /* Call actual non-interruptable thread suspension routine. */ + _tx_thread_system_ni_suspend(thread_ptr, wait_option); + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Set the suspending flag. */ + thread_ptr -> tx_thread_suspending = TX_TRUE; + + /* Setup the timeout period. */ + thread_ptr -> tx_thread_timer.tx_timer_internal_remaining_ticks = wait_option; + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Call actual thread suspension routine. */ + _tx_thread_system_suspend(thread_ptr); +#endif + +#ifdef TX_ENABLE_EVENT_TRACE + + /* Check that the event time stamp is unchanged. A different + timestamp means that a later event wrote over the byte + allocate event. In that case, do nothing here. */ + if (entry_ptr != TX_NULL) + { + + /* Is the timestamp the same? */ + if (time_stamp == entry_ptr -> tx_trace_buffer_entry_time_stamp) + { + + /* Timestamp is the same, update the entry with the address. */ +#ifdef TX_MISRA_ENABLE + entry_ptr -> tx_trace_buffer_entry_info_2 = TX_POINTER_TO_ULONG_CONVERT(*memory_ptr); +#else + entry_ptr -> tx_trace_buffer_entry_information_field_2 = TX_POINTER_TO_ULONG_CONVERT(*memory_ptr); +#endif + } + } +#endif + +#ifdef TX_ENABLE_EVENT_LOGGING + /* Check that the event time stamp is unchanged. A different + timestamp means that a later event wrote over the byte + allocate event. In that case, do nothing here. */ + if (lower_tbu == *((ULONG *) (log_entry_ptr + TX_EL_EVENT_TIME_LOWER_OFFSET)) && + upper_tbu == *((ULONG *) (log_entry_ptr + TX_EL_EVENT_TIME_UPPER_OFFSET))) + { + + /* Store the address of the allocated fragment. */ + *((ULONG *) (log_entry_ptr + TX_EL_EVENT_INFO_4_OFFSET)) = (ULONG) *memory_ptr; + } +#endif + + /* Return the completion status. */ + status = thread_ptr -> tx_thread_suspend_status; + } + } + else + { + + /* Restore interrupts. */ + TX_RESTORE + + /* Immediate return, return error completion. */ + status = TX_NO_MEMORY; + } + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/tx_byte_pool_cleanup.c b/common_smp/src/tx_byte_pool_cleanup.c new file mode 100644 index 00000000..6beca7c2 --- /dev/null +++ b/common_smp/src/tx_byte_pool_cleanup.c @@ -0,0 +1,212 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Byte Memory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_byte_pool.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_byte_pool_cleanup PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes byte allocate timeout and thread terminate */ +/* actions that require the byte pool data structures to be cleaned */ +/* up. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to suspended thread's */ +/* control block */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_system_resume Resume thread service */ +/* _tx_thread_system_ni_resume Non-interruptable resume thread */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_timeout Thread timeout processing */ +/* _tx_thread_terminate Thread terminate processing */ +/* _tx_thread_wait_abort Thread wait abort processing */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_byte_pool_cleanup(TX_THREAD *thread_ptr, ULONG suspension_sequence) +{ + +#ifndef TX_NOT_INTERRUPTABLE +TX_INTERRUPT_SAVE_AREA +#endif + +TX_BYTE_POOL *pool_ptr; +UINT suspended_count; +TX_THREAD *next_thread; +TX_THREAD *previous_thread; + + +#ifndef TX_NOT_INTERRUPTABLE + + /* Disable interrupts to remove the suspended thread from the byte pool. */ + TX_DISABLE + + /* Determine if the cleanup is still required. */ + if (thread_ptr -> tx_thread_suspend_cleanup == &(_tx_byte_pool_cleanup)) + { + + /* Check for valid suspension sequence. */ + if (suspension_sequence == thread_ptr -> tx_thread_suspension_sequence) + { + + /* Setup pointer to byte pool control block. */ + pool_ptr = TX_VOID_TO_BYTE_POOL_POINTER_CONVERT(thread_ptr -> tx_thread_suspend_control_block); + + /* Check for a NULL byte pool pointer. */ + if (pool_ptr != TX_NULL) + { + + /* Check for valid pool ID. */ + if (pool_ptr -> tx_byte_pool_id == TX_BYTE_POOL_ID) + { + + /* Determine if there are any thread suspensions. */ + if (pool_ptr -> tx_byte_pool_suspended_count != TX_NO_SUSPENSIONS) + { +#else + + /* Setup pointer to byte pool control block. */ + pool_ptr = TX_VOID_TO_BYTE_POOL_POINTER_CONVERT(thread_ptr -> tx_thread_suspend_control_block); +#endif + + /* Thread suspended for memory... Clear the suspension cleanup flag. */ + thread_ptr -> tx_thread_suspend_cleanup = TX_NULL; + + /* Decrement the suspension count. */ + pool_ptr -> tx_byte_pool_suspended_count--; + + /* Pickup the suspended count. */ + suspended_count = pool_ptr -> tx_byte_pool_suspended_count; + + /* Remove the suspended thread from the list. */ + + /* See if this is the only suspended thread on the list. */ + if (suspended_count == TX_NO_SUSPENSIONS) + { + + /* Yes, the only suspended thread. */ + + /* Update the head pointer. */ + pool_ptr -> tx_byte_pool_suspension_list = TX_NULL; + } + else + { + + /* At least one more thread is on the same suspension list. */ + + /* Update the links of the adjacent threads. */ + next_thread = thread_ptr -> tx_thread_suspended_next; + previous_thread = thread_ptr -> tx_thread_suspended_previous; + next_thread -> tx_thread_suspended_previous = previous_thread; + previous_thread -> tx_thread_suspended_next = next_thread; + + /* Determine if we need to update the head pointer. */ + if (pool_ptr -> tx_byte_pool_suspension_list == thread_ptr) + { + + /* Update the list head pointer. */ + pool_ptr -> tx_byte_pool_suspension_list = next_thread; + } + } + + /* Now we need to determine if this cleanup is from a terminate, timeout, + or from a wait abort. */ + if (thread_ptr -> tx_thread_state == TX_BYTE_MEMORY) + { + + /* Timeout condition and the thread still suspended on the byte pool. + Setup return error status and resume the thread. */ + +#ifdef TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO + + /* Increment the total timeouts counter. */ + _tx_byte_pool_performance_timeout_count++; + + /* Increment the number of timeouts on this byte pool. */ + pool_ptr -> tx_byte_pool_performance_timeout_count++; +#endif + + /* Setup return status. */ + thread_ptr -> tx_thread_suspend_status = TX_NO_MEMORY; + +#ifdef TX_NOT_INTERRUPTABLE + + /* Resume the thread! */ + _tx_thread_system_ni_resume(thread_ptr); +#else + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Resume the thread! */ + _tx_thread_system_resume(thread_ptr); + + /* Disable interrupts. */ + TX_DISABLE +#endif + } +#ifndef TX_NOT_INTERRUPTABLE + } + } + } + } + } + + /* Restore interrupts. */ + TX_RESTORE +#endif +} + diff --git a/common_smp/src/tx_byte_pool_create.c b/common_smp/src/tx_byte_pool_create.c new file mode 100644 index 00000000..25075458 --- /dev/null +++ b/common_smp/src/tx_byte_pool_create.c @@ -0,0 +1,197 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Byte Pool */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_byte_pool.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_byte_pool_create PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates a pool of memory bytes in the specified */ +/* memory area. */ +/* */ +/* INPUT */ +/* */ +/* pool_ptr Pointer to pool control block */ +/* name_ptr Pointer to byte pool name */ +/* pool_start Address of beginning of pool area */ +/* pool_size Number of bytes in the byte pool */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SUCCESS Successful completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_byte_pool_create(TX_BYTE_POOL *pool_ptr, CHAR *name_ptr, VOID *pool_start, ULONG pool_size) +{ + +TX_INTERRUPT_SAVE_AREA + +UCHAR *block_ptr; +UCHAR **block_indirect_ptr; +UCHAR *temp_ptr; +TX_BYTE_POOL *next_pool; +TX_BYTE_POOL *previous_pool; +ALIGN_TYPE *free_ptr; + + + /* Initialize the byte pool control block to all zeros. */ + TX_MEMSET(pool_ptr, 0, (sizeof(TX_BYTE_POOL))); + + /* Round the pool size down to something that is evenly divisible by + an ULONG. */ + pool_size = (pool_size/(sizeof(ALIGN_TYPE))) * (sizeof(ALIGN_TYPE)); + + /* Setup the basic byte pool fields. */ + pool_ptr -> tx_byte_pool_name = name_ptr; + + /* Save the start and size of the pool. */ + pool_ptr -> tx_byte_pool_start = TX_VOID_TO_UCHAR_POINTER_CONVERT(pool_start); + pool_ptr -> tx_byte_pool_size = pool_size; + + /* Setup memory list to the beginning as well as the search pointer. */ + pool_ptr -> tx_byte_pool_list = TX_VOID_TO_UCHAR_POINTER_CONVERT(pool_start); + pool_ptr -> tx_byte_pool_search = TX_VOID_TO_UCHAR_POINTER_CONVERT(pool_start); + + /* Initially, the pool will have two blocks. One large block at the + beginning that is available and a small allocated block at the end + of the pool that is there just for the algorithm. Be sure to count + the available block's header in the available bytes count. */ + pool_ptr -> tx_byte_pool_available = pool_size - ((sizeof(VOID *)) + (sizeof(ALIGN_TYPE))); + pool_ptr -> tx_byte_pool_fragments = ((UINT) 2); + + /* Each block contains a "next" pointer that points to the next block in the pool followed by a ALIGN_TYPE + field that contains either the constant TX_BYTE_BLOCK_FREE (if the block is free) or a pointer to the + owning pool (if the block is allocated). */ + + /* Calculate the end of the pool's memory area. */ + block_ptr = TX_VOID_TO_UCHAR_POINTER_CONVERT(pool_start); + block_ptr = TX_UCHAR_POINTER_ADD(block_ptr, pool_size); + + /* Backup the end of the pool pointer and build the pre-allocated block. */ + block_ptr = TX_UCHAR_POINTER_SUB(block_ptr, (sizeof(ALIGN_TYPE))); + + /* Cast the pool pointer into a ULONG. */ + temp_ptr = TX_BYTE_POOL_TO_UCHAR_POINTER_CONVERT(pool_ptr); + block_indirect_ptr = TX_UCHAR_TO_INDIRECT_UCHAR_POINTER_CONVERT(block_ptr); + *block_indirect_ptr = temp_ptr; + + block_ptr = TX_UCHAR_POINTER_SUB(block_ptr, (sizeof(UCHAR *))); + block_indirect_ptr = TX_UCHAR_TO_INDIRECT_UCHAR_POINTER_CONVERT(block_ptr); + *block_indirect_ptr = TX_VOID_TO_UCHAR_POINTER_CONVERT(pool_start); + + /* Now setup the large available block in the pool. */ + temp_ptr = TX_VOID_TO_UCHAR_POINTER_CONVERT(pool_start); + block_indirect_ptr = TX_UCHAR_TO_INDIRECT_UCHAR_POINTER_CONVERT(temp_ptr); + *block_indirect_ptr = block_ptr; + block_ptr = TX_VOID_TO_UCHAR_POINTER_CONVERT(pool_start); + block_ptr = TX_UCHAR_POINTER_ADD(block_ptr, (sizeof(UCHAR *))); + free_ptr = TX_UCHAR_TO_ALIGN_TYPE_POINTER_CONVERT(block_ptr); + *free_ptr = TX_BYTE_BLOCK_FREE; + + /* Clear the owner id. */ + pool_ptr -> tx_byte_pool_owner = TX_NULL; + + /* Disable interrupts to place the byte pool on the created list. */ + TX_DISABLE + + /* Setup the byte pool ID to make it valid. */ + pool_ptr -> tx_byte_pool_id = TX_BYTE_POOL_ID; + + /* Place the byte pool on the list of created byte pools. First, + check for an empty list. */ + if (_tx_byte_pool_created_count == TX_EMPTY) + { + + /* The created byte pool list is empty. Add byte pool to empty list. */ + _tx_byte_pool_created_ptr = pool_ptr; + pool_ptr -> tx_byte_pool_created_next = pool_ptr; + pool_ptr -> tx_byte_pool_created_previous = pool_ptr; + } + else + { + + /* This list is not NULL, add to the end of the list. */ + next_pool = _tx_byte_pool_created_ptr; + previous_pool = next_pool -> tx_byte_pool_created_previous; + + /* Place the new byte pool in the list. */ + next_pool -> tx_byte_pool_created_previous = pool_ptr; + previous_pool -> tx_byte_pool_created_next = pool_ptr; + + /* Setup this byte pool's created links. */ + pool_ptr -> tx_byte_pool_created_previous = previous_pool; + pool_ptr -> tx_byte_pool_created_next = next_pool; + } + + /* Increment the number of created byte pools. */ + _tx_byte_pool_created_count++; + + /* Optional byte pool create extended processing. */ + TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) + + /* If trace is enabled, register this object. */ + TX_TRACE_OBJECT_REGISTER(TX_TRACE_OBJECT_TYPE_BYTE_POOL, pool_ptr, name_ptr, pool_size, 0) + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_BYTE_POOL_CREATE, pool_ptr, TX_POINTER_TO_ULONG_CONVERT(pool_start), pool_size, TX_POINTER_TO_ULONG_CONVERT(&block_ptr), TX_TRACE_BYTE_POOL_EVENTS) + + /* Log this kernel call. */ + TX_EL_BYTE_POOL_CREATE_INSERT + + /* Restore interrupts. */ + TX_RESTORE + + /* Return TX_SUCCESS. */ + return(TX_SUCCESS); +} + diff --git a/common_smp/src/tx_byte_pool_delete.c b/common_smp/src/tx_byte_pool_delete.c new file mode 100644 index 00000000..c4c84e38 --- /dev/null +++ b/common_smp/src/tx_byte_pool_delete.c @@ -0,0 +1,211 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Byte Pool */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_thread.h" +#include "tx_byte_pool.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_byte_pool_delete PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function deletes the specified byte pool. All threads */ +/* suspended on the byte pool are resumed with the TX_DELETED status */ +/* code. */ +/* */ +/* It is important to note that the byte pool being deleted, or the */ +/* memory associated with it should not be in use when this function */ +/* is called. */ +/* */ +/* INPUT */ +/* */ +/* pool_ptr Pointer to pool control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SUCCESS Successful completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_system_preempt_check Check for preemption */ +/* _tx_thread_system_resume Resume thread service */ +/* _tx_thread_system_ni_resume Non-interruptable resume thread */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_byte_pool_delete(TX_BYTE_POOL *pool_ptr) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_THREAD *thread_ptr; +TX_THREAD *next_thread; +UINT suspended_count; +TX_BYTE_POOL *next_pool; +TX_BYTE_POOL *previous_pool; + + + /* Disable interrupts to remove the byte pool from the created list. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_BYTE_POOL_DELETE, pool_ptr, TX_POINTER_TO_ULONG_CONVERT(&thread_ptr), 0, 0, TX_TRACE_BYTE_POOL_EVENTS) + + /* Optional byte pool delete extended processing. */ + TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) + + /* If trace is enabled, unregister this object. */ + TX_TRACE_OBJECT_UNREGISTER(pool_ptr) + + /* Log this kernel call. */ + TX_EL_BYTE_POOL_DELETE_INSERT + + /* Clear the byte pool ID to make it invalid. */ + pool_ptr -> tx_byte_pool_id = TX_CLEAR_ID; + + /* Decrement the number of byte pools created. */ + _tx_byte_pool_created_count--; + + /* See if the byte pool is the only one on the list. */ + if (_tx_byte_pool_created_count == TX_EMPTY) + { + + /* Only created byte pool, just set the created list to NULL. */ + _tx_byte_pool_created_ptr = TX_NULL; + } + else + { + + /* Link-up the neighbors. */ + next_pool = pool_ptr -> tx_byte_pool_created_next; + previous_pool = pool_ptr -> tx_byte_pool_created_previous; + next_pool -> tx_byte_pool_created_previous = previous_pool; + previous_pool -> tx_byte_pool_created_next = next_pool; + + /* See if we have to update the created list head pointer. */ + if (_tx_byte_pool_created_ptr == pool_ptr) + { + + /* Yes, move the head pointer to the next link. */ + _tx_byte_pool_created_ptr = next_pool; + } + } + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Pickup the suspension information. */ + thread_ptr = pool_ptr -> tx_byte_pool_suspension_list; + pool_ptr -> tx_byte_pool_suspension_list = TX_NULL; + suspended_count = pool_ptr -> tx_byte_pool_suspended_count; + pool_ptr -> tx_byte_pool_suspended_count = TX_NO_SUSPENSIONS; + + /* Restore interrupts. */ + TX_RESTORE + + /* Walk through the byte pool list to resume any and all threads suspended + on this byte pool. */ + while (suspended_count != TX_NO_SUSPENSIONS) + { + + /* Decrement the suspension count. */ + suspended_count--; + + /* Lockout interrupts. */ + TX_DISABLE + + /* Clear the cleanup pointer, this prevents the timeout from doing + anything. */ + thread_ptr -> tx_thread_suspend_cleanup = TX_NULL; + + /* Set the return status in the thread to TX_DELETED. */ + thread_ptr -> tx_thread_suspend_status = TX_DELETED; + + /* Move the thread pointer ahead. */ + next_thread = thread_ptr -> tx_thread_suspended_next; + +#ifdef TX_NOT_INTERRUPTABLE + + /* Resume the thread! */ + _tx_thread_system_ni_resume(thread_ptr); + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Temporarily disable preemption again. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Resume the thread. */ + _tx_thread_system_resume(thread_ptr); +#endif + + /* Move to next thread. */ + thread_ptr = next_thread; + } + + /* Execute Port-Specific completion processing. If needed, it is typically defined in tx_port.h. */ + TX_BYTE_POOL_DELETE_PORT_COMPLETION(pool_ptr) + + /* Disable interrupts. */ + TX_DISABLE + + /* Release previous preempt disable. */ + _tx_thread_preempt_disable--; + + /* Restore interrupts. */ + TX_RESTORE + + /* Check for preemption. */ + _tx_thread_system_preempt_check(); + + /* Return TX_SUCCESS. */ + return(TX_SUCCESS); +} + diff --git a/common_smp/src/tx_byte_pool_info_get.c b/common_smp/src/tx_byte_pool_info_get.c new file mode 100644 index 00000000..028c251b --- /dev/null +++ b/common_smp/src/tx_byte_pool_info_get.c @@ -0,0 +1,146 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Byte Memory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_byte_pool.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_byte_pool_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves information from the specified byte pool. */ +/* */ +/* INPUT */ +/* */ +/* pool_ptr Pointer to byte pool control block*/ +/* name Destination for the pool name */ +/* available_bytes Number of free bytes in byte pool */ +/* fragments Number of fragments in byte pool */ +/* first_suspended Destination for pointer of first */ +/* thread suspended on byte pool */ +/* suspended_count Destination for suspended count */ +/* next_pool Destination for pointer to next */ +/* byte pool on the created list */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_byte_pool_info_get(TX_BYTE_POOL *pool_ptr, CHAR **name, ULONG *available_bytes, + ULONG *fragments, TX_THREAD **first_suspended, + ULONG *suspended_count, TX_BYTE_POOL **next_pool) +{ + +TX_INTERRUPT_SAVE_AREA + + + /* Disable interrupts. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_BYTE_POOL_INFO_GET, pool_ptr, 0, 0, 0, TX_TRACE_BYTE_POOL_EVENTS) + + /* Log this kernel call. */ + TX_EL_BYTE_POOL_INFO_GET_INSERT + + /* Retrieve all the pertinent information and return it in the supplied + destinations. */ + + /* Retrieve the name of the byte pool. */ + if (name != TX_NULL) + { + + *name = pool_ptr -> tx_byte_pool_name; + } + + /* Retrieve the number of available bytes in the byte pool. */ + if (available_bytes != TX_NULL) + { + + *available_bytes = pool_ptr -> tx_byte_pool_available; + } + + /* Retrieve the total number of bytes in the byte pool. */ + if (fragments != TX_NULL) + { + + *fragments = (ULONG) pool_ptr -> tx_byte_pool_fragments; + } + + /* Retrieve the first thread suspended on this byte pool. */ + if (first_suspended != TX_NULL) + { + + *first_suspended = pool_ptr -> tx_byte_pool_suspension_list; + } + + /* Retrieve the number of threads suspended on this byte pool. */ + if (suspended_count != TX_NULL) + { + + *suspended_count = (ULONG) pool_ptr -> tx_byte_pool_suspended_count; + } + + /* Retrieve the pointer to the next byte pool created. */ + if (next_pool != TX_NULL) + { + + *next_pool = pool_ptr -> tx_byte_pool_created_next; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return completion status. */ + return(TX_SUCCESS); +} + diff --git a/common_smp/src/tx_byte_pool_initialize.c b/common_smp/src/tx_byte_pool_initialize.c new file mode 100644 index 00000000..5ad4c1cb --- /dev/null +++ b/common_smp/src/tx_byte_pool_initialize.c @@ -0,0 +1,147 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Byte Pool */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_byte_pool.h" + + +#ifndef TX_INLINE_INITIALIZATION + +/* Locate byte pool component data in this file. */ + +/* Define the head pointer of the created byte pool list. */ + +TX_BYTE_POOL * _tx_byte_pool_created_ptr; + + +/* Define the variable that holds the number of created byte pools. */ + +ULONG _tx_byte_pool_created_count; + + +#ifdef TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO + +/* Define the total number of allocates. */ + +ULONG _tx_byte_pool_performance_allocate_count; + + +/* Define the total number of releases. */ + +ULONG _tx_byte_pool_performance_release_count; + + +/* Define the total number of adjacent memory fragment merges. */ + +ULONG _tx_byte_pool_performance_merge_count; + + +/* Define the total number of memory fragment splits. */ + +ULONG _tx_byte_pool_performance_split_count; + + +/* Define the total number of memory fragments searched during allocation. */ + +ULONG _tx_byte_pool_performance_search_count; + + +/* Define the total number of byte pool suspensions. */ + +ULONG _tx_byte_pool_performance_suspension_count; + + +/* Define the total number of byte pool timeouts. */ + +ULONG _tx_byte_pool_performance_timeout_count; + +#endif +#endif + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_byte_pool_initialize PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes the various control data structures for */ +/* the byte pool component. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_high_level High level initialization */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_byte_pool_initialize(VOID) +{ + +#ifndef TX_DISABLE_REDUNDANT_CLEARING + + /* Initialize the head pointer of the created byte pools list and the + number of byte pools created. */ + _tx_byte_pool_created_ptr = TX_NULL; + _tx_byte_pool_created_count = TX_EMPTY; + +#ifdef TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO + + /* Initialize byte pool performance counters. */ + _tx_byte_pool_performance_allocate_count = ((ULONG) 0); + _tx_byte_pool_performance_release_count = ((ULONG) 0); + _tx_byte_pool_performance_merge_count = ((ULONG) 0); + _tx_byte_pool_performance_split_count = ((ULONG) 0); + _tx_byte_pool_performance_search_count = ((ULONG) 0); + _tx_byte_pool_performance_suspension_count = ((ULONG) 0); + _tx_byte_pool_performance_timeout_count = ((ULONG) 0); +#endif +#endif +} + diff --git a/common_smp/src/tx_byte_pool_performance_info_get.c b/common_smp/src/tx_byte_pool_performance_info_get.c new file mode 100644 index 00000000..0c93e270 --- /dev/null +++ b/common_smp/src/tx_byte_pool_performance_info_get.c @@ -0,0 +1,253 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Byte Memory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_byte_pool.h" +#ifdef TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO +#include "tx_trace.h" +#endif + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_byte_pool_performance_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves performance information from the specified */ +/* byte pool. */ +/* */ +/* INPUT */ +/* */ +/* pool_ptr Pointer to byte pool control block*/ +/* allocates Destination for number of */ +/* allocates on this pool */ +/* releases Destination for number of */ +/* releases on this pool */ +/* fragments_searched Destination for number of */ +/* fragments searched during */ +/* allocation */ +/* merges Destination for number of adjacent*/ +/* free fragments merged */ +/* splits Destination for number of */ +/* fragments split during */ +/* allocation */ +/* suspensions Destination for number of */ +/* suspensions on this pool */ +/* timeouts Destination for number of timeouts*/ +/* on this byte pool */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_byte_pool_performance_info_get(TX_BYTE_POOL *pool_ptr, ULONG *allocates, ULONG *releases, + ULONG *fragments_searched, ULONG *merges, ULONG *splits, ULONG *suspensions, ULONG *timeouts) +{ + +#ifdef TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO + +TX_INTERRUPT_SAVE_AREA + +UINT status; + + + /* Determine if this is a legal request. */ + if (pool_ptr == TX_NULL) + { + + /* Byte pool pointer is illegal, return error. */ + status = TX_PTR_ERROR; + } + + /* Determine if the pool ID is invalid. */ + else if (pool_ptr -> tx_byte_pool_id != TX_BYTE_POOL_ID) + { + + /* Byte pool pointer is illegal, return error. */ + status = TX_PTR_ERROR; + } + else + { + + /* Disable interrupts. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_BYTE_POOL_PERFORMANCE_INFO_GET, pool_ptr, 0, 0, 0, TX_TRACE_BYTE_POOL_EVENTS) + + /* Log this kernel call. */ + TX_EL_BYTE_POOL_PERFORMANCE_INFO_GET_INSERT + + /* Retrieve all the pertinent information and return it in the supplied + destinations. */ + + /* Retrieve the number of allocates on this byte pool. */ + if (allocates != TX_NULL) + { + + *allocates = pool_ptr -> tx_byte_pool_performance_allocate_count; + } + + /* Retrieve the number of releases on this byte pool. */ + if (releases != TX_NULL) + { + + *releases = pool_ptr -> tx_byte_pool_performance_release_count; + } + + /* Retrieve the number of fragments searched in this byte pool. */ + if (fragments_searched != TX_NULL) + { + + *fragments_searched = pool_ptr -> tx_byte_pool_performance_search_count; + } + + /* Retrieve the number of fragments merged on this byte pool. */ + if (merges != TX_NULL) + { + + *merges = pool_ptr -> tx_byte_pool_performance_merge_count; + } + + /* Retrieve the number of fragment splits on this byte pool. */ + if (splits != TX_NULL) + { + + *splits = pool_ptr -> tx_byte_pool_performance_split_count; + } + + /* Retrieve the number of suspensions on this byte pool. */ + if (suspensions != TX_NULL) + { + + *suspensions = pool_ptr -> tx_byte_pool_performance_suspension_count; + } + + /* Retrieve the number of timeouts on this byte pool. */ + if (timeouts != TX_NULL) + { + + *timeouts = pool_ptr -> tx_byte_pool_performance_timeout_count; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return completion status. */ + status = TX_SUCCESS; + } + + /* Return completion status. */ + return(status); +#else + +UINT status; + + + /* Access input arguments just for the sake of lint, MISRA, etc. */ + if (pool_ptr != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (allocates != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (releases != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (fragments_searched != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (merges != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (splits != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (suspensions != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (timeouts != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + + /* Return completion status. */ + return(status); +#endif +} + diff --git a/common_smp/src/tx_byte_pool_performance_system_info_get.c b/common_smp/src/tx_byte_pool_performance_system_info_get.c new file mode 100644 index 00000000..67c84cbf --- /dev/null +++ b/common_smp/src/tx_byte_pool_performance_system_info_get.c @@ -0,0 +1,221 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Byte Memory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_byte_pool.h" +#ifdef TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO +#include "tx_trace.h" +#endif + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_byte_pool_performance_system_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves byte pool performance information. */ +/* */ +/* INPUT */ +/* */ +/* allocates Destination for total number of */ +/* allocates */ +/* releases Destination for total number of */ +/* releases */ +/* fragments_searched Destination for total number of */ +/* fragments searched during */ +/* allocation */ +/* merges Destination for total number of */ +/* adjacent free fragments merged */ +/* splits Destination for total number of */ +/* fragments split during */ +/* allocation */ +/* suspensions Destination for total number of */ +/* suspensions */ +/* timeouts Destination for total number of */ +/* timeouts */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_byte_pool_performance_system_info_get(ULONG *allocates, ULONG *releases, + ULONG *fragments_searched, ULONG *merges, ULONG *splits, ULONG *suspensions, ULONG *timeouts) +{ + +#ifdef TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO + +TX_INTERRUPT_SAVE_AREA + + + /* Disable interrupts. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_BYTE_POOL__PERFORMANCE_SYSTEM_INFO_GET, 0, 0, 0, 0, TX_TRACE_BYTE_POOL_EVENTS) + + /* Log this kernel call. */ + TX_EL_BYTE_POOL_PERFORMANCE_SYSTEM_INFO_GET_INSERT + + /* Retrieve all the pertinent information and return it in the supplied + destinations. */ + + /* Retrieve the total number of byte pool allocates. */ + if (allocates != TX_NULL) + { + + *allocates = _tx_byte_pool_performance_allocate_count; + } + + /* Retrieve the total number of byte pool releases. */ + if (releases != TX_NULL) + { + + *releases = _tx_byte_pool_performance_release_count; + } + + /* Retrieve the total number of byte pool fragments searched. */ + if (fragments_searched != TX_NULL) + { + + *fragments_searched = _tx_byte_pool_performance_search_count; + } + + /* Retrieve the total number of byte pool fragments merged. */ + if (merges != TX_NULL) + { + + *merges = _tx_byte_pool_performance_merge_count; + } + + /* Retrieve the total number of byte pool fragment splits. */ + if (splits != TX_NULL) + { + + *splits = _tx_byte_pool_performance_split_count; + } + + /* Retrieve the total number of byte pool suspensions. */ + if (suspensions != TX_NULL) + { + + *suspensions = _tx_byte_pool_performance_suspension_count; + } + + /* Retrieve the total number of byte pool timeouts. */ + if (timeouts != TX_NULL) + { + + *timeouts = _tx_byte_pool_performance_timeout_count; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return completion status. */ + return(TX_SUCCESS); + +#else + +UINT status; + + + /* Access input arguments just for the sake of lint, MISRA, etc. */ + if (allocates != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (releases != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (fragments_searched != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (merges != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (splits != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (suspensions != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (timeouts != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + + /* Return completion status. */ + return(status); +#endif +} + diff --git a/common_smp/src/tx_byte_pool_prioritize.c b/common_smp/src/tx_byte_pool_prioritize.c new file mode 100644 index 00000000..516bd67e --- /dev/null +++ b/common_smp/src/tx_byte_pool_prioritize.c @@ -0,0 +1,249 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Byte Memory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_thread.h" +#include "tx_byte_pool.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_byte_pool_prioritize PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function places the highest priority suspended thread at the */ +/* front of the suspension list. All other threads remain in the same */ +/* FIFO suspension order. */ +/* */ +/* INPUT */ +/* */ +/* pool_ptr Pointer to pool control block */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_system_preempt_check Check for preemption */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_byte_pool_prioritize(TX_BYTE_POOL *pool_ptr) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_THREAD *thread_ptr; +TX_THREAD *priority_thread_ptr; +TX_THREAD *head_ptr; +UINT suspended_count; +TX_THREAD *next_thread; +TX_THREAD *previous_thread; +UINT list_changed; + + + /* Disable interrupts. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_BYTE_POOL_PRIORITIZE, pool_ptr, pool_ptr -> tx_byte_pool_suspended_count, TX_POINTER_TO_ULONG_CONVERT(&suspended_count), 0, TX_TRACE_BYTE_POOL_EVENTS) + + /* Log this kernel call. */ + TX_EL_BYTE_POOL_PRIORITIZE_INSERT + + /* Pickup the suspended count. */ + suspended_count = pool_ptr -> tx_byte_pool_suspended_count; + + /* Determine if there are fewer than 2 suspended threads. */ + if (suspended_count < ((UINT) 2)) + { + + /* Restore interrupts. */ + TX_RESTORE + } + + /* Determine if there how many threads are suspended on this byte memory pool. */ + else if (suspended_count == ((UINT) 2)) + { + + /* Pickup the head pointer and the next pointer. */ + head_ptr = pool_ptr -> tx_byte_pool_suspension_list; + next_thread = head_ptr -> tx_thread_suspended_next; + + /* Determine if the next suspended thread has a higher priority. */ + if ((next_thread -> tx_thread_priority) < (head_ptr -> tx_thread_priority)) + { + + /* Yes, move the list head to the next thread. */ + pool_ptr -> tx_byte_pool_suspension_list = next_thread; + } + + /* Restore interrupts. */ + TX_RESTORE + } + else + { + + /* Remember the suspension count and head pointer. */ + head_ptr = pool_ptr -> tx_byte_pool_suspension_list; + + /* Default the highest priority thread to the thread at the front of the list. */ + priority_thread_ptr = head_ptr; + + /* Setup search pointer. */ + thread_ptr = priority_thread_ptr -> tx_thread_suspended_next; + + /* Disable preemption. */ + _tx_thread_preempt_disable++; + + /* Set the list changed flag to false. */ + list_changed = TX_FALSE; + + /* Search through the list to find the highest priority thread. */ + do + { + + /* Is the current thread higher priority? */ + if (thread_ptr -> tx_thread_priority < priority_thread_ptr -> tx_thread_priority) + { + + /* Yes, remember that this thread is the highest priority. */ + priority_thread_ptr = thread_ptr; + } + + /* Restore interrupts temporarily. */ + TX_RESTORE + + /* Disable interrupts again. */ + TX_DISABLE + + /* Determine if any changes to the list have occurred while + interrupts were enabled. */ + + /* Is the list head the same? */ + if (head_ptr != pool_ptr -> tx_byte_pool_suspension_list) + { + + /* The list head has changed, set the list changed flag. */ + list_changed = TX_TRUE; + } + else + { + + /* Is the suspended count the same? */ + if (suspended_count != pool_ptr -> tx_byte_pool_suspended_count) + { + + /* The list head has changed, set the list changed flag. */ + list_changed = TX_TRUE; + } + } + + /* Determine if the list has changed. */ + if (list_changed == TX_FALSE) + { + + /* Move the thread pointer to the next thread. */ + thread_ptr = thread_ptr -> tx_thread_suspended_next; + } + else + { + + /* Remember the suspension count and head pointer. */ + head_ptr = pool_ptr -> tx_byte_pool_suspension_list; + suspended_count = pool_ptr -> tx_byte_pool_suspended_count; + + /* Default the highest priority thread to the thread at the front of the list. */ + priority_thread_ptr = head_ptr; + + /* Setup search pointer. */ + thread_ptr = priority_thread_ptr -> tx_thread_suspended_next; + + /* Reset the list changed flag. */ + list_changed = TX_FALSE; + } + + } while (thread_ptr != head_ptr); + + /* Release preemption. */ + _tx_thread_preempt_disable--; + + /* Now determine if the highest priority thread is at the front + of the list. */ + if (priority_thread_ptr != head_ptr) + { + + /* No, we need to move the highest priority suspended thread to the + front of the list. */ + + /* First, remove the highest priority thread by updating the + adjacent suspended threads. */ + next_thread = priority_thread_ptr -> tx_thread_suspended_next; + previous_thread = priority_thread_ptr -> tx_thread_suspended_previous; + next_thread -> tx_thread_suspended_previous = previous_thread; + previous_thread -> tx_thread_suspended_next = next_thread; + + /* Now, link the highest priority thread at the front of the list. */ + previous_thread = head_ptr -> tx_thread_suspended_previous; + priority_thread_ptr -> tx_thread_suspended_next = head_ptr; + priority_thread_ptr -> tx_thread_suspended_previous = previous_thread; + previous_thread -> tx_thread_suspended_next = priority_thread_ptr; + head_ptr -> tx_thread_suspended_previous = priority_thread_ptr; + + /* Move the list head pointer to the highest priority suspended thread. */ + pool_ptr -> tx_byte_pool_suspension_list = priority_thread_ptr; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Check for preemption. */ + _tx_thread_system_preempt_check(); + } + + /* Return completion status. */ + return(TX_SUCCESS); +} + diff --git a/common_smp/src/tx_byte_pool_search.c b/common_smp/src/tx_byte_pool_search.c new file mode 100644 index 00000000..18dbe2b8 --- /dev/null +++ b/common_smp/src/tx_byte_pool_search.c @@ -0,0 +1,378 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Byte Pool */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_byte_pool.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_byte_pool_search PORTABLE SMP */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function searches a byte pool for a memory block to satisfy */ +/* the requested number of bytes. Merging of adjacent free blocks */ +/* takes place during the search and a split of the block that */ +/* satisfies the request may occur before this function returns. */ +/* */ +/* It is assumed that this function is called with interrupts enabled */ +/* and with the tx_pool_owner field set to the thread performing the */ +/* search. Also note that the search can occur during allocation and */ +/* release of a memory block. */ +/* */ +/* INPUT */ +/* */ +/* pool_ptr Pointer to pool control block */ +/* memory_size Number of bytes required */ +/* */ +/* OUTPUT */ +/* */ +/* UCHAR * Pointer to the allocated memory, */ +/* if successful. Otherwise, a */ +/* NULL is returned */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_byte_allocate Allocate bytes of memory */ +/* _tx_byte_release Release bytes of memory */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UCHAR *_tx_byte_pool_search(TX_BYTE_POOL *pool_ptr, ULONG memory_size) +{ + +TX_INTERRUPT_SAVE_AREA + +UCHAR *current_ptr; +UCHAR *next_ptr; +UCHAR **this_block_link_ptr; +UCHAR **next_block_link_ptr; +ULONG available_bytes; +UINT examine_blocks; +UINT first_free_block_found = TX_FALSE; +TX_THREAD *thread_ptr; +ALIGN_TYPE *free_ptr; +UCHAR *work_ptr; + +#ifdef TX_BYTE_POOL_MULTIPLE_BLOCK_SEARCH +UINT blocks_searched = ((UINT) 0); +#endif + + + /* Disable interrupts. */ + TX_DISABLE + + /* First, determine if there are enough bytes in the pool. */ + if (memory_size >= pool_ptr -> tx_byte_pool_available) + { + + /* Restore interrupts. */ + TX_RESTORE + + /* Not enough memory, return a NULL pointer. */ + current_ptr = TX_NULL; + } + else + { + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr) + + /* Setup ownership of the byte pool. */ + pool_ptr -> tx_byte_pool_owner = thread_ptr; + + /* Walk through the memory pool in search for a large enough block. */ + current_ptr = pool_ptr -> tx_byte_pool_search; + examine_blocks = pool_ptr -> tx_byte_pool_fragments + ((UINT) 1); + available_bytes = ((ULONG) 0); + do + { + + +#ifdef TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO + + /* Increment the total fragment search counter. */ + _tx_byte_pool_performance_search_count++; + + /* Increment the number of fragments searched on this pool. */ + pool_ptr -> tx_byte_pool_performance_search_count++; +#endif + + /* Check to see if this block is free. */ + work_ptr = TX_UCHAR_POINTER_ADD(current_ptr, (sizeof(UCHAR *))); + free_ptr = TX_UCHAR_TO_ALIGN_TYPE_POINTER_CONVERT(work_ptr); + if ((*free_ptr) == TX_BYTE_BLOCK_FREE) + { + + /* Determine if this is the first free block. */ + if (first_free_block_found == TX_FALSE) + { + + /* This is the first free block. */ + pool_ptr->tx_byte_pool_search = current_ptr; + + /* Set the flag to indicate we have found the first free + block. */ + first_free_block_found = TX_TRUE; + } + + /* Block is free, see if it is large enough. */ + + /* Pickup the next block's pointer. */ + this_block_link_ptr = TX_UCHAR_TO_INDIRECT_UCHAR_POINTER_CONVERT(current_ptr); + next_ptr = *this_block_link_ptr; + + /* Calculate the number of bytes available in this block. */ + available_bytes = TX_UCHAR_POINTER_DIF(next_ptr, current_ptr); + available_bytes = available_bytes - ((sizeof(UCHAR *)) + (sizeof(ALIGN_TYPE))); + + /* If this is large enough, we are done because our first-fit algorithm + has been satisfied! */ + if (available_bytes >= memory_size) + { + + /* Get out of the search loop! */ + break; + } + else + { + + /* Clear the available bytes variable. */ + available_bytes = ((ULONG) 0); + + /* Not enough memory, check to see if the neighbor is + free and can be merged. */ + work_ptr = TX_UCHAR_POINTER_ADD(next_ptr, (sizeof(UCHAR *))); + free_ptr = TX_UCHAR_TO_ALIGN_TYPE_POINTER_CONVERT(work_ptr); + if ((*free_ptr) == TX_BYTE_BLOCK_FREE) + { + + /* Yes, neighbor block can be merged! This is quickly accomplished + by updating the current block with the next blocks pointer. */ + next_block_link_ptr = TX_UCHAR_TO_INDIRECT_UCHAR_POINTER_CONVERT(next_ptr); + *this_block_link_ptr = *next_block_link_ptr; + + /* Reduce the fragment total. We don't need to increase the bytes + available because all free headers are also included in the available + count. */ + pool_ptr -> tx_byte_pool_fragments--; + +#ifdef TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO + + /* Increment the total merge counter. */ + _tx_byte_pool_performance_merge_count++; + + /* Increment the number of blocks merged on this pool. */ + pool_ptr -> tx_byte_pool_performance_merge_count++; +#endif + + /* See if the search pointer is affected. */ + if (pool_ptr -> tx_byte_pool_search == next_ptr) + { + + /* Yes, update the search pointer. */ + pool_ptr -> tx_byte_pool_search = current_ptr; + } + } + else + { + + /* Neighbor is not free so we can skip over it! */ + next_block_link_ptr = TX_UCHAR_TO_INDIRECT_UCHAR_POINTER_CONVERT(next_ptr); + current_ptr = *next_block_link_ptr; + + /* Decrement the examined block count to account for this one. */ + if (examine_blocks != ((UINT) 0)) + { + examine_blocks--; + +#ifdef TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO + + /* Increment the total fragment search counter. */ + _tx_byte_pool_performance_search_count++; + + /* Increment the number of fragments searched on this pool. */ + pool_ptr -> tx_byte_pool_performance_search_count++; +#endif + } + } + } + } + else + { + + /* Block is not free, move to next block. */ + this_block_link_ptr = TX_UCHAR_TO_INDIRECT_UCHAR_POINTER_CONVERT(current_ptr); + current_ptr = *this_block_link_ptr; + } + + /* Another block has been searched... decrement counter. */ + if (examine_blocks != ((UINT) 0)) + { + + examine_blocks--; + } + +#ifdef TX_BYTE_POOL_MULTIPLE_BLOCK_SEARCH + + /* When this is enabled, multiple blocks are searched while holding the protection. */ + + /* Increment the number of blocks searched. */ + blocks_searched = blocks_searched + ((UINT) 1); + + /* Have we reached the maximum number of blocks to search while holding the protection? */ + if (blocks_searched >= ((UINT) TX_BYTE_POOL_MULTIPLE_BLOCK_SEARCH)) + { + + /* Yes, we have exceeded the multiple block search limit. */ + + /* Restore interrupts temporarily. */ + TX_RESTORE + + /* Disable interrupts. */ + TX_DISABLE + + /* Reset the number of blocks searched counter. */ + blocks_searched = ((UINT) 0); + } +#else + /* Restore interrupts temporarily. */ + TX_RESTORE + + /* Disable interrupts. */ + TX_DISABLE +#endif + + /* Determine if anything has changed in terms of pool ownership. */ + if (pool_ptr -> tx_byte_pool_owner != thread_ptr) + { + + /* Pool changed ownership in the brief period interrupts were + enabled. Reset the search. */ + current_ptr = pool_ptr -> tx_byte_pool_search; + examine_blocks = pool_ptr -> tx_byte_pool_fragments + ((UINT) 1); + + /* Setup our ownership again. */ + pool_ptr -> tx_byte_pool_owner = thread_ptr; + } + } while(examine_blocks != ((UINT) 0)); + + /* Determine if a block was found. If so, determine if it needs to be + split. */ + if (available_bytes != ((ULONG) 0)) + { + + /* Determine if we need to split this block. */ + if ((available_bytes - memory_size) >= ((ULONG) TX_BYTE_BLOCK_MIN)) + { + + /* Split the block. */ + next_ptr = TX_UCHAR_POINTER_ADD(current_ptr, (memory_size + ((sizeof(UCHAR *)) + (sizeof(ALIGN_TYPE))))); + + /* Setup the new free block. */ + next_block_link_ptr = TX_UCHAR_TO_INDIRECT_UCHAR_POINTER_CONVERT(next_ptr); + this_block_link_ptr = TX_UCHAR_TO_INDIRECT_UCHAR_POINTER_CONVERT(current_ptr); + *next_block_link_ptr = *this_block_link_ptr; + work_ptr = TX_UCHAR_POINTER_ADD(next_ptr, (sizeof(UCHAR *))); + free_ptr = TX_UCHAR_TO_ALIGN_TYPE_POINTER_CONVERT(work_ptr); + *free_ptr = TX_BYTE_BLOCK_FREE; + + /* Increase the total fragment counter. */ + pool_ptr -> tx_byte_pool_fragments++; + + /* Update the current pointer to point at the newly created block. */ + *this_block_link_ptr = next_ptr; + + /* Set available equal to memory size for subsequent calculation. */ + available_bytes = memory_size; + +#ifdef TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO + + /* Increment the total split counter. */ + _tx_byte_pool_performance_split_count++; + + /* Increment the number of blocks split on this pool. */ + pool_ptr -> tx_byte_pool_performance_split_count++; +#endif + } + + /* In any case, mark the current block as allocated. */ + work_ptr = TX_UCHAR_POINTER_ADD(current_ptr, (sizeof(UCHAR *))); + this_block_link_ptr = TX_UCHAR_TO_INDIRECT_UCHAR_POINTER_CONVERT(work_ptr); + *this_block_link_ptr = TX_BYTE_POOL_TO_UCHAR_POINTER_CONVERT(pool_ptr); + + /* Reduce the number of available bytes in the pool. */ + pool_ptr -> tx_byte_pool_available = (pool_ptr -> tx_byte_pool_available - available_bytes) - ((sizeof(UCHAR *)) + (sizeof(ALIGN_TYPE))); + + /* Determine if the search pointer needs to be updated. This is only done + if the search pointer matches the block to be returned. */ + if (current_ptr == pool_ptr -> tx_byte_pool_search) + { + + /* Yes, update the search pointer to the next block. */ + this_block_link_ptr = TX_UCHAR_TO_INDIRECT_UCHAR_POINTER_CONVERT(current_ptr); + pool_ptr -> tx_byte_pool_search = *this_block_link_ptr; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Adjust the pointer for the application. */ + current_ptr = TX_UCHAR_POINTER_ADD(current_ptr, (((sizeof(UCHAR *)) + (sizeof(ALIGN_TYPE))))); + } + else + { + + /* Restore interrupts. */ + TX_RESTORE + + /* Set current pointer to NULL to indicate nothing was found. */ + current_ptr = TX_NULL; + } + } + + /* Return the search pointer. */ + return(current_ptr); +} + diff --git a/common_smp/src/tx_byte_release.c b/common_smp/src/tx_byte_release.c new file mode 100644 index 00000000..c1e5d702 --- /dev/null +++ b/common_smp/src/tx_byte_release.c @@ -0,0 +1,376 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Byte Memory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_thread.h" +#include "tx_byte_pool.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_byte_release PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function returns previously allocated memory to its */ +/* associated memory byte pool. */ +/* */ +/* INPUT */ +/* */ +/* memory_ptr Pointer to allocated memory */ +/* */ +/* OUTPUT */ +/* */ +/* [TX_PTR_ERROR | TX_SUCCESS] Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_system_preempt_check Check for preemption */ +/* _tx_thread_system_resume Resume thread service */ +/* _tx_thread_system_ni_resume Non-interruptable resume thread */ +/* _tx_byte_pool_search Search the byte pool for memory */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_byte_release(VOID *memory_ptr) +{ + +TX_INTERRUPT_SAVE_AREA + +UINT status; +TX_BYTE_POOL *pool_ptr; +TX_THREAD *thread_ptr; +UCHAR *work_ptr; +UCHAR *temp_ptr; +UCHAR *next_block_ptr; +TX_THREAD *susp_thread_ptr; +UINT suspended_count; +TX_THREAD *next_thread; +TX_THREAD *previous_thread; +ULONG memory_size; +ALIGN_TYPE *free_ptr; +TX_BYTE_POOL **byte_pool_ptr; +UCHAR **block_link_ptr; +UCHAR **suspend_info_ptr; + + + /* Default to successful status. */ + status = TX_SUCCESS; + + /* Set the pool pointer to NULL. */ + pool_ptr = TX_NULL; + + /* Lockout interrupts. */ + TX_DISABLE + + /* Determine if the memory pointer is valid. */ + work_ptr = TX_VOID_TO_UCHAR_POINTER_CONVERT(memory_ptr); + if (work_ptr != TX_NULL) + { + + /* Back off the memory pointer to pickup its header. */ + work_ptr = TX_UCHAR_POINTER_SUB(work_ptr, ((sizeof(UCHAR *)) + (sizeof(ALIGN_TYPE)))); + + /* There is a pointer, pickup the pool pointer address. */ + temp_ptr = TX_UCHAR_POINTER_ADD(work_ptr, (sizeof(UCHAR *))); + free_ptr = TX_UCHAR_TO_ALIGN_TYPE_POINTER_CONVERT(temp_ptr); + if ((*free_ptr) != TX_BYTE_BLOCK_FREE) + { + + /* Pickup the pool pointer. */ + temp_ptr = TX_UCHAR_POINTER_ADD(work_ptr, (sizeof(UCHAR *))); + byte_pool_ptr = TX_UCHAR_TO_INDIRECT_BYTE_POOL_POINTER(temp_ptr); + pool_ptr = *byte_pool_ptr; + + /* See if we have a valid pool pointer. */ + if (pool_ptr == TX_NULL) + { + + /* Return pointer error. */ + status = TX_PTR_ERROR; + } + else + { + + /* See if we have a valid pool. */ + if (pool_ptr -> tx_byte_pool_id != TX_BYTE_POOL_ID) + { + + /* Return pointer error. */ + status = TX_PTR_ERROR; + + /* Reset the pool pointer is NULL. */ + pool_ptr = TX_NULL; + } + } + } + else + { + + /* Return pointer error. */ + status = TX_PTR_ERROR; + } + } + else + { + + /* Return pointer error. */ + status = TX_PTR_ERROR; + } + + /* Determine if the pointer is valid. */ + if (pool_ptr == TX_NULL) + { + + /* Restore interrupts. */ + TX_RESTORE + } + else + { + + /* At this point, we know that the pointer is valid. */ + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr) + + /* Indicate that this thread is the current owner. */ + pool_ptr -> tx_byte_pool_owner = thread_ptr; + +#ifdef TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO + + /* Increment the total release counter. */ + _tx_byte_pool_performance_release_count++; + + /* Increment the number of releases on this pool. */ + pool_ptr -> tx_byte_pool_performance_release_count++; +#endif + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_BYTE_RELEASE, pool_ptr, TX_POINTER_TO_ULONG_CONVERT(memory_ptr), pool_ptr -> tx_byte_pool_suspended_count, pool_ptr -> tx_byte_pool_available, TX_TRACE_BYTE_POOL_EVENTS) + + /* Log this kernel call. */ + TX_EL_BYTE_RELEASE_INSERT + + /* Release the memory. */ + temp_ptr = TX_UCHAR_POINTER_ADD(work_ptr, (sizeof(UCHAR *))); + free_ptr = TX_UCHAR_TO_ALIGN_TYPE_POINTER_CONVERT(temp_ptr); + *free_ptr = TX_BYTE_BLOCK_FREE; + + /* Update the number of available bytes in the pool. */ + block_link_ptr = TX_UCHAR_TO_INDIRECT_UCHAR_POINTER_CONVERT(work_ptr); + next_block_ptr = *block_link_ptr; + pool_ptr -> tx_byte_pool_available = + pool_ptr -> tx_byte_pool_available + TX_UCHAR_POINTER_DIF(next_block_ptr, work_ptr); + + /* Determine if the free block is prior to current search pointer. */ + if (work_ptr < (pool_ptr -> tx_byte_pool_search)) + { + + /* Yes, update the search pointer to the released block. */ + pool_ptr -> tx_byte_pool_search = work_ptr; + } + + /* Determine if there are threads suspended on this byte pool. */ + if (pool_ptr -> tx_byte_pool_suspended_count != TX_NO_SUSPENSIONS) + { + + /* Now examine the suspension list to find threads waiting for + memory. Maybe it is now available! */ + while (pool_ptr -> tx_byte_pool_suspended_count != TX_NO_SUSPENSIONS) + { + + /* Pickup the first suspended thread pointer. */ + susp_thread_ptr = pool_ptr -> tx_byte_pool_suspension_list; + + /* Pickup the size of the memory the thread is requesting. */ + memory_size = susp_thread_ptr -> tx_thread_suspend_info; + + /* Restore interrupts. */ + TX_RESTORE + + /* See if the request can be satisfied. */ + work_ptr = _tx_byte_pool_search(pool_ptr, memory_size); + + /* Optional processing extension. */ + TX_BYTE_RELEASE_EXTENSION + + /* Disable interrupts. */ + TX_DISABLE + + /* Indicate that this thread is the current owner. */ + pool_ptr -> tx_byte_pool_owner = thread_ptr; + + /* If there is not enough memory, break this loop! */ + if (work_ptr == TX_NULL) + { + + /* Break out of the loop. */ + break; + } + + /* Check to make sure the thread is still suspended. */ + if (susp_thread_ptr == pool_ptr -> tx_byte_pool_suspension_list) + { + + /* Also, makes sure the memory size is the same. */ + if (susp_thread_ptr -> tx_thread_suspend_info == memory_size) + { + + /* Remove the suspended thread from the list. */ + + /* Decrement the number of threads suspended. */ + pool_ptr -> tx_byte_pool_suspended_count--; + + /* Pickup the suspended count. */ + suspended_count = pool_ptr -> tx_byte_pool_suspended_count; + + /* See if this is the only suspended thread on the list. */ + if (suspended_count == TX_NO_SUSPENSIONS) + { + + /* Yes, the only suspended thread. */ + + /* Update the head pointer. */ + pool_ptr -> tx_byte_pool_suspension_list = TX_NULL; + } + else + { + + /* At least one more thread is on the same expiration list. */ + + /* Update the list head pointer. */ + next_thread = susp_thread_ptr -> tx_thread_suspended_next; + pool_ptr -> tx_byte_pool_suspension_list = next_thread; + + /* Update the links of the adjacent threads. */ + previous_thread = susp_thread_ptr -> tx_thread_suspended_previous; + next_thread -> tx_thread_suspended_previous = previous_thread; + previous_thread -> tx_thread_suspended_next = next_thread; + } + + /* Prepare for resumption of the thread. */ + + /* Clear cleanup routine to avoid timeout. */ + susp_thread_ptr -> tx_thread_suspend_cleanup = TX_NULL; + + /* Return this block pointer to the suspended thread waiting for + a block. */ + suspend_info_ptr = TX_VOID_TO_INDIRECT_UCHAR_POINTER_CONVERT(susp_thread_ptr -> tx_thread_additional_suspend_info); + *suspend_info_ptr = work_ptr; + + /* Clear the memory pointer to indicate that it was given to the suspended thread. */ + work_ptr = TX_NULL; + + /* Put return status into the thread control block. */ + susp_thread_ptr -> tx_thread_suspend_status = TX_SUCCESS; + +#ifdef TX_NOT_INTERRUPTABLE + + /* Resume the thread! */ + _tx_thread_system_ni_resume(susp_thread_ptr); + + /* Restore interrupts. */ + TX_RESTORE +#else + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Resume thread. */ + _tx_thread_system_resume(susp_thread_ptr); +#endif + + /* Lockout interrupts. */ + TX_DISABLE + } + } + + /* Determine if the memory was given to the suspended thread. */ + if (work_ptr != TX_NULL) + { + + /* No, it wasn't given to the suspended thread. */ + + /* Put the memory back on the available list since this thread is no longer + suspended. */ + work_ptr = TX_UCHAR_POINTER_SUB(work_ptr, (((sizeof(UCHAR *)) + (sizeof(ALIGN_TYPE))))); + temp_ptr = TX_UCHAR_POINTER_ADD(work_ptr, (sizeof(UCHAR *))); + free_ptr = TX_UCHAR_TO_ALIGN_TYPE_POINTER_CONVERT(temp_ptr); + *free_ptr = TX_BYTE_BLOCK_FREE; + + /* Update the number of available bytes in the pool. */ + block_link_ptr = TX_UCHAR_TO_INDIRECT_UCHAR_POINTER_CONVERT(work_ptr); + next_block_ptr = *block_link_ptr; + pool_ptr -> tx_byte_pool_available = + pool_ptr -> tx_byte_pool_available + TX_UCHAR_POINTER_DIF(next_block_ptr, work_ptr); + + /* Determine if the current pointer is before the search pointer. */ + if (work_ptr < (pool_ptr -> tx_byte_pool_search)) + { + + /* Yes, update the search pointer. */ + pool_ptr -> tx_byte_pool_search = work_ptr; + } + } + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Check for preemption. */ + _tx_thread_system_preempt_check(); + } + else + { + + /* No, threads suspended, restore interrupts. */ + TX_RESTORE + } + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/tx_event_flags_cleanup.c b/common_smp/src/tx_event_flags_cleanup.c new file mode 100644 index 00000000..53fc8d34 --- /dev/null +++ b/common_smp/src/tx_event_flags_cleanup.c @@ -0,0 +1,237 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Event Flags */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_event_flags.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_event_flags_cleanup PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes event flags timeout and thread terminate */ +/* actions that require the event flags data structures to be cleaned */ +/* up. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to suspended thread's */ +/* control block */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_system_resume Resume thread service */ +/* _tx_thread_system_ni_resume Non-interruptable resume thread */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_timeout Thread timeout processing */ +/* _tx_thread_terminate Thread terminate processing */ +/* _tx_thread_wait_abort Thread wait abort processing */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_event_flags_cleanup(TX_THREAD *thread_ptr, ULONG suspension_sequence) +{ + +#ifndef TX_NOT_INTERRUPTABLE +TX_INTERRUPT_SAVE_AREA +#endif + +TX_EVENT_FLAGS_GROUP *group_ptr; +UINT suspended_count; +TX_THREAD *suspension_head; +TX_THREAD *next_thread; +TX_THREAD *previous_thread; + + +#ifndef TX_NOT_INTERRUPTABLE + + /* Disable interrupts to remove the suspended thread from the event flags group. */ + TX_DISABLE + + /* Determine if the cleanup is still required. */ + if (thread_ptr -> tx_thread_suspend_cleanup == &(_tx_event_flags_cleanup)) + { + + /* Check for valid suspension sequence. */ + if (suspension_sequence == thread_ptr -> tx_thread_suspension_sequence) + { + + /* Setup pointer to event flags control block. */ + group_ptr = TX_VOID_TO_EVENT_FLAGS_POINTER_CONVERT(thread_ptr -> tx_thread_suspend_control_block); + + /* Check for a NULL event flags control block pointer. */ + if (group_ptr != TX_NULL) + { + + /* Is the group pointer ID valid? */ + if (group_ptr -> tx_event_flags_group_id == TX_EVENT_FLAGS_ID) + { + + /* Determine if there are any thread suspensions. */ + if (group_ptr -> tx_event_flags_group_suspended_count != TX_NO_SUSPENSIONS) + { +#else + + /* Setup pointer to event flags control block. */ + group_ptr = TX_VOID_TO_EVENT_FLAGS_POINTER_CONVERT(thread_ptr -> tx_thread_suspend_control_block); +#endif + + /* Yes, we still have thread suspension! */ + + /* Clear the suspension cleanup flag. */ + thread_ptr -> tx_thread_suspend_cleanup = TX_NULL; + + /* Pickup the suspended count. */ + suspended_count = group_ptr -> tx_event_flags_group_suspended_count; + + /* Pickup the suspension head. */ + suspension_head = group_ptr -> tx_event_flags_group_suspension_list; + + /* Determine if the cleanup is being done while a set operation was interrupted. If the + suspended count is non-zero and the suspension head is NULL, the list is being processed + and cannot be touched from here. The suspension list removal will instead take place + inside the event flag set code. */ + if (suspension_head != TX_NULL) + { + + /* Remove the suspended thread from the list. */ + + /* Decrement the local suspension count. */ + suspended_count--; + + /* Store the updated suspended count. */ + group_ptr -> tx_event_flags_group_suspended_count = suspended_count; + + /* See if this is the only suspended thread on the list. */ + if (suspended_count == TX_NO_SUSPENSIONS) + { + + /* Yes, the only suspended thread. */ + + /* Update the head pointer. */ + group_ptr -> tx_event_flags_group_suspension_list = TX_NULL; + } + else + { + + /* At least one more thread is on the same suspension list. */ + + /* Update the links of the adjacent threads. */ + next_thread = thread_ptr -> tx_thread_suspended_next; + previous_thread = thread_ptr -> tx_thread_suspended_previous; + next_thread -> tx_thread_suspended_previous = previous_thread; + previous_thread -> tx_thread_suspended_next = next_thread; + + /* Determine if we need to update the head pointer. */ + if (suspension_head == thread_ptr) + { + + /* Update the list head pointer. */ + group_ptr -> tx_event_flags_group_suspension_list = next_thread; + } + } + } + else + { + + /* In this case, the search pointer in an interrupted event flag set must be reset. */ + group_ptr -> tx_event_flags_group_reset_search = TX_TRUE; + } + + /* Now we need to determine if this cleanup is from a terminate, timeout, + or from a wait abort. */ + if (thread_ptr -> tx_thread_state == TX_EVENT_FLAG) + { + + /* Timeout condition and the thread still suspended on the event flags group. + Setup return error status and resume the thread. */ + +#ifdef TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO + + /* Increment the total timeouts counter. */ + _tx_event_flags_performance_timeout_count++; + + /* Increment the number of timeouts on this event flags group. */ + group_ptr -> tx_event_flags_group____performance_timeout_count++; +#endif + + /* Setup return status. */ + thread_ptr -> tx_thread_suspend_status = TX_NO_EVENTS; + +#ifdef TX_NOT_INTERRUPTABLE + + /* Resume the thread! */ + _tx_thread_system_ni_resume(thread_ptr); +#else + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Resume the thread! Check for preemption even though we are executing + from the system timer thread right now which normally executes at the + highest priority. */ + _tx_thread_system_resume(thread_ptr); + + /* Disable interrupts. */ + TX_DISABLE +#endif + } +#ifndef TX_NOT_INTERRUPTABLE + } + } + } + } + } + + /* Restore interrupts. */ + TX_RESTORE +#endif +} + diff --git a/common_smp/src/tx_event_flags_create.c b/common_smp/src/tx_event_flags_create.c new file mode 100644 index 00000000..bb52b670 --- /dev/null +++ b/common_smp/src/tx_event_flags_create.c @@ -0,0 +1,141 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Event Flags */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_event_flags.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_event_flags_create PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates a group of 32 event flags. All the flags are */ +/* initially in a cleared state. */ +/* */ +/* INPUT */ +/* */ +/* group_ptr Pointer to event flags group */ +/* control block */ +/* name_ptr Pointer to event flags name */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SUCCESS Successful completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_event_flags_create(TX_EVENT_FLAGS_GROUP *group_ptr, CHAR *name_ptr) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_EVENT_FLAGS_GROUP *next_group; +TX_EVENT_FLAGS_GROUP *previous_group; + + + /* Initialize event flags control block to all zeros. */ + TX_MEMSET(group_ptr, 0, (sizeof(TX_EVENT_FLAGS_GROUP))); + + /* Setup the basic event flags group fields. */ + group_ptr -> tx_event_flags_group_name = name_ptr; + + /* Disable interrupts to put the event flags group on the created list. */ + TX_DISABLE + + /* Setup the event flags ID to make it valid. */ + group_ptr -> tx_event_flags_group_id = TX_EVENT_FLAGS_ID; + + /* Place the group on the list of created event flag groups. First, + check for an empty list. */ + if (_tx_event_flags_created_count == TX_EMPTY) + { + + /* The created event flags list is empty. Add event flag group to empty list. */ + _tx_event_flags_created_ptr = group_ptr; + group_ptr -> tx_event_flags_group_created_next = group_ptr; + group_ptr -> tx_event_flags_group_created_previous = group_ptr; + } + else + { + + /* This list is not NULL, add to the end of the list. */ + next_group = _tx_event_flags_created_ptr; + previous_group = next_group -> tx_event_flags_group_created_previous; + + /* Place the new event flag group in the list. */ + next_group -> tx_event_flags_group_created_previous = group_ptr; + previous_group -> tx_event_flags_group_created_next = group_ptr; + + /* Setup this group's created links. */ + group_ptr -> tx_event_flags_group_created_previous = previous_group; + group_ptr -> tx_event_flags_group_created_next = next_group; + } + + /* Increment the number of created event flag groups. */ + _tx_event_flags_created_count++; + + /* Optional event flag group create extended processing. */ + TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) + + /* If trace is enabled, register this object. */ + TX_TRACE_OBJECT_REGISTER(TX_TRACE_OBJECT_TYPE_EVENT_FLAGS, group_ptr, name_ptr, 0, 0) + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_EVENT_FLAGS_CREATE, group_ptr, TX_POINTER_TO_ULONG_CONVERT(&next_group), 0, 0, TX_TRACE_EVENT_FLAGS_EVENTS) + + /* Log this kernel call. */ + TX_EL_EVENT_FLAGS_CREATE_INSERT + + /* Restore interrupts. */ + TX_RESTORE + + /* Return TX_SUCCESS. */ + return(TX_SUCCESS); +} + diff --git a/common_smp/src/tx_event_flags_delete.c b/common_smp/src/tx_event_flags_delete.c new file mode 100644 index 00000000..392b5f04 --- /dev/null +++ b/common_smp/src/tx_event_flags_delete.c @@ -0,0 +1,207 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Event Flags */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_thread.h" +#include "tx_event_flags.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_event_flags_delete PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function deletes the specified event flag group. All threads */ +/* suspended on the group are resumed with the TX_DELETED status */ +/* code. */ +/* */ +/* INPUT */ +/* */ +/* group_ptr Pointer to group control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SUCCESS Successful completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_system_preempt_check Check for preemption */ +/* _tx_thread_system_resume Resume thread service */ +/* _tx_thread_system_ni_resume Non-interruptable resume thread */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_event_flags_delete(TX_EVENT_FLAGS_GROUP *group_ptr) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_THREAD *thread_ptr; +TX_THREAD *next_thread; +UINT suspended_count; +TX_EVENT_FLAGS_GROUP *next_group; +TX_EVENT_FLAGS_GROUP *previous_group; + + + /* Disable interrupts to remove the group from the created list. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_EVENT_FLAGS_DELETE, group_ptr, TX_POINTER_TO_ULONG_CONVERT(&thread_ptr), 0, 0, TX_TRACE_EVENT_FLAGS_EVENTS) + + /* Optional event flags group delete extended processing. */ + TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) + + /* If trace is enabled, unregister this object. */ + TX_TRACE_OBJECT_UNREGISTER(group_ptr) + + /* Log this kernel call. */ + TX_EL_EVENT_FLAGS_DELETE_INSERT + + /* Clear the event flag group ID to make it invalid. */ + group_ptr -> tx_event_flags_group_id = TX_CLEAR_ID; + + /* Decrement the number of created event flag groups. */ + _tx_event_flags_created_count--; + + /* See if this group is the only one on the list. */ + if (_tx_event_flags_created_count == TX_EMPTY) + { + + /* Only created event flag group, just set the created list to NULL. */ + _tx_event_flags_created_ptr = TX_NULL; + } + else + { + + /* Link-up the neighbors. */ + next_group = group_ptr -> tx_event_flags_group_created_next; + previous_group = group_ptr -> tx_event_flags_group_created_previous; + next_group -> tx_event_flags_group_created_previous = previous_group; + previous_group -> tx_event_flags_group_created_next = next_group; + + /* See if we have to update the created list head pointer. */ + if (_tx_event_flags_created_ptr == group_ptr) + { + + /* Yes, move the head pointer to the next link. */ + _tx_event_flags_created_ptr = next_group; + } + } + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Pickup the suspension information. */ + thread_ptr = group_ptr -> tx_event_flags_group_suspension_list; + group_ptr -> tx_event_flags_group_suspension_list = TX_NULL; + suspended_count = group_ptr -> tx_event_flags_group_suspended_count; + group_ptr -> tx_event_flags_group_suspended_count = TX_NO_SUSPENSIONS; + + /* Restore interrupts. */ + TX_RESTORE + + /* Walk through the event flag suspension list to resume any and all threads + suspended on this group. */ + while (suspended_count != TX_NO_SUSPENSIONS) + { + + /* Decrement the number of suspended threads. */ + suspended_count--; + + /* Lockout interrupts. */ + TX_DISABLE + + /* Clear the cleanup pointer, this prevents the timeout from doing + anything. */ + thread_ptr -> tx_thread_suspend_cleanup = TX_NULL; + + /* Set the return status in the thread to TX_DELETED. */ + thread_ptr -> tx_thread_suspend_status = TX_DELETED; + + /* Move the thread pointer ahead. */ + next_thread = thread_ptr -> tx_thread_suspended_next; + +#ifdef TX_NOT_INTERRUPTABLE + + /* Resume the thread! */ + _tx_thread_system_ni_resume(thread_ptr); + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Temporarily disable preemption again. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Resume the thread. */ + _tx_thread_system_resume(thread_ptr); +#endif + + /* Move to next thread. */ + thread_ptr = next_thread; + } + + /* Execute Port-Specific completion processing. If needed, it is typically defined in tx_port.h. */ + TX_EVENT_FLAGS_GROUP_DELETE_PORT_COMPLETION(group_ptr) + + /* Disable interrupts. */ + TX_DISABLE + + /* Release previous preempt disable. */ + _tx_thread_preempt_disable--; + + /* Restore interrupts. */ + TX_RESTORE + + /* Check for preemption. */ + _tx_thread_system_preempt_check(); + + /* Return TX_SUCCESS. */ + return(TX_SUCCESS); +} + diff --git a/common_smp/src/tx_event_flags_get.c b/common_smp/src/tx_event_flags_get.c new file mode 100644 index 00000000..aafe244e --- /dev/null +++ b/common_smp/src/tx_event_flags_get.c @@ -0,0 +1,401 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Event Flags */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_thread.h" +#include "tx_event_flags.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_event_flags_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets the specified event flags from the group, */ +/* according to the get option. The get option also specifies whether */ +/* or not the retrieved flags are cleared. */ +/* */ +/* INPUT */ +/* */ +/* group_ptr Pointer to group control block */ +/* requested_event_flags Event flags requested */ +/* get_option Specifies and/or and clear options*/ +/* actual_flags_ptr Pointer to place the actual flags */ +/* the service retrieved */ +/* wait_option Suspension option */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_system_suspend Suspend thread service */ +/* _tx_thread_system_ni_suspend Non-interruptable suspend thread */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_event_flags_get(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG requested_flags, + UINT get_option, ULONG *actual_flags_ptr, ULONG wait_option) +{ + +TX_INTERRUPT_SAVE_AREA + +UINT status; +UINT and_request; +UINT clear_request; +ULONG current_flags; +ULONG flags_satisfied; +#ifndef TX_NOT_INTERRUPTABLE +ULONG delayed_clear_flags; +#endif +UINT suspended_count; +TX_THREAD *thread_ptr; +TX_THREAD *next_thread; +TX_THREAD *previous_thread; +#ifndef TX_NOT_INTERRUPTABLE +UINT interrupted_set_request; +#endif + + + /* Disable interrupts to examine the event flags group. */ + TX_DISABLE + +#ifdef TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO + + /* Increment the total event flags get counter. */ + _tx_event_flags_performance_get_count++; + + /* Increment the number of event flags gets on this semaphore. */ + group_ptr -> tx_event_flags_group__performance_get_count++; +#endif + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_EVENT_FLAGS_GET, group_ptr, requested_flags, group_ptr -> tx_event_flags_group_current, get_option, TX_TRACE_EVENT_FLAGS_EVENTS) + + /* Log this kernel call. */ + TX_EL_EVENT_FLAGS_GET_INSERT + + /* Pickup current flags. */ + current_flags = group_ptr -> tx_event_flags_group_current; + + /* Apply the event flag option mask. */ + and_request = (get_option & TX_AND); + +#ifdef TX_NOT_INTERRUPTABLE + + /* Check for AND condition. All flags must be present to satisfy request. */ + if (and_request == TX_AND) + { + + /* AND request is present. */ + + /* Calculate the flags present. */ + flags_satisfied = (current_flags & requested_flags); + + /* Determine if they satisfy the AND request. */ + if (flags_satisfied != requested_flags) + { + + /* No, not all the requested flags are present. Clear the flags present variable. */ + flags_satisfied = ((ULONG) 0); + } + } + else + { + + /* OR request is present. Simply or the requested flags and the current flags. */ + flags_satisfied = (current_flags & requested_flags); + } + + /* Determine if the request is satisfied. */ + if (flags_satisfied != ((ULONG) 0)) + { + + /* Return the actual event flags that satisfied the request. */ + *actual_flags_ptr = current_flags; + + /* Pickup the clear bit. */ + clear_request = (get_option & TX_EVENT_FLAGS_CLEAR_MASK); + + /* Determine whether or not clearing needs to take place. */ + if (clear_request == TX_TRUE) + { + + /* Yes, clear the flags that satisfied this request. */ + group_ptr -> tx_event_flags_group_current = + group_ptr -> tx_event_flags_group_current & (~requested_flags); + } + + /* Return success. */ + status = TX_SUCCESS; + } + +#else + + /* Pickup delayed clear flags. */ + delayed_clear_flags = group_ptr -> tx_event_flags_group_delayed_clear; + + /* Determine if there are any delayed clear operations pending. */ + if (delayed_clear_flags != ((ULONG) 0)) + { + + /* Yes, apply them to the current flags. */ + current_flags = current_flags & (~delayed_clear_flags); + } + + /* Check for AND condition. All flags must be present to satisfy request. */ + if (and_request == TX_AND) + { + + /* AND request is present. */ + + /* Calculate the flags present. */ + flags_satisfied = (current_flags & requested_flags); + + /* Determine if they satisfy the AND request. */ + if (flags_satisfied != requested_flags) + { + + /* No, not all the requested flags are present. Clear the flags present variable. */ + flags_satisfied = ((ULONG) 0); + } + } + else + { + + /* OR request is present. Simply AND together the requested flags and the current flags + to see if any are present. */ + flags_satisfied = (current_flags & requested_flags); + } + + /* Determine if the request is satisfied. */ + if (flags_satisfied != ((ULONG) 0)) + { + + /* Yes, this request can be handled immediately. */ + + /* Return the actual event flags that satisfied the request. */ + *actual_flags_ptr = current_flags; + + /* Pickup the clear bit. */ + clear_request = (get_option & TX_EVENT_FLAGS_CLEAR_MASK); + + /* Determine whether or not clearing needs to take place. */ + if (clear_request == TX_TRUE) + { + + /* Set interrupted set request flag to false. */ + interrupted_set_request = TX_FALSE; + + /* Determine if the suspension list is being processed by an interrupted + set request. */ + if (group_ptr -> tx_event_flags_group_suspended_count != TX_NO_SUSPENSIONS) + { + + if (group_ptr -> tx_event_flags_group_suspension_list == TX_NULL) + { + + /* Set the interrupted set request flag. */ + interrupted_set_request = TX_TRUE; + } + } + + /* Was a set request interrupted? */ + if (interrupted_set_request == TX_TRUE) + { + + /* A previous set operation is was interrupted, we need to defer the + event clearing until the set operation is complete. */ + + /* Remember the events to clear. */ + group_ptr -> tx_event_flags_group_delayed_clear = + group_ptr -> tx_event_flags_group_delayed_clear | requested_flags; + } + else + { + + /* Yes, clear the flags that satisfied this request. */ + group_ptr -> tx_event_flags_group_current = + group_ptr -> tx_event_flags_group_current & ~requested_flags; + } + } + + /* Set status to success. */ + status = TX_SUCCESS; + } + +#endif + else + { + + /* Determine if the request specifies suspension. */ + if (wait_option != TX_NO_WAIT) + { + + /* Determine if the preempt disable flag is non-zero. */ + if (_tx_thread_preempt_disable != ((UINT) 0)) + { + + /* Suspension is not allowed if the preempt disable flag is non-zero at this point, return error completion. */ + status = TX_NO_EVENTS; + } + else + { + + /* Prepare for suspension of this thread. */ + +#ifdef TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO + + /* Increment the total event flags suspensions counter. */ + _tx_event_flags_performance_suspension_count++; + + /* Increment the number of event flags suspensions on this semaphore. */ + group_ptr -> tx_event_flags_group___performance_suspension_count++; +#endif + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr) + + /* Setup cleanup routine pointer. */ + thread_ptr -> tx_thread_suspend_cleanup = &(_tx_event_flags_cleanup); + + /* Remember which event flags we are looking for. */ + thread_ptr -> tx_thread_suspend_info = requested_flags; + + /* Save the get option as well. */ + thread_ptr -> tx_thread_suspend_option = get_option; + + /* Save the destination for the current events. */ + thread_ptr -> tx_thread_additional_suspend_info = (VOID *) actual_flags_ptr; + + /* Setup cleanup information, i.e. this event flags group control + block. */ + thread_ptr -> tx_thread_suspend_control_block = (VOID *) group_ptr; + +#ifndef TX_NOT_INTERRUPTABLE + + /* Increment the suspension sequence number, which is used to identify + this suspension event. */ + thread_ptr -> tx_thread_suspension_sequence++; +#endif + + /* Pickup the suspended count. */ + suspended_count = group_ptr -> tx_event_flags_group_suspended_count; + + /* Setup suspension list. */ + if (suspended_count == TX_NO_SUSPENSIONS) + { + + /* No other threads are suspended. Setup the head pointer and + just setup this threads pointers to itself. */ + group_ptr -> tx_event_flags_group_suspension_list = thread_ptr; + thread_ptr -> tx_thread_suspended_next = thread_ptr; + thread_ptr -> tx_thread_suspended_previous = thread_ptr; + } + else + { + + /* This list is not NULL, add current thread to the end. */ + next_thread = group_ptr -> tx_event_flags_group_suspension_list; + thread_ptr -> tx_thread_suspended_next = next_thread; + previous_thread = next_thread -> tx_thread_suspended_previous; + thread_ptr -> tx_thread_suspended_previous = previous_thread; + previous_thread -> tx_thread_suspended_next = thread_ptr; + next_thread -> tx_thread_suspended_previous = thread_ptr; + } + + /* Increment the number of threads suspended. */ + group_ptr -> tx_event_flags_group_suspended_count++; + + /* Set the state to suspended. */ + thread_ptr -> tx_thread_state = TX_EVENT_FLAG; + +#ifdef TX_NOT_INTERRUPTABLE + + /* Call actual non-interruptable thread suspension routine. */ + _tx_thread_system_ni_suspend(thread_ptr, wait_option); + + /* Return the completion status. */ + status = thread_ptr -> tx_thread_suspend_status; +#else + + /* Set the suspending flag. */ + thread_ptr -> tx_thread_suspending = TX_TRUE; + + /* Setup the timeout period. */ + thread_ptr -> tx_thread_timer.tx_timer_internal_remaining_ticks = wait_option; + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Call actual thread suspension routine. */ + _tx_thread_system_suspend(thread_ptr); + + /* Disable interrupts. */ + TX_DISABLE + + /* Return the completion status. */ + status = thread_ptr -> tx_thread_suspend_status; +#endif + } + } + else + { + + /* Immediate return, return error completion. */ + status = TX_NO_EVENTS; + } + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/tx_event_flags_info_get.c b/common_smp/src/tx_event_flags_info_get.c new file mode 100644 index 00000000..5e5524fd --- /dev/null +++ b/common_smp/src/tx_event_flags_info_get.c @@ -0,0 +1,143 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Event Flags */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_event_flags.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_event_flags_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves information from the specified event flag */ +/* group. */ +/* */ +/* INPUT */ +/* */ +/* group_ptr Pointer to event flag group */ +/* name Destination for the event flag */ +/* group name */ +/* current_flags Current event flags */ +/* first_suspended Destination for pointer of first */ +/* thread suspended on event flags */ +/* suspended_count Destination for suspended count */ +/* next_group Destination for pointer to next */ +/* event flag group on the created */ +/* list */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_event_flags_info_get(TX_EVENT_FLAGS_GROUP *group_ptr, CHAR **name, ULONG *current_flags, + TX_THREAD **first_suspended, ULONG *suspended_count, + TX_EVENT_FLAGS_GROUP **next_group) +{ + +TX_INTERRUPT_SAVE_AREA + + + /* Disable interrupts. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_EVENT_FLAGS_INFO_GET, group_ptr, 0, 0, 0, TX_TRACE_EVENT_FLAGS_EVENTS) + + /* Log this kernel call. */ + TX_EL_EVENT_FLAGS_INFO_GET_INSERT + + /* Retrieve all the pertinent information and return it in the supplied + destinations. */ + + /* Retrieve the name of the event flag group. */ + if (name != TX_NULL) + { + + *name = group_ptr -> tx_event_flags_group_name; + } + + /* Retrieve the current event flags in the event flag group. */ + if (current_flags != TX_NULL) + { + + /* Pickup the current flags and apply delayed clearing. */ + *current_flags = group_ptr -> tx_event_flags_group_current & + ~group_ptr -> tx_event_flags_group_delayed_clear; + } + + /* Retrieve the first thread suspended on this event flag group. */ + if (first_suspended != TX_NULL) + { + + *first_suspended = group_ptr -> tx_event_flags_group_suspension_list; + } + + /* Retrieve the number of threads suspended on this event flag group. */ + if (suspended_count != TX_NULL) + { + + *suspended_count = (ULONG) group_ptr -> tx_event_flags_group_suspended_count; + } + + /* Retrieve the pointer to the next event flag group created. */ + if (next_group != TX_NULL) + { + + *next_group = group_ptr -> tx_event_flags_group_created_next; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return completion status. */ + return(TX_SUCCESS); +} + diff --git a/common_smp/src/tx_event_flags_initialize.c b/common_smp/src/tx_event_flags_initialize.c new file mode 100644 index 00000000..f9f4ab5d --- /dev/null +++ b/common_smp/src/tx_event_flags_initialize.c @@ -0,0 +1,130 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Event Flags */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_event_flags.h" + + +#ifndef TX_INLINE_INITIALIZATION + +/* Locate event flags component data in this file. */ +/* Define the head pointer of the created event flags list. */ + +TX_EVENT_FLAGS_GROUP * _tx_event_flags_created_ptr; + + +/* Define the variable that holds the number of created event flag groups. */ + +ULONG _tx_event_flags_created_count; + + +#ifdef TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO + +/* Define the total number of event flag sets. */ + +ULONG _tx_event_flags_performance_set_count; + + +/* Define the total number of event flag gets. */ + +ULONG _tx_event_flags_performance_get_count; + + +/* Define the total number of event flag suspensions. */ + +ULONG _tx_event_flags_performance_suspension_count; + + +/* Define the total number of event flag timeouts. */ + +ULONG _tx_event_flags_performance_timeout_count; + + +#endif +#endif + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_event_flags_initialize PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes the various control data structures for */ +/* the event flags component. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_high_level High level initialization */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_event_flags_initialize(VOID) +{ + +#ifndef TX_DISABLE_REDUNDANT_CLEARING + + /* Initialize the head pointer of the created event flags list and the + number of event flags created. */ + _tx_event_flags_created_ptr = TX_NULL; + _tx_event_flags_created_count = TX_EMPTY; + +#ifdef TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO + + /* Initialize event flags performance counters. */ + _tx_event_flags_performance_set_count = ((ULONG) 0); + _tx_event_flags_performance_get_count = ((ULONG) 0); + _tx_event_flags_performance_suspension_count = ((ULONG) 0); + _tx_event_flags_performance_timeout_count = ((ULONG) 0); +#endif +#endif +} + diff --git a/common_smp/src/tx_event_flags_performance_info_get.c b/common_smp/src/tx_event_flags_performance_info_get.c new file mode 100644 index 00000000..6c410cf6 --- /dev/null +++ b/common_smp/src/tx_event_flags_performance_info_get.c @@ -0,0 +1,202 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Event Flags */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_event_flags.h" +#ifdef TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO +#include "tx_trace.h" +#endif + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_event_flags_performance_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves performance information from the specified */ +/* event flag group. */ +/* */ +/* INPUT */ +/* */ +/* group_ptr Pointer to event flag group */ +/* sets Destination for the number of */ +/* event flag sets on this group */ +/* gets Destination for the number of */ +/* event flag gets on this group */ +/* suspensions Destination for the number of */ +/* event flag suspensions on this */ +/* group */ +/* timeouts Destination for number of timeouts*/ +/* on this event flag group */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_event_flags_performance_info_get(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG *sets, ULONG *gets, + ULONG *suspensions, ULONG *timeouts) +{ + +#ifdef TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO + +TX_INTERRUPT_SAVE_AREA +UINT status; + + + /* Determine if this is a legal request. */ + if (group_ptr == TX_NULL) + { + + /* Event flags group pointer is illegal, return error. */ + status = TX_PTR_ERROR; + } + + /* Determine if the event group ID is invalid. */ + else if (group_ptr -> tx_event_flags_group_id != TX_EVENT_FLAGS_ID) + { + + /* Event flags group pointer is illegal, return error. */ + status = TX_PTR_ERROR; + } + else + { + + /* Disable interrupts. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_EVENT_FLAGS_PERFORMANCE_INFO_GET, group_ptr, 0, 0, 0, TX_TRACE_EVENT_FLAGS_EVENTS) + + /* Log this kernel call. */ + TX_EL_EVENT_FLAGS_PERFORMANCE_INFO_GET_INSERT + + /* Retrieve all the pertinent information and return it in the supplied + destinations. */ + + /* Retrieve the number of set operations on this event flag group. */ + if (sets != TX_NULL) + { + + *sets = group_ptr -> tx_event_flags_group_performance_set_count; + } + + /* Retrieve the number of get operations on this event flag group. */ + if (gets != TX_NULL) + { + + *gets = group_ptr -> tx_event_flags_group__performance_get_count; + } + + /* Retrieve the number of thread suspensions on this event flag group. */ + if (suspensions != TX_NULL) + { + + *suspensions = group_ptr -> tx_event_flags_group___performance_suspension_count; + } + + /* Retrieve the number of thread timeouts on this event flag group. */ + if (timeouts != TX_NULL) + { + + *timeouts = group_ptr -> tx_event_flags_group____performance_timeout_count; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return successful completion. */ + status = TX_SUCCESS; + } +#else +UINT status; + + + /* Access input arguments just for the sake of lint, MISRA, etc. */ + if (group_ptr != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (sets != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (gets != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (suspensions != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (timeouts != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } +#endif + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/tx_event_flags_performance_system_info_get.c b/common_smp/src/tx_event_flags_performance_system_info_get.c new file mode 100644 index 00000000..65c33973 --- /dev/null +++ b/common_smp/src/tx_event_flags_performance_system_info_get.c @@ -0,0 +1,174 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Event Flags */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_event_flags.h" +#ifdef TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO +#include "tx_trace.h" +#endif + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_event_flags_performance_system_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves system event flag performance information. */ +/* */ +/* INPUT */ +/* */ +/* sets Destination for total number of */ +/* event flag sets */ +/* gets Destination for total number of */ +/* event flag gets */ +/* suspensions Destination for total number of */ +/* event flag suspensions */ +/* timeouts Destination for total number of */ +/* timeouts */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_event_flags_performance_system_info_get(ULONG *sets, ULONG *gets, ULONG *suspensions, ULONG *timeouts) +{ + +#ifdef TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO + +TX_INTERRUPT_SAVE_AREA + + + /* Disable interrupts. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_EVENT_FLAGS__PERFORMANCE_SYSTEM_INFO_GET, 0, 0, 0, 0, TX_TRACE_EVENT_FLAGS_EVENTS) + + /* Log this kernel call. */ + TX_EL_EVENT_FLAGS__PERFORMANCE_SYSTEM_INFO_GET_INSERT + + /* Retrieve all the pertinent information and return it in the supplied + destinations. */ + + /* Retrieve the total number of event flag set operations. */ + if (sets != TX_NULL) + { + + *sets = _tx_event_flags_performance_set_count; + } + + /* Retrieve the total number of event flag get operations. */ + if (gets != TX_NULL) + { + + *gets = _tx_event_flags_performance_get_count; + } + + /* Retrieve the total number of event flag thread suspensions. */ + if (suspensions != TX_NULL) + { + + *suspensions = _tx_event_flags_performance_suspension_count; + } + + /* Retrieve the total number of event flag thread timeouts. */ + if (timeouts != TX_NULL) + { + + *timeouts = _tx_event_flags_performance_timeout_count; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return completion status. */ + return(TX_SUCCESS); + +#else + +UINT status; + + + /* Access input arguments just for the sake of lint, MISRA, etc. */ + if (sets != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (gets != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (suspensions != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (timeouts != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + + /* Return completion status. */ + return(status); +#endif +} + diff --git a/common_smp/src/tx_event_flags_set.c b/common_smp/src/tx_event_flags_set.c new file mode 100644 index 00000000..7710be6b --- /dev/null +++ b/common_smp/src/tx_event_flags_set.c @@ -0,0 +1,620 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Event Flags */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_thread.h" +#include "tx_event_flags.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_event_flags_set PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets the specified flags in the event group based on */ +/* the set option specified. All threads suspended on the group whose */ +/* get request can now be satisfied are resumed. */ +/* */ +/* INPUT */ +/* */ +/* group_ptr Pointer to group control block */ +/* flags_to_set Event flags to set */ +/* set_option Specified either AND or OR */ +/* operation on the event flags */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SUCCESS Always returns success */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_system_preempt_check Check for preemption */ +/* _tx_thread_system_resume Resume thread service */ +/* _tx_thread_system_ni_resume Non-interruptable resume thread */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_event_flags_set(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG flags_to_set, UINT set_option) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_THREAD *thread_ptr; +TX_THREAD *next_thread_ptr; +TX_THREAD *next_thread; +TX_THREAD *previous_thread; +TX_THREAD *satisfied_list; +TX_THREAD *last_satisfied; +TX_THREAD *suspended_list; +UINT suspended_count; +ULONG current_event_flags; +ULONG requested_flags; +ULONG flags_satisfied; +ULONG *suspend_info_ptr; +UINT and_request; +UINT get_option; +UINT clear_request; +UINT preempt_check; +#ifndef TX_NOT_INTERRUPTABLE +UINT interrupted_set_request; +#endif +#ifndef TX_DISABLE_NOTIFY_CALLBACKS +VOID (*events_set_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *notify_group_ptr); +#endif + + + /* Disable interrupts to remove the semaphore from the created list. */ + TX_DISABLE + +#ifdef TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO + + /* Increment the total event flags set counter. */ + _tx_event_flags_performance_set_count++; + + /* Increment the number of event flags sets on this semaphore. */ + group_ptr -> tx_event_flags_group_performance_set_count++; +#endif + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_EVENT_FLAGS_SET, group_ptr, flags_to_set, set_option, group_ptr -> tx_event_flags_group_suspended_count, TX_TRACE_EVENT_FLAGS_EVENTS) + + /* Log this kernel call. */ + TX_EL_EVENT_FLAGS_SET_INSERT + + /* Determine how to set this group's event flags. */ + if ((set_option & TX_EVENT_FLAGS_AND_MASK) == TX_AND) + { + +#ifndef TX_NOT_INTERRUPTABLE + + /* Set interrupted set request flag to false. */ + interrupted_set_request = TX_FALSE; + + /* Determine if the suspension list is being processed by an interrupted + set request. */ + if (group_ptr -> tx_event_flags_group_suspended_count != TX_NO_SUSPENSIONS) + { + + if (group_ptr -> tx_event_flags_group_suspension_list == TX_NULL) + { + + /* Set the interrupted set request flag. */ + interrupted_set_request = TX_TRUE; + } + } + + /* Was a set request interrupted? */ + if (interrupted_set_request == TX_TRUE) + { + + /* A previous set operation was interrupted, we need to defer the + event clearing until the set operation is complete. */ + + /* Remember the events to clear. */ + group_ptr -> tx_event_flags_group_delayed_clear = + group_ptr -> tx_event_flags_group_delayed_clear | ~flags_to_set; + } + else + { +#endif + + /* Previous set operation was not interrupted, simply clear the + specified flags by "ANDing" the flags into the current events + of the group. */ + group_ptr -> tx_event_flags_group_current = + group_ptr -> tx_event_flags_group_current & flags_to_set; + +#ifndef TX_NOT_INTERRUPTABLE + + } +#endif + + /* Restore interrupts. */ + TX_RESTORE + } + else + { + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the notify callback routine for this event flag group. */ + events_set_notify = group_ptr -> tx_event_flags_group_set_notify; +#endif + + /* "OR" the flags into the current events of the group. */ + group_ptr -> tx_event_flags_group_current = + group_ptr -> tx_event_flags_group_current | flags_to_set; + +#ifndef TX_NOT_INTERRUPTABLE + + /* Determine if there are any delayed flags to clear. */ + if (group_ptr -> tx_event_flags_group_delayed_clear != ((ULONG) 0)) + { + + /* Yes, we need to neutralize the delayed clearing as well. */ + group_ptr -> tx_event_flags_group_delayed_clear = + group_ptr -> tx_event_flags_group_delayed_clear & ~flags_to_set; + } +#endif + + /* Clear the preempt check flag. */ + preempt_check = TX_FALSE; + + /* Pickup the thread suspended count. */ + suspended_count = group_ptr -> tx_event_flags_group_suspended_count; + + /* Determine if there are any threads suspended on the event flag group. */ + if (group_ptr -> tx_event_flags_group_suspension_list != TX_NULL) + { + + /* Determine if there is just a single thread waiting on the event + flag group. */ + if (suspended_count == ((UINT) 1)) + { + + /* Single thread waiting for event flags. Bypass the multiple thread + logic. */ + + /* Setup thread pointer. */ + thread_ptr = group_ptr -> tx_event_flags_group_suspension_list; + + /* Pickup the current event flags. */ + current_event_flags = group_ptr -> tx_event_flags_group_current; + + /* Pickup the suspend information. */ + requested_flags = thread_ptr -> tx_thread_suspend_info; + + /* Pickup the suspend option. */ + get_option = thread_ptr -> tx_thread_suspend_option; + + /* Isolate the AND selection. */ + and_request = (get_option & TX_AND); + + /* Check for AND condition. All flags must be present to satisfy request. */ + if (and_request == TX_AND) + { + + /* AND request is present. */ + + /* Calculate the flags present. */ + flags_satisfied = (current_event_flags & requested_flags); + + /* Determine if they satisfy the AND request. */ + if (flags_satisfied != requested_flags) + { + + /* No, not all the requested flags are present. Clear the flags present variable. */ + flags_satisfied = ((ULONG) 0); + } + } + else + { + + /* OR request is present. Simply or the requested flags and the current flags. */ + flags_satisfied = (current_event_flags & requested_flags); + } + + /* Determine if the request is satisfied. */ + if (flags_satisfied != ((ULONG) 0)) + { + + /* Yes, resume the thread and apply any event flag + clearing. */ + + /* Set the preempt check flag. */ + preempt_check = TX_TRUE; + + /* Return the actual event flags that satisfied the request. */ + suspend_info_ptr = TX_VOID_TO_ULONG_POINTER_CONVERT(thread_ptr -> tx_thread_additional_suspend_info); + *suspend_info_ptr = current_event_flags; + + /* Pickup the clear bit. */ + clear_request = (get_option & TX_EVENT_FLAGS_CLEAR_MASK); + + /* Determine whether or not clearing needs to take place. */ + if (clear_request == TX_TRUE) + { + + /* Yes, clear the flags that satisfied this request. */ + group_ptr -> tx_event_flags_group_current = group_ptr -> tx_event_flags_group_current & (~requested_flags); + } + + /* Clear the suspension information in the event flag group. */ + group_ptr -> tx_event_flags_group_suspension_list = TX_NULL; + group_ptr -> tx_event_flags_group_suspended_count = TX_NO_SUSPENSIONS; + + /* Clear cleanup routine to avoid timeout. */ + thread_ptr -> tx_thread_suspend_cleanup = TX_NULL; + + /* Put return status into the thread control block. */ + thread_ptr -> tx_thread_suspend_status = TX_SUCCESS; + +#ifdef TX_NOT_INTERRUPTABLE + + /* Resume the thread! */ + _tx_thread_system_ni_resume(thread_ptr); +#else + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Resume thread. */ + _tx_thread_system_resume(thread_ptr); + + /* Disable interrupts to remove the semaphore from the created list. */ + TX_DISABLE +#endif + } + } + else + { + + /* Otherwise, the event flag requests of multiple threads must be + examined. */ + + /* Setup thread pointer, keep a local copy of the head pointer. */ + suspended_list = group_ptr -> tx_event_flags_group_suspension_list; + thread_ptr = suspended_list; + + /* Clear the suspended list head pointer to thwart manipulation of + the list in ISR's while we are processing here. */ + group_ptr -> tx_event_flags_group_suspension_list = TX_NULL; + + /* Setup the satisfied thread pointers. */ + satisfied_list = TX_NULL; + last_satisfied = TX_NULL; + + /* Pickup the current event flags. */ + current_event_flags = group_ptr -> tx_event_flags_group_current; + + /* Disable preemption while we process the suspended list. */ + _tx_thread_preempt_disable++; + + /* Loop to examine all of the suspended threads. */ + do + { + +#ifndef TX_NOT_INTERRUPTABLE + + /* Restore interrupts temporarily. */ + TX_RESTORE + + /* Disable interrupts again. */ + TX_DISABLE +#endif + + /* Determine if we need to reset the search. */ + if (group_ptr -> tx_event_flags_group_reset_search != TX_FALSE) + { + + /* Clear the reset search flag. */ + group_ptr -> tx_event_flags_group_reset_search = TX_FALSE; + + /* Move the thread pointer to the beginning of the search list. */ + thread_ptr = suspended_list; + + /* Reset the suspended count. */ + suspended_count = group_ptr -> tx_event_flags_group_suspended_count; + + /* Update the current events with any new ones that might + have been set in a nested set events call from an ISR. */ + current_event_flags = current_event_flags | group_ptr -> tx_event_flags_group_current; + } + + /* Save next thread pointer. */ + next_thread_ptr = thread_ptr -> tx_thread_suspended_next; + + /* Pickup the suspend information. */ + requested_flags = thread_ptr -> tx_thread_suspend_info; + + /* Pickup this thread's suspension get option. */ + get_option = thread_ptr -> tx_thread_suspend_option; + + /* Isolate the AND selection. */ + and_request = (get_option & TX_AND); + + /* Check for AND condition. All flags must be present to satisfy request. */ + if (and_request == TX_AND) + { + + /* AND request is present. */ + + /* Calculate the flags present. */ + flags_satisfied = (current_event_flags & requested_flags); + + /* Determine if they satisfy the AND request. */ + if (flags_satisfied != requested_flags) + { + + /* No, not all the requested flags are present. Clear the flags present variable. */ + flags_satisfied = ((ULONG) 0); + } + } + else + { + + /* OR request is present. Simply or the requested flags and the current flags. */ + flags_satisfied = (current_event_flags & requested_flags); + } + + /* Check to see if the thread had a timeout or wait abort during the event search processing. + If so, just set the flags satisfied to ensure the processing here removes the thread from + the suspension list. */ + if (thread_ptr -> tx_thread_state != TX_EVENT_FLAG) + { + + /* Simply set the satisfied flags to 1 in order to remove the thread from the suspension list. */ + flags_satisfied = ((ULONG) 1); + } + + /* Determine if the request is satisfied. */ + if (flags_satisfied != ((ULONG) 0)) + { + + /* Yes, this request can be handled now. */ + + /* Set the preempt check flag. */ + preempt_check = TX_TRUE; + + /* Determine if the thread is still suspended on the event flag group. If not, a wait + abort must have been done from an ISR. */ + if (thread_ptr -> tx_thread_state == TX_EVENT_FLAG) + { + + /* Return the actual event flags that satisfied the request. */ + suspend_info_ptr = TX_VOID_TO_ULONG_POINTER_CONVERT(thread_ptr -> tx_thread_additional_suspend_info); + *suspend_info_ptr = current_event_flags; + + /* Pickup the clear bit. */ + clear_request = (get_option & TX_EVENT_FLAGS_CLEAR_MASK); + + /* Determine whether or not clearing needs to take place. */ + if (clear_request == TX_TRUE) + { + + /* Yes, clear the flags that satisfied this request. */ + group_ptr -> tx_event_flags_group_current = group_ptr -> tx_event_flags_group_current & ~requested_flags; + } + + /* Prepare for resumption of the first thread. */ + + /* Clear cleanup routine to avoid timeout. */ + thread_ptr -> tx_thread_suspend_cleanup = TX_NULL; + + /* Put return status into the thread control block. */ + thread_ptr -> tx_thread_suspend_status = TX_SUCCESS; + } + + /* We need to remove the thread from the suspension list and place it in the + expired list. */ + + /* See if this is the only suspended thread on the list. */ + if (thread_ptr == thread_ptr -> tx_thread_suspended_next) + { + + /* Yes, the only suspended thread. */ + + /* Update the head pointer. */ + suspended_list = TX_NULL; + } + else + { + + /* At least one more thread is on the same expiration list. */ + + /* Update the links of the adjacent threads. */ + next_thread = thread_ptr -> tx_thread_suspended_next; + previous_thread = thread_ptr -> tx_thread_suspended_previous; + next_thread -> tx_thread_suspended_previous = previous_thread; + previous_thread -> tx_thread_suspended_next = next_thread; + + /* Update the list head pointer, if removing the head of the + list. */ + if (suspended_list == thread_ptr) + { + + /* Yes, head pointer needs to be updated. */ + suspended_list = thread_ptr -> tx_thread_suspended_next; + } + } + + /* Decrement the suspension count. */ + group_ptr -> tx_event_flags_group_suspended_count--; + + /* Place this thread on the expired list. */ + if (satisfied_list == TX_NULL) + { + + /* First thread on the satisfied list. */ + satisfied_list = thread_ptr; + last_satisfied = thread_ptr; + + /* Setup initial next pointer. */ + thread_ptr -> tx_thread_suspended_next = TX_NULL; + } + else + { + + /* Not the first thread on the satisfied list. */ + + /* Link it up at the end. */ + last_satisfied -> tx_thread_suspended_next = thread_ptr; + thread_ptr -> tx_thread_suspended_next = TX_NULL; + last_satisfied = thread_ptr; + } + } + + /* Copy next thread pointer to working thread ptr. */ + thread_ptr = next_thread_ptr; + + /* Decrement the suspension count. */ + suspended_count--; + + } while (suspended_count != TX_NO_SUSPENSIONS); + + /* Setup the group's suspension list head again. */ + group_ptr -> tx_event_flags_group_suspension_list = suspended_list; + +#ifndef TX_NOT_INTERRUPTABLE + + /* Determine if there is any delayed event clearing to perform. */ + if (group_ptr -> tx_event_flags_group_delayed_clear != ((ULONG) 0)) + { + + /* Perform the delayed event clearing. */ + group_ptr -> tx_event_flags_group_current = + group_ptr -> tx_event_flags_group_current & ~(group_ptr -> tx_event_flags_group_delayed_clear); + + /* Clear the delayed event flag clear value. */ + group_ptr -> tx_event_flags_group_delayed_clear = ((ULONG) 0); + } +#endif + + /* Restore interrupts. */ + TX_RESTORE + + /* Walk through the satisfied list, setup initial thread pointer. */ + thread_ptr = satisfied_list; + while(thread_ptr != TX_NULL) + { + + /* Get next pointer first. */ + next_thread_ptr = thread_ptr -> tx_thread_suspended_next; + + /* Disable interrupts. */ + TX_DISABLE + +#ifdef TX_NOT_INTERRUPTABLE + + /* Resume the thread! */ + _tx_thread_system_ni_resume(thread_ptr); + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Disable preemption again. */ + _tx_thread_preempt_disable++; + + /* Restore interrupt posture. */ + TX_RESTORE + + /* Resume the thread. */ + _tx_thread_system_resume(thread_ptr); +#endif + + /* Move next thread to current. */ + thread_ptr = next_thread_ptr; + } + + /* Disable interrupts. */ + TX_DISABLE + + /* Release thread preemption disable. */ + _tx_thread_preempt_disable--; + } + } + else + { + + /* Determine if we need to set the reset search field. */ + if (group_ptr -> tx_event_flags_group_suspended_count != TX_NO_SUSPENSIONS) + { + + /* We interrupted a search of an event flag group suspension + list. Make sure we reset the search. */ + group_ptr -> tx_event_flags_group_reset_search = TX_TRUE; + } + } + + /* Restore interrupts. */ + TX_RESTORE + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Determine if a notify callback is required. */ + if (events_set_notify != TX_NULL) + { + + /* Call application event flags set notification. */ + (events_set_notify)(group_ptr); + } +#endif + + /* Determine if a check for preemption is necessary. */ + if (preempt_check == TX_TRUE) + { + + /* Yes, one or more threads were resumed, check for preemption. */ + _tx_thread_system_preempt_check(); + } + } + + /* Return completion status. */ + return(TX_SUCCESS); +} + diff --git a/common_smp/src/tx_event_flags_set_notify.c b/common_smp/src/tx_event_flags_set_notify.c new file mode 100644 index 00000000..3168c876 --- /dev/null +++ b/common_smp/src/tx_event_flags_set_notify.c @@ -0,0 +1,107 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Event Flags */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_event_flags.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_event_flags_set_notify PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application callback function that is */ +/* called whenever an event flag is set in this group. */ +/* */ +/* INPUT */ +/* */ +/* group_ptr Pointer to group control block*/ +/* group_put_notify Application callback function */ +/* (TX_NULL disables notify) */ +/* */ +/* OUTPUT */ +/* */ +/* status Service return status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_event_flags_set_notify(TX_EVENT_FLAGS_GROUP *group_ptr, VOID (*events_set_notify)(TX_EVENT_FLAGS_GROUP *notify_group_ptr)) +{ + +#ifdef TX_DISABLE_NOTIFY_CALLBACKS + + TX_EVENT_FLAGS_GROUP_NOT_USED(group_ptr); + TX_EVENT_FLAGS_SET_NOTIFY_NOT_USED(events_set_notify); + + /* Feature is not enabled, return error. */ + return(TX_FEATURE_NOT_ENABLED); +#else + +TX_INTERRUPT_SAVE_AREA + + + /* Disable interrupts. */ + TX_DISABLE + + /* Make entry in event log. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_EVENT_FLAGS_SET_NOTIFY, group_ptr, 0, 0, 0, TX_TRACE_EVENT_FLAGS_EVENTS) + + /* Make entry in event log. */ + TX_EL_EVENT_FLAGS_SET_NOTIFY_INSERT + + /* Setup event flag group set notification callback function. */ + group_ptr -> tx_event_flags_group_set_notify = events_set_notify; + + /* Restore interrupts. */ + TX_RESTORE + + /* Return success to caller. */ + return(TX_SUCCESS); +#endif +} + diff --git a/common_smp/src/tx_initialize_high_level.c b/common_smp/src/tx_initialize_high_level.c new file mode 100644 index 00000000..fe4f2965 --- /dev/null +++ b/common_smp/src/tx_initialize_high_level.c @@ -0,0 +1,150 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" + +/* Determine if in-line initialization is required. */ +#ifdef TX_INLINE_INITIALIZATION +#define TX_INVOKE_INLINE_INITIALIZATION +#endif + +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_timer.h" +#include "tx_semaphore.h" +#include "tx_queue.h" +#include "tx_event_flags.h" +#include "tx_mutex.h" +#include "tx_block_pool.h" +#include "tx_byte_pool.h" + + +/* Define the unused memory pointer. The value of the first available + memory address is placed in this variable in the low-level + initialization function. The content of this variable is passed + to the application's system definition function. */ + +VOID *_tx_initialize_unused_memory; + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_high_level PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for initializing all of the other */ +/* components in the ThreadX real-time kernel. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_initialize Initialize the thread control */ +/* component */ +/* _tx_timer_initialize Initialize the timer control */ +/* component */ +/* _tx_semaphore_initialize Initialize the semaphore control */ +/* component */ +/* _tx_queue_initialize Initialize the queue control */ +/* component */ +/* _tx_event_flags_initialize Initialize the event flags control*/ +/* component */ +/* _tx_block_pool_initialize Initialize the block pool control */ +/* component */ +/* _tx_byte_pool_initialize Initialize the byte pool control */ +/* component */ +/* _tx_mutex_initialize Initialize the mutex control */ +/* component */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter Kernel entry function */ +/* _tx_initialize_kernel_setup Early kernel setup function that */ +/* is optionally called by */ +/* compiler's startup code. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_initialize_high_level(VOID) +{ + + /* Initialize event tracing, if enabled. */ + TX_TRACE_INITIALIZE + + /* Initialize the event log, if enabled. */ + TX_EL_INITIALIZE + + /* Call the thread control initialization function. */ + _tx_thread_initialize(); + +#ifndef TX_NO_TIMER + + /* Call the timer control initialization function. */ + _tx_timer_initialize(); +#endif + +#ifndef TX_DISABLE_REDUNDANT_CLEARING + + /* Call the semaphore initialization function. */ + _tx_semaphore_initialize(); + + /* Call the queue initialization function. */ + _tx_queue_initialize(); + + /* Call the event flag initialization function. */ + _tx_event_flags_initialize(); + + /* Call the block pool initialization function. */ + _tx_block_pool_initialize(); + + /* Call the byte pool initialization function. */ + _tx_byte_pool_initialize(); + + /* Call the mutex initialization function. */ + _tx_mutex_initialize(); +#endif +} + diff --git a/common_smp/src/tx_initialize_kernel_enter.c b/common_smp/src/tx_initialize_kernel_enter.c new file mode 100644 index 00000000..990bea11 --- /dev/null +++ b/common_smp/src/tx_initialize_kernel_enter.c @@ -0,0 +1,188 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_timer.h" + + +/* Define any port-specific scheduling data structures. */ + +TX_PORT_SPECIFIC_DATA + + +#ifdef TX_SAFETY_CRITICAL +TX_SAFETY_CRITICAL_EXCEPTION_HANDLER +#endif + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_kernel_enter PORTABLE SMP */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is the first ThreadX function called during */ +/* initialization. It is called from the application's "main()" */ +/* function. It is important to note that this routine never */ +/* returns. The processing of this function is relatively simple: */ +/* it calls several ThreadX initialization functions (if needed), */ +/* calls the application define function, and then invokes the */ +/* scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_smp_high_level_initialize SMP initialization */ +/* _tx_thread_smp_current_state_set Set system state for all cores */ +/* _tx_initialize_low_level Low-level initialization */ +/* _tx_initialize_high_level High-level initialization */ +/* tx_application_define Application define function */ +/* _tx_thread_scheduler ThreadX scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* main Application main program */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_initialize_kernel_enter(VOID) +{ + +ULONG other_core_status, i; + + + /* Determine if the compiler has pre-initialized ThreadX. */ + if (_tx_thread_system_state[0] != TX_INITIALIZE_ALMOST_DONE) + { + + /* No, the initialization still needs to take place. */ + + /* Ensure that the system state variable is set to indicate + initialization is in progress. Note that this variable is + later used to represent interrupt nesting. */ + _tx_thread_smp_current_state_set(TX_INITIALIZE_IN_PROGRESS); + + /* Call any port specific preprocessing. */ + TX_PORT_SPECIFIC_PRE_INITIALIZATION + + /* Invoke the low-level initialization to handle all processor specific + initialization issues. */ + _tx_initialize_low_level(); + + /* Call the high-level SMP Initialization. */ + _tx_thread_smp_high_level_initialize(); + + /* Invoke the high-level initialization to exercise all of the + ThreadX components and the application's initialization + function. */ + _tx_initialize_high_level(); + + /* Call any port specific post-processing. */ + TX_PORT_SPECIFIC_POST_INITIALIZATION + } + + /* Optional processing extension. */ + TX_INITIALIZE_KERNEL_ENTER_EXTENSION + + /* Ensure that the system state variable is set to indicate + initialization is in progress. Note that this variable is + later used to represent interrupt nesting. */ + _tx_thread_system_state[0] = TX_INITIALIZE_IN_PROGRESS; + + /* Call the application provided initialization function. Pass the + first available memory address to it. */ + tx_application_define(_tx_initialize_unused_memory); + + /* Call any port specific pre-scheduler processing. */ + TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION + + /* Now wait for all cores to become ready for scheduling. */ + do + { + + /* Release the other cores from initialization. */ + _tx_thread_smp_release_cores_flag = TX_TRUE; + + /* Add all the status together... Other cores must clear their system + state before they they are released. */ + other_core_status = ((ULONG) 0); + +#ifndef TX_THREAD_SMP_DYNAMIC_CORE_MAX + for (i = ((ULONG) 1); i < ((ULONG) TX_THREAD_SMP_MAX_CORES); i++) +#else + for (i = ((ULONG) 1); i < _tx_thread_smp_max_cores; i++) +#endif + { + + + /* Call port-specific memory synchronization primitive. */ + TX_PORT_SPECIFIC_MEMORY_SYNCHRONIZATION + + /* Add the states of each subsequent core. */ + other_core_status = other_core_status + _tx_thread_system_state[i]; + } + + } while (other_core_status != ((ULONG) 0)); + + /* Set the system state in preparation for entering the thread + scheduler. */ + _tx_thread_system_state[0] = TX_INITIALIZE_IS_FINISHED; + + /* Call port-specific memory synchronization primitive. */ + TX_PORT_SPECIFIC_MEMORY_SYNCHRONIZATION + + /* Enter the scheduling loop to start executing threads! */ + _tx_thread_schedule(); + +#ifdef TX_SAFETY_CRITICAL + + /* If we ever get here, raise safety critical exception. */ + TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0); +#endif +} + diff --git a/common_smp/src/tx_initialize_kernel_setup.c b/common_smp/src/tx_initialize_kernel_setup.c new file mode 100644 index 00000000..c00bb592 --- /dev/null +++ b/common_smp/src/tx_initialize_kernel_setup.c @@ -0,0 +1,106 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_kernel_setup PORTABLE SMP */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the compiler's startup code to make */ +/* ThreadX objects accessible to the compiler's library. If this */ +/* function is not called by the compiler, all ThreadX initialization */ +/* takes place from the kernel enter function defined previously. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_smp_high_level_initialize SMP initialization */ +/* _tx_thread_smp_current_state_set Set system state for all cores */ +/* _tx_initialize_low_level Low-level initialization */ +/* _tx_initialize_high_level High-level initialization */ +/* */ +/* CALLED BY */ +/* */ +/* startup code Compiler startup code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_initialize_kernel_setup(VOID) +{ + + /* Ensure that the system state variable is set to indicate + initialization is in progress. Note that this variable is + later used to represent interrupt nesting. */ + _tx_thread_smp_current_state_set(TX_INITIALIZE_IN_PROGRESS); + + /* Call any port specific preprocessing. */ + TX_PORT_SPECIFIC_PRE_INITIALIZATION + + /* Invoke the low-level initialization to handle all processor specific + initialization issues. */ + _tx_initialize_low_level(); + + /* Call the high-level SMP Initialization. */ + _tx_thread_smp_high_level_initialize(); + + /* Invoke the high-level initialization to exercise all of the + ThreadX components and the application's initialization + function. */ + _tx_initialize_high_level(); + + /* Call any port specific post-processing. */ + TX_PORT_SPECIFIC_POST_INITIALIZATION + + /* Set the system state to indicate initialization is almost done. */ + _tx_thread_system_state[0] = TX_INITIALIZE_ALMOST_DONE; +} + diff --git a/common_smp/src/tx_misra.c b/common_smp/src/tx_misra.c new file mode 100644 index 00000000..291ff091 --- /dev/null +++ b/common_smp/src/tx_misra.c @@ -0,0 +1,833 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** ThreadX MISRA Compliance */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** _tx_version_id */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#ifdef TX_MISRA_ENABLE +#define TX_THREAD_INIT +//CHAR _tx_version_id[100] = "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX 6.0.1 MISRA C Compliant *"; +#endif + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_trace.h" + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_memset(VOID *ptr, UINT value, UINT size); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +VOID _tx_misra_memset(VOID *ptr, UINT value, UINT size) +{ + memset(ptr, value, size); +} + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UCHAR *_tx_misra_uchar_pointer_add(UCHAR *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +UCHAR *_tx_misra_uchar_pointer_add(UCHAR *ptr, ULONG amount) +{ + ptr = ptr + amount; + return(ptr); +} + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UCHAR *_tx_misra_uchar_pointer_sub(UCHAR *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +UCHAR *_tx_misra_uchar_pointer_sub(UCHAR *ptr, ULONG amount) +{ + ptr = ptr - amount; + return(ptr); +} + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_uchar_pointer_dif(UCHAR *ptr1, UCHAR *ptr2); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +ULONG _tx_misra_uchar_pointer_dif(UCHAR *ptr1, UCHAR *ptr2) +{ + +ULONG value; + + value = ptr1 - ptr2; + return(value); +} + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr) +{ + return((ULONG) ptr); +} + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG *_tx_misra_ulong_pointer_add(ULONG *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +ULONG *_tx_misra_ulong_pointer_add(ULONG *ptr, ULONG amount) +{ + ptr = ptr + amount; + return(ptr); +} + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG *_tx_misra_ulong_pointer_sub(ULONG *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +ULONG *_tx_misra_ulong_pointer_sub(ULONG *ptr, ULONG amount) +{ + + ptr = ptr - amount; + return(ptr); +} + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_ulong_pointer_dif(ULONG *ptr1, ULONG *ptr2); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +ULONG _tx_misra_ulong_pointer_dif(ULONG *ptr1, ULONG *ptr2) +{ +ULONG value; + + value = ptr1 - ptr2; + return(value); +} + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +VOID *_tx_misra_ulong_to_pointer_convert(ULONG input) +{ + + return((VOID *) input); +} + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_message_copy(ULONG **source, ULONG **destination, */ +/** UINT size); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +VOID _tx_misra_message_copy(ULONG **source, ULONG **destination, UINT size) +{ + +ULONG *s, *d; +UINT z; + + s = *source; + d = *destination; + z = size; + + *(d) = *(s); + (d)++; + (s)++; + if ((z) > ((UINT) 1)) + { + (z)--; + while ((z)) + { + *(d) = *(s); + (d)++; + (s)++; + (z)--; + } + } + + *source = s; + *destination = d; +} + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_timer_pointer_dif(TX_TIMER_INTERNAL **ptr1, */ +/** TX_TIMER_INTERNAL **ptr2); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +ULONG _tx_misra_timer_pointer_dif(TX_TIMER_INTERNAL **ptr1, TX_TIMER_INTERNAL **ptr2) +{ + +ULONG value; + + value = ptr1 - ptr2; + return(value); +} + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** TX_TIMER_INTERNAL **_tx_misra_timer_pointer_add(TX_TIMER_INTERNAL */ +/** **ptr1, ULONG size); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +TX_TIMER_INTERNAL **_tx_misra_timer_pointer_add(TX_TIMER_INTERNAL **ptr1, ULONG amount) +{ + ptr1 = ptr1 + amount; + return(ptr1); +} + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_user_timer_pointer_get(TX_TIMER_INTERNAL */ +/** *internal_timer, TX_TIMER **user_timer); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +VOID _tx_misra_user_timer_pointer_get(TX_TIMER_INTERNAL *internal_timer, TX_TIMER **user_timer) +{ + +UCHAR *working_ptr; +TX_TIMER *temp_timer; + + + working_ptr = (UCHAR *) internal_timer; + + temp_timer = (TX_TIMER *) working_ptr; + working_ptr = working_ptr - (((UCHAR *) &temp_timer -> tx_timer_internal) - ((UCHAR *) &temp_timer -> tx_timer_id)); + *user_timer = (TX_TIMER *) working_ptr; +} + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_thread_stack_check(TX_THREAD *thread_ptr, */ +/** VOID **highest_stack); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +VOID _tx_misra_thread_stack_check(TX_THREAD *thread_ptr, VOID **highest_stack) +{ + +TX_INTERRUPT_SAVE_AREA + + TX_DISABLE + if (((thread_ptr)) && ((thread_ptr) -> tx_thread_id == TX_THREAD_ID)) + { + if (((ULONG *) (thread_ptr) -> tx_thread_stack_ptr) < ((ULONG *) *highest_stack)) + { + *highest_stack = (thread_ptr) -> tx_thread_stack_ptr; + } + if ((*((ULONG *) (thread_ptr) -> tx_thread_stack_start) != TX_STACK_FILL) || + (*((ULONG *) (((UCHAR *) (thread_ptr) -> tx_thread_stack_end) + 1)) != TX_STACK_FILL) || + (((ULONG *) *highest_stack) < ((ULONG *) (thread_ptr) -> tx_thread_stack_start))) + { + TX_RESTORE + _tx_thread_stack_error_handler((thread_ptr)); + TX_DISABLE + } + if (*(((ULONG *) *highest_stack) - 1) != TX_STACK_FILL) + { + TX_RESTORE + _tx_thread_stack_analyze((thread_ptr)); + TX_DISABLE + } + } + TX_RESTORE +} + + +#ifdef TX_ENABLE_EVENT_TRACE + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_trace_event_insert(ULONG event_id, */ +/** VOID *info_field_1, ULONG info_field_2, ULONG info_field_3, */ +/** ULONG info_field_4, ULONG filter, ULONG time_stamp); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +VOID _tx_misra_trace_event_insert(ULONG event_id, VOID *info_field_1, ULONG info_field_2, ULONG info_field_3, ULONG info_field_4, ULONG filter, ULONG time_stamp) +{ + +TX_TRACE_BUFFER_ENTRY *trace_event_ptr; +ULONG trace_system_state; +ULONG trace_priority; +TX_THREAD *trace_thread_ptr; + + + trace_event_ptr = _tx_trace_buffer_current_ptr; + if ((trace_event_ptr) && (_tx_trace_event_enable_bits & ((ULONG) (filter)))) + { + TX_TRACE_PORT_EXTENSION + trace_system_state = (ULONG) _tx_thread_system_state; + trace_thread_ptr = _tx_thread_current_ptr; + + if (trace_system_state == 0) + { + trace_priority = trace_thread_ptr -> tx_thread_priority; + trace_priority = trace_priority | 0x80000000UL | (trace_thread_ptr -> tx_thread_preempt_threshold << 16); + } + else if (trace_system_state < 0xF0F0F0F0UL) + { + trace_priority = (ULONG) trace_thread_ptr; + trace_thread_ptr = (TX_THREAD *) 0xFFFFFFFFUL; + } + else + { + trace_thread_ptr = (TX_THREAD *) 0xF0F0F0F0UL; + trace_priority = 0; + } + trace_event_ptr -> tx_trace_buffer_entry_thread_pointer = (ULONG) trace_thread_ptr; + trace_event_ptr -> tx_trace_buffer_entry_thread_priority = (ULONG) trace_priority; + trace_event_ptr -> tx_trace_buffer_entry_event_id = (ULONG) (event_id); + trace_event_ptr -> tx_trace_buffer_entry_time_stamp = (ULONG) (time_stamp); +#ifdef TX_MISRA_ENABLE + trace_event_ptr -> tx_trace_buffer_entry_info_1 = (ULONG) (info_field_1); + trace_event_ptr -> tx_trace_buffer_entry_info_2 = (ULONG) (info_field_2); + trace_event_ptr -> tx_trace_buffer_entry_info_3 = (ULONG) (info_field_3); + trace_event_ptr -> tx_trace_buffer_entry_info_4 = (ULONG) (info_field_4); +#else + trace_event_ptr -> tx_trace_buffer_entry_information_field_1 = (ULONG) (info_field_1); + trace_event_ptr -> tx_trace_buffer_entry_information_field_2 = (ULONG) (info_field_2); + trace_event_ptr -> tx_trace_buffer_entry_information_field_3 = (ULONG) (info_field_3); + trace_event_ptr -> tx_trace_buffer_entry_information_field_4 = (ULONG) (info_field_4); +#endif + trace_event_ptr++; + if (trace_event_ptr >= _tx_trace_buffer_end_ptr) + { + trace_event_ptr = _tx_trace_buffer_start_ptr; + _tx_trace_buffer_current_ptr = trace_event_ptr; + _tx_trace_header_ptr -> tx_trace_header_buffer_current_pointer = (ULONG) trace_event_ptr; + if (_tx_trace_full_notify_function) + (_tx_trace_full_notify_function)((VOID *) _tx_trace_header_ptr); + } + else + { + _tx_trace_buffer_current_ptr = trace_event_ptr; + _tx_trace_header_ptr -> tx_trace_header_buffer_current_pointer = (ULONG) trace_event_ptr; + } + } +} + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_time_stamp_get(VOID); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +ULONG _tx_misra_time_stamp_get(VOID) +{ + + /* Return time stamp. */ + return(0); +} + +#endif + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UINT _tx_misra_always_true(void); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +UINT _tx_misra_always_true(void) +{ + return(TX_TRUE); +} + + +/******************************************************************************************/ +/******************************************************************************************/ +/** */ +/** UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr); */ +/** */ +/******************************************************************************************/ +/******************************************************************************************/ +UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr) +{ + + /* Return an indirect UCHAR pointer. */ + return((UCHAR **) ((VOID *) return_ptr)); +} + + +/***************************************************************************************/ +/***************************************************************************************/ +/** */ +/** UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); */ +/** */ +/***************************************************************************************/ +/***************************************************************************************/ +UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer) +{ + + /* Return an indirect UCHAR pointer. */ + return((UCHAR **) ((VOID *) pointer)); +} + + +/***********************************************************************************/ +/***********************************************************************************/ +/** */ +/** UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); */ +/** */ +/***********************************************************************************/ +/***********************************************************************************/ +UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool) +{ + + /* Return a UCHAR pointer. */ + return((UCHAR *) ((VOID *) pool)); +} + + +/******************************************************************************************/ +/******************************************************************************************/ +/** */ +/** TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); */ +/** */ +/******************************************************************************************/ +/******************************************************************************************/ +TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer) +{ + + /* Return a block pool pointer. */ + return((TX_BLOCK_POOL *) ((VOID *) pointer)); +} + + +/*****************************************************************************/ +/*****************************************************************************/ +/** */ +/** UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); */ +/** */ +/*****************************************************************************/ +/*****************************************************************************/ +UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer) +{ + + /* Return a UCHAR pointer. */ + return((UCHAR *) ((VOID *) pointer)); +} + + +/************************************************************************************/ +/************************************************************************************/ +/** */ +/** TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); */ +/** */ +/************************************************************************************/ +/************************************************************************************/ +TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer) +{ + + /* Return a UCHAR pointer. */ + return((TX_BLOCK_POOL *) ((VOID *) pointer)); +} + + +/**************************************************************************************/ +/**************************************************************************************/ +/** */ +/** UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); */ +/** */ +/**************************************************************************************/ +/**************************************************************************************/ +UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer) +{ + + /* Return a UCHAR pointer. */ + return((UCHAR **) ((VOID *) pointer)); +} + + +/*****************************************************************************************/ +/*****************************************************************************************/ +/** */ +/** TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); */ +/** */ +/*****************************************************************************************/ +/*****************************************************************************************/ +TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer) +{ + + /* Return a byte pool pointer. */ + return((TX_BYTE_POOL *) ((VOID *) pointer)); +} + + +/***************************************************************************************/ +/***************************************************************************************/ +/** */ +/** UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); */ +/** */ +/***************************************************************************************/ +/***************************************************************************************/ +UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool) +{ + + /* Return a UCHAR pointer. */ + return((UCHAR *) ((VOID *) pool)); +} + + +/*****************************************************************************************/ +/*****************************************************************************************/ +/** */ +/** ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); */ +/** */ +/*****************************************************************************************/ +/*****************************************************************************************/ +ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer) +{ + + /* Return an align time pointer. */ + return((ALIGN_TYPE *) ((VOID *) pointer)); +} + + +/****************************************************************************************************/ +/****************************************************************************************************/ +/** */ +/** TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); */ +/** */ +/****************************************************************************************************/ +/****************************************************************************************************/ +TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer) +{ + + /* Return a byte pool pointer. */ + return((TX_BYTE_POOL **) ((VOID *) pointer)); +} + + +/**************************************************************************************************/ +/**************************************************************************************************/ +/** */ +/** TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); */ +/** */ +/**************************************************************************************************/ +/**************************************************************************************************/ +TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer) +{ + + /* Return event flags pointer. */ + return((TX_EVENT_FLAGS_GROUP *) ((VOID *) pointer)); +} + + +/*****************************************************************************/ +/*****************************************************************************/ +/** */ +/** ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); */ +/** */ +/*****************************************************************************/ +/*****************************************************************************/ +ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer) +{ + + /* Return a ULONG pointer. */ + return((ULONG *) ((VOID *) pointer)); +} + + +/********************************************************************************/ +/********************************************************************************/ +/** */ +/** TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); */ +/** */ +/********************************************************************************/ +/********************************************************************************/ +TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer) +{ + + /* Return a mutex pointer. */ + return((TX_MUTEX *) ((VOID *) pointer)); +} + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UINT _tx_misra_status_get(UINT status); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +UINT _tx_misra_status_get(UINT status) +{ + + /* Return a successful status. */ + return(TX_SUCCESS); +} + + +/********************************************************************************/ +/********************************************************************************/ +/** */ +/** TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); */ +/** */ +/********************************************************************************/ +/********************************************************************************/ +TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer) +{ + + /* Return queue pointer. */ + return((TX_QUEUE *) ((VOID *) pointer)); +} + + +/****************************************************************************************/ +/****************************************************************************************/ +/** */ +/** TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); */ +/** */ +/****************************************************************************************/ +/****************************************************************************************/ +TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer) +{ + + /* Return semaphore pointer. */ + return((TX_SEMAPHORE *) ((VOID *) pointer)); +} + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer) +{ + + /* Return a VOID pointer. */ + return((VOID *) ((VOID *) pointer)); +} + + +/*********************************************************************************/ +/*********************************************************************************/ +/** */ +/** TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); */ +/** */ +/*********************************************************************************/ +/*********************************************************************************/ +TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value) +{ + + /* Return a thread pointer. */ + return((TX_THREAD *) ((VOID *) value)); +} + + +/***************************************************************************************************/ +/***************************************************************************************************/ +/** */ +/** VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); */ +/** */ +/***************************************************************************************************/ +/***************************************************************************************************/ +VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer) +{ + + /* Return a void pointer. */ + return((VOID *) ((VOID *) pointer)); +} + + +/***************************************************************************************/ +/***************************************************************************************/ +/** */ +/** CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); */ +/** */ +/***************************************************************************************/ +/***************************************************************************************/ +CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer) +{ + + /* Return a CHAR pointer. */ + return((CHAR *) ((VOID *) pointer)); +} + + +/**********************************************************************************/ +/**********************************************************************************/ +/** */ +/** TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer); */ +/** */ +/**********************************************************************************/ +/**********************************************************************************/ +TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer) +{ + + /* Return thread pointer. */ + return((TX_THREAD *) ((VOID *) pointer)); +} + + +#ifdef TX_ENABLE_EVENT_TRACE + +/************************************************************************************************/ +/************************************************************************************************/ +/** */ +/** UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); */ +/** */ +/************************************************************************************************/ +/************************************************************************************************/ +UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer) +{ + + /* Return a UCHAR pointer. */ + return((UCHAR *) ((VOID *) pointer)); +} + + +/************************************************************************************************/ +/************************************************************************************************/ +/** */ +/** TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); */ +/** */ +/************************************************************************************************/ +/************************************************************************************************/ +TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer) +{ + + /* Return an object entry pointer. */ + return((TX_TRACE_OBJECT_ENTRY *) ((VOID *) pointer)); +} + + +/******************************************************************************************/ +/******************************************************************************************/ +/** */ +/** TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); */ +/** */ +/******************************************************************************************/ +/******************************************************************************************/ +TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer) +{ + + /* Return a trace header pointer. */ + return((TX_TRACE_HEADER *) ((VOID *) pointer)); +} + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ +TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer) +{ + + /* Return a trace buffer entry pointer. */ + return((TX_TRACE_BUFFER_ENTRY *) ((VOID *) pointer)); +} + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ +UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer) +{ + + /* Return a UCHAR pointer. */ + return((UCHAR *) ((VOID *) pointer)); +} + +#endif + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ +UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer) +{ + + /* Return a UCHAR pointer. */ + return((UCHAR *) ((VOID *) pointer)); +} + + + diff --git a/common_smp/src/tx_mutex_cleanup.c b/common_smp/src/tx_mutex_cleanup.c new file mode 100644 index 00000000..88d6e313 --- /dev/null +++ b/common_smp/src/tx_mutex_cleanup.c @@ -0,0 +1,313 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Mutex */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_mutex.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_mutex_cleanup PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes mutex timeout and thread terminate */ +/* actions that require the mutex data structures to be cleaned */ +/* up. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to suspended thread's */ +/* control block */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_system_resume Resume thread service */ +/* _tx_thread_system_ni_resume Non-interruptable resume thread */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_timeout Thread timeout processing */ +/* _tx_thread_terminate Thread terminate processing */ +/* _tx_thread_wait_abort Thread wait abort processing */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_mutex_cleanup(TX_THREAD *thread_ptr, ULONG suspension_sequence) +{ + +#ifndef TX_NOT_INTERRUPTABLE +TX_INTERRUPT_SAVE_AREA +#endif + +TX_MUTEX *mutex_ptr; +UINT suspended_count; +TX_THREAD *next_thread; +TX_THREAD *previous_thread; + + +#ifndef TX_NOT_INTERRUPTABLE + + /* Disable interrupts to remove the suspended thread from the mutex. */ + TX_DISABLE + + /* Determine if the cleanup is still required. */ + if (thread_ptr -> tx_thread_suspend_cleanup == &(_tx_mutex_cleanup)) + { + + /* Check for valid suspension sequence. */ + if (suspension_sequence == thread_ptr -> tx_thread_suspension_sequence) + { + + /* Setup pointer to mutex control block. */ + mutex_ptr = TX_VOID_TO_MUTEX_POINTER_CONVERT(thread_ptr -> tx_thread_suspend_control_block); + + /* Check for NULL mutex pointer. */ + if (mutex_ptr != TX_NULL) + { + + /* Determine if the mutex ID is valid. */ + if (mutex_ptr -> tx_mutex_id == TX_MUTEX_ID) + { + + /* Determine if there are any thread suspensions. */ + if (mutex_ptr -> tx_mutex_suspended_count != TX_NO_SUSPENSIONS) + { +#else + + /* Setup pointer to mutex control block. */ + mutex_ptr = TX_VOID_TO_MUTEX_POINTER_CONVERT(thread_ptr -> tx_thread_suspend_control_block); +#endif + + /* Yes, we still have thread suspension! */ + + /* Clear the suspension cleanup flag. */ + thread_ptr -> tx_thread_suspend_cleanup = TX_NULL; + + /* Decrement the suspension count. */ + mutex_ptr -> tx_mutex_suspended_count--; + + /* Pickup the suspended count. */ + suspended_count = mutex_ptr -> tx_mutex_suspended_count; + + /* Remove the suspended thread from the list. */ + + /* See if this is the only suspended thread on the list. */ + if (suspended_count == TX_NO_SUSPENSIONS) + { + + /* Yes, the only suspended thread. */ + + /* Update the head pointer. */ + mutex_ptr -> tx_mutex_suspension_list = TX_NULL; + } + else + { + + /* At least one more thread is on the same suspension list. */ + + /* Update the links of the adjacent threads. */ + next_thread = thread_ptr -> tx_thread_suspended_next; + previous_thread = thread_ptr -> tx_thread_suspended_previous; + next_thread -> tx_thread_suspended_previous = previous_thread; + previous_thread -> tx_thread_suspended_next = next_thread; + + /* Determine if we need to update the head pointer. */ + if (mutex_ptr -> tx_mutex_suspension_list == thread_ptr) + { + + /* Update the list head pointer. */ + mutex_ptr -> tx_mutex_suspension_list = next_thread; + } + } + + /* Now we need to determine if this cleanup is from a terminate, timeout, + or from a wait abort. */ + if (thread_ptr -> tx_thread_state == TX_MUTEX_SUSP) + { + + /* Timeout condition and the thread still suspended on the mutex. + Setup return error status and resume the thread. */ + +#ifdef TX_MUTEX_ENABLE_PERFORMANCE_INFO + + /* Increment the total timeouts counter. */ + _tx_mutex_performance_timeout_count++; + + /* Increment the number of timeouts on this semaphore. */ + mutex_ptr -> tx_mutex_performance_timeout_count++; +#endif + + /* Setup return status. */ + thread_ptr -> tx_thread_suspend_status = TX_NOT_AVAILABLE; + +#ifdef TX_NOT_INTERRUPTABLE + + /* Resume the thread! */ + _tx_thread_system_ni_resume(thread_ptr); +#else + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Resume the thread! */ + _tx_thread_system_resume(thread_ptr); + + /* Disable interrupts. */ + TX_DISABLE +#endif + } +#ifndef TX_NOT_INTERRUPTABLE + } + } + } + } + } + + /* Restore interrupts. */ + TX_RESTORE +#endif +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_mutex_thread_release PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function releases all mutexes owned by the thread. This */ +/* function is called when the thread completes or is terminated. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread's control block */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_mutex_put Release the mutex */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_shell_entry Thread completion processing */ +/* _tx_thread_terminate Thread terminate processing */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_mutex_thread_release(TX_THREAD *thread_ptr) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_MUTEX *mutex_ptr; +#ifdef TX_MISRA_ENABLE +UINT status; +#endif + + + /* Disable interrupts. */ + TX_DISABLE + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Loop to look at all the mutexes. */ + do + { + + /* Pickup the mutex head pointer. */ + mutex_ptr = thread_ptr -> tx_thread_owned_mutex_list; + + /* Determine if there is a mutex. */ + if (mutex_ptr != TX_NULL) + { + + /* Yes, set the ownership count to 1. */ + mutex_ptr -> tx_mutex_ownership_count = ((UINT) 1); + + /* Restore interrupts. */ + TX_RESTORE + +#ifdef TX_MISRA_ENABLE + /* Release the mutex. */ + do + { + status = _tx_mutex_put(mutex_ptr); + } while (status != TX_SUCCESS); +#else + _tx_mutex_put(mutex_ptr); +#endif + + /* Disable interrupts. */ + TX_DISABLE + + /* Move to the next mutex. */ + mutex_ptr = thread_ptr -> tx_thread_owned_mutex_list; + } + } while (mutex_ptr != TX_NULL); + + /* Restore preemption. */ + _tx_thread_preempt_disable--; + + /* Restore interrupts. */ + TX_RESTORE +} + diff --git a/common_smp/src/tx_mutex_create.c b/common_smp/src/tx_mutex_create.c new file mode 100644 index 00000000..ea53fe2d --- /dev/null +++ b/common_smp/src/tx_mutex_create.c @@ -0,0 +1,146 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Mutex */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_trace.h" +#include "tx_mutex.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_mutex_create PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates a mutex with optional priority inheritance as */ +/* specified in this call. */ +/* */ +/* INPUT */ +/* */ +/* mutex_ptr Pointer to mutex control block*/ +/* name_ptr Pointer to mutex name */ +/* inherit Priority inheritance option */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SUCCESS Successful completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_mutex_create(TX_MUTEX *mutex_ptr, CHAR *name_ptr, UINT inherit) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_MUTEX *next_mutex; +TX_MUTEX *previous_mutex; + + + /* Initialize mutex control block to all zeros. */ + TX_MEMSET(mutex_ptr, 0, (sizeof(TX_MUTEX))); + + /* Setup the basic mutex fields. */ + mutex_ptr -> tx_mutex_name = name_ptr; + mutex_ptr -> tx_mutex_inherit = inherit; + + /* Disable interrupts to place the mutex on the created list. */ + TX_DISABLE + + /* Setup the mutex ID to make it valid. */ + mutex_ptr -> tx_mutex_id = TX_MUTEX_ID; + + /* Setup the thread mutex release function pointer. */ + _tx_thread_mutex_release = &(_tx_mutex_thread_release); + + /* Place the mutex on the list of created mutexes. First, + check for an empty list. */ + if (_tx_mutex_created_count == TX_EMPTY) + { + + /* The created mutex list is empty. Add mutex to empty list. */ + _tx_mutex_created_ptr = mutex_ptr; + mutex_ptr -> tx_mutex_created_next = mutex_ptr; + mutex_ptr -> tx_mutex_created_previous = mutex_ptr; + } + else + { + + /* This list is not NULL, add to the end of the list. */ + next_mutex = _tx_mutex_created_ptr; + previous_mutex = next_mutex -> tx_mutex_created_previous; + + /* Place the new mutex in the list. */ + next_mutex -> tx_mutex_created_previous = mutex_ptr; + previous_mutex -> tx_mutex_created_next = mutex_ptr; + + /* Setup this mutex's next and previous created links. */ + mutex_ptr -> tx_mutex_created_previous = previous_mutex; + mutex_ptr -> tx_mutex_created_next = next_mutex; + } + + /* Increment the ownership count. */ + _tx_mutex_created_count++; + + /* Optional mutex create extended processing. */ + TX_MUTEX_CREATE_EXTENSION(mutex_ptr) + + /* If trace is enabled, register this object. */ + TX_TRACE_OBJECT_REGISTER(TX_TRACE_OBJECT_TYPE_MUTEX, mutex_ptr, name_ptr, inherit, 0) + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_MUTEX_CREATE, mutex_ptr, inherit, TX_POINTER_TO_ULONG_CONVERT(&next_mutex), 0, TX_TRACE_MUTEX_EVENTS) + + /* Log this kernel call. */ + TX_EL_MUTEX_CREATE_INSERT + + /* Restore interrupts. */ + TX_RESTORE + + /* Return TX_SUCCESS. */ + return(TX_SUCCESS); +} + diff --git a/common_smp/src/tx_mutex_delete.c b/common_smp/src/tx_mutex_delete.c new file mode 100644 index 00000000..0f91ed3f --- /dev/null +++ b/common_smp/src/tx_mutex_delete.c @@ -0,0 +1,243 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Mutex */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_thread.h" +#include "tx_mutex.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_mutex_delete PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function deletes the specified mutex. All threads */ +/* suspended on the mutex are resumed with the TX_DELETED status */ +/* code. */ +/* */ +/* INPUT */ +/* */ +/* mutex_ptr Pointer to mutex control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SUCCESS Successful completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_mutex_put Release an owned mutex */ +/* _tx_thread_system_preempt_check Check for preemption */ +/* _tx_thread_system_resume Resume thread service */ +/* _tx_thread_system_ni_resume Non-interruptable resume thread */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_mutex_delete(TX_MUTEX *mutex_ptr) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_THREAD *thread_ptr; +TX_THREAD *next_thread; +TX_THREAD *owner_thread; +UINT suspended_count; +TX_MUTEX *next_mutex; +TX_MUTEX *previous_mutex; +#ifdef TX_MISRA_ENABLE +UINT status; +#endif + + /* Disable interrupts to remove the mutex from the created list. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_MUTEX_DELETE, mutex_ptr, TX_POINTER_TO_ULONG_CONVERT(&thread_ptr), 0, 0, TX_TRACE_MUTEX_EVENTS) + + /* Optional mutex delete extended processing. */ + TX_MUTEX_DELETE_EXTENSION(mutex_ptr) + + /* If trace is enabled, unregister this object. */ + TX_TRACE_OBJECT_UNREGISTER(mutex_ptr) + + /* Log this kernel call. */ + TX_EL_MUTEX_DELETE_INSERT + + /* Clear the mutex ID to make it invalid. */ + mutex_ptr -> tx_mutex_id = TX_CLEAR_ID; + + /* Decrement the created count. */ + _tx_mutex_created_count--; + + /* See if the mutex is the only one on the list. */ + if (_tx_mutex_created_count == TX_EMPTY) + { + + /* Only created mutex, just set the created list to NULL. */ + _tx_mutex_created_ptr = TX_NULL; + } + else + { + + /* Link-up the neighbors. */ + next_mutex = mutex_ptr -> tx_mutex_created_next; + previous_mutex = mutex_ptr -> tx_mutex_created_previous; + next_mutex -> tx_mutex_created_previous = previous_mutex; + previous_mutex -> tx_mutex_created_next = next_mutex; + + /* See if we have to update the created list head pointer. */ + if (_tx_mutex_created_ptr == mutex_ptr) + { + + /* Yes, move the head pointer to the next link. */ + _tx_mutex_created_ptr = next_mutex; + } + } + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Pickup the suspension information. */ + thread_ptr = mutex_ptr -> tx_mutex_suspension_list; + mutex_ptr -> tx_mutex_suspension_list = TX_NULL; + suspended_count = mutex_ptr -> tx_mutex_suspended_count; + mutex_ptr -> tx_mutex_suspended_count = TX_NO_SUSPENSIONS; + + + /* Determine if the mutex is currently on a thread's ownership list. */ + + /* Setup pointer to owner of mutex. */ + owner_thread = mutex_ptr -> tx_mutex_owner; + + /* Determine if there is a valid thread pointer. */ + if (owner_thread != TX_NULL) + { + + /* Yes, remove this mutex from the owned list. */ + + /* Set the ownership count to 1. */ + mutex_ptr -> tx_mutex_ownership_count = ((UINT) 1); + + /* Restore interrupts. */ + TX_RESTORE + +#ifdef TX_MISRA_ENABLE + /* Release the mutex. */ + do + { + status = _tx_mutex_put(mutex_ptr); + } while (status != TX_SUCCESS); +#else + _tx_mutex_put(mutex_ptr); +#endif + + /* Disable interrupts. */ + TX_DISABLE + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Walk through the mutex list to resume any and all threads suspended + on this mutex. */ + while (suspended_count != ((ULONG) 0)) + { + + /* Decrement the suspension count. */ + suspended_count--; + + /* Lockout interrupts. */ + TX_DISABLE + + /* Clear the cleanup pointer, this prevents the timeout from doing + anything. */ + thread_ptr -> tx_thread_suspend_cleanup = TX_NULL; + + /* Set the return status in the thread to TX_DELETED. */ + thread_ptr -> tx_thread_suspend_status = TX_DELETED; + + /* Move the thread pointer ahead. */ + next_thread = thread_ptr -> tx_thread_suspended_next; + +#ifdef TX_NOT_INTERRUPTABLE + + /* Resume the thread! */ + _tx_thread_system_ni_resume(thread_ptr); + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Temporarily disable preemption again. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Resume the thread. */ + _tx_thread_system_resume(thread_ptr); +#endif + + /* Move to next thread. */ + thread_ptr = next_thread; + } + + /* Execute Port-Specific completion processing. If needed, it is typically defined in tx_port.h. */ + TX_MUTEX_DELETE_PORT_COMPLETION(mutex_ptr) + + /* Disable interrupts. */ + TX_DISABLE + + /* Release previous preempt disable. */ + _tx_thread_preempt_disable--; + + /* Restore interrupts. */ + TX_RESTORE + + /* Check for preemption. */ + _tx_thread_system_preempt_check(); + + /* Return TX_SUCCESS. */ + return(TX_SUCCESS); +} + diff --git a/common_smp/src/tx_mutex_get.c b/common_smp/src/tx_mutex_get.c new file mode 100644 index 00000000..98b019d2 --- /dev/null +++ b/common_smp/src/tx_mutex_get.c @@ -0,0 +1,409 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Mutex */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_thread.h" +#include "tx_mutex.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_mutex_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets the specified mutex. If the calling thread */ +/* already owns the mutex, an ownership count is simply increased. */ +/* */ +/* INPUT */ +/* */ +/* mutex_ptr Pointer to mutex control block */ +/* wait_option Suspension option */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_system_suspend Suspend thread service */ +/* _tx_thread_system_ni_suspend Non-interruptable suspend thread */ +/* _tx_mutex_priority_change Inherit thread priority */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_mutex_get(TX_MUTEX *mutex_ptr, ULONG wait_option) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_THREAD *thread_ptr; +TX_MUTEX *next_mutex; +TX_MUTEX *previous_mutex; +TX_THREAD *mutex_owner; +TX_THREAD *next_thread; +TX_THREAD *previous_thread; +UINT status; + + + /* Disable interrupts to get an instance from the mutex. */ + TX_DISABLE + +#ifdef TX_MUTEX_ENABLE_PERFORMANCE_INFO + + /* Increment the total mutex get counter. */ + _tx_mutex_performance_get_count++; + + /* Increment the number of attempts to get this mutex. */ + mutex_ptr -> tx_mutex_performance_get_count++; +#endif + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_MUTEX_GET, mutex_ptr, wait_option, TX_POINTER_TO_ULONG_CONVERT(mutex_ptr -> tx_mutex_owner), mutex_ptr -> tx_mutex_ownership_count, TX_TRACE_MUTEX_EVENTS) + + /* Log this kernel call. */ + TX_EL_MUTEX_GET_INSERT + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr) + + /* Determine if this mutex is available. */ + if (mutex_ptr -> tx_mutex_ownership_count == ((UINT) 0)) + { + + /* Set the ownership count to 1. */ + mutex_ptr -> tx_mutex_ownership_count = ((UINT) 1); + + /* Remember that the calling thread owns the mutex. */ + mutex_ptr -> tx_mutex_owner = thread_ptr; + + /* Determine if the thread pointer is valid. */ + if (thread_ptr != TX_NULL) + { + + /* Determine if priority inheritance is required. */ + if (mutex_ptr -> tx_mutex_inherit == TX_TRUE) + { + + /* Remember the current priority of thread. */ + mutex_ptr -> tx_mutex_original_priority = thread_ptr -> tx_thread_priority; + + /* Setup the highest priority waiting thread. */ + mutex_ptr -> tx_mutex_highest_priority_waiting = ((UINT) TX_MAX_PRIORITIES); + } + + /* Pickup next mutex pointer, which is the head of the list. */ + next_mutex = thread_ptr -> tx_thread_owned_mutex_list; + + /* Determine if this thread owns any other mutexes that have priority inheritance. */ + if (next_mutex != TX_NULL) + { + + /* Non-empty list. Link up the mutex. */ + + /* Pickup the next and previous mutex pointer. */ + previous_mutex = next_mutex -> tx_mutex_owned_previous; + + /* Place the owned mutex in the list. */ + next_mutex -> tx_mutex_owned_previous = mutex_ptr; + previous_mutex -> tx_mutex_owned_next = mutex_ptr; + + /* Setup this mutex's next and previous created links. */ + mutex_ptr -> tx_mutex_owned_previous = previous_mutex; + mutex_ptr -> tx_mutex_owned_next = next_mutex; + } + else + { + + /* The owned mutex list is empty. Add mutex to empty list. */ + thread_ptr -> tx_thread_owned_mutex_list = mutex_ptr; + mutex_ptr -> tx_mutex_owned_next = mutex_ptr; + mutex_ptr -> tx_mutex_owned_previous = mutex_ptr; + } + + /* Increment the number of mutexes owned counter. */ + thread_ptr -> tx_thread_owned_mutex_count++; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return success. */ + status = TX_SUCCESS; + } + + /* Otherwise, see if the owning thread is trying to obtain the same mutex. */ + else if (mutex_ptr -> tx_mutex_owner == thread_ptr) + { + + /* The owning thread is requesting the mutex again, just + increment the ownership count. */ + mutex_ptr -> tx_mutex_ownership_count++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Return success. */ + status = TX_SUCCESS; + } + else + { + + /* Determine if the request specifies suspension. */ + if (wait_option != TX_NO_WAIT) + { + + /* Determine if the preempt disable flag is non-zero. */ + if (_tx_thread_preempt_disable != ((UINT) 0)) + { + + /* Restore interrupts. */ + TX_RESTORE + + /* Suspension is not allowed if the preempt disable flag is non-zero at this point - return error completion. */ + status = TX_NOT_AVAILABLE; + } + else + { + + /* Prepare for suspension of this thread. */ + + /* Pickup the mutex owner. */ + mutex_owner = mutex_ptr -> tx_mutex_owner; + +#ifdef TX_MUTEX_ENABLE_PERFORMANCE_INFO + + /* Increment the total mutex suspension counter. */ + _tx_mutex_performance_suspension_count++; + + /* Increment the number of suspensions on this mutex. */ + mutex_ptr -> tx_mutex_performance_suspension_count++; + + /* Determine if a priority inversion is present. */ + if (thread_ptr -> tx_thread_priority < mutex_owner -> tx_thread_priority) + { + + /* Yes, priority inversion is present! */ + + /* Increment the total mutex priority inversions counter. */ + _tx_mutex_performance_priority_inversion_count++; + + /* Increment the number of priority inversions on this mutex. */ + mutex_ptr -> tx_mutex_performance_priority_inversion_count++; + +#ifdef TX_THREAD_ENABLE_PERFORMANCE_INFO + + /* Increment the number of total thread priority inversions. */ + _tx_thread_performance_priority_inversion_count++; + + /* Increment the number of priority inversions for this thread. */ + thread_ptr -> tx_thread_performance_priority_inversion_count++; +#endif + } +#endif + + /* Setup cleanup routine pointer. */ + thread_ptr -> tx_thread_suspend_cleanup = &(_tx_mutex_cleanup); + + /* Setup cleanup information, i.e. this mutex control + block. */ + thread_ptr -> tx_thread_suspend_control_block = (VOID *) mutex_ptr; + +#ifndef TX_NOT_INTERRUPTABLE + + /* Increment the suspension sequence number, which is used to identify + this suspension event. */ + thread_ptr -> tx_thread_suspension_sequence++; +#endif + + /* Setup suspension list. */ + if (mutex_ptr -> tx_mutex_suspended_count == TX_NO_SUSPENSIONS) + { + + /* No other threads are suspended. Setup the head pointer and + just setup this threads pointers to itself. */ + mutex_ptr -> tx_mutex_suspension_list = thread_ptr; + thread_ptr -> tx_thread_suspended_next = thread_ptr; + thread_ptr -> tx_thread_suspended_previous = thread_ptr; + } + else + { + + /* This list is not NULL, add current thread to the end. */ + next_thread = mutex_ptr -> tx_mutex_suspension_list; + thread_ptr -> tx_thread_suspended_next = next_thread; + previous_thread = next_thread -> tx_thread_suspended_previous; + thread_ptr -> tx_thread_suspended_previous = previous_thread; + previous_thread -> tx_thread_suspended_next = thread_ptr; + next_thread -> tx_thread_suspended_previous = thread_ptr; + } + + /* Increment the suspension count. */ + mutex_ptr -> tx_mutex_suspended_count++; + + /* Set the state to suspended. */ + thread_ptr -> tx_thread_state = TX_MUTEX_SUSP; + +#ifdef TX_NOT_INTERRUPTABLE + + /* Determine if we need to raise the priority of the thread + owning the mutex. */ + if (mutex_ptr -> tx_mutex_inherit == TX_TRUE) + { + + /* Determine if this is the highest priority to raise for this mutex. */ + if (mutex_ptr -> tx_mutex_highest_priority_waiting > thread_ptr -> tx_thread_priority) + { + + /* Remember this priority. */ + mutex_ptr -> tx_mutex_highest_priority_waiting = thread_ptr -> tx_thread_priority; + } + + /* Determine if we have to update inherit priority level of the mutex owner. */ + if (thread_ptr -> tx_thread_priority < mutex_owner -> tx_thread_inherit_priority) + { + + /* Remember the new priority inheritance priority. */ + mutex_owner -> tx_thread_inherit_priority = thread_ptr -> tx_thread_priority; + } + + /* Priority inheritance is requested, check to see if the thread that owns the mutex is lower priority. */ + if (mutex_owner -> tx_thread_priority > thread_ptr -> tx_thread_priority) + { + + /* Yes, raise the suspended, owning thread's priority to that + of the current thread. */ + _tx_mutex_priority_change(mutex_owner, thread_ptr -> tx_thread_priority); + +#ifdef TX_MUTEX_ENABLE_PERFORMANCE_INFO + + /* Increment the total mutex priority inheritance counter. */ + _tx_mutex_performance__priority_inheritance_count++; + + /* Increment the number of priority inheritance situations on this mutex. */ + mutex_ptr -> tx_mutex_performance__priority_inheritance_count++; +#endif + } + } + + /* Call actual non-interruptable thread suspension routine. */ + _tx_thread_system_ni_suspend(thread_ptr, wait_option); + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Set the suspending flag. */ + thread_ptr -> tx_thread_suspending = TX_TRUE; + + /* Setup the timeout period. */ + thread_ptr -> tx_thread_timer.tx_timer_internal_remaining_ticks = wait_option; + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Determine if we need to raise the priority of the thread + owning the mutex. */ + if (mutex_ptr -> tx_mutex_inherit == TX_TRUE) + { + + /* Determine if this is the highest priority to raise for this mutex. */ + if (mutex_ptr -> tx_mutex_highest_priority_waiting > thread_ptr -> tx_thread_priority) + { + + /* Remember this priority. */ + mutex_ptr -> tx_mutex_highest_priority_waiting = thread_ptr -> tx_thread_priority; + } + + /* Determine if we have to update inherit priority level of the mutex owner. */ + if (thread_ptr -> tx_thread_priority < mutex_owner -> tx_thread_inherit_priority) + { + + /* Remember the new priority inheritance priority. */ + mutex_owner -> tx_thread_inherit_priority = thread_ptr -> tx_thread_priority; + } + + /* Priority inheritance is requested, check to see if the thread that owns the mutex is lower priority. */ + if (mutex_owner -> tx_thread_priority > thread_ptr -> tx_thread_priority) + { + + /* Yes, raise the suspended, owning thread's priority to that + of the current thread. */ + _tx_mutex_priority_change(mutex_owner, thread_ptr -> tx_thread_priority); + +#ifdef TX_MUTEX_ENABLE_PERFORMANCE_INFO + + /* Increment the total mutex priority inheritance counter. */ + _tx_mutex_performance__priority_inheritance_count++; + + /* Increment the number of priority inheritance situations on this mutex. */ + mutex_ptr -> tx_mutex_performance__priority_inheritance_count++; +#endif + } + } + + /* Call actual thread suspension routine. */ + _tx_thread_system_suspend(thread_ptr); +#endif + /* Return the completion status. */ + status = thread_ptr -> tx_thread_suspend_status; + } + } + else + { + + /* Restore interrupts. */ + TX_RESTORE + + /* Immediate return, return error completion. */ + status = TX_NOT_AVAILABLE; + } + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/tx_mutex_info_get.c b/common_smp/src/tx_mutex_info_get.c new file mode 100644 index 00000000..769ce02d --- /dev/null +++ b/common_smp/src/tx_mutex_info_get.c @@ -0,0 +1,147 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Mutex */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_mutex.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_mutex_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves information from the specified mutex. */ +/* */ +/* INPUT */ +/* */ +/* mutex_ptr Pointer to mutex control block */ +/* name Destination for the mutex name */ +/* count Destination for the owner count */ +/* owner Destination for the owner's */ +/* thread control block pointer */ +/* first_suspended Destination for pointer of first */ +/* thread suspended on the mutex */ +/* suspended_count Destination for suspended count */ +/* next_mutex Destination for pointer to next */ +/* mutex on the created list */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_mutex_info_get(TX_MUTEX *mutex_ptr, CHAR **name, ULONG *count, TX_THREAD **owner, + TX_THREAD **first_suspended, ULONG *suspended_count, + TX_MUTEX **next_mutex) +{ + +TX_INTERRUPT_SAVE_AREA + + + /* Disable interrupts. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_MUTEX_INFO_GET, mutex_ptr, 0, 0, 0, TX_TRACE_MUTEX_EVENTS) + + /* Log this kernel call. */ + TX_EL_MUTEX_INFO_GET_INSERT + + /* Retrieve all the pertinent information and return it in the supplied + destinations. */ + + /* Retrieve the name of the mutex. */ + if (name != TX_NULL) + { + + *name = mutex_ptr -> tx_mutex_name; + } + + /* Retrieve the current ownership count of the mutex. */ + if (count != TX_NULL) + { + + *count = ((ULONG) mutex_ptr -> tx_mutex_ownership_count); + } + + /* Retrieve the current owner of the mutex. */ + if (owner != TX_NULL) + { + + *owner = mutex_ptr -> tx_mutex_owner; + } + + /* Retrieve the first thread suspended on this mutex. */ + if (first_suspended != TX_NULL) + { + + *first_suspended = mutex_ptr -> tx_mutex_suspension_list; + } + + /* Retrieve the number of threads suspended on this mutex. */ + if (suspended_count != TX_NULL) + { + + *suspended_count = (ULONG) mutex_ptr -> tx_mutex_suspended_count; + } + + /* Retrieve the pointer to the next mutex created. */ + if (next_mutex != TX_NULL) + { + + *next_mutex = mutex_ptr -> tx_mutex_created_next; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return completion status. */ + return(TX_SUCCESS); +} + diff --git a/common_smp/src/tx_mutex_initialize.c b/common_smp/src/tx_mutex_initialize.c new file mode 100644 index 00000000..3d53a99e --- /dev/null +++ b/common_smp/src/tx_mutex_initialize.c @@ -0,0 +1,141 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Mutex */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_mutex.h" + + +#ifndef TX_INLINE_INITIALIZATION + +/* Locate mutex component data in this file. */ + +/* Define the head pointer of the created mutex list. */ + +TX_MUTEX * _tx_mutex_created_ptr; + + +/* Define the variable that holds the number of created mutexes. */ + +ULONG _tx_mutex_created_count; + + +#ifdef TX_MUTEX_ENABLE_PERFORMANCE_INFO + +/* Define the total number of mutex puts. */ + +ULONG _tx_mutex_performance_put_count; + + +/* Define the total number of mutex gets. */ + +ULONG _tx_mutex_performance_get_count; + + +/* Define the total number of mutex suspensions. */ + +ULONG _tx_mutex_performance_suspension_count; + + +/* Define the total number of mutex timeouts. */ + +ULONG _tx_mutex_performance_timeout_count; + + +/* Define the total number of priority inversions. */ + +ULONG _tx_mutex_performance_priority_inversion_count; + + +/* Define the total number of priority inheritance conditions. */ + +ULONG _tx_mutex_performance__priority_inheritance_count; + +#endif +#endif + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_mutex_initialize PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes the various control data structures for */ +/* the mutex component. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_high_level High level initialization */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_mutex_initialize(VOID) +{ + +#ifndef TX_DISABLE_REDUNDANT_CLEARING + + /* Initialize the head pointer of the created mutexes list and the + number of mutexes created. */ + _tx_mutex_created_ptr = TX_NULL; + _tx_mutex_created_count = TX_EMPTY; + +#ifdef TX_MUTEX_ENABLE_PERFORMANCE_INFO + + /* Initialize the mutex performance counters. */ + _tx_mutex_performance_put_count = ((ULONG) 0); + _tx_mutex_performance_get_count = ((ULONG) 0); + _tx_mutex_performance_suspension_count = ((ULONG) 0); + _tx_mutex_performance_timeout_count = ((ULONG) 0); + _tx_mutex_performance_priority_inversion_count = ((ULONG) 0); + _tx_mutex_performance__priority_inheritance_count = ((ULONG) 0); +#endif +#endif +} + diff --git a/common_smp/src/tx_mutex_performance_info_get.c b/common_smp/src/tx_mutex_performance_info_get.c new file mode 100644 index 00000000..2ae2849d --- /dev/null +++ b/common_smp/src/tx_mutex_performance_info_get.c @@ -0,0 +1,230 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Mutex */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_mutex.h" +#ifdef TX_MUTEX_ENABLE_PERFORMANCE_INFO +#include "tx_trace.h" +#endif + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_mutex_performance_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves performance information from the specified */ +/* mutex. */ +/* */ +/* INPUT */ +/* */ +/* mutex_ptr Pointer to mutex control block */ +/* puts Destination for the number of */ +/* puts on to this mutex */ +/* gets Destination for the number of */ +/* gets on this mutex */ +/* suspensions Destination for the number of */ +/* suspensions on this mutex */ +/* timeouts Destination for number of timeouts*/ +/* on this mutex */ +/* inversions Destination for number of priority*/ +/* inversions on this mutex */ +/* inheritances Destination for number of priority*/ +/* inheritances on this mutex */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_mutex_performance_info_get(TX_MUTEX *mutex_ptr, ULONG *puts, ULONG *gets, + ULONG *suspensions, ULONG *timeouts, ULONG *inversions, ULONG *inheritances) +{ + +#ifdef TX_MUTEX_ENABLE_PERFORMANCE_INFO + +TX_INTERRUPT_SAVE_AREA +UINT status; + + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Determine if this is a legal request. */ + if (mutex_ptr == TX_NULL) + { + + /* Mutex pointer is illegal, return error. */ + status = TX_PTR_ERROR; + } + + /* Determine if the mutex ID is invalid. */ + else if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Mutex pointer is illegal, return error. */ + status = TX_PTR_ERROR; + } + else + { + + /* Disable interrupts. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_MUTEX_PERFORMANCE_INFO_GET, mutex_ptr, 0, 0, 0, TX_TRACE_MUTEX_EVENTS) + + /* Log this kernel call. */ + TX_EL_MUTEX_PERFORMANCE_INFO_GET_INSERT + + /* Retrieve all the pertinent information and return it in the supplied + destinations. */ + + /* Retrieve the number of puts on this mutex. */ + if (puts != TX_NULL) + { + + *puts = mutex_ptr -> tx_mutex_performance_put_count; + } + + /* Retrieve the number of gets on this mutex. */ + if (gets != TX_NULL) + { + + *gets = mutex_ptr -> tx_mutex_performance_get_count; + } + + /* Retrieve the number of suspensions on this mutex. */ + if (suspensions != TX_NULL) + { + + *suspensions = mutex_ptr -> tx_mutex_performance_suspension_count; + } + + /* Retrieve the number of timeouts on this mutex. */ + if (timeouts != TX_NULL) + { + + *timeouts = mutex_ptr -> tx_mutex_performance_timeout_count; + } + + /* Retrieve the number of priority inversions on this mutex. */ + if (inversions != TX_NULL) + { + + *inversions = mutex_ptr -> tx_mutex_performance_priority_inversion_count; + } + + /* Retrieve the number of priority inheritances on this mutex. */ + if (inheritances != TX_NULL) + { + + *inheritances = mutex_ptr -> tx_mutex_performance__priority_inheritance_count; + } + + /* Restore interrupts. */ + TX_RESTORE + } +#else +UINT status; + + + /* Access input arguments just for the sake of lint, MISRA, etc. */ + if (mutex_ptr != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (puts != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (gets != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (suspensions != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (timeouts != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (inversions != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (inheritances != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } +#endif + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/tx_mutex_performance_system_info_get.c b/common_smp/src/tx_mutex_performance_system_info_get.c new file mode 100644 index 00000000..df385b5e --- /dev/null +++ b/common_smp/src/tx_mutex_performance_system_info_get.c @@ -0,0 +1,205 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Mutex */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_mutex.h" +#ifdef TX_MUTEX_ENABLE_PERFORMANCE_INFO +#include "tx_trace.h" +#endif + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_mutex_performance_system_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves system mutex performance information. */ +/* */ +/* INPUT */ +/* */ +/* puts Destination for total number of */ +/* mutex puts */ +/* gets Destination for total number of */ +/* mutex gets */ +/* suspensions Destination for total number of */ +/* mutex suspensions */ +/* timeouts Destination for total number of */ +/* mutex timeouts */ +/* inversions Destination for total number of */ +/* mutex priority inversions */ +/* inheritances Destination for total number of */ +/* mutex priority inheritances */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_mutex_performance_system_info_get(ULONG *puts, ULONG *gets, ULONG *suspensions, + ULONG *timeouts, ULONG *inversions, ULONG *inheritances) +{ + +#ifdef TX_MUTEX_ENABLE_PERFORMANCE_INFO + +TX_INTERRUPT_SAVE_AREA + + + /* Disable interrupts. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_MUTEX_PERFORMANCE_SYSTEM_INFO_GET, 0, 0, 0, 0, TX_TRACE_MUTEX_EVENTS) + + /* Log this kernel call. */ + TX_EL_MUTEX_PERFORMANCE_SYSTEM_INFO_GET_INSERT + + /* Retrieve all the pertinent information and return it in the supplied + destinations. */ + + /* Retrieve the total number of mutex puts. */ + if (puts != TX_NULL) + { + + *puts = _tx_mutex_performance_put_count; + } + + /* Retrieve the total number of mutex gets. */ + if (gets != TX_NULL) + { + + *gets = _tx_mutex_performance_get_count; + } + + /* Retrieve the total number of mutex suspensions. */ + if (suspensions != TX_NULL) + { + + *suspensions = _tx_mutex_performance_suspension_count; + } + + /* Retrieve the total number of mutex timeouts. */ + if (timeouts != TX_NULL) + { + + *timeouts = _tx_mutex_performance_timeout_count; + } + + /* Retrieve the total number of mutex priority inversions. */ + if (inversions != TX_NULL) + { + + *inversions = _tx_mutex_performance_priority_inversion_count; + } + + /* Retrieve the total number of mutex priority inheritances. */ + if (inheritances != TX_NULL) + { + + *inheritances = _tx_mutex_performance__priority_inheritance_count; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return completion status. */ + return(TX_SUCCESS); + +#else + +UINT status; + + + /* Access input arguments just for the sake of lint, MISRA, etc. */ + if (puts != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (gets != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (suspensions != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (timeouts != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (inversions != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (inheritances != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + + /* Return completion status. */ + return(status); +#endif +} + diff --git a/common_smp/src/tx_mutex_prioritize.c b/common_smp/src/tx_mutex_prioritize.c new file mode 100644 index 00000000..38664b97 --- /dev/null +++ b/common_smp/src/tx_mutex_prioritize.c @@ -0,0 +1,265 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Mutex */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_thread.h" +#include "tx_mutex.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_mutex_prioritize PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function places the highest priority suspended thread at the */ +/* front of the suspension list. All other threads remain in the same */ +/* FIFO suspension order. */ +/* */ +/* INPUT */ +/* */ +/* mutex_ptr Pointer to mutex control block */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_system_preempt_check Check for preemption */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_mutex_prioritize(TX_MUTEX *mutex_ptr) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_THREAD *thread_ptr; +TX_THREAD *priority_thread_ptr; +TX_THREAD *head_ptr; +UINT suspended_count; +TX_THREAD *next_thread; +TX_THREAD *previous_thread; +UINT list_changed; +#ifdef TX_MISRA_ENABLE +UINT status; +#endif + + + /* Disable interrupts. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_MUTEX_PRIORITIZE, mutex_ptr, mutex_ptr -> tx_mutex_suspended_count, TX_POINTER_TO_ULONG_CONVERT(&suspended_count), 0, TX_TRACE_MUTEX_EVENTS) + + /* Log this kernel call. */ + TX_EL_MUTEX_PRIORITIZE_INSERT + + /* Pickup the suspended count. */ + suspended_count = mutex_ptr -> tx_mutex_suspended_count; + + /* Determine if there are fewer than 2 suspended threads. */ + if (suspended_count < ((UINT) 2)) + { + + /* Restore interrupts. */ + TX_RESTORE + } + + /* Determine if there how many threads are suspended on this mutex. */ + else if (suspended_count == ((UINT) 2)) + { + + /* Pickup the head pointer and the next pointer. */ + head_ptr = mutex_ptr -> tx_mutex_suspension_list; + next_thread = head_ptr -> tx_thread_suspended_next; + + /* Determine if the next suspended thread has a higher priority. */ + if ((next_thread -> tx_thread_priority) < (head_ptr -> tx_thread_priority)) + { + + /* Yes, move the list head to the next thread. */ + mutex_ptr -> tx_mutex_suspension_list = next_thread; + } + + /* Restore interrupts. */ + TX_RESTORE + } + else + { + + /* Remember the suspension count and head pointer. */ + head_ptr = mutex_ptr -> tx_mutex_suspension_list; + + /* Default the highest priority thread to the thread at the front of the list. */ + priority_thread_ptr = head_ptr; + + /* Setup search pointer. */ + thread_ptr = priority_thread_ptr -> tx_thread_suspended_next; + + /* Disable preemption. */ + _tx_thread_preempt_disable++; + + /* Set the list changed flag to false. */ + list_changed = TX_FALSE; + + /* Search through the list to find the highest priority thread. */ + do + { + + /* Is the current thread higher priority? */ + if (thread_ptr -> tx_thread_priority < priority_thread_ptr -> tx_thread_priority) + { + + /* Yes, remember that this thread is the highest priority. */ + priority_thread_ptr = thread_ptr; + } + + /* Restore interrupts temporarily. */ + TX_RESTORE + + /* Disable interrupts again. */ + TX_DISABLE + + /* Determine if any changes to the list have occurred while + interrupts were enabled. */ + + /* Is the list head the same? */ + if (head_ptr != mutex_ptr -> tx_mutex_suspension_list) + { + + /* The list head has changed, set the list changed flag. */ + list_changed = TX_TRUE; + } + else + { + + /* Is the suspended count the same? */ + if (suspended_count != mutex_ptr -> tx_mutex_suspended_count) + { + + /* The list head has changed, set the list changed flag. */ + list_changed = TX_TRUE; + } + } + + /* Determine if the list has changed. */ + if (list_changed == TX_FALSE) + { + + /* Move the thread pointer to the next thread. */ + thread_ptr = thread_ptr -> tx_thread_suspended_next; + } + else + { + + /* Remember the suspension count and head pointer. */ + head_ptr = mutex_ptr -> tx_mutex_suspension_list; + suspended_count = mutex_ptr -> tx_mutex_suspended_count; + + /* Default the highest priority thread to the thread at the front of the list. */ + priority_thread_ptr = head_ptr; + + /* Setup search pointer. */ + thread_ptr = priority_thread_ptr -> tx_thread_suspended_next; + + /* Reset the list changed flag. */ + list_changed = TX_FALSE; + } + + } while (thread_ptr != head_ptr); + + /* Release preemption. */ + _tx_thread_preempt_disable--; + + /* Now determine if the highest priority thread is at the front + of the list. */ + if (priority_thread_ptr != head_ptr) + { + + /* No, we need to move the highest priority suspended thread to the + front of the list. */ + + /* First, remove the highest priority thread by updating the + adjacent suspended threads. */ + next_thread = priority_thread_ptr -> tx_thread_suspended_next; + previous_thread = priority_thread_ptr -> tx_thread_suspended_previous; + next_thread -> tx_thread_suspended_previous = previous_thread; + previous_thread -> tx_thread_suspended_next = next_thread; + + /* Now, link the highest priority thread at the front of the list. */ + previous_thread = head_ptr -> tx_thread_suspended_previous; + priority_thread_ptr -> tx_thread_suspended_next = head_ptr; + priority_thread_ptr -> tx_thread_suspended_previous = previous_thread; + previous_thread -> tx_thread_suspended_next = priority_thread_ptr; + head_ptr -> tx_thread_suspended_previous = priority_thread_ptr; + + /* Move the list head pointer to the highest priority suspended thread. */ + mutex_ptr -> tx_mutex_suspension_list = priority_thread_ptr; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Check for preemption. */ + _tx_thread_system_preempt_check(); + } + +#ifdef TX_MISRA_ENABLE + + /* Initialize status to success. */ + status = TX_SUCCESS; + + /* Define extended processing option. */ + status = TX_MUTEX_PRIORITIZE_MISRA_EXTENSION(status); + + /* Return completion status. */ + return(status); +#else + + /* Return successful completion. */ + return(TX_SUCCESS); +#endif +} + diff --git a/common_smp/src/tx_mutex_priority_change.c b/common_smp/src/tx_mutex_priority_change.c new file mode 100644 index 00000000..0c5c705b --- /dev/null +++ b/common_smp/src/tx_mutex_priority_change.c @@ -0,0 +1,487 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Mutex */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_mutex.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_mutex_priority_change PORTABLE SMP */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function changes the priority of the specified thread for the */ +/* priority inheritance option of the mutex service. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread to suspend */ +/* new_priority New thread priority */ +/* new_threshold New preemption-threshold */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_smp_rebalance_execute_list */ +/* Rebalance the execution list */ +/* _tx_thread_smp_simple_priority_change */ +/* Change priority */ +/* _tx_thread_system_resume Resume thread */ +/* _tx_thread_system_ni_resume Non-interruptable resume thread */ +/* _tx_thread_system_suspend Suspend thread */ +/* _tx_thread_system_ni_suspend Non-interruptable suspend thread */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_mutex_get Inherit priority */ +/* _tx_mutex_put Restore previous priority */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_mutex_priority_change(TX_THREAD *thread_ptr, UINT new_priority) +{ + +#ifndef TX_NOT_INTERRUPTABLE + +TX_INTERRUPT_SAVE_AREA +#endif + +TX_THREAD *execute_ptr; +UINT core_index; +UINT original_priority; +UINT lowest_priority; +TX_THREAD *original_pt_thread; +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD +TX_THREAD *new_pt_thread; +UINT priority; +ULONG priority_bit; +#if TX_MAX_PRIORITIES > 32 +UINT map_index; +#endif +#endif +UINT finished; + + + /* Default finished to false. */ + finished = TX_FALSE; + +#ifndef TX_NOT_INTERRUPTABLE + + /* Lockout interrupts while the thread is being suspended. */ + TX_DISABLE +#endif + + /* Determine if there is anything to do. */ + if (thread_ptr -> tx_thread_priority == new_priority) + { + + if (thread_ptr -> tx_thread_preempt_threshold == new_priority) + { + + /* Set the finished flag to true. */ + finished = TX_TRUE; + } + } + + /* Determine if there is still more to do. */ + if (finished == TX_FALSE) + { + + /* Default the execute pointer to NULL. */ + execute_ptr = TX_NULL; + + /* Determine if this thread is currently ready. */ + if (thread_ptr -> tx_thread_state != TX_READY) + { + + /* Change thread priority to the new mutex priority-inheritance priority. */ + thread_ptr -> tx_thread_priority = new_priority; + + /* Determine how to setup the thread's preemption-threshold. */ + if (thread_ptr -> tx_thread_user_preempt_threshold < new_priority) + { + + /* Change thread preemption-threshold to the user's preemption-threshold. */ + thread_ptr -> tx_thread_preempt_threshold = thread_ptr -> tx_thread_user_preempt_threshold; + } + else + { + + /* Change the thread preemption-threshold to the new threshold. */ + thread_ptr -> tx_thread_preempt_threshold = new_priority; + } + + } + else + { + + /* Pickup the core index. */ + core_index = thread_ptr -> tx_thread_smp_core_mapped; + + /* Save the original priority. */ + original_priority = thread_ptr -> tx_thread_priority; + + /* Determine if this thread is the currently executing thread. */ + if (thread_ptr == _tx_thread_execute_ptr[core_index]) + { + + /* Yes, this thread is scheduled. */ + + /* Remember this thread as the currently executing thread. */ + execute_ptr = thread_ptr; + + /* Determine if the thread is being set to a higher-priority and it does't have + preemption-threshold set. */ + if (new_priority < thread_ptr -> tx_thread_priority) + { + + /* Check for preemption-threshold. */ + if (thread_ptr -> tx_thread_user_priority == thread_ptr -> tx_thread_user_preempt_threshold) + { + + /* Simple case, remove the thread from the current priority list and place in + the higher priority list. */ + _tx_thread_smp_simple_priority_change(thread_ptr, new_priority); + + /* Set the finished flag to true. */ + finished = TX_TRUE; + } + } + } + else + { + + /* Thread is not currently executing, so it can just be moved to the lower priority in the list. */ + + /* Determine if the thread is being set to a lower-priority and it does't have + preemption-threshold set. */ + if (new_priority > thread_ptr -> tx_thread_priority) + { + + /* Check for preemption-threshold. */ + if (thread_ptr -> tx_thread_user_priority == thread_ptr -> tx_thread_user_preempt_threshold) + { + + /* Simple case, remove the thread from the current priority list and place in + the lower priority list. */ + if (new_priority < thread_ptr -> tx_thread_user_priority) + { + + /* Use the new priority. */ + _tx_thread_smp_simple_priority_change(thread_ptr, new_priority); + } + else + { + + /* Use the user priority. */ + _tx_thread_smp_simple_priority_change(thread_ptr, thread_ptr -> tx_thread_user_priority); + } + + /* Set the finished flag to true. */ + finished = TX_TRUE; + } + } + } + + /* Now determine if we are finished. */ + if (finished == TX_FALSE) + { + + /* Save the original preemption-threshold thread. */ + original_pt_thread = _tx_thread_preemption__threshold_scheduled; + +#ifdef TX_NOT_INTERRUPTABLE + + /* Increment the preempt disable flag. */ + _tx_thread_preempt_disable++; + + /* Set the state to suspended. */ + thread_ptr -> tx_thread_state = TX_SUSPENDED; + + /* Call actual non-interruptable thread suspension routine. */ + _tx_thread_system_ni_suspend(thread_ptr, ((ULONG) 0)); + + /* At this point, the preempt disable flag is still set, so we still have + protection against all preemption. */ + + /* Determine how to setup the thread's priority. */ + if (thread_ptr -> tx_thread_user_priority < new_priority) + { + + /* Change thread priority to the user's priority. */ + thread_ptr -> tx_thread_priority = thread_ptr -> tx_thread_user_priority; + } + else + { + + /* Change thread priority to the new mutex priority-inheritance priority. */ + thread_ptr -> tx_thread_priority = new_priority; + } + + /* Determine how to setup the thread's preemption-threshold. */ + if (thread_ptr -> tx_thread_user_preempt_threshold < new_priority) + { + + /* Change thread preemption-threshold to the user's preemption-threshold. */ + thread_ptr -> tx_thread_preempt_threshold = thread_ptr -> tx_thread_user_preempt_threshold; + } + else + { + + /* Change the thread preemption-threshold to the new threshold. */ + thread_ptr -> tx_thread_preempt_threshold = new_priority; + } + + /* Resume the thread with the new priority. */ + _tx_thread_system_ni_resume(thread_ptr); + + /* Decrement the preempt disable flag. */ + _tx_thread_preempt_disable--; +#else + + /* Increment the preempt disable flag. */ + _tx_thread_preempt_disable = _tx_thread_preempt_disable + ((UINT) 2); + + /* Set the state to suspended. */ + thread_ptr -> tx_thread_state = TX_SUSPENDED; + + /* Set the suspending flag. */ + thread_ptr -> tx_thread_suspending = TX_TRUE; + + /* Setup the timeout period. */ + thread_ptr -> tx_thread_timer.tx_timer_internal_remaining_ticks = ((UINT) 0); + + /* Restore interrupts. */ + TX_RESTORE + + /* The thread is ready and must first be removed from the list. Call the + system suspend function to accomplish this. */ + _tx_thread_system_suspend(thread_ptr); + + /* Lockout interrupts again. */ + TX_DISABLE + + /* At this point, the preempt disable flag is still set, so we still have + protection against all preemption. */ + + /* Determine how to setup the thread's priority. */ + if (thread_ptr -> tx_thread_user_priority < new_priority) + { + + /* Change thread priority to the user's priority. */ + thread_ptr -> tx_thread_priority = thread_ptr -> tx_thread_user_priority; + } + else + { + + /* Change thread priority to the new mutex priority-inheritance priority. */ + thread_ptr -> tx_thread_priority = new_priority; + } + + /* Determine how to setup the thread's preemption-threshold. */ + if (thread_ptr -> tx_thread_user_preempt_threshold < new_priority) + { + + /* Change thread preemption-threshold to the user's preemption-threshold. */ + thread_ptr -> tx_thread_preempt_threshold = thread_ptr -> tx_thread_user_preempt_threshold; + } + else + { + + /* Change the thread preemption-threshold to the new threshold. */ + thread_ptr -> tx_thread_preempt_threshold = new_priority; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Resume the thread with the new priority. */ + _tx_thread_system_resume(thread_ptr); +#endif + + /* Optional processing extension. */ + TX_MUTEX_PRIORITY_CHANGE_EXTENSION + +#ifndef TX_NOT_INTERRUPTABLE + + /* Disable interrupts. */ + TX_DISABLE +#endif + + /* Determine if the thread was previously executing. */ + if (thread_ptr == execute_ptr) + { + +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD + /* Determine if preemption-threshold is in force at the new priority level. */ + if (_tx_thread_preemption_threshold_list[thread_ptr -> tx_thread_priority] == TX_NULL) + { + + /* Ensure that this thread is placed at the front of the priority list. */ + _tx_thread_priority_list[thread_ptr -> tx_thread_priority] = thread_ptr; + } +#else + + /* Ensure that this thread is placed at the front of the priority list. */ + _tx_thread_priority_list[thread_ptr -> tx_thread_priority] = thread_ptr; +#endif + } + + /* Pickup the core index. */ + core_index = thread_ptr -> tx_thread_smp_core_mapped; + +#ifndef TX_THREAD_SMP_DYNAMIC_CORE_MAX + + /* Pickup the next thread to execute. */ + if (core_index < ((UINT) TX_THREAD_SMP_MAX_CORES)) +#else + + /* Pickup the next thread to execute. */ + if (core_index < _tx_thread_smp_max_cores) +#endif + { + + /* Determine if this thread is not the next thread to execute. */ + if (thread_ptr != _tx_thread_execute_ptr[core_index]) + { + + /* Now determine if this thread was previously executing thread. */ + if (thread_ptr == execute_ptr) + { + + /* Determine if we moved to a lower priority. If so, move the thread to the front of the priority list. */ + if (original_priority < new_priority) + { + + /* Make sure the thread is still ready. */ + if (thread_ptr -> tx_thread_state == TX_READY) + { + + /* Determine the lowest priority scheduled thread. */ + lowest_priority = _tx_thread_smp_lowest_priority_get(); + + /* Determine if this thread has a higher or same priority as the lowest priority + in the list. */ + if (thread_ptr -> tx_thread_priority <= lowest_priority) + { + + /* Yes, we need to rebalance to make it possible for this thread to execute. */ + + /* Determine if the thread with preemption-threshold thread has changed... and is + not the scheduled thread. */ + if ((original_pt_thread != _tx_thread_preemption__threshold_scheduled) && + (original_pt_thread != thread_ptr)) + { + + /* Yes, preemption-threshold has changed. Determine if it can or should + be reversed. */ + +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD + + /* Pickup the preemption-threshold thread. */ + new_pt_thread = _tx_thread_preemption__threshold_scheduled; +#endif + + /* Restore the original preemption-threshold thread. */ + _tx_thread_preemption__threshold_scheduled = original_pt_thread; + + +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD + + /* Determine if there is a new preemption-threshold thread to reverse. */ + if (new_pt_thread != TX_NULL) + { + + /* Clear the information associated with the new preemption-threshold thread. */ + + /* Pickup the priority. */ + priority = new_pt_thread -> tx_thread_priority; + + /* Clear the preempted list entry. */ + _tx_thread_preemption_threshold_list[priority] = TX_NULL; + +#if TX_MAX_PRIORITIES > 32 + /* Calculate the bit map array index. */ + map_index = new_priority/((UINT) 32); +#endif + /* Ensure that this thread's priority is clear in the preempt map. */ + TX_MOD32_BIT_SET(priority, priority_bit) + _tx_thread_preempted_maps[MAP_INDEX] = _tx_thread_preempted_maps[MAP_INDEX] & (~(priority_bit)); +#if TX_MAX_PRIORITIES > 32 + + /* Determine if there are any other bits set in this preempt map. */ + if (_tx_thread_preempted_maps[MAP_INDEX] == ((ULONG) 0)) + { + + /* No, clear the active bit to signify this preempted map has nothing set. */ + TX_DIV32_BIT_SET(priority, priority_bit) + _tx_thread_preempted_map_active = _tx_thread_preempted_map_active & (~(priority_bit)); + } +#endif + } +#endif + } + + /* Pickup the index. */ + core_index = TX_SMP_CORE_ID; + + /* Call the rebalance routine. This routine maps cores and ready threads. */ + _tx_thread_smp_rebalance_execute_list(core_index); + } + } + } + } + } + } + } + } + } + +#ifndef TX_NOT_INTERRUPTABLE + + /* Restore interrupts. */ + TX_RESTORE +#endif +} + diff --git a/common_smp/src/tx_mutex_put.c b/common_smp/src/tx_mutex_put.c new file mode 100644 index 00000000..45cb1c4b --- /dev/null +++ b/common_smp/src/tx_mutex_put.c @@ -0,0 +1,654 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Mutex */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_thread.h" +#include "tx_mutex.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_mutex_put PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function puts back an instance of the specified mutex. */ +/* */ +/* INPUT */ +/* */ +/* mutex_ptr Pointer to mutex control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SUCCESS Success completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_system_preempt_check Check for preemption */ +/* _tx_thread_system_resume Resume thread service */ +/* _tx_thread_system_ni_resume Non-interruptable resume thread */ +/* _tx_mutex_priority_change Restore previous thread priority */ +/* _tx_mutex_prioritize Prioritize the mutex suspension */ +/* _tx_mutex_thread_release Release all thread's mutexes */ +/* _tx_mutex_delete Release ownership upon mutex */ +/* deletion */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_mutex_put(TX_MUTEX *mutex_ptr) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_THREAD *thread_ptr; +TX_THREAD *old_owner; +UINT old_priority; +UINT status; +TX_MUTEX *next_mutex; +TX_MUTEX *previous_mutex; +UINT owned_count; +UINT suspended_count; +TX_THREAD *current_thread; +TX_THREAD *next_thread; +TX_THREAD *previous_thread; +TX_THREAD *suspended_thread; +UINT inheritance_priority; + + + /* Setup status to indicate the processing is not complete. */ + status = TX_NOT_DONE; + + /* Disable interrupts to put an instance back to the mutex. */ + TX_DISABLE + +#ifdef TX_MUTEX_ENABLE_PERFORMANCE_INFO + + /* Increment the total mutex put counter. */ + _tx_mutex_performance_put_count++; + + /* Increment the number of attempts to put this mutex. */ + mutex_ptr -> tx_mutex_performance_put_count++; +#endif + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_MUTEX_PUT, mutex_ptr, TX_POINTER_TO_ULONG_CONVERT(mutex_ptr -> tx_mutex_owner), mutex_ptr -> tx_mutex_ownership_count, TX_POINTER_TO_ULONG_CONVERT(&old_priority), TX_TRACE_MUTEX_EVENTS) + + /* Log this kernel call. */ + TX_EL_MUTEX_PUT_INSERT + + /* Determine if this mutex is owned. */ + if (mutex_ptr -> tx_mutex_ownership_count != ((UINT) 0)) + { + + /* Pickup the owning thread pointer. */ + thread_ptr = mutex_ptr -> tx_mutex_owner; + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(current_thread) + + /* Check to see if the mutex is owned by the calling thread. */ + if (mutex_ptr -> tx_mutex_owner != current_thread) + { + + /* Determine if the preempt disable flag is set, indicating that + the caller is not the application but from ThreadX. In such + cases, the thread mutex owner does not need to match. */ + if (_tx_thread_preempt_disable == ((UINT) 0)) + { + + /* Invalid mutex release. */ + + /* Restore interrupts. */ + TX_RESTORE + + /* Caller does not own the mutex. */ + status = TX_NOT_OWNED; + } + } + + /* Determine if we should continue. */ + if (status == TX_NOT_DONE) + { + + /* Decrement the mutex ownership count. */ + mutex_ptr -> tx_mutex_ownership_count--; + + /* Determine if the mutex is still owned by the current thread. */ + if (mutex_ptr -> tx_mutex_ownership_count != ((UINT) 0)) + { + + /* Restore interrupts. */ + TX_RESTORE + + /* Mutex is still owned, just return successful status. */ + status = TX_SUCCESS; + } + else + { + + /* Check for a NULL thread pointer, which can only happen during initialization. */ + if (thread_ptr == TX_NULL) + { + + /* Restore interrupts. */ + TX_RESTORE + + /* Mutex is now available, return successful status. */ + status = TX_SUCCESS; + } + else + { + + /* The mutex is now available. */ + + /* Remove this mutex from the owned mutex list. */ + + /* Decrement the ownership count. */ + thread_ptr -> tx_thread_owned_mutex_count--; + + /* Determine if this mutex was the only one on the list. */ + if (thread_ptr -> tx_thread_owned_mutex_count == ((UINT) 0)) + { + + /* Yes, the list is empty. Simply set the head pointer to NULL. */ + thread_ptr -> tx_thread_owned_mutex_list = TX_NULL; + } + else + { + + /* No, there are more mutexes on the list. */ + + /* Link-up the neighbors. */ + next_mutex = mutex_ptr -> tx_mutex_owned_next; + previous_mutex = mutex_ptr -> tx_mutex_owned_previous; + next_mutex -> tx_mutex_owned_previous = previous_mutex; + previous_mutex -> tx_mutex_owned_next = next_mutex; + + /* See if we have to update the created list head pointer. */ + if (thread_ptr -> tx_thread_owned_mutex_list == mutex_ptr) + { + + /* Yes, move the head pointer to the next link. */ + thread_ptr -> tx_thread_owned_mutex_list = next_mutex; + } + } + + /* Determine if the simple, non-suspension, non-priority inheritance case is present. */ + if (mutex_ptr -> tx_mutex_suspension_list == TX_NULL) + { + + /* Is this a priority inheritance mutex? */ + if (mutex_ptr -> tx_mutex_inherit == TX_FALSE) + { + + /* Yes, we are done - set the mutex owner to NULL. */ + mutex_ptr -> tx_mutex_owner = TX_NULL; + + /* Restore interrupts. */ + TX_RESTORE + + /* Mutex is now available, return successful status. */ + status = TX_SUCCESS; + } + } + + /* Determine if the processing is complete. */ + if (status == TX_NOT_DONE) + { + + /* Initialize original owner and thread priority. */ + old_owner = TX_NULL; + old_priority = thread_ptr -> tx_thread_user_priority; + + /* Does this mutex support priority inheritance? */ + if (mutex_ptr -> tx_mutex_inherit == TX_TRUE) + { + +#ifndef TX_NOT_INTERRUPTABLE + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE +#endif + + /* Default the inheritance priority to disabled. */ + inheritance_priority = ((UINT) TX_MAX_PRIORITIES); + + /* Search the owned mutexes for this thread to determine the highest priority for this + former mutex owner to return to. */ + next_mutex = thread_ptr -> tx_thread_owned_mutex_list; + while (next_mutex != TX_NULL) + { + + /* Does this mutex support priority inheritance? */ + if (next_mutex -> tx_mutex_inherit == TX_TRUE) + { + + /* Determine if highest priority field of the mutex is higher than the priority to + restore. */ + if (next_mutex -> tx_mutex_highest_priority_waiting < inheritance_priority) + { + + /* Use this priority to return releasing thread to. */ + inheritance_priority = next_mutex -> tx_mutex_highest_priority_waiting; + } + } + + /* Move mutex pointer to the next mutex in the list. */ + next_mutex = next_mutex -> tx_mutex_owned_next; + + /* Are we at the end of the list? */ + if (next_mutex == thread_ptr -> tx_thread_owned_mutex_list) + { + + /* Yes, set the next mutex to NULL. */ + next_mutex = TX_NULL; + } + } + +#ifndef TX_NOT_INTERRUPTABLE + + /* Disable interrupts. */ + TX_DISABLE + + /* Undo the temporarily preemption disable. */ + _tx_thread_preempt_disable--; +#endif + + /* Set the inherit priority to that of the highest priority thread waiting on the mutex. */ + thread_ptr -> tx_thread_inherit_priority = inheritance_priority; + + /* Determine if the inheritance priority is less than the default old priority. */ + if (inheritance_priority < old_priority) + { + + /* Yes, update the old priority. */ + old_priority = inheritance_priority; + } + } + + /* Determine if priority inheritance is in effect and there are one or more + threads suspended on the mutex. */ + if (mutex_ptr -> tx_mutex_suspended_count > ((UINT) 1)) + { + + /* Is priority inheritance in effect? */ + if (mutex_ptr -> tx_mutex_inherit == TX_TRUE) + { + + /* Yes, this code is simply to ensure the highest priority thread is positioned + at the front of the suspension list. */ + +#ifndef TX_NOT_INTERRUPTABLE + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE +#endif + + /* Call the mutex prioritize processing to ensure the + highest priority thread is resumed. */ +#ifdef TX_MISRA_ENABLE + do + { + status = _tx_mutex_prioritize(mutex_ptr); + } while (status != TX_SUCCESS); +#else + _tx_mutex_prioritize(mutex_ptr); +#endif + + /* At this point, the highest priority thread is at the + front of the suspension list. */ + + /* Optional processing extension. */ + TX_MUTEX_PUT_EXTENSION_1 + +#ifndef TX_NOT_INTERRUPTABLE + + /* Disable interrupts. */ + TX_DISABLE + + /* Back off the preemption disable. */ + _tx_thread_preempt_disable--; +#endif + } + } + + /* Now determine if there are any threads still waiting on the mutex. */ + if (mutex_ptr -> tx_mutex_suspension_list == TX_NULL) + { + + /* No, there are no longer any threads waiting on the mutex. */ + +#ifndef TX_NOT_INTERRUPTABLE + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE +#endif + + /* Mutex is not owned, but it is possible that a thread that + caused a priority inheritance to occur is no longer waiting + on the mutex. */ + + /* Setup the highest priority waiting thread. */ + mutex_ptr -> tx_mutex_highest_priority_waiting = (UINT) TX_MAX_PRIORITIES; + + /* Determine if we need to restore priority. */ + if ((mutex_ptr -> tx_mutex_owner) -> tx_thread_priority != old_priority) + { + + /* Yes, restore the priority of thread. */ + _tx_mutex_priority_change(mutex_ptr -> tx_mutex_owner, old_priority); + } + +#ifndef TX_NOT_INTERRUPTABLE + + /* Disable interrupts again. */ + TX_DISABLE + + /* Back off the preemption disable. */ + _tx_thread_preempt_disable--; +#endif + + /* Set the mutex owner to NULL. */ + mutex_ptr -> tx_mutex_owner = TX_NULL; + + /* Restore interrupts. */ + TX_RESTORE + + /* Check for preemption. */ + _tx_thread_system_preempt_check(); + + /* Set status to success. */ + status = TX_SUCCESS; + } + else + { + + /* Pickup the thread at the front of the suspension list. */ + thread_ptr = mutex_ptr -> tx_mutex_suspension_list; + + /* Save the previous ownership information, if inheritance is + in effect. */ + if (mutex_ptr -> tx_mutex_inherit == TX_TRUE) + { + + /* Remember the old mutex owner. */ + old_owner = mutex_ptr -> tx_mutex_owner; + + /* Setup owner thread priority information. */ + mutex_ptr -> tx_mutex_original_priority = thread_ptr -> tx_thread_priority; + + /* Setup the highest priority waiting thread. */ + mutex_ptr -> tx_mutex_highest_priority_waiting = (UINT) TX_MAX_PRIORITIES; + } + + /* Determine how many mutexes are owned by this thread. */ + owned_count = thread_ptr -> tx_thread_owned_mutex_count; + + /* Determine if this thread owns any other mutexes that have priority inheritance. */ + if (owned_count == ((UINT) 0)) + { + + /* The owned mutex list is empty. Add mutex to empty list. */ + thread_ptr -> tx_thread_owned_mutex_list = mutex_ptr; + mutex_ptr -> tx_mutex_owned_next = mutex_ptr; + mutex_ptr -> tx_mutex_owned_previous = mutex_ptr; + } + else + { + + /* Non-empty list. Link up the mutex. */ + + /* Pickup tail pointer. */ + next_mutex = thread_ptr -> tx_thread_owned_mutex_list; + previous_mutex = next_mutex -> tx_mutex_owned_previous; + + /* Place the owned mutex in the list. */ + next_mutex -> tx_mutex_owned_previous = mutex_ptr; + previous_mutex -> tx_mutex_owned_next = mutex_ptr; + + /* Setup this mutex's next and previous created links. */ + mutex_ptr -> tx_mutex_owned_previous = previous_mutex; + mutex_ptr -> tx_mutex_owned_next = next_mutex; + } + + /* Increment the number of mutexes owned counter. */ + thread_ptr -> tx_thread_owned_mutex_count = owned_count + ((UINT) 1); + + /* Mark the Mutex as owned and fill in the corresponding information. */ + mutex_ptr -> tx_mutex_ownership_count = (UINT) 1; + mutex_ptr -> tx_mutex_owner = thread_ptr; + + /* Remove the suspended thread from the list. */ + + /* Decrement the suspension count. */ + mutex_ptr -> tx_mutex_suspended_count--; + + /* Pickup the suspended count. */ + suspended_count = mutex_ptr -> tx_mutex_suspended_count; + + /* See if this is the only suspended thread on the list. */ + if (suspended_count == TX_NO_SUSPENSIONS) + { + + /* Yes, the only suspended thread. */ + + /* Update the head pointer. */ + mutex_ptr -> tx_mutex_suspension_list = TX_NULL; + } + else + { + + /* At least one more thread is on the same expiration list. */ + + /* Update the list head pointer. */ + next_thread = thread_ptr -> tx_thread_suspended_next; + mutex_ptr -> tx_mutex_suspension_list = next_thread; + + /* Update the links of the adjacent threads. */ + previous_thread = thread_ptr -> tx_thread_suspended_previous; + next_thread -> tx_thread_suspended_previous = previous_thread; + previous_thread -> tx_thread_suspended_next = next_thread; + } + + /* Prepare for resumption of the first thread. */ + + /* Clear cleanup routine to avoid timeout. */ + thread_ptr -> tx_thread_suspend_cleanup = TX_NULL; + + /* Put return status into the thread control block. */ + thread_ptr -> tx_thread_suspend_status = TX_SUCCESS; + +#ifdef TX_NOT_INTERRUPTABLE + + /* Determine if priority inheritance is enabled for this mutex. */ + if (mutex_ptr -> tx_mutex_inherit == TX_TRUE) + { + + /* Yes, priority inheritance is requested. */ + + /* Determine if there are any more threads still suspended on the mutex. */ + if (mutex_ptr -> tx_mutex_suspended_count != ((ULONG) 0)) + { + + /* Determine if there are more than one thread suspended on the mutex. */ + if (mutex_ptr -> tx_mutex_suspended_count > ((ULONG) 1)) + { + + /* If so, prioritize the list so the highest priority thread is placed at the + front of the suspension list. */ +#ifdef TX_MISRA_ENABLE + do + { + status = _tx_mutex_prioritize(mutex_ptr); + } while (status != TX_SUCCESS); +#else + _tx_mutex_prioritize(mutex_ptr); +#endif + } + + /* Now, pickup the list head and set the priority. */ + + /* Determine if there still are threads suspended for this mutex. */ + suspended_thread = mutex_ptr -> tx_mutex_suspension_list; + if (suspended_thread != TX_NULL) + { + + /* Setup the highest priority thread waiting on this mutex. */ + mutex_ptr -> tx_mutex_highest_priority_waiting = suspended_thread -> tx_thread_priority; + } + } + + /* Restore previous priority needs to be restored after priority + inheritance. */ + + /* Determine if we need to restore priority. */ + if (old_owner -> tx_thread_priority != old_priority) + { + + /* Restore priority of thread. */ + _tx_mutex_priority_change(old_owner, old_priority); + } + } + + /* Resume the thread! */ + _tx_thread_system_ni_resume(thread_ptr); + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Determine if priority inheritance is enabled for this mutex. */ + if (mutex_ptr -> tx_mutex_inherit == TX_TRUE) + { + + /* Yes, priority inheritance is requested. */ + + /* Determine if there are any more threads still suspended on the mutex. */ + if (mutex_ptr -> tx_mutex_suspended_count != TX_NO_SUSPENSIONS) + { + + /* Prioritize the list so the highest priority thread is placed at the + front of the suspension list. */ +#ifdef TX_MISRA_ENABLE + do + { + status = _tx_mutex_prioritize(mutex_ptr); + } while (status != TX_SUCCESS); +#else + _tx_mutex_prioritize(mutex_ptr); +#endif + + /* Now, pickup the list head and set the priority. */ + + /* Optional processing extension. */ + TX_MUTEX_PUT_EXTENSION_2 + + /* Disable interrupts. */ + TX_DISABLE + + /* Determine if there still are threads suspended for this mutex. */ + suspended_thread = mutex_ptr -> tx_mutex_suspension_list; + if (suspended_thread != TX_NULL) + { + + /* Setup the highest priority thread waiting on this mutex. */ + mutex_ptr -> tx_mutex_highest_priority_waiting = suspended_thread -> tx_thread_priority; + } + + /* Restore interrupts. */ + TX_RESTORE + } + + /* Restore previous priority needs to be restored after priority + inheritance. */ + + /* Is the priority different? */ + if (old_owner -> tx_thread_priority != old_priority) + { + + /* Restore the priority of thread. */ + _tx_mutex_priority_change(old_owner, old_priority); + } + } + + /* Resume thread. */ + _tx_thread_system_resume(thread_ptr); +#endif + + /* Return a successful status. */ + status = TX_SUCCESS; + } + } + } + } + } + } + else + { + + /* Restore interrupts. */ + TX_RESTORE + + /* Caller does not own the mutex. */ + status = TX_NOT_OWNED; + } + + /* Return the completion status. */ + return(status); +} + diff --git a/common_smp/src/tx_queue_cleanup.c b/common_smp/src/tx_queue_cleanup.c new file mode 100644 index 00000000..43dc3341 --- /dev/null +++ b/common_smp/src/tx_queue_cleanup.c @@ -0,0 +1,225 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Queue */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_queue.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_queue_cleanup PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes queue timeout and thread terminate */ +/* actions that require the queue data structures to be cleaned */ +/* up. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to suspended thread's */ +/* control block */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_system_resume Resume thread service */ +/* _tx_thread_system_ni_resume Non-interruptable resume thread */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_timeout Thread timeout processing */ +/* _tx_thread_terminate Thread terminate processing */ +/* _tx_thread_wait_abort Thread wait abort processing */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_queue_cleanup(TX_THREAD *thread_ptr, ULONG suspension_sequence) +{ + +#ifndef TX_NOT_INTERRUPTABLE +TX_INTERRUPT_SAVE_AREA +#endif + +TX_QUEUE *queue_ptr; +UINT suspended_count; +TX_THREAD *next_thread; +TX_THREAD *previous_thread; + + +#ifndef TX_NOT_INTERRUPTABLE + + /* Disable interrupts to remove the suspended thread from the queue. */ + TX_DISABLE + + /* Determine if the cleanup is still required. */ + if (thread_ptr -> tx_thread_suspend_cleanup == &(_tx_queue_cleanup)) + { + + /* Check for valid suspension sequence. */ + if (suspension_sequence == thread_ptr -> tx_thread_suspension_sequence) + { + + /* Setup pointer to queue control block. */ + queue_ptr = TX_VOID_TO_QUEUE_POINTER_CONVERT(thread_ptr -> tx_thread_suspend_control_block); + + /* Check for NULL queue pointer. */ + if (queue_ptr != TX_NULL) + { + + /* Is the queue ID valid? */ + if (queue_ptr -> tx_queue_id == TX_QUEUE_ID) + { + + /* Determine if there are any thread suspensions. */ + if (queue_ptr -> tx_queue_suspended_count != TX_NO_SUSPENSIONS) + { +#else + + /* Setup pointer to queue control block. */ + queue_ptr = TX_VOID_TO_QUEUE_POINTER_CONVERT(thread_ptr -> tx_thread_suspend_control_block); +#endif + + /* Yes, we still have thread suspension! */ + + /* Clear the suspension cleanup flag. */ + thread_ptr -> tx_thread_suspend_cleanup = TX_NULL; + + /* Decrement the suspended count. */ + queue_ptr -> tx_queue_suspended_count--; + + /* Pickup the suspended count. */ + suspended_count = queue_ptr -> tx_queue_suspended_count; + + /* Remove the suspended thread from the list. */ + + /* See if this is the only suspended thread on the list. */ + if (suspended_count == TX_NO_SUSPENSIONS) + { + + /* Yes, the only suspended thread. */ + + /* Update the head pointer. */ + queue_ptr -> tx_queue_suspension_list = TX_NULL; + } + else + { + + /* At least one more thread is on the same suspension list. */ + + /* Update the links of the adjacent threads. */ + next_thread = thread_ptr -> tx_thread_suspended_next; + previous_thread = thread_ptr -> tx_thread_suspended_previous; + next_thread -> tx_thread_suspended_previous = previous_thread; + previous_thread -> tx_thread_suspended_next = next_thread; + + /* Determine if we need to update the head pointer. */ + if (queue_ptr -> tx_queue_suspension_list == thread_ptr) + { + + /* Update the list head pointer. */ + queue_ptr -> tx_queue_suspension_list = next_thread; + } + } + + /* Now we need to determine if this cleanup is from a terminate, timeout, + or from a wait abort. */ + if (thread_ptr -> tx_thread_state == TX_QUEUE_SUSP) + { + + /* Timeout condition and the thread still suspended on the queue. + Setup return error status and resume the thread. */ + +#ifdef TX_QUEUE_ENABLE_PERFORMANCE_INFO + + /* Increment the total timeouts counter. */ + _tx_queue_performance_timeout_count++; + + /* Increment the number of timeouts on this queue. */ + queue_ptr -> tx_queue_performance_timeout_count++; +#endif + + /* Setup return status. */ + if (queue_ptr -> tx_queue_enqueued != TX_NO_MESSAGES) + { + + /* Queue full timeout! */ + thread_ptr -> tx_thread_suspend_status = TX_QUEUE_FULL; + } + else + { + + /* Queue empty timeout! */ + thread_ptr -> tx_thread_suspend_status = TX_QUEUE_EMPTY; + } + +#ifdef TX_NOT_INTERRUPTABLE + + /* Resume the thread! */ + _tx_thread_system_ni_resume(thread_ptr); +#else + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Resume the thread! */ + _tx_thread_system_resume(thread_ptr); + + /* Disable interrupts. */ + TX_DISABLE +#endif + } +#ifndef TX_NOT_INTERRUPTABLE + } + } + } + } + } + + /* Restore interrupts. */ + TX_RESTORE +#endif +} + diff --git a/common_smp/src/tx_queue_create.c b/common_smp/src/tx_queue_create.c new file mode 100644 index 00000000..698d4548 --- /dev/null +++ b/common_smp/src/tx_queue_create.c @@ -0,0 +1,170 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Queue */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_queue.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_queue_create PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates a message queue. The message size and depth */ +/* of the queue is specified by the caller. */ +/* */ +/* INPUT */ +/* */ +/* queue_ptr Pointer to queue control block */ +/* name_ptr Pointer to queue name */ +/* message_size Size of each queue message */ +/* queue_start Starting address of the queue area*/ +/* queue_size Number of bytes in the queue */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SUCCESS Successful completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_queue_create(TX_QUEUE *queue_ptr, CHAR *name_ptr, UINT message_size, + VOID *queue_start, ULONG queue_size) +{ + +TX_INTERRUPT_SAVE_AREA + +UINT capacity; +UINT used_words; +TX_QUEUE *next_queue; +TX_QUEUE *previous_queue; + + + /* Initialize queue control block to all zeros. */ + TX_MEMSET(queue_ptr, 0, (sizeof(TX_QUEUE))); + + /* Setup the basic queue fields. */ + queue_ptr -> tx_queue_name = name_ptr; + + /* Save the message size in the control block. */ + queue_ptr -> tx_queue_message_size = message_size; + + /* Determine how many messages will fit in the queue area and the number + of ULONGs used. */ + capacity = (UINT) (queue_size / ((ULONG) (((ULONG) message_size) * (sizeof(ULONG))))); + used_words = capacity * message_size; + + /* Save the starting address and calculate the ending address of + the queue. Note that the ending address is really one past the + end! */ + queue_ptr -> tx_queue_start = TX_VOID_TO_ULONG_POINTER_CONVERT(queue_start); + queue_ptr -> tx_queue_end = TX_ULONG_POINTER_ADD(queue_ptr -> tx_queue_start, used_words); + + /* Set the read and write pointers to the beginning of the queue + area. */ + queue_ptr -> tx_queue_read = TX_VOID_TO_ULONG_POINTER_CONVERT(queue_start); + queue_ptr -> tx_queue_write = TX_VOID_TO_ULONG_POINTER_CONVERT(queue_start); + + /* Setup the number of enqueued messages and the number of message + slots available in the queue. */ + queue_ptr -> tx_queue_available_storage = (UINT) capacity; + queue_ptr -> tx_queue_capacity = (UINT) capacity; + + /* Disable interrupts to put the queue on the created list. */ + TX_DISABLE + + /* Setup the queue ID to make it valid. */ + queue_ptr -> tx_queue_id = TX_QUEUE_ID; + + /* Place the queue on the list of created queues. First, + check for an empty list. */ + if (_tx_queue_created_count == TX_EMPTY) + { + + /* The created queue list is empty. Add queue to empty list. */ + _tx_queue_created_ptr = queue_ptr; + queue_ptr -> tx_queue_created_next = queue_ptr; + queue_ptr -> tx_queue_created_previous = queue_ptr; + } + else + { + + /* This list is not NULL, add to the end of the list. */ + next_queue = _tx_queue_created_ptr; + previous_queue = next_queue -> tx_queue_created_previous; + + /* Place the new queue in the list. */ + next_queue -> tx_queue_created_previous = queue_ptr; + previous_queue -> tx_queue_created_next = queue_ptr; + + /* Setup this queues's created links. */ + queue_ptr -> tx_queue_created_previous = previous_queue; + queue_ptr -> tx_queue_created_next = next_queue; + } + + /* Increment the created queue count. */ + _tx_queue_created_count++; + + /* Optional queue create extended processing. */ + TX_QUEUE_CREATE_EXTENSION(queue_ptr) + + /* If trace is enabled, register this object. */ + TX_TRACE_OBJECT_REGISTER(TX_TRACE_OBJECT_TYPE_QUEUE, queue_ptr, name_ptr, queue_size, message_size) + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_QUEUE_CREATE, queue_ptr, message_size, TX_POINTER_TO_ULONG_CONVERT(queue_start), queue_size, TX_TRACE_QUEUE_EVENTS) + + /* Log this kernel call. */ + TX_EL_QUEUE_CREATE_INSERT + + /* Restore interrupts. */ + TX_RESTORE + + /* Return TX_SUCCESS. */ + return(TX_SUCCESS); +} + diff --git a/common_smp/src/tx_queue_delete.c b/common_smp/src/tx_queue_delete.c new file mode 100644 index 00000000..067e7655 --- /dev/null +++ b/common_smp/src/tx_queue_delete.c @@ -0,0 +1,206 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Queue */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_thread.h" +#include "tx_queue.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_queue_delete PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function deletes the specified queue. All threads suspended */ +/* on the queue are resumed with the TX_DELETED status code. */ +/* */ +/* INPUT */ +/* */ +/* queue_ptr Pointer to queue control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SUCCESS Successful completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_system_preempt_check Check for preemption */ +/* _tx_thread_system_resume Resume thread service */ +/* _tx_thread_system_ni_resume Non-interruptable resume thread */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_queue_delete(TX_QUEUE *queue_ptr) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_THREAD *thread_ptr; +TX_THREAD *next_thread; +UINT suspended_count; +TX_QUEUE *next_queue; +TX_QUEUE *previous_queue; + + + /* Disable interrupts to remove the queue from the created list. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_QUEUE_DELETE, queue_ptr, TX_POINTER_TO_ULONG_CONVERT(&thread_ptr), 0, 0, TX_TRACE_QUEUE_EVENTS) + + /* Optional queue delete extended processing. */ + TX_QUEUE_DELETE_EXTENSION(queue_ptr) + + /* If trace is enabled, unregister this object. */ + TX_TRACE_OBJECT_UNREGISTER(queue_ptr) + + /* Log this kernel call. */ + TX_EL_QUEUE_DELETE_INSERT + + /* Clear the queue ID to make it invalid. */ + queue_ptr -> tx_queue_id = TX_CLEAR_ID; + + /* Decrement the number of created queues. */ + _tx_queue_created_count--; + + /* See if the queue is the only one on the list. */ + if (_tx_queue_created_count == TX_EMPTY) + { + + /* Only created queue, just set the created list to NULL. */ + _tx_queue_created_ptr = TX_NULL; + } + else + { + + /* Link-up the neighbors. */ + next_queue = queue_ptr -> tx_queue_created_next; + previous_queue = queue_ptr -> tx_queue_created_previous; + next_queue -> tx_queue_created_previous = previous_queue; + previous_queue -> tx_queue_created_next = next_queue; + + /* See if we have to update the created list head pointer. */ + if (_tx_queue_created_ptr == queue_ptr) + { + + /* Yes, move the head pointer to the next link. */ + _tx_queue_created_ptr = next_queue; + } + } + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Pickup the suspension information. */ + thread_ptr = queue_ptr -> tx_queue_suspension_list; + queue_ptr -> tx_queue_suspension_list = TX_NULL; + suspended_count = queue_ptr -> tx_queue_suspended_count; + queue_ptr -> tx_queue_suspended_count = TX_NO_SUSPENSIONS; + + /* Restore interrupts. */ + TX_RESTORE + + /* Walk through the queue list to resume any and all threads suspended + on this queue. */ + while (suspended_count != TX_NO_SUSPENSIONS) + { + + /* Decrement the suspension count. */ + suspended_count--; + + /* Lockout interrupts. */ + TX_DISABLE + + /* Clear the cleanup pointer, this prevents the timeout from doing + anything. */ + thread_ptr -> tx_thread_suspend_cleanup = TX_NULL; + + /* Set the return status in the thread to TX_DELETED. */ + thread_ptr -> tx_thread_suspend_status = TX_DELETED; + + /* Move the thread pointer ahead. */ + next_thread = thread_ptr -> tx_thread_suspended_next; + +#ifdef TX_NOT_INTERRUPTABLE + + /* Resume the thread! */ + _tx_thread_system_ni_resume(thread_ptr); + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Temporarily disable preemption again. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Resume the thread. */ + _tx_thread_system_resume(thread_ptr); +#endif + + /* Move to next thread. */ + thread_ptr = next_thread; + } + + /* Execute Port-Specific completion processing. If needed, it is typically defined in tx_port.h. */ + TX_QUEUE_DELETE_PORT_COMPLETION(queue_ptr) + + /* Disable interrupts. */ + TX_DISABLE + + /* Release previous preempt disable. */ + _tx_thread_preempt_disable--; + + /* Restore interrupts. */ + TX_RESTORE + + /* Check for preemption. */ + _tx_thread_system_preempt_check(); + + /* Return TX_SUCCESS. */ + return(TX_SUCCESS); +} + diff --git a/common_smp/src/tx_queue_flush.c b/common_smp/src/tx_queue_flush.c new file mode 100644 index 00000000..cd0acf12 --- /dev/null +++ b/common_smp/src/tx_queue_flush.c @@ -0,0 +1,205 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Queue */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_thread.h" +#include "tx_queue.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_queue_flush PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function resets the specified queue, if there are any messages */ +/* in it. Messages waiting to be placed on the queue are also thrown */ +/* out. */ +/* */ +/* INPUT */ +/* */ +/* queue_ptr Pointer to queue control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SUCCESS Successful completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_system_preempt_check Check for preemption */ +/* _tx_thread_system_resume Resume thread service */ +/* _tx_thread_system_ni_resume Non-interruptable resume thread */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_queue_flush(TX_QUEUE *queue_ptr) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_THREAD *suspension_list; +UINT suspended_count; +TX_THREAD *thread_ptr; + + + /* Initialize the suspended count and list. */ + suspended_count = TX_NO_SUSPENSIONS; + suspension_list = TX_NULL; + + /* Disable interrupts to reset various queue parameters. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_QUEUE_FLUSH, queue_ptr, TX_POINTER_TO_ULONG_CONVERT(&thread_ptr), 0, 0, TX_TRACE_QUEUE_EVENTS) + + /* Log this kernel call. */ + TX_EL_QUEUE_FLUSH_INSERT + + /* Determine if there is something on the queue. */ + if (queue_ptr -> tx_queue_enqueued != TX_NO_MESSAGES) + { + + /* Yes, there is something in the queue. */ + + /* Reset the queue parameters to erase all of the queued messages. */ + queue_ptr -> tx_queue_enqueued = TX_NO_MESSAGES; + queue_ptr -> tx_queue_available_storage = queue_ptr -> tx_queue_capacity; + queue_ptr -> tx_queue_read = queue_ptr -> tx_queue_start; + queue_ptr -> tx_queue_write = queue_ptr -> tx_queue_start; + + /* Now determine if there are any threads suspended on a full queue. */ + if (queue_ptr -> tx_queue_suspended_count != TX_NO_SUSPENSIONS) + { + + /* Yes, there are threads suspended on this queue, they must be + resumed! */ + + /* Copy the information into temporary variables. */ + suspension_list = queue_ptr -> tx_queue_suspension_list; + suspended_count = queue_ptr -> tx_queue_suspended_count; + + /* Clear the queue variables. */ + queue_ptr -> tx_queue_suspension_list = TX_NULL; + queue_ptr -> tx_queue_suspended_count = TX_NO_SUSPENSIONS; + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + } + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Walk through the queue list to resume any and all threads suspended + on this queue. */ + if (suspended_count != TX_NO_SUSPENSIONS) + { + + /* Pickup the thread to resume. */ + thread_ptr = suspension_list; + while (suspended_count != ((ULONG) 0)) + { + + /* Decrement the suspension count. */ + suspended_count--; + + /* Check for a NULL thread pointer. */ + if (thread_ptr == TX_NULL) + { + + /* Get out of the loop. */ + break; + } + + /* Resume the next suspended thread. */ + + /* Lockout interrupts. */ + TX_DISABLE + + /* Clear the cleanup pointer, this prevents the timeout from doing + anything. */ + thread_ptr -> tx_thread_suspend_cleanup = TX_NULL; + + /* Set the return status in the thread to TX_SUCCESS. */ + thread_ptr -> tx_thread_suspend_status = TX_SUCCESS; + + /* Move the thread pointer ahead. */ + thread_ptr = thread_ptr -> tx_thread_suspended_next; + +#ifdef TX_NOT_INTERRUPTABLE + + /* Resume the thread! */ + _tx_thread_system_ni_resume(thread_ptr -> tx_thread_suspended_previous); + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Temporarily disable preemption again. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Resume the thread. */ + _tx_thread_system_resume(thread_ptr -> tx_thread_suspended_previous); +#endif + } + + /* Disable interrupts. */ + TX_DISABLE + + /* Restore previous preempt posture. */ + _tx_thread_preempt_disable--; + + /* Restore interrupts. */ + TX_RESTORE + + /* Check for preemption. */ + _tx_thread_system_preempt_check(); + } + + /* Return TX_SUCCESS. */ + return(TX_SUCCESS); +} + diff --git a/common_smp/src/tx_queue_front_send.c b/common_smp/src/tx_queue_front_send.c new file mode 100644 index 00000000..45edb803 --- /dev/null +++ b/common_smp/src/tx_queue_front_send.c @@ -0,0 +1,421 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Queue */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_thread.h" +#include "tx_queue.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_queue_front_send PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function places a message at the front of the specified queue. */ +/* If there is no room in the queue, this function returns the */ +/* queue full status. */ +/* */ +/* INPUT */ +/* */ +/* queue_ptr Pointer to queue control block */ +/* source_ptr Pointer to message source */ +/* wait_option Suspension option */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_system_resume Resume thread routine */ +/* _tx_thread_system_ni_resume Non-interruptable resume thread */ +/* _tx_thread_system_suspend Suspend thread routine */ +/* _tx_thread_system_ni_suspend Non-interruptable suspend thread */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_queue_front_send(TX_QUEUE *queue_ptr, VOID *source_ptr, ULONG wait_option) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_THREAD *thread_ptr; +ULONG *source; +ULONG *destination; +UINT size; +UINT suspended_count; +TX_THREAD *next_thread; +TX_THREAD *previous_thread; +UINT status; +#ifndef TX_DISABLE_NOTIFY_CALLBACKS +VOID (*queue_send_notify)(struct TX_QUEUE_STRUCT *notify_queue_ptr); +#endif + + + /* Default the status to TX_SUCCESS. */ + status = TX_SUCCESS; + + /* Disable interrupts to place message in the queue. */ + TX_DISABLE + +#ifdef TX_QUEUE_ENABLE_PERFORMANCE_INFO + + /* Increment the total messages sent counter. */ + _tx_queue_performance_messages_sent_count++; + + /* Increment the number of messages sent to this queue. */ + queue_ptr -> tx_queue_performance_messages_sent_count++; +#endif + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_QUEUE_FRONT_SEND, queue_ptr, TX_POINTER_TO_ULONG_CONVERT(source_ptr), wait_option, queue_ptr -> tx_queue_enqueued, TX_TRACE_QUEUE_EVENTS) + + /* Log this kernel call. */ + TX_EL_QUEUE_FRONT_SEND_INSERT + + /* Pickup the suspended count. */ + suspended_count = queue_ptr -> tx_queue_suspended_count; + + /* Now check for room in the queue for placing the new message in front. */ + if (queue_ptr -> tx_queue_available_storage != ((UINT) 0)) + { + + /* Yes there is room in the queue. Now determine if there is a thread waiting + for a message. */ + if (suspended_count == TX_NO_SUSPENSIONS) + { + + /* No thread suspended while waiting for a message from + this queue. */ + + /* Adjust the read pointer since we are adding to the front of the + queue. */ + + /* See if the read pointer is at the beginning of the queue area. */ + if (queue_ptr -> tx_queue_read == queue_ptr -> tx_queue_start) + { + + /* Adjust the read pointer to the last message at the end of the + queue. */ + queue_ptr -> tx_queue_read = TX_ULONG_POINTER_SUB(queue_ptr -> tx_queue_end, queue_ptr -> tx_queue_message_size); + } + else + { + + /* Not at the beginning of the queue, just move back one message. */ + queue_ptr -> tx_queue_read = TX_ULONG_POINTER_SUB(queue_ptr -> tx_queue_read, queue_ptr -> tx_queue_message_size); + } + + /* Simply place the message in the queue. */ + + /* Reduce the amount of available storage. */ + queue_ptr -> tx_queue_available_storage--; + + /* Increase the enqueued count. */ + queue_ptr -> tx_queue_enqueued++; + + /* Setup source and destination pointers. */ + source = TX_VOID_TO_ULONG_POINTER_CONVERT(source_ptr); + destination = queue_ptr -> tx_queue_read; + size = queue_ptr -> tx_queue_message_size; + + /* Copy message. Note that the source and destination pointers are + incremented by the macro. */ + TX_QUEUE_MESSAGE_COPY(source, destination, size) + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the notify callback routine for this queue. */ + queue_send_notify = queue_ptr -> tx_queue_send_notify; +#endif + + /* Restore interrupts. */ + TX_RESTORE + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Determine if a notify callback is required. */ + if (queue_send_notify != TX_NULL) + { + + /* Call application queue send notification. */ + (queue_send_notify)(queue_ptr); + } +#endif + } + else + { + + /* Thread suspended waiting for a message. Remove it and copy this message + into its storage area. */ + thread_ptr = queue_ptr -> tx_queue_suspension_list; + + /* See if this is the only suspended thread on the list. */ + suspended_count--; + if (suspended_count == TX_NO_SUSPENSIONS) + { + + /* Yes, the only suspended thread. */ + + /* Update the head pointer. */ + queue_ptr -> tx_queue_suspension_list = TX_NULL; + } + else + { + + /* At least one more thread is on the same expiration list. */ + + /* Update the list head pointer. */ + queue_ptr -> tx_queue_suspension_list = thread_ptr -> tx_thread_suspended_next; + + /* Update the links of the adjacent threads. */ + next_thread = thread_ptr -> tx_thread_suspended_next; + queue_ptr -> tx_queue_suspension_list = next_thread; + + /* Update the links of the adjacent threads. */ + previous_thread = thread_ptr -> tx_thread_suspended_previous; + next_thread -> tx_thread_suspended_previous = previous_thread; + previous_thread -> tx_thread_suspended_next = next_thread; + } + + /* Decrement the suspension count. */ + queue_ptr -> tx_queue_suspended_count = suspended_count; + + /* Prepare for resumption of the thread. */ + + /* Clear cleanup routine to avoid timeout. */ + thread_ptr -> tx_thread_suspend_cleanup = TX_NULL; + + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the notify callback routine for this queue. */ + queue_send_notify = queue_ptr -> tx_queue_send_notify; +#endif + + /* Setup source and destination pointers. */ + source = TX_VOID_TO_ULONG_POINTER_CONVERT(source_ptr); + destination = TX_VOID_TO_ULONG_POINTER_CONVERT(thread_ptr -> tx_thread_additional_suspend_info); + size = queue_ptr -> tx_queue_message_size; + + /* Copy message. Note that the source and destination pointers are + incremented by the macro. */ + TX_QUEUE_MESSAGE_COPY(source, destination, size) + + /* Put return status into the thread control block. */ + thread_ptr -> tx_thread_suspend_status = TX_SUCCESS; + +#ifdef TX_NOT_INTERRUPTABLE + + /* Resume the thread! */ + _tx_thread_system_ni_resume(thread_ptr); + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Resume thread. */ + _tx_thread_system_resume(thread_ptr); +#endif + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Determine if a notify callback is required. */ + if (queue_send_notify != TX_NULL) + { + + /* Call application queue send notification. */ + (queue_send_notify)(queue_ptr); + } +#endif + } + } + + /* Determine if the caller has requested suspension. */ + else if (wait_option != TX_NO_WAIT) + { + + /* Determine if the preempt disable flag is non-zero. */ + if (_tx_thread_preempt_disable != ((UINT) 0)) + { + + /* Restore interrupts. */ + TX_RESTORE + + /* Suspension is not allowed if the preempt disable flag is non-zero at this point - return error completion. */ + status = TX_QUEUE_FULL; + } + else + { + + /* Yes, suspension is requested. */ + + /* Prepare for suspension of this thread. */ + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr) + + /* Setup cleanup routine pointer. */ + thread_ptr -> tx_thread_suspend_cleanup = &(_tx_queue_cleanup); + + /* Setup cleanup information, i.e. this queue control + block and the source pointer. */ + thread_ptr -> tx_thread_suspend_control_block = (VOID *) queue_ptr; + thread_ptr -> tx_thread_additional_suspend_info = (VOID *) source_ptr; + + /* Set the flag to true to indicate a queue front send suspension. */ + thread_ptr -> tx_thread_suspend_option = TX_TRUE; + +#ifndef TX_NOT_INTERRUPTABLE + + /* Increment the suspension sequence number, which is used to identify + this suspension event. */ + thread_ptr -> tx_thread_suspension_sequence++; +#endif + + /* Place this thread at the front of the suspension list, since it is a + queue front send suspension. */ + if (suspended_count == TX_NO_SUSPENSIONS) + { + + /* No other threads are suspended. Setup the head pointer and + just setup this threads pointers to itself. */ + queue_ptr -> tx_queue_suspension_list = thread_ptr; + thread_ptr -> tx_thread_suspended_next = thread_ptr; + thread_ptr -> tx_thread_suspended_previous = thread_ptr; + } + else + { + + /* This list is not NULL, add current thread to the end. */ + next_thread = queue_ptr -> tx_queue_suspension_list; + thread_ptr -> tx_thread_suspended_next = next_thread; + previous_thread = next_thread -> tx_thread_suspended_previous; + thread_ptr -> tx_thread_suspended_previous = previous_thread; + previous_thread -> tx_thread_suspended_next = thread_ptr; + next_thread -> tx_thread_suspended_previous = thread_ptr; + + /* Update the suspension list to put this thread in front, which will put + the message that was removed in the proper relative order when room is + made in the queue. */ + queue_ptr -> tx_queue_suspension_list = thread_ptr; + } + + /* Increment the suspended thread count. */ + queue_ptr -> tx_queue_suspended_count = suspended_count + ((UINT) 1); + + /* Set the state to suspended. */ + thread_ptr -> tx_thread_state = TX_QUEUE_SUSP; + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the notify callback routine for this queue. */ + queue_send_notify = queue_ptr -> tx_queue_send_notify; +#endif + +#ifdef TX_NOT_INTERRUPTABLE + + /* Call actual non-interruptable thread suspension routine. */ + _tx_thread_system_ni_suspend(thread_ptr, wait_option); + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Set the suspending flag. */ + thread_ptr -> tx_thread_suspending = TX_TRUE; + + /* Setup the timeout period. */ + thread_ptr -> tx_thread_timer.tx_timer_internal_remaining_ticks = wait_option; + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Call actual thread suspension routine. */ + _tx_thread_system_suspend(thread_ptr); +#endif + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Determine if a notify callback is required. */ + if (thread_ptr -> tx_thread_suspend_status == TX_SUCCESS) + { + + /* Check for a notify callback. */ + if (queue_send_notify != TX_NULL) + { + + /* Call application queue send notification. */ + (queue_send_notify)(queue_ptr); + } + } +#endif + + /* Return the completion status. */ + status = thread_ptr -> tx_thread_suspend_status; + } + } + else + { + + /* Restore interrupts. */ + TX_RESTORE + + /* No room in queue and no suspension requested, return error completion. */ + status = TX_QUEUE_FULL; + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/tx_queue_info_get.c b/common_smp/src/tx_queue_info_get.c new file mode 100644 index 00000000..2a9dce14 --- /dev/null +++ b/common_smp/src/tx_queue_info_get.c @@ -0,0 +1,145 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Queue */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_queue.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_queue_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves information from the specified queue. */ +/* */ +/* INPUT */ +/* */ +/* queue_ptr Pointer to queue control block */ +/* name Destination for the queue name */ +/* enqueued Destination for enqueued count */ +/* available_storage Destination for available storage */ +/* first_suspended Destination for pointer of first */ +/* thread suspended on this queue */ +/* suspended_count Destination for suspended count */ +/* next_queue Destination for pointer to next */ +/* queue on the created list */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_queue_info_get(TX_QUEUE *queue_ptr, CHAR **name, ULONG *enqueued, ULONG *available_storage, + TX_THREAD **first_suspended, ULONG *suspended_count, TX_QUEUE **next_queue) +{ + +TX_INTERRUPT_SAVE_AREA + + + /* Disable interrupts. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_QUEUE_INFO_GET, queue_ptr, 0, 0, 0, TX_TRACE_QUEUE_EVENTS) + + /* Log this kernel call. */ + TX_EL_QUEUE_INFO_GET_INSERT + + /* Retrieve all the pertinent information and return it in the supplied + destinations. */ + + /* Retrieve the name of the queue. */ + if (name != TX_NULL) + { + + *name = queue_ptr -> tx_queue_name; + } + + /* Retrieve the number of messages currently in the queue. */ + if (enqueued != TX_NULL) + { + + *enqueued = (ULONG) queue_ptr -> tx_queue_enqueued; + } + + /* Retrieve the number of messages that will still fit in the queue. */ + if (available_storage != TX_NULL) + { + + *available_storage = (ULONG) queue_ptr -> tx_queue_available_storage; + } + + /* Retrieve the first thread suspended on this queue. */ + if (first_suspended != TX_NULL) + { + + *first_suspended = queue_ptr -> tx_queue_suspension_list; + } + + /* Retrieve the number of threads suspended on this queue. */ + if (suspended_count != TX_NULL) + { + + *suspended_count = (ULONG) queue_ptr -> tx_queue_suspended_count; + } + + /* Retrieve the pointer to the next queue created. */ + if (next_queue != TX_NULL) + { + + *next_queue = queue_ptr -> tx_queue_created_next; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return completion status. */ + return(TX_SUCCESS); +} + diff --git a/common_smp/src/tx_queue_initialize.c b/common_smp/src/tx_queue_initialize.c new file mode 100644 index 00000000..e594d946 --- /dev/null +++ b/common_smp/src/tx_queue_initialize.c @@ -0,0 +1,138 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Queue */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_queue.h" + + +#ifndef TX_INLINE_INITIALIZATION + +/* Define the head pointer of the created queue list. */ + +TX_QUEUE * _tx_queue_created_ptr; + + +/* Define the variable that holds the number of created queues. */ + +ULONG _tx_queue_created_count; + + +#ifdef TX_QUEUE_ENABLE_PERFORMANCE_INFO + +/* Define the total number of messages sent. */ + +ULONG _tx_queue_performance_messages_sent_count; + + +/* Define the total number of messages received. */ + +ULONG _tx_queue_performance__messages_received_count; + + +/* Define the total number of queue empty suspensions. */ + +ULONG _tx_queue_performance_empty_suspension_count; + + +/* Define the total number of queue full suspensions. */ + +ULONG _tx_queue_performance_full_suspension_count; + + +/* Define the total number of queue full errors. */ + +ULONG _tx_queue_performance_full_error_count; + + +/* Define the total number of queue timeouts. */ + +ULONG _tx_queue_performance_timeout_count; + +#endif +#endif + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_queue_initialize PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes the various control data structures for */ +/* the queue component. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_high_level High level initialization */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_queue_initialize(VOID) +{ + +#ifndef TX_DISABLE_REDUNDANT_CLEARING + + /* Initialize the head pointer of the created queue list and the + number of queues created. */ + _tx_queue_created_ptr = TX_NULL; + _tx_queue_created_count = TX_EMPTY; + +#ifdef TX_QUEUE_ENABLE_PERFORMANCE_INFO + + /* Initialize the queue performance counters. */ + _tx_queue_performance_messages_sent_count = ((ULONG) 0); + _tx_queue_performance__messages_received_count = ((ULONG) 0); + _tx_queue_performance_empty_suspension_count = ((ULONG) 0); + _tx_queue_performance_full_suspension_count = ((ULONG) 0); + _tx_queue_performance_timeout_count = ((ULONG) 0); +#endif +#endif +} + diff --git a/common_smp/src/tx_queue_performance_info_get.c b/common_smp/src/tx_queue_performance_info_get.c new file mode 100644 index 00000000..6c34a3a3 --- /dev/null +++ b/common_smp/src/tx_queue_performance_info_get.c @@ -0,0 +1,229 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Queue */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_queue.h" +#ifdef TX_QUEUE_ENABLE_PERFORMANCE_INFO +#include "tx_trace.h" +#endif + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_queue_performance_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves performance information from the specified */ +/* queue. */ +/* */ +/* INPUT */ +/* */ +/* queue_ptr Pointer to queue control block */ +/* messages_sent Destination for messages sent */ +/* messages_received Destination for messages received */ +/* empty_suspensions Destination for number of empty */ +/* queue suspensions */ +/* full_suspensions Destination for number of full */ +/* queue suspensions */ +/* full_errors Destination for queue full errors */ +/* returned - no suspension */ +/* timeouts Destination for number of timeouts*/ +/* on this queue */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_queue_performance_info_get(TX_QUEUE *queue_ptr, ULONG *messages_sent, ULONG *messages_received, + ULONG *empty_suspensions, ULONG *full_suspensions, ULONG *full_errors, ULONG *timeouts) +{ + +#ifdef TX_QUEUE_ENABLE_PERFORMANCE_INFO + +TX_INTERRUPT_SAVE_AREA +UINT status; + + + /* Determine if this is a legal request. */ + if (queue_ptr == TX_NULL) + { + + /* Queue pointer is illegal, return error. */ + status = TX_PTR_ERROR; + } + + /* Determine if the queue ID is invalid. */ + else if (queue_ptr -> tx_queue_id != TX_QUEUE_ID) + { + + /* Queue pointer is illegal, return error. */ + status = TX_PTR_ERROR; + } + else + { + + /* Disable interrupts. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_QUEUE_PERFORMANCE_INFO_GET, queue_ptr, 0, 0, 0, TX_TRACE_QUEUE_EVENTS) + + /* Log this kernel call. */ + TX_EL_QUEUE_PERFORMANCE_INFO_GET_INSERT + + /* Retrieve all the pertinent information and return it in the supplied + destinations. */ + + /* Retrieve the number of messages sent to this queue. */ + if (messages_sent != TX_NULL) + { + + *messages_sent = queue_ptr -> tx_queue_performance_messages_sent_count; + } + + /* Retrieve the number of messages received from this queue. */ + if (messages_received != TX_NULL) + { + + *messages_received = queue_ptr -> tx_queue_performance_messages_received_count; + } + + /* Retrieve the number of empty queue suspensions on this queue. */ + if (empty_suspensions != TX_NULL) + { + + *empty_suspensions = queue_ptr -> tx_queue_performance_empty_suspension_count; + } + + /* Retrieve the number of full queue suspensions on this queue. */ + if (full_suspensions != TX_NULL) + { + + *full_suspensions = queue_ptr -> tx_queue_performance_full_suspension_count; + } + + /* Retrieve the number of full errors (no suspension!) on this queue. */ + if (full_errors != TX_NULL) + { + + *full_errors = queue_ptr -> tx_queue_performance_full_error_count; + } + + /* Retrieve the number of timeouts on this queue. */ + if (timeouts != TX_NULL) + { + + *timeouts = queue_ptr -> tx_queue_performance_timeout_count; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return completion status. */ + status = TX_SUCCESS; + } +#else +UINT status; + + + /* Access input arguments just for the sake of lint, MISRA, etc. */ + if (queue_ptr != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (messages_sent != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (messages_received != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (empty_suspensions != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (full_suspensions != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (full_errors != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (timeouts != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } +#endif + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/tx_queue_performance_system_info_get.c b/common_smp/src/tx_queue_performance_system_info_get.c new file mode 100644 index 00000000..edba3b41 --- /dev/null +++ b/common_smp/src/tx_queue_performance_system_info_get.c @@ -0,0 +1,205 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Queue */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_queue.h" +#ifdef TX_QUEUE_ENABLE_PERFORMANCE_INFO +#include "tx_trace.h" +#endif + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_queue_performance_system_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves queue system performance information. */ +/* */ +/* INPUT */ +/* */ +/* messages_sent Destination for total messages */ +/* sent */ +/* messages_received Destination for total messages */ +/* received */ +/* empty_suspensions Destination for total empty */ +/* queue suspensions */ +/* full_suspensions Destination for total full */ +/* queue suspensions */ +/* full_errors Destination for total queue full */ +/* errors returned - no suspension */ +/* timeouts Destination for total number of */ +/* timeouts */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_queue_performance_system_info_get(ULONG *messages_sent, ULONG *messages_received, + ULONG *empty_suspensions, ULONG *full_suspensions, ULONG *full_errors, ULONG *timeouts) +{ + +#ifdef TX_QUEUE_ENABLE_PERFORMANCE_INFO + +TX_INTERRUPT_SAVE_AREA + + + /* Disable interrupts. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_QUEUE_PERFORMANCE_SYSTEM_INFO_GET, 0, 0, 0, 0, TX_TRACE_QUEUE_EVENTS) + + /* Log this kernel call. */ + TX_EL_QUEUE_PERFORMANCE_SYSTEM_INFO_GET_INSERT + + /* Retrieve all the pertinent information and return it in the supplied + destinations. */ + + /* Retrieve the total number of queue messages sent. */ + if (messages_sent != TX_NULL) + { + + *messages_sent = _tx_queue_performance_messages_sent_count; + } + + /* Retrieve the total number of queue messages received. */ + if (messages_received != TX_NULL) + { + + *messages_received = _tx_queue_performance__messages_received_count; + } + + /* Retrieve the total number of empty queue suspensions. */ + if (empty_suspensions != TX_NULL) + { + + *empty_suspensions = _tx_queue_performance_empty_suspension_count; + } + + /* Retrieve the total number of full queue suspensions. */ + if (full_suspensions != TX_NULL) + { + + *full_suspensions = _tx_queue_performance_full_suspension_count; + } + + /* Retrieve the total number of full errors. */ + if (full_errors != TX_NULL) + { + + *full_errors = _tx_queue_performance_full_error_count; + } + + /* Retrieve the total number of queue timeouts. */ + if (timeouts != TX_NULL) + { + + *timeouts = _tx_queue_performance_timeout_count; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return completion status. */ + return(TX_SUCCESS); + +#else + +UINT status; + + + /* Access input arguments just for the sake of lint, MISRA, etc. */ + if (messages_sent != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (messages_received != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (empty_suspensions != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (full_suspensions != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (full_errors != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (timeouts != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + + /* Return completion status. */ + return(status); +#endif +} + diff --git a/common_smp/src/tx_queue_prioritize.c b/common_smp/src/tx_queue_prioritize.c new file mode 100644 index 00000000..98fde588 --- /dev/null +++ b/common_smp/src/tx_queue_prioritize.c @@ -0,0 +1,249 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Queue */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_thread.h" +#include "tx_queue.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_queue_prioritize PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function places the highest priority suspended thread at the */ +/* front of the suspension list. All other threads remain in the same */ +/* FIFO suspension order. */ +/* */ +/* INPUT */ +/* */ +/* queue_ptr Pointer to queue control block */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_system_preempt_check Check for preemption */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_queue_prioritize(TX_QUEUE *queue_ptr) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_THREAD *thread_ptr; +TX_THREAD *priority_thread_ptr; +TX_THREAD *head_ptr; +UINT suspended_count; +TX_THREAD *next_thread; +TX_THREAD *previous_thread; +UINT list_changed; + + + /* Disable interrupts to place message in the queue. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_QUEUE_PRIORITIZE, queue_ptr, queue_ptr -> tx_queue_suspended_count, TX_POINTER_TO_ULONG_CONVERT(&suspended_count), 0, TX_TRACE_QUEUE_EVENTS) + + /* Log this kernel call. */ + TX_EL_QUEUE_PRIORITIZE_INSERT + + /* Pickup the suspended count. */ + suspended_count = queue_ptr -> tx_queue_suspended_count; + + /* Determine if there are fewer than 2 suspended threads. */ + if (suspended_count < ((UINT) 2)) + { + + /* Restore interrupts. */ + TX_RESTORE + } + + /* Determine if there how many threads are suspended on this queue. */ + else if (suspended_count == ((UINT) 2)) + { + + /* Pickup the head pointer and the next pointer. */ + head_ptr = queue_ptr -> tx_queue_suspension_list; + next_thread = head_ptr -> tx_thread_suspended_next; + + /* Determine if the next suspended thread has a higher priority. */ + if ((next_thread -> tx_thread_priority) < (head_ptr -> tx_thread_priority)) + { + + /* Yes, move the list head to the next thread. */ + queue_ptr -> tx_queue_suspension_list = next_thread; + } + + /* Restore interrupts. */ + TX_RESTORE + } + else + { + + /* Remember the suspension count and head pointer. */ + head_ptr = queue_ptr -> tx_queue_suspension_list; + + /* Default the highest priority thread to the thread at the front of the list. */ + priority_thread_ptr = head_ptr; + + /* Setup search pointer. */ + thread_ptr = priority_thread_ptr -> tx_thread_suspended_next; + + /* Disable preemption. */ + _tx_thread_preempt_disable++; + + /* Set the list changed flag to false. */ + list_changed = TX_FALSE; + + /* Search through the list to find the highest priority thread. */ + do + { + + /* Is the current thread higher priority? */ + if (thread_ptr -> tx_thread_priority < priority_thread_ptr -> tx_thread_priority) + { + + /* Yes, remember that this thread is the highest priority. */ + priority_thread_ptr = thread_ptr; + } + + /* Restore interrupts temporarily. */ + TX_RESTORE + + /* Disable interrupts again. */ + TX_DISABLE + + /* Determine if any changes to the list have occurred while + interrupts were enabled. */ + + /* Is the list head the same? */ + if (head_ptr != queue_ptr -> tx_queue_suspension_list) + { + + /* The list head has changed, set the list changed flag. */ + list_changed = TX_TRUE; + } + else + { + + /* Is the suspended count the same? */ + if (suspended_count != queue_ptr -> tx_queue_suspended_count) + { + + /* The list head has changed, set the list changed flag. */ + list_changed = TX_TRUE; + } + } + + /* Determine if the list has changed. */ + if (list_changed == TX_FALSE) + { + + /* Move the thread pointer to the next thread. */ + thread_ptr = thread_ptr -> tx_thread_suspended_next; + } + else + { + + /* Save the suspension count and head pointer. */ + head_ptr = queue_ptr -> tx_queue_suspension_list; + suspended_count = queue_ptr -> tx_queue_suspended_count; + + /* Default the highest priority thread to the thread at the front of the list. */ + priority_thread_ptr = head_ptr; + + /* Setup search pointer. */ + thread_ptr = priority_thread_ptr -> tx_thread_suspended_next; + + /* Reset the list changed flag. */ + list_changed = TX_FALSE; + } + + } while (thread_ptr != head_ptr); + + /* Release preemption. */ + _tx_thread_preempt_disable--; + + /* Now determine if the highest priority thread is at the front + of the list. */ + if (priority_thread_ptr != head_ptr) + { + + /* No, we need to move the highest priority suspended thread to the + front of the list. */ + + /* First, remove the highest priority thread by updating the + adjacent suspended threads. */ + next_thread = priority_thread_ptr -> tx_thread_suspended_next; + previous_thread = priority_thread_ptr -> tx_thread_suspended_previous; + next_thread -> tx_thread_suspended_previous = previous_thread; + previous_thread -> tx_thread_suspended_next = next_thread; + + /* Now, link the highest priority thread at the front of the list. */ + previous_thread = head_ptr -> tx_thread_suspended_previous; + priority_thread_ptr -> tx_thread_suspended_next = head_ptr; + priority_thread_ptr -> tx_thread_suspended_previous = previous_thread; + previous_thread -> tx_thread_suspended_next = priority_thread_ptr; + head_ptr -> tx_thread_suspended_previous = priority_thread_ptr; + + /* Move the list head pointer to the highest priority suspended thread. */ + queue_ptr -> tx_queue_suspension_list = priority_thread_ptr; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Check for preemption. */ + _tx_thread_system_preempt_check(); + } + + /* Return successful status. */ + return(TX_SUCCESS); +} + diff --git a/common_smp/src/tx_queue_receive.c b/common_smp/src/tx_queue_receive.c new file mode 100644 index 00000000..56094f92 --- /dev/null +++ b/common_smp/src/tx_queue_receive.c @@ -0,0 +1,486 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Queue */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_thread.h" +#include "tx_queue.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_queue_receive PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function receives a message from the specified queue. If there */ +/* are no messages in the queue, this function waits according to the */ +/* option specified. */ +/* */ +/* INPUT */ +/* */ +/* queue_ptr Pointer to queue control block */ +/* destination_ptr Pointer to message destination */ +/* **** MUST BE LARGE ENOUGH TO */ +/* HOLD MESSAGE **** */ +/* wait_option Suspension option */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_system_resume Resume thread routine */ +/* _tx_thread_system_ni_resume Non-interruptable resume thread */ +/* _tx_thread_system_suspend Suspend thread routine */ +/* _tx_thread_system_ni_suspend Non-interruptable suspend thread */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_queue_receive(TX_QUEUE *queue_ptr, VOID *destination_ptr, ULONG wait_option) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_THREAD *thread_ptr; +ULONG *source; +ULONG *destination; +UINT size; +UINT suspended_count; +TX_THREAD *next_thread; +TX_THREAD *previous_thread; +UINT status; + + + /* Default the status to TX_SUCCESS. */ + status = TX_SUCCESS; + + /* Disable interrupts to receive message from queue. */ + TX_DISABLE + +#ifdef TX_QUEUE_ENABLE_PERFORMANCE_INFO + + /* Increment the total messages received counter. */ + _tx_queue_performance__messages_received_count++; + + /* Increment the number of messages received from this queue. */ + queue_ptr -> tx_queue_performance_messages_received_count++; + +#endif + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_QUEUE_RECEIVE, queue_ptr, TX_POINTER_TO_ULONG_CONVERT(destination_ptr), wait_option, queue_ptr -> tx_queue_enqueued, TX_TRACE_QUEUE_EVENTS) + + /* Log this kernel call. */ + TX_EL_QUEUE_RECEIVE_INSERT + + /* Pickup the thread suspension count. */ + suspended_count = queue_ptr -> tx_queue_suspended_count; + + /* Determine if there is anything in the queue. */ + if (queue_ptr -> tx_queue_enqueued != TX_NO_MESSAGES) + { + + /* Determine if there are any suspensions. */ + if (suspended_count == TX_NO_SUSPENSIONS) + { + + /* There is a message waiting in the queue and there are no suspensi. */ + + /* Setup source and destination pointers. */ + source = queue_ptr -> tx_queue_read; + destination = TX_VOID_TO_ULONG_POINTER_CONVERT(destination_ptr); + size = queue_ptr -> tx_queue_message_size; + + /* Copy message. Note that the source and destination pointers are + incremented by the macro. */ + TX_QUEUE_MESSAGE_COPY(source, destination, size) + + /* Determine if we are at the end. */ + if (source == queue_ptr -> tx_queue_end) + { + + /* Yes, wrap around to the beginning. */ + source = queue_ptr -> tx_queue_start; + } + + /* Setup the queue read pointer. */ + queue_ptr -> tx_queue_read = source; + + /* Increase the amount of available storage. */ + queue_ptr -> tx_queue_available_storage++; + + /* Decrease the enqueued count. */ + queue_ptr -> tx_queue_enqueued--; + + /* Restore interrupts. */ + TX_RESTORE + } + else + { + + /* At this point we know the queue is full. */ + + /* Pickup thread suspension list head pointer. */ + thread_ptr = queue_ptr -> tx_queue_suspension_list; + + /* Now determine if there is a queue front suspension active. */ + + /* Is the front suspension flag set? */ + if (thread_ptr -> tx_thread_suspend_option == TX_TRUE) + { + + /* Yes, a queue front suspension is present. */ + + /* Return the message associated with this suspension. */ + + /* Setup source and destination pointers. */ + source = TX_VOID_TO_ULONG_POINTER_CONVERT(thread_ptr -> tx_thread_additional_suspend_info); + destination = TX_VOID_TO_ULONG_POINTER_CONVERT(destination_ptr); + size = queue_ptr -> tx_queue_message_size; + + /* Copy message. Note that the source and destination pointers are + incremented by the macro. */ + TX_QUEUE_MESSAGE_COPY(source, destination, size) + + /* Message is now in the caller's destination. See if this is the only suspended thread + on the list. */ + suspended_count--; + if (suspended_count == TX_NO_SUSPENSIONS) + { + + /* Yes, the only suspended thread. */ + + /* Update the head pointer. */ + queue_ptr -> tx_queue_suspension_list = TX_NULL; + } + else + { + + /* At least one more thread is on the same expiration list. */ + + /* Update the list head pointer. */ + next_thread = thread_ptr -> tx_thread_suspended_next; + queue_ptr -> tx_queue_suspension_list = next_thread; + + /* Update the links of the adjacent threads. */ + previous_thread = thread_ptr -> tx_thread_suspended_previous; + next_thread -> tx_thread_suspended_previous = previous_thread; + previous_thread -> tx_thread_suspended_next = next_thread; + } + + /* Decrement the suspension count. */ + queue_ptr -> tx_queue_suspended_count = suspended_count; + + /* Prepare for resumption of the first thread. */ + + /* Clear cleanup routine to avoid timeout. */ + thread_ptr -> tx_thread_suspend_cleanup = TX_NULL; + + /* Put return status into the thread control block. */ + thread_ptr -> tx_thread_suspend_status = TX_SUCCESS; + +#ifdef TX_NOT_INTERRUPTABLE + + /* Resume the thread! */ + _tx_thread_system_ni_resume(thread_ptr); + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Resume thread. */ + _tx_thread_system_resume(thread_ptr); +#endif + } + else + { + + /* At this point, we know that the queue is full and there + are one or more threads suspended trying to send another + message to this queue. */ + + /* Setup source and destination pointers. */ + source = queue_ptr -> tx_queue_read; + destination = TX_VOID_TO_ULONG_POINTER_CONVERT(destination_ptr); + size = queue_ptr -> tx_queue_message_size; + + /* Copy message. Note that the source and destination pointers are + incremented by the macro. */ + TX_QUEUE_MESSAGE_COPY(source, destination, size) + + /* Determine if we are at the end. */ + if (source == queue_ptr -> tx_queue_end) + { + + /* Yes, wrap around to the beginning. */ + source = queue_ptr -> tx_queue_start; + } + + /* Setup the queue read pointer. */ + queue_ptr -> tx_queue_read = source; + + /* Disable preemption. */ + _tx_thread_preempt_disable++; + +#ifdef TX_NOT_INTERRUPTABLE + + /* Restore interrupts. */ + TX_RESTORE + + /* Interrupts are enabled briefly here to keep the interrupt + lockout time deterministic. */ + + /* Disable interrupts again. */ + TX_DISABLE +#endif + + /* Decrement the preemption disable variable. */ + _tx_thread_preempt_disable--; + + /* Setup source and destination pointers. */ + source = TX_VOID_TO_ULONG_POINTER_CONVERT(thread_ptr -> tx_thread_additional_suspend_info); + destination = queue_ptr -> tx_queue_write; + size = queue_ptr -> tx_queue_message_size; + + /* Copy message. Note that the source and destination pointers are + incremented by the macro. */ + TX_QUEUE_MESSAGE_COPY(source, destination, size) + + /* Determine if we are at the end. */ + if (destination == queue_ptr -> tx_queue_end) + { + + /* Yes, wrap around to the beginning. */ + destination = queue_ptr -> tx_queue_start; + } + + /* Adjust the write pointer. */ + queue_ptr -> tx_queue_write = destination; + + /* Pickup thread pointer. */ + thread_ptr = queue_ptr -> tx_queue_suspension_list; + + /* Message is now in the queue. See if this is the only suspended thread + on the list. */ + suspended_count--; + if (suspended_count == TX_NO_SUSPENSIONS) + { + + /* Yes, the only suspended thread. */ + + /* Update the head pointer. */ + queue_ptr -> tx_queue_suspension_list = TX_NULL; + } + else + { + + /* At least one more thread is on the same expiration list. */ + + /* Update the list head pointer. */ + next_thread = thread_ptr -> tx_thread_suspended_next; + queue_ptr -> tx_queue_suspension_list = next_thread; + + /* Update the links of the adjacent threads. */ + previous_thread = thread_ptr -> tx_thread_suspended_previous; + next_thread -> tx_thread_suspended_previous = previous_thread; + previous_thread -> tx_thread_suspended_next = next_thread; + } + + /* Decrement the suspension count. */ + queue_ptr -> tx_queue_suspended_count = suspended_count; + + /* Prepare for resumption of the first thread. */ + + /* Clear cleanup routine to avoid timeout. */ + thread_ptr -> tx_thread_suspend_cleanup = TX_NULL; + + /* Put return status into the thread control block. */ + thread_ptr -> tx_thread_suspend_status = TX_SUCCESS; + +#ifdef TX_NOT_INTERRUPTABLE + + /* Resume the thread! */ + _tx_thread_system_ni_resume(thread_ptr); + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Resume thread. */ + _tx_thread_system_resume(thread_ptr); +#endif + } + } + } + + /* Determine if the request specifies suspension. */ + else if (wait_option != TX_NO_WAIT) + { + + /* Determine if the preempt disable flag is non-zero. */ + if (_tx_thread_preempt_disable != ((UINT) 0)) + { + + /* Restore interrupts. */ + TX_RESTORE + + /* Suspension is not allowed if the preempt disable flag is non-zero at this point - return error completion. */ + status = TX_QUEUE_EMPTY; + } + else + { + + /* Prepare for suspension of this thread. */ + +#ifdef TX_QUEUE_ENABLE_PERFORMANCE_INFO + + /* Increment the total queue empty suspensions counter. */ + _tx_queue_performance_empty_suspension_count++; + + /* Increment the number of empty suspensions on this queue. */ + queue_ptr -> tx_queue_performance_empty_suspension_count++; +#endif + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr) + + /* Setup cleanup routine pointer. */ + thread_ptr -> tx_thread_suspend_cleanup = &(_tx_queue_cleanup); + + /* Setup cleanup information, i.e. this queue control + block and the source pointer. */ + thread_ptr -> tx_thread_suspend_control_block = (VOID *) queue_ptr; + thread_ptr -> tx_thread_additional_suspend_info = (VOID *) destination_ptr; + thread_ptr -> tx_thread_suspend_option = TX_FALSE; + +#ifndef TX_NOT_INTERRUPTABLE + + /* Increment the suspension sequence number, which is used to identify + this suspension event. */ + thread_ptr -> tx_thread_suspension_sequence++; +#endif + + /* Setup suspension list. */ + if (suspended_count == TX_NO_SUSPENSIONS) + { + + /* No other threads are suspended. Setup the head pointer and + just setup this threads pointers to itself. */ + queue_ptr -> tx_queue_suspension_list = thread_ptr; + thread_ptr -> tx_thread_suspended_next = thread_ptr; + thread_ptr -> tx_thread_suspended_previous = thread_ptr; + } + else + { + + /* This list is not NULL, add current thread to the end. */ + next_thread = queue_ptr -> tx_queue_suspension_list; + thread_ptr -> tx_thread_suspended_next = next_thread; + previous_thread = next_thread -> tx_thread_suspended_previous; + thread_ptr -> tx_thread_suspended_previous = previous_thread; + previous_thread -> tx_thread_suspended_next = thread_ptr; + next_thread -> tx_thread_suspended_previous = thread_ptr; + } + + /* Increment the suspended thread count. */ + queue_ptr -> tx_queue_suspended_count = suspended_count + ((UINT) 1); + + /* Set the state to suspended. */ + thread_ptr -> tx_thread_state = TX_QUEUE_SUSP; + +#ifdef TX_NOT_INTERRUPTABLE + + /* Call actual non-interruptable thread suspension routine. */ + _tx_thread_system_ni_suspend(thread_ptr, wait_option); + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Set the suspending flag. */ + thread_ptr -> tx_thread_suspending = TX_TRUE; + + /* Setup the timeout period. */ + thread_ptr -> tx_thread_timer.tx_timer_internal_remaining_ticks = wait_option; + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Call actual thread suspension routine. */ + _tx_thread_system_suspend(thread_ptr); +#endif + + /* Return the completion status. */ + status = thread_ptr -> tx_thread_suspend_status; + } + } + else + { + + /* Restore interrupts. */ + TX_RESTORE + + /* Immediate return, return error completion. */ + status = TX_QUEUE_EMPTY; + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/tx_queue_send.c b/common_smp/src/tx_queue_send.c new file mode 100644 index 00000000..61f48c47 --- /dev/null +++ b/common_smp/src/tx_queue_send.c @@ -0,0 +1,426 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Queue */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_thread.h" +#include "tx_queue.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_queue_send PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function places a message into the specified queue. If there */ +/* is no room in the queue, this function waits according to the */ +/* option specified. */ +/* */ +/* INPUT */ +/* */ +/* queue_ptr Pointer to queue control block */ +/* source_ptr Pointer to message source */ +/* wait_option Suspension option */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_system_resume Resume thread routine */ +/* _tx_thread_system_ni_resume Non-interruptable resume thread */ +/* _tx_thread_system_suspend Suspend thread routine */ +/* _tx_thread_system_ni_suspend Non-interruptable suspend thread */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_queue_send(TX_QUEUE *queue_ptr, VOID *source_ptr, ULONG wait_option) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_THREAD *thread_ptr; +ULONG *source; +ULONG *destination; +UINT size; +UINT suspended_count; +TX_THREAD *next_thread; +TX_THREAD *previous_thread; +UINT status; +#ifndef TX_DISABLE_NOTIFY_CALLBACKS +VOID (*queue_send_notify)(struct TX_QUEUE_STRUCT *notify_queue_ptr); +#endif + + + /* Default the status to TX_SUCCESS. */ + status = TX_SUCCESS; + + /* Disable interrupts to place message in the queue. */ + TX_DISABLE + +#ifdef TX_QUEUE_ENABLE_PERFORMANCE_INFO + + /* Increment the total messages sent counter. */ + _tx_queue_performance_messages_sent_count++; + + /* Increment the number of messages sent to this queue. */ + queue_ptr -> tx_queue_performance_messages_sent_count++; +#endif + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_QUEUE_SEND, queue_ptr, TX_POINTER_TO_ULONG_CONVERT(source_ptr), wait_option, queue_ptr -> tx_queue_enqueued, TX_TRACE_QUEUE_EVENTS) + + /* Log this kernel call. */ + TX_EL_QUEUE_SEND_INSERT + + /* Pickup the thread suspension count. */ + suspended_count = queue_ptr -> tx_queue_suspended_count; + + /* Determine if there is room in the queue. */ + if (queue_ptr -> tx_queue_available_storage != TX_NO_MESSAGES) + { + + /* There is room for the message in the queue. */ + + /* Determine if there are suspended on this queue. */ + if (suspended_count == TX_NO_SUSPENSIONS) + { + + /* No suspended threads, simply place the message in the queue. */ + + /* Reduce the amount of available storage. */ + queue_ptr -> tx_queue_available_storage--; + + /* Increase the enqueued count. */ + queue_ptr -> tx_queue_enqueued++; + + /* Setup source and destination pointers. */ + source = TX_VOID_TO_ULONG_POINTER_CONVERT(source_ptr); + destination = queue_ptr -> tx_queue_write; + size = queue_ptr -> tx_queue_message_size; + + /* Copy message. Note that the source and destination pointers are + incremented by the macro. */ + TX_QUEUE_MESSAGE_COPY(source, destination, size) + + /* Determine if we are at the end. */ + if (destination == queue_ptr -> tx_queue_end) + { + + /* Yes, wrap around to the beginning. */ + destination = queue_ptr -> tx_queue_start; + } + + /* Adjust the write pointer. */ + queue_ptr -> tx_queue_write = destination; + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the notify callback routine for this queue. */ + queue_send_notify = queue_ptr -> tx_queue_send_notify; +#endif + + /* No thread suspended, just return to caller. */ + + /* Restore interrupts. */ + TX_RESTORE + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Determine if a notify callback is required. */ + if (queue_send_notify != TX_NULL) + { + + /* Call application queue send notification. */ + (queue_send_notify)(queue_ptr); + } +#endif + } + else + { + + /* There is a thread suspended on an empty queue. Simply + copy the message to the suspended thread's destination + pointer. */ + + /* Pickup the head of the suspension list. */ + thread_ptr = queue_ptr -> tx_queue_suspension_list; + + /* See if this is the only suspended thread on the list. */ + suspended_count--; + if (suspended_count == TX_NO_SUSPENSIONS) + { + + /* Yes, the only suspended thread. */ + + /* Update the head pointer. */ + queue_ptr -> tx_queue_suspension_list = TX_NULL; + } + else + { + + /* At least one more thread is on the same expiration list. */ + + /* Update the list head pointer. */ + queue_ptr -> tx_queue_suspension_list = thread_ptr -> tx_thread_suspended_next; + + /* Update the links of the adjacent threads. */ + next_thread = thread_ptr -> tx_thread_suspended_next; + queue_ptr -> tx_queue_suspension_list = next_thread; + + /* Update the links of the adjacent threads. */ + previous_thread = thread_ptr -> tx_thread_suspended_previous; + next_thread -> tx_thread_suspended_previous = previous_thread; + previous_thread -> tx_thread_suspended_next = next_thread; + } + + /* Decrement the suspension count. */ + queue_ptr -> tx_queue_suspended_count = suspended_count; + + /* Prepare for resumption of the thread. */ + + /* Clear cleanup routine to avoid timeout. */ + thread_ptr -> tx_thread_suspend_cleanup = TX_NULL; + + /* Setup source and destination pointers. */ + source = TX_VOID_TO_ULONG_POINTER_CONVERT(source_ptr); + destination = TX_VOID_TO_ULONG_POINTER_CONVERT(thread_ptr -> tx_thread_additional_suspend_info); + size = queue_ptr -> tx_queue_message_size; + + /* Copy message. Note that the source and destination pointers are + incremented by the macro. */ + TX_QUEUE_MESSAGE_COPY(source, destination, size) + + /* Put return status into the thread control block. */ + thread_ptr -> tx_thread_suspend_status = TX_SUCCESS; + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the notify callback routine for this queue. */ + queue_send_notify = queue_ptr -> tx_queue_send_notify; +#endif + +#ifdef TX_NOT_INTERRUPTABLE + + /* Resume the thread! */ + _tx_thread_system_ni_resume(thread_ptr); + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Resume thread. */ + _tx_thread_system_resume(thread_ptr); +#endif + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Determine if a notify callback is required. */ + if (queue_send_notify != TX_NULL) + { + + /* Call application queue send notification. */ + (queue_send_notify)(queue_ptr); + } +#endif + } + } + + /* At this point, the queue is full. Determine if suspension is requested. */ + else if (wait_option != TX_NO_WAIT) + { + + /* Determine if the preempt disable flag is non-zero. */ + if (_tx_thread_preempt_disable != ((UINT) 0)) + { + + /* Restore interrupts. */ + TX_RESTORE + + /* Suspension is not allowed if the preempt disable flag is non-zero at this point - return error completion. */ + status = TX_QUEUE_FULL; + } + else + { + + /* Yes, prepare for suspension of this thread. */ + +#ifdef TX_QUEUE_ENABLE_PERFORMANCE_INFO + + /* Increment the total number of queue full suspensions. */ + _tx_queue_performance_full_suspension_count++; + + /* Increment the number of full suspensions on this queue. */ + queue_ptr -> tx_queue_performance_full_suspension_count++; +#endif + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr) + + /* Setup cleanup routine pointer. */ + thread_ptr -> tx_thread_suspend_cleanup = &(_tx_queue_cleanup); + + /* Setup cleanup information, i.e. this queue control + block and the source pointer. */ + thread_ptr -> tx_thread_suspend_control_block = (VOID *) queue_ptr; + thread_ptr -> tx_thread_additional_suspend_info = (VOID *) source_ptr; + thread_ptr -> tx_thread_suspend_option = TX_FALSE; + +#ifndef TX_NOT_INTERRUPTABLE + + /* Increment the suspension sequence number, which is used to identify + this suspension event. */ + thread_ptr -> tx_thread_suspension_sequence++; +#endif + + /* Setup suspension list. */ + if (suspended_count == TX_NO_SUSPENSIONS) + { + + /* No other threads are suspended. Setup the head pointer and + just setup this threads pointers to itself. */ + queue_ptr -> tx_queue_suspension_list = thread_ptr; + thread_ptr -> tx_thread_suspended_next = thread_ptr; + thread_ptr -> tx_thread_suspended_previous = thread_ptr; + } + else + { + + /* This list is not NULL, add current thread to the end. */ + next_thread = queue_ptr -> tx_queue_suspension_list; + thread_ptr -> tx_thread_suspended_next = next_thread; + previous_thread = next_thread -> tx_thread_suspended_previous; + thread_ptr -> tx_thread_suspended_previous = previous_thread; + previous_thread -> tx_thread_suspended_next = thread_ptr; + next_thread -> tx_thread_suspended_previous = thread_ptr; + } + + /* Increment the suspended thread count. */ + queue_ptr -> tx_queue_suspended_count = suspended_count + ((UINT) 1); + + /* Set the state to suspended. */ + thread_ptr -> tx_thread_state = TX_QUEUE_SUSP; + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the notify callback routine for this queue. */ + queue_send_notify = queue_ptr -> tx_queue_send_notify; +#endif + +#ifdef TX_NOT_INTERRUPTABLE + + /* Call actual non-interruptable thread suspension routine. */ + _tx_thread_system_ni_suspend(thread_ptr, wait_option); + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Set the suspending flag. */ + thread_ptr -> tx_thread_suspending = TX_TRUE; + + /* Setup the timeout period. */ + thread_ptr -> tx_thread_timer.tx_timer_internal_remaining_ticks = wait_option; + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Call actual thread suspension routine. */ + _tx_thread_system_suspend(thread_ptr); +#endif + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Determine if a notify callback is required. */ + if (thread_ptr -> tx_thread_suspend_status == TX_SUCCESS) + { + + /* Determine if there is a notify callback. */ + if (queue_send_notify != TX_NULL) + { + + /* Call application queue send notification. */ + (queue_send_notify)(queue_ptr); + } + } +#endif + + /* Return the completion status. */ + status = thread_ptr -> tx_thread_suspend_status; + } + } + else + { + + /* Otherwise, just return a queue full error message to the caller. */ + +#ifdef TX_QUEUE_ENABLE_PERFORMANCE_INFO + + /* Increment the number of full non-suspensions on this queue. */ + queue_ptr -> tx_queue_performance_full_error_count++; + + /* Increment the total number of full non-suspensions. */ + _tx_queue_performance_full_error_count++; +#endif + + /* Restore interrupts. */ + TX_RESTORE + + /* Return error completion. */ + status = TX_QUEUE_FULL; + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/tx_queue_send_notify.c b/common_smp/src/tx_queue_send_notify.c new file mode 100644 index 00000000..8bbf26ce --- /dev/null +++ b/common_smp/src/tx_queue_send_notify.c @@ -0,0 +1,107 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Queue */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_queue.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_queue_send_notify PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application callback function that is */ +/* called whenever a messages is sent to this queue. */ +/* */ +/* INPUT */ +/* */ +/* queue_ptr Pointer to queue control block*/ +/* queue_send_notify Application callback function */ +/* (TX_NULL disables notify) */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_queue_send_notify(TX_QUEUE *queue_ptr, VOID (*queue_send_notify)(TX_QUEUE *notify_queue_ptr)) +{ + +#ifdef TX_DISABLE_NOTIFY_CALLBACKS + + TX_QUEUE_NOT_USED(queue_ptr); + TX_QUEUE_SEND_NOTIFY_NOT_USED(queue_send_notify); + + /* Feature is not enabled, return error. */ + return(TX_FEATURE_NOT_ENABLED); +#else + +TX_INTERRUPT_SAVE_AREA + + + /* Disable interrupts. */ + TX_DISABLE + + /* Make entry in event log. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_QUEUE_SEND_NOTIFY, queue_ptr, 0, 0, 0, TX_TRACE_QUEUE_EVENTS) + + /* Make entry in event log. */ + TX_EL_QUEUE_SEND_NOTIFY_INSERT + + /* Setup queue send notification callback function. */ + queue_ptr -> tx_queue_send_notify = queue_send_notify; + + /* Restore interrupts. */ + TX_RESTORE + + /* Return success to caller. */ + return(TX_SUCCESS); +#endif +} + diff --git a/common_smp/src/tx_semaphore_ceiling_put.c b/common_smp/src/tx_semaphore_ceiling_put.c new file mode 100644 index 00000000..8c41a336 --- /dev/null +++ b/common_smp/src/tx_semaphore_ceiling_put.c @@ -0,0 +1,243 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Semaphore */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_thread.h" +#include "tx_semaphore.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_semaphore_ceiling_put PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function puts an instance into the specified counting */ +/* semaphore up to the specified semaphore ceiling. */ +/* */ +/* INPUT */ +/* */ +/* semaphore_ptr Pointer to semaphore */ +/* ceiling Maximum value of semaphore */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_system_resume Resume thread service */ +/* _tx_thread_system_ni_resume Non-interruptable resume */ +/* thread */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_semaphore_ceiling_put(TX_SEMAPHORE *semaphore_ptr, ULONG ceiling) +{ + +TX_INTERRUPT_SAVE_AREA + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS +VOID (*semaphore_put_notify)(struct TX_SEMAPHORE_STRUCT *notify_semaphore_ptr); +#endif + +TX_THREAD *thread_ptr; +UINT suspended_count; +TX_THREAD *next_thread; +TX_THREAD *previous_thread; +UINT status; + + + /* Default the status to TX_SUCCESS. */ + status = TX_SUCCESS; + + /* Disable interrupts to put an instance back to the semaphore. */ + TX_DISABLE + +#ifdef TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO + + /* Increment the total semaphore put counter. */ + _tx_semaphore_performance_put_count++; + + /* Increment the number of puts on this semaphore. */ + semaphore_ptr -> tx_semaphore_performance_put_count++; +#endif + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_SEMAPHORE_CEILING_PUT, semaphore_ptr, semaphore_ptr -> tx_semaphore_count, semaphore_ptr -> tx_semaphore_suspended_count, ceiling, TX_TRACE_SEMAPHORE_EVENTS) + + /* Log this kernel call. */ + TX_EL_SEMAPHORE_CEILING_PUT_INSERT + + /* Pickup the number of suspended threads. */ + suspended_count = semaphore_ptr -> tx_semaphore_suspended_count; + + /* Determine if there are any threads suspended on the semaphore. */ + if (suspended_count == TX_NO_SUSPENSIONS) + { + + /* Determine if the ceiling has been exceeded. */ + if (semaphore_ptr -> tx_semaphore_count >= ceiling) + { + + /* Restore interrupts. */ + TX_RESTORE + + /* Return an error. */ + status = TX_CEILING_EXCEEDED; + } + else + { + + /* Increment the semaphore count. */ + semaphore_ptr -> tx_semaphore_count++; + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the application notify function. */ + semaphore_put_notify = semaphore_ptr -> tx_semaphore_put_notify; +#endif + + /* Restore interrupts. */ + TX_RESTORE + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Determine if notification is required. */ + if (semaphore_put_notify != TX_NULL) + { + + /* Yes, call the appropriate notify callback function. */ + (semaphore_put_notify)(semaphore_ptr); + } +#endif + + /* Return successful completion status. */ + status = TX_SUCCESS; + } + } + else + { + + /* Remove the suspended thread from the list. */ + + /* Pickup the pointer to the first suspended thread. */ + thread_ptr = semaphore_ptr -> tx_semaphore_suspension_list; + + /* See if this is the only suspended thread on the list. */ + suspended_count--; + if (suspended_count == TX_NO_SUSPENSIONS) + { + + /* Yes, the only suspended thread. */ + + /* Update the head pointer. */ + semaphore_ptr -> tx_semaphore_suspension_list = TX_NULL; + } + else + { + + /* At least one more thread is on the same expiration list. */ + + /* Update the list head pointer. */ + next_thread = thread_ptr -> tx_thread_suspended_next; + semaphore_ptr -> tx_semaphore_suspension_list = next_thread; + + /* Update the links of the adjacent threads. */ + previous_thread = thread_ptr -> tx_thread_suspended_previous; + next_thread -> tx_thread_suspended_previous = previous_thread; + previous_thread -> tx_thread_suspended_next = next_thread; + } + + /* Decrement the suspension count. */ + semaphore_ptr -> tx_semaphore_suspended_count = suspended_count; + + /* Prepare for resumption of the first thread. */ + + /* Clear cleanup routine to avoid timeout. */ + thread_ptr -> tx_thread_suspend_cleanup = TX_NULL; + + /* Put return status into the thread control block. */ + thread_ptr -> tx_thread_suspend_status = TX_SUCCESS; + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the application notify function. */ + semaphore_put_notify = semaphore_ptr -> tx_semaphore_put_notify; +#endif + +#ifdef TX_NOT_INTERRUPTABLE + + /* Resume the thread! */ + _tx_thread_system_ni_resume(thread_ptr); + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Resume thread. */ + _tx_thread_system_resume(thread_ptr); +#endif + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Determine if notification is required. */ + if (semaphore_put_notify != TX_NULL) + { + + /* Yes, call the appropriate notify callback function. */ + (semaphore_put_notify)(semaphore_ptr); + } +#endif + } + + /* Return successful completion. */ + return(status); +} + diff --git a/common_smp/src/tx_semaphore_cleanup.c b/common_smp/src/tx_semaphore_cleanup.c new file mode 100644 index 00000000..711a5bb4 --- /dev/null +++ b/common_smp/src/tx_semaphore_cleanup.c @@ -0,0 +1,215 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Semaphore */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_semaphore.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_semaphore_cleanup PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes semaphore timeout and thread terminate */ +/* actions that require the semaphore data structures to be cleaned */ +/* up. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to suspended thread's */ +/* control block */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_system_resume Resume thread service */ +/* _tx_thread_system_ni_resume Non-interruptable resume thread */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_timeout Thread timeout processing */ +/* _tx_thread_terminate Thread terminate processing */ +/* _tx_thread_wait_abort Thread wait abort processing */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_semaphore_cleanup(TX_THREAD *thread_ptr, ULONG suspension_sequence) +{ + +#ifndef TX_NOT_INTERRUPTABLE +TX_INTERRUPT_SAVE_AREA +#endif + +TX_SEMAPHORE *semaphore_ptr; +UINT suspended_count; +TX_THREAD *next_thread; +TX_THREAD *previous_thread; + + + +#ifndef TX_NOT_INTERRUPTABLE + + /* Disable interrupts to remove the suspended thread from the semaphore. */ + TX_DISABLE + + /* Determine if the cleanup is still required. */ + if (thread_ptr -> tx_thread_suspend_cleanup == &(_tx_semaphore_cleanup)) + { + + /* Check for valid suspension sequence. */ + if (suspension_sequence == thread_ptr -> tx_thread_suspension_sequence) + { + + /* Setup pointer to semaphore control block. */ + semaphore_ptr = TX_VOID_TO_SEMAPHORE_POINTER_CONVERT(thread_ptr -> tx_thread_suspend_control_block); + + /* Check for a NULL semaphore pointer. */ + if (semaphore_ptr != TX_NULL) + { + + /* Check for a valid semaphore ID. */ + if (semaphore_ptr -> tx_semaphore_id == TX_SEMAPHORE_ID) + { + + /* Determine if there are any thread suspensions. */ + if (semaphore_ptr -> tx_semaphore_suspended_count != TX_NO_SUSPENSIONS) + { +#else + + /* Setup pointer to semaphore control block. */ + semaphore_ptr = TX_VOID_TO_SEMAPHORE_POINTER_CONVERT(thread_ptr -> tx_thread_suspend_control_block); +#endif + + /* Yes, we still have thread suspension! */ + + /* Clear the suspension cleanup flag. */ + thread_ptr -> tx_thread_suspend_cleanup = TX_NULL; + + /* Decrement the suspended count. */ + semaphore_ptr -> tx_semaphore_suspended_count--; + + /* Pickup the suspended count. */ + suspended_count = semaphore_ptr -> tx_semaphore_suspended_count; + + /* Remove the suspended thread from the list. */ + + /* See if this is the only suspended thread on the list. */ + if (suspended_count == TX_NO_SUSPENSIONS) + { + + /* Yes, the only suspended thread. */ + + /* Update the head pointer. */ + semaphore_ptr -> tx_semaphore_suspension_list = TX_NULL; + } + else + { + + /* At least one more thread is on the same suspension list. */ + + /* Update the links of the adjacent threads. */ + next_thread = thread_ptr -> tx_thread_suspended_next; + previous_thread = thread_ptr -> tx_thread_suspended_previous; + next_thread -> tx_thread_suspended_previous = previous_thread; + previous_thread -> tx_thread_suspended_next = next_thread; + + /* Determine if we need to update the head pointer. */ + if (semaphore_ptr -> tx_semaphore_suspension_list == thread_ptr) + { + + /* Update the list head pointer. */ + semaphore_ptr -> tx_semaphore_suspension_list = next_thread; + } + } + + /* Now we need to determine if this cleanup is from a terminate, timeout, + or from a wait abort. */ + if (thread_ptr -> tx_thread_state == TX_SEMAPHORE_SUSP) + { + + /* Timeout condition and the thread is still suspended on the semaphore. + Setup return error status and resume the thread. */ + +#ifdef TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO + + /* Increment the total timeouts counter. */ + _tx_semaphore_performance_timeout_count++; + + /* Increment the number of timeouts on this semaphore. */ + semaphore_ptr -> tx_semaphore_performance_timeout_count++; +#endif + + /* Setup return status. */ + thread_ptr -> tx_thread_suspend_status = TX_NO_INSTANCE; + +#ifdef TX_NOT_INTERRUPTABLE + + /* Resume the thread! */ + _tx_thread_system_ni_resume(thread_ptr); +#else + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Resume the thread! */ + _tx_thread_system_resume(thread_ptr); + + /* Disable interrupts. */ + TX_DISABLE +#endif + } +#ifndef TX_NOT_INTERRUPTABLE + } + } + } + } + } + + /* Restore interrupts. */ + TX_RESTORE +#endif +} + diff --git a/common_smp/src/tx_semaphore_create.c b/common_smp/src/tx_semaphore_create.c new file mode 100644 index 00000000..0a0d6d3c --- /dev/null +++ b/common_smp/src/tx_semaphore_create.c @@ -0,0 +1,142 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Semaphore */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_semaphore.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_semaphore_create PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates a counting semaphore with the initial count */ +/* specified in this call. */ +/* */ +/* INPUT */ +/* */ +/* semaphore_ptr Pointer to semaphore control block*/ +/* name_ptr Pointer to semaphore name */ +/* initial_count Initial semaphore count */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SUCCESS Successful completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_semaphore_create(TX_SEMAPHORE *semaphore_ptr, CHAR *name_ptr, ULONG initial_count) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_SEMAPHORE *next_semaphore; +TX_SEMAPHORE *previous_semaphore; + + + /* Initialize semaphore control block to all zeros. */ + TX_MEMSET(semaphore_ptr, 0, (sizeof(TX_SEMAPHORE))); + + /* Setup the basic semaphore fields. */ + semaphore_ptr -> tx_semaphore_name = name_ptr; + semaphore_ptr -> tx_semaphore_count = initial_count; + + /* Disable interrupts to place the semaphore on the created list. */ + TX_DISABLE + + /* Setup the semaphore ID to make it valid. */ + semaphore_ptr -> tx_semaphore_id = TX_SEMAPHORE_ID; + + /* Place the semaphore on the list of created semaphores. First, + check for an empty list. */ + if (_tx_semaphore_created_count == TX_EMPTY) + { + + /* The created semaphore list is empty. Add semaphore to empty list. */ + _tx_semaphore_created_ptr = semaphore_ptr; + semaphore_ptr -> tx_semaphore_created_next = semaphore_ptr; + semaphore_ptr -> tx_semaphore_created_previous = semaphore_ptr; + } + else + { + + /* This list is not NULL, add to the end of the list. */ + next_semaphore = _tx_semaphore_created_ptr; + previous_semaphore = next_semaphore -> tx_semaphore_created_previous; + + /* Place the new semaphore in the list. */ + next_semaphore -> tx_semaphore_created_previous = semaphore_ptr; + previous_semaphore -> tx_semaphore_created_next = semaphore_ptr; + + /* Setup this semaphore's next and previous created links. */ + semaphore_ptr -> tx_semaphore_created_previous = previous_semaphore; + semaphore_ptr -> tx_semaphore_created_next = next_semaphore; + } + + /* Increment the created count. */ + _tx_semaphore_created_count++; + + /* Optional semaphore create extended processing. */ + TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) + + /* If trace is enabled, register this object. */ + TX_TRACE_OBJECT_REGISTER(TX_TRACE_OBJECT_TYPE_SEMAPHORE, semaphore_ptr, name_ptr, initial_count, 0) + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_SEMAPHORE_CREATE, semaphore_ptr, initial_count, TX_POINTER_TO_ULONG_CONVERT(&next_semaphore), 0, TX_TRACE_SEMAPHORE_EVENTS) + + /* Log this kernel call. */ + TX_EL_SEMAPHORE_CREATE_INSERT + + /* Restore interrupts. */ + TX_RESTORE + + /* Return TX_SUCCESS. */ + return(TX_SUCCESS); +} + diff --git a/common_smp/src/tx_semaphore_delete.c b/common_smp/src/tx_semaphore_delete.c new file mode 100644 index 00000000..962c78b9 --- /dev/null +++ b/common_smp/src/tx_semaphore_delete.c @@ -0,0 +1,207 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Semaphore */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_thread.h" +#include "tx_semaphore.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_semaphore_delete PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function deletes the specified semaphore. All threads */ +/* suspended on the semaphore are resumed with the TX_DELETED status */ +/* code. */ +/* */ +/* INPUT */ +/* */ +/* semaphore_ptr Pointer to semaphore control block*/ +/* */ +/* OUTPUT */ +/* */ +/* TX_SUCCESS Successful completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_system_preempt_check Check for preemption */ +/* _tx_thread_system_resume Resume thread service */ +/* _tx_thread_system_ni_resume Non-interruptable resume thread */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_semaphore_delete(TX_SEMAPHORE *semaphore_ptr) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_THREAD *thread_ptr; +TX_THREAD *next_thread; +UINT suspended_count; +TX_SEMAPHORE *next_semaphore; +TX_SEMAPHORE *previous_semaphore; + + + /* Disable interrupts to remove the semaphore from the created list. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_SEMAPHORE_DELETE, semaphore_ptr, TX_POINTER_TO_ULONG_CONVERT(&thread_ptr), 0, 0, TX_TRACE_SEMAPHORE_EVENTS) + + /* Optional semaphore delete extended processing. */ + TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) + + /* If trace is enabled, unregister this object. */ + TX_TRACE_OBJECT_UNREGISTER(semaphore_ptr) + + /* Log this kernel call. */ + TX_EL_SEMAPHORE_DELETE_INSERT + + /* Clear the semaphore ID to make it invalid. */ + semaphore_ptr -> tx_semaphore_id = TX_CLEAR_ID; + + /* Decrement the number of semaphores. */ + _tx_semaphore_created_count--; + + /* See if the semaphore is the only one on the list. */ + if (_tx_semaphore_created_count == TX_EMPTY) + { + + /* Only created semaphore, just set the created list to NULL. */ + _tx_semaphore_created_ptr = TX_NULL; + } + else + { + + /* Link-up the neighbors. */ + next_semaphore = semaphore_ptr -> tx_semaphore_created_next; + previous_semaphore = semaphore_ptr -> tx_semaphore_created_previous; + next_semaphore -> tx_semaphore_created_previous = previous_semaphore; + previous_semaphore -> tx_semaphore_created_next = next_semaphore; + + /* See if we have to update the created list head pointer. */ + if (_tx_semaphore_created_ptr == semaphore_ptr) + { + + /* Yes, move the head pointer to the next link. */ + _tx_semaphore_created_ptr = next_semaphore; + } + } + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Pickup the suspension information. */ + thread_ptr = semaphore_ptr -> tx_semaphore_suspension_list; + semaphore_ptr -> tx_semaphore_suspension_list = TX_NULL; + suspended_count = semaphore_ptr -> tx_semaphore_suspended_count; + semaphore_ptr -> tx_semaphore_suspended_count = TX_NO_SUSPENSIONS; + + /* Restore interrupts. */ + TX_RESTORE + + /* Walk through the semaphore list to resume any and all threads suspended + on this semaphore. */ + while (suspended_count != TX_NO_SUSPENSIONS) + { + + /* Decrement the suspension count. */ + suspended_count--; + + /* Lockout interrupts. */ + TX_DISABLE + + /* Clear the cleanup pointer, this prevents the timeout from doing + anything. */ + thread_ptr -> tx_thread_suspend_cleanup = TX_NULL; + + /* Set the return status in the thread to TX_DELETED. */ + thread_ptr -> tx_thread_suspend_status = TX_DELETED; + + /* Move the thread pointer ahead. */ + next_thread = thread_ptr -> tx_thread_suspended_next; + +#ifdef TX_NOT_INTERRUPTABLE + + /* Resume the thread! */ + _tx_thread_system_ni_resume(thread_ptr); + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Temporarily disable preemption again. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Resume the thread. */ + _tx_thread_system_resume(thread_ptr); +#endif + + /* Move to next thread. */ + thread_ptr = next_thread; + } + + /* Execute Port-Specific completion processing. If needed, it is typically defined in tx_port.h. */ + TX_SEMAPHORE_DELETE_PORT_COMPLETION(semaphore_ptr) + + /* Disable interrupts. */ + TX_DISABLE + + /* Release previous preempt disable. */ + _tx_thread_preempt_disable--; + + /* Restore interrupts. */ + TX_RESTORE + + /* Check for preemption. */ + _tx_thread_system_preempt_check(); + + /* Return TX_SUCCESS. */ + return(TX_SUCCESS); +} + diff --git a/common_smp/src/tx_semaphore_get.c b/common_smp/src/tx_semaphore_get.c new file mode 100644 index 00000000..0cec8daa --- /dev/null +++ b/common_smp/src/tx_semaphore_get.c @@ -0,0 +1,232 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Semaphore */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_thread.h" +#include "tx_semaphore.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_semaphore_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets an instance from the specified counting */ +/* semaphore. */ +/* */ +/* INPUT */ +/* */ +/* semaphore_ptr Pointer to semaphore control block*/ +/* wait_option Suspension option */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_system_suspend Suspend thread service */ +/* _tx_thread_system_ni_suspend Non-interruptable suspend thread */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_semaphore_get(TX_SEMAPHORE *semaphore_ptr, ULONG wait_option) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_THREAD *thread_ptr; +TX_THREAD *next_thread; +TX_THREAD *previous_thread; +UINT status; + + + /* Default the status to TX_SUCCESS. */ + status = TX_SUCCESS; + + /* Disable interrupts to get an instance from the semaphore. */ + TX_DISABLE + +#ifdef TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO + + /* Increment the total semaphore get counter. */ + _tx_semaphore_performance_get_count++; + + /* Increment the number of attempts to get this semaphore. */ + semaphore_ptr -> tx_semaphore_performance_get_count++; +#endif + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_SEMAPHORE_GET, semaphore_ptr, wait_option, semaphore_ptr -> tx_semaphore_count, TX_POINTER_TO_ULONG_CONVERT(&thread_ptr), TX_TRACE_SEMAPHORE_EVENTS) + + /* Log this kernel call. */ + TX_EL_SEMAPHORE_GET_INSERT + + /* Determine if there is an instance of the semaphore. */ + if (semaphore_ptr -> tx_semaphore_count != ((ULONG) 0)) + { + + /* Decrement the semaphore count. */ + semaphore_ptr -> tx_semaphore_count--; + + /* Restore interrupts. */ + TX_RESTORE + } + + /* Determine if the request specifies suspension. */ + else if (wait_option != TX_NO_WAIT) + { + + /* Determine if the preempt disable flag is non-zero. */ + if (_tx_thread_preempt_disable != ((UINT) 0)) + { + + /* Restore interrupts. */ + TX_RESTORE + + /* Suspension is not allowed if the preempt disable flag is non-zero at this point - return error completion. */ + status = TX_NO_INSTANCE; + } + else + { + + /* Prepare for suspension of this thread. */ + +#ifdef TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO + + /* Increment the total semaphore suspensions counter. */ + _tx_semaphore_performance_suspension_count++; + + /* Increment the number of suspensions on this semaphore. */ + semaphore_ptr -> tx_semaphore_performance_suspension_count++; +#endif + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr) + + /* Setup cleanup routine pointer. */ + thread_ptr -> tx_thread_suspend_cleanup = &(_tx_semaphore_cleanup); + + /* Setup cleanup information, i.e. this semaphore control + block. */ + thread_ptr -> tx_thread_suspend_control_block = (VOID *) semaphore_ptr; + +#ifndef TX_NOT_INTERRUPTABLE + + /* Increment the suspension sequence number, which is used to identify + this suspension event. */ + thread_ptr -> tx_thread_suspension_sequence++; +#endif + + /* Setup suspension list. */ + if (semaphore_ptr -> tx_semaphore_suspended_count == TX_NO_SUSPENSIONS) + { + + /* No other threads are suspended. Setup the head pointer and + just setup this threads pointers to itself. */ + semaphore_ptr -> tx_semaphore_suspension_list = thread_ptr; + thread_ptr -> tx_thread_suspended_next = thread_ptr; + thread_ptr -> tx_thread_suspended_previous = thread_ptr; + } + else + { + + /* This list is not NULL, add current thread to the end. */ + next_thread = semaphore_ptr -> tx_semaphore_suspension_list; + thread_ptr -> tx_thread_suspended_next = next_thread; + previous_thread = next_thread -> tx_thread_suspended_previous; + thread_ptr -> tx_thread_suspended_previous = previous_thread; + previous_thread -> tx_thread_suspended_next = thread_ptr; + next_thread -> tx_thread_suspended_previous = thread_ptr; + } + + /* Increment the number of suspensions. */ + semaphore_ptr -> tx_semaphore_suspended_count++; + + /* Set the state to suspended. */ + thread_ptr -> tx_thread_state = TX_SEMAPHORE_SUSP; + +#ifdef TX_NOT_INTERRUPTABLE + + /* Call actual non-interruptable thread suspension routine. */ + _tx_thread_system_ni_suspend(thread_ptr, wait_option); + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Set the suspending flag. */ + thread_ptr -> tx_thread_suspending = TX_TRUE; + + /* Setup the timeout period. */ + thread_ptr -> tx_thread_timer.tx_timer_internal_remaining_ticks = wait_option; + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Call actual thread suspension routine. */ + _tx_thread_system_suspend(thread_ptr); +#endif + + /* Return the completion status. */ + status = thread_ptr -> tx_thread_suspend_status; + } + } + else + { + + /* Restore interrupts. */ + TX_RESTORE + + /* Immediate return, return error completion. */ + status = TX_NO_INSTANCE; + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/tx_semaphore_info_get.c b/common_smp/src/tx_semaphore_info_get.c new file mode 100644 index 00000000..42fb990d --- /dev/null +++ b/common_smp/src/tx_semaphore_info_get.c @@ -0,0 +1,139 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Semaphore */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_semaphore.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_semaphore_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves information from the specified semaphore. */ +/* */ +/* INPUT */ +/* */ +/* semaphore_ptr Pointer to semaphore control block*/ +/* name Destination for the semaphore name*/ +/* current_value Destination for current value of */ +/* the semaphore */ +/* first_suspended Destination for pointer of first */ +/* thread suspended on semaphore */ +/* suspended_count Destination for suspended count */ +/* next_semaphore Destination for pointer to next */ +/* semaphore on the created list */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_semaphore_info_get(TX_SEMAPHORE *semaphore_ptr, CHAR **name, ULONG *current_value, + TX_THREAD **first_suspended, ULONG *suspended_count, + TX_SEMAPHORE **next_semaphore) +{ + +TX_INTERRUPT_SAVE_AREA + + + /* Disable interrupts. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_SEMAPHORE_INFO_GET, semaphore_ptr, 0, 0, 0, TX_TRACE_SEMAPHORE_EVENTS) + + /* Log this kernel call. */ + TX_EL_SEMAPHORE_INFO_GET_INSERT + + /* Retrieve all the pertinent information and return it in the supplied + destinations. */ + + /* Retrieve the name of the semaphore. */ + if (name != TX_NULL) + { + + *name = semaphore_ptr -> tx_semaphore_name; + } + + /* Retrieve the current value of the semaphore. */ + if (current_value != TX_NULL) + { + + *current_value = semaphore_ptr -> tx_semaphore_count; + } + + /* Retrieve the first thread suspended on this semaphore. */ + if (first_suspended != TX_NULL) + { + + *first_suspended = semaphore_ptr -> tx_semaphore_suspension_list; + } + + /* Retrieve the number of threads suspended on this semaphore. */ + if (suspended_count != TX_NULL) + { + + *suspended_count = (ULONG) semaphore_ptr -> tx_semaphore_suspended_count; + } + + /* Retrieve the pointer to the next semaphore created. */ + if (next_semaphore != TX_NULL) + { + + *next_semaphore = semaphore_ptr -> tx_semaphore_created_next; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return completion status. */ + return(TX_SUCCESS); +} + diff --git a/common_smp/src/tx_semaphore_initialize.c b/common_smp/src/tx_semaphore_initialize.c new file mode 100644 index 00000000..b86dfe02 --- /dev/null +++ b/common_smp/src/tx_semaphore_initialize.c @@ -0,0 +1,129 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Semaphore */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_semaphore.h" + + +#ifndef TX_INLINE_INITIALIZATION + +/* Locate semaphore component data in this file. */ + +/* Define the head pointer of the created semaphore list. */ + +TX_SEMAPHORE * _tx_semaphore_created_ptr; + + +/* Define the variable that holds the number of created semaphores. */ + +ULONG _tx_semaphore_created_count; + + +#ifdef TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO + +/* Define the total number of semaphore puts. */ + +ULONG _tx_semaphore_performance_put_count; + + +/* Define the total number of semaphore gets. */ + +ULONG _tx_semaphore_performance_get_count; + + +/* Define the total number of semaphore suspensions. */ + +ULONG _tx_semaphore_performance_suspension_count; + + +/* Define the total number of semaphore timeouts. */ + +ULONG _tx_semaphore_performance_timeout_count; + +#endif +#endif + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_semaphore_initialize PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes the various control data structures for */ +/* the semaphore component. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_high_level High level initialization */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_semaphore_initialize(VOID) +{ + +#ifndef TX_DISABLE_REDUNDANT_CLEARING + + /* Initialize the head pointer of the created semaphores list and the + number of semaphores created. */ + _tx_semaphore_created_ptr = TX_NULL; + _tx_semaphore_created_count = TX_EMPTY; + +#ifdef TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO + + /* Initialize semaphore performance counters. */ + _tx_semaphore_performance_put_count = ((ULONG) 0); + _tx_semaphore_performance_get_count = ((ULONG) 0); + _tx_semaphore_performance_suspension_count = ((ULONG) 0); + _tx_semaphore_performance_timeout_count = ((ULONG) 0); +#endif +#endif +} + diff --git a/common_smp/src/tx_semaphore_performance_info_get.c b/common_smp/src/tx_semaphore_performance_info_get.c new file mode 100644 index 00000000..7457ae89 --- /dev/null +++ b/common_smp/src/tx_semaphore_performance_info_get.c @@ -0,0 +1,201 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Semaphore */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_semaphore.h" +#ifdef TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO +#include "tx_trace.h" +#endif + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_semaphore_performance_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves performance information from the specified */ +/* semaphore. */ +/* */ +/* INPUT */ +/* */ +/* semaphore_ptr Pointer to semaphore control block*/ +/* puts Destination for the number of */ +/* puts on to this semaphore */ +/* gets Destination for the number of */ +/* gets on this semaphore */ +/* suspensions Destination for the number of */ +/* suspensions on this semaphore */ +/* timeouts Destination for number of timeouts*/ +/* on this semaphore */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_semaphore_performance_info_get(TX_SEMAPHORE *semaphore_ptr, ULONG *puts, ULONG *gets, + ULONG *suspensions, ULONG *timeouts) +{ + +#ifdef TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO + +TX_INTERRUPT_SAVE_AREA +UINT status; + + + /* Determine if this is a legal request. */ + if (semaphore_ptr == TX_NULL) + { + + /* Semaphore pointer is illegal, return error. */ + status = TX_PTR_ERROR; + } + + /* Determine if the semaphore ID is invalid. */ + else if (semaphore_ptr -> tx_semaphore_id != TX_SEMAPHORE_ID) + { + + /* Semaphore pointer is illegal, return error. */ + status = TX_PTR_ERROR; + } + else + { + + /* Disable interrupts. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_SEMAPHORE_PERFORMANCE_INFO_GET, semaphore_ptr, 0, 0, 0, TX_TRACE_SEMAPHORE_EVENTS) + + /* Log this kernel call. */ + TX_EL_SEMAPHORE_PERFORMANCE_INFO_GET_INSERT + + /* Retrieve all the pertinent information and return it in the supplied + destinations. */ + + /* Retrieve the number of puts on this semaphore. */ + if (puts != TX_NULL) + { + + *puts = semaphore_ptr -> tx_semaphore_performance_put_count; + } + + /* Retrieve the number of gets on this semaphore. */ + if (gets != TX_NULL) + { + + *gets = semaphore_ptr -> tx_semaphore_performance_get_count; + } + + /* Retrieve the number of suspensions on this semaphore. */ + if (suspensions != TX_NULL) + { + + *suspensions = semaphore_ptr -> tx_semaphore_performance_suspension_count; + } + + /* Retrieve the number of timeouts on this semaphore. */ + if (timeouts != TX_NULL) + { + + *timeouts = semaphore_ptr -> tx_semaphore_performance_timeout_count; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return successful completion. */ + status = TX_SUCCESS; + } +#else +UINT status; + + + /* Access input arguments just for the sake of lint, MISRA, etc. */ + if (semaphore_ptr != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (puts != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (gets != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (suspensions != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (timeouts != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } +#endif + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/tx_semaphore_performance_system_info_get.c b/common_smp/src/tx_semaphore_performance_system_info_get.c new file mode 100644 index 00000000..c1fe425c --- /dev/null +++ b/common_smp/src/tx_semaphore_performance_system_info_get.c @@ -0,0 +1,174 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Semaphore */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_semaphore.h" +#ifdef TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO +#include "tx_trace.h" +#endif + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_semaphore_performance_system_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves system semaphore performance information. */ +/* */ +/* INPUT */ +/* */ +/* puts Destination for total number of */ +/* semaphore puts */ +/* gets Destination for total number of */ +/* semaphore gets */ +/* suspensions Destination for total number of */ +/* semaphore suspensions */ +/* timeouts Destination for total number of */ +/* timeouts */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_semaphore_performance_system_info_get(ULONG *puts, ULONG *gets, ULONG *suspensions, ULONG *timeouts) +{ + +#ifdef TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO + +TX_INTERRUPT_SAVE_AREA + + + /* Disable interrupts. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_SEMAPHORE__PERFORMANCE_SYSTEM_INFO_GET, 0, 0, 0, 0, TX_TRACE_SEMAPHORE_EVENTS) + + /* Log this kernel call. */ + TX_EL_SEMAPHORE_PERFORMANCE_SYSTEM_INFO_GET_INSERT + + /* Retrieve all the pertinent information and return it in the supplied + destinations. */ + + /* Retrieve the total number of semaphore puts. */ + if (puts != TX_NULL) + { + + *puts = _tx_semaphore_performance_put_count; + } + + /* Retrieve the total number of semaphore gets. */ + if (gets != TX_NULL) + { + + *gets = _tx_semaphore_performance_get_count; + } + + /* Retrieve the total number of semaphore suspensions. */ + if (suspensions != TX_NULL) + { + + *suspensions = _tx_semaphore_performance_suspension_count; + } + + /* Retrieve the total number of semaphore timeouts. */ + if (timeouts != TX_NULL) + { + + *timeouts = _tx_semaphore_performance_timeout_count; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return completion status. */ + return(TX_SUCCESS); + +#else + +UINT status; + + + /* Access input arguments just for the sake of lint, MISRA, etc. */ + if (puts != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (gets != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (suspensions != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (timeouts != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + + /* Return completion status. */ + return(status); +#endif +} + diff --git a/common_smp/src/tx_semaphore_prioritize.c b/common_smp/src/tx_semaphore_prioritize.c new file mode 100644 index 00000000..41e60988 --- /dev/null +++ b/common_smp/src/tx_semaphore_prioritize.c @@ -0,0 +1,251 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Semaphore */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_thread.h" +#include "tx_semaphore.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_semaphore_prioritize PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function places the highest priority suspended thread at the */ +/* front of the suspension list. All other threads remain in the same */ +/* FIFO suspension order. */ +/* */ +/* INPUT */ +/* */ +/* semaphore_ptr Pointer to semaphore control block*/ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_system_preempt_check Check for preemption */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_semaphore_prioritize(TX_SEMAPHORE *semaphore_ptr) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_THREAD *thread_ptr; +TX_THREAD *priority_thread_ptr; +TX_THREAD *head_ptr; +UINT suspended_count; +TX_THREAD *next_thread; +TX_THREAD *previous_thread; +UINT list_changed; + + + /* Disable interrupts. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_SEMAPHORE_PRIORITIZE, semaphore_ptr, semaphore_ptr -> tx_semaphore_suspended_count, TX_POINTER_TO_ULONG_CONVERT(&suspended_count), 0, TX_TRACE_SEMAPHORE_EVENTS) + + /* Log this kernel call. */ + TX_EL_SEMAPHORE_PRIORITIZE_INSERT + + /* Pickup the suspended count. */ + suspended_count = semaphore_ptr -> tx_semaphore_suspended_count; + + /* Determine if there are fewer than 2 suspended threads. */ + if (suspended_count < ((UINT) 2)) + { + + /* Restore interrupts. */ + TX_RESTORE + } + + /* Determine if there how many threads are suspended on this semaphore. */ + else if (suspended_count == ((UINT) 2)) + { + + /* Pickup the head pointer and the next pointer. */ + head_ptr = semaphore_ptr -> tx_semaphore_suspension_list; + next_thread = head_ptr -> tx_thread_suspended_next; + + /* Determine if the next suspended thread has a higher priority. */ + if ((next_thread -> tx_thread_priority) < (head_ptr -> tx_thread_priority)) + { + + /* Yes, move the list head to the next thread. */ + semaphore_ptr -> tx_semaphore_suspension_list = next_thread; + } + + /* Restore interrupts. */ + TX_RESTORE + } + else + { + + /* Remember the suspension count and head pointer. */ + head_ptr = semaphore_ptr -> tx_semaphore_suspension_list; + + /* Default the highest priority thread to the thread at the front of the list. */ + priority_thread_ptr = head_ptr; + + /* Setup search pointer. */ + thread_ptr = priority_thread_ptr -> tx_thread_suspended_next; + + /* Disable preemption. */ + _tx_thread_preempt_disable++; + + /* Set the list changed flag to false. */ + list_changed = TX_FALSE; + + /* Search through the list to find the highest priority thread. */ + do + { + + /* Is the current thread higher priority? */ + if (thread_ptr -> tx_thread_priority < priority_thread_ptr -> tx_thread_priority) + { + + /* Yes, remember that this thread is the highest priority. */ + priority_thread_ptr = thread_ptr; + } + + /* Restore interrupts temporarily. */ + TX_RESTORE + + /* Disable interrupts again. */ + TX_DISABLE + + /* Determine if any changes to the list have occurred while + interrupts were enabled. */ + + /* Is the list head the same? */ + if (head_ptr != semaphore_ptr -> tx_semaphore_suspension_list) + { + + /* The list head has changed, set the list changed flag. */ + list_changed = TX_TRUE; + } + else + { + + /* Is the suspended count the same? */ + if (suspended_count != semaphore_ptr -> tx_semaphore_suspended_count) + { + + /* The list head has changed, set the list changed flag. */ + list_changed = TX_TRUE; + } + } + + /* Determine if the list has changed. */ + if (list_changed == TX_FALSE) + { + + /* Yes, everything is the same... move the thread pointer to the next thread. */ + thread_ptr = thread_ptr -> tx_thread_suspended_next; + } + else + { + + /* No, the list is been modified so we need to start the search over. */ + + /* Save the suspension count and head pointer. */ + head_ptr = semaphore_ptr -> tx_semaphore_suspension_list; + suspended_count = semaphore_ptr -> tx_semaphore_suspended_count; + + /* Default the highest priority thread to the thread at the front of the list. */ + priority_thread_ptr = head_ptr; + + /* Setup search pointer. */ + thread_ptr = priority_thread_ptr -> tx_thread_suspended_next; + + /* Reset the list changed flag. */ + list_changed = TX_FALSE; + } + + } while (thread_ptr != head_ptr); + + /* Release preemption. */ + _tx_thread_preempt_disable--; + + /* Now determine if the highest priority thread is at the front + of the list. */ + if (priority_thread_ptr != head_ptr) + { + + /* No, we need to move the highest priority suspended thread to the + front of the list. */ + + /* First, remove the highest priority thread by updating the + adjacent suspended threads. */ + next_thread = priority_thread_ptr -> tx_thread_suspended_next; + previous_thread = priority_thread_ptr -> tx_thread_suspended_previous; + next_thread -> tx_thread_suspended_previous = previous_thread; + previous_thread -> tx_thread_suspended_next = next_thread; + + /* Now, link the highest priority thread at the front of the list. */ + previous_thread = head_ptr -> tx_thread_suspended_previous; + priority_thread_ptr -> tx_thread_suspended_next = head_ptr; + priority_thread_ptr -> tx_thread_suspended_previous = previous_thread; + previous_thread -> tx_thread_suspended_next = priority_thread_ptr; + head_ptr -> tx_thread_suspended_previous = priority_thread_ptr; + + /* Move the list head pointer to the highest priority suspended thread. */ + semaphore_ptr -> tx_semaphore_suspension_list = priority_thread_ptr; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Check for preemption. */ + _tx_thread_system_preempt_check(); + } + + /* Return completion status. */ + return(TX_SUCCESS); +} + diff --git a/common_smp/src/tx_semaphore_put.c b/common_smp/src/tx_semaphore_put.c new file mode 100644 index 00000000..b2b37568 --- /dev/null +++ b/common_smp/src/tx_semaphore_put.c @@ -0,0 +1,222 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Semaphore */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_thread.h" +#include "tx_semaphore.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_semaphore_put PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function puts an instance into the specified counting */ +/* semaphore. */ +/* */ +/* INPUT */ +/* */ +/* semaphore_ptr Pointer to semaphore control block*/ +/* */ +/* OUTPUT */ +/* */ +/* TX_SUCCESS Success completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_system_resume Resume thread service */ +/* _tx_thread_system_ni_resume Non-interruptable resume thread */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_semaphore_put(TX_SEMAPHORE *semaphore_ptr) +{ + +TX_INTERRUPT_SAVE_AREA + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS +VOID (*semaphore_put_notify)(struct TX_SEMAPHORE_STRUCT *notify_semaphore_ptr); +#endif + +TX_THREAD *thread_ptr; +UINT suspended_count; +TX_THREAD *next_thread; +TX_THREAD *previous_thread; + + + /* Disable interrupts to put an instance back to the semaphore. */ + TX_DISABLE + +#ifdef TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO + + /* Increment the total semaphore put counter. */ + _tx_semaphore_performance_put_count++; + + /* Increment the number of puts on this semaphore. */ + semaphore_ptr -> tx_semaphore_performance_put_count++; +#endif + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_SEMAPHORE_PUT, semaphore_ptr, semaphore_ptr -> tx_semaphore_count, semaphore_ptr -> tx_semaphore_suspended_count, TX_POINTER_TO_ULONG_CONVERT(&thread_ptr), TX_TRACE_SEMAPHORE_EVENTS) + + /* Log this kernel call. */ + TX_EL_SEMAPHORE_PUT_INSERT + + /* Pickup the number of suspended threads. */ + suspended_count = semaphore_ptr -> tx_semaphore_suspended_count; + + /* Determine if there are any threads suspended on the semaphore. */ + if (suspended_count == TX_NO_SUSPENSIONS) + { + + /* Increment the semaphore count. */ + semaphore_ptr -> tx_semaphore_count++; + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the application notify function. */ + semaphore_put_notify = semaphore_ptr -> tx_semaphore_put_notify; +#endif + + /* Restore interrupts. */ + TX_RESTORE + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Determine if notification is required. */ + if (semaphore_put_notify != TX_NULL) + { + + /* Yes, call the appropriate notify callback function. */ + (semaphore_put_notify)(semaphore_ptr); + } +#endif + } + else + { + + /* A thread is suspended on this semaphore. */ + + /* Pickup the pointer to the first suspended thread. */ + thread_ptr = semaphore_ptr -> tx_semaphore_suspension_list; + + /* Remove the suspended thread from the list. */ + + /* See if this is the only suspended thread on the list. */ + suspended_count--; + if (suspended_count == TX_NO_SUSPENSIONS) + { + + /* Yes, the only suspended thread. */ + + /* Update the head pointer. */ + semaphore_ptr -> tx_semaphore_suspension_list = TX_NULL; + } + else + { + + /* At least one more thread is on the same expiration list. */ + + /* Update the list head pointer. */ + next_thread = thread_ptr -> tx_thread_suspended_next; + semaphore_ptr -> tx_semaphore_suspension_list = next_thread; + + /* Update the links of the adjacent threads. */ + previous_thread = thread_ptr -> tx_thread_suspended_previous; + next_thread -> tx_thread_suspended_previous = previous_thread; + previous_thread -> tx_thread_suspended_next = next_thread; + } + + /* Decrement the suspension count. */ + semaphore_ptr -> tx_semaphore_suspended_count = suspended_count; + + /* Prepare for resumption of the first thread. */ + + /* Clear cleanup routine to avoid timeout. */ + thread_ptr -> tx_thread_suspend_cleanup = TX_NULL; + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the application notify function. */ + semaphore_put_notify = semaphore_ptr -> tx_semaphore_put_notify; +#endif + + /* Put return status into the thread control block. */ + thread_ptr -> tx_thread_suspend_status = TX_SUCCESS; + +#ifdef TX_NOT_INTERRUPTABLE + + /* Resume the thread! */ + _tx_thread_system_ni_resume(thread_ptr); + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Resume thread. */ + _tx_thread_system_resume(thread_ptr); +#endif + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Determine if notification is required. */ + if (semaphore_put_notify != TX_NULL) + { + + /* Yes, call the appropriate notify callback function. */ + (semaphore_put_notify)(semaphore_ptr); + } +#endif + } + + /* Return successful completion. */ + return(TX_SUCCESS); +} + diff --git a/common_smp/src/tx_semaphore_put_notify.c b/common_smp/src/tx_semaphore_put_notify.c new file mode 100644 index 00000000..f2918aa0 --- /dev/null +++ b/common_smp/src/tx_semaphore_put_notify.c @@ -0,0 +1,107 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Semaphore */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_semaphore.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_semaphore_put_notify PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application callback function that is */ +/* called whenever the this semaphore is put. */ +/* */ +/* INPUT */ +/* */ +/* semaphore_ptr Pointer to semaphore */ +/* semaphore_put_notify Application callback function */ +/* (TX_NULL disables notify) */ +/* */ +/* OUTPUT */ +/* */ +/* status Service return status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_semaphore_put_notify(TX_SEMAPHORE *semaphore_ptr, VOID (*semaphore_put_notify)(TX_SEMAPHORE *notify_semaphore_ptr)) +{ + +#ifdef TX_DISABLE_NOTIFY_CALLBACKS + + TX_SEMAPHORE_NOT_USED(semaphore_ptr); + TX_SEMAPHORE_PUT_NOTIFY_NOT_USED(semaphore_put_notify); + + /* Feature is not enabled, return error. */ + return(TX_FEATURE_NOT_ENABLED); +#else + +TX_INTERRUPT_SAVE_AREA + + + /* Disable interrupts. */ + TX_DISABLE + + /* Make entry in event log. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_SEMAPHORE_PUT_NOTIFY, semaphore_ptr, 0, 0, 0, TX_TRACE_SEMAPHORE_EVENTS) + + /* Make entry in event log. */ + TX_EL_SEMAPHORE_PUT_NOTIFY_INSERT + + /* Setup semaphore put notification callback function. */ + semaphore_ptr -> tx_semaphore_put_notify = semaphore_put_notify; + + /* Restore interrupts. */ + TX_RESTORE + + /* Return success to caller. */ + return(TX_SUCCESS); +#endif +} + diff --git a/common_smp/src/tx_thread_create.c b/common_smp/src/tx_thread_create.c new file mode 100644 index 00000000..f92e8381 --- /dev/null +++ b/common_smp/src/tx_thread_create.c @@ -0,0 +1,346 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_thread.h" +#include "tx_initialize.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_create PORTABLE SMP */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates a thread and places it on the list of created */ +/* threads. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* name_ptr Pointer to thread name string */ +/* entry_function Entry function of the thread */ +/* entry_input 32-bit input value to thread */ +/* stack_start Pointer to start of stack */ +/* stack_size Stack size in bytes */ +/* priority Priority of thread (0-31) */ +/* preempt_threshold Preemption threshold */ +/* time_slice Thread time-slice value */ +/* auto_start Automatic start selection */ +/* */ +/* OUTPUT */ +/* */ +/* return status Thread create return status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_smp_rebalance_execute_list Rebalance execution list */ +/* _tx_thread_stack_build Build initial thread stack */ +/* _tx_thread_system_resume Resume automatic start thread */ +/* _tx_thread_system_ni_resume Noninterruptable resume thread*/ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* _tx_timer_initialize Create system timer thread */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_thread_create(TX_THREAD *thread_ptr, CHAR *name_ptr, VOID (*entry_function)(ULONG id), ULONG entry_input, + VOID *stack_start, ULONG stack_size, UINT priority, UINT preempt_threshold, + ULONG time_slice, UINT auto_start) +{ + +TX_INTERRUPT_SAVE_AREA + +UINT core_index; +TX_THREAD *next_thread; +TX_THREAD *previous_thread; +UCHAR *temp_ptr; +#ifdef TX_ENABLE_STACK_CHECKING +ULONG new_stack_start; +ULONG updated_stack_start; +#endif + + +#ifndef TX_DISABLE_STACK_FILLING + + /* Set the thread stack to a pattern prior to creating the initial + stack frame. This pattern is used by the stack checking routines + to see how much has been used. */ + TX_MEMSET(stack_start, ((UCHAR) TX_STACK_FILL), stack_size); +#endif + +#ifdef TX_ENABLE_STACK_CHECKING + + /* Ensure that there are two ULONG of 0xEF patterns at the top and + bottom of the thread's stack. This will be used to check for stack + overflow conditions during run-time. */ + stack_size = ((stack_size/(sizeof(ULONG))) * (sizeof(ULONG))) - (sizeof(ULONG)); + + /* Ensure the starting stack address is evenly aligned. */ + new_stack_start = TX_POINTER_TO_ULONG_CONVERT(stack_start); + updated_stack_start = ((((ULONG) new_stack_start) + ((sizeof(ULONG)) - ((ULONG) 1)) ) & (~((sizeof(ULONG)) - ((ULONG) 1)))); + + /* Determine if the starting stack address is different. */ + if (new_stack_start != updated_stack_start) + { + + /* Yes, subtract another ULONG from the size to avoid going past the stack area. */ + stack_size = stack_size - (sizeof(ULONG)); + } + + /* Update the starting stack pointer. */ + stack_start = TX_ULONG_TO_POINTER_CONVERT(updated_stack_start); +#endif + + /* Prepare the thread control block prior to placing it on the created + list. */ + + /* Initialize thread control block to all zeros. */ + TX_MEMSET(thread_ptr, 0, (sizeof(TX_THREAD))); + + /* Place the supplied parameters into the thread's control block. */ + thread_ptr -> tx_thread_name = name_ptr; + thread_ptr -> tx_thread_entry = entry_function; + thread_ptr -> tx_thread_entry_parameter = entry_input; + thread_ptr -> tx_thread_stack_start = stack_start; + thread_ptr -> tx_thread_stack_size = stack_size; + thread_ptr -> tx_thread_priority = priority; + thread_ptr -> tx_thread_user_priority = priority; + thread_ptr -> tx_thread_time_slice = time_slice; + thread_ptr -> tx_thread_new_time_slice = time_slice; + thread_ptr -> tx_thread_inherit_priority = ((UINT) TX_MAX_PRIORITIES); + thread_ptr -> tx_thread_smp_core_executing = ((UINT) TX_THREAD_SMP_MAX_CORES); + thread_ptr -> tx_thread_smp_cores_excluded = ((ULONG) 0); +#ifndef TX_THREAD_SMP_DYNAMIC_CORE_MAX + thread_ptr -> tx_thread_smp_cores_allowed = ((ULONG) TX_THREAD_SMP_CORE_MASK); +#else + thread_ptr -> tx_thread_smp_cores_allowed = (((ULONG) 1) << _tx_thread_smp_max_cores) - 1; +#endif + +#ifdef TX_THREAD_SMP_ONLY_CORE_0_DEFAULT + + /* Default thread creation such that core0 is the only allowed core for execution, i.e., bit 1 is set to exclude core1. */ + thread_ptr -> tx_thread_smp_cores_excluded = (TX_THREAD_SMP_CORE_MASK & 0xFFFFFFFE); + thread_ptr -> tx_thread_smp_cores_allowed = 1; + + /* Default the timers to run on core 0 as well. */ + thread_ptr -> tx_thread_timer.tx_timer_internal_smp_cores_excluded = (TX_THREAD_SMP_CORE_MASK & 0xFFFFFFFE); + + /* Default the mapped to 0 too. */ + thread_ptr -> tx_thread_smp_core_mapped = 0; +#endif + + /* Calculate the end of the thread's stack area. */ + temp_ptr = TX_VOID_TO_UCHAR_POINTER_CONVERT(stack_start); + temp_ptr = (TX_UCHAR_POINTER_ADD(temp_ptr, (stack_size - ((ULONG) 1)))); + thread_ptr -> tx_thread_stack_end = TX_UCHAR_TO_VOID_POINTER_CONVERT(temp_ptr); + + +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD + + /* Preemption-threshold is enabled, setup accordingly. */ + thread_ptr -> tx_thread_preempt_threshold = preempt_threshold; + thread_ptr -> tx_thread_user_preempt_threshold = preempt_threshold; +#else + + /* Preemption-threshold is disabled, determine if preemption-threshold was required. */ + if (priority != preempt_threshold) + { + + /* Preemption-threshold specified. Since specific preemption-threshold is not supported, + disable all preemption. */ + thread_ptr -> tx_thread_preempt_threshold = ((UINT) 0); + thread_ptr -> tx_thread_user_preempt_threshold = ((UINT) 0); + } + else + { + + /* Preemption-threshold is not specified, just setup with the priority. */ + thread_ptr -> tx_thread_preempt_threshold = priority; + thread_ptr -> tx_thread_user_preempt_threshold = priority; + } +#endif + + /* Now fill in the values that are required for thread initialization. */ + thread_ptr -> tx_thread_state = TX_SUSPENDED; + + /* Setup the necessary fields in the thread timer block. */ + TX_THREAD_CREATE_TIMEOUT_SETUP(thread_ptr) + + /* Perform any additional thread setup activities for tool or user purpose. */ + TX_THREAD_CREATE_INTERNAL_EXTENSION(thread_ptr) + + /* Call the target specific stack frame building routine to build the + thread's initial stack and to setup the actual stack pointer in the + control block. */ + _tx_thread_stack_build(thread_ptr, _tx_thread_shell_entry); + +#ifdef TX_ENABLE_STACK_CHECKING + + /* Setup the highest usage stack pointer. */ + thread_ptr -> tx_thread_stack_highest_ptr = thread_ptr -> tx_thread_stack_ptr; +#endif + + /* Prepare to make this thread a member of the created thread list. */ + TX_DISABLE + + /* Load the thread ID field in the thread control block. */ + thread_ptr -> tx_thread_id = TX_THREAD_ID; + + /* Place the thread on the list of created threads. First, + check for an empty list. */ + if (_tx_thread_created_count == TX_EMPTY) + { + + /* The created thread list is empty. Add thread to empty list. */ + _tx_thread_created_ptr = thread_ptr; + thread_ptr -> tx_thread_created_next = thread_ptr; + thread_ptr -> tx_thread_created_previous = thread_ptr; + } + else + { + + /* This list is not NULL, add to the end of the list. */ + next_thread = _tx_thread_created_ptr; + previous_thread = next_thread -> tx_thread_created_previous; + + /* Place the new thread in the list. */ + next_thread -> tx_thread_created_previous = thread_ptr; + previous_thread -> tx_thread_created_next = thread_ptr; + + /* Setup this thread's created links. */ + thread_ptr -> tx_thread_created_previous = previous_thread; + thread_ptr -> tx_thread_created_next = next_thread; + } + + /* Increment the thread created count. */ + _tx_thread_created_count++; + + /* If trace is enabled, register this object. */ + TX_TRACE_OBJECT_REGISTER(TX_TRACE_OBJECT_TYPE_THREAD, thread_ptr, name_ptr, TX_POINTER_TO_ULONG_CONVERT(stack_start), stack_size) + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_CREATE, thread_ptr, priority, TX_POINTER_TO_ULONG_CONVERT(stack_start), stack_size, TX_TRACE_THREAD_EVENTS) + + /* Register thread in the thread array structure. */ + TX_EL_THREAD_REGISTER(thread_ptr) + + /* Log this kernel call. */ + TX_EL_THREAD_CREATE_INSERT + + /* Determine if an automatic start was requested. If so, call the resume + thread function and then check for a preemption condition. */ + if (auto_start == TX_AUTO_START) + { + +#ifdef TX_NOT_INTERRUPTABLE + + /* Perform any additional activities for tool or user purpose. */ + TX_THREAD_CREATE_EXTENSION(thread_ptr) + + /* Resume the thread! */ + _tx_thread_system_ni_resume(thread_ptr); + +#else + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Restore previous interrupt posture. */ + TX_RESTORE + + /* Perform any additional activities for tool or user purpose. */ + TX_THREAD_CREATE_EXTENSION(thread_ptr) + + /* Call the resume thread function to make this thread ready. */ + _tx_thread_system_resume(thread_ptr); + + /* Disable interrupts again. */ + TX_DISABLE +#endif + + /* Determine if the execution list needs to be re-evaluated. */ + if (_tx_thread_smp_current_state_get() >= TX_INITIALIZE_IN_PROGRESS) + { + +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD + + /* Clear the preemption bit maps, since nothing has yet run during initialization. */ + TX_MEMSET(_tx_thread_preempted_maps, 0, sizeof(_tx_thread_preempted_maps)); +#if TX_MAX_PRIORITIES > 32 + _tx_thread_preempted_map_active = ((ULONG) 0); +#endif + + /* Clear the entry in the preempted thread list. */ + _tx_thread_preemption_threshold_list[priority] = TX_NULL; +#endif + + /* Set the pointer to the thread currently with preemption-threshold set to NULL. */ + _tx_thread_preemption__threshold_scheduled = TX_NULL; + +#ifdef TX_THREAD_SMP_DEBUG_ENABLE + + /* Debug entry. */ + _tx_thread_smp_debug_entry_insert(12, 0, thread_ptr); +#endif + + /* Get the core index. */ + core_index = TX_SMP_CORE_ID; + + /* Call the rebalance routine. This routine maps cores and ready threads. */ + _tx_thread_smp_rebalance_execute_list(core_index); + +#ifdef TX_THREAD_SMP_DEBUG_ENABLE + + /* Debug entry. */ + _tx_thread_smp_debug_entry_insert(13, 0, thread_ptr); +#endif + } + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Always return a success. */ + return(TX_SUCCESS); +} + diff --git a/common_smp/src/tx_thread_delete.c b/common_smp/src/tx_thread_delete.c new file mode 100644 index 00000000..1fcaa482 --- /dev/null +++ b/common_smp/src/tx_thread_delete.c @@ -0,0 +1,166 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_delete PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles application delete thread requests. The */ +/* thread to delete must be in a terminated or completed state, */ +/* otherwise this function just returns an error code. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread to suspend */ +/* */ +/* OUTPUT */ +/* */ +/* status Return completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_thread_delete(TX_THREAD *thread_ptr) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_THREAD *next_thread; +TX_THREAD *previous_thread; +UINT status; + + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Lockout interrupts while the thread is being deleted. */ + TX_DISABLE + + /* Check for proper status of this thread to delete. */ + if (thread_ptr -> tx_thread_state != TX_COMPLETED) + { + + /* Now check for terminated state. */ + if (thread_ptr -> tx_thread_state != TX_TERMINATED) + { + + /* Restore interrupts. */ + TX_RESTORE + + /* Thread not completed or terminated - return an error! */ + status = TX_DELETE_ERROR; + } + } + + /* Determine if the delete operation is okay. */ + if (status == TX_SUCCESS) + { + + /* Yes, continue with deleting the thread. */ + + /* Perform any additional activities for tool or user purpose. */ + TX_THREAD_DELETE_EXTENSION(thread_ptr) + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_DELETE, thread_ptr, TX_POINTER_TO_ULONG_CONVERT(&next_thread), 0, 0, TX_TRACE_THREAD_EVENTS) + + /* If trace is enabled, unregister this object. */ + TX_TRACE_OBJECT_UNREGISTER(thread_ptr) + + /* Log this kernel call. */ + TX_EL_THREAD_DELETE_INSERT + + /* Unregister thread in the thread array structure. */ + TX_EL_THREAD_UNREGISTER(thread_ptr) + + /* Clear the thread ID to make it invalid. */ + thread_ptr -> tx_thread_id = TX_CLEAR_ID; + + /* Decrement the number of created threads. */ + _tx_thread_created_count--; + + /* See if the thread is the only one on the list. */ + if (_tx_thread_created_count == TX_EMPTY) + { + + /* Only created thread, just set the created list to NULL. */ + _tx_thread_created_ptr = TX_NULL; + } + else + { + + /* Otherwise, not the only created thread, link-up the neighbors. */ + next_thread = thread_ptr -> tx_thread_created_next; + previous_thread = thread_ptr -> tx_thread_created_previous; + next_thread -> tx_thread_created_previous = previous_thread; + previous_thread -> tx_thread_created_next = next_thread; + + /* See if we have to update the created list head pointer. */ + if (_tx_thread_created_ptr == thread_ptr) + { + + /* Yes, move the head pointer to the next link. */ + _tx_thread_created_ptr = next_thread; + } + } + + /* Execute Port-Specific completion processing. If needed, it is typically defined in tx_port.h. */ + TX_THREAD_DELETE_PORT_COMPLETION(thread_ptr) + + /* Restore interrupts. */ + TX_RESTORE + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/tx_thread_entry_exit_notify.c b/common_smp/src/tx_thread_entry_exit_notify.c new file mode 100644 index 00000000..1625ba25 --- /dev/null +++ b/common_smp/src/tx_thread_entry_exit_notify.c @@ -0,0 +1,109 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_entry_exit_notify PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application entry/exit notification */ +/* callback routine for the application. Once registered, the callback */ +/* routine is called when the thread is initially entered and called */ +/* again when the thread completes or is terminated. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread */ +/* thread_entry_exit_notify Pointer to notify callback */ +/* function, TX_NULL to disable*/ +/* */ +/* OUTPUT */ +/* */ +/* status Service return status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_thread_entry_exit_notify(TX_THREAD *thread_ptr, VOID (*thread_entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT id)) +{ + +#ifdef TX_DISABLE_NOTIFY_CALLBACKS + + TX_THREAD_NOT_USED(thread_ptr); + TX_THREAD_ENTRY_EXIT_NOTIFY_NOT_USED(thread_entry_exit_notify); + + /* Feature is not enabled, return error. */ + return(TX_FEATURE_NOT_ENABLED); +#else + +TX_INTERRUPT_SAVE_AREA + + + /* Disable interrupts. */ + TX_DISABLE + + /* Make entry in event log. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_ENTRY_EXIT_NOTIFY, thread_ptr, thread_ptr -> tx_thread_state, 0, 0, TX_TRACE_THREAD_EVENTS) + + /* Make entry in event log. */ + TX_EL_THREAD_ENTRY_EXIT_NOTIFY_INSERT + + /* Setup thread entry/exit notification callback function. */ + thread_ptr -> tx_thread_entry_exit_notify = thread_entry_exit_notify; + + /* Restore interrupts. */ + TX_RESTORE + + /* Return success to caller. */ + return(TX_SUCCESS); +#endif +} + diff --git a/common_smp/src/tx_thread_identify.c b/common_smp/src/tx_thread_identify.c new file mode 100644 index 00000000..21116f4e --- /dev/null +++ b/common_smp/src/tx_thread_identify.c @@ -0,0 +1,103 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#ifdef TX_ENABLE_EVENT_TRACE +#include "tx_trace.h" +#endif + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_identify PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function returns the control block pointer of the currently */ +/* executing thread. If the return value is NULL, no thread is */ +/* executing. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD * Pointer to control block of */ +/* currently executing thread */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +TX_THREAD *_tx_thread_identify(VOID) +{ + +TX_THREAD *thread_ptr; + +TX_INTERRUPT_SAVE_AREA + + + /* Disable interrupts to put the timer on the created list. */ + TX_DISABLE + +#ifdef TX_ENABLE_EVENT_TRACE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_IDENTIFY, 0, 0, 0, 0, TX_TRACE_THREAD_EVENTS) +#endif + + /* Log this kernel call. */ + TX_EL_THREAD_IDENTIFY_INSERT + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr) + + /* Restore interrupts. */ + TX_RESTORE + + /* Return the current thread pointer. */ + return(thread_ptr); +} + diff --git a/common_smp/src/tx_thread_info_get.c b/common_smp/src/tx_thread_info_get.c new file mode 100644 index 00000000..a4068920 --- /dev/null +++ b/common_smp/src/tx_thread_info_get.c @@ -0,0 +1,163 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves information from the specified thread. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control block */ +/* name Destination for the thread name */ +/* state Destination for thread state */ +/* run_count Destination for thread run count */ +/* priority Destination for thread priority */ +/* preemption_threshold Destination for thread preemption-*/ +/* threshold */ +/* time_slice Destination for thread time-slice */ +/* next_thread Destination for next created */ +/* thread */ +/* next_suspended_thread Destination for next suspended */ +/* thread */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_thread_info_get(TX_THREAD *thread_ptr, CHAR **name, UINT *state, ULONG *run_count, + UINT *priority, UINT *preemption_threshold, ULONG *time_slice, + TX_THREAD **next_thread, TX_THREAD **next_suspended_thread) +{ + +TX_INTERRUPT_SAVE_AREA + + + /* Disable interrupts. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_INFO_GET, thread_ptr, thread_ptr -> tx_thread_state, 0, 0, TX_TRACE_THREAD_EVENTS) + + /* Log this kernel call. */ + TX_EL_THREAD_INFO_GET_INSERT + + /* Retrieve all the pertinent information and return it in the supplied + destinations. */ + + /* Retrieve the name of the thread. */ + if (name != TX_NULL) + { + + *name = thread_ptr -> tx_thread_name; + } + + /* Pickup the thread's current state. */ + if (state != TX_NULL) + { + + *state = thread_ptr -> tx_thread_state; + } + + /* Pickup the number of times the thread has been scheduled. */ + if (run_count != TX_NULL) + { + + *run_count = thread_ptr -> tx_thread_run_count; + } + + /* Pickup the thread's priority. */ + if (priority != TX_NULL) + { + + *priority = thread_ptr -> tx_thread_user_priority; + } + + /* Pickup the thread's preemption-threshold. */ + if (preemption_threshold != TX_NULL) + { + + *preemption_threshold = thread_ptr -> tx_thread_user_preempt_threshold; + } + + /* Pickup the thread's current time-slice. */ + if (time_slice != TX_NULL) + { + + *time_slice = thread_ptr -> tx_thread_time_slice; + } + + /* Pickup the next created thread. */ + if (next_thread != TX_NULL) + { + + *next_thread = thread_ptr -> tx_thread_created_next; + } + + /* Pickup the next thread suspended. */ + if (next_suspended_thread != TX_NULL) + { + + *next_suspended_thread = thread_ptr -> tx_thread_suspended_next; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return completion status. */ + return(TX_SUCCESS); +} + diff --git a/common_smp/src/tx_thread_initialize.c b/common_smp/src/tx_thread_initialize.c new file mode 100644 index 00000000..7aa9b221 --- /dev/null +++ b/common_smp/src/tx_thread_initialize.c @@ -0,0 +1,483 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +#ifndef TX_MISRA_ENABLE +#define TX_THREAD_INIT +#endif + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" + + +/* Define the pointer that contains the system stack pointer. This is + utilized when control returns from a thread to the system to reset the + current stack. This is setup in the low-level initialization function. */ + +VOID * _tx_thread_system_stack_ptr[TX_THREAD_SMP_MAX_CORES]; + + +/* Define the current thread pointer. This variable points to the currently + executing thread. If this variable is NULL, no thread is executing. */ + +TX_THREAD * _tx_thread_current_ptr[TX_THREAD_SMP_MAX_CORES]; + + +/* Define the variable that holds the next thread to execute. It is important + to remember that this is not necessarily equal to the current thread + pointer. */ + +TX_THREAD * _tx_thread_execute_ptr[TX_THREAD_SMP_MAX_CORES]; + + +/* Define the ThreadX SMP scheduling and mapping data structures. */ + +TX_THREAD * _tx_thread_smp_schedule_list[TX_THREAD_SMP_MAX_CORES]; +ULONG _tx_thread_smp_reschedule_pending; +TX_THREAD_SMP_PROTECT _tx_thread_smp_protection; +volatile ULONG _tx_thread_smp_release_cores_flag; +ULONG _tx_thread_smp_system_error; +ULONG _tx_thread_smp_inter_core_interrupts[TX_THREAD_SMP_MAX_CORES]; + +ULONG _tx_thread_smp_protect_wait_list_size; +ULONG _tx_thread_smp_protect_wait_list[TX_THREAD_SMP_PROTECT_WAIT_LIST_SIZE]; +ULONG _tx_thread_smp_protect_wait_counts[TX_THREAD_SMP_MAX_CORES]; +ULONG _tx_thread_smp_protect_wait_list_lock_protect_in_force; +ULONG _tx_thread_smp_protect_wait_list_tail; +ULONG _tx_thread_smp_protect_wait_list_head; + + +/* Define logic for conditional dynamic maximum number of cores. */ + +#ifdef TX_THREAD_SMP_DYNAMIC_CORE_MAX + +ULONG _tx_thread_smp_max_cores; +ULONG _tx_thread_smp_detected_cores; + +#endif + + + +/* Define the head pointer of the created thread list. */ + +TX_THREAD * _tx_thread_created_ptr; + + +/* Define the variable that holds the number of created threads. */ + +ULONG _tx_thread_created_count; + + +/* Define the current state variable. When this value is 0, a thread + is executing or the system is idle. Other values indicate that + interrupt or initialization processing is active. This variable is + initialized to TX_INITIALIZE_IN_PROGRESS to indicate initialization is + active. */ + +volatile ULONG _tx_thread_system_state[TX_THREAD_SMP_MAX_CORES]; + + +/* Define the 32-bit priority bit-maps. There is one priority bit map for each + 32 priority levels supported. If only 32 priorities are supported there is + only one bit map. Each bit within a priority bit map represents that one + or more threads at the associated thread priority are ready. */ + +ULONG _tx_thread_priority_maps[TX_MAX_PRIORITIES/32]; + + +/* Define the priority map active bit map that specifies which of the previously + defined priority maps have something set. This is only necessary if more than + 32 priorities are supported. */ + +#if TX_MAX_PRIORITIES > 32 +ULONG _tx_thread_priority_map_active; +#endif + + +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD + +/* Define the 32-bit preempt priority bit maps. There is one preempt bit map + for each 32 priority levels supported. If only 32 priorities are supported + there is only one bit map. Each set set bit corresponds to a preempted priority + level that had preemption-threshold active to protect against preemption of a + range of relatively higher priority threads. */ + +ULONG _tx_thread_preempted_maps[TX_MAX_PRIORITIES/32]; + + +/* Define the preempt map active bit map that specifies which of the previously + defined preempt maps have something set. This is only necessary if more than + 32 priorities are supported. */ + +#if TX_MAX_PRIORITIES > 32 +ULONG _tx_thread_preempted_map_active; +#endif + + +/* Define the array that contains the thread at each priority level that was scheduled with + preemption-threshold enabled. This will be useful when returning from a nested + preemption-threshold condition. */ + +TX_THREAD *_tx_thread_preemption_threshold_list[TX_MAX_PRIORITIES]; + + +#endif + + +/* Define the last thread scheduled with preemption-threshold. When preemption-threshold is + disabled, a thread with preemption-threshold set disables all other threads from running. + Effectively, its preemption-threshold is 0. */ + +TX_THREAD *_tx_thread_preemption__threshold_scheduled; + + +/* Define the array of thread pointers. Each entry represents the threads that + are ready at that priority group. For example, index 10 in this array + represents the first thread ready at priority 10. If this entry is NULL, + no threads are ready at that priority. */ + +TX_THREAD * _tx_thread_priority_list[TX_MAX_PRIORITIES]; + + +/* Define the global preempt disable variable. If this is non-zero, preemption is + disabled. It is used internally by ThreadX to prevent preemption of a thread in + the middle of a service that is resuming or suspending another thread. */ + +volatile UINT _tx_thread_preempt_disable; + + +/* Define the global function pointer for mutex cleanup on thread completion or + termination. This pointer is setup during mutex initialization. */ + +VOID (*_tx_thread_mutex_release)(TX_THREAD *thread_ptr); + + +/* Define the global build options variable. This contains a bit map representing + how the ThreadX library was built. The following are the bit field definitions: + + Bit(s) Meaning + + 31 Reserved + 30 TX_NOT_INTERRUPTABLE defined + 29-24 Priority groups 1 -> 32 priorities + 2 -> 64 priorities + 3 -> 96 priorities + + ... + + 32 -> 1024 priorities + 23 TX_TIMER_PROCESS_IN_ISR defined + 22 TX_REACTIVATE_INLINE defined + 21 TX_DISABLE_STACK_FILLING defined + 20 TX_ENABLE_STACK_CHECKING defined + 19 TX_DISABLE_PREEMPTION_THRESHOLD defined + 18 TX_DISABLE_REDUNDANT_CLEARING defined + 17 TX_DISABLE_NOTIFY_CALLBACKS defined + 16 TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO defined + 15 TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO defined + 14 TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO defined + 13 TX_MUTEX_ENABLE_PERFORMANCE_INFO defined + 12 TX_QUEUE_ENABLE_PERFORMANCE_INFO defined + 11 TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO defined + 10 TX_THREAD_ENABLE_PERFORMANCE_INFO defined + 9 TX_TIMER_ENABLE_PERFORMANCE_INFO defined + 8 TX_ENABLE_EVENT_TRACE | TX_ENABLE_EVENT_LOGGING defined + 7 Reserved + 6 Reserved + 5 Reserved + 4 Reserved + 3 Reserved + 2 Reserved + 1 64-bit FPU Enabled + 0 Reserved */ + +ULONG _tx_build_options; + + +#ifdef TX_ENABLE_STACK_CHECKING + +/* Define the global function pointer for stack error handling. If a stack error is + detected and the application has registered a stack error handler, it will be + called via this function pointer. */ + +VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); + +#endif + +#ifdef TX_THREAD_ENABLE_PERFORMANCE_INFO + +/* Define the total number of thread resumptions. Each time a thread enters the + ready state this variable is incremented. */ + +ULONG _tx_thread_performance_resume_count; + + +/* Define the total number of thread suspensions. Each time a thread enters a + suspended state this variable is incremented. */ + +ULONG _tx_thread_performance_suspend_count; + + +/* Define the total number of solicited thread preemptions. Each time a thread is + preempted by directly calling a ThreadX service, this variable is incremented. */ + +ULONG _tx_thread_performance_solicited_preemption_count; + + +/* Define the total number of interrupt thread preemptions. Each time a thread is + preempted as a result of an ISR calling a ThreadX service, this variable is + incremented. */ + +ULONG _tx_thread_performance_interrupt_preemption_count; + + +/* Define the total number of priority inversions. Each time a thread is blocked by + a mutex owned by a lower-priority thread, this variable is incremented. */ + +ULONG _tx_thread_performance_priority_inversion_count; + + +/* Define the total number of time-slices. Each time a time-slice operation is + actually performed (another thread is setup for running) this variable is + incremented. */ + +ULONG _tx_thread_performance_time_slice_count; + + +/* Define the total number of thread relinquish operations. Each time a thread + relinquish operation is actually performed (another thread is setup for running) + this variable is incremented. */ + +ULONG _tx_thread_performance_relinquish_count; + + +/* Define the total number of thread timeouts. Each time a thread has a + timeout this variable is incremented. */ + +ULONG _tx_thread_performance_timeout_count; + + +/* Define the total number of thread wait aborts. Each time a thread's suspension + is lifted by the tx_thread_wait_abort call this variable is incremented. */ + +ULONG _tx_thread_performance_wait_abort_count; + + +/* Define the total number of idle system thread returns. Each time a thread returns to + an idle system (no other thread is ready to run) this variable is incremented. */ + +ULONG _tx_thread_performance_idle_return_count; + + +/* Define the total number of non-idle system thread returns. Each time a thread returns to + a non-idle system (another thread is ready to run) this variable is incremented. */ + +ULONG _tx_thread_performance_non_idle_return_count; + +#endif + + +/* Define special string. */ + +#ifndef TX_MISRA_ENABLE +const CHAR _tx_thread_special_string[] = + "G-ML-EL-ML-BL-DL-BL-GB-GL-M-D-DL-GZ-KH-EL-CM-NH-HA-GF-DD-JC-YZ-CT-AT-DW-USA-CA-SD-SDSU"; +#endif + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_initialize PORTABLE SMP */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes the various control data structures for */ +/* the thread control component. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_high_level High level initialization */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_initialize(VOID) +{ + + /* Note: the system stack pointer and the system state variables are + initialized by the low and high-level initialization functions, + respectively. */ + +#ifndef TX_DISABLE_REDUNDANT_CLEARING + + /* Set current thread pointer to NULL. */ + TX_THREAD_SET_CURRENT(0) + + /* Clear the execute thread list. */ + TX_MEMSET(&_tx_thread_execute_ptr[0], 0, (sizeof(_tx_thread_execute_ptr))); + + /* Initialize the priority information. */ + TX_MEMSET(&_tx_thread_priority_maps[0], 0, (sizeof(_tx_thread_priority_maps))); + +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD + TX_MEMSET(&_tx_thread_preempted_maps[0], 0, (sizeof(_tx_thread_preempted_maps))); + TX_MEMSET(&_tx_thread_preemption_threshold_list[0], 0, (sizeof(_tx_thread_preemption_threshold_list))); +#endif + _tx_thread_preemption__threshold_scheduled = TX_NULL; + + +#endif + +#ifndef TX_DISABLE_REDUNDANT_CLEARING + + /* Initialize the array of priority head pointers. */ + TX_MEMSET(&_tx_thread_priority_list[0], 0, (sizeof(_tx_thread_priority_list))); + + /* Initialize the head pointer of the created threads list and the + number of threads created. */ + _tx_thread_created_ptr = TX_NULL; + _tx_thread_created_count = TX_EMPTY; + + /* Clear the global preempt disable variable. */ + _tx_thread_preempt_disable = ((UINT) 0); + + /* Initialize the thread mutex release function pointer. */ + _tx_thread_mutex_release = TX_NULL; + +#ifdef TX_ENABLE_STACK_CHECKING + + /* Clear application registered stack error handler. */ + _tx_thread_application_stack_error_handler = TX_NULL; +#endif + +#ifdef TX_THREAD_ENABLE_PERFORMANCE_INFO + + /* Clear performance counters. */ + _tx_thread_performance_resume_count = ((ULONG) 0); + _tx_thread_performance_suspend_count = ((ULONG) 0); + _tx_thread_performance_solicited_preemption_count = ((ULONG) 0); + _tx_thread_performance_interrupt_preemption_count = ((ULONG) 0); + _tx_thread_performance_priority_inversion_count = ((ULONG) 0); + _tx_thread_performance_time_slice_count = ((ULONG) 0); + _tx_thread_performance_relinquish_count = ((ULONG) 0); + _tx_thread_performance_timeout_count = ((ULONG) 0); + _tx_thread_performance_wait_abort_count = ((ULONG) 0); + _tx_thread_performance_idle_return_count = ((ULONG) 0); + _tx_thread_performance_non_idle_return_count = ((ULONG) 0); +#endif +#endif + + /* Setup the build options flag. This is used to identify how the ThreadX library was constructed. */ + _tx_build_options = _tx_build_options + | (((ULONG) (TX_MAX_PRIORITIES/32)) << 24) +#ifdef TX_NOT_INTERRUPTABLE + | (((ULONG) 1) << 31) +#endif +#ifdef TX_INLINE_THREAD_RESUME_SUSPEND + | (((ULONG) 1) << 30) +#endif +#ifdef TX_TIMER_PROCESS_IN_ISR + | (((ULONG) 1) << 23) +#endif +#ifdef TX_REACTIVATE_INLINE + | (((ULONG) 1) << 22) +#endif +#ifdef TX_DISABLE_STACK_FILLING + | (((ULONG) 1) << 21) +#endif +#ifdef TX_ENABLE_STACK_CHECKING + | (((ULONG) 1) << 20) +#endif +#ifdef TX_DISABLE_PREEMPTION_THRESHOLD + | (((ULONG) 1) << 19) +#endif +#ifdef TX_DISABLE_REDUNDANT_CLEARING + | (((ULONG) 1) << 18) +#endif +#ifdef TX_DISABLE_NOTIFY_CALLBACKS + | (((ULONG) 1) << 17) +#endif +#ifdef TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO + | (((ULONG) 1) << 16) +#endif +#ifdef TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO + | (((ULONG) 1) << 15) +#endif +#ifdef TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO + | (((ULONG) 1) << 14) +#endif +#ifdef TX_MUTEX_ENABLE_PERFORMANCE_INFO + | (((ULONG) 1) << 13) +#endif +#ifdef TX_QUEUE_ENABLE_PERFORMANCE_INFO + | (((ULONG) 1) << 12) +#endif +#ifdef TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO + | (((ULONG) 1) << 11) +#endif +#ifdef TX_THREAD_ENABLE_PERFORMANCE_INFO + | (((ULONG) 1) << 10) +#endif +#ifdef TX_TIMER_ENABLE_PERFORMANCE_INFO + | (((ULONG) 1) << 9) +#endif +#ifdef TX_ENABLE_EVENT_TRACE + | (((ULONG) 1) << 8) +#endif +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + | (((ULONG) 1) << 7) +#endif +#if TX_PORT_SPECIFIC_BUILD_OPTIONS != 0 + | TX_PORT_SPECIFIC_BUILD_OPTIONS +#endif + ; +} + diff --git a/common_smp/src/tx_thread_performance_info_get.c b/common_smp/src/tx_thread_performance_info_get.c new file mode 100644 index 00000000..718fecf6 --- /dev/null +++ b/common_smp/src/tx_thread_performance_info_get.c @@ -0,0 +1,297 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#ifdef TX_THREAD_ENABLE_PERFORMANCE_INFO +#include "tx_trace.h" +#endif + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_performance_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves performance information from the specified */ +/* thread. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control block */ +/* resumptions Destination for number of times */ +/* thread was resumed */ +/* suspensions Destination for number of times */ +/* thread was suspended */ +/* solicited_preemptions Destination for number of times */ +/* thread called another service */ +/* that resulted in preemption */ +/* interrupt_preemptions Destination for number of times */ +/* thread was preempted by another */ +/* thread made ready in Interrupt */ +/* Service Routine (ISR) */ +/* priority_inversions Destination for number of times */ +/* a priority inversion was */ +/* detected for this thread */ +/* time_slices Destination for number of times */ +/* thread was time-sliced */ +/* relinquishes Destination for number of thread */ +/* relinquishes */ +/* timeouts Destination for number of timeouts*/ +/* for thread */ +/* wait_aborts Destination for number of wait */ +/* aborts for thread */ +/* last_preempted_by Destination for pointer of the */ +/* thread that last preempted this */ +/* thread */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_thread_performance_info_get(TX_THREAD *thread_ptr, ULONG *resumptions, ULONG *suspensions, + ULONG *solicited_preemptions, ULONG *interrupt_preemptions, ULONG *priority_inversions, + ULONG *time_slices, ULONG *relinquishes, ULONG *timeouts, ULONG *wait_aborts, TX_THREAD **last_preempted_by) +{ + +#ifdef TX_THREAD_ENABLE_PERFORMANCE_INFO + +TX_INTERRUPT_SAVE_AREA +UINT status; + + + /* Determine if this is a legal request. */ + if (thread_ptr == TX_NULL) + { + + /* Thread pointer is illegal, return error. */ + status = TX_PTR_ERROR; + } + + /* Determine if the thread ID is invalid. */ + else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) + { + + /* Thread pointer is illegal, return error. */ + status = TX_PTR_ERROR; + } + else + { + + /* Disable interrupts. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_PERFORMANCE_INFO_GET, thread_ptr, thread_ptr -> tx_thread_state, 0, 0, TX_TRACE_THREAD_EVENTS) + + /* Log this kernel call. */ + TX_EL_THREAD_PERFORMANCE_INFO_GET_INSERT + + /* Retrieve all the pertinent information and return it in the supplied + destinations. */ + + /* Retrieve number of resumptions for this thread. */ + if (resumptions != TX_NULL) + { + + *resumptions = thread_ptr -> tx_thread_performance_resume_count; + } + + /* Retrieve number of suspensions for this thread. */ + if (suspensions != TX_NULL) + { + + *suspensions = thread_ptr -> tx_thread_performance_suspend_count; + } + + /* Retrieve number of solicited preemptions for this thread. */ + if (solicited_preemptions != TX_NULL) + { + + *solicited_preemptions = thread_ptr -> tx_thread_performance_solicited_preemption_count; + } + + /* Retrieve number of interrupt preemptions for this thread. */ + if (interrupt_preemptions != TX_NULL) + { + + *interrupt_preemptions = thread_ptr -> tx_thread_performance_interrupt_preemption_count; + } + + /* Retrieve number of priority inversions for this thread. */ + if (priority_inversions != TX_NULL) + { + + *priority_inversions = thread_ptr -> tx_thread_performance_priority_inversion_count; + } + + /* Retrieve number of time-slices for this thread. */ + if (time_slices != TX_NULL) + { + + *time_slices = thread_ptr -> tx_thread_performance_time_slice_count; + } + + /* Retrieve number of relinquishes for this thread. */ + if (relinquishes != TX_NULL) + { + + *relinquishes = thread_ptr -> tx_thread_performance_relinquish_count; + } + + /* Retrieve number of timeouts for this thread. */ + if (timeouts != TX_NULL) + { + + *timeouts = thread_ptr -> tx_thread_performance_timeout_count; + } + + /* Retrieve number of wait aborts for this thread. */ + if (wait_aborts != TX_NULL) + { + + *wait_aborts = thread_ptr -> tx_thread_performance_wait_abort_count; + } + + /* Retrieve the pointer of the last thread that preempted this thread. */ + if (last_preempted_by != TX_NULL) + { + + *last_preempted_by = thread_ptr -> tx_thread_performance_last_preempting_thread; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return completion status. */ + status = TX_SUCCESS; + } +#else +UINT status; + + + /* Access input arguments just for the sake of lint, MISRA, etc. */ + if (thread_ptr != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (resumptions != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (suspensions != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (solicited_preemptions != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (interrupt_preemptions != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (priority_inversions != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (time_slices != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (relinquishes != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (timeouts != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (wait_aborts != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (last_preempted_by != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } +#endif + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/tx_thread_performance_system_info_get.c b/common_smp/src/tx_thread_performance_system_info_get.c new file mode 100644 index 00000000..8f4d776e --- /dev/null +++ b/common_smp/src/tx_thread_performance_system_info_get.c @@ -0,0 +1,287 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#ifdef TX_THREAD_ENABLE_PERFORMANCE_INFO +#include "tx_trace.h" +#endif + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_performance_system_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves thread system performance information. */ +/* */ +/* INPUT */ +/* */ +/* resumptions Destination for total number of */ +/* thread resumptions */ +/* suspensions Destination for total number of */ +/* thread suspensions */ +/* solicited_preemptions Destination for total number of */ +/* thread preemption from thread */ +/* API calls */ +/* interrupt_preemptions Destination for total number of */ +/* thread preemptions as a result */ +/* of threads made ready inside of */ +/* Interrupt Service Routines */ +/* priority_inversions Destination for total number of */ +/* priority inversions */ +/* time_slices Destination for total number of */ +/* time-slices */ +/* relinquishes Destination for total number of */ +/* relinquishes */ +/* timeouts Destination for total number of */ +/* timeouts */ +/* wait_aborts Destination for total number of */ +/* wait aborts */ +/* non_idle_returns Destination for total number of */ +/* times threads return when */ +/* another thread is ready */ +/* idle_returns Destination for total number of */ +/* times threads return when no */ +/* other thread is ready */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_thread_performance_system_info_get(ULONG *resumptions, ULONG *suspensions, + ULONG *solicited_preemptions, ULONG *interrupt_preemptions, ULONG *priority_inversions, + ULONG *time_slices, ULONG *relinquishes, ULONG *timeouts, ULONG *wait_aborts, + ULONG *non_idle_returns, ULONG *idle_returns) +{ + +#ifdef TX_THREAD_ENABLE_PERFORMANCE_INFO + +TX_INTERRUPT_SAVE_AREA + + + /* Disable interrupts. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_PERFORMANCE_SYSTEM_INFO_GET, 0, 0, 0, 0, TX_TRACE_THREAD_EVENTS) + + /* Log this kernel call. */ + TX_EL_THREAD_PERFORMANCE_SYSTEM_INFO_GET_INSERT + + /* Retrieve all the pertinent information and return it in the supplied + destinations. */ + + /* Retrieve total number of thread resumptions. */ + if (resumptions != TX_NULL) + { + + *resumptions = _tx_thread_performance_resume_count; + } + + /* Retrieve total number of thread suspensions. */ + if (suspensions != TX_NULL) + { + + *suspensions = _tx_thread_performance_suspend_count; + } + + /* Retrieve total number of solicited thread preemptions. */ + if (solicited_preemptions != TX_NULL) + { + + *solicited_preemptions = _tx_thread_performance_solicited_preemption_count; + } + + /* Retrieve total number of interrupt thread preemptions. */ + if (interrupt_preemptions != TX_NULL) + { + + *interrupt_preemptions = _tx_thread_performance_interrupt_preemption_count; + } + + /* Retrieve total number of thread priority inversions. */ + if (priority_inversions != TX_NULL) + { + + *priority_inversions = _tx_thread_performance_priority_inversion_count; + } + + /* Retrieve total number of thread time-slices. */ + if (time_slices != TX_NULL) + { + + *time_slices = _tx_thread_performance_time_slice_count; + } + + /* Retrieve total number of thread relinquishes. */ + if (relinquishes != TX_NULL) + { + + *relinquishes = _tx_thread_performance_relinquish_count; + } + + /* Retrieve total number of thread timeouts. */ + if (timeouts != TX_NULL) + { + + *timeouts = _tx_thread_performance_timeout_count; + } + + /* Retrieve total number of thread wait aborts. */ + if (wait_aborts != TX_NULL) + { + + *wait_aborts = _tx_thread_performance_wait_abort_count; + } + + /* Retrieve total number of thread non-idle system returns. */ + if (non_idle_returns != TX_NULL) + { + + *non_idle_returns = _tx_thread_performance_non_idle_return_count; + } + + /* Retrieve total number of thread idle system returns. */ + if (idle_returns != TX_NULL) + { + + *idle_returns = _tx_thread_performance_idle_return_count; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return completion status. */ + return(TX_SUCCESS); + +#else + +UINT status; + + + /* Access input arguments just for the sake of lint, MISRA, etc. */ + if (resumptions != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (suspensions != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (solicited_preemptions != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (interrupt_preemptions != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (priority_inversions != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (time_slices != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (relinquishes != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (timeouts != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (wait_aborts != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (non_idle_returns != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (idle_returns != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + + /* Return completion status. */ + return(status); +#endif +} + diff --git a/common_smp/src/tx_thread_preemption_change.c b/common_smp/src/tx_thread_preemption_change.c new file mode 100644 index 00000000..a43cb21f --- /dev/null +++ b/common_smp/src/tx_thread_preemption_change.c @@ -0,0 +1,298 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_initialize.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_preemption_change PORTABLE SMP */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes preemption-threshold change requests. The */ +/* previous preemption is returned to the caller. If the new request */ +/* allows a higher priority thread to execute, preemption takes place */ +/* inside of this function. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread */ +/* new_threshold New preemption-threshold */ +/* old_threshold Old preemption-threshold */ +/* */ +/* OUTPUT */ +/* */ +/* status Service return status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_smp_rebalance_execute_list Rebalance the execution list */ +/* _tx_thread_system_preempt_check Check for preemption */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_thread_preemption_change(TX_THREAD *thread_ptr, UINT new_threshold, UINT *old_threshold) +{ + +TX_INTERRUPT_SAVE_AREA + +UINT core_index; + +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD +ULONG priority_bit; +UINT base_priority; +UINT priority_bit_set; +ULONG priority_map; +UINT next_preempted; +TX_THREAD *preempted_thread; +#if TX_MAX_PRIORITIES > 32 +UINT map_index; +#endif +#endif +UINT status; + + +#ifdef TX_DISABLE_PREEMPTION_THRESHOLD + + /* Only allow 0 (disable all preemption) and returning preemption-threshold to the + current thread priority if preemption-threshold is disabled. All other threshold + values are converted to 0. */ + if (new_threshold < thread_ptr -> tx_thread_user_priority) + { + + /* Is the new threshold zero? */ + if (new_threshold != ((UINT) 0)) + { + + /* Convert the new threshold to disable all preemption, since preemption-threshold is + not supported. */ + new_threshold = ((UINT) 0); + } + } +#endif + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Lockout interrupts while the thread is being resumed. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_PREEMPTION_CHANGE, thread_ptr, new_threshold, thread_ptr -> tx_thread_preempt_threshold, thread_ptr -> tx_thread_state, TX_TRACE_THREAD_EVENTS) + + /* Log this kernel call. */ + TX_EL_THREAD_PREEMPTION_CHANGE_INSERT + + /* Determine if the new threshold is greater than the current user priority. */ + if (new_threshold > thread_ptr -> tx_thread_user_priority) + { + + /* Restore interrupts. */ + TX_RESTORE + + /* Return error. */ + status = TX_THRESH_ERROR; + } + else + { + + /* Return the user's preemption-threshold. */ + *old_threshold = thread_ptr -> tx_thread_user_preempt_threshold; + + /* Setup the new threshold. */ + thread_ptr -> tx_thread_user_preempt_threshold = new_threshold; + + /* Determine if the new threshold represents a higher priority than the priority inheritance threshold. */ + if (new_threshold < thread_ptr -> tx_thread_inherit_priority) + { + + /* Update the actual preemption-threshold with the new threshold. */ + thread_ptr -> tx_thread_preempt_threshold = new_threshold; + } + else + { + + /* Update the actual preemption-threshold with the priority inheritance. */ + thread_ptr -> tx_thread_preempt_threshold = thread_ptr -> tx_thread_inherit_priority; + } + + /* Determine if the thread is ready and scheduled. */ + if (thread_ptr -> tx_thread_state == TX_READY) + { + +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD + + /* Determine if the new threshold is the same as the priority. */ + if (thread_ptr -> tx_thread_user_priority == new_threshold) + { + + /* Yes, preemption-threshold is being disabled. */ + + /* Determine if this thread was scheduled with preemption-threshold in force. */ + if (_tx_thread_preemption_threshold_list[thread_ptr -> tx_thread_user_priority] == thread_ptr) + { + + /* Clear the entry in the preempted list. */ + _tx_thread_preemption_threshold_list[thread_ptr -> tx_thread_user_priority] = TX_NULL; + +#if TX_MAX_PRIORITIES > 32 + + /* Calculate the index into the bit map array. */ + map_index = (thread_ptr -> tx_thread_user_priority)/((UINT) 32); +#endif + + /* Yes, this thread is at the front of the list. Make sure + the preempted bit is cleared for this thread. */ + TX_MOD32_BIT_SET(thread_ptr -> tx_thread_user_priority, priority_bit) + _tx_thread_preempted_maps[MAP_INDEX] = _tx_thread_preempted_maps[MAP_INDEX] & (~(priority_bit)); + +#if TX_MAX_PRIORITIES > 32 + + /* Determine if there are any other bits set in this preempt map. */ + if (_tx_thread_preempted_maps[MAP_INDEX] == ((ULONG) 0)) + { + + /* No, clear the active bit to signify this preempt map has nothing set. */ + TX_DIV32_BIT_SET(thread_ptr -> tx_thread_user_priority, priority_bit) + _tx_thread_preempted_map_active = _tx_thread_preempted_map_active & (~(priority_bit)); + } +#endif + } + } +#endif + + /* Determine if this thread has global preemption disabled. */ + if (thread_ptr == _tx_thread_preemption__threshold_scheduled) + { + + /* Clear the global preemption disable flag. */ + _tx_thread_preemption__threshold_scheduled = TX_NULL; + +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD + + /* Calculate the first thread with preemption-threshold active. */ +#if TX_MAX_PRIORITIES > 32 + if (_tx_thread_preempted_map_active != ((ULONG) 0)) +#else + if (_tx_thread_preempted_maps[0] != ((ULONG) 0)) +#endif + { +#if TX_MAX_PRIORITIES > 32 + + /* Calculate the index to find the next highest priority thread ready for execution. */ + priority_map = _tx_thread_preempted_map_active; + + /* Calculate the lowest bit set in the priority map. */ + TX_LOWEST_SET_BIT_CALCULATE(priority_map, map_index) + + /* Calculate the base priority as well. */ + base_priority = map_index * ((UINT) 32); +#else + + /* Setup the base priority to zero. */ + base_priority = ((UINT) 0); +#endif + + /* Setup temporary preempted map. */ + priority_map = _tx_thread_preempted_maps[MAP_INDEX]; + + /* Calculate the lowest bit set in the priority map. */ + TX_LOWEST_SET_BIT_CALCULATE(priority_map, priority_bit_set) + + /* Move priority bit set into priority bit. */ + priority_bit = (ULONG) priority_bit_set; + + /* Setup the highest priority preempted thread. */ + next_preempted = base_priority + priority_bit; + + /* Pickup the previously preempted thread. */ + preempted_thread = _tx_thread_preemption_threshold_list[next_preempted]; + + /* Pickup the preempted thread. */ + _tx_thread_preemption__threshold_scheduled = preempted_thread; + } +#endif + } + + /* See if preemption needs to take place. */ + +#ifdef TX_THREAD_SMP_DEBUG_ENABLE + + /* Debug entry. */ + _tx_thread_smp_debug_entry_insert(12, 0, thread_ptr); +#endif + + /* Pickup the index. */ + core_index = TX_SMP_CORE_ID; + + /* Call the rebalance routine. This routine maps cores and ready threads. */ + _tx_thread_smp_rebalance_execute_list(core_index); + +#ifdef TX_THREAD_SMP_DEBUG_ENABLE + + /* Debug entry. */ + _tx_thread_smp_debug_entry_insert(13, 0, thread_ptr); +#endif + + /* Restore interrupts. */ + TX_RESTORE + + /* Check for preemption. */ + _tx_thread_system_preempt_check(); + } + else + { + + /* Restore interrupts. */ + TX_RESTORE + } + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/tx_thread_priority_change.c b/common_smp/src/tx_thread_priority_change.c new file mode 100644 index 00000000..56d4cdf5 --- /dev/null +++ b/common_smp/src/tx_thread_priority_change.c @@ -0,0 +1,514 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_priority_change PORTABLE SMP */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function changes the priority of the specified thread. It */ +/* also returns the old priority and handles preemption if the calling */ +/* thread is currently executing and the priority change results in a */ +/* higher priority thread ready for execution. */ +/* */ +/* Note: the preemption-threshold is automatically changed to the new */ +/* priority. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread to suspend */ +/* new_priority New thread priority */ +/* old_priority Old thread priority */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_smp_rebalance_execute_list Rebalance the execution list */ +/* _tx_thread_smp_simple_priority_change Change priority */ +/* _tx_thread_system_resume Resume thread */ +/* _tx_thread_system_ni_resume Non-interruptable resume */ +/* _tx_thread_system_suspend Suspend thread */ +/* _tx_thread_system_ni_suspend Non-interruptable suspend */ +/* _tx_thread_system_preempt_check Check for preemption */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_thread_priority_change(TX_THREAD *thread_ptr, UINT new_priority, UINT *old_priority) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_THREAD *execute_ptr; +UINT core_index; +UINT original_priority; +UINT lowest_priority; +TX_THREAD *original_pt_thread; +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD +TX_THREAD *new_pt_thread; +UINT priority; +ULONG priority_bit; +#if TX_MAX_PRIORITIES > 32 +UINT map_index; +#endif +#endif +UINT status; + + + /* Default status to not done. */ + status = TX_NOT_DONE; + + /* Lockout interrupts while the thread is being suspended. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_PRIORITY_CHANGE, thread_ptr, new_priority, thread_ptr -> tx_thread_priority, thread_ptr -> tx_thread_state, TX_TRACE_THREAD_EVENTS) + + /* Log this kernel call. */ + TX_EL_THREAD_PRIORITY_CHANGE_INSERT + + /* Save the previous priority. */ + *old_priority = thread_ptr -> tx_thread_user_priority; + + /* Determine if the new priority is the same as the last requested priority. */ + if ((thread_ptr -> tx_thread_user_priority == new_priority) && + (thread_ptr -> tx_thread_user_preempt_threshold == new_priority)) + { + + /* Nothing to do at this point, simply return. */ + + /* Restore interrupts. */ + TX_RESTORE + + /* Done, return success. */ + status = TX_SUCCESS; + } + + /* Determine if the inherit priority is in effect and there is no preemption-threshold in force. */ + else if ((thread_ptr -> tx_thread_inherit_priority < new_priority) && + (thread_ptr -> tx_thread_user_preempt_threshold == thread_ptr -> tx_thread_user_priority)) + { + + /* In this case, simply setup the user priority and preemption-threshold and return. */ + + /* Setup the new priority for this thread. */ + thread_ptr -> tx_thread_user_priority = new_priority; + thread_ptr -> tx_thread_user_preempt_threshold = new_priority; + + /* Restore interrupts. */ + TX_RESTORE + + /* Done, return success. */ + status = TX_SUCCESS; + } + else + { + + /* Default the execute pointer to NULL. */ + execute_ptr = TX_NULL; + + /* Determine if this thread is currently ready. */ + if (thread_ptr -> tx_thread_state != TX_READY) + { + + /* Setup the user priority and threshold in the thread's control + block. */ + thread_ptr -> tx_thread_user_priority = new_priority; + thread_ptr -> tx_thread_user_preempt_threshold = new_priority; + + /* Determine if the actual thread priority should be setup, which is the + case if the new priority is higher than the priority inheritance. */ + if (new_priority < thread_ptr -> tx_thread_inherit_priority) + { + + /* Change thread priority to the new user's priority. */ + thread_ptr -> tx_thread_priority = new_priority; + thread_ptr -> tx_thread_preempt_threshold = new_priority; + } + else + { + + /* Change thread priority to the priority inheritance. */ + thread_ptr -> tx_thread_priority = thread_ptr -> tx_thread_inherit_priority; + thread_ptr -> tx_thread_preempt_threshold = thread_ptr -> tx_thread_inherit_priority; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Done, return success. */ + status = TX_SUCCESS; + } + else + { + + /* Pickup the core index. */ + core_index = thread_ptr -> tx_thread_smp_core_mapped; + + /* Save the original priority. */ + original_priority = thread_ptr -> tx_thread_priority; + + /* Determine if this thread is the currently scheduled thread. */ + if (thread_ptr == _tx_thread_execute_ptr[core_index]) + { + + /* Yes, this thread is scheduled. */ + + /* Remember this thread as the currently executing thread. */ + execute_ptr = thread_ptr; + + /* Determine if the thread is being set to a higher-priority and it does't have + preemption-threshold set. */ + if ((new_priority < thread_ptr -> tx_thread_priority) && + (thread_ptr -> tx_thread_user_priority == thread_ptr -> tx_thread_user_preempt_threshold)) + { + + /* Simple case, remove the thread from the current priority list and place in + the higher priority list. */ + _tx_thread_smp_simple_priority_change(thread_ptr, new_priority); + + /* Setup the new priority for this thread. */ + thread_ptr -> tx_thread_user_priority = new_priority; + thread_ptr -> tx_thread_user_preempt_threshold = new_priority; + + /* Restore interrupts. */ + TX_RESTORE + + /* Return a successful completion. */ + status = TX_SUCCESS; + } + } + else + { + + /* Thread is not currently executing, so it can just be moved to the lower priority in the list. */ + + /* Determine if the thread is being set to a lower-priority and it does't have + preemption-threshold set. */ + if ((new_priority > thread_ptr -> tx_thread_priority) && + (thread_ptr -> tx_thread_user_priority == thread_ptr -> tx_thread_user_preempt_threshold)) + { + + /* Simple case, remove the thread from the current priority list and place in + the lower priority list. */ + _tx_thread_smp_simple_priority_change(thread_ptr, new_priority); + + /* Setup the new priority for this thread. */ + thread_ptr -> tx_thread_user_priority = new_priority; + thread_ptr -> tx_thread_user_preempt_threshold = new_priority; + + /* Restore interrupts. */ + TX_RESTORE + + /* Return a successful completion. */ + status = TX_SUCCESS; + } + } + + /* Determine if we are done. */ + if (status == TX_NOT_DONE) + { + + /* Yes, more to do. */ + + /* Default the status to success. */ + status = TX_SUCCESS; + + /* Save the original preemption-threshold thread. */ + original_pt_thread = _tx_thread_preemption__threshold_scheduled; + +#ifdef TX_NOT_INTERRUPTABLE + + /* Increment the preempt disable flag. */ + _tx_thread_preempt_disable++; + + /* Set the state to suspended. */ + thread_ptr -> tx_thread_state = TX_SUSPENDED; + + /* Call actual non-interruptable thread suspension routine. */ + _tx_thread_system_ni_suspend(thread_ptr, ((ULONG) 0)); + + /* At this point, the preempt disable flag is still set, so we still have + protection against all preemption. */ + + /* Setup the new priority for this thread. */ + thread_ptr -> tx_thread_user_priority = new_priority; + thread_ptr -> tx_thread_user_preempt_threshold = new_priority; + + /* Determine if the actual thread priority should be setup, which is the + case if the new priority is higher than the priority inheritance. */ + if (new_priority < thread_ptr -> tx_thread_inherit_priority) + { + + /* Change thread priority to the new user's priority. */ + thread_ptr -> tx_thread_priority = new_priority; + thread_ptr -> tx_thread_preempt_threshold = new_priority; + } + else + { + + /* Change thread priority to the priority inheritance. */ + thread_ptr -> tx_thread_priority = thread_ptr -> tx_thread_inherit_priority; + thread_ptr -> tx_thread_preempt_threshold = thread_ptr -> tx_thread_inherit_priority; + } + + /* Resume the thread with the new priority. */ + _tx_thread_system_ni_resume(thread_ptr); + + /* Decrement the preempt disable flag. */ + _tx_thread_preempt_disable--; +#else + + /* Increment the preempt disable flag. */ + _tx_thread_preempt_disable = _tx_thread_preempt_disable + ((UINT) 3); + + /* Set the state to suspended. */ + thread_ptr -> tx_thread_state = TX_SUSPENDED; + + /* Set the suspending flag. */ + thread_ptr -> tx_thread_suspending = TX_TRUE; + + /* Setup the timeout period. */ + thread_ptr -> tx_thread_timer.tx_timer_internal_remaining_ticks = ((ULONG) 0); + + /* Restore interrupts. */ + TX_RESTORE + + /* The thread is ready and must first be removed from the list. Call the + system suspend function to accomplish this. */ + _tx_thread_system_suspend(thread_ptr); + + /* Lockout interrupts again. */ + TX_DISABLE + + /* At this point, the preempt disable flag is still set, so we still have + protection against all preemption. */ + + /* Setup the new priority for this thread. */ + thread_ptr -> tx_thread_user_priority = new_priority; + thread_ptr -> tx_thread_user_preempt_threshold = new_priority; + + /* Determine if the actual thread priority should be setup, which is the + case if the new priority is higher than the priority inheritance. */ + if (new_priority < thread_ptr -> tx_thread_inherit_priority) + { + + /* Change thread priority to the new user's priority. */ + thread_ptr -> tx_thread_priority = new_priority; + thread_ptr -> tx_thread_preempt_threshold = new_priority; + } + else + { + + /* Change thread priority to the priority inheritance. */ + thread_ptr -> tx_thread_priority = thread_ptr -> tx_thread_inherit_priority; + thread_ptr -> tx_thread_preempt_threshold = thread_ptr -> tx_thread_inherit_priority; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Resume the thread with the new priority. */ + _tx_thread_system_resume(thread_ptr); +#endif + + /* Optional processing extension. */ + TX_THREAD_PRIORITY_CHANGE_EXTENSION + +#ifndef TX_NOT_INTERRUPTABLE + + /* Disable interrupts. */ + TX_DISABLE + + /* Decrement the preemption-threshold flag. */ + _tx_thread_preempt_disable--; +#endif + + /* Determine if the thread was previously executing. */ + if (thread_ptr == execute_ptr) + { + +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD + /* Determine if preemption-threshold is in force at the new priority level. */ + if (_tx_thread_preemption_threshold_list[thread_ptr -> tx_thread_priority] == TX_NULL) + { + + /* Ensure that this thread is placed at the front of the priority list. */ + _tx_thread_priority_list[thread_ptr -> tx_thread_priority] = thread_ptr; + } +#else + + /* Ensure that this thread is placed at the front of the priority list. */ + _tx_thread_priority_list[thread_ptr -> tx_thread_priority] = thread_ptr; +#endif + } + + /* Pickup the core index. */ + core_index = thread_ptr -> tx_thread_smp_core_mapped; + +#ifndef TX_THREAD_SMP_DYNAMIC_CORE_MAX + + /* Pickup the next thread to execute. */ + if (core_index < ((UINT) TX_THREAD_SMP_MAX_CORES)) +#else + + /* Pickup the next thread to execute. */ + if (core_index < _tx_thread_smp_max_cores) +#endif + { + + /* Determine if this thread is not the next thread to execute. */ + if (thread_ptr != _tx_thread_execute_ptr[core_index]) + { + + /* Now determine if this thread was previously executing thread. */ + if (thread_ptr == execute_ptr) + { + + /* Determine if we moved to a lower priority. If so, move the thread to the front of the priority list. */ + if (original_priority < new_priority) + { + + /* Make sure the thread is still ready. */ + if (thread_ptr -> tx_thread_state == TX_READY) + { + + /* Determine the lowest priority scheduled thread. */ + lowest_priority = _tx_thread_smp_lowest_priority_get(); + + /* Determine if this thread has a higher or same priority as the lowest priority + in the list. */ + if (thread_ptr -> tx_thread_priority <= lowest_priority) + { + + /* Yes, we need to rebalance to make it possible for this thread to execute. */ + + /* Determine if the thread with preemption-threshold thread has changed... and is + not the scheduled thread. */ + if ((original_pt_thread != _tx_thread_preemption__threshold_scheduled) && + (original_pt_thread != thread_ptr)) + { + + /* Yes, preemption-threshold has changed. Determine if it can or should + be reversed. */ + +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD + + /* Pickup the preemption-threshold thread. */ + new_pt_thread = _tx_thread_preemption__threshold_scheduled; +#endif + + /* Restore the original preemption-threshold thread. */ + _tx_thread_preemption__threshold_scheduled = original_pt_thread; + + +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD + + /* Determine if there is a new preemption-threshold thread to reverse. */ + if (new_pt_thread != TX_NULL) + { + + /* Clear the information associated with the new preemption-threshold thread. */ + + /* Pickup the priority. */ + priority = new_pt_thread -> tx_thread_priority; + + /* Clear the preempted list entry. */ + _tx_thread_preemption_threshold_list[priority] = TX_NULL; + +#if TX_MAX_PRIORITIES > 32 + /* Calculate the bit map array index. */ + map_index = new_priority/((UINT) 32); +#endif + + /* Ensure that this thread's priority is clear in the preempt map. */ + TX_MOD32_BIT_SET(priority, priority_bit) + _tx_thread_preempted_maps[MAP_INDEX] = _tx_thread_preempted_maps[MAP_INDEX] & (~(priority_bit)); +#if TX_MAX_PRIORITIES > 32 + + /* Determine if there are any other bits set in this preempt map. */ + if (_tx_thread_preempted_maps[MAP_INDEX] == ((ULONG) 0)) + { + + /* No, clear the active bit to signify this preempted map has nothing set. */ + TX_DIV32_BIT_SET(priority, priority_bit) + _tx_thread_preempted_map_active = _tx_thread_preempted_map_active & (~(priority_bit)); + } +#endif + } +#endif + } + + /* Pickup the index. */ + core_index = TX_SMP_CORE_ID; + + /* Call the rebalance routine. This routine maps cores and ready threads. */ + _tx_thread_smp_rebalance_execute_list(core_index); + } + } + } + } + } + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Check for preemption. */ + _tx_thread_system_preempt_check(); + } + } + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/tx_thread_relinquish.c b/common_smp/src/tx_thread_relinquish.c new file mode 100644 index 00000000..20a5a165 --- /dev/null +++ b/common_smp/src/tx_thread_relinquish.c @@ -0,0 +1,504 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +#include "tx_trace.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_relinquish PORTABLE SMP */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function determines if there is another higher or equal */ +/* priority, non-executing thread that can execute on this processor. */ +/* such a thread is found, the calling thread relinquishes control. */ +/* Otherwise, this function simply returns. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_smp_rebalance_execute_list Rebalance the execution list */ +/* _tx_thread_system_return Return to the system */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_relinquish(VOID) +{ + +TX_INTERRUPT_SAVE_AREA + +UINT priority; +TX_THREAD *thread_ptr; +TX_THREAD *head_ptr; +TX_THREAD *tail_ptr; +TX_THREAD *next_thread; +TX_THREAD *previous_thread; +UINT core_index; +UINT rebalance; +UINT mapped_core; +ULONG excluded; + +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD +UINT base_priority; +UINT priority_bit_set; +UINT next_preempted; +ULONG priority_bit; +ULONG priority_map; +TX_THREAD *preempted_thread; +#if TX_MAX_PRIORITIES > 32 +UINT map_index; +#endif +#endif +UINT finished; + + + /* Default finished to false. */ + finished = TX_FALSE; + + /* Initialize the rebalance flag to false. */ + rebalance = TX_FALSE; + + /* Lockout interrupts while thread attempts to relinquish control. */ + TX_DISABLE + + /* Pickup the index. */ + core_index = TX_SMP_CORE_ID; + + /* Pickup the current thread pointer. */ + thread_ptr = _tx_thread_current_ptr[core_index]; + +#ifndef TX_NO_TIMER + + /* Reset time slice for current thread. */ + _tx_timer_time_slice[core_index] = thread_ptr -> tx_thread_new_time_slice; +#endif + +#ifdef TX_ENABLE_STACK_CHECKING + + /* Check this thread's stack. */ + TX_THREAD_STACK_CHECK(thread_ptr) +#endif + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_RELINQUISH, &thread_ptr, TX_POINTER_TO_ULONG_CONVERT(thread_ptr -> tx_thread_ready_next), 0, 0, TX_TRACE_THREAD_EVENTS) + + /* Log this kernel call. */ + TX_EL_THREAD_RELINQUISH_INSERT + + /* Pickup the thread's priority. */ + priority = thread_ptr -> tx_thread_priority; + +#ifdef TX_THREAD_SMP_DEBUG_ENABLE + + /* Debug entry. */ + _tx_thread_smp_debug_entry_insert(0, 0, thread_ptr); +#endif + + /* Pickup the next thread. */ + next_thread = thread_ptr -> tx_thread_ready_next; + + /* Pickup the head of the list. */ + head_ptr = _tx_thread_priority_list[priority]; + + /* Pickup the list tail. */ + tail_ptr = head_ptr -> tx_thread_ready_previous; + + /* Determine if this thread is not the tail pointer. */ + if (thread_ptr != tail_ptr) + { + + /* Not the tail pointer, this thread must be moved to the end of the ready list. */ + + /* Determine if this thread is at the head of the list. */ + if (head_ptr == thread_ptr) + { + + /* Simply move the head pointer to put this thread at the end of the ready list at this priority. */ + _tx_thread_priority_list[priority] = next_thread; + } + else + { + + /* Now we need to remove this thread from its current position and place it at the end of the list. */ + + /* Pickup the previous thread pointer. */ + previous_thread = thread_ptr -> tx_thread_ready_previous; + + /* Remove the thread from the ready list. */ + next_thread -> tx_thread_ready_previous = previous_thread; + previous_thread -> tx_thread_ready_next = next_thread; + + /* Insert the thread at the end of the list. */ + tail_ptr -> tx_thread_ready_next = thread_ptr; + head_ptr -> tx_thread_ready_previous = thread_ptr; + thread_ptr -> tx_thread_ready_previous = tail_ptr; + thread_ptr -> tx_thread_ready_next = head_ptr; + } + + /* Pickup the mapped core of the relinquishing thread - this can be different from the current core. */ + mapped_core = thread_ptr -> tx_thread_smp_core_mapped; + + /* Determine if the relinquishing thread is no longer present in the execute list. */ + if (thread_ptr != _tx_thread_execute_ptr[mapped_core]) + { + + /* Yes, the thread is no longer mapped. Set the rebalance flag to determine if there is a new mapping due to moving + this thread to the end of the priority list. */ + + /* Set the rebalance flag to true. */ + rebalance = TX_FALSE; + } + + /* Determine if preemption-threshold is in force. */ + else if (thread_ptr -> tx_thread_preempt_threshold == priority) + { + + /* No preemption-threshold is in force. */ + + /* Determine if there is a thread at the same priority that isn't currently executing. */ + do + { + + /* Isolate the exclusion for this core. */ + excluded = (next_thread -> tx_thread_smp_cores_excluded >> mapped_core) & ((ULONG) 1); + + /* Determine if the next thread has preemption-threshold set or is excluded from running on the + mapped core. */ + if ((next_thread -> tx_thread_preempt_threshold < next_thread -> tx_thread_priority) || + (excluded == ((ULONG) 1))) + { + + /* Set the rebalance flag. */ + rebalance = TX_TRUE; + + /* Get out of the loop. We need to rebalance the list when we detect preemption-threshold. */ + break; + } + else + { + + /* Is the next thread already in the execute list? */ + if (next_thread != _tx_thread_execute_ptr[next_thread -> tx_thread_smp_core_mapped]) + { + + /* No, we can place this thread in the position the relinquishing thread + was in. */ + + /* Remember this index in the thread control block. */ + next_thread -> tx_thread_smp_core_mapped = mapped_core; + + /* Setup the entry in the execution list. */ + _tx_thread_execute_ptr[mapped_core] = next_thread; + +#ifdef TX_THREAD_SMP_DEBUG_ENABLE + + /* Debug entry. */ + _tx_thread_smp_debug_entry_insert(1, 0, next_thread); +#endif + +#ifdef TX_THREAD_ENABLE_PERFORMANCE_INFO + + /* Increment the number of thread relinquishes. */ + thread_ptr -> tx_thread_performance_relinquish_count++; + + /* Increment the total number of thread relinquish operations. */ + _tx_thread_performance_relinquish_count++; + + /* No, there is another thread ready to run and will be scheduled upon return. */ + _tx_thread_performance_non_idle_return_count++; +#endif + +#ifdef TX_ENABLE_STACK_CHECKING + + /* Check this thread's stack. */ + TX_THREAD_STACK_CHECK(next_thread) +#endif + +#ifndef TX_NOT_INTERRUPTABLE + + /* Increment the preempt disable flag in order to keep the protection. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE +#endif + + /* Transfer control to the system so the scheduler can execute + the next thread. */ + _tx_thread_system_return(); + + +#ifdef TX_NOT_INTERRUPTABLE + + /* Restore interrupts. */ + TX_RESTORE +#endif + + /* Set the finished flag. */ + finished = TX_TRUE; + + } + + /* Move to the next thread at this priority. */ + next_thread = next_thread -> tx_thread_ready_next; + + } + } while ((next_thread != thread_ptr) && (finished == TX_FALSE)); + + /* Determine if we are finished. */ + if (finished == TX_FALSE) + { + + /* No other thread is ready at this priority... simply return. */ + +#ifdef TX_THREAD_SMP_DEBUG_ENABLE + + /* Debug entry. */ + _tx_thread_smp_debug_entry_insert(1, 0, thread_ptr); +#endif + + /* Restore interrupts. */ + TX_RESTORE + + /* Set the finished flag. */ + finished = TX_TRUE; + } + } + else + { + + /* Preemption-threshold is in force. */ + + /* Set the rebalance flag. */ + rebalance = TX_TRUE; + } + } + + /* Determine if preemption-threshold is in force. */ + if (thread_ptr -> tx_thread_preempt_threshold < priority) + { + + /* Set the rebalance flag. */ + rebalance = TX_TRUE; + +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD + +#if TX_MAX_PRIORITIES > 32 + + /* Calculate the index into the bit map array. */ + map_index = priority/((UINT) 32); +#endif + + /* Ensure that this thread's priority is clear in the preempt map. */ + TX_MOD32_BIT_SET(priority, priority_bit) + _tx_thread_preempted_maps[MAP_INDEX] = _tx_thread_preempted_maps[MAP_INDEX] & (~(priority_bit)); + +#if TX_MAX_PRIORITIES > 32 + + /* Determine if there are any other bits set in this preempt map. */ + if (_tx_thread_preempted_maps[MAP_INDEX] == ((ULONG) 0)) + { + + /* No, clear the active bit to signify this preempted map has nothing set. */ + TX_DIV32_BIT_SET(priority, priority_bit) + _tx_thread_preempted_map_active = _tx_thread_preempted_map_active & (~(priority_bit)); + } +#endif + + /* Clear the entry in the preempted list. */ + _tx_thread_preemption_threshold_list[priority] = TX_NULL; + + /* Does this thread have preemption-threshold? */ + if (_tx_thread_preemption__threshold_scheduled == thread_ptr) + { + + /* Yes, set the preempted thread to NULL. */ + _tx_thread_preemption__threshold_scheduled = TX_NULL; + } + + /* Calculate the first thread with preemption-threshold active. */ +#if TX_MAX_PRIORITIES > 32 + if (_tx_thread_preempted_map_active != ((ULONG) 0)) +#else + if (_tx_thread_preempted_maps[0] != ((ULONG) 0)) +#endif + { +#if TX_MAX_PRIORITIES > 32 + + /* Calculate the index to find the next highest priority thread ready for execution. */ + priority_map = _tx_thread_preempted_map_active; + + /* Calculate the lowest bit set in the priority map. */ + TX_LOWEST_SET_BIT_CALCULATE(priority_map, map_index) + + /* Calculate the base priority as well. */ + base_priority = map_index * ((UINT) 32); +#else + + /* Setup the base priority to zero. */ + base_priority = ((UINT) 0); +#endif + + /* Setup temporary preempted map. */ + priority_map = _tx_thread_preempted_maps[MAP_INDEX]; + + /* Calculate the lowest bit set in the priority map. */ + TX_LOWEST_SET_BIT_CALCULATE(priority_map, priority_bit_set) + + /* Move priority bit set into priority bit. */ + priority_bit = (ULONG) priority_bit_set; + + /* Setup the highest priority preempted thread. */ + next_preempted = base_priority + priority_bit; + + /* Pickup the previously preempted thread. */ + preempted_thread = _tx_thread_preemption_threshold_list[next_preempted]; + + /* Setup the preempted thread. */ + _tx_thread_preemption__threshold_scheduled = preempted_thread; + } +#else + + /* Determine if this thread has preemption-threshold disabled. */ + if (thread_ptr == _tx_thread_preemption__threshold_scheduled) + { + + /* Clear the global preemption disable flag. */ + _tx_thread_preemption__threshold_scheduled = TX_NULL; + } +#endif + } + + /* Check to see if there is still work to do. */ + if (finished == TX_FALSE) + { + +#ifdef TX_THREAD_SMP_DEBUG_ENABLE + + /* Debug entry. */ + _tx_thread_smp_debug_entry_insert(1, 0, thread_ptr); +#endif + + /* Determine if we need to rebalance the execute list. */ + if (rebalance == TX_TRUE) + { + + /* Rebalance the excute list. */ + _tx_thread_smp_rebalance_execute_list(core_index); + } + + /* Determine if this thread needs to return to the system. */ + if (_tx_thread_execute_ptr[core_index] != thread_ptr) + { + +#ifdef TX_THREAD_ENABLE_PERFORMANCE_INFO + + /* Increment the number of thread relinquishes. */ + thread_ptr -> tx_thread_performance_relinquish_count++; + + /* Increment the total number of thread relinquish operations. */ + _tx_thread_performance_relinquish_count++; + + /* Determine if an idle system return is present. */ + if (_tx_thread_execute_ptr[core_index] == TX_NULL) + { + + /* Yes, increment the return to idle return count. */ + _tx_thread_performance_idle_return_count++; + } + else + { + + /* No, there is another thread ready to run and will be scheduled upon return. */ + _tx_thread_performance_non_idle_return_count++; + } +#endif + +#ifdef TX_ENABLE_STACK_CHECKING + + /* Pickup new thread pointer. */ + thread_ptr = _tx_thread_execute_ptr[core_index]; + + /* Check this thread's stack. */ + TX_THREAD_STACK_CHECK(thread_ptr) +#endif + +#ifndef TX_NOT_INTERRUPTABLE + + /* Increment the preempt disable flag in order to keep the protection. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE +#endif + + /* Transfer control to the system so the scheduler can execute + the next thread. */ + _tx_thread_system_return(); + +#ifdef TX_NOT_INTERRUPTABLE + + /* Restore interrupts. */ + TX_RESTORE +#endif + } + else + { + + /* Restore interrupts. */ + TX_RESTORE + } + } +} + diff --git a/common_smp/src/tx_thread_reset.c b/common_smp/src/tx_thread_reset.c new file mode 100644 index 00000000..8c6c0794 --- /dev/null +++ b/common_smp/src/tx_thread_reset.c @@ -0,0 +1,163 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_reset PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function prepares the thread to run again from the entry */ +/* point specified during thread creation. The application must */ +/* call tx_thread_resume after this call completes for the thread */ +/* to actually run. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread to reset */ +/* */ +/* OUTPUT */ +/* */ +/* status Service return status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_stack_build Build initial thread stack */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_thread_reset(TX_THREAD *thread_ptr) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_THREAD *current_thread; +UINT status; + + + /* Default a successful completion status. */ + status = TX_SUCCESS; + + /* Disable interrupts. */ + TX_DISABLE + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(current_thread) + + /* Check for a call from the current thread, which is not allowed! */ + if (current_thread == thread_ptr) + { + + /* Thread not completed or terminated - return an error! */ + status = TX_NOT_DONE; + } + else + { + + /* Check for proper status of this thread to reset. */ + if (thread_ptr -> tx_thread_state != TX_COMPLETED) + { + + /* Now check for terminated state. */ + if (thread_ptr -> tx_thread_state != TX_TERMINATED) + { + + /* Thread not completed or terminated - return an error! */ + status = TX_NOT_DONE; + } + } + } + + /* Is the request valid? */ + if (status == TX_SUCCESS) + { + + /* Modify the thread status to prevent additional reset calls. */ + thread_ptr -> tx_thread_state = TX_NOT_DONE; + + /* Execute Port-Specific completion processing. If needed, it is typically defined in tx_port.h. */ + TX_THREAD_RESET_PORT_COMPLETION(thread_ptr) + + /* Restore interrupts. */ + TX_RESTORE + +#ifndef TX_DISABLE_STACK_FILLING + + /* Set the thread stack to a pattern prior to creating the initial + stack frame. This pattern is used by the stack checking routines + to see how much has been used. */ + TX_MEMSET(thread_ptr -> tx_thread_stack_start, ((UCHAR) TX_STACK_FILL), thread_ptr -> tx_thread_stack_size); +#endif + + /* Call the target specific stack frame building routine to build the + thread's initial stack and to setup the actual stack pointer in the + control block. */ + _tx_thread_stack_build(thread_ptr, _tx_thread_shell_entry); + + /* Disable interrupts. */ + TX_DISABLE + + /* Finally, move into a suspended state to allow for the thread to be resumed. */ + thread_ptr -> tx_thread_state = TX_SUSPENDED; + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_RESET, thread_ptr, thread_ptr -> tx_thread_state, 0, 0, TX_TRACE_THREAD_EVENTS) + + /* Log this kernel call. */ + TX_EL_THREAD_RESET_INSERT + + /* Log the thread status change. */ + TX_EL_THREAD_STATUS_CHANGE_INSERT(thread_ptr, TX_SUSPENDED) + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return completion status to caller. */ + return(status); +} + diff --git a/common_smp/src/tx_thread_resume.c b/common_smp/src/tx_thread_resume.c new file mode 100644 index 00000000..993dbe84 --- /dev/null +++ b/common_smp/src/tx_thread_resume.c @@ -0,0 +1,178 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_thread.h" +#include "tx_initialize.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_resume PORTABLE SMP */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes application resume thread services. Actual */ +/* thread resumption is performed in the core service. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread to resume */ +/* */ +/* OUTPUT */ +/* */ +/* status Service return status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_smp_rebalance_execute_list Rebalance the execution list */ +/* _tx_thread_system_resume Resume thread */ +/* _tx_thread_system_ni_resume Non-interruptable resume */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_thread_resume(TX_THREAD *thread_ptr) +{ + +TX_INTERRUPT_SAVE_AREA + +UINT status; +UINT core_index; + + + /* Lockout interrupts while the thread is being resumed. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_RESUME_API, thread_ptr, thread_ptr -> tx_thread_state, TX_POINTER_TO_ULONG_CONVERT(&status), 0, TX_TRACE_THREAD_EVENTS) + + /* Log this kernel call. */ + TX_EL_THREAD_RESUME_INSERT + + /* Determine if the thread is suspended or in the process of suspending. + If so, call the thread resume processing. */ + if (thread_ptr -> tx_thread_state == TX_SUSPENDED) + { + +#ifdef TX_NOT_INTERRUPTABLE + + /* Resume the thread! */ + _tx_thread_system_ni_resume(thread_ptr); + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Call the actual resume service to resume the thread. */ + _tx_thread_system_resume(thread_ptr); +#endif + + /* Disable interrupts. */ + TX_DISABLE + + /* Determine if the thread's preemption-threshold needs to be restored. */ + if (_tx_thread_smp_current_state_get() >= TX_INITIALIZE_IN_PROGRESS) + { + +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD + + /* Clear the preemption bit maps, since nothing has yet run during initialization. */ + TX_MEMSET(_tx_thread_preempted_maps, 0, sizeof(_tx_thread_preempted_maps)); +#if TX_MAX_PRIORITIES > 32 + _tx_thread_preempted_map_active = ((ULONG) 0); +#endif +#endif + _tx_thread_preemption__threshold_scheduled = TX_NULL; + +#ifdef TX_THREAD_SMP_DEBUG_ENABLE + + /* Debug entry. */ + _tx_thread_smp_debug_entry_insert(14, 0, thread_ptr); +#endif + + /* Get the core index. */ + core_index = TX_SMP_CORE_ID; + + /* Call the rebalance routine. This routine maps cores and ready threads. */ + _tx_thread_smp_rebalance_execute_list(core_index); + +#ifdef TX_THREAD_SMP_DEBUG_ENABLE + + /* Debug entry. */ + _tx_thread_smp_debug_entry_insert(15, 0, thread_ptr); +#endif + } + + /* Setup successful return status. */ + status = TX_SUCCESS; + } + else if (thread_ptr -> tx_thread_delayed_suspend != TX_FALSE) + { + + /* Clear the delayed suspension. */ + thread_ptr -> tx_thread_delayed_suspend = TX_FALSE; + + /* Setup delayed suspend lifted return status. */ + status = TX_SUSPEND_LIFTED; + } + else + { + + /* Setup invalid resume return status. */ + status = TX_RESUME_ERROR; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/tx_thread_shell_entry.c b/common_smp/src/tx_thread_shell_entry.c new file mode 100644 index 00000000..ca4647ad --- /dev/null +++ b/common_smp/src/tx_thread_shell_entry.c @@ -0,0 +1,201 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_shell_entry PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calls the specified entry function of the thread. It */ +/* also provides a place for the thread's entry function to return. */ +/* If the thread returns, this function places the thread in a */ +/* "COMPLETED" state. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* thread_entry Thread's entry function */ +/* _tx_thread_system_suspend Thread suspension routine */ +/* _tx_thread_system_ni_suspend Non-interruptable suspend thread */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_shell_entry(VOID) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_THREAD *thread_ptr; +#ifndef TX_DISABLE_NOTIFY_CALLBACKS +VOID (*entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT type); +#endif + + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr) + + /* Perform any additional activities for tool or user purpose. */ + TX_THREAD_STARTED_EXTENSION(thread_ptr) + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Disable interrupts. */ + TX_DISABLE + + /* Pickup the entry/exit application callback routine. */ + entry_exit_notify = thread_ptr -> tx_thread_entry_exit_notify; + + /* Restore interrupts. */ + TX_RESTORE + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has been entered! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_ENTRY); + } +#endif + + /* Call current thread's entry function. */ + (thread_ptr -> tx_thread_entry) (thread_ptr -> tx_thread_entry_parameter); + + /* Suspend thread with a "completed" state. */ + + /* Determine if the application is using mutexes. */ + if (_tx_thread_mutex_release != TX_NULL) + { + + /* Yes, call the mutex release function via a function pointer that + is setup during mutex initialization. */ + (_tx_thread_mutex_release)(thread_ptr); + } + + /* Lockout interrupts while the thread state is setup. */ + TX_DISABLE + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine again. */ + entry_exit_notify = thread_ptr -> tx_thread_entry_exit_notify; +#endif + + /* Set the status to suspending, in order to indicate the suspension + is in progress. */ + thread_ptr -> tx_thread_state = TX_COMPLETED; + + /* Thread state change. */ + TX_THREAD_STATE_CHANGE(thread_ptr, TX_COMPLETED) + +#ifdef TX_NOT_INTERRUPTABLE + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has exited! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_EXIT); + } +#endif + + /* Perform any additional activities for tool or user purpose. */ + TX_THREAD_COMPLETED_EXTENSION(thread_ptr) + + /* Call actual non-interruptable thread suspension routine. */ + _tx_thread_system_ni_suspend(thread_ptr, ((ULONG) 0)); + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Set the suspending flag. */ + thread_ptr -> tx_thread_suspending = TX_TRUE; + + /* Setup for no timeout period. */ + thread_ptr -> tx_thread_timer.tx_timer_internal_remaining_ticks = ((ULONG) 0); + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Perform any additional activities for tool or user purpose. */ + TX_THREAD_COMPLETED_EXTENSION(thread_ptr) + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has exited! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_EXIT); + } +#endif + + /* Call actual thread suspension routine. */ + _tx_thread_system_suspend(thread_ptr); +#endif + + +#ifdef TX_SAFETY_CRITICAL + + /* If we ever get here, raise safety critical exception. */ + TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0); +#endif +} + diff --git a/common_smp/src/tx_thread_sleep.c b/common_smp/src/tx_thread_sleep.c new file mode 100644 index 00000000..833f83ec --- /dev/null +++ b/common_smp/src/tx_thread_sleep.c @@ -0,0 +1,198 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_thread.h" +#include "tx_timer.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_sleep PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles application thread sleep requests. If the */ +/* sleep request was called from a non-thread, an error is returned. */ +/* */ +/* INPUT */ +/* */ +/* timer_ticks Number of timer ticks to sleep*/ +/* */ +/* OUTPUT */ +/* */ +/* status Return completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_system_suspend Actual thread suspension */ +/* _tx_thread_system_ni_suspend Non-interruptable suspend thread */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_thread_sleep(ULONG timer_ticks) +{ + +TX_INTERRUPT_SAVE_AREA + +UINT status; +TX_THREAD *thread_ptr; + + + /* Lockout interrupts while the thread is being resumed. */ + TX_DISABLE + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr) + + /* Determine if this is a legal request. */ + + /* Is there a current thread? */ + if (thread_ptr == TX_NULL) + { + + /* Restore interrupts. */ + TX_RESTORE + + /* Illegal caller of this service. */ + status = TX_CALLER_ERROR; + } + + /* Is the caller an ISR or Initialization? */ + else if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + + /* Restore interrupts. */ + TX_RESTORE + + /* Illegal caller of this service. */ + status = TX_CALLER_ERROR; + } + +#ifndef TX_TIMER_PROCESS_IN_ISR + + /* Is the caller the system timer thread? */ + else if (thread_ptr == &_tx_timer_thread) + { + + /* Restore interrupts. */ + TX_RESTORE + + /* Illegal caller of this service. */ + status = TX_CALLER_ERROR; + } +#endif + + /* Determine if the requested number of ticks is zero. */ + else if (timer_ticks == ((ULONG) 0)) + { + + /* Restore interrupts. */ + TX_RESTORE + + /* Just return with a successful status. */ + status = TX_SUCCESS; + } + else + { + + /* Determine if the preempt disable flag is non-zero. */ + if (_tx_thread_preempt_disable != ((UINT) 0)) + { + + /* Restore interrupts. */ + TX_RESTORE + + /* Suspension is not allowed if the preempt disable flag is non-zero at this point - return error completion. */ + status = TX_CALLER_ERROR; + } + else + { + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_SLEEP, TX_ULONG_TO_POINTER_CONVERT(timer_ticks), thread_ptr -> tx_thread_state, TX_POINTER_TO_ULONG_CONVERT(&status), 0, TX_TRACE_THREAD_EVENTS) + + /* Log this kernel call. */ + TX_EL_THREAD_SLEEP_INSERT + + /* Suspend the current thread. */ + + /* Set the state to suspended. */ + thread_ptr -> tx_thread_state = TX_SLEEP; + +#ifdef TX_NOT_INTERRUPTABLE + + /* Call actual non-interruptable thread suspension routine. */ + _tx_thread_system_ni_suspend(thread_ptr, timer_ticks); + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Set the suspending flag. */ + thread_ptr -> tx_thread_suspending = TX_TRUE; + + /* Initialize the status to successful. */ + thread_ptr -> tx_thread_suspend_status = TX_SUCCESS; + + /* Setup the timeout period. */ + thread_ptr -> tx_thread_timer.tx_timer_internal_remaining_ticks = timer_ticks; + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Call actual thread suspension routine. */ + _tx_thread_system_suspend(thread_ptr); +#endif + + /* Return status to the caller. */ + status = thread_ptr -> tx_thread_suspend_status; + } + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/tx_thread_smp_core_exclude.c b/common_smp/src/tx_thread_smp_core_exclude.c new file mode 100644 index 00000000..61e843e5 --- /dev/null +++ b/common_smp/src/tx_thread_smp_core_exclude.c @@ -0,0 +1,237 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - High Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_timer.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_core_exclude PORTABLE SMP */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function allows the application to exclude one or more cores */ +/* from executing the specified thread. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to the thread */ +/* exclusion_map Bit map of exclusion list, */ +/* where bit 0 set means that */ +/* this thread cannot run on */ +/* core0, etc. */ +/* */ +/* OUTPUT */ +/* */ +/* Status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_smp_rebalance_execute_list Build execution list */ +/* _tx_thread_system_return System return */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_thread_smp_core_exclude(TX_THREAD *thread_ptr, ULONG exclusion_map) +{ + +TX_INTERRUPT_SAVE_AREA + +UINT core_index; +UINT new_mapped_core; +ULONG mapped_core; +ULONG available_cores; +UINT restore_needed; +UINT status; + + + /* Default status to success. */ + status = TX_SUCCESS; + + /* First, make sure the thread pointer is valid. */ + if (thread_ptr == TX_NULL) + { + + /* Return pointer error. */ + status = TX_THREAD_ERROR; + } + + /* Check for valid ID. */ + else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) + { + + /* Return pointer error. */ + status = TX_THREAD_ERROR; + } + else + { + + /* Disable interrupts. */ + TX_DISABLE + + /* Set the restore needed flag. */ + restore_needed = TX_TRUE; + +#ifdef TX_THREAD_SMP_DEBUG_ENABLE + + /* Debug entry. */ + _tx_thread_smp_debug_entry_insert(2, 0, thread_ptr); +#endif + + /* Build the bitmap for the last mapped core. */ + mapped_core = (((ULONG) 1) << thread_ptr -> tx_thread_smp_core_mapped); + + /* Calculate the available cores map. */ + available_cores = (~exclusion_map) & ((ULONG) TX_THREAD_SMP_CORE_MASK); + + /* Save the excluded and available cores. */ + thread_ptr -> tx_thread_smp_cores_excluded = exclusion_map; + thread_ptr -> tx_thread_smp_cores_allowed = available_cores; + + /* Determine if this is within the now available cores. */ + if ((mapped_core & available_cores) == ((ULONG) 0)) + { + + /* Determine if there are any cores available. */ + if (available_cores == ((ULONG) 0)) + { + + /* No cores are available, simply set the last running core to 0. */ + thread_ptr -> tx_thread_smp_core_mapped = ((UINT) 0); + } + else + { + + /* No, we need set the last mapped core to a valid core. */ + TX_LOWEST_SET_BIT_CALCULATE(available_cores, new_mapped_core) + + /* Now setup the last core mapped. */ + thread_ptr -> tx_thread_smp_core_mapped = new_mapped_core; + } + } + +#ifdef TX_THREAD_SMP_DEBUG_ENABLE + + /* Determine if the thread is in a ready state. */ + if (thread_ptr -> tx_thread_state != TX_READY) + { + + + /* Debug entry. */ + _tx_thread_smp_debug_entry_insert(3, 0, thread_ptr); + + } +#endif + + /* Determine if the thread is ready. */ + if (thread_ptr -> tx_thread_state == TX_READY) + { + + /* Pickup the index. */ + core_index = TX_SMP_CORE_ID; + + /* Call the rebalance routine. This routine maps cores and ready threads. */ + _tx_thread_smp_rebalance_execute_list(core_index); + +#ifdef TX_THREAD_SMP_DEBUG_ENABLE + + /* Debug entry. */ + _tx_thread_smp_debug_entry_insert(3, 0, thread_ptr); +#endif + + /* Determine if this thread needs to return to the system. */ + + /* Is there a difference between the current and execute thread pointers? */ + if (_tx_thread_execute_ptr[core_index] != _tx_thread_current_ptr[core_index]) + { + + /* Yes, check to see if we are at the thread level. */ + if (_tx_thread_system_state[core_index] == ((ULONG) 0)) + { + + /* At the thread level, check for the preempt disable flag being set. */ + if (_tx_thread_preempt_disable == ((UINT) 0)) + { + +#ifndef TX_NOT_INTERRUPTABLE + + /* Increment the preempt disable flag in order to keep the protection. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE +#endif + + /* Transfer control to the system so the scheduler can execute + the next thread. */ + _tx_thread_system_return(); + +#ifdef TX_NOT_INTERRUPTABLE + + /* Restore interrupts. */ + TX_RESTORE +#endif + + /* Clear the restore needed flag, since the interrupt poster/protection has been done. */ + restore_needed = TX_FALSE; + } + } + } + } + + /* Determine if the protection still needs to be restored. */ + if (restore_needed == TX_TRUE) + { + + /* Restore interrupts. */ + TX_RESTORE + } + } + + /* Return status. */ + return(status); +} + diff --git a/common_smp/src/tx_thread_smp_core_exclude_get.c b/common_smp/src/tx_thread_smp_core_exclude_get.c new file mode 100644 index 00000000..2ffce8b3 --- /dev/null +++ b/common_smp/src/tx_thread_smp_core_exclude_get.c @@ -0,0 +1,116 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - High Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_timer.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_core_exclude_get PROTABLE SMP */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function returns the current exclusion list. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to the thread */ +/* exclusion_map_ptr Destination for the current */ +/* exclusion list */ +/* */ +/* OUTPUT */ +/* */ +/* Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_thread_smp_core_exclude_get(TX_THREAD *thread_ptr, ULONG *exclusion_map_ptr) +{ + +UINT status; + + + /* First, make sure the thread pointer is valid. */ + if (thread_ptr == TX_NULL) + { + + /* Return pointer error. */ + status = TX_THREAD_ERROR; + } + + /* Check for valid ID. */ + else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) + { + + /* Return pointer error. */ + status = TX_THREAD_ERROR; + } + + /* Is the destination pointer NULL? */ + else if (exclusion_map_ptr == TX_NULL) + { + + /* Return pointer error. */ + status = TX_PTR_ERROR; + } + else + { + + /* Save the current exclusion map in the destination. */ + *exclusion_map_ptr = thread_ptr -> tx_thread_smp_cores_excluded; + + /* Return a successful status. */ + status = TX_SUCCESS; + } + + /* Return status. */ + return(status); +} + diff --git a/common_smp/src/tx_thread_smp_current_state_set.c b/common_smp/src/tx_thread_smp_current_state_set.c new file mode 100644 index 00000000..e1c0236d --- /dev/null +++ b/common_smp/src/tx_thread_smp_current_state_set.c @@ -0,0 +1,100 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - High Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_timer.h" +#include "tx_thread.h" + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_current_state_set PORTABLE SMP */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is sets the current state to all of the cores. */ +/* */ +/* INPUT */ +/* */ +/* new_state New per-system state */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +void _tx_thread_smp_current_state_set(ULONG new_state) +{ + +UINT i; + + /* Initialize the state for each to initialization. */ + i = ((UINT) (TX_THREAD_SMP_MAX_CORES-1)); + do + { + + /* Set this core's state. */ + _tx_thread_system_state[i] = new_state; + + if (i == ((UINT) 0)) + { + + /* We are finished, exit the loop. */ + break; + } + else + { + + /* Decrement the index. */ + i--; + } + } while (TX_LOOP_FOREVER); +} + diff --git a/common_smp/src/tx_thread_smp_debug_entry_insert.c b/common_smp/src/tx_thread_smp_debug_entry_insert.c new file mode 100644 index 00000000..4472dba5 --- /dev/null +++ b/common_smp/src/tx_thread_smp_debug_entry_insert.c @@ -0,0 +1,223 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_timer.h" +#include "tx_thread.h" + + +/* Determine if debugging is enabled. */ + +#ifdef TX_THREAD_SMP_DEBUG_ENABLE + + +/* Define the maximum number of debug entries. */ + +#ifndef TX_THREAD_SMP_MAX_DEBUG_ENTRIES +#define TX_THREAD_SMP_MAX_DEBUG_ENTRIES 100 +#endif + + +/* Define the debug information structures. */ + +typedef struct TX_THREAD_SMP_DEBUG_ENTRY_STRUCT +{ + + ULONG tx_thread_smp_debug_entry_id; + ULONG tx_thread_smp_debug_entry_suspend; + ULONG tx_thread_smp_debug_entry_core_index; + ULONG tx_thread_smp_debug_entry_time; + ULONG tx_thread_smp_debug_entry_timer_clock; + TX_THREAD *tx_thread_smp_debug_entry_thread; + UINT tx_thread_smp_debug_entry_thread_priority; + UINT tx_thread_smp_debug_entry_thread_threshold; + ULONG tx_thread_smp_debug_entry_thread_core_control; + TX_THREAD *tx_thread_smp_debug_entry_current_thread; + TX_THREAD_SMP_PROTECT tx_thread_smp_debug_protection; + ULONG tx_thread_smp_debug_entry_preempt_disable; + ULONG tx_thread_smp_debug_entry_system_state[TX_THREAD_SMP_MAX_CORES]; +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD + ULONG tx_thread_smp_debug_entry_preempt_map; +#endif + TX_THREAD *tx_thread_smp_debug_entry_preempt_thread; + ULONG tx_thread_smp_debug_entry_priority_map; + ULONG tx_thread_smp_debug_entry_reschedule_pending; + TX_THREAD *tx_thread_smp_debug_entry_current_threads[TX_THREAD_SMP_MAX_CORES]; + TX_THREAD *tx_thread_smp_debug_entry_execute_threads[TX_THREAD_SMP_MAX_CORES]; + +} TX_THREAD_SMP_DEBUG_ENTRY_INFO; + + +/* Define the circular array of debug entries. */ + +TX_THREAD_SMP_DEBUG_ENTRY_INFO _tx_thread_smp_debug_info_array[TX_THREAD_SMP_MAX_DEBUG_ENTRIES]; + + +/* Define the starting index. */ + +ULONG _tx_thread_smp_debug_info_current_index; + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_debug_entry_insert PORTABLE SMP */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for making an entry in the circular */ +/* debug log. */ +/* */ +/* INPUT */ +/* */ +/* id ID of event */ +/* suspend Flag set to true for suspend */ +/* events */ +/* thread_ptr Specified thread */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_smp_time_get Get global time stamp */ +/* */ +/* CALLED BY */ +/* */ +/* Internal routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +void _tx_thread_smp_debug_entry_insert(ULONG id, ULONG suspend, VOID *thread_void_ptr) +{ + +ULONG i; +ULONG core_index; +TX_THREAD_SMP_DEBUG_ENTRY_INFO *entry_ptr; +TX_THREAD *thread_ptr; + + + /* Spin, if an error is detected. No sense in populating the debug after the error occurs. */ + while (_tx_thread_smp_system_error) + { + + /* Spin here! */ + } + + /* Check for a bad current index. */ + while (_tx_thread_smp_debug_info_current_index >= TX_THREAD_SMP_MAX_DEBUG_ENTRIES) + { + + /* Spin here! */ + } + + thread_ptr = (TX_THREAD *) thread_void_ptr; + + /* It is assumed that interrupts are locked out at this point. */ + + /* Setup pointer to debug entry. */ + entry_ptr = &_tx_thread_smp_debug_info_array[_tx_thread_smp_debug_info_current_index++]; + + /* Check for wrap on the index. */ + if (_tx_thread_smp_debug_info_current_index >= TX_THREAD_SMP_MAX_DEBUG_ENTRIES) + { + + /* Wrap back to 0. */ + _tx_thread_smp_debug_info_current_index = 0; + } + + /* Get the index. */ + core_index = TX_SMP_CORE_ID; + + /* We know at this point that multithreading and interrupts are disabled... so start populating the array. */ + entry_ptr -> tx_thread_smp_debug_entry_id = id; + entry_ptr -> tx_thread_smp_debug_entry_suspend = suspend; + entry_ptr -> tx_thread_smp_debug_entry_thread = thread_ptr; + entry_ptr -> tx_thread_smp_debug_entry_time = _tx_thread_smp_time_get(); + entry_ptr -> tx_thread_smp_debug_entry_timer_clock = _tx_timer_system_clock; + entry_ptr -> tx_thread_smp_debug_entry_core_index = core_index; + entry_ptr -> tx_thread_smp_debug_entry_current_thread = _tx_thread_current_ptr[core_index]; + if (entry_ptr -> tx_thread_smp_debug_entry_current_thread) + { + + entry_ptr -> tx_thread_smp_debug_entry_thread_priority = (entry_ptr -> tx_thread_smp_debug_entry_current_thread) -> tx_thread_priority; + entry_ptr -> tx_thread_smp_debug_entry_thread_threshold = (entry_ptr -> tx_thread_smp_debug_entry_current_thread) -> tx_thread_preempt_threshold; + entry_ptr -> tx_thread_smp_debug_entry_thread_core_control = (entry_ptr -> tx_thread_smp_debug_entry_current_thread) -> tx_thread_smp_core_control; + } + else + { + + entry_ptr -> tx_thread_smp_debug_entry_thread_priority = 0; + entry_ptr -> tx_thread_smp_debug_entry_thread_threshold = 0; + entry_ptr -> tx_thread_smp_debug_entry_thread_core_control = 0; + } + + entry_ptr -> tx_thread_smp_debug_protection = _tx_thread_smp_protection; + entry_ptr -> tx_thread_smp_debug_entry_preempt_disable = _tx_thread_preempt_disable; +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD + entry_ptr -> tx_thread_smp_debug_entry_preempt_map = _tx_thread_preempted_maps[0]; +#endif + entry_ptr -> tx_thread_smp_debug_entry_preempt_thread = _tx_thread_preemption__threshold_scheduled; + entry_ptr -> tx_thread_smp_debug_entry_priority_map = _tx_thread_priority_maps[0]; + +#ifndef TX_THREAD_SMP_DYNAMIC_CORE_MAX + + /* Loop to save the current and execute lists. */ + for (i = 0; i < TX_THREAD_SMP_MAX_CORES; i++) +#else + + /* Loop to save the current and execute lists. */ + for (i = 0; i < _tx_thread_smp_max_cores; i++) +#endif + { + + /* Save the pointers. */ + entry_ptr -> tx_thread_smp_debug_entry_current_threads[i] = _tx_thread_current_ptr[i]; + entry_ptr -> tx_thread_smp_debug_entry_execute_threads[i] = _tx_thread_execute_ptr[i]; + + /* Save the system state. */ + entry_ptr -> tx_thread_smp_debug_entry_system_state[i] = _tx_thread_system_state[i]; + } +} + + +#endif + diff --git a/common_smp/src/tx_thread_smp_high_level_initialize.c b/common_smp/src/tx_thread_smp_high_level_initialize.c new file mode 100644 index 00000000..dd8d6547 --- /dev/null +++ b/common_smp/src/tx_thread_smp_high_level_initialize.c @@ -0,0 +1,118 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialization */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_timer.h" +#include "tx_thread.h" + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_high_level_initialize PORTABLE SMP */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes the ThreadX SMP data structures and */ +/* CPU registers. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +void _tx_thread_smp_high_level_initialize(void) +{ + + /* Clear the system error flag. */ + _tx_thread_smp_system_error = TX_FALSE; + + /* Ensure that the system state variable is set to indicate + initialization is in progress. Note that this variable is + later used to represent interrupt nesting. */ + _tx_thread_smp_current_state_set(TX_INITIALIZE_IN_PROGRESS); + + /* Clear the thread protection. */ + TX_MEMSET(&_tx_thread_smp_protection, 0, sizeof(TX_THREAD_SMP_PROTECT)); + + /* Set the field of the protection to all ones to indicate it is invalid. */ + _tx_thread_smp_protection.tx_thread_smp_protect_core = ((ULONG) 0xFFFFFFFFUL); + + /* Clear the thread schedule list. */ + TX_MEMSET(&_tx_thread_smp_schedule_list[0], 0, sizeof(_tx_thread_smp_schedule_list)); + + /* Initialize core list. */ + TX_MEMSET(&_tx_thread_smp_protect_wait_list[0], 0xff, sizeof(_tx_thread_smp_protect_wait_list)); + + /* Set the wait list size so we can access it from assembly functions. */ + _tx_thread_smp_protect_wait_list_size = TX_THREAD_SMP_PROTECT_WAIT_LIST_SIZE; + +#ifndef TX_THREAD_SMP_DYNAMIC_CORE_MAX + + /* Call low-level SMP initialize. */ + _tx_thread_smp_low_level_initialize(((UINT) TX_THREAD_SMP_MAX_CORES)); +#else + + /* Determine if the dynamic maximum number of cores is 0. If so, default it + to the compile-time maximum. */ + if (_tx_thread_smp_max_cores == 0) + { + + /* Default to the compile-time maximum. */ + _tx_thread_smp_max_cores = TX_THREAD_SMP_MAX_CORES; + } + + /* Call low-level SMP initialize. */ + _tx_thread_smp_low_level_initialize(_tx_thread_smp_max_cores); +#endif +} diff --git a/common_smp/src/tx_thread_smp_rebalance_execute_list.c b/common_smp/src/tx_thread_smp_rebalance_execute_list.c new file mode 100644 index 00000000..04be5d8d --- /dev/null +++ b/common_smp/src/tx_thread_smp_rebalance_execute_list.c @@ -0,0 +1,581 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - High Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_timer.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_rebalance_execute_list PORTABLE SMP */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for mapping ready ThreadX threads with */ +/* cores in the SMP . The basic idea is the standard ThreadX */ +/* ready list is traversed to build the _tx_thread_execute_ptr list. */ +/* Each index represents the and the corresponding entry in this */ +/* array contains the thread that should be executed by that core. If */ +/* the was previously running a different thread, it will be */ +/* preempted and restarted so it can run the new thread. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_smp_execute_list_clear Clear the thread execute list */ +/* _tx_thread_smp_execute_list_setup Setup the thread execute list */ +/* _tx_thread_smp_next_priority_find Find next priority with one */ +/* or more ready threads */ +/* _tx_thread_smp_remap_solution_find Attempt to remap threads to */ +/* schedule another thread */ +/* _tx_thread_smp_schedule_list_clear Clear the thread schedule list*/ +/* */ +/* CALLED BY */ +/* */ +/* _tx_mutex_priority_change Mutex priority change */ +/* _tx_thread_create Thread create */ +/* _tx_thread_preemption_change Thread preemption change */ +/* _tx_thread_priority_change Thread priority change */ +/* _tx_thread_relinquish Thread relinquish */ +/* _tx_thread_resume Thread resume */ +/* _tx_thread_smp_core_exclude Thread SMP core exclude */ +/* _tx_thread_system_resume Thread system resume */ +/* _tx_thread_system_suspend Thread suspend */ +/* _tx_thread_time_slice Thread time-slice */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +void _tx_thread_smp_rebalance_execute_list(UINT core_index) +{ + +UINT i, j, core; +UINT next_priority; +UINT last_priority; +TX_THREAD *schedule_thread; +#ifdef TX_THREAD_ENABLE_PERFORMANCE_INFO +TX_THREAD *mapped_thread; +#endif +TX_THREAD *preempted_thread; +ULONG possible_cores; +ULONG thread_possible_cores; +ULONG available_cores; +ULONG test_possible_cores; +ULONG test_cores; +UINT this_pass_complete; +UINT loop_finished; + +#ifdef TX_THREAD_SMP_EQUAL_PRIORITY +TX_THREAD *highest_priority_thread; +#endif +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD +ULONG priority_bit; +#if TX_MAX_PRIORITIES > 32 +UINT map_index; +#endif +#endif + + + /* It is assumed that the preempt disable flag is still set at this point. */ + + /* Pickup the last schedule thread with preemption-threshold enabled. */ + preempted_thread = _tx_thread_preemption__threshold_scheduled; + + /* Clear the schedule list. */ + _tx_thread_smp_schedule_list_clear(); + + /* Initialize the next priority to 0, the highest priority. */ + next_priority = ((UINT) 0); + + /* Initialize the last priority. */ + last_priority = ((UINT) 0); + +#ifndef TX_THREAD_SMP_DYNAMIC_CORE_MAX + + /* Set the possible cores bit map to all cores. */ + possible_cores = ((ULONG) TX_THREAD_SMP_CORE_MASK); +#else + + /* Set the possible cores bit map to all cores. */ + possible_cores = (((ULONG) 1) << _tx_thread_smp_max_cores) - 1; +#endif + + /* Setup the available cores bit map. */ + available_cores = possible_cores; + + /* Clear the schedule thread pointer. */ + schedule_thread = TX_NULL; + +#ifdef TX_THREAD_SMP_EQUAL_PRIORITY + + /* Set the highest priority thread to NULL. */ + highest_priority_thread = TX_NULL; +#endif + + /* Loop to rebuild the schedule list. */ + i = ((UINT) 0); + loop_finished = TX_FALSE; + do + { + + /* Clear the pass complete flag, which is used to skip the remaining processing + of this loop on certain conditions. */ + this_pass_complete = TX_FALSE; + + /* Determine if there is a thread to schedule. */ + if (schedule_thread == TX_NULL) + { + + /* Calculate the next ready priority. */ + next_priority = _tx_thread_smp_next_priority_find(next_priority); + + /* Determine if there are no more threads to execute. */ + if (next_priority == ((UINT) TX_MAX_PRIORITIES)) + { + + /* Break out of loop. */ + loop_finished = TX_TRUE; + this_pass_complete = TX_TRUE; + } + else + { + + /* Determine if a thread was executed with preemption-threshold set. */ + if (preempted_thread != TX_NULL) + { + + /* Yes, a thread was previously preempted. Let's first see if we reached the + interrupted preemption-threshold level. */ + if (next_priority >= preempted_thread -> tx_thread_preempt_threshold) + { + + /* Yes, now lets see if we are within the preemption-threshold level. */ + if (next_priority <= preempted_thread -> tx_thread_priority) + { + + /* Yes, move the next priority to the preempted priority. */ + next_priority = preempted_thread -> tx_thread_priority; + + /* Setup the schedule thread to the preempted thread. */ + schedule_thread = preempted_thread; + + /* Start at the top of the loop. */ + this_pass_complete = TX_TRUE; + } + else + { + + /* Nothing else is allowed to execute after the preemption-threshold thread. */ + next_priority = ((UINT) TX_MAX_PRIORITIES); + + /* Break out of loop. */ + loop_finished = TX_TRUE; + this_pass_complete = TX_TRUE; + } + } + } + } + + /* Determine if this pass through the loop is already complete. */ + if (this_pass_complete == TX_FALSE) + { + + /* Pickup the next thread to schedule. */ + schedule_thread = _tx_thread_priority_list[next_priority]; + } + } + + /* Determine if this pass through the loop is already complete. */ + if (this_pass_complete == TX_FALSE) + { + + /* Determine what the possible cores are for this thread. */ + thread_possible_cores = schedule_thread -> tx_thread_smp_cores_allowed; + + /* Apply the current possible cores. */ + thread_possible_cores = thread_possible_cores & (available_cores | possible_cores); + + /* Determine if it is possible to schedule this thread. */ + if (thread_possible_cores == ((ULONG) 0)) + { + + /* No, this thread can't be scheduled. */ + + /* Look at the next thread at the same priority level. */ + schedule_thread = schedule_thread -> tx_thread_ready_next; + + /* Determine if this is the head of the list. */ + if (schedule_thread == _tx_thread_priority_list[next_priority]) + { + + /* Set the schedule thread to NULL to force examination of the next priority level. */ + schedule_thread = TX_NULL; + + /* Move to the next priority level. */ + next_priority++; + + /* Determine if there are no more threads to execute. */ + if (next_priority == ((UINT) TX_MAX_PRIORITIES)) + { + + /* Break out of loop. */ + loop_finished = TX_TRUE; + } + } + } + else + { + + /* It is possible to schedule this thread. */ + + /* Determine if this thread has preemption-threshold set. */ + if (schedule_thread -> tx_thread_preempt_threshold < schedule_thread -> tx_thread_priority) + { + + /* Yes, preemption-threshold is set. */ + + /* Determine if the last priority is above the preemption-threshold. If not, we can't + schedule this thread with preemption-threshold set. */ + if ((last_priority >= schedule_thread -> tx_thread_preempt_threshold) && (i != ((UINT) 0))) + { + + /* A thread was found that violates the next thread to be scheduled's preemption-threshold. We will simply + skip this thread and see if there is anything else we can schedule. */ + + /* Look at the next thread at the same priority level. */ + schedule_thread = schedule_thread -> tx_thread_ready_next; + + /* Determine if this is the head of the list. */ + if (schedule_thread == _tx_thread_priority_list[next_priority]) + { + + /* Set the schedule thread to NULL to force examination of the next priority level. */ + schedule_thread = TX_NULL; + + /* Move to the next priority level. */ + next_priority++; + + /* Determine if there are no more threads to execute. */ + if (next_priority == ((UINT) TX_MAX_PRIORITIES)) + { + + /* Break out of loop. */ + loop_finished = TX_TRUE; + } + } + + /* Restart the loop. */ + this_pass_complete = TX_TRUE; + } + } + + /* Determine if this pass through the loop is already complete. */ + if (this_pass_complete == TX_FALSE) + { + +#ifdef TX_THREAD_ENABLE_PERFORMANCE_INFO + + /* Initialize index to an invalid value. */ + j = ((UINT) TX_THREAD_SMP_MAX_CORES); +#endif + + /* Determine if there is an available core for this thread to execute on. */ + if ((thread_possible_cores & available_cores) != ((ULONG) 0)) + { + + /* Pickup the last executed core for this thread. */ + j = schedule_thread -> tx_thread_smp_core_mapped; + + /* Is this core valid and available? */ + if ((thread_possible_cores & available_cores & (((ULONG) 1) << j)) == ((ULONG) 0)) + { + + /* No, we must find the next core for this thread. */ + test_cores = (thread_possible_cores & available_cores); + TX_LOWEST_SET_BIT_CALCULATE(test_cores, j) + + /* Setup the last executed core for this thread. */ + schedule_thread -> tx_thread_smp_core_mapped = j; + } + + /* Place the this thread on this core. */ + _tx_thread_smp_schedule_list[j] = schedule_thread; + + /* Clear the associated available cores bit. */ + available_cores = available_cores & ~(((ULONG) 1) << j); + } + else + { + + /* Note that we know that the thread must have at least one core excluded at this point, + since we didn't find a match and we have available cores. */ + + /* Now we need to see if one of the other threads in the non-excluded cores can be moved to make room + for this thread. */ + + /* Determine the possible core remapping attempt. */ + test_possible_cores = possible_cores & ~(thread_possible_cores); + + /* Attempt to remap the cores in order to schedule this thread. */ + core = _tx_thread_smp_remap_solution_find(schedule_thread, available_cores, thread_possible_cores, test_possible_cores); + + /* Determine if remapping was successful. */ + if (core != ((UINT) TX_THREAD_SMP_MAX_CORES)) + { + + /* Yes, remapping was successful. Update the available cores accordingly. */ + available_cores = available_cores & ~(((ULONG) 1) << core); + } + else + { + + /* We couldn't assign the thread to any of the cores possible for the thread. */ + + /* Check to see if the thread is the last thread preempted. */ + if (schedule_thread == preempted_thread) + { + + /* To honor the preemption-threshold, we cannot schedule any more threads. */ + loop_finished = TX_TRUE; + } + else + { + + /* update the available cores for the next pass so we don't waste time looking at them again! */ + possible_cores = possible_cores & (~thread_possible_cores); + + /* No, we couldn't load the thread because none of the required cores were available. Look at the next thread at the same priority level. */ + schedule_thread = schedule_thread -> tx_thread_ready_next; + + /* Determine if this is the head of the list. */ + if (schedule_thread == _tx_thread_priority_list[next_priority]) + { + + /* Set the schedule thread to NULL to force examination of the next priority level. */ + schedule_thread = TX_NULL; + + /* Move to the next priority level. */ + next_priority++; + + /* Determine if there are no more threads to execute. */ + if (next_priority == ((UINT) TX_MAX_PRIORITIES)) + { + + /* Break out of loop. */ + loop_finished = TX_TRUE; + } + } + } + + /* Restart the loop. */ + this_pass_complete = TX_TRUE; + } + } + + /* Determine if this pass through the loop is already complete. */ + if (this_pass_complete == TX_FALSE) + { + +#ifdef TX_THREAD_SMP_EQUAL_PRIORITY + + /* Determine if this is the highest priority thread. */ + if (highest_priority_thread == TX_NULL) + { + + /* No highest priority yet, remember this thread. */ + highest_priority_thread = schedule_thread; + } +#endif + + /* Increment the number of threads loaded. */ + i++; + +#ifdef TX_THREAD_ENABLE_PERFORMANCE_INFO + + /* Determine if the thread was mapped. */ + if (j != ((UINT) TX_THREAD_SMP_MAX_CORES)) + { + + /* Pickup the currently mapped thread. */ + mapped_thread = _tx_thread_execute_ptr[j]; + + /* Determine if preemption is present. */ + if ((mapped_thread != TX_NULL) && (schedule_thread != mapped_thread)) + { + + /* Determine if the previously mapped thread is still ready. */ + if (mapped_thread -> tx_thread_state == TX_READY) + { + + /* Determine if the caller is an interrupt or from a thread. */ + if (_tx_thread_system_state[core_index] == ((ULONG) 0)) + { + + /* Caller is a thread, so this is a solicited preemption. */ + _tx_thread_performance_solicited_preemption_count++; + + /* Increment the thread's solicited preemption counter. */ + mapped_thread -> tx_thread_performance_solicited_preemption_count++; + } + else + { + + /* Is this an interrupt? */ + if (_tx_thread_system_state[core_index] < TX_INITIALIZE_IN_PROGRESS) + { + + /* Caller is an interrupt, so this is an interrupt preemption. */ + _tx_thread_performance_interrupt_preemption_count++; + + /* Increment the thread's interrupt preemption counter. */ + mapped_thread -> tx_thread_performance_interrupt_preemption_count++; + } + } + } + } + } +#endif + + /* Determine if this thread has preemption-threshold set. */ + if (schedule_thread -> tx_thread_preempt_threshold < schedule_thread -> tx_thread_priority) + { + +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD + + /* mark the bit map to show that a thread with preemption-threshold has been executed. */ +#if TX_MAX_PRIORITIES > 32 + + /* Calculate the index into the bit map array. */ + map_index = (schedule_thread -> tx_thread_priority)/((UINT) 32); + + /* Set the active bit to remember that the preempt map has something set. */ + TX_DIV32_BIT_SET(schedule_thread -> tx_thread_priority, priority_bit) + _tx_thread_preempted_map_active = _tx_thread_preempted_map_active | priority_bit; +#endif + + /* Remember that this thread was executed with preemption-threshold set. */ + TX_MOD32_BIT_SET(schedule_thread -> tx_thread_priority, priority_bit) + _tx_thread_preempted_maps[MAP_INDEX] = _tx_thread_preempted_maps[MAP_INDEX] | priority_bit; + + /* Place the thread in the preempted list indicating preemption-threshold is in force. */ + _tx_thread_preemption_threshold_list[schedule_thread -> tx_thread_priority] = schedule_thread; +#endif + + /* Set the last thread with preemption-threshold enabled. */ + _tx_thread_preemption__threshold_scheduled = schedule_thread; + + /* Now break out of the scheduling loop. */ + loop_finished = TX_TRUE; + } + else + { + + /* Remember the last priority. */ + last_priority = next_priority; + + /* Pickup the next ready thread at the current priority level. */ + schedule_thread = schedule_thread -> tx_thread_ready_next; + + /* Determine if this is the head of the list, which implies that we have exhausted this priority level. */ + if (schedule_thread == _tx_thread_priority_list[next_priority]) + { + + /* Set the schedule thread to NULL to force examination of the next priority level. */ + schedule_thread = TX_NULL; + + /* Move to the next priority level. */ + next_priority++; + +#ifdef TX_THREAD_SMP_EQUAL_PRIORITY + + /* Determine if there is a highest priority thread. */ + if (highest_priority_thread) + { + + /* Yes, break out of the loop, since only same priority threads can be + scheduled in this mode. */ + loop_finished = TX_TRUE; + } +#endif + + /* Determine if there are no more threads to execute. */ + if (next_priority == ((UINT) TX_MAX_PRIORITIES)) + { + + /* Break out of loop. */ + loop_finished = TX_TRUE; + } + } + } + } + } + } + } + + /* Determine if the loop is finished. */ + if (loop_finished == TX_TRUE) + { + + /* Finished, break the loop. */ + break; + } + +#ifndef TX_THREAD_SMP_DYNAMIC_CORE_MAX + + } while (i < ((UINT) TX_THREAD_SMP_MAX_CORES)); +#else + + } while (i < _tx_thread_smp_max_cores); +#endif + + /* Clear the execute list. */ + _tx_thread_smp_execute_list_clear(); + + /* Setup the execute list based on the updated schedule list. */ + _tx_thread_smp_execute_list_setup(core_index); +} + diff --git a/common_smp/src/tx_thread_smp_utilities.c b/common_smp/src/tx_thread_smp_utilities.c new file mode 100644 index 00000000..f7b5749b --- /dev/null +++ b/common_smp/src/tx_thread_smp_utilities.c @@ -0,0 +1,1120 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + + +#ifdef TX_DISABLE_INLINE + +/* Define the routine to calculate the lowest set bit. */ + +UINT _tx_thread_lowest_set_bit_calculate(ULONG map) +{ +UINT bit_set; + + if ((map & ((ULONG) 0x1)) != ((ULONG) 0)) + { + bit_set = ((UINT) 0); + } + else + { + map = map & (ULONG) ((~map) + ((ULONG) 1)); + if (map < ((ULONG) 0x100)) + { + bit_set = ((UINT) 1); + } + else if (map < ((ULONG) 0x10000)) + { + bit_set = ((UINT) 9); + map = map >> ((UINT) 8); + } + else if (map < ((ULONG) 0x01000000)) + { + bit_set = ((UINT) 17); + map = map >> ((UINT) 16); + } + else + { + bit_set = ((UINT) 25); + map = map >> ((UINT) 24); + } + if (map >= ((ULONG) 0x10)) + { + map = map >> ((UINT) 4); + bit_set = bit_set + ((UINT) 4); + } + if (map >= ((ULONG) 0x4)) + { + map = map >> ((UINT) 2); + bit_set = bit_set + ((UINT) 2); + } + bit_set = bit_set - (UINT) (map & (ULONG) 0x1); + } + + return(bit_set); +} + + +/* Define the next priority macro. Note, that this may be overridden + by a port specific definition. */ + +#if TX_MAX_PRIORITIES > 32 + +UINT _tx_thread_smp_next_priority_find(UINT priority) +{ +ULONG map_index; +ULONG local_priority_map_active; +ULONG local_priority_map; +ULONG priority_bit; +ULONG first_bit_set; +ULONG found_priority; + + found_priority = ((UINT) TX_MAX_PRIORITIES); + if (priority < ((UINT) TX_MAX_PRIORITIES)) + { + map_index = priority/((UINT) 32); + local_priority_map = _tx_thread_priority_maps[map_index]; + priority_bit = (((ULONG) 1) << (priority % ((UINT) 32))); + local_priority_map = local_priority_map & ~(priority_bit - ((UINT)1)); + if (local_priority_map != ((ULONG) 0)) + { + TX_LOWEST_SET_BIT_CALCULATE(local_priority_map, first_bit_set) + found_priority = (map_index * ((UINT) 32)) + first_bit_set; + } + else + { + /* Move to next map index. */ + map_index++; + if (map_index < (((UINT) TX_MAX_PRIORITIES)/((UINT) 32))) + { + priority_bit = (((ULONG) 1) << (map_index)); + local_priority_map_active = _tx_thread_priority_map_active & ~(priority_bit - ((UINT) 1)); + if (local_priority_map_active != ((ULONG) 0)) + { + TX_LOWEST_SET_BIT_CALCULATE(local_priority_map_active, map_index) + local_priority_map = _tx_thread_priority_maps[map_index]; + TX_LOWEST_SET_BIT_CALCULATE(local_priority_map, first_bit_set) + found_priority = (map_index * ((UINT) 32)) + first_bit_set; + } + } + } + } + return(found_priority); +} +#else + +UINT _tx_thread_smp_next_priority_find(UINT priority) +{ +UINT first_bit_set; +ULONG local_priority_map; +UINT next_priority; + + local_priority_map = _tx_thread_priority_maps[0]; + local_priority_map = local_priority_map >> priority; + next_priority = priority; + if (local_priority_map == ((ULONG) 0)) + { + next_priority = ((UINT) TX_MAX_PRIORITIES); + } + else + { + if (next_priority >= ((UINT) TX_MAX_PRIORITIES)) + { + next_priority = ((UINT) TX_MAX_PRIORITIES); + } + else + { + TX_LOWEST_SET_BIT_CALCULATE(local_priority_map, first_bit_set) + next_priority = priority + first_bit_set; + } + } + + return(next_priority); +} +#endif + + +void _tx_thread_smp_schedule_list_clear(void) +{ +#if TX_THREAD_SMP_MAX_CORES > 6 +UINT i; +#endif + + + /* Clear the schedule list. */ + _tx_thread_smp_schedule_list[0] = TX_NULL; +#if TX_THREAD_SMP_MAX_CORES > 1 + _tx_thread_smp_schedule_list[1] = TX_NULL; +#if TX_THREAD_SMP_MAX_CORES > 2 + _tx_thread_smp_schedule_list[2] = TX_NULL; +#if TX_THREAD_SMP_MAX_CORES > 3 + _tx_thread_smp_schedule_list[3] = TX_NULL; +#if TX_THREAD_SMP_MAX_CORES > 4 + _tx_thread_smp_schedule_list[4] = TX_NULL; +#if TX_THREAD_SMP_MAX_CORES > 5 + _tx_thread_smp_schedule_list[5] = TX_NULL; +#if TX_THREAD_SMP_MAX_CORES > 6 + + /* Loop to clear the remainder of the schedule list. */ + i = ((UINT) 6); + +#ifndef TX_THREAD_SMP_DYNAMIC_CORE_MAX + + while (i < ((UINT) TX_THREAD_SMP_MAX_CORES)) +#else + + while (i < _tx_thread_smp_max_cores) +#endif + { + /* Clear entry in schedule list. */ + _tx_thread_smp_schedule_list[i] = TX_NULL; + + /* Move to next index. */ + i++; + } +#endif +#endif +#endif +#endif +#endif +#endif +} + +VOID _tx_thread_smp_execute_list_clear(void) +{ +#if TX_THREAD_SMP_MAX_CORES > 6 +UINT j; +#endif + + /* Clear the execute list. */ + _tx_thread_execute_ptr[0] = TX_NULL; +#if TX_THREAD_SMP_MAX_CORES > 1 + _tx_thread_execute_ptr[1] = TX_NULL; +#if TX_THREAD_SMP_MAX_CORES > 2 + _tx_thread_execute_ptr[2] = TX_NULL; +#if TX_THREAD_SMP_MAX_CORES > 3 + _tx_thread_execute_ptr[3] = TX_NULL; +#if TX_THREAD_SMP_MAX_CORES > 4 + _tx_thread_execute_ptr[4] = TX_NULL; +#if TX_THREAD_SMP_MAX_CORES > 5 + _tx_thread_execute_ptr[5] = TX_NULL; +#if TX_THREAD_SMP_MAX_CORES > 6 + + /* Loop to clear the remainder of the execute list. */ + j = ((UINT) 6); + +#ifndef TX_THREAD_SMP_DYNAMIC_CORE_MAX + + while (j < ((UINT) TX_THREAD_SMP_MAX_CORES)) +#else + + while (j < _tx_thread_smp_max_cores) +#endif + { + + /* Clear entry in execute list. */ + _tx_thread_execute_ptr[j] = TX_NULL; + + /* Move to next index. */ + j++; + } +#endif +#endif +#endif +#endif +#endif +#endif +} + + +VOID _tx_thread_smp_schedule_list_setup(void) +{ +#if TX_THREAD_SMP_MAX_CORES > 6 +UINT j; +#endif + + _tx_thread_smp_schedule_list[0] = _tx_thread_execute_ptr[0]; +#if TX_THREAD_SMP_MAX_CORES > 1 + _tx_thread_smp_schedule_list[1] = _tx_thread_execute_ptr[1]; +#if TX_THREAD_SMP_MAX_CORES > 2 + _tx_thread_smp_schedule_list[2] = _tx_thread_execute_ptr[2]; +#if TX_THREAD_SMP_MAX_CORES > 3 + _tx_thread_smp_schedule_list[3] = _tx_thread_execute_ptr[3]; +#if TX_THREAD_SMP_MAX_CORES > 4 + _tx_thread_smp_schedule_list[4] = _tx_thread_execute_ptr[4]; +#if TX_THREAD_SMP_MAX_CORES > 5 + _tx_thread_smp_schedule_list[5] = _tx_thread_execute_ptr[5]; +#if TX_THREAD_SMP_MAX_CORES > 6 + + /* Loop to setup the remainder of the schedule list. */ + j = ((UINT) 6); + +#ifndef TX_THREAD_SMP_DYNAMIC_CORE_MAX + while (j < ((UINT) TX_THREAD_SMP_MAX_CORES)) +#else + + while (j < _tx_thread_smp_max_cores) +#endif + { + + /* Setup entry in schedule list. */ + _tx_thread_smp_schedule_list[j] = _tx_thread_execute_ptr[j]; + + /* Move to next index. */ + j++; + } +#endif +#endif +#endif +#endif +#endif +#endif +} + + +#ifdef TX_THREAD_SMP_INTER_CORE_INTERRUPT +VOID _tx_thread_smp_core_interrupt(TX_THREAD *thread_ptr, UINT current_core, UINT target_core) +{ + +TX_THREAD *current_thread; + + + /* Make sure this is a different core, since there is no need to interrupt the current core for + a scheduling change. */ + if (current_core != target_core) + { + + /* Yes, a different core is present. */ + + /* Pickup the currently executing thread. */ + current_thread = _tx_thread_current_ptr[target_core]; + + /* Determine if they are the same. */ + if ((current_thread != TX_NULL) && (thread_ptr != current_thread)) + { + + /* Not the same and not NULL... determine if the core is running at thread level. */ + if (_tx_thread_system_state[target_core] < TX_INITIALIZE_IN_PROGRESS) + { + + /* Preempt the mapped thread. */ + _tx_thread_smp_core_preempt(target_core); + } + } + } +} +#endif + + +#ifdef TX_THREAD_SMP_WAKEUP_LOGIC +VOID _tx_thread_smp_core_wakeup(UINT current_core, UINT target_core) +{ + + /* Determine if the core specified is not the current core - no need to wakeup the + current core. */ + if (target_core != current_core) + { + + /* Wakeup based on application's macro. */ + TX_THREAD_SMP_WAKEUP(target_core); + } +} +#endif + + +VOID _tx_thread_smp_execute_list_setup(UINT core_index) +{ + +TX_THREAD *schedule_thread; +UINT i; + + + /* Loop to copy the schedule list into the execution list. */ + i = ((UINT) 0); +#ifndef TX_THREAD_SMP_DYNAMIC_CORE_MAX + + while (i < ((UINT) TX_THREAD_SMP_MAX_CORES)) +#else + + while (i < _tx_thread_smp_max_cores) +#endif + { + + /* Pickup the thread to schedule. */ + schedule_thread = _tx_thread_smp_schedule_list[i]; + + /* Copy the schedule list into the execution list. */ + _tx_thread_execute_ptr[i] = schedule_thread; + + /* If necessary, interrupt the core with the new thread to schedule. */ + _tx_thread_smp_core_interrupt(schedule_thread, core_index, i); + +#ifdef TX_THREAD_SMP_WAKEUP_LOGIC + + /* Does this need to be waked up? */ + if ((i != core_index) && (schedule_thread != TX_NULL)) + { + + /* Wakeup based on application's macro. */ + TX_THREAD_SMP_WAKEUP(i); + } +#endif + /* Move to next index. */ + i++; + } +} + + +ULONG _tx_thread_smp_available_cores_get(void) +{ + +#if TX_THREAD_SMP_MAX_CORES > 6 +UINT j; +#endif +ULONG available_cores; + + available_cores = ((ULONG) 0); + if (_tx_thread_execute_ptr[0] == TX_NULL) + { + available_cores = ((ULONG) 1); + } +#if TX_THREAD_SMP_MAX_CORES > 1 + if (_tx_thread_execute_ptr[1] == TX_NULL) + { + available_cores = available_cores | ((ULONG) 2); + } +#if TX_THREAD_SMP_MAX_CORES > 2 + if (_tx_thread_execute_ptr[2] == TX_NULL) + { + available_cores = available_cores | ((ULONG) 4); + } +#if TX_THREAD_SMP_MAX_CORES > 3 + if (_tx_thread_execute_ptr[3] == TX_NULL) + { + available_cores = available_cores | ((ULONG) 8); + } +#if TX_THREAD_SMP_MAX_CORES > 4 + if (_tx_thread_execute_ptr[4] == TX_NULL) + { + available_cores = available_cores | ((ULONG) 0x10); + } +#if TX_THREAD_SMP_MAX_CORES > 5 + if (_tx_thread_execute_ptr[5] == TX_NULL) + { + available_cores = available_cores | ((ULONG) 0x20); + } +#if TX_THREAD_SMP_MAX_CORES > 6 + + /* Loop to setup the remainder of the schedule list. */ + j = ((UINT) 6); + +#ifndef TX_THREAD_SMP_DYNAMIC_CORE_MAX + while (j < ((UINT) TX_THREAD_SMP_MAX_CORES)) +#else + + while (j < _tx_thread_smp_max_cores) +#endif + { + + /* Determine if this core is available. */ + if (_tx_thread_execute_ptr[j] == TX_NULL) + { + available_cores = available_cores | (((ULONG) 1) << j); + } + + /* Move to next core. */ + j++; + } +#endif +#endif +#endif +#endif +#endif +#endif + return(available_cores); +} + + +ULONG _tx_thread_smp_possible_cores_get(void) +{ + +#if TX_THREAD_SMP_MAX_CORES > 6 +UINT j; +#endif +ULONG possible_cores; +TX_THREAD *thread_ptr; + + possible_cores = ((ULONG) 0); + thread_ptr = _tx_thread_execute_ptr[0]; + if (thread_ptr != TX_NULL) + { + possible_cores = thread_ptr -> tx_thread_smp_cores_allowed; + } +#if TX_THREAD_SMP_MAX_CORES > 1 + thread_ptr = _tx_thread_execute_ptr[1]; + if (thread_ptr != TX_NULL) + { + possible_cores = possible_cores | thread_ptr -> tx_thread_smp_cores_allowed; + } +#if TX_THREAD_SMP_MAX_CORES > 2 + thread_ptr = _tx_thread_execute_ptr[2]; + if (thread_ptr != TX_NULL) + { + possible_cores = possible_cores | thread_ptr -> tx_thread_smp_cores_allowed; + } +#if TX_THREAD_SMP_MAX_CORES > 3 + thread_ptr = _tx_thread_execute_ptr[3]; + if (thread_ptr != TX_NULL) + { + possible_cores = possible_cores | thread_ptr -> tx_thread_smp_cores_allowed; + } +#if TX_THREAD_SMP_MAX_CORES > 4 + thread_ptr = _tx_thread_execute_ptr[4]; + if (thread_ptr != TX_NULL) + { + possible_cores = possible_cores | thread_ptr -> tx_thread_smp_cores_allowed; + } +#if TX_THREAD_SMP_MAX_CORES > 5 + thread_ptr = _tx_thread_execute_ptr[5]; + if (thread_ptr != TX_NULL) + { + possible_cores = possible_cores | thread_ptr -> tx_thread_smp_cores_allowed; + } +#if TX_THREAD_SMP_MAX_CORES > 6 + + /* Loop to setup the remainder of the schedule list. */ + j = ((UINT) 6); + +#ifndef TX_THREAD_SMP_DYNAMIC_CORE_MAX + while (j < ((UINT) TX_THREAD_SMP_MAX_CORES)) +#else + + while (j < _tx_thread_smp_max_cores) +#endif + { + + /* Determine if this core is available. */ + thread_ptr = _tx_thread_execute_ptr[j]; + if (thread_ptr != TX_NULL) + { + possible_cores = possible_cores | thread_ptr -> tx_thread_smp_cores_allowed; + } + + /* Move to next core. */ + j++; + } +#endif +#endif +#endif +#endif +#endif +#endif + return(possible_cores); +} + + +UINT _tx_thread_smp_lowest_priority_get(void) +{ + +#if TX_THREAD_SMP_MAX_CORES > 6 +UINT j; +#endif +TX_THREAD *thread_ptr; +UINT lowest_priority; + + lowest_priority = ((UINT) 0); + thread_ptr = _tx_thread_execute_ptr[0]; + if (thread_ptr != TX_NULL) + { + if (thread_ptr -> tx_thread_priority > lowest_priority) + { + lowest_priority = thread_ptr -> tx_thread_priority; + } + } +#if TX_THREAD_SMP_MAX_CORES > 1 + thread_ptr = _tx_thread_execute_ptr[1]; + if (thread_ptr != TX_NULL) + { + if (thread_ptr -> tx_thread_priority > lowest_priority) + { + lowest_priority = thread_ptr -> tx_thread_priority; + } + } +#if TX_THREAD_SMP_MAX_CORES > 2 + thread_ptr = _tx_thread_execute_ptr[2]; + if (thread_ptr != TX_NULL) + { + if (thread_ptr -> tx_thread_priority > lowest_priority) + { + lowest_priority = thread_ptr -> tx_thread_priority; + } + } +#if TX_THREAD_SMP_MAX_CORES > 3 + thread_ptr = _tx_thread_execute_ptr[3]; + if (thread_ptr != TX_NULL) + { + if (thread_ptr -> tx_thread_priority > lowest_priority) + { + lowest_priority = thread_ptr -> tx_thread_priority; + } + } +#if TX_THREAD_SMP_MAX_CORES > 4 + thread_ptr = _tx_thread_execute_ptr[4]; + if (thread_ptr != TX_NULL) + { + if (thread_ptr -> tx_thread_priority > lowest_priority) + { + lowest_priority = thread_ptr -> tx_thread_priority; + } + } +#if TX_THREAD_SMP_MAX_CORES > 5 + thread_ptr = _tx_thread_execute_ptr[5]; + if (thread_ptr != TX_NULL) + { + if (thread_ptr -> tx_thread_priority > lowest_priority) + { + lowest_priority = thread_ptr -> tx_thread_priority; + } + } +#if TX_THREAD_SMP_MAX_CORES > 6 + + /* Loop to setup the remainder of the schedule list. */ + j = ((UINT) 6); + +#ifndef TX_THREAD_SMP_DYNAMIC_CORE_MAX + while (j < ((UINT) TX_THREAD_SMP_MAX_CORES)) +#else + + while (j < _tx_thread_smp_max_cores) +#endif + { + + /* Determine if this core has a thread scheduled. */ + thread_ptr = _tx_thread_execute_ptr[j]; + if (thread_ptr != TX_NULL) + { + + /* Is this the new lowest priority? */ + if (thread_ptr -> tx_thread_priority > lowest_priority) + { + lowest_priority = thread_ptr -> tx_thread_priority; + } + } + + /* Move to next core. */ + j++; + } +#endif +#endif +#endif +#endif +#endif +#endif + return(lowest_priority); +} + + +UINT _tx_thread_smp_remap_solution_find(TX_THREAD *schedule_thread, ULONG available_cores, ULONG thread_possible_cores, ULONG test_possible_cores) +{ + +UINT core; +UINT previous_core; +ULONG test_cores; +ULONG last_thread_cores; +UINT queue_first, queue_last; +UINT core_queue[TX_THREAD_SMP_MAX_CORES-1]; +TX_THREAD *thread_ptr; +TX_THREAD *last_thread; +TX_THREAD *thread_remap_list[TX_THREAD_SMP_MAX_CORES]; + + + /* Clear the last thread cores in the search. */ + last_thread_cores = ((ULONG) 0); + + /* Set the last thread pointer to NULL. */ + last_thread = TX_NULL; + + /* Setup the core queue indices. */ + queue_first = ((UINT) 0); + queue_last = ((UINT) 0); + + /* Build a list of possible cores for this thread to execute on, starting + with the previously mapped core. */ + core = schedule_thread -> tx_thread_smp_core_mapped; + if ((thread_possible_cores & (((ULONG) 1) << core)) != ((ULONG) 0)) + { + + /* Remember this potential mapping. */ + thread_remap_list[core] = schedule_thread; + core_queue[queue_last] = core; + + /* Move to next slot. */ + queue_last++; + + /* Clear this core. */ + thread_possible_cores = thread_possible_cores & ~(((ULONG) 1) << core); + } + + /* Loop to add additional possible cores. */ + while (thread_possible_cores != ((ULONG) 0)) + { + + /* Determine the first possible core. */ + test_cores = thread_possible_cores; + TX_LOWEST_SET_BIT_CALCULATE(test_cores, core) + + /* Clear this core. */ + thread_possible_cores = thread_possible_cores & ~(((ULONG) 1) << core); + + /* Remember this potential mapping. */ + thread_remap_list[core] = schedule_thread; + core_queue[queue_last] = core; + + /* Move to next slot. */ + queue_last++; + } + + /* Loop to evaluate the potential thread mappings, against what is already mapped. */ + do + { + + /* Pickup the next entry. */ + core = core_queue[queue_first]; + + /* Move to next slot. */ + queue_first++; + + /* Retrieve the thread from the current mapping. */ + thread_ptr = _tx_thread_smp_schedule_list[core]; + + /* Determine if there is a thread currently mapped to this core. */ + if (thread_ptr != TX_NULL) + { + + /* Determine the cores available for this thread. */ + thread_possible_cores = thread_ptr -> tx_thread_smp_cores_allowed; + thread_possible_cores = test_possible_cores & thread_possible_cores; + + /* Are there any possible cores for this thread? */ + if (thread_possible_cores != ((ULONG) 0)) + { + + /* Determine if there are cores available for this thread. */ + if ((thread_possible_cores & available_cores) != ((ULONG) 0)) + { + + /* Yes, remember the final thread and cores that are valid for this thread. */ + last_thread_cores = thread_possible_cores & available_cores; + last_thread = thread_ptr; + + /* We are done - get out of the loop! */ + break; + } + else + { + + /* Remove cores that will be added to the list. */ + test_possible_cores = test_possible_cores & ~(thread_possible_cores); + + /* Loop to add this thread to the potential mapping list. */ + do + { + + /* Calculate the core. */ + test_cores = thread_possible_cores; + TX_LOWEST_SET_BIT_CALCULATE(test_cores, core) + + /* Clear this core. */ + thread_possible_cores = thread_possible_cores & ~(((ULONG) 1) << core); + + /* Remember this thread for remapping. */ + thread_remap_list[core] = thread_ptr; + + /* Remember this core. */ + core_queue[queue_last] = core; + + /* Move to next slot. */ + queue_last++; + + } while (thread_possible_cores != ((ULONG) 0)); + } + } + } + } while (queue_first != queue_last); + + /* Was a remapping solution found? */ + if (last_thread != TX_NULL) + { + + /* Pickup the core of the last thread to remap. */ + core = last_thread -> tx_thread_smp_core_mapped; + + /* Pickup the thread from the remapping list. */ + thread_ptr = thread_remap_list[core]; + + /* Loop until we arrive at the thread we have been trying to map. */ + while (thread_ptr != schedule_thread) + { + + /* Move this thread in the schedule list. */ + _tx_thread_smp_schedule_list[core] = thread_ptr; + + /* Remember the previous core. */ + previous_core = core; + + /* Pickup the core of thread to remap. */ + core = thread_ptr -> tx_thread_smp_core_mapped; + + /* Save the new core mapping for this thread. */ + thread_ptr -> tx_thread_smp_core_mapped = previous_core; + + /* Move the next thread. */ + thread_ptr = thread_remap_list[core]; + } + + /* Save the remaining thread in the updated schedule list. */ + _tx_thread_smp_schedule_list[core] = thread_ptr; + + /* Update this thread's core mapping. */ + thread_ptr -> tx_thread_smp_core_mapped = core; + + /* Finally, setup the last thread in the remapping solution. */ + test_cores = last_thread_cores; + TX_LOWEST_SET_BIT_CALCULATE(test_cores, core) + + /* Setup the last thread. */ + _tx_thread_smp_schedule_list[core] = last_thread; + + /* Remember the core mapping for this thread. */ + last_thread -> tx_thread_smp_core_mapped = core; + } + else + { + + /* Set core to the maximum value in order to signal a remapping solution was not found. */ + core = ((UINT) TX_THREAD_SMP_MAX_CORES); + } + + /* Return core to the caller. */ + return(core); +} + + +ULONG _tx_thread_smp_preemptable_threads_get(UINT priority, TX_THREAD *possible_preemption_list[]) +{ + +UINT i, j, k; +TX_THREAD *thread_ptr; +TX_THREAD *next_thread; +TX_THREAD *search_thread; +TX_THREAD *list_head; +ULONG possible_cores = ((ULONG) 0); + + + /* Clear the possible preemption list. */ + possible_preemption_list[0] = TX_NULL; +#if TX_THREAD_SMP_MAX_CORES > 1 + possible_preemption_list[1] = TX_NULL; +#if TX_THREAD_SMP_MAX_CORES > 2 + possible_preemption_list[2] = TX_NULL; +#if TX_THREAD_SMP_MAX_CORES > 3 + possible_preemption_list[3] = TX_NULL; +#if TX_THREAD_SMP_MAX_CORES > 4 + possible_preemption_list[4] = TX_NULL; +#if TX_THREAD_SMP_MAX_CORES > 5 + possible_preemption_list[5] = TX_NULL; +#if TX_THREAD_SMP_MAX_CORES > 6 + + /* Loop to clear the remainder of the possible preemption list. */ + j = ((UINT) 6); + +#ifndef TX_THREAD_SMP_DYNAMIC_CORE_MAX + + while (j < ((UINT) TX_THREAD_SMP_MAX_CORES)) +#else + + while (j < _tx_thread_smp_max_cores) +#endif + { + + /* Clear entry in possible preemption list. */ + possible_preemption_list[j] = TX_NULL; + + /* Move to next core. */ + j++; + } +#endif +#endif +#endif +#endif +#endif +#endif + + /* Loop to build a list of threads of less priority. */ + i = ((UINT) 0); + j = ((UINT) 0); +#ifndef TX_THREAD_SMP_DYNAMIC_CORE_MAX + while (i < ((UINT) TX_THREAD_SMP_MAX_CORES)) +#else + + while (i < _tx_thread_smp_max_cores) +#endif + { + + /* Pickup the currently mapped thread. */ + thread_ptr = _tx_thread_execute_ptr[i]; + + /* Is there a thread scheduled for this core? */ + if (thread_ptr != TX_NULL) + { + + /* Update the possible cores bit map. */ + possible_cores = possible_cores | thread_ptr -> tx_thread_smp_cores_allowed; + + /* Can this thread be preempted? */ + if (priority < thread_ptr -> tx_thread_priority) + { + + /* Thread that can be added to the preemption possible list. */ + + /* Yes, this scheduled thread is lower priority, so add it to the preemption possible list. */ + possible_preemption_list[j] = thread_ptr; + + /* Move to next entry in preemption possible list. */ + j++; + } + } + + /* Move to next core. */ + i++; + } + + /* Check to see if there are more than 2 threads that can be preempted. */ + if (j > ((UINT) 1)) + { + + /* Yes, loop through the preemption possible list and sort by priority. */ + i = ((UINT) 0); + do + { + + /* Pickup preemptable thread. */ + thread_ptr = possible_preemption_list[i]; + + /* Initialize the search index. */ + k = i + ((UINT) 1); + + /* Loop to get the lowest priority thread at the front of the list. */ + while (k < j) + { + + /* Pickup the next thread to evaluate. */ + next_thread = possible_preemption_list[k]; + + /* Is this thread lower priority? */ + if (next_thread -> tx_thread_priority > thread_ptr -> tx_thread_priority) + { + + /* Yes, swap the threads. */ + possible_preemption_list[i] = next_thread; + possible_preemption_list[k] = thread_ptr; + thread_ptr = next_thread; + } + else + { + + /* Compare the thread priorities. */ + if (next_thread -> tx_thread_priority == thread_ptr -> tx_thread_priority) + { + + /* Equal priority threads... see which is in the ready list first. */ + search_thread = thread_ptr -> tx_thread_ready_next; + + /* Pickup the list head. */ + list_head = _tx_thread_priority_list[thread_ptr -> tx_thread_priority]; + + /* Now loop to see if the next thread is after the current thread preemption. */ + while (search_thread != list_head) + { + + /* Have we found the next thread? */ + if (search_thread == next_thread) + { + + /* Yes, swap the threads. */ + possible_preemption_list[i] = next_thread; + possible_preemption_list[k] = thread_ptr; + thread_ptr = next_thread; + break; + } + + /* Move to the next thread. */ + search_thread = search_thread -> tx_thread_ready_next; + } + } + + /* Move to examine the next possible preemptable thread. */ + k++; + } + } + + /* We have found the lowest priority thread to preempt, now find the next lowest. */ + i++; + } + while (i < (j-((UINT) 1))); + } + + /* Return the possible cores. */ + return(possible_cores); +} + +VOID _tx_thread_smp_simple_priority_change(TX_THREAD *thread_ptr, UINT new_priority) +{ + +UINT priority; +ULONG priority_bit; +TX_THREAD *head_ptr; +TX_THREAD *tail_ptr; +#if TX_MAX_PRIORITIES > 32 +UINT map_index; +#endif + + /* Pickup the priority. */ + priority = thread_ptr -> tx_thread_priority; + + /* Determine if there are other threads at this priority that are + ready. */ + if (thread_ptr -> tx_thread_ready_next != thread_ptr) + { + + /* Yes, there are other threads at this priority ready. */ + + /* Just remove this thread from the priority list. */ + (thread_ptr -> tx_thread_ready_next) -> tx_thread_ready_previous = thread_ptr -> tx_thread_ready_previous; + (thread_ptr -> tx_thread_ready_previous) -> tx_thread_ready_next = thread_ptr -> tx_thread_ready_next; + + /* Determine if this is the head of the priority list. */ + if (_tx_thread_priority_list[priority] == thread_ptr) + { + + /* Update the head pointer of this priority list. */ + _tx_thread_priority_list[priority] = thread_ptr -> tx_thread_ready_next; + } + } + else + { + + /* This is the only thread at this priority ready to run. Set the head + pointer to NULL. */ + _tx_thread_priority_list[priority] = TX_NULL; + +#if TX_MAX_PRIORITIES > 32 + + /* Calculate the index into the bit map array. */ + map_index = priority/((UINT) 32); +#endif + + /* Clear this priority bit in the ready priority bit map. */ + TX_MOD32_BIT_SET(priority, priority_bit) + _tx_thread_priority_maps[MAP_INDEX] = _tx_thread_priority_maps[MAP_INDEX] & (~(priority_bit)); + +#if TX_MAX_PRIORITIES > 32 + + /* Determine if there are any other bits set in this priority map. */ + if (_tx_thread_priority_maps[MAP_INDEX] == ((ULONG) 0)) + { + + /* No, clear the active bit to signify this priority map has nothing set. */ + TX_DIV32_BIT_SET(priority, priority_bit) + _tx_thread_priority_map_active = _tx_thread_priority_map_active & (~(priority_bit)); + } +#endif + } + + /* Determine if the actual thread priority should be setup, which is the + case if the new priority is higher than the priority inheritance. */ + if (new_priority < thread_ptr -> tx_thread_inherit_priority) + { + + /* Change thread priority to the new user's priority. */ + thread_ptr -> tx_thread_priority = new_priority; + thread_ptr -> tx_thread_preempt_threshold = new_priority; + } + else + { + + /* Change thread priority to the priority inheritance. */ + thread_ptr -> tx_thread_priority = thread_ptr -> tx_thread_inherit_priority; + thread_ptr -> tx_thread_preempt_threshold = thread_ptr -> tx_thread_inherit_priority; + } + + /* Now, place the thread at the new priority level. */ + + /* Determine if there are other threads at this priority that are + ready. */ + head_ptr = _tx_thread_priority_list[new_priority]; + if (head_ptr != TX_NULL) + { + + /* Yes, there are other threads at this priority already ready. */ + + /* Just add this thread to the priority list. */ + tail_ptr = head_ptr -> tx_thread_ready_previous; + tail_ptr -> tx_thread_ready_next = thread_ptr; + head_ptr -> tx_thread_ready_previous = thread_ptr; + thread_ptr -> tx_thread_ready_previous = tail_ptr; + thread_ptr -> tx_thread_ready_next = head_ptr; + } + else + { + + /* First thread at this priority ready. Add to the front of the list. */ + _tx_thread_priority_list[new_priority] = thread_ptr; + thread_ptr -> tx_thread_ready_next = thread_ptr; + thread_ptr -> tx_thread_ready_previous = thread_ptr; + +#if TX_MAX_PRIORITIES > 32 + + /* Calculate the index into the bit map array. */ + map_index = new_priority/((UINT) 32); + + /* Set the active bit to remember that the priority map has something set. */ + TX_DIV32_BIT_SET(new_priority, priority_bit) + _tx_thread_priority_map_active = _tx_thread_priority_map_active | priority_bit; +#endif + + /* Or in the thread's priority bit. */ + TX_MOD32_BIT_SET(new_priority, priority_bit) + _tx_thread_priority_maps[MAP_INDEX] = _tx_thread_priority_maps[MAP_INDEX] | priority_bit; + } +} + +#endif + + diff --git a/common_smp/src/tx_thread_stack_analyze.c b/common_smp/src/tx_thread_stack_analyze.c new file mode 100644 index 00000000..2cc67691 --- /dev/null +++ b/common_smp/src/tx_thread_stack_analyze.c @@ -0,0 +1,181 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_analyze PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function analyzes the stack to calculate the highest stack */ +/* pointer in the thread's stack. This can then be used to derive the */ +/* minimum amount of stack left for any given thread. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX internal code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_stack_analyze(TX_THREAD *thread_ptr) +{ + +TX_INTERRUPT_SAVE_AREA + +ULONG *stack_ptr; +ULONG *stack_lowest; +ULONG *stack_highest; +ULONG size; + + + /* Disable interrupts. */ + TX_DISABLE + + /* Determine if the thread pointer is NULL. */ + if (thread_ptr != TX_NULL) + { + + /* Determine if the thread ID is invalid. */ + if (thread_ptr -> tx_thread_id == TX_THREAD_ID) + { + + /* Pickup the current stack variables. */ + stack_lowest = TX_VOID_TO_ULONG_POINTER_CONVERT(thread_ptr -> tx_thread_stack_start); + + /* Determine if the pointer is null. */ + if (stack_lowest != TX_NULL) + { + + /* Pickup the highest stack pointer. */ + stack_highest = TX_VOID_TO_ULONG_POINTER_CONVERT(thread_ptr -> tx_thread_stack_highest_ptr); + + /* Determine if the pointer is null. */ + if (stack_highest != TX_NULL) + { + + /* Restore interrupts. */ + TX_RESTORE + + /* We need to binary search the remaining stack for missing 0xEFEFEFEF 32-bit data pattern. + This is a best effort algorithm to find the highest stack usage. */ + do + { + + /* Calculate the size again. */ + size = (ULONG) (TX_ULONG_POINTER_DIF(stack_highest, stack_lowest))/((ULONG) 2); + stack_ptr = TX_ULONG_POINTER_ADD(stack_lowest, size); + + /* Determine if the pattern is still there. */ + if (*stack_ptr != TX_STACK_FILL) + { + + /* Update the stack highest, since we need to look in the upper half now. */ + stack_highest = stack_ptr; + } + else + { + + /* Update the stack lowest, since we need to look in the lower half now. */ + stack_lowest = stack_ptr; + } + + } while(size > ((ULONG) 1)); + + /* Position to first used word - at this point we are within a few words. */ + while (*stack_ptr == TX_STACK_FILL) + { + + /* Position to next word in stack. */ + stack_ptr = TX_ULONG_POINTER_ADD(stack_ptr, 1); + } + + /* Optional processing extension. */ + TX_THREAD_STACK_ANALYZE_EXTENSION + + /* Disable interrupts. */ + TX_DISABLE + + /* Check to see if the thread is still created. */ + if (thread_ptr -> tx_thread_id == TX_THREAD_ID) + { + + /* Yes, thread is still created. */ + + /* Now check the new highest stack pointer is past the stack start. */ + if (stack_ptr > (TX_VOID_TO_ULONG_POINTER_CONVERT(thread_ptr -> tx_thread_stack_start))) + { + + /* Yes, now check that the new highest stack pointer is less than the previous highest stack pointer. */ + if (stack_ptr < (TX_VOID_TO_ULONG_POINTER_CONVERT(thread_ptr -> tx_thread_stack_highest_ptr))) + { + + /* Yes, is the current highest stack pointer pointing at used memory? */ + if (*stack_ptr != TX_STACK_FILL) + { + + /* Yes, setup the highest stack usage. */ + thread_ptr -> tx_thread_stack_highest_ptr = stack_ptr; + } + } + } + } + } + } + } + } + + /* Restore interrupts. */ + TX_RESTORE +} + diff --git a/common_smp/src/tx_thread_stack_error_handler.c b/common_smp/src/tx_thread_stack_error_handler.c new file mode 100644 index 00000000..bc1465b2 --- /dev/null +++ b/common_smp/src/tx_thread_stack_error_handler.c @@ -0,0 +1,105 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_error_handler PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes stack errors detected during run-time. The */ +/* processing currently consists of a spin loop. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX internal code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) +{ + +TX_INTERRUPT_SAVE_AREA + +#ifdef TX_ENABLE_STACK_CHECKING + + /* Disable interrupts. */ + TX_DISABLE + + /* Determine if the application has registered an error handler. */ + if (_tx_thread_application_stack_error_handler != TX_NULL) + { + + /* Yes, an error handler is present, simply call the application error handler. */ + (_tx_thread_application_stack_error_handler)(thread_ptr); + } + + /* Restore interrupts. */ + TX_RESTORE + +#else + + /* Access input argument just for the sake of lint, MISRA, etc. */ + if (thread_ptr != TX_NULL) + { + + /* Disable interrupts. */ + TX_DISABLE + + /* Restore interrupts. */ + TX_RESTORE + } +#endif +} + diff --git a/common_smp/src/tx_thread_stack_error_notify.c b/common_smp/src/tx_thread_stack_error_notify.c new file mode 100644 index 00000000..72cb2c09 --- /dev/null +++ b/common_smp/src/tx_thread_stack_error_notify.c @@ -0,0 +1,125 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#ifdef TX_ENABLE_STACK_CHECKING +#include "tx_trace.h" +#endif + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_error_notify PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application stack error handler. If */ +/* ThreadX detects a stack error, this application handler is called. */ +/* */ +/* Note: stack checking must be enabled for this routine to serve any */ +/* purpose via the TX_ENABLE_STACK_CHECKING define. */ +/* */ +/* INPUT */ +/* */ +/* stack_error_handler Pointer to stack error */ +/* handler, TX_NULL to disable */ +/* */ +/* OUTPUT */ +/* */ +/* status Service return status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr)) +{ + +#ifndef TX_ENABLE_STACK_CHECKING + +UINT status; + + + /* Access input argument just for the sake of lint, MISRA, etc. */ + if (stack_error_handler != TX_NULL) + { + + /* Stack checking is not enabled, just return an error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else + { + + /* Stack checking is not enabled, just return an error. */ + status = TX_FEATURE_NOT_ENABLED; + } + + /* Return completion status. */ + return(status); +#else + +TX_INTERRUPT_SAVE_AREA + + + /* Disable interrupts. */ + TX_DISABLE + + /* Make entry in event log. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_STACK_ERROR_NOTIFY, 0, 0, 0, 0, TX_TRACE_THREAD_EVENTS) + + /* Make entry in event log. */ + TX_EL_THREAD_STACK_ERROR_NOTIFY_INSERT + + /* Setup global thread stack error handler. */ + _tx_thread_application_stack_error_handler = stack_error_handler; + + /* Restore interrupts. */ + TX_RESTORE + + /* Return success to caller. */ + return(TX_SUCCESS); +#endif +} + diff --git a/common_smp/src/tx_thread_suspend.c b/common_smp/src/tx_thread_suspend.c new file mode 100644 index 00000000..fd12d755 --- /dev/null +++ b/common_smp/src/tx_thread_suspend.c @@ -0,0 +1,207 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_suspend PORTABLE SMP */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles application suspend requests. If the suspend */ +/* requires actual processing, this function calls the actual suspend */ +/* thread routine. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread to suspend */ +/* */ +/* OUTPUT */ +/* */ +/* status Return completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_system_suspend Actual thread suspension */ +/* _tx_thread_system_ni_suspend Non-interruptable suspend thread */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_thread_suspend(TX_THREAD *thread_ptr) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_THREAD *current_thread; +UINT status; +UINT core_index; + + + /* Lockout interrupts while the thread is being suspended. */ + TX_DISABLE + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(current_thread) + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_SUSPEND_API, thread_ptr, thread_ptr -> tx_thread_state, TX_POINTER_TO_ULONG_CONVERT(&status), 0, TX_TRACE_THREAD_EVENTS) + + /* Log this kernel call. */ + TX_EL_THREAD_SUSPEND_INSERT + + /* Check the specified thread's current status. */ + if (thread_ptr -> tx_thread_state == TX_READY) + { + + /* Initialize status to success. */ + status = TX_SUCCESS; + + /* Pickup the index. */ + core_index = TX_SMP_CORE_ID; + + /* Determine if we are in a thread context. */ + if (_tx_thread_system_state[core_index] == ((ULONG) 0)) + { + + /* Yes, we are in a thread context. */ + + /* Determine if the current thread is also the suspending thread. */ + if (current_thread == thread_ptr) + { + + /* Determine if the preempt disable flag is non-zero. */ + if (_tx_thread_preempt_disable != ((UINT) 0)) + { + + /* Thread is terminated or completed. */ + status = TX_SUSPEND_ERROR; + } + } + } + + /* Determine if the status is still successful. */ + if (status == TX_SUCCESS) + { + + /* Set the state to suspended. */ + thread_ptr -> tx_thread_state = TX_SUSPENDED; + +#ifdef TX_NOT_INTERRUPTABLE + + /* Call actual non-interruptable thread suspension routine. */ + _tx_thread_system_ni_suspend(thread_ptr, ((ULONG) 0)); + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Set the suspending flag. */ + thread_ptr -> tx_thread_suspending = TX_TRUE; + + /* Setup for no timeout period. */ + thread_ptr -> tx_thread_timer.tx_timer_internal_remaining_ticks = ((ULONG) 0); + + /* Temporarily disable preemption. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Call actual thread suspension routine. */ + _tx_thread_system_suspend(thread_ptr); +#endif + +#ifdef TX_MISRA_ENABLE + + /* Disable interrupts. */ + TX_DISABLE + + /* Return success. */ + status = TX_SUCCESS; +#else + + /* If MISRA is not enabled, return directly. */ + return(TX_SUCCESS); +#endif + } + } + else if (thread_ptr -> tx_thread_state == TX_TERMINATED) + { + + /* Thread is terminated. */ + status = TX_SUSPEND_ERROR; + } + else if (thread_ptr -> tx_thread_state == TX_COMPLETED) + { + + /* Thread is completed. */ + status = TX_SUSPEND_ERROR; + } + else if (thread_ptr -> tx_thread_state == TX_SUSPENDED) + { + + /* Already suspended, just set status to success. */ + status = TX_SUCCESS; + } + else + { + + /* Just set the delayed suspension flag. */ + thread_ptr -> tx_thread_delayed_suspend = TX_TRUE; + + /* Set status to success. */ + status = TX_SUCCESS; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Always return success, since this function does not perform error + checking. */ + return(status); +} + diff --git a/common_smp/src/tx_thread_system_preempt_check.c b/common_smp/src/tx_thread_system_preempt_check.c new file mode 100644 index 00000000..24e18274 --- /dev/null +++ b/common_smp/src/tx_thread_system_preempt_check.c @@ -0,0 +1,168 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_preempt_check PORTABLE SMP */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for preemption that could have occurred as a */ +/* result scheduling activities occurring while the preempt disable */ +/* flag was set. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_system_return Return to the system */ +/* */ +/* CALLED BY */ +/* */ +/* Other ThreadX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_system_preempt_check(VOID) +{ + +TX_INTERRUPT_SAVE_AREA + +UINT core_index; +UINT restore_needed; + + + /* Disable interrupts. */ + TX_DISABLE + + /* Set the restore needed flag. */ + restore_needed = TX_TRUE; + + /* Pickup the index. */ + core_index = TX_SMP_CORE_ID; + + /* Determine if the call is from initialization, an ISR or if the preempt disable flag is set. */ + if (_tx_thread_system_state[core_index] == ((ULONG) 0)) + { + + /* Ensure the preempt disable flag is not set. */ + if (_tx_thread_preempt_disable == ((UINT) 0)) + { + + /* Thread execution - now determine if preemption should take place. */ + if (_tx_thread_current_ptr[core_index] != _tx_thread_execute_ptr[core_index]) + { + + /* Yes, thread preemption should take place. */ + +#ifdef TX_ENABLE_STACK_CHECKING + TX_THREAD *thread_ptr; + + /* Pickup the next execute pointer. */ + thread_ptr = _tx_thread_execute_ptr[core_index]; + + /* Determine if there is a thread pointer. */ + if (thread_ptr != TX_NULL) + { + + /* Check this thread's stack. */ + TX_THREAD_STACK_CHECK(thread_ptr) + } +#endif + +#ifdef TX_THREAD_ENABLE_PERFORMANCE_INFO + + /* Determine if an idle system return is present. */ + if (_tx_thread_execute_ptr[core_index] == TX_NULL) + { + + /* Yes, increment the return to idle return count. */ + _tx_thread_performance_idle_return_count++; + } + else + { + + /* No, there is another thread ready to run and will be scheduled upon return. */ + _tx_thread_performance_non_idle_return_count++; + } +#endif + +#ifndef TX_NOT_INTERRUPTABLE + + /* Increment the preempt disable flag in order to keep the protection. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE +#endif + + /* Return to the system so the higher priority thread can be scheduled. */ + _tx_thread_system_return(); + +#ifdef TX_NOT_INTERRUPTABLE + + /* Restore interrupts. */ + TX_RESTORE +#endif + + /* Clear the restore needed flag, since the interrupt poster/protection has been done. */ + restore_needed = TX_FALSE; + } + } + } + + /* Determine if the protection still needs to be restored. */ + if (restore_needed == TX_TRUE) + { + + /* Restore interrupts. */ + TX_RESTORE + } +} + diff --git a/common_smp/src/tx_thread_system_resume.c b/common_smp/src/tx_thread_system_resume.c new file mode 100644 index 00000000..70700c77 --- /dev/null +++ b/common_smp/src/tx_thread_system_resume.c @@ -0,0 +1,969 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_timer.h" +#include "tx_thread.h" +#include "tx_trace.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_resume PORTABLE SMP */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function places the specified thread on the list of ready */ +/* threads at the thread's specific priority. If a thread preemption */ +/* is detected, this function returns a TX_TRUE. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread to resume */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_smp_available_cores_get Get available cores bitmap */ +/* _tx_thread_smp_core_preempt Preempt core for new thread */ +/* _tx_thread_smp_core_wakeup Wakeup other core */ +/* _tx_thread_smp_execute_list_clear Clear the thread execute list */ +/* _tx_thread_smp_execute_list_setup Setup the thread execute list */ +/* _tx_thread_smp_core_interrupt Interrupt other core */ +/* _tx_thread_smp_lowest_priority_get Get lowest priority scheduled */ +/* thread */ +/* _tx_thread_smp_next_priority_find Find next priority with one */ +/* or more ready threads */ +/* _tx_thread_smp_possible_cores_get Get possible cores bitmap */ +/* _tx_thread_smp_preemptable_threads_get */ +/* Get list of thread preemption */ +/* possibilities */ +/* [_tx_thread_smp_protect] Get protection */ +/* _tx_thread_smp_rebalance_execute_list Rebalance the execution list */ +/* _tx_thread_smp_remap_solution_find Attempt to remap threads to */ +/* schedule another thread */ +/* _tx_thread_smp_schedule_list_clear Clear the thread schedule list*/ +/* _tx_thread_smp_schedule_list_setup Inherit schedule list from */ +/* execute list */ +/* _tx_thread_system_return Return to the system */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Thread create function */ +/* _tx_thread_priority_change Thread priority change */ +/* _tx_thread_resume Application resume service */ +/* _tx_thread_timeout Thread timeout */ +/* _tx_thread_wait_abort Thread wait abort */ +/* Other ThreadX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_system_resume(TX_THREAD *thread_ptr) +{ + +#ifndef TX_NOT_INTERRUPTABLE + +TX_INTERRUPT_SAVE_AREA + +#endif + +UINT priority; +ULONG priority_bit; +TX_THREAD *head_ptr; +TX_THREAD *tail_ptr; +UINT core_index; +#ifndef TX_THREAD_SMP_EQUAL_PRIORITY +UINT j; +UINT lowest_priority; +TX_THREAD *next_thread; +ULONG test_cores; +UINT core; +UINT thread_mapped; +TX_THREAD *preempt_thread; +ULONG possible_cores; +ULONG thread_possible_cores; +ULONG available_cores; +ULONG test_possible_cores; +TX_THREAD *possible_preemption_list[TX_THREAD_SMP_MAX_CORES]; +#endif +TX_THREAD *execute_thread; +UINT i; +UINT loop_finished; +UINT processing_complete; + +#ifdef TX_ENABLE_EVENT_TRACE +TX_TRACE_BUFFER_ENTRY *entry_ptr; +ULONG time_stamp = ((ULONG) 0); +#endif + +#if TX_MAX_PRIORITIES > 32 +UINT map_index; +#endif + +#ifndef TX_NO_TIMER +TX_TIMER_INTERNAL *timer_ptr; +TX_TIMER_INTERNAL **list_head; +TX_TIMER_INTERNAL *next_timer; +TX_TIMER_INTERNAL *previous_timer; +#endif + + + /* Set the processing complete flag to false. */ + processing_complete = TX_FALSE; + +#ifndef TX_NOT_INTERRUPTABLE + + /* Lockout interrupts while the thread is being resumed. */ + TX_DISABLE +#endif + + +#ifndef TX_NO_TIMER + + /* Deactivate the timeout timer if necessary. */ + if ((thread_ptr -> tx_thread_timer.tx_timer_internal_list_head) != TX_NULL) + { + + /* Deactivate the thread's timeout timer. This is now done in-line + for ThreadX SMP so the additional protection logic can be avoided. */ + + /* Deactivate the timer. */ + + /* Pickup internal timer pointer. */ + timer_ptr = &(thread_ptr -> tx_thread_timer); + + /* Pickup the list head pointer. */ + list_head = timer_ptr -> tx_timer_internal_list_head; + + /* Pickup the next active timer. */ + next_timer = timer_ptr -> tx_timer_internal_active_next; + + /* See if this is the only timer in the list. */ + if (timer_ptr == next_timer) + { + + /* Yes, the only timer on the list. */ + + /* Determine if the head pointer needs to be updated. */ + if (*(list_head) == timer_ptr) + { + + /* Update the head pointer. */ + *(list_head) = TX_NULL; + } + } + else + { + + /* At least one more timer is on the same expiration list. */ + + /* Update the links of the adjacent timers. */ + previous_timer = timer_ptr -> tx_timer_internal_active_previous; + next_timer -> tx_timer_internal_active_previous = previous_timer; + previous_timer -> tx_timer_internal_active_next = next_timer; + + /* Determine if the head pointer needs to be updated. */ + if (*(list_head) == timer_ptr) + { + + /* Update the next timer in the list with the list head pointer. */ + next_timer -> tx_timer_internal_list_head = list_head; + + /* Update the head pointer. */ + *(list_head) = next_timer; + } + } + + /* Clear the timer's list head pointer. */ + timer_ptr -> tx_timer_internal_list_head = TX_NULL; + } + else + { + + /* Clear the remaining time to ensure timer doesn't get activated. */ + thread_ptr -> tx_thread_timer.tx_timer_internal_remaining_ticks = ((ULONG) 0); + } +#endif + +#ifdef TX_ENABLE_STACK_CHECKING + + /* Check this thread's stack. */ + TX_THREAD_STACK_CHECK(thread_ptr) +#endif + + + /* Pickup index. */ + core_index = TX_SMP_CORE_ID; + +#ifdef TX_ENABLE_EVENT_TRACE + + /* If trace is enabled, save the current event pointer. */ + entry_ptr = _tx_trace_buffer_current_ptr; +#endif + + /* Log the thread status change. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_RESUME, thread_ptr, thread_ptr -> tx_thread_state, TX_POINTER_TO_ULONG_CONVERT(&time_stamp), TX_POINTER_TO_ULONG_CONVERT(_tx_thread_execute_ptr[core_index]), TX_TRACE_INTERNAL_EVENTS) + +#ifdef TX_THREAD_SMP_DEBUG_ENABLE + + /* Debug entry. */ + _tx_thread_smp_debug_entry_insert(4, 0, thread_ptr); +#endif + +#ifdef TX_ENABLE_EVENT_TRACE + + /* Save the time stamp for later comparison to verify that + the event hasn't been overwritten by the time we have + computed the next thread to execute. */ + if (entry_ptr != TX_NULL) + { + + /* Save time stamp. */ + time_stamp = entry_ptr -> tx_trace_buffer_entry_time_stamp; + } +#endif + + + /* Determine if the thread is in the process of suspending. If so, the thread + control block is already on the linked list so nothing needs to be done. */ + if (thread_ptr -> tx_thread_suspending == TX_TRUE) + { + + /* Make sure the type of suspension under way is not a terminate or + thread completion. In either of these cases, do not void the + interrupted suspension processing. */ + if (thread_ptr -> tx_thread_state != TX_COMPLETED) + { + + /* Make sure the thread isn't terminated. */ + if (thread_ptr -> tx_thread_state != TX_TERMINATED) + { + + /* No, now check to see if the delayed suspension flag is set. */ + if (thread_ptr -> tx_thread_delayed_suspend == TX_FALSE) + { + + /* Clear the suspending flag. */ + thread_ptr -> tx_thread_suspending = TX_FALSE; + + /* Restore the state to ready. */ + thread_ptr -> tx_thread_state = TX_READY; + + /* Thread state change. */ + TX_THREAD_STATE_CHANGE(thread_ptr, TX_READY) + + /* Log the thread status change. */ + TX_EL_THREAD_STATUS_CHANGE_INSERT(thread_ptr, TX_READY) + } + else + { + + /* Clear the delayed suspend flag and change the state. */ + thread_ptr -> tx_thread_delayed_suspend = TX_FALSE; + thread_ptr -> tx_thread_state = TX_SUSPENDED; + } + +#ifdef TX_THREAD_ENABLE_PERFORMANCE_INFO + + /* Increment the total number of thread resumptions. */ + _tx_thread_performance_resume_count++; + + /* Increment this thread's resume count. */ + thread_ptr -> tx_thread_performance_resume_count++; +#endif + } + } + } + else + { + + /* Check to make sure the thread has not already been resumed. */ + if (thread_ptr -> tx_thread_state != TX_READY) + { + + /* Check for a delayed suspend flag. */ + if (thread_ptr -> tx_thread_delayed_suspend == TX_TRUE) + { + + /* Clear the delayed suspend flag and change the state. */ + thread_ptr -> tx_thread_delayed_suspend = TX_FALSE; + thread_ptr -> tx_thread_state = TX_SUSPENDED; + } + else + { + + /* Thread state change. */ + TX_THREAD_STATE_CHANGE(thread_ptr, TX_READY) + + /* Log the thread status change. */ + TX_EL_THREAD_STATUS_CHANGE_INSERT(thread_ptr, TX_READY) + + /* Make this thread ready. */ + + /* Change the state to ready. */ + thread_ptr -> tx_thread_state = TX_READY; + + /* Pickup priority of thread. */ + priority = thread_ptr -> tx_thread_priority; + +#ifdef TX_THREAD_ENABLE_PERFORMANCE_INFO + + /* Increment the total number of thread resumptions. */ + _tx_thread_performance_resume_count++; + + /* Increment this thread's resume count. */ + thread_ptr -> tx_thread_performance_resume_count++; +#endif + + /* Determine if there are other threads at this priority that are + ready. */ + head_ptr = _tx_thread_priority_list[priority]; + if (head_ptr != TX_NULL) + { + + /* Yes, there are other threads at this priority already ready. */ + + /* Just add this thread to the priority list. */ + tail_ptr = head_ptr -> tx_thread_ready_previous; + tail_ptr -> tx_thread_ready_next = thread_ptr; + head_ptr -> tx_thread_ready_previous = thread_ptr; + thread_ptr -> tx_thread_ready_previous = tail_ptr; + thread_ptr -> tx_thread_ready_next = head_ptr; + } + else + { + + /* First thread at this priority ready. Add to the front of the list. */ + _tx_thread_priority_list[priority] = thread_ptr; + thread_ptr -> tx_thread_ready_next = thread_ptr; + thread_ptr -> tx_thread_ready_previous = thread_ptr; + +#if TX_MAX_PRIORITIES > 32 + + /* Calculate the index into the bit map array. */ + map_index = priority/((UINT) 32); + + /* Set the active bit to remember that the priority map has something set. */ + TX_DIV32_BIT_SET(priority, priority_bit) + _tx_thread_priority_map_active = _tx_thread_priority_map_active | priority_bit; +#endif + + /* Or in the thread's priority bit. */ + TX_MOD32_BIT_SET(priority, priority_bit) + _tx_thread_priority_maps[MAP_INDEX] = _tx_thread_priority_maps[MAP_INDEX] | priority_bit; + } + + /* Determine if a thread with preemption-threshold is currently scheduled. */ + if (_tx_thread_preemption__threshold_scheduled != TX_NULL) + { + + /* Yes, there has been a thread with preemption-threshold scheduled. */ + + /* Determine if this thread can run with the current preemption-threshold. */ + if (priority >= _tx_thread_preemption__threshold_scheduled -> tx_thread_preempt_threshold) + { + + /* The thread cannot run because of the current preemption-threshold. Simply + return at this point. */ + +#ifndef TX_NOT_INTERRUPTABLE + + /* Decrement the preemption disable flag. */ + _tx_thread_preempt_disable--; +#endif + +#ifdef TX_THREAD_SMP_DEBUG_ENABLE + + /* Debug entry. */ + _tx_thread_smp_debug_entry_insert(5, 0, thread_ptr); +#endif + +#ifndef TX_NOT_INTERRUPTABLE + + /* Restore interrupts. */ + TX_RESTORE +#endif + + /* Processing is complete, set the complete flag. */ + processing_complete = TX_TRUE; + } + } + + /* Is the processing complete at this point? */ + if (processing_complete == TX_FALSE) + { + + /* Determine if this newly ready thread has preemption-threshold set. If so, determine + if any other threads would need to be unscheduled for this thread to execute. */ + if (thread_ptr -> tx_thread_preempt_threshold < priority) + { + + /* Is there a place in the execution list for the newly ready thread? */ + i = ((UINT) 0); + loop_finished = TX_FALSE; +#ifndef TX_THREAD_SMP_DYNAMIC_CORE_MAX + while(i < ((UINT) TX_THREAD_SMP_MAX_CORES)) +#else + while(i < _tx_thread_smp_max_cores) +#endif + { + + /* Pickup the current execute thread for this core. */ + execute_thread = _tx_thread_execute_ptr[i]; + + /* Is there a thread mapped to this core? */ + if (execute_thread == TX_NULL) + { + + /* Get out of the loop. */ + loop_finished = TX_TRUE; + } + else + { + + /* Determine if this thread should preempt the thread in the execution list. */ + if (priority < execute_thread -> tx_thread_preempt_threshold) + { + + /* Get out of the loop. */ + loop_finished = TX_TRUE; + } + } + + /* Determine if we need to get out of the loop. */ + if (loop_finished == TX_TRUE) + { + + /* Get out of the loop. */ + break; + } + + /* Move to next index. */ + i++; + } + + /* Determine if there is a reason to rebalance the list. */ +#ifndef TX_THREAD_SMP_DYNAMIC_CORE_MAX + if (i < ((UINT) TX_THREAD_SMP_MAX_CORES)) +#else + if (i < _tx_thread_smp_max_cores) +#endif + { + + /* Yes, the new thread has preemption-threshold set and there is a slot in the + execution list for it. */ + + /* Call the rebalance routine. This routine maps cores and ready threads. */ + _tx_thread_smp_rebalance_execute_list(core_index); + } + } +#ifdef TX_THREAD_SMP_EQUAL_PRIORITY + else + { + + /* For equal priority SMP, we simply use the rebalance list function. */ + + /* Call the rebalance routine. This routine maps cores and ready threads. */ + _tx_thread_smp_rebalance_execute_list(core_index); + } +#else + else + { + + /* Determine if this thread has any available cores to execute on. */ + if (thread_ptr -> tx_thread_smp_cores_allowed != ((ULONG) 0)) + { + + /* At this point we know that the newly ready thread does not have preemption-threshold set and that + any existing preemption-threshold is not blocking this thread from executing. */ + + /* Pickup the core this thread was previously executing on. */ + i = thread_ptr -> tx_thread_smp_core_mapped; + + /* Pickup the currently executing thread for the previously mapped core. */ + execute_thread = _tx_thread_execute_ptr[i]; + + /* First, let's see if the last core this thread executed on is available. */ + if (execute_thread == TX_NULL) + { + + /* Yes, simply place this thread into the execute list at the same location. */ + _tx_thread_execute_ptr[i] = thread_ptr; + + /* If necessary, interrupt the core with the new thread to schedule. */ + _tx_thread_smp_core_interrupt(thread_ptr, core_index, i); + + /* If necessary, wakeup the target core. */ + _tx_thread_smp_core_wakeup(core_index, i); + } + else + { + + /* This core is not able to execute on the core it last executed on + because another thread is already scheduled on that core. */ + + /* Pickup the available cores for the newly ready thread. */ + available_cores = thread_ptr -> tx_thread_smp_cores_allowed; + + /* Isolate the lowest set bit so we can determine if more than one core is + available. */ + available_cores = available_cores & ((~available_cores) + ((ULONG) 1)); + + /* Determine if either this thread or the currently schedule thread can + run on more than one core or on a different core and preemption is not + possible. */ + if ((available_cores == thread_ptr -> tx_thread_smp_cores_allowed) && + (available_cores == execute_thread -> tx_thread_smp_cores_allowed)) + { + + /* Both this thread and the execute thread can only execute on the same core, + so this thread can only be scheduled if its priority is less. Otherwise, + there is nothing else to examine. */ + if (thread_ptr -> tx_thread_priority < execute_thread -> tx_thread_priority) + { + + /* We know that we have to preempt the executing thread. */ + + /* Preempt the executing thread. */ + _tx_thread_execute_ptr[i] = thread_ptr; + + /* If necessary, interrupt the core with the new thread to schedule. */ + _tx_thread_smp_core_interrupt(thread_ptr, core_index, i); + + /* If necessary, wakeup the core. */ + _tx_thread_smp_core_wakeup(core_index, i); + } + } + else + { + + /* Determine if there are any available cores to execute on. */ + available_cores = _tx_thread_smp_available_cores_get(); + + /* Determine what the possible cores are for this thread. */ + thread_possible_cores = thread_ptr -> tx_thread_smp_cores_allowed; + + /* Set the thread mapped flag to false. */ + thread_mapped = TX_FALSE; + + /* Determine if there are available cores. */ + if (available_cores != ((ULONG) 0)) + { + + /* Determine if one of the available cores is allowed for this thread. */ + if ((available_cores & thread_possible_cores) != ((ULONG) 0)) + { + + /* Calculate the lowest set bit of allowed cores. */ + test_cores = (thread_possible_cores & available_cores); + TX_LOWEST_SET_BIT_CALCULATE(test_cores, i) + + /* Remember this index in the thread control block. */ + thread_ptr -> tx_thread_smp_core_mapped = i; + + /* Map this thread to the free slot. */ + _tx_thread_execute_ptr[i] = thread_ptr; + + /* Indicate this thread was mapped. */ + thread_mapped = TX_TRUE; + + /* If necessary, wakeup the target core. */ + _tx_thread_smp_core_wakeup(core_index, i); + } + else + { + + /* There are available cores, however, they are all excluded. */ + + /* Calculate the possible cores from the cores currently scheduled. */ + possible_cores = _tx_thread_smp_possible_cores_get(); + + /* Determine if it is worthwhile to try to remap the execution list. */ + if ((available_cores & possible_cores) != ((ULONG) 0)) + { + + /* Yes, some of the currently scheduled threads can be moved. */ + + /* Now determine if there could be a remap solution that will allow us to schedule this thread. */ + + /* Narrow to the current possible cores. */ + thread_possible_cores = thread_possible_cores & possible_cores; + + /* Now we need to see if one of the other threads in the non-excluded cores can be moved to make room + for this thread. */ + + /* Default the schedule list to the current execution list. */ + _tx_thread_smp_schedule_list_setup(); + + /* Determine the possible core mapping. */ + test_possible_cores = possible_cores & ~(thread_possible_cores); + + /* Attempt to remap the cores in order to schedule this thread. */ + core = _tx_thread_smp_remap_solution_find(thread_ptr, available_cores, thread_possible_cores, test_possible_cores); + + /* Determine if remapping was successful. */ + if (core != ((UINT) TX_THREAD_SMP_MAX_CORES)) + { + + /* Clear the execute list. */ + _tx_thread_smp_execute_list_clear(); + + /* Setup the execute list based on the updated schedule list. */ + _tx_thread_smp_execute_list_setup(core_index); + + /* Indicate this thread was mapped. */ + thread_mapped = TX_TRUE; + } + } + } + } + + /* Determine if we need to investigate thread preemption. */ + if (thread_mapped == TX_FALSE) + { + + /* At this point, we need to first check for thread preemption possibilities. */ + lowest_priority = _tx_thread_smp_lowest_priority_get(); + + /* Does this thread have a higher priority? */ + if (thread_ptr -> tx_thread_priority < lowest_priority) + { + + /* Yes, preemption is possible. */ + + /* Pickup the thread to preempt. */ + preempt_thread = _tx_thread_priority_list[lowest_priority]; + + /* Determine if there are more than one thread ready at this priority level. */ + if (preempt_thread -> tx_thread_ready_next != preempt_thread) + { + + /* Remember the list head. */ + head_ptr = preempt_thread; + + /* Setup thread search pointer to the start of the list. */ + next_thread = preempt_thread -> tx_thread_ready_next; + + /* Loop to find the last thread scheduled at this priority. */ + i = ((UINT) 0); +#ifndef TX_THREAD_SMP_DYNAMIC_CORE_MAX + while (i < ((UINT) TX_THREAD_SMP_MAX_CORES)) +#else + + while (i < _tx_thread_smp_max_cores) +#endif + { + + /* Is this thread currently scheduled? */ + if (next_thread == _tx_thread_execute_ptr[next_thread -> tx_thread_smp_core_mapped]) + { + + /* Yes, this is the new preempt thread. */ + preempt_thread = next_thread; + + /* Increment core count. */ + i++; + } + + /* Move to the next thread. */ + next_thread = next_thread -> tx_thread_ready_next; + + /* Are we at the head of the list? */ + if (next_thread == head_ptr) + { + + /* End the loop. */ + i = ((UINT) TX_THREAD_SMP_MAX_CORES); + } + } + } + + /* Calculate the core that this thread is scheduled on. */ + possible_cores = (((ULONG) 1) << preempt_thread -> tx_thread_smp_core_mapped); + + /* Determine if preemption is possible. */ + if ((thread_possible_cores & possible_cores) != ((ULONG) 0)) + { + + /* Pickup the newly available core. */ + i = preempt_thread -> tx_thread_smp_core_mapped; + + /* Remember this index in the thread control block. */ + thread_ptr -> tx_thread_smp_core_mapped = i; + + /* Map this thread to the free slot. */ + _tx_thread_execute_ptr[i] = thread_ptr; + + /* If necessary, interrupt the core with the new thread to schedule. */ + _tx_thread_smp_core_interrupt(thread_ptr, core_index, i); + + /* If necessary, wakeup the target core. */ + _tx_thread_smp_core_wakeup(core_index, i); + } + else + { + + /* Build the list of possible thread preemptions, ordered lowest priority first. */ + possible_cores = _tx_thread_smp_preemptable_threads_get(thread_ptr -> tx_thread_priority, possible_preemption_list); + + /* Determine if preemption is possible. */ + + /* Loop through the potential threads can can be preempted. */ + i = ((UINT) 0); + loop_finished = TX_FALSE; + while (possible_preemption_list[i] != TX_NULL) + { + + /* Pickup the thread to preempt. */ + preempt_thread = possible_preemption_list[i]; + + /* Pickup the core this thread is mapped to. */ + j = preempt_thread -> tx_thread_smp_core_mapped; + + /* Calculate the core that this thread is scheduled on. */ + available_cores = (((ULONG) 1) << j); + + /* Can this thread execute on this core? */ + if ((thread_possible_cores & available_cores) != ((ULONG) 0)) + { + + /* Remember this index in the thread control block. */ + thread_ptr -> tx_thread_smp_core_mapped = j; + + /* Map this thread to the free slot. */ + _tx_thread_execute_ptr[j] = thread_ptr; + + /* If necessary, interrupt the core with the new thread to schedule. */ + _tx_thread_smp_core_interrupt(thread_ptr, core_index, j); + + /* If necessary, wakeup the target core. */ + _tx_thread_smp_core_wakeup(core_index, j); + + /* Finished with the preemption condition. */ + loop_finished = TX_TRUE; + } + else + { + + /* No, the thread to preempt is not running on a core available to the new thread. + Attempt to find a remapping solution. */ + + /* Narrow to the current possible cores. */ + thread_possible_cores = thread_possible_cores & possible_cores; + + /* Now we need to see if one of the other threads in the non-excluded cores can be moved to make room + for this thread. */ + + /* Temporarily set the execute thread to NULL. */ + _tx_thread_execute_ptr[j] = TX_NULL; + + /* Default the schedule list to the current execution list. */ + _tx_thread_smp_schedule_list_setup(); + + /* Determine the possible core mapping. */ + test_possible_cores = possible_cores & ~(thread_possible_cores); + + /* Attempt to remap the cores in order to schedule this thread. */ + core = _tx_thread_smp_remap_solution_find(thread_ptr, available_cores, thread_possible_cores, test_possible_cores); + + /* Determine if remapping was successful. */ + if (core != ((UINT) TX_THREAD_SMP_MAX_CORES)) + { + + /* Clear the execute list. */ + _tx_thread_smp_execute_list_clear(); + + /* Setup the execute list based on the updated schedule list. */ + _tx_thread_smp_execute_list_setup(core_index); + + /* Finished with the preemption condition. */ + loop_finished = TX_TRUE; + } + else + { + + /* Restore the preempted thread and examine the next thread. */ + _tx_thread_execute_ptr[j] = preempt_thread; + } + } + + /* Determine if we should get out of the loop. */ + if (loop_finished == TX_TRUE) + { + + /* Yes, get out of the loop. */ + break; + } + + /* Move to the next possible thread preemption. */ + i++; + } + } + } + } + } + } + } + } +#endif + } + } + } + } + + /* Determine if there is more processing. */ + if (processing_complete == TX_FALSE) + { + +#ifdef TX_THREAD_SMP_DEBUG_ENABLE + + /* Debug entry. */ + _tx_thread_smp_debug_entry_insert(5, 0, thread_ptr); +#endif + +#ifdef TX_ENABLE_EVENT_TRACE + + /* Check that the event time stamp is unchanged. A different + timestamp means that a later event wrote over the thread + resume event. In that case, do nothing here. */ + if ((entry_ptr != TX_NULL) && (time_stamp == entry_ptr -> tx_trace_buffer_entry_time_stamp)) + { + + /* Timestamp is the same, set the "next thread pointer" to NULL. This can + be used by the trace analysis tool to show idle system conditions. */ +#ifdef TX_MISRA_ENABLE + entry_ptr -> tx_trace_buffer_entry_info_4 = TX_POINTER_TO_ULONG_CONVERT(_tx_thread_execute_ptr[core_index]); +#else + entry_ptr -> tx_trace_buffer_entry_information_field_4 = TX_POINTER_TO_ULONG_CONVERT(_tx_thread_execute_ptr[core_index]); +#endif + } +#endif + +#ifndef TX_NOT_INTERRUPTABLE + + /* Decrement the preemption disable flag. */ + _tx_thread_preempt_disable--; +#endif + + if (_tx_thread_current_ptr[core_index] != _tx_thread_execute_ptr[core_index]) + { + +#ifdef TX_ENABLE_STACK_CHECKING + + /* Pickup the next thread to execute. */ + thread_ptr = _tx_thread_execute_ptr[core_index]; + + /* Determine if there is a thread pointer. */ + if (thread_ptr != TX_NULL) + { + + /* Check this thread's stack. */ + TX_THREAD_STACK_CHECK(thread_ptr) + } +#endif + + /* Now determine if preemption should take place. This is only possible if the current thread pointer is + not the same as the execute thread pointer AND the system state and preempt disable flags are clear. */ + if (_tx_thread_system_state[core_index] == ((ULONG) 0)) + { + + /* Is the preempt disable flag set? */ + if (_tx_thread_preempt_disable == ((UINT) 0)) + { + + +#ifdef TX_THREAD_ENABLE_PERFORMANCE_INFO + + /* No, there is another thread ready to run and will be scheduled upon return. */ + _tx_thread_performance_non_idle_return_count++; +#endif + +#ifndef TX_NOT_INTERRUPTABLE + + /* Increment the preempt disable flag in order to keep the protection. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE +#endif + + /* Preemption is needed - return to the system! */ + _tx_thread_system_return(); + +#ifdef TX_NOT_INTERRUPTABLE + + /* Setup protection again since caller is expecting that it is still in force. */ + _tx_thread_smp_protect(); +#endif + +#ifndef TX_NOT_INTERRUPTABLE + + /* Set the processing complete flag. */ + processing_complete = TX_TRUE; +#endif + } + } + } + +#ifndef TX_NOT_INTERRUPTABLE + + /* Determine if processing is complete. If so, no need to restore interrupts. */ + if (processing_complete == TX_FALSE) + { + + /* Restore interrupts. */ + TX_RESTORE + } +#endif + } +} + +#ifdef TX_NOT_INTERRUPTABLE +VOID _tx_thread_system_ni_resume(TX_THREAD *thread_ptr) +{ + + /* Call system resume. */ + _tx_thread_system_resume(thread_ptr); +} +#endif + diff --git a/common_smp/src/tx_thread_system_suspend.c b/common_smp/src/tx_thread_system_suspend.c new file mode 100644 index 00000000..bed18d4e --- /dev/null +++ b/common_smp/src/tx_thread_system_suspend.c @@ -0,0 +1,1013 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_timer.h" +#include "tx_thread.h" +#include "tx_trace.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_suspend PORTABLE SMP */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function suspends the specified thread and changes the thread */ +/* state to the value specified. Note: delayed suspension processing */ +/* is handled outside of this routine. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread to suspend */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_smp_available_cores_get Get available cores bitmap */ +/* _tx_thread_smp_core_preempt Preempt core for new thread */ +/* _tx_thread_smp_execute_list_clear Clear the thread execute list */ +/* _tx_thread_smp_execute_list_setup Setup the thread execute list */ +/* _tx_thread_smp_next_priority_find Find next priority with one */ +/* or more ready threads */ +/* _tx_thread_smp_possible_cores_get Get possible cores bitmap */ +/* [_tx_thread_smp_protect] Get protection */ +/* _tx_thread_smp_rebalance_execute_list Rebalance the execution list */ +/* _tx_thread_smp_remap_solution_find Attempt to remap threads to */ +/* schedule another thread */ +/* _tx_thread_smp_schedule_list_setup Inherit schedule list from */ +/* execute list */ +/* _tx_thread_system_return Return to system */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_priority_change Thread priority change */ +/* _tx_thread_shell_entry Thread shell function */ +/* _tx_thread_sleep Thread sleep */ +/* _tx_thread_suspend Application thread suspend */ +/* _tx_thread_terminate Thread terminate */ +/* Other ThreadX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_system_suspend(TX_THREAD *thread_ptr) +{ + +#ifndef TX_NOT_INTERRUPTABLE + +TX_INTERRUPT_SAVE_AREA +#endif + +UINT priority; +UINT i; +ULONG priority_bit; +ULONG combined_flags; +ULONG priority_map; +UINT core_index; +#ifndef TX_THREAD_SMP_EQUAL_PRIORITY +ULONG complex_path_possible; +UINT core; +ULONG possible_cores; +ULONG thread_possible_cores; +ULONG available_cores; +ULONG test_possible_cores; +UINT next_priority; +TX_THREAD *next_thread; +UINT loop_finished; +#endif +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD +UINT next_preempted; +UINT base_priority; +UINT priority_bit_set; +TX_THREAD *preempted_thread; +#endif +#if TX_MAX_PRIORITIES > 32 +UINT map_index; +#endif + +#ifndef TX_NO_TIMER +TX_TIMER_INTERNAL **timer_list; +TX_TIMER_INTERNAL *next_timer; +TX_TIMER_INTERNAL *timer_ptr; +TX_TIMER_INTERNAL *previous_timer; +ULONG expiration_time; +ULONG delta; +ULONG timeout; +#endif + +#ifdef TX_ENABLE_EVENT_TRACE +TX_TRACE_BUFFER_ENTRY *entry_ptr = TX_NULL; +ULONG time_stamp = ((ULONG) 0); +#endif +UINT processing_complete; + + + /* Set the processing complete flag to false. */ + processing_complete = TX_FALSE; + +#ifndef TX_NOT_INTERRUPTABLE + + /* Disable interrupts. */ + TX_DISABLE +#endif + + /* Pickup the index. */ + core_index = TX_SMP_CORE_ID; + +#ifdef TX_THREAD_SMP_DEBUG_ENABLE + + /* Debug entry. */ + _tx_thread_smp_debug_entry_insert(6, 1, thread_ptr); +#endif + +#ifndef TX_NO_TIMER + + /* Determine if a timeout needs to be activated. */ + if (thread_ptr == _tx_thread_current_ptr[core_index]) + { + + /* Reset time slice for current thread. */ + _tx_timer_time_slice[core_index] = thread_ptr -> tx_thread_new_time_slice; + + /* Pickup the wait option. */ + timeout = thread_ptr -> tx_thread_timer.tx_timer_internal_remaining_ticks; + + /* Determine if an activation is needed. */ + if (timeout != TX_NO_WAIT) + { + + /* Make sure the suspension is not a wait-forever. */ + if (timeout != TX_WAIT_FOREVER) + { + + /* Activate the thread timer with the timeout value setup in the caller. This is now done in-line + for ThreadX SMP so the additional protection logic can be avoided. */ + + /* Activate the thread's timeout timer. */ + + /* Setup pointer to internal timer. */ + timer_ptr = &(thread_ptr -> tx_thread_timer); + + /* Calculate the amount of time remaining for the timer. */ + if (timeout > TX_TIMER_ENTRIES) + { + + /* Set expiration time to the maximum number of entries. */ + expiration_time = TX_TIMER_ENTRIES - ((ULONG) 1); + } + else + { + + /* Timer value fits in the timer entries. */ + + /* Set the expiration time. */ + expiration_time = (UINT) (timeout - ((ULONG) 1)); + } + + /* At this point, we are ready to put the timer on one of + the timer lists. */ + + /* Calculate the proper place for the timer. */ + timer_list = TX_TIMER_POINTER_ADD(_tx_timer_current_ptr, expiration_time); + if (TX_TIMER_INDIRECT_TO_VOID_POINTER_CONVERT(timer_list) >= TX_TIMER_INDIRECT_TO_VOID_POINTER_CONVERT(_tx_timer_list_end)) + { + + /* Wrap from the beginning of the list. */ + delta = TX_TIMER_POINTER_DIF(timer_list, _tx_timer_list_end); + timer_list = TX_TIMER_POINTER_ADD(_tx_timer_list_start, delta); + } + + /* Now put the timer on this list. */ + if ((*timer_list) == TX_NULL) + { + + /* This list is NULL, just put the new timer on it. */ + + /* Setup the links in this timer. */ + timer_ptr -> tx_timer_internal_active_next = timer_ptr; + timer_ptr -> tx_timer_internal_active_previous = timer_ptr; + + /* Setup the list head pointer. */ + *timer_list = timer_ptr; + } + else + { + + /* This list is not NULL, add current timer to the end. */ + next_timer = *timer_list; + previous_timer = next_timer -> tx_timer_internal_active_previous; + previous_timer -> tx_timer_internal_active_next = timer_ptr; + next_timer -> tx_timer_internal_active_previous = timer_ptr; + timer_ptr -> tx_timer_internal_active_next = next_timer; + timer_ptr -> tx_timer_internal_active_previous = previous_timer; + } + + /* Setup list head pointer. */ + timer_ptr -> tx_timer_internal_list_head = timer_list; + } + } + } +#endif + + +#ifdef TX_ENABLE_STACK_CHECKING + + /* Check this thread's stack. */ + TX_THREAD_STACK_CHECK(thread_ptr) +#endif + + +#ifndef TX_NOT_INTERRUPTABLE + + /* Decrement the preempt disable flag. */ + _tx_thread_preempt_disable--; +#endif + +#ifdef TX_THREAD_ENABLE_PERFORMANCE_INFO + + /* Increment the thread's suspend count. */ + thread_ptr -> tx_thread_performance_suspend_count++; + + /* Increment the total number of thread suspensions. */ + _tx_thread_performance_suspend_count++; +#endif + + +#ifndef TX_NOT_INTERRUPTABLE + + /* Check to make sure the thread suspending flag is still set. If not, it + has already been resumed. */ + if ((thread_ptr -> tx_thread_suspending) == TX_TRUE) + { +#endif + + /* Thread state change. */ + TX_THREAD_STATE_CHANGE(thread_ptr, thread_ptr -> tx_thread_state) + + /* Log the thread status change. */ + TX_EL_THREAD_STATUS_CHANGE_INSERT(thread_ptr, thread_ptr -> tx_thread_state) + +#ifdef TX_ENABLE_EVENT_TRACE + + /* If trace is enabled, save the current event pointer. */ + entry_ptr = _tx_trace_buffer_current_ptr; + + /* Log the thread status change. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_SUSPEND, thread_ptr, thread_ptr -> tx_thread_state, TX_POINTER_TO_ULONG_CONVERT(&priority), TX_POINTER_TO_ULONG_CONVERT(_tx_thread_execute_ptr[core_index]), TX_TRACE_INTERNAL_EVENTS) + + /* Save the time stamp for later comparison to verify that + the event hasn't been overwritten by the time we have + computed the next thread to execute. */ + if (entry_ptr != TX_NULL) + { + + /* Save time stamp. */ + time_stamp = entry_ptr -> tx_trace_buffer_entry_time_stamp; + } +#endif + + /* Actually suspend this thread. But first, clear the suspending flag. */ + thread_ptr -> tx_thread_suspending = TX_FALSE; + + /* Pickup priority of thread. */ + priority = thread_ptr -> tx_thread_priority; + +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD + +#if TX_MAX_PRIORITIES > 32 + + /* Calculate the index into the bit map array. */ + map_index = priority/((UINT) 32); +#endif + + /* Determine if this thread has preemption-threshold set. */ + if (thread_ptr -> tx_thread_preempt_threshold < priority) + { + + /* Was this thread with preemption-threshold set actually preempted with preemption-threshold set? */ + if (_tx_thread_preemption_threshold_list[priority] == thread_ptr) + { + + /* Clear the preempted list entry. */ + _tx_thread_preemption_threshold_list[priority] = TX_NULL; + + /* Ensure that this thread's priority is clear in the preempt map. */ + TX_MOD32_BIT_SET(priority, priority_bit) + _tx_thread_preempted_maps[MAP_INDEX] = _tx_thread_preempted_maps[MAP_INDEX] & (~(priority_bit)); + +#if TX_MAX_PRIORITIES > 32 + + /* Determine if there are any other bits set in this preempt map. */ + if (_tx_thread_preempted_maps[MAP_INDEX] == ((ULONG) 0)) + { + + /* No, clear the active bit to signify this preempted map has nothing set. */ + TX_DIV32_BIT_SET(priority, priority_bit) + _tx_thread_preempted_map_active = _tx_thread_preempted_map_active & (~(priority_bit)); + } +#endif + } + } +#endif + + /* Determine if this thread has global preemption disabled. */ + if (thread_ptr == _tx_thread_preemption__threshold_scheduled) + { + + /* Clear the global preemption disable flag. */ + _tx_thread_preemption__threshold_scheduled = TX_NULL; + +#ifndef TX_DISABLE_PREEMPTION_THRESHOLD + + /* Clear the entry in the preempted list. */ + _tx_thread_preemption_threshold_list[thread_ptr -> tx_thread_priority] = TX_NULL; + + /* Calculate the first thread with preemption-threshold active. */ +#if TX_MAX_PRIORITIES > 32 + if (_tx_thread_preempted_map_active != ((ULONG) 0)) +#else + if (_tx_thread_preempted_maps[0] != ((ULONG) 0)) +#endif + { +#if TX_MAX_PRIORITIES > 32 + + /* Calculate the index to find the next highest priority thread ready for execution. */ + priority_map = _tx_thread_preempted_map_active; + + /* Calculate the lowest bit set in the priority map. */ + TX_LOWEST_SET_BIT_CALCULATE(priority_map, map_index) + + /* Calculate the base priority as well. */ + base_priority = map_index * ((UINT) 32); +#else + + /* Setup the base priority to zero. */ + base_priority = ((UINT) 0); +#endif + + /* Setup temporary preempted map. */ + priority_map = _tx_thread_preempted_maps[MAP_INDEX]; + + /* Calculate the lowest bit set in the priority map. */ + TX_LOWEST_SET_BIT_CALCULATE(priority_map, priority_bit_set) + + /* Move priority bit set into priority bit. */ + priority_bit = (ULONG) priority_bit_set; + + /* Setup the highest priority preempted thread. */ + next_preempted = base_priority + priority_bit; + + /* Pickup the next preempted thread. */ + preempted_thread = _tx_thread_preemption_threshold_list[next_preempted]; + + /* Setup the preempted thread. */ + _tx_thread_preemption__threshold_scheduled = preempted_thread; + } +#endif + } + + /* Determine if there are other threads at this priority that are + ready. */ + if (thread_ptr -> tx_thread_ready_next != thread_ptr) + { + + /* Yes, there are other threads at this priority ready. */ + +#ifndef TX_THREAD_SMP_EQUAL_PRIORITY + + /* Remember the head of the priority list. */ + next_thread = _tx_thread_priority_list[priority]; +#endif + + /* Just remove this thread from the priority list. */ + (thread_ptr -> tx_thread_ready_next) -> tx_thread_ready_previous = thread_ptr -> tx_thread_ready_previous; + (thread_ptr -> tx_thread_ready_previous) -> tx_thread_ready_next = thread_ptr -> tx_thread_ready_next; + + /* Determine if this is the head of the priority list. */ + if (_tx_thread_priority_list[priority] == thread_ptr) + { + + /* Update the head pointer of this priority list. */ + _tx_thread_priority_list[priority] = thread_ptr -> tx_thread_ready_next; + +#ifndef TX_THREAD_SMP_EQUAL_PRIORITY + + /* Update the next pointer as well. */ + next_thread = thread_ptr -> tx_thread_ready_next; +#endif + } + } + else + { + +#ifndef TX_THREAD_SMP_EQUAL_PRIORITY + + /* Remember the head of the priority list. */ + next_thread = thread_ptr; +#endif + + /* This is the only thread at this priority ready to run. Set the head + pointer to NULL. */ + _tx_thread_priority_list[priority] = TX_NULL; + +#if TX_MAX_PRIORITIES > 32 + + /* Calculate the index into the bit map array. */ + map_index = priority/((UINT) 32); +#endif + + /* Clear this priority bit in the ready priority bit map. */ + TX_MOD32_BIT_SET(priority, priority_bit) + _tx_thread_priority_maps[MAP_INDEX] = _tx_thread_priority_maps[MAP_INDEX] & (~(priority_bit)); + +#if TX_MAX_PRIORITIES > 32 + + /* Determine if there are any other bits set in this priority map. */ + if (_tx_thread_priority_maps[MAP_INDEX] == ((ULONG) 0)) + { + + /* No, clear the active bit to signify this priority map has nothing set. */ + TX_DIV32_BIT_SET(priority, priority_bit) + _tx_thread_priority_map_active = _tx_thread_priority_map_active & (~(priority_bit)); + } +#endif + } + +#if TX_MAX_PRIORITIES > 32 + + /* Calculate the index to find the next highest priority thread ready for execution. */ + priority_map = _tx_thread_priority_map_active; + + /* Determine if there is anything. */ + if (priority_map != ((ULONG) 0)) + { + + /* Calculate the lowest bit set in the priority map. */ + TX_LOWEST_SET_BIT_CALCULATE(priority_map, map_index) + } +#endif + + /* Setup working variable for the priority map. */ + priority_map = _tx_thread_priority_maps[MAP_INDEX]; + + /* Make a quick check for no other threads ready for execution. */ + if (priority_map == ((ULONG) 0)) + { + +#ifdef TX_ENABLE_EVENT_TRACE + + /* Check that the event time stamp is unchanged. A different + timestamp means that a later event wrote over the thread + suspend event. In that case, do nothing here. */ + if ((entry_ptr != TX_NULL) && (time_stamp == entry_ptr -> tx_trace_buffer_entry_time_stamp)) + { + + /* Timestamp is the same, set the "next thread pointer" to NULL. This can + be used by the trace analysis tool to show idle system conditions. */ +#ifdef TX_MISRA_ENABLE + entry_ptr -> tx_trace_buffer_entry_info_4 = ((ULONG) 0); +#else + entry_ptr -> tx_trace_buffer_entry_information_field_4 = ((ULONG) 0); +#endif + } +#endif + + /* Check to see if the thread is in the execute list. */ + i = thread_ptr -> tx_thread_smp_core_mapped; + if (_tx_thread_execute_ptr[i] == thread_ptr) + { + + /* Clear the entry in the thread execution list. */ + _tx_thread_execute_ptr[i] = TX_NULL; + +#ifdef TX_THREAD_SMP_INTER_CORE_INTERRUPT + + /* Determine if we need to preempt the core. */ + if (i != core_index) + { + + if (_tx_thread_system_state[i] < TX_INITIALIZE_IN_PROGRESS) + { + + /* Preempt the mapped thread. */ + _tx_thread_smp_core_preempt(i); + } + } +#endif + +#ifdef TX_THREAD_SMP_WAKEUP_LOGIC + + /* Does this need to be waked up? */ + if ((i != core_index) && (_tx_thread_execute_ptr[i] != TX_NULL)) + { + + /* Wakeup based on application's macro. */ + TX_THREAD_SMP_WAKEUP(i); + } +#endif + } + +#ifdef TX_THREAD_SMP_DEBUG_ENABLE + + /* Debug entry. */ + _tx_thread_smp_debug_entry_insert(7, 1, thread_ptr); +#endif + +#ifdef TX_ENABLE_EVENT_TRACE + + /* Check that the event time stamp is unchanged. A different + timestamp means that a later event wrote over the system suspend + event. In that case, do nothing here. */ + if ((entry_ptr != TX_NULL) && (time_stamp == entry_ptr -> tx_trace_buffer_entry_time_stamp)) + { + + /* Timestamp is the same, set the "next thread pointer" to the next thread scheduled + for this core. */ +#ifdef TX_MISRA_ENABLE + entry_ptr -> tx_trace_buffer_entry_info_4 = TX_POINTER_TO_ULONG_CONVERT(_tx_thread_execute_ptr[core_index]); +#else + entry_ptr -> tx_trace_buffer_entry_information_field_4 = TX_POINTER_TO_ULONG_CONVERT(_tx_thread_execute_ptr[core_index]); +#endif + } +#endif + + /* Check to see if the caller is a thread and the preempt disable flag is clear. */ + combined_flags = ((ULONG) _tx_thread_system_state[core_index]); + combined_flags = combined_flags | ((ULONG) _tx_thread_preempt_disable); + if (combined_flags == ((ULONG) 0)) + { + + +#ifdef TX_THREAD_ENABLE_PERFORMANCE_INFO + + /* Yes, increment the return to idle return count. */ + _tx_thread_performance_idle_return_count++; +#endif + + +#ifndef TX_NOT_INTERRUPTABLE + + /* Increment the preempt disable flag in order to keep the protection. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE +#endif + + /* If so, return control to the system. */ + _tx_thread_system_return(); + +#ifdef TX_NOT_INTERRUPTABLE + + /* Setup protection again since caller is expecting that it is still in force. */ + _tx_thread_smp_protect(); +#endif + + /* Processing complete, set the flag. */ + processing_complete = TX_TRUE; + } + } + else + { + + /* There are more threads ready to execute. */ + + /* Check to see if the thread is in the execute list. If not, there is nothing else to do. */ + i = thread_ptr -> tx_thread_smp_core_mapped; + if (_tx_thread_execute_ptr[i] == thread_ptr) + { + + /* Clear the entry in the thread execution list. */ + _tx_thread_execute_ptr[i] = TX_NULL; + + /* Determine if preemption-threshold is present in the suspending thread or present in another executing or previously executing + thread. */ + if ((_tx_thread_preemption__threshold_scheduled != TX_NULL) || (thread_ptr -> tx_thread_preempt_threshold < thread_ptr -> tx_thread_priority)) + { + + /* Call the rebalance routine. This routine maps cores and ready threads. */ + _tx_thread_smp_rebalance_execute_list(core_index); + } +#ifdef TX_THREAD_SMP_EQUAL_PRIORITY + else + { + + /* For equal priority SMP, we simply use the rebalance list function. */ + + /* Call the rebalance routine. This routine maps cores and ready threads. */ + _tx_thread_smp_rebalance_execute_list(core_index); + } +#else + else + { + + /* Now we need to find the next, highest-priority thread ready for execution. */ + + /* Start at the priority of the thread suspending, since we know that higher priority threads + have already been evaluated when preemption-threshold is not in effect. */ + next_priority = thread_ptr -> tx_thread_priority; + + /* Determine if there are other threads at the same priority level as the suspending thread. */ + if (next_thread == thread_ptr) + { + + /* No more threads at this priority level. */ + + /* Start at the priority after that of the thread suspending, since we know there are no + other threads at the suspending thread's priority ready to execute. */ + next_priority++; + + /* Set next thread to NULL.. */ + next_thread = TX_NULL; + } + + /* Get the possible cores bit map, based on what has already been scheduled. */ + possible_cores = _tx_thread_smp_possible_cores_get(); + + /* Setup the available cores bit map. In the suspend case, this is simply the core that is now available. */ + available_cores = (((ULONG) 1) << i); + + /* Calculate the possible complex path. */ + complex_path_possible = possible_cores & available_cores; + + /* Loop to find the next highest priority ready thread that is allowed to run on this core. */ + loop_finished = TX_FALSE; + do + { + + /* Determine if there is a thread to examine. */ + if (next_thread == TX_NULL) + { + + /* Calculate the next ready priority. */ + next_priority = _tx_thread_smp_next_priority_find(next_priority); + + /* Determine if there are no more threads to execute. */ + if (next_priority == ((UINT) TX_MAX_PRIORITIES)) + { + + /* Break out of loop. */ + loop_finished = TX_TRUE; + } + else + { + + /* Pickup the next thread to schedule. */ + next_thread = _tx_thread_priority_list[next_priority]; + } + } + + /* Determine if the processing is not complete. */ + if (loop_finished == TX_FALSE) + { + + /* Is the this thread already in the execute list? */ + if (next_thread != _tx_thread_execute_ptr[next_thread -> tx_thread_smp_core_mapped]) + { + + /* No, not already on the execute list. */ + + /* Check to see if the thread has preemption-threshold set. */ + if (next_thread -> tx_thread_preempt_threshold != next_thread -> tx_thread_priority) + { + + /* Call the rebalance routine. This routine maps cores and ready threads. */ + _tx_thread_smp_rebalance_execute_list(core_index); + + /* Get out of the loop. */ + loop_finished = TX_TRUE; + } + else + { + + /* Now determine if this thread is allowed to run on this core. */ + if ((((next_thread -> tx_thread_smp_cores_allowed >> i) & ((ULONG) 1))) != ((ULONG) 0)) + { + + /* Remember this index in the thread control block. */ + next_thread -> tx_thread_smp_core_mapped = i; + + /* Setup the entry in the execution list. */ + _tx_thread_execute_ptr[i] = next_thread; + + /* Found the thread to execute. */ + loop_finished = TX_TRUE; + } + else + { + + /* Determine if nontrivial scheduling is possible. */ + if (complex_path_possible != ((ULONG) 0)) + { + + /* Check for nontrivial scheduling, i.e., can other threads be remapped to allow this thread to be + scheduled. */ + + /* Determine what the possible cores are for this thread. */ + thread_possible_cores = next_thread -> tx_thread_smp_cores_allowed; + + /* Apply the current possible cores. */ + thread_possible_cores = thread_possible_cores & possible_cores; + if (thread_possible_cores != ((ULONG) 0)) + { + + /* Note that we know that the thread must have the target core excluded at this point, + since we failed the test above. */ + + /* Now we need to see if one of the other threads in the non-excluded cores can be moved to make room + for this thread. */ + + /* Default the schedule list to the current execution list. */ + _tx_thread_smp_schedule_list_setup(); + + /* Determine the possible core mapping. */ + test_possible_cores = possible_cores & ~(thread_possible_cores); + + /* Attempt to remap the cores in order to schedule this thread. */ + core = _tx_thread_smp_remap_solution_find(next_thread, available_cores, thread_possible_cores, test_possible_cores); + + /* Determine if remapping was successful. */ + if (core != ((UINT) TX_THREAD_SMP_MAX_CORES)) + { + + /* Clear the execute list. */ + _tx_thread_smp_execute_list_clear(); + + /* Setup the execute list based on the updated schedule list. */ + _tx_thread_smp_execute_list_setup(core_index); + + /* At this point, we are done since we have found a solution for one core. */ + loop_finished = TX_TRUE; + } + else + { + + /* We couldn't assign the thread to any of the cores possible for the thread so update the possible cores for the + next pass so we don't waste time looking at them again! */ + possible_cores = possible_cores & (~thread_possible_cores); + } + } + } + } + } + } + } + + /* Determine if the loop is finished. */ + if (loop_finished == TX_FALSE) + { + + /* Move to the next thread. */ + next_thread = next_thread -> tx_thread_ready_next; + + /* Determine if we are at the head of the list. */ + if (next_thread == _tx_thread_priority_list[next_priority]) + { + + /* Yes, set the next thread pointer to NULL, increment the priority, and continue. */ + next_thread = TX_NULL; + next_priority++; + + /* Determine if there are no more threads to execute. */ + if (next_priority == ((UINT) TX_MAX_PRIORITIES)) + { + + /* Break out of loop. */ + loop_finished = TX_TRUE; + } + } + } + } while (loop_finished == TX_FALSE); + +#ifdef TX_THREAD_SMP_INTER_CORE_INTERRUPT + + /* Determine if we need to preempt the core. */ + if (i != core_index) + { + + /* Make sure thread execution has started. */ + if (_tx_thread_system_state[i] < ((ULONG) TX_INITIALIZE_IN_PROGRESS)) + { + + /* Preempt the mapped thread. */ + _tx_thread_smp_core_preempt(i); + } + } +#endif + +#ifdef TX_THREAD_SMP_WAKEUP_LOGIC + + /* Does this need to be waked up? */ + if (i != core_index) + { + + /* Check to make sure there a thread to execute for this core. */ + if (_tx_thread_execute_ptr[i] != TX_NULL) + { + + /* Wakeup based on application's macro. */ + TX_THREAD_SMP_WAKEUP(i); + } + } +#endif + } +#endif + } + } + +#ifndef TX_NOT_INTERRUPTABLE + + } +#endif + + /* Check to see if the processing is complete. */ + if (processing_complete == TX_FALSE) + { + +#ifdef TX_THREAD_SMP_DEBUG_ENABLE + + /* Debug entry. */ + _tx_thread_smp_debug_entry_insert(7, 1, thread_ptr); +#endif + +#ifdef TX_ENABLE_EVENT_TRACE + + /* Check that the event time stamp is unchanged. A different + timestamp means that a later event wrote over the thread + suspend event. In that case, do nothing here. */ + if ((entry_ptr != TX_NULL) && (time_stamp == entry_ptr -> tx_trace_buffer_entry_time_stamp)) + { + + /* Timestamp is the same, set the "next thread pointer" to the next thread scheduled + for this core. */ +#ifdef TX_MISRA_ENABLE + entry_ptr -> tx_trace_buffer_entry_info_4 = TX_POINTER_TO_ULONG_CONVERT(_tx_thread_execute_ptr[core_index]); +#else + entry_ptr -> tx_trace_buffer_entry_information_field_4 = TX_POINTER_TO_ULONG_CONVERT(_tx_thread_execute_ptr[core_index]); +#endif + } +#endif + + /* Determine if a preemption condition is present. */ + if (_tx_thread_current_ptr[core_index] != _tx_thread_execute_ptr[core_index]) + { + +#ifdef TX_THREAD_SMP_WAKEUP_LOGIC + + /* Loop to wakeup any cores that have a thread ready to schedule. */ + i = ((UINT) 0); +#ifndef TX_THREAD_SMP_DYNAMIC_CORE_MAX + + while (i < ((UINT) TX_THREAD_SMP_MAX_CORES)) +#else + + while (i < _tx_thread_smp_max_cores) +#endif + { + + /* Is there a thread for this core? */ + if (_tx_thread_execute_ptr[i] != NULL) + { + + /* Yes, wake it up! */ + TX_THREAD_SMP_WAKEUP(i); + } + + /* Move to next entry. */ + i++; + } +#endif + +#ifdef TX_ENABLE_STACK_CHECKING + + /* Pickup the next execute pointer. */ + thread_ptr = _tx_thread_execute_ptr[core_index]; + + /* Determine if there is a thread pointer. */ + if (thread_ptr != TX_NULL) + { + + /* Check this thread's stack. */ + TX_THREAD_STACK_CHECK(thread_ptr) + } +#endif + + /* Determine if preemption should take place. This is only possible if the current thread pointer is + not the same as the execute thread pointer AND the system state and preempt disable flags are clear. */ + if (_tx_thread_system_state[core_index] == ((ULONG) 0)) + { + + /* Check the preempt disable flag. */ + if (_tx_thread_preempt_disable == ((UINT) 0)) + { + +#ifdef TX_THREAD_ENABLE_PERFORMANCE_INFO + + /* Determine if an idle system return is present. */ + if (_tx_thread_execute_ptr[core_index] == TX_NULL) + { + + /* Yes, increment the return to idle return count. */ + _tx_thread_performance_idle_return_count++; + } + else + { + + /* No, there is another thread ready to run and will be scheduled upon return. */ + _tx_thread_performance_non_idle_return_count++; + } +#endif + + +#ifndef TX_NOT_INTERRUPTABLE + + /* Increment the preempt disable flag in order to keep the protection. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE +#endif + + /* Preemption is needed - return to the system! */ + _tx_thread_system_return(); + +#ifdef TX_NOT_INTERRUPTABLE + + /* Setup protection again since caller is expecting that it is still in force. */ + _tx_thread_smp_protect(); +#endif + +#ifndef TX_NOT_INTERRUPTABLE + + /* Set the processing complete flag. */ + processing_complete = TX_TRUE; +#endif + } + } + } + +#ifndef TX_NOT_INTERRUPTABLE + + /* Determine if processing is complete. If so, no need to restore interrupts. */ + if (processing_complete == TX_FALSE) + { + + /* Restore interrupts. */ + TX_RESTORE + } +#endif + } +} + +#ifdef TX_NOT_INTERRUPTABLE +VOID _tx_thread_system_ni_suspend(TX_THREAD *thread_ptr, ULONG timeout) +{ + + /* Setup timeout. */ + thread_ptr -> tx_thread_timer.tx_timer_internal_remaining_ticks = timeout; + + /* Call system suspend function. */ + _tx_thread_system_suspend(thread_ptr); +} +#endif + diff --git a/common_smp/src/tx_thread_terminate.c b/common_smp/src/tx_thread_terminate.c new file mode 100644 index 00000000..54fc2076 --- /dev/null +++ b/common_smp/src/tx_thread_terminate.c @@ -0,0 +1,310 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_thread.h" +#include "tx_timer.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_terminate PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles application thread terminate requests. Once */ +/* a thread is terminated, it cannot be executed again unless it is */ +/* deleted and recreated. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread to suspend */ +/* */ +/* OUTPUT */ +/* */ +/* status Return completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_system_deactivate Timer deactivate function */ +/* _tx_thread_system_suspend Actual thread suspension */ +/* _tx_thread_system_ni_suspend Non-interruptable suspend */ +/* thread */ +/* _tx_thread_system_preempt_check Check for preemption */ +/* Suspend Cleanup Routine Suspension cleanup function */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_thread_terminate(TX_THREAD *thread_ptr) +{ + +TX_INTERRUPT_SAVE_AREA + +VOID (*suspend_cleanup)(struct TX_THREAD_STRUCT *suspend_thread_ptr, ULONG suspension_sequence); +#ifndef TX_DISABLE_NOTIFY_CALLBACKS +VOID (*entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT id); +#endif +UINT status; +ULONG suspension_sequence; + + + /* Default to successful completion. */ + status = TX_SUCCESS; + + /* Lockout interrupts while the thread is being terminated. */ + TX_DISABLE + + /* Deactivate thread timer, if active. */ + _tx_timer_system_deactivate(&thread_ptr -> tx_thread_timer); + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_TERMINATE, thread_ptr, thread_ptr -> tx_thread_state, TX_POINTER_TO_ULONG_CONVERT(&suspend_cleanup), 0, TX_TRACE_THREAD_EVENTS) + + /* Log this kernel call. */ + TX_EL_THREAD_TERMINATE_INSERT + + /* Is the thread already terminated? */ + if (thread_ptr -> tx_thread_state == TX_TERMINATED) + { + + /* Restore interrupts. */ + TX_RESTORE + + /* Return success since thread is already terminated. */ + status = TX_SUCCESS; + } + + /* Check the specified thread's current status. */ + else if (thread_ptr -> tx_thread_state != TX_COMPLETED) + { + + /* Disable preemption. */ + _tx_thread_preempt_disable++; + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine. */ + entry_exit_notify = thread_ptr -> tx_thread_entry_exit_notify; +#endif + + /* Check to see if the thread is currently ready. */ + if (thread_ptr -> tx_thread_state == TX_READY) + { + + /* Set the state to terminated. */ + thread_ptr -> tx_thread_state = TX_TERMINATED; + + /* Thread state change. */ + TX_THREAD_STATE_CHANGE(thread_ptr, TX_TERMINATED) + +#ifdef TX_NOT_INTERRUPTABLE + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has exited! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_EXIT); + } +#endif + + /* Call actual non-interruptable thread suspension routine. */ + _tx_thread_system_ni_suspend(thread_ptr, ((ULONG) 0)); +#else + + /* Set the suspending flag. */ + thread_ptr -> tx_thread_suspending = TX_TRUE; + + /* Setup for no timeout period. */ + thread_ptr -> tx_thread_timer.tx_timer_internal_remaining_ticks = ((ULONG) 0); + + /* Disable preemption. */ + _tx_thread_preempt_disable++; + + /* Since the thread is currently ready, we don't need to + worry about calling the suspend cleanup routine! */ + + /* Restore interrupts. */ + TX_RESTORE + + /* Perform any additional activities for tool or user purpose. */ + TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has exited! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_EXIT); + } +#endif + + /* Call actual thread suspension routine. */ + _tx_thread_system_suspend(thread_ptr); + + /* Disable interrupts. */ + TX_DISABLE +#endif + } + else + { + + /* Change the state to terminated. */ + thread_ptr -> tx_thread_state = TX_TERMINATED; + + /* Thread state change. */ + TX_THREAD_STATE_CHANGE(thread_ptr, TX_TERMINATED) + + /* Set the suspending flag. This prevents the thread from being + resumed before the cleanup routine is executed. */ + thread_ptr -> tx_thread_suspending = TX_TRUE; + + /* Pickup the cleanup routine address. */ + suspend_cleanup = thread_ptr -> tx_thread_suspend_cleanup; + +#ifndef TX_NOT_INTERRUPTABLE + + /* Pickup the suspension sequence number that is used later to verify that the + cleanup is still necessary. */ + suspension_sequence = thread_ptr -> tx_thread_suspension_sequence; +#else + + /* When not interruptable is selected, the suspension sequence is not used - just set to 0. */ + suspension_sequence = ((ULONG) 0); +#endif + +#ifndef TX_NOT_INTERRUPTABLE + + /* Restore interrupts. */ + TX_RESTORE +#endif + + /* Call any cleanup routines. */ + if (suspend_cleanup != TX_NULL) + { + + /* Yes, there is a function to call. */ + (suspend_cleanup)(thread_ptr, suspension_sequence); + } + +#ifndef TX_NOT_INTERRUPTABLE + + /* Disable interrupts. */ + TX_DISABLE +#endif + + /* Clear the suspending flag. */ + thread_ptr -> tx_thread_suspending = TX_FALSE; + +#ifndef TX_NOT_INTERRUPTABLE + + /* Restore interrupts. */ + TX_RESTORE +#endif + + /* Perform any additional activities for tool or user purpose. */ + TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has exited! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_EXIT); + } +#endif + +#ifndef TX_NOT_INTERRUPTABLE + + /* Disable interrupts. */ + TX_DISABLE +#endif + } + +#ifndef TX_NOT_INTERRUPTABLE + + /* Restore interrupts. */ + TX_RESTORE +#endif + + /* Determine if the application is using mutexes. */ + if (_tx_thread_mutex_release != TX_NULL) + { + + /* Yes, call the mutex release function via a function pointer that + is setup during initialization. */ + (_tx_thread_mutex_release)(thread_ptr); + } + +#ifndef TX_NOT_INTERRUPTABLE + + /* Disable interrupts. */ + TX_DISABLE +#endif + + /* Enable preemption. */ + _tx_thread_preempt_disable--; + + /* Restore interrupts. */ + TX_RESTORE + } + else + { + + /* Restore interrupts. */ + TX_RESTORE + } + + /* Check for preemption. */ + _tx_thread_system_preempt_check(); + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/tx_thread_time_slice.c b/common_smp/src/tx_thread_time_slice.c new file mode 100644 index 00000000..1c2796b9 --- /dev/null +++ b/common_smp/src/tx_thread_time_slice.c @@ -0,0 +1,358 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_timer.h" +#include "tx_thread.h" +#include "tx_trace.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_time_slice PORTABLE SMP */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function moves the currently executing thread to the end of */ +/* the threads ready at the same priority level as a result of a */ +/* time-slice interrupt. If no other thread of the same priority is */ +/* ready, this function simply returns. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_smp_rebalance_execute_list Rebalance the execution list */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_timer_interrupt Timer interrupt handling */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_time_slice(VOID) +{ + +ULONG core_index, current_core; +UINT priority; +TX_THREAD *thread_ptr; +TX_THREAD *next_thread; +TX_THREAD *previous_thread; +TX_THREAD *head_ptr; +TX_THREAD *tail_ptr; +UINT loop_finished; +UINT rebalance; +ULONG excluded; +#ifdef TX_ENABLE_EVENT_TRACE +ULONG system_state; +UINT preempt_disable; +#endif + + + /* Quick check for expiration. */ +#if TX_THREAD_SMP_MAX_CORES == 1 + if (_tx_timer_time_slice[0] != 0) + { +#endif +#if TX_THREAD_SMP_MAX_CORES == 2 + if ((_tx_timer_time_slice[0] != ((ULONG) 0)) || (_tx_timer_time_slice[1] != ((ULONG) 0))) + { +#endif +#if TX_THREAD_SMP_MAX_CORES == 3 + if ((_tx_timer_time_slice[0] != ((ULONG) 0)) || (_tx_timer_time_slice[1] != ((ULONG) 0)) || (_tx_timer_time_slice[2] != ((ULONG) 0))) + { +#endif +#if TX_THREAD_SMP_MAX_CORES == 4 + if ((_tx_timer_time_slice[0] != ((ULONG) 0)) || (_tx_timer_time_slice[1] != ((ULONG) 0)) || (_tx_timer_time_slice[2] != ((ULONG) 0)) || (_tx_timer_time_slice[3] != ((ULONG) 0))) + { +#endif + + /* Initialize the rebalance flag to false. */ + rebalance = TX_FALSE; + + /* Get the core index. */ + current_core = TX_SMP_CORE_ID; + + /* Loop to process all time-slices. */ + +#ifndef TX_THREAD_SMP_DYNAMIC_CORE_MAX + + for (core_index = ((ULONG) 0); core_index < ((ULONG) TX_THREAD_SMP_MAX_CORES); core_index++) +#else + + for (core_index = ((ULONG) 0); core_index < _tx_thread_smp_max_cores; core_index++) +#endif + { + + /* Determine if there is a time-slice active on this core. */ + if (_tx_timer_time_slice[core_index] != ((ULONG) 0)) + { + + /* Time-slice is active, decrement it for this core. */ + _tx_timer_time_slice[core_index]--; + + /* Has the time-slice expired? */ + if (_tx_timer_time_slice[core_index] == ((ULONG) 0)) + { + + /* Yes, time-slice on this core has expired. */ + + /* Pickup the current thread pointer. */ + thread_ptr = _tx_thread_current_ptr[core_index]; + + /* Make sure the thread is still active, i.e. not suspended. */ + if ((thread_ptr != TX_NULL) && (thread_ptr -> tx_thread_state == TX_READY) && (thread_ptr -> tx_thread_time_slice != ((ULONG) 0))) + { + + /* Yes, thread is still active and time-slice has expired. */ + + /* Setup a fresh time-slice for the thread. */ + thread_ptr -> tx_thread_time_slice = thread_ptr -> tx_thread_new_time_slice; + + /* Reset the actual time-slice variable. */ + _tx_timer_time_slice[core_index] = thread_ptr -> tx_thread_time_slice; + +#ifdef TX_THREAD_SMP_DEBUG_ENABLE + + /* Debug entry. */ + _tx_thread_smp_debug_entry_insert(10, 0, thread_ptr); +#endif + +#ifdef TX_ENABLE_STACK_CHECKING + + /* Check this thread's stack. */ + TX_THREAD_STACK_CHECK(thread_ptr) +#endif + +#ifdef TX_THREAD_ENABLE_PERFORMANCE_INFO + + /* Increment the thread's time-slice counter. */ + thread_ptr -> tx_thread_performance_time_slice_count++; + + /* Increment the total number of thread time-slice operations. */ + _tx_thread_performance_time_slice_count++; +#endif + + /* Setup the priority. */ + priority = thread_ptr -> tx_thread_priority; + + /* Determine if preemption-threshold is set. If so, don't time-slice. */ + if (priority == thread_ptr -> tx_thread_preempt_threshold) + { + + /* Preemption-threshold is not set. */ + + /* Pickup the next thread. */ + next_thread = thread_ptr -> tx_thread_ready_next; + + /* Pickup the head of the list. */ + head_ptr = _tx_thread_priority_list[priority]; + + /* Pickup the list tail. */ + tail_ptr = head_ptr -> tx_thread_ready_previous; + + /* Determine if this thread is not the tail pointer. */ + if (thread_ptr != tail_ptr) + { + + /* Not the tail pointer, this thread must be moved to the end of the ready list. */ + + /* Determine if this thread is at the head of the list. */ + if (head_ptr == thread_ptr) + { + + /* Simply move the head pointer to put this thread at the end of the ready list at this priority. */ + _tx_thread_priority_list[priority] = next_thread; + } + else + { + + /* Now we need to remove this thread from its current position and place it at the end of the list. */ + + /* Pickup the previous thread pointer. */ + previous_thread = thread_ptr -> tx_thread_ready_previous; + + /* Remove the thread from the ready list. */ + next_thread -> tx_thread_ready_previous = previous_thread; + previous_thread -> tx_thread_ready_next = next_thread; + + /* Insert the thread at the end of the list. */ + tail_ptr -> tx_thread_ready_next = thread_ptr; + head_ptr -> tx_thread_ready_previous = thread_ptr; + thread_ptr -> tx_thread_ready_previous = tail_ptr; + thread_ptr -> tx_thread_ready_next = head_ptr; + } + + /* Make sure the current core execute pointer is still this thread. If not, a higher priority thread has already + preempted it either from another ISR or from the timer processing. */ + if (_tx_thread_execute_ptr[core_index] != thread_ptr) + { + + /* Set the rebalance flag. */ + rebalance = TX_TRUE; + } + + /* Determine if the rebalance flag has been set already. If so, don't bother trying to update the + execute list from this routine. */ + if (rebalance == TX_FALSE) + { + + /* Set the loop finished flag to false. */ + loop_finished = TX_FALSE; + + /* Determine if there is a thread at the same priority that isn't currently executing. */ + do + { + + /* Isolate the exclusion for this core. */ + excluded = (next_thread -> tx_thread_smp_cores_excluded >> core_index) & ((ULONG) 1); + + /* Determine if the next thread has preemption-threshold set. */ + if (next_thread -> tx_thread_preempt_threshold < next_thread -> tx_thread_priority) + { + + /* Set the rebalance flag. */ + rebalance = TX_TRUE; + + /* Get out of the loop. */ + loop_finished = TX_TRUE; + } + + /* Determine if the next thread is excluded from running on this core. */ + else if (excluded == ((ULONG) 1)) + { + + /* Set the rebalance flag. */ + rebalance = TX_TRUE; + + /* Get out of the loop. */ + loop_finished = TX_TRUE; + } + else + { + + /* Is the next thread not scheduled */ + if (next_thread != _tx_thread_execute_ptr[next_thread -> tx_thread_smp_core_mapped]) + { + + /* Remember this index in the thread control block. */ + next_thread -> tx_thread_smp_core_mapped = core_index; + + /* Setup the entry in the execution list. */ + _tx_thread_execute_ptr[core_index] = next_thread; + +#ifdef TX_THREAD_SMP_INTER_CORE_INTERRUPT + + /* Determine if we need to preempt the core. */ + if (core_index != current_core) + { + + /* Preempt the mapped thread. */ + _tx_thread_smp_core_preempt(core_index); + } +#endif + /* Get out of the loop. */ + loop_finished = TX_TRUE; + } + } + + /* Is the loop fininshed? */ + if (loop_finished == TX_TRUE) + { + + /* Yes, break out of the loop. */ + break; + } + + /* Move to the next thread at this priority. */ + next_thread = next_thread -> tx_thread_ready_next; + + } while (next_thread != thread_ptr); + } + } + +#ifdef TX_THREAD_SMP_DEBUG_ENABLE + + /* Debug entry. */ + _tx_thread_smp_debug_entry_insert(11, 0, thread_ptr); +#endif + } + } + } + } + } + + /* Determine if rebalance was set. */ + if (rebalance == TX_TRUE) + { + + /* Call the rebalance routine. This routine maps cores and ready threads. */ + _tx_thread_smp_rebalance_execute_list(current_core); + } + +#ifdef TX_ENABLE_EVENT_TRACE + + /* Pickup the volatile information. */ + system_state = TX_THREAD_GET_SYSTEM_STATE(); + preempt_disable = _tx_thread_preempt_disable; + + /* Insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_TIME_SLICE, _tx_thread_execute_ptr[0], system_state, preempt_disable, TX_POINTER_TO_ULONG_CONVERT(&thread_ptr), TX_TRACE_INTERNAL_EVENTS) +#endif + +#if TX_THREAD_SMP_MAX_CORES == 1 + } +#endif +#if TX_THREAD_SMP_MAX_CORES == 2 + } +#endif +#if TX_THREAD_SMP_MAX_CORES == 3 + } +#endif +#if TX_THREAD_SMP_MAX_CORES == 4 + } +#endif +} + diff --git a/common_smp/src/tx_thread_time_slice_change.c b/common_smp/src/tx_thread_time_slice_change.c new file mode 100644 index 00000000..9a7813c0 --- /dev/null +++ b/common_smp/src/tx_thread_time_slice_change.c @@ -0,0 +1,124 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +#include "tx_trace.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_time_slice_change PORTABLE SMP */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes thread time slice change requests. The */ +/* previous time slice is returned to the caller. If the new request */ +/* is made for an executing thread, it is also placed in the actual */ +/* time-slice countdown variable. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread */ +/* new_time_slice New time slice */ +/* old_time_slice Old time slice */ +/* */ +/* OUTPUT */ +/* */ +/* status Service return status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_thread_time_slice_change(TX_THREAD *thread_ptr, ULONG new_time_slice, ULONG *old_time_slice) +{ + +TX_INTERRUPT_SAVE_AREA + +ULONG core_index; + + + /* Lockout interrupts while the thread is being resumed. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_TIME_SLICE_CHANGE, thread_ptr, new_time_slice, thread_ptr -> tx_thread_new_time_slice, 0, TX_TRACE_THREAD_EVENTS) + + /* Log this kernel call. */ + TX_EL_THREAD_TIME_SLICE_CHANGE_INSERT + + /* Return the old time slice. */ + *old_time_slice = thread_ptr -> tx_thread_new_time_slice; + + /* Setup the new time-slice. */ + thread_ptr -> tx_thread_time_slice = new_time_slice; + thread_ptr -> tx_thread_new_time_slice = new_time_slice; + + /* Pickup index. */ + core_index = thread_ptr -> tx_thread_smp_core_mapped; + + /* Determine if this thread is the currently executing thread. */ +#ifndef TX_THREAD_SMP_DYNAMIC_CORE_MAX + + if ((core_index < ((ULONG) TX_THREAD_SMP_MAX_CORES)) && (thread_ptr == _tx_thread_current_ptr[core_index])) +#else + + if ((core_index < _tx_thread_smp_max_cores) && (thread_ptr == _tx_thread_current_ptr[core_index])) +#endif + { + + /* Yes, update the time-slice countdown variable. */ + _tx_timer_time_slice[core_index] = new_time_slice; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return completion status. */ + return(TX_SUCCESS); +} + diff --git a/common_smp/src/tx_thread_timeout.c b/common_smp/src/tx_thread_timeout.c new file mode 100644 index 00000000..e96989e5 --- /dev/null +++ b/common_smp/src/tx_thread_timeout.c @@ -0,0 +1,164 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_timeout PORTABLE SMP */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles thread timeout processing. Timeouts occur in */ +/* two flavors, namely the thread sleep timeout and all other service */ +/* call timeouts. Thread sleep timeouts are processed locally, while */ +/* the others are processed by the appropriate suspension clean-up */ +/* service. */ +/* */ +/* INPUT */ +/* */ +/* timeout_input Contains the thread pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* Suspension Cleanup Functions */ +/* _tx_thread_system_resume Resume thread */ +/* _tx_thread_system_ni_resume Non-interruptable resume thread */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_timer_expiration_process Timer expiration function */ +/* _tx_timer_thread_entry Timer thread function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_timeout(ULONG timeout_input) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_THREAD *thread_ptr; +VOID (*suspend_cleanup)(struct TX_THREAD_STRUCT *suspend_thread_ptr, ULONG suspension_sequence); +ULONG suspension_sequence; + + + /* Pickup the thread pointer. */ + TX_THREAD_TIMEOUT_POINTER_SETUP(thread_ptr) + + /* Disable interrupts. */ + TX_DISABLE + + /* Determine how the thread is currently suspended. */ + if (thread_ptr -> tx_thread_state == TX_SLEEP) + { + +#ifdef TX_NOT_INTERRUPTABLE + + /* Resume the thread! */ + _tx_thread_system_ni_resume(thread_ptr); + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Increment the disable preemption flag. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Lift the suspension on the sleeping thread. */ + _tx_thread_system_resume(thread_ptr); +#endif + } + else + { + + /* Process all other suspension timeouts. */ + +#ifdef TX_THREAD_ENABLE_PERFORMANCE_INFO + + /* Increment the total number of thread timeouts. */ + _tx_thread_performance_timeout_count++; + + /* Increment the number of timeouts for this thread. */ + thread_ptr -> tx_thread_performance_timeout_count++; +#endif + + /* Pickup the cleanup routine address. */ + suspend_cleanup = thread_ptr -> tx_thread_suspend_cleanup; + +#ifndef TX_NOT_INTERRUPTABLE + + /* Pickup the suspension sequence number that is used later to verify that the + cleanup is still necessary. */ + suspension_sequence = thread_ptr -> tx_thread_suspension_sequence; +#else + + /* When not interruptable is selected, the suspension sequence is not used - just set to 0. */ + suspension_sequence = ((ULONG) 0); +#endif + +#ifndef TX_NOT_INTERRUPTABLE + + /* Restore interrupts. */ + TX_RESTORE +#endif + + /* Call any cleanup routines. */ + if (suspend_cleanup != TX_NULL) + { + + /* Yes, there is a function to call. */ + (suspend_cleanup)(thread_ptr, suspension_sequence); + } + +#ifdef TX_NOT_INTERRUPTABLE + + /* Restore interrupts. */ + TX_RESTORE +#endif + } +} + diff --git a/common_smp/src/tx_thread_wait_abort.c b/common_smp/src/tx_thread_wait_abort.c new file mode 100644 index 00000000..d0513175 --- /dev/null +++ b/common_smp/src/tx_thread_wait_abort.c @@ -0,0 +1,235 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_wait_abort PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function aborts the wait condition that the specified thread */ +/* is in - regardless of what object the thread is waiting on - and */ +/* returns a TX_WAIT_ABORTED status to the specified thread. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread to abort the wait on */ +/* */ +/* OUTPUT */ +/* */ +/* status Return completion status */ +/* */ +/* CALLS */ +/* */ +/* Suspension Cleanup Functions */ +/* _tx_thread_system_resume */ +/* _tx_thread_system_ni_resume Non-interruptable resume thread */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_thread_wait_abort(TX_THREAD *thread_ptr) +{ + +TX_INTERRUPT_SAVE_AREA + +VOID (*suspend_cleanup)(struct TX_THREAD_STRUCT *suspend_thread_ptr, ULONG suspension_sequence); +UINT status; +ULONG suspension_sequence; + + + /* Disable interrupts. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_WAIT_ABORT, thread_ptr, thread_ptr -> tx_thread_state, 0, 0, TX_TRACE_THREAD_EVENTS) + + /* Log this kernel call. */ + TX_EL_THREAD_WAIT_ABORT_INSERT + + /* Determine if the thread is currently suspended. */ + if (thread_ptr -> tx_thread_state < TX_SLEEP) + { + + /* Thread is either ready, completed, terminated, or in a pure + suspension condition. */ + + /* Restore interrupts. */ + TX_RESTORE + + /* Just return with an error message to indicate that + nothing was done. */ + status = TX_WAIT_ABORT_ERROR; + } + else + { + + /* Check for a sleep condition. */ + if (thread_ptr -> tx_thread_state == TX_SLEEP) + { + + /* Set the state to terminated. */ + thread_ptr -> tx_thread_state = TX_SUSPENDED; + + /* Set the TX_WAIT_ABORTED status in the thread that is + sleeping. */ + thread_ptr -> tx_thread_suspend_status = TX_WAIT_ABORTED; + + /* Make sure there isn't a suspend cleanup routine. */ + thread_ptr -> tx_thread_suspend_cleanup = TX_NULL; + +#ifndef TX_NOT_INTERRUPTABLE + + /* Increment the disable preemption flag. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE +#endif + } + else + { + + /* Process all other suspension timeouts. */ + + /* Set the state to suspended. */ + thread_ptr -> tx_thread_state = TX_SUSPENDED; + + /* Pickup the cleanup routine address. */ + suspend_cleanup = thread_ptr -> tx_thread_suspend_cleanup; + +#ifndef TX_NOT_INTERRUPTABLE + + /* Pickup the suspension sequence number that is used later to verify that the + cleanup is still necessary. */ + suspension_sequence = thread_ptr -> tx_thread_suspension_sequence; +#else + + /* When not interruptable is selected, the suspension sequence is not used - just set to 0. */ + suspension_sequence = ((ULONG) 0); +#endif + + /* Set the TX_WAIT_ABORTED status in the thread that was + suspended. */ + thread_ptr -> tx_thread_suspend_status = TX_WAIT_ABORTED; + +#ifndef TX_NOT_INTERRUPTABLE + + /* Increment the disable preemption flag. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE +#endif + + /* Call any cleanup routines. */ + if (suspend_cleanup != TX_NULL) + { + + /* Yes, there is a function to call. */ + (suspend_cleanup)(thread_ptr, suspension_sequence); + } + } + + /* If the abort of the thread wait was successful, if so resume the thread. */ + if (thread_ptr -> tx_thread_suspend_status == TX_WAIT_ABORTED) + { + +#ifdef TX_THREAD_ENABLE_PERFORMANCE_INFO + + /* Increment the total number of thread wait aborts. */ + _tx_thread_performance_wait_abort_count++; + + /* Increment this thread's wait abort count. */ + thread_ptr -> tx_thread_performance_wait_abort_count++; +#endif + +#ifdef TX_NOT_INTERRUPTABLE + + /* Resume the thread! */ + _tx_thread_system_ni_resume(thread_ptr); + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Lift the suspension on the previously waiting thread. */ + _tx_thread_system_resume(thread_ptr); +#endif + + /* Return a successful status. */ + status = TX_SUCCESS; + } + else + { + +#ifdef TX_NOT_INTERRUPTABLE + + /* Restore interrupts. */ + TX_RESTORE + +#else + + /* Disable interrupts. */ + TX_DISABLE + + /* Decrement the disable preemption flag. */ + _tx_thread_preempt_disable--; + + /* Restore interrupts. */ + TX_RESTORE +#endif + + /* Return with an error message to indicate that + nothing was done. */ + status = TX_WAIT_ABORT_ERROR; + } + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/tx_time_get.c b/common_smp/src/tx_time_get.c new file mode 100644 index 00000000..72697778 --- /dev/null +++ b/common_smp/src/tx_time_get.c @@ -0,0 +1,100 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_timer.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_time_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves the internal, free-running, system clock */ +/* and returns it to the caller. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* _tx_timer_system_clock Returns the system clock value */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +ULONG _tx_time_get(VOID) +{ + +TX_INTERRUPT_SAVE_AREA + +#ifdef TX_ENABLE_EVENT_TRACE +ULONG another_temp_time = ((ULONG) 0); +#endif +ULONG temp_time; + + + /* Disable interrupts. */ + TX_DISABLE + + /* Pickup the system clock time. */ + temp_time = _tx_timer_system_clock; + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_TIME_GET, TX_ULONG_TO_POINTER_CONVERT(temp_time), TX_POINTER_TO_ULONG_CONVERT(&another_temp_time), 0, 0, TX_TRACE_TIME_EVENTS) + + /* Log this kernel call. */ + TX_EL_TIME_GET_INSERT + + /* Restore interrupts. */ + TX_RESTORE + + /* Return the time. */ + return(temp_time); +} + diff --git a/common_smp/src/tx_time_set.c b/common_smp/src/tx_time_set.c new file mode 100644 index 00000000..053a540a --- /dev/null +++ b/common_smp/src/tx_time_set.c @@ -0,0 +1,92 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_timer.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_time_set PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function modifies the internal, free-running, system clock */ +/* as specified by the caller. */ +/* */ +/* INPUT */ +/* */ +/* new_time New time value */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_time_set(ULONG new_time) +{ + +TX_INTERRUPT_SAVE_AREA + + + /* Disable interrupts. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_TIME_SET, TX_ULONG_TO_POINTER_CONVERT(new_time), 0, 0, 0, TX_TRACE_TIME_EVENTS) + + /* Log this kernel call. */ + TX_EL_TIME_SET_INSERT + + /* Set the system clock time. */ + _tx_timer_system_clock = new_time; + + /* Restore interrupts. */ + TX_RESTORE +} + diff --git a/common_smp/src/tx_timer_activate.c b/common_smp/src/tx_timer_activate.c new file mode 100644 index 00000000..b529c109 --- /dev/null +++ b/common_smp/src/tx_timer_activate.c @@ -0,0 +1,135 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_timer.h" +#ifdef TX_ENABLE_EVENT_TRACE +#include "tx_trace.h" +#endif + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_activate PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function activates the specified application timer. */ +/* */ +/* INPUT */ +/* */ +/* timer_ptr Pointer to timer control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SUCCESS Always returns success */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_system_activate Actual timer activation function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_timer_activate(TX_TIMER *timer_ptr) +{ + +TX_INTERRUPT_SAVE_AREA + +UINT status; + + + /* Disable interrupts to put the timer on the created list. */ + TX_DISABLE + +#ifdef TX_ENABLE_EVENT_TRACE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_TIMER_ACTIVATE, timer_ptr, 0, 0, 0, TX_TRACE_TIMER_EVENTS) +#endif + +#ifdef TX_ENABLE_EVENT_LOGGING + + /* Log this kernel call. */ + TX_EL_TIMER_ACTIVATE_INSERT +#endif + + /* Check for an already active timer. */ + if (timer_ptr -> tx_timer_internal.tx_timer_internal_list_head != TX_NULL) + { + + /* Timer is already active, return an error. */ + status = TX_ACTIVATE_ERROR; + } + + /* Check for a timer with a zero expiration. */ + else if (timer_ptr -> tx_timer_internal.tx_timer_internal_remaining_ticks == ((ULONG) 0)) + { + + /* Timer is being activated with a zero expiration. */ + status = TX_ACTIVATE_ERROR; + } + else + { + +#ifdef TX_TIMER_ENABLE_PERFORMANCE_INFO + + /* Increment the total activations counter. */ + _tx_timer_performance_activate_count++; + + /* Increment the number of activations on this timer. */ + timer_ptr -> tx_timer_performance_activate_count++; +#endif + + /* Call actual activation function. */ + _tx_timer_system_activate(&(timer_ptr -> tx_timer_internal)); + + /* Return a successful status. */ + status = TX_SUCCESS; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/tx_timer_change.c b/common_smp/src/tx_timer_change.c new file mode 100644 index 00000000..b097012e --- /dev/null +++ b/common_smp/src/tx_timer_change.c @@ -0,0 +1,103 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_timer.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_change PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function modifies an application timer as specified by the */ +/* input. */ +/* */ +/* INPUT */ +/* */ +/* timer_ptr Pointer to timer control block */ +/* initial_ticks Initial expiration ticks */ +/* reschedule_ticks Reschedule ticks */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SUCCESS Successful completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_timer_change(TX_TIMER *timer_ptr, ULONG initial_ticks, ULONG reschedule_ticks) +{ + +TX_INTERRUPT_SAVE_AREA + + + /* Disable interrupts to put the timer on the created list. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_TIMER_CHANGE, timer_ptr, initial_ticks, reschedule_ticks, 0, TX_TRACE_TIMER_EVENTS) + + /* Log this kernel call. */ + TX_EL_TIMER_CHANGE_INSERT + + /* Determine if the timer is active. */ + if (timer_ptr -> tx_timer_internal.tx_timer_internal_list_head == TX_NULL) + { + + /* Setup the new expiration fields. */ + timer_ptr -> tx_timer_internal.tx_timer_internal_remaining_ticks = initial_ticks; + timer_ptr -> tx_timer_internal.tx_timer_internal_re_initialize_ticks = reschedule_ticks; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return TX_SUCCESS. */ + return(TX_SUCCESS); +} + diff --git a/common_smp/src/tx_timer_create.c b/common_smp/src/tx_timer_create.c new file mode 100644 index 00000000..97b2b2e5 --- /dev/null +++ b/common_smp/src/tx_timer_create.c @@ -0,0 +1,174 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_timer.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_create PORTABLE SMP */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates an application timer from the specified */ +/* input. */ +/* */ +/* INPUT */ +/* */ +/* timer_ptr Pointer to timer control block */ +/* name_ptr Pointer to timer name */ +/* expiration_function Application expiration function */ +/* initial_ticks Initial expiration ticks */ +/* reschedule_ticks Reschedule ticks */ +/* auto_activate Automatic activation flag */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SUCCESS Successful completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_system_activate Timer activation function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_timer_create(TX_TIMER *timer_ptr, CHAR *name_ptr, + VOID (*expiration_function)(ULONG id), ULONG expiration_input, + ULONG initial_ticks, ULONG reschedule_ticks, UINT auto_activate) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_TIMER *next_timer; +TX_TIMER *previous_timer; + + + /* Initialize timer control block to all zeros. */ + TX_MEMSET(timer_ptr, 0, (sizeof(TX_TIMER))); + + /* Setup the basic timer fields. */ + timer_ptr -> tx_timer_name = name_ptr; + timer_ptr -> tx_timer_internal.tx_timer_internal_remaining_ticks = initial_ticks; + timer_ptr -> tx_timer_internal.tx_timer_internal_re_initialize_ticks = reschedule_ticks; + timer_ptr -> tx_timer_internal.tx_timer_internal_timeout_function = expiration_function; + timer_ptr -> tx_timer_internal.tx_timer_internal_timeout_param = expiration_input; + +#ifdef TX_THREAD_SMP_ONLY_CORE_0_DEFAULT + + /* Default the timers to run on core 0. */ + timer_ptr -> tx_timer_internal.tx_timer_internal_smp_cores_excluded = (TX_THREAD_SMP_CORE_MASK & 0xFFFFFFFE); +#endif + + /* Disable interrupts to put the timer on the created list. */ + TX_DISABLE + + /* Setup the timer ID to make it valid. */ + timer_ptr -> tx_timer_id = TX_TIMER_ID; + + /* Place the timer on the list of created application timers. First, + check for an empty list. */ + if (_tx_timer_created_count == TX_EMPTY) + { + + /* The created timer list is empty. Add timer to empty list. */ + _tx_timer_created_ptr = timer_ptr; + timer_ptr -> tx_timer_created_next = timer_ptr; + timer_ptr -> tx_timer_created_previous = timer_ptr; + } + else + { + + /* This list is not NULL, add to the end of the list. */ + next_timer = _tx_timer_created_ptr; + previous_timer = next_timer -> tx_timer_created_previous; + + /* Place the new timer in the list. */ + next_timer -> tx_timer_created_previous = timer_ptr; + previous_timer -> tx_timer_created_next = timer_ptr; + + /* Setup this timer's created links. */ + timer_ptr -> tx_timer_created_previous = previous_timer; + timer_ptr -> tx_timer_created_next = next_timer; + } + + /* Increment the number of created timers. */ + _tx_timer_created_count++; + + /* Optional timer create extended processing. */ + TX_TIMER_CREATE_EXTENSION(timer_ptr) + + /* If trace is enabled, register this object. */ + TX_TRACE_OBJECT_REGISTER(TX_TRACE_OBJECT_TYPE_TIMER, timer_ptr, name_ptr, initial_ticks, reschedule_ticks) + + /* If trace is enabled, insert this call in the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_TIMER_CREATE, timer_ptr, initial_ticks, reschedule_ticks, auto_activate, TX_TRACE_TIMER_EVENTS) + + /* Log this kernel call. */ + TX_EL_TIMER_CREATE_INSERT + + /* Determine if this timer needs to be activated. */ + if (auto_activate == TX_AUTO_ACTIVATE) + { + +#ifdef TX_TIMER_ENABLE_PERFORMANCE_INFO + + /* Increment the total activations counter. */ + _tx_timer_performance_activate_count++; + + /* Increment the number of activations on this timer. */ + timer_ptr -> tx_timer_performance_activate_count++; +#endif + + /* Call actual activation function. */ + _tx_timer_system_activate(&(timer_ptr -> tx_timer_internal)); + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return TX_SUCCESS. */ + return(TX_SUCCESS); +} + diff --git a/common_smp/src/tx_timer_deactivate.c b/common_smp/src/tx_timer_deactivate.c new file mode 100644 index 00000000..d48798ef --- /dev/null +++ b/common_smp/src/tx_timer_deactivate.c @@ -0,0 +1,250 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_timer.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_deactivate PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function deactivates the specified application timer. */ +/* */ +/* INPUT */ +/* */ +/* timer_ptr Pointer to timer control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SUCCESS Always returns success */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_timer_deactivate(TX_TIMER *timer_ptr) +{ +TX_INTERRUPT_SAVE_AREA + +TX_TIMER_INTERNAL *internal_ptr; +TX_TIMER_INTERNAL **list_head; +TX_TIMER_INTERNAL *next_timer; +TX_TIMER_INTERNAL *previous_timer; +ULONG ticks_left; +UINT active_timer_list; + + + /* Setup internal timer pointer. */ + internal_ptr = &(timer_ptr -> tx_timer_internal); + + /* Disable interrupts while the remaining time before expiration is + calculated. */ + TX_DISABLE + +#ifdef TX_TIMER_ENABLE_PERFORMANCE_INFO + + /* Increment the total deactivations counter. */ + _tx_timer_performance_deactivate_count++; + + /* Increment the number of deactivations on this timer. */ + timer_ptr -> tx_timer_performance_deactivate_count++; +#endif + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_TIMER_DEACTIVATE, timer_ptr, TX_POINTER_TO_ULONG_CONVERT(&ticks_left), 0, 0, TX_TRACE_TIMER_EVENTS) + + /* Log this kernel call. */ + TX_EL_TIMER_DEACTIVATE_INSERT + + /* Pickup the list head. */ + list_head = internal_ptr -> tx_timer_internal_list_head; + + /* Is the timer active? */ + if (list_head != TX_NULL) + { + + /* Default the active timer list flag to false. */ + active_timer_list = TX_FALSE; + + /* Determine if the head pointer is within the timer expiration list. */ + if (TX_TIMER_INDIRECT_TO_VOID_POINTER_CONVERT(list_head) >= TX_TIMER_INDIRECT_TO_VOID_POINTER_CONVERT(_tx_timer_list_start)) + { + + /* Now check to make sure the list head is before the end of the list. */ + if (TX_TIMER_INDIRECT_TO_VOID_POINTER_CONVERT(list_head) < TX_TIMER_INDIRECT_TO_VOID_POINTER_CONVERT(_tx_timer_list_end)) + { + + /* Set the active timer list flag to true. */ + active_timer_list = TX_TRUE; + } + } + + /* Determine if the timer is on active timer list. */ + if (active_timer_list == TX_TRUE) + { + + /* This timer is active and has not yet expired. */ + + /* Calculate the amount of time that has elapsed since the timer + was activated. */ + + /* Is this timer's entry after the current timer pointer? */ + if (TX_TIMER_INDIRECT_TO_VOID_POINTER_CONVERT(list_head) >= TX_TIMER_INDIRECT_TO_VOID_POINTER_CONVERT(_tx_timer_current_ptr)) + { + + /* Calculate ticks left to expiration - just the difference between this + timer's entry and the current timer pointer. */ + ticks_left = (ULONG) (TX_TIMER_POINTER_DIF(list_head,_tx_timer_current_ptr)) + ((ULONG) 1); + } + else + { + + /* Calculate the ticks left with a wrapped list condition. */ + ticks_left = (ULONG) (TX_TIMER_POINTER_DIF(list_head,_tx_timer_list_start)); + + ticks_left = ticks_left + (ULONG) ((TX_TIMER_POINTER_DIF(_tx_timer_list_end, _tx_timer_current_ptr)) + ((ULONG) 1)); + } + + /* Adjust the remaining ticks accordingly. */ + if (internal_ptr -> tx_timer_internal_remaining_ticks > TX_TIMER_ENTRIES) + { + + /* Subtract off the last full pass through the timer list and add the + time left. */ + internal_ptr -> tx_timer_internal_remaining_ticks = + (internal_ptr -> tx_timer_internal_remaining_ticks - TX_TIMER_ENTRIES) + ticks_left; + } + else + { + + /* Just put the ticks left into the timer's remaining ticks. */ + internal_ptr -> tx_timer_internal_remaining_ticks = ticks_left; + } + } + else + { + + /* Determine if this is timer has just expired. */ + if (_tx_timer_expired_timer_ptr != internal_ptr) + { + + /* No, it hasn't expired. Now check for remaining time greater than the list + size. */ + if (internal_ptr -> tx_timer_internal_remaining_ticks > TX_TIMER_ENTRIES) + { + + /* Adjust the remaining ticks. */ + internal_ptr -> tx_timer_internal_remaining_ticks = + internal_ptr -> tx_timer_internal_remaining_ticks - TX_TIMER_ENTRIES; + } + else + { + + /* Set the remaining time to the reactivation time. */ + internal_ptr -> tx_timer_internal_remaining_ticks = internal_ptr -> tx_timer_internal_re_initialize_ticks; + } + } + else + { + + /* Set the remaining time to the reactivation time. */ + internal_ptr -> tx_timer_internal_remaining_ticks = internal_ptr -> tx_timer_internal_re_initialize_ticks; + } + } + + /* Pickup the next timer. */ + next_timer = internal_ptr -> tx_timer_internal_active_next; + + /* See if this is the only timer in the list. */ + if (internal_ptr == next_timer) + { + + /* Yes, the only timer on the list. */ + + /* Determine if the head pointer needs to be updated. */ + if (*(list_head) == internal_ptr) + { + + /* Update the head pointer. */ + *(list_head) = TX_NULL; + } + } + else + { + + /* At least one more timer is on the same expiration list. */ + + /* Update the links of the adjacent timers. */ + previous_timer = internal_ptr -> tx_timer_internal_active_previous; + next_timer -> tx_timer_internal_active_previous = previous_timer; + previous_timer -> tx_timer_internal_active_next = next_timer; + + /* Determine if the head pointer needs to be updated. */ + if (*(list_head) == internal_ptr) + { + + /* Update the next timer in the list with the list head + pointer. */ + next_timer -> tx_timer_internal_list_head = list_head; + + /* Update the head pointer. */ + *(list_head) = next_timer; + } + } + + /* Clear the timer's list head pointer. */ + internal_ptr -> tx_timer_internal_list_head = TX_NULL; + } + + /* Restore interrupts to previous posture. */ + TX_RESTORE + + /* Return TX_SUCCESS. */ + return(TX_SUCCESS); +} + diff --git a/common_smp/src/tx_timer_delete.c b/common_smp/src/tx_timer_delete.c new file mode 100644 index 00000000..49074bc2 --- /dev/null +++ b/common_smp/src/tx_timer_delete.c @@ -0,0 +1,142 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_timer.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_delete PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function deletes the specified application timer. */ +/* */ +/* INPUT */ +/* */ +/* timer_ptr Pointer to timer control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SUCCESS Successful completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_system_deactivate Timer deactivation function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_timer_delete(TX_TIMER *timer_ptr) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_TIMER *next_timer; +TX_TIMER *previous_timer; + + + /* Disable interrupts to remove the timer from the created list. */ + TX_DISABLE + + /* Determine if the timer needs to be deactivated. */ + if (timer_ptr -> tx_timer_internal.tx_timer_internal_list_head != TX_NULL) + { + + /* Yes, deactivate the timer before it is deleted. */ + _tx_timer_system_deactivate(&(timer_ptr -> tx_timer_internal)); + } + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_TIMER_DELETE, timer_ptr, 0, 0, 0, TX_TRACE_TIMER_EVENTS) + + /* Optional timer delete extended processing. */ + TX_TIMER_DELETE_EXTENSION(timer_ptr) + + /* If trace is enabled, unregister this object. */ + TX_TRACE_OBJECT_UNREGISTER(timer_ptr) + + /* Log this kernel call. */ + TX_EL_TIMER_DELETE_INSERT + + /* Clear the timer ID to make it invalid. */ + timer_ptr -> tx_timer_id = TX_CLEAR_ID; + + /* Decrement the number of created timers. */ + _tx_timer_created_count--; + + /* See if the timer is the only one on the list. */ + if (_tx_timer_created_count == TX_EMPTY) + { + + /* Only created timer, just set the created list to NULL. */ + _tx_timer_created_ptr = TX_NULL; + } + else + { + + /* Link-up the neighbors. */ + next_timer = timer_ptr -> tx_timer_created_next; + previous_timer = timer_ptr -> tx_timer_created_previous; + next_timer -> tx_timer_created_previous = previous_timer; + previous_timer -> tx_timer_created_next = next_timer; + + /* See if we have to update the created list head pointer. */ + if (_tx_timer_created_ptr == timer_ptr) + { + + /* Yes, move the head pointer to the next link. */ + _tx_timer_created_ptr = next_timer; + } + } + + /* Execute Port-Specific completion processing. If needed, it is typically defined in tx_port.h. */ + TX_TIMER_DELETE_PORT_COMPLETION(timer_ptr) + + /* Restore interrupts. */ + TX_RESTORE + + /* Return TX_SUCCESS. */ + return(TX_SUCCESS); +} + diff --git a/common_smp/src/tx_timer_expiration_process.c b/common_smp/src/tx_timer_expiration_process.c new file mode 100644 index 00000000..998aa5e4 --- /dev/null +++ b/common_smp/src/tx_timer_expiration_process.c @@ -0,0 +1,477 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_timer.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_expiration_process PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes thread and application timer expirations. */ +/* It is called from the _tx_timer_interrupt handler and either */ +/* processes the timer expiration in the ISR or defers to the system */ +/* timer thread. The actual processing is determined during */ +/* compilation. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_system_resume Thread resume processing */ +/* _tx_thread_system_ni_resume Non-interruptable resume thread */ +/* _tx_timer_system_activate Timer reactivate processing */ +/* Timer Expiration Function */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_timer_interrupt Timer interrupt handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_timer_expiration_process(VOID) +{ + +TX_INTERRUPT_SAVE_AREA + +#ifdef TX_TIMER_PROCESS_IN_ISR + +TX_TIMER_INTERNAL *expired_timers; +TX_TIMER_INTERNAL *reactivate_timer; +TX_TIMER_INTERNAL *next_timer; +TX_TIMER_INTERNAL *previous_timer; +#ifdef TX_REACTIVATE_INLINE +TX_TIMER_INTERNAL **timer_list; /* Timer list pointer */ +UINT expiration_time; /* Value used for pointer offset*/ +ULONG delta; +#endif +TX_TIMER_INTERNAL *current_timer; +VOID (*timeout_function)(ULONG id); +ULONG timeout_param = ((ULONG) 0); +#ifdef TX_TIMER_ENABLE_PERFORMANCE_INFO +TX_TIMER *timer_ptr; +#endif +#endif + +#ifndef TX_TIMER_PROCESS_IN_ISR + + /* Don't process in the ISR, wakeup the system timer thread to process the + timer expiration. */ + + /* Disable interrupts. */ + TX_DISABLE + +#ifdef TX_NOT_INTERRUPTABLE + + /* Resume the thread! */ + _tx_thread_system_ni_resume(&_tx_timer_thread); + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Increment the preempt disable flag. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Call the system resume function to activate the timer thread. */ + _tx_thread_system_resume(&_tx_timer_thread); +#endif + +#else + + /* Process the timer expiration directly in the ISR. This increases the interrupt + processing, however, it eliminates the need for a system timer thread and associated + resources. */ + + /* Disable interrupts. */ + TX_DISABLE + + /* Determine if the timer processing is already active. This needs to be checked outside + of the processing loop because it remains set throughout nested timer interrupt conditions. */ + if (_tx_timer_processing_active == TX_FALSE) + { + + /* Timer processing is not nested. */ + + /* Determine if the timer expiration has already been cleared. */ + if (_tx_timer_expired != ((UINT) 0)) + { + + /* Proceed with timer processing. */ + + /* Set the timer interrupt processing active flag. */ + _tx_timer_processing_active = TX_TRUE; + + /* Now go into an infinite loop to process timer expirations. */ + do + { + + /* First, move the current list pointer and clear the timer + expired value. This allows the interrupt handling portion + to continue looking for timer expirations. */ + + /* Save the current timer expiration list pointer. */ + expired_timers = *_tx_timer_current_ptr; + + /* Modify the head pointer in the first timer in the list, if there + is one! */ + if (expired_timers != TX_NULL) + { + + expired_timers -> tx_timer_internal_list_head = &expired_timers; + } + + /* Set the current list pointer to NULL. */ + *_tx_timer_current_ptr = TX_NULL; + + /* Move the current pointer up one timer entry wrap if we get to + the end of the list. */ + _tx_timer_current_ptr = TX_TIMER_POINTER_ADD(_tx_timer_current_ptr, 1); + if (_tx_timer_current_ptr == _tx_timer_list_end) + { + + _tx_timer_current_ptr = _tx_timer_list_start; + } + + /* Clear the expired flag. */ + _tx_timer_expired = TX_FALSE; + + /* Restore interrupts temporarily. */ + TX_RESTORE + + /* Disable interrupts again. */ + TX_DISABLE + + /* Next, process the expiration of the associated timers at this + time slot. */ + while (expired_timers != TX_NULL) + { + + /* Something is on the list. Remove it and process the expiration. */ + current_timer = expired_timers; + + /* Pickup the next timer. */ + next_timer = expired_timers -> tx_timer_internal_active_next; + + /* Set the reactivate timer to NULL. */ + reactivate_timer = TX_NULL; + + /* Determine if this is the only timer. */ + if (current_timer == next_timer) + { + + /* Yes, this is the only timer in the list. */ + + /* Set the head pointer to NULL. */ + expired_timers = TX_NULL; + } + else + { + + /* No, not the only expired timer. */ + + /* Remove this timer from the expired list. */ + previous_timer = current_timer -> tx_timer_internal_active_previous; + next_timer -> tx_timer_internal_active_previous = previous_timer; + previous_timer -> tx_timer_internal_active_next = next_timer; + + /* Modify the next timer's list head to point at the current list head. */ + next_timer -> tx_timer_internal_list_head = &expired_timers; + + /* Set the list head pointer. */ + expired_timers = next_timer; + } + + /* In any case, the timer is now off of the expired list. */ + + /* Determine if the timer has expired or if it is just a really + big timer that needs to be placed in the list again. */ + if (current_timer -> tx_timer_internal_remaining_ticks > TX_TIMER_ENTRIES) + { + + /* Timer is bigger than the timer entries and must be + rescheduled. */ + +#ifdef TX_TIMER_ENABLE_PERFORMANCE_INFO + + /* Increment the total expiration adjustments counter. */ + _tx_timer_performance__expiration_adjust_count++; + + /* Determine if this is an application timer. */ + if (current_timer -> tx_timer_internal_timeout_function != &_tx_thread_timeout) + { + + /* Derive the application timer pointer. */ + + /* Pickup the application timer pointer. */ + TX_USER_TIMER_POINTER_GET(current_timer, timer_ptr) + + /* Increment the number of expiration adjustments on this timer. */ + if (timer_ptr -> tx_timer_id == TX_TIMER_ID) + { + + timer_ptr -> tx_timer_performance__expiration_adjust_count++; + } + } +#endif + + /* Decrement the remaining ticks of the timer. */ + current_timer -> tx_timer_internal_remaining_ticks = + current_timer -> tx_timer_internal_remaining_ticks - TX_TIMER_ENTRIES; + + /* Set the timeout function to NULL in order to bypass the + expiration. */ + timeout_function = TX_NULL; + + /* Make the timer appear that it is still active while interrupts + are enabled. This will permit proper processing of a timer + deactivate from an ISR. */ + current_timer -> tx_timer_internal_list_head = &reactivate_timer; + current_timer -> tx_timer_internal_active_next = current_timer; + + /* Setup the temporary timer list head pointer. */ + reactivate_timer = current_timer; + } + else + { + + /* Timer did expire. */ + +#ifdef TX_TIMER_ENABLE_PERFORMANCE_INFO + + /* Increment the total expirations counter. */ + _tx_timer_performance_expiration_count++; + + /* Determine if this is an application timer. */ + if (current_timer -> tx_timer_internal_timeout_function != &_tx_thread_timeout) + { + + /* Derive the application timer pointer. */ + + /* Pickup the application timer pointer. */ + TX_USER_TIMER_POINTER_GET(current_timer, timer_ptr) + + /* Increment the number of expirations on this timer. */ + if (timer_ptr -> tx_timer_id == TX_TIMER_ID) + { + + timer_ptr -> tx_timer_performance_expiration_count++; + } + } +#endif + + /* Copy the calling function and ID into local variables before interrupts + are re-enabled. */ + timeout_function = current_timer -> tx_timer_internal_timeout_function; + timeout_param = current_timer -> tx_timer_internal_timeout_param; + + /* Copy the reinitialize ticks into the remaining ticks. */ + current_timer -> tx_timer_internal_remaining_ticks = current_timer -> tx_timer_internal_re_initialize_ticks; + + /* Determine if the timer should be reactivated. */ + if (current_timer -> tx_timer_internal_remaining_ticks != ((ULONG) 0)) + { + + /* Make the timer appear that it is still active while processing + the expiration routine and with interrupts enabled. This will + permit proper processing of a timer deactivate from both the + expiration routine and an ISR. */ + current_timer -> tx_timer_internal_list_head = &reactivate_timer; + current_timer -> tx_timer_internal_active_next = current_timer; + + /* Setup the temporary timer list head pointer. */ + reactivate_timer = current_timer; + } + else + { + + /* Set the list pointer of this timer to NULL. This is used to indicate + the timer is no longer active. */ + current_timer -> tx_timer_internal_list_head = TX_NULL; + } + } + + /* Set pointer to indicate the expired timer that is currently being processed. */ + _tx_timer_expired_timer_ptr = current_timer; + + /* Restore interrupts for timer expiration call. */ + TX_RESTORE + + /* Call the timer-expiration function, if non-NULL. */ + if (timeout_function != TX_NULL) + { + + (timeout_function) (timeout_param); + } + + /* Lockout interrupts again. */ + TX_DISABLE + + /* Clear expired timer pointer. */ + _tx_timer_expired_timer_ptr = TX_NULL; + + /* Determine if the timer needs to be reactivated. */ + if (reactivate_timer == current_timer) + { + + /* Reactivate the timer. */ + +#ifdef TX_TIMER_ENABLE_PERFORMANCE_INFO + + /* Determine if this timer expired. */ + if (timeout_function != TX_NULL) + { + + /* Increment the total reactivations counter. */ + _tx_timer_performance_reactivate_count++; + + /* Determine if this is an application timer. */ + if (current_timer -> tx_timer_internal_timeout_function != &_tx_thread_timeout) + { + + /* Derive the application timer pointer. */ + + /* Pickup the application timer pointer. */ + TX_USER_TIMER_POINTER_GET(current_timer, timer_ptr) + + /* Increment the number of expirations on this timer. */ + if (timer_ptr -> tx_timer_id == TX_TIMER_ID) + { + + timer_ptr -> tx_timer_performance_reactivate_count++; + } + } + } +#endif + + +#ifdef TX_REACTIVATE_INLINE + + /* Calculate the amount of time remaining for the timer. */ + if (current_timer -> tx_timer_internal_remaining_ticks > TX_TIMER_ENTRIES) + { + + /* Set expiration time to the maximum number of entries. */ + expiration_time = TX_TIMER_ENTRIES - ((UINT) 1); + } + else + { + + /* Timer value fits in the timer entries. */ + + /* Set the expiration time. */ + expiration_time = ((UINT) current_timer -> tx_timer_internal_remaining_ticks) - ((UINT) 1); + } + + /* At this point, we are ready to put the timer back on one of + the timer lists. */ + + /* Calculate the proper place for the timer. */ + timer_list = TX_TIMER_POINTER_ADD(_tx_timer_current_ptr, expiration_time); + if (TX_TIMER_INDIRECT_TO_VOID_POINTER_CONVERT(timer_list) >= TX_TIMER_INDIRECT_TO_VOID_POINTER_CONVERT(_tx_timer_list_end)) + { + + /* Wrap from the beginning of the list. */ + delta = TX_TIMER_POINTER_DIF(timer_list, _tx_timer_list_end); + timer_list = TX_TIMER_POINTER_ADD(_tx_timer_list_start, delta); + } + + /* Now put the timer on this list. */ + if ((*timer_list) == TX_NULL) + { + + /* This list is NULL, just put the new timer on it. */ + + /* Setup the links in this timer. */ + current_timer -> tx_timer_internal_active_next = current_timer; + current_timer -> tx_timer_internal_active_previous = current_timer; + + /* Setup the list head pointer. */ + *timer_list = current_timer; + } + else + { + + /* This list is not NULL, add current timer to the end. */ + next_timer = *timer_list; + previous_timer = next_timer -> tx_timer_internal_active_previous; + previous_timer -> tx_timer_internal_active_next = current_timer; + next_timer -> tx_timer_internal_active_previous = current_timer; + current_timer -> tx_timer_internal_active_next = next_timer; + current_timer -> tx_timer_internal_active_previous = previous_timer; + } + + /* Setup list head pointer. */ + current_timer -> tx_timer_internal_list_head = timer_list; +#else + + /* Reactivate through the timer activate function. */ + + /* Clear the list head for the timer activate call. */ + current_timer -> tx_timer_internal_list_head = TX_NULL; + + /* Activate the current timer. */ + _tx_timer_system_activate(current_timer); +#endif + } + } + } while (_tx_timer_expired != TX_FALSE); + + /* Clear the timer interrupt processing active flag. */ + _tx_timer_processing_active = TX_FALSE; + } + } + + /* Restore interrupts. */ + TX_RESTORE +#endif +} + diff --git a/common_smp/src/tx_timer_info_get.c b/common_smp/src/tx_timer_info_get.c new file mode 100644 index 00000000..4a6457cb --- /dev/null +++ b/common_smp/src/tx_timer_info_get.c @@ -0,0 +1,248 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_timer.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves information from the specified timer. */ +/* */ +/* INPUT */ +/* */ +/* timer_ptr Pointer to timer control block */ +/* name Destination for the timer name */ +/* active Destination for active flag */ +/* remaining_ticks Destination for remaining ticks */ +/* before expiration */ +/* reschedule_ticks Destination for reschedule ticks */ +/* next_timer Destination for next timer on the */ +/* created list */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_timer_info_get(TX_TIMER *timer_ptr, CHAR **name, UINT *active, ULONG *remaining_ticks, + ULONG *reschedule_ticks, TX_TIMER **next_timer) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_TIMER_INTERNAL *internal_ptr; +TX_TIMER_INTERNAL **list_head; +ULONG ticks_left; +UINT timer_active; +UINT active_timer_list; + + + /* Disable interrupts. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_TIMER_INFO_GET, timer_ptr, TX_POINTER_TO_ULONG_CONVERT(&ticks_left), 0, 0, TX_TRACE_TIMER_EVENTS) + + /* Log this kernel call. */ + TX_EL_TIMER_INFO_GET_INSERT + + /* Retrieve the name of the timer. */ + if (name != TX_NULL) + { + + *name = timer_ptr -> tx_timer_name; + } + + /* Pickup address of internal timer structure. */ + internal_ptr = &(timer_ptr -> tx_timer_internal); + + /* Retrieve all the pertinent information and return it in the supplied + destinations. */ + + /* Default active to false. */ + timer_active = TX_FALSE; + + /* Default the ticks left to the remaining ticks. */ + ticks_left = internal_ptr -> tx_timer_internal_remaining_ticks; + + /* Determine if the timer is still active. */ + if (internal_ptr -> tx_timer_internal_list_head != TX_NULL) + { + + /* Indicate this timer is active. */ + timer_active = TX_TRUE; + + /* Default the active timer list flag to false. */ + active_timer_list = TX_FALSE; + + /* Determine if the timer is still active. */ + if (internal_ptr -> tx_timer_internal_list_head >= _tx_timer_list_start) + { + + /* Determine if the list head is before the end of the list. */ + if (internal_ptr -> tx_timer_internal_list_head < _tx_timer_list_end) + { + + /* This timer is active and has not yet expired. */ + active_timer_list = TX_TRUE; + } + } + + /* Determine if the timer is on the active timer list. */ + if (active_timer_list == TX_TRUE) + { + + /* Calculate the amount of time that has elapsed since the timer + was activated. */ + + /* Setup the list head pointer. */ + list_head = internal_ptr -> tx_timer_internal_list_head; + + /* Is this timer's entry after the current timer pointer? */ + if (internal_ptr -> tx_timer_internal_list_head >= _tx_timer_current_ptr) + { + + /* Calculate ticks left to expiration - just the difference between this + timer's entry and the current timer pointer. */ + ticks_left = ((TX_TIMER_POINTER_DIF(list_head, _tx_timer_current_ptr)) + ((ULONG) 1)); + } + else + { + + /* Calculate the ticks left with a wrapped list condition. */ + ticks_left = ((TX_TIMER_POINTER_DIF(list_head, _tx_timer_list_start))); + + ticks_left = ticks_left + ((TX_TIMER_POINTER_DIF(_tx_timer_list_end, _tx_timer_current_ptr)) + ((ULONG) 1)); + } + + /* Adjust the remaining ticks accordingly. */ + if (internal_ptr -> tx_timer_internal_remaining_ticks > TX_TIMER_ENTRIES) + { + + /* Subtract off the last full pass through the timer list and add the + time left. */ + ticks_left = (internal_ptr -> tx_timer_internal_remaining_ticks - TX_TIMER_ENTRIES) + ticks_left; + } + + } + else + { + + /* The timer is not on the actual timer list so it must either be being processed + or on a temporary list to be processed. */ + + /* Check to see if this timer is the timer currently being processed. */ + if (_tx_timer_expired_timer_ptr == internal_ptr) + { + + /* Timer dispatch routine is executing, waiting to execute, or just finishing. No more remaining ticks for this expiration. */ + ticks_left = ((ULONG) 0); + } + else + { + + /* Timer is not the one being processed, which means it must be on the temporary expiration list + waiting to be processed. */ + + /* Calculate the remaining ticks for a timer in the process of expiring. */ + if (ticks_left > TX_TIMER_ENTRIES) + { + + /* Calculate the number of ticks remaining. */ + ticks_left = internal_ptr -> tx_timer_internal_remaining_ticks - TX_TIMER_ENTRIES; + } + else + { + + /* Timer dispatch routine is waiting to execute, no more remaining ticks for this expiration. */ + ticks_left = ((ULONG) 0); + } + } + } + } + + /* Setup return values for an inactive timer. */ + if (active != TX_NULL) + { + + /* Setup the timer active indication. */ + *active = timer_active; + } + if (remaining_ticks != TX_NULL) + { + + /* Setup the default remaining ticks value. */ + *remaining_ticks = ticks_left; + } + + /* Pickup the reschedule ticks value. */ + if (reschedule_ticks != TX_NULL) + { + + *reschedule_ticks = internal_ptr -> tx_timer_internal_re_initialize_ticks; + } + + /* Pickup the next created application timer. */ + if (next_timer != TX_NULL) + { + + *next_timer = timer_ptr -> tx_timer_created_next; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return completion status. */ + return(TX_SUCCESS); +} + diff --git a/common_smp/src/tx_timer_initialize.c b/common_smp/src/tx_timer_initialize.c new file mode 100644 index 00000000..5872b744 --- /dev/null +++ b/common_smp/src/tx_timer_initialize.c @@ -0,0 +1,303 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" + + +/* Check for the TX_NO_TIMER option. When defined, do not define all of the + timer component global variables. */ + +#ifndef TX_NO_TIMER + + +/* Define the system clock value that is continually incremented by the + periodic timer interrupt processing. */ + +volatile ULONG _tx_timer_system_clock; + + +/* Define count to detect when timer interrupt is active. */ + +ULONG _tx_timer_interrupt_active; + + +/* Define the time-slice expiration flag. This is used to indicate that a time-slice + has happened. */ + +UINT _tx_timer_expired_time_slice; + + +/* Define the thread and application timer entry list. This list provides a direct access + method for insertion of times less than TX_TIMER_ENTRIES. */ + +TX_TIMER_INTERNAL *_tx_timer_list[TX_TIMER_ENTRIES]; + + +/* Define the boundary pointers to the list. These are setup to easily manage + wrapping the list. */ + +TX_TIMER_INTERNAL **_tx_timer_list_start; +TX_TIMER_INTERNAL **_tx_timer_list_end; + + +/* Define the current timer pointer in the list. This pointer is moved sequentially + through the timer list by the timer interrupt handler. */ + +TX_TIMER_INTERNAL **_tx_timer_current_ptr; + + +/* Define the timer expiration flag. This is used to indicate that a timer + has expired. */ + +UINT _tx_timer_expired; + + +/* Define the created timer list head pointer. */ + +TX_TIMER *_tx_timer_created_ptr; + + +/* Define the created timer count. */ + +ULONG _tx_timer_created_count; + + +/* Define the pointer to the timer that has expired and is being processed. */ + +TX_TIMER_INTERNAL *_tx_timer_expired_timer_ptr; + + +#ifndef TX_TIMER_PROCESS_IN_ISR + +/* Define the timer thread's control block. */ + +TX_THREAD _tx_timer_thread; + + +/* Define the variable that holds the timer thread's starting stack address. */ + +VOID *_tx_timer_stack_start; + + +/* Define the variable that holds the timer thread's stack size. */ + +ULONG _tx_timer_stack_size; + + +/* Define the variable that holds the timer thread's priority. */ + +UINT _tx_timer_priority; + +/* Define the system timer thread's stack. The default size is defined + in tx_port.h. */ + +ULONG _tx_timer_thread_stack_area[(((UINT) TX_TIMER_THREAD_STACK_SIZE)+((sizeof(ULONG)) - ((UINT) 1)))/sizeof(ULONG)]; + +#else + + +/* Define the busy flag that will prevent nested timer ISR processing. */ + +UINT _tx_timer_processing_active; + +#endif + +#ifdef TX_TIMER_ENABLE_PERFORMANCE_INFO + +/* Define the total number of timer activations. */ + +ULONG _tx_timer_performance_activate_count; + + +/* Define the total number of timer reactivations. */ + +ULONG _tx_timer_performance_reactivate_count; + + +/* Define the total number of timer deactivations. */ + +ULONG _tx_timer_performance_deactivate_count; + + +/* Define the total number of timer expirations. */ + +ULONG _tx_timer_performance_expiration_count; + + +/* Define the total number of timer expiration adjustments. These are required + if the expiration time is greater than the size of the timer list. In such + cases, the timer is placed at the end of the list and then reactivated + as many times as necessary to finally achieve the resulting timeout. */ + +ULONG _tx_timer_performance__expiration_adjust_count; + +#endif +#endif + + +/* Define the current time slice value. If non-zero, a time-slice is active. + Otherwise, the time_slice is not active. There is one of these entries + per core. */ + +ULONG _tx_timer_time_slice[TX_THREAD_SMP_MAX_CORES]; + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_initialize PORTABLE SMP */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes the various control data structures for */ +/* the clock control component. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_create Create the system timer thread */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_high_level High level initialization */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_timer_initialize(VOID) +{ +#ifndef TX_NO_TIMER +#ifndef TX_TIMER_PROCESS_IN_ISR +UINT status; +#endif + +#ifndef TX_DISABLE_REDUNDANT_CLEARING + + + /* Initialize the system clock to 0. */ + _tx_timer_system_clock = ((ULONG) 0); + + /* Initialize timer interrupt active count. */ + _tx_timer_interrupt_active = ((ULONG) 0); + + /* Initialize the time-slice array to 0 to make sure everything is disabled. */ + TX_MEMSET(&_tx_timer_time_slice[0], 0, (sizeof(_tx_timer_time_slice))); + + /* Clear the expired flags. */ + _tx_timer_expired_time_slice = TX_FALSE; + _tx_timer_expired = TX_FALSE; + + /* Set the currently expired timer being processed pointer to NULL. */ + _tx_timer_expired_timer_ptr = TX_NULL; + + /* Initialize the thread and application timer management control structures. */ + + /* First, initialize the timer list. */ + TX_MEMSET(&_tx_timer_list[0], 0, sizeof(_tx_timer_list)); +#endif + + /* Initialize all of the list pointers. */ + _tx_timer_list_start = &_tx_timer_list[0]; + _tx_timer_current_ptr = &_tx_timer_list[0]; + + /* Set the timer list end pointer to one past the actual timer list. This is done + to make the timer interrupt handling in assembly language a little easier. */ + _tx_timer_list_end = &_tx_timer_list[TX_TIMER_ENTRIES-((ULONG) 1)]; + _tx_timer_list_end = TX_TIMER_POINTER_ADD(_tx_timer_list_end, ((ULONG) 1)); + +#ifndef TX_TIMER_PROCESS_IN_ISR + + /* Setup the variables associated with the system timer thread's stack and + priority. */ + _tx_timer_stack_start = (VOID *) &_tx_timer_thread_stack_area[0]; + _tx_timer_stack_size = ((ULONG) TX_TIMER_THREAD_STACK_SIZE); + _tx_timer_priority = ((UINT) TX_TIMER_THREAD_PRIORITY); + + /* Create the system timer thread. This thread processes all of the timer + expirations and reschedules. Its stack and priority are defined in the + low-level initialization component. */ + do + { + + /* Create the system timer thread. */ + status = _tx_thread_create(&_tx_timer_thread, + TX_CONST_CHAR_TO_CHAR_POINTER_CONVERT("System Timer Thread"), + _tx_timer_thread_entry, + (ULONG) TX_TIMER_ID, _tx_timer_stack_start, _tx_timer_stack_size, + _tx_timer_priority, _tx_timer_priority, TX_NO_TIME_SLICE, TX_DONT_START); + + /* Define timer initialize extension. */ + TX_TIMER_INITIALIZE_EXTENSION(status) + + } while (status != TX_SUCCESS); + +#else + + /* Clear the timer interrupt processing active flag. */ + _tx_timer_processing_active = TX_FALSE; +#endif + +#ifndef TX_DISABLE_REDUNDANT_CLEARING + + /* Initialize the head pointer of the created application timer list. */ + _tx_timer_created_ptr = TX_NULL; + + /* Set the created count to zero. */ + _tx_timer_created_count = TX_EMPTY; + +#ifdef TX_TIMER_ENABLE_PERFORMANCE_INFO + + /* Initialize timer performance counters. */ + _tx_timer_performance_activate_count = ((ULONG) 0); + _tx_timer_performance_reactivate_count = ((ULONG) 0); + _tx_timer_performance_deactivate_count = ((ULONG) 0); + _tx_timer_performance_expiration_count = ((ULONG) 0); + _tx_timer_performance__expiration_adjust_count = ((ULONG) 0); +#endif +#endif +#endif +} + diff --git a/common_smp/src/tx_timer_performance_info_get.c b/common_smp/src/tx_timer_performance_info_get.c new file mode 100644 index 00000000..cd0ac3db --- /dev/null +++ b/common_smp/src/tx_timer_performance_info_get.c @@ -0,0 +1,214 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_timer.h" +#ifdef TX_TIMER_ENABLE_PERFORMANCE_INFO +#include "tx_trace.h" +#endif + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_performance_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves performance information from the specified */ +/* timer. */ +/* */ +/* INPUT */ +/* */ +/* timer_ptr Pointer to timer control block */ +/* activates Destination for the number of */ +/* activations of this timer */ +/* reactivates Destination for the number of */ +/* reactivations of this timer */ +/* deactivates Destination for the number of */ +/* deactivations of this timer */ +/* expirations Destination for the number of */ +/* expirations of this timer */ +/* expiration_adjusts Destination for the number of */ +/* expiration adjustments of this */ +/* timer */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_timer_performance_info_get(TX_TIMER *timer_ptr, ULONG *activates, ULONG *reactivates, + ULONG *deactivates, ULONG *expirations, ULONG *expiration_adjusts) +{ + +#ifdef TX_TIMER_ENABLE_PERFORMANCE_INFO + +TX_INTERRUPT_SAVE_AREA +UINT status; + + + /* Determine if this is a legal request. */ + if (timer_ptr == TX_NULL) + { + + /* Timer pointer is illegal, return error. */ + status = TX_PTR_ERROR; + } + + /* Determine if the timer ID is invalid. */ + else if (timer_ptr -> tx_timer_id != TX_TIMER_ID) + { + + /* Timer pointer is illegal, return error. */ + status = TX_PTR_ERROR; + } + else + { + + /* Disable interrupts. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_TIMER_PERFORMANCE_INFO_GET, timer_ptr, 0, 0, 0, TX_TRACE_TIMER_EVENTS) + + /* Log this kernel call. */ + TX_EL_TIMER_PERFORMANCE_INFO_GET_INSERT + + /* Retrieve the number of activations of this timer. */ + if (activates != TX_NULL) + { + + *activates = timer_ptr -> tx_timer_performance_activate_count; + } + + /* Retrieve the number of reactivations of this timer. */ + if (reactivates != TX_NULL) + { + + *reactivates = timer_ptr -> tx_timer_performance_reactivate_count; + } + + /* Retrieve the number of deactivations of this timer. */ + if (deactivates != TX_NULL) + { + + *deactivates = timer_ptr -> tx_timer_performance_deactivate_count; + } + + /* Retrieve the number of expirations of this timer. */ + if (expirations != TX_NULL) + { + + *expirations = timer_ptr -> tx_timer_performance_expiration_count; + } + + /* Retrieve the number of expiration adjustments of this timer. */ + if (expiration_adjusts != TX_NULL) + { + + *expiration_adjusts = timer_ptr -> tx_timer_performance__expiration_adjust_count; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return successful completion. */ + status = TX_SUCCESS; + } +#else +UINT status; + + + /* Access input arguments just for the sake of lint, MISRA, etc. */ + if (timer_ptr != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (activates != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (reactivates != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (deactivates != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (expirations != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (expiration_adjusts != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } +#endif + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/tx_timer_performance_system_info_get.c b/common_smp/src/tx_timer_performance_system_info_get.c new file mode 100644 index 00000000..80e23529 --- /dev/null +++ b/common_smp/src/tx_timer_performance_system_info_get.c @@ -0,0 +1,187 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_timer.h" +#ifdef TX_TIMER_ENABLE_PERFORMANCE_INFO +#include "tx_trace.h" +#endif + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_performance_system_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function retrieves timer performance information. */ +/* */ +/* INPUT */ +/* */ +/* activates Destination for total number of */ +/* activations */ +/* reactivates Destination for total number of */ +/* reactivations */ +/* deactivates Destination for total number of */ +/* deactivations */ +/* expirations Destination for total number of */ +/* expirations */ +/* expiration_adjusts Destination for total number of */ +/* expiration adjustments */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_timer_performance_system_info_get(ULONG *activates, ULONG *reactivates, + ULONG *deactivates, ULONG *expirations, ULONG *expiration_adjusts) +{ + +#ifdef TX_TIMER_ENABLE_PERFORMANCE_INFO + +TX_INTERRUPT_SAVE_AREA + + + /* Disable interrupts. */ + TX_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_TIMER_PERFORMANCE_SYSTEM_INFO_GET, 0, 0, 0, 0, TX_TRACE_TIMER_EVENTS) + + /* Log this kernel call. */ + TX_EL_TIMER_PERFORMANCE_SYSTEM_INFO_GET_INSERT + + /* Retrieve the total number of timer activations. */ + if (activates != TX_NULL) + { + + *activates = _tx_timer_performance_activate_count; + } + + /* Retrieve the total number of timer reactivations. */ + if (reactivates != TX_NULL) + { + + *reactivates = _tx_timer_performance_reactivate_count; + } + + /* Retrieve the total number of timer deactivations. */ + if (deactivates != TX_NULL) + { + + *deactivates = _tx_timer_performance_deactivate_count; + } + + /* Retrieve the total number of timer expirations. */ + if (expirations != TX_NULL) + { + + *expirations = _tx_timer_performance_expiration_count; + } + + /* Retrieve the total number of timer expiration adjustments. */ + if (expiration_adjusts != TX_NULL) + { + + *expiration_adjusts = _tx_timer_performance__expiration_adjust_count; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return completion status. */ + return(TX_SUCCESS); + +#else + +UINT status; + + + /* Access input arguments just for the sake of lint, MISRA, etc. */ + if (activates != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (reactivates != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (deactivates != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (expirations != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (expiration_adjusts != TX_NULL) + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else + { + + /* Not enabled, return error. */ + status = TX_FEATURE_NOT_ENABLED; + } + + /* Return completion status. */ + return(status); +#endif +} + diff --git a/common_smp/src/tx_timer_smp_core_exclude.c b/common_smp/src/tx_timer_smp_core_exclude.c new file mode 100644 index 00000000..01e59e2c --- /dev/null +++ b/common_smp/src/tx_timer_smp_core_exclude.c @@ -0,0 +1,120 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer - High Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_timer.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_smp_core_exclude PORTABLE SMP */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function allows the application to exclude one or more cores */ +/* from executing the specified timer. */ +/* */ +/* INPUT */ +/* */ +/* timer_ptr Pointer to the timer */ +/* exclusion_map Bit map of exclusion list, */ +/* where bit 0 set means that */ +/* this thread cannot run on */ +/* core0, etc. */ +/* */ +/* OUTPUT */ +/* */ +/* Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_timer_smp_core_exclude(TX_TIMER *timer_ptr, ULONG exclusion_map) +{ + +TX_INTERRUPT_SAVE_AREA + +UINT status; + + + /* First, make sure the timer pointer is valid. */ + if (timer_ptr == TX_NULL) + { + + /* Return pointer error. */ + status = TX_TIMER_ERROR; + } + + /* Check for valid ID. */ + else if (timer_ptr -> tx_timer_id != TX_TIMER_ID) + { + + /* Return pointer error. */ + status = TX_TIMER_ERROR; + } + else + { + + /* Disable interrupts. */ + TX_DISABLE + + /* Now store in the core exclusion information. */ + timer_ptr -> tx_timer_internal.tx_timer_internal_smp_cores_excluded = (timer_ptr -> tx_timer_internal.tx_timer_internal_smp_cores_excluded & ~(((ULONG) TX_THREAD_SMP_CORE_MASK))) | + (exclusion_map & ((ULONG) TX_THREAD_SMP_CORE_MASK)); + + /* Restore interrupts. */ + TX_RESTORE + + /* Return success. */ + status = TX_SUCCESS; + } + + /* Return success. */ + return(status); +} + diff --git a/common_smp/src/tx_timer_smp_core_exclude_get.c b/common_smp/src/tx_timer_smp_core_exclude_get.c new file mode 100644 index 00000000..31d7a288 --- /dev/null +++ b/common_smp/src/tx_timer_smp_core_exclude_get.c @@ -0,0 +1,116 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer - High Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_timer.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_smp_core_exclude_get PROTABLE SMP */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function returns the current exclusion list for the timer. */ +/* */ +/* INPUT */ +/* */ +/* timer_ptr Pointer to the timer */ +/* exclusion_map_ptr Destination for the current */ +/* exclusion list */ +/* */ +/* OUTPUT */ +/* */ +/* Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_timer_smp_core_exclude_get(TX_TIMER *timer_ptr, ULONG *exclusion_map_ptr) +{ + +UINT status; + + + /* First, make sure the timer pointer is valid. */ + if (timer_ptr == TX_NULL) + { + + /* Return pointer error. */ + status = TX_TIMER_ERROR; + } + + /* Check for valid ID. */ + else if (timer_ptr -> tx_timer_id != TX_TIMER_ID) + { + + /* Return pointer error. */ + status = TX_TIMER_ERROR; + } + + /* Is the destination pointer NULL? */ + else if (exclusion_map_ptr == TX_NULL) + { + + /* Return pointer error. */ + status = TX_PTR_ERROR; + } + else + { + + /* Save the current exclusion map in the destination. */ + *exclusion_map_ptr = (timer_ptr -> tx_timer_internal.tx_timer_internal_smp_cores_excluded) & ((ULONG) TX_THREAD_SMP_CORE_MASK); + + /* Set the status to success. */ + status = TX_SUCCESS; + } + + /* Return success. */ + return(status); +} + diff --git a/common_smp/src/tx_timer_system_activate.c b/common_smp/src/tx_timer_system_activate.c new file mode 100644 index 00000000..505257db --- /dev/null +++ b/common_smp/src/tx_timer_system_activate.c @@ -0,0 +1,164 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_timer.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_system_activate PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function places the specified internal timer in the proper */ +/* place in the timer expiration list. If the timer is already active */ +/* this function does nothing. */ +/* */ +/* INPUT */ +/* */ +/* timer_ptr Pointer to timer control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SUCCESS Always returns success */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_system_suspend Thread suspend function */ +/* _tx_thread_system_ni_suspend Non-interruptable suspend thread */ +/* _tx_timer_thread_entry Timer thread processing */ +/* _tx_timer_activate Application timer activate */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_timer_system_activate(TX_TIMER_INTERNAL *timer_ptr) +{ + +TX_TIMER_INTERNAL **timer_list; +TX_TIMER_INTERNAL *next_timer; +TX_TIMER_INTERNAL *previous_timer; +ULONG delta; +ULONG remaining_ticks; +ULONG expiration_time; + + + /* Pickup the remaining ticks. */ + remaining_ticks = timer_ptr -> tx_timer_internal_remaining_ticks; + + /* Determine if there is a timer to activate. */ + if (remaining_ticks != ((ULONG) 0)) + { + + /* Determine if the timer is set to wait forever. */ + if (remaining_ticks != TX_WAIT_FOREVER) + { + + /* Valid timer activate request. */ + + /* Determine if the timer still needs activation. */ + if (timer_ptr -> tx_timer_internal_list_head == TX_NULL) + { + + /* Activate the timer. */ + + /* Calculate the amount of time remaining for the timer. */ + if (remaining_ticks > TX_TIMER_ENTRIES) + { + + /* Set expiration time to the maximum number of entries. */ + expiration_time = TX_TIMER_ENTRIES - ((ULONG) 1); + } + else + { + + /* Timer value fits in the timer entries. */ + + /* Set the expiration time. */ + expiration_time = (remaining_ticks - ((ULONG) 1)); + } + + /* At this point, we are ready to put the timer on one of + the timer lists. */ + + /* Calculate the proper place for the timer. */ + timer_list = TX_TIMER_POINTER_ADD(_tx_timer_current_ptr, expiration_time); + if (TX_TIMER_INDIRECT_TO_VOID_POINTER_CONVERT(timer_list) >= TX_TIMER_INDIRECT_TO_VOID_POINTER_CONVERT(_tx_timer_list_end)) + { + + /* Wrap from the beginning of the list. */ + delta = TX_TIMER_POINTER_DIF(timer_list, _tx_timer_list_end); + timer_list = TX_TIMER_POINTER_ADD(_tx_timer_list_start, delta); + } + + /* Now put the timer on this list. */ + if ((*timer_list) == TX_NULL) + { + + /* This list is NULL, just put the new timer on it. */ + + /* Setup the links in this timer. */ + timer_ptr -> tx_timer_internal_active_next = timer_ptr; + timer_ptr -> tx_timer_internal_active_previous = timer_ptr; + + /* Setup the list head pointer. */ + *timer_list = timer_ptr; + } + else + { + + /* This list is not NULL, add current timer to the end. */ + next_timer = *timer_list; + previous_timer = next_timer -> tx_timer_internal_active_previous; + previous_timer -> tx_timer_internal_active_next = timer_ptr; + next_timer -> tx_timer_internal_active_previous = timer_ptr; + timer_ptr -> tx_timer_internal_active_next = next_timer; + timer_ptr -> tx_timer_internal_active_previous = previous_timer; + } + + /* Setup list head pointer. */ + timer_ptr -> tx_timer_internal_list_head = timer_list; + } + } + } +} + diff --git a/common_smp/src/tx_timer_system_deactivate.c b/common_smp/src/tx_timer_system_deactivate.c new file mode 100644 index 00000000..72cf3045 --- /dev/null +++ b/common_smp/src/tx_timer_system_deactivate.c @@ -0,0 +1,132 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_timer.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_system_deactivate PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function deactivates, or removes the timer from the active */ +/* timer expiration list. If the timer is already deactivated, this */ +/* function just returns. */ +/* */ +/* INPUT */ +/* */ +/* timer_ptr Pointer to timer control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SUCCESS Always returns success */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_system_resume Thread resume function */ +/* _tx_timer_thread_entry Timer thread processing */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_timer_system_deactivate(TX_TIMER_INTERNAL *timer_ptr) +{ + +TX_TIMER_INTERNAL **list_head; +TX_TIMER_INTERNAL *next_timer; +TX_TIMER_INTERNAL *previous_timer; + + + /* Pickup the list head pointer. */ + list_head = timer_ptr -> tx_timer_internal_list_head; + + /* Determine if the timer still needs deactivation. */ + if (list_head != TX_NULL) + { + + /* Deactivate the timer. */ + + /* Pickup the next active timer. */ + next_timer = timer_ptr -> tx_timer_internal_active_next; + + /* See if this is the only timer in the list. */ + if (timer_ptr == next_timer) + { + + /* Yes, the only timer on the list. */ + + /* Determine if the head pointer needs to be updated. */ + if (*(list_head) == timer_ptr) + { + + /* Update the head pointer. */ + *(list_head) = TX_NULL; + } + } + else + { + + /* At least one more timer is on the same expiration list. */ + + /* Update the links of the adjacent timers. */ + previous_timer = timer_ptr -> tx_timer_internal_active_previous; + next_timer -> tx_timer_internal_active_previous = previous_timer; + previous_timer -> tx_timer_internal_active_next = next_timer; + + /* Determine if the head pointer needs to be updated. */ + if (*(list_head) == timer_ptr) + { + + /* Update the next timer in the list with the list head pointer. */ + next_timer -> tx_timer_internal_list_head = list_head; + + /* Update the head pointer. */ + *(list_head) = next_timer; + } + } + + /* Clear the timer's list head pointer. */ + timer_ptr -> tx_timer_internal_list_head = TX_NULL; + } +} + diff --git a/common_smp/src/tx_timer_thread_entry.c b/common_smp/src/tx_timer_thread_entry.c new file mode 100644 index 00000000..32c3f300 --- /dev/null +++ b/common_smp/src/tx_timer_thread_entry.c @@ -0,0 +1,547 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_timer.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_thread_entry PORTABLE SMP */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function manages thread and application timer expirations. */ +/* Actually, from this thread's point of view, there is no difference. */ +/* */ +/* INPUT */ +/* */ +/* timer_thread_input Used just for verification */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* Timer Expiration Function */ +/* _tx_thread_system_suspend Thread suspension */ +/* _tx_thread_system_ni_suspend Non-interruptable suspend thread */ +/* _tx_timer_system_activate Timer reactivate processing */ +/* _tx_thread_smp_core_exclude Exclude core from timer execution */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Scheduler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +#ifndef TX_TIMER_PROCESS_IN_ISR +VOID _tx_timer_thread_entry(ULONG timer_thread_input) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_TIMER_INTERNAL *expired_timers; +TX_TIMER_INTERNAL *reactivate_timer; +TX_TIMER_INTERNAL *next_timer; +TX_TIMER_INTERNAL *previous_timer; +TX_TIMER_INTERNAL *current_timer; +VOID (*timeout_function)(ULONG id); +ULONG timeout_param = ((ULONG) 0); +TX_THREAD *thread_ptr; +#ifdef TX_REACTIVATE_INLINE +TX_TIMER_INTERNAL **timer_list; /* Timer list pointer */ +UINT expiration_time; /* Value used for pointer offset*/ +ULONG delta; +#endif +#ifdef TX_TIMER_ENABLE_PERFORMANCE_INFO +UCHAR *working_ptr; +TX_TIMER *timer_ptr; +#endif +ULONG core_exclusion; +#ifdef TX_MISRA_ENABLE +UINT status; +#endif + + + /* Make sure the timer input is correct. This also gets rid of the + silly compiler warnings. */ + if (timer_thread_input == TX_TIMER_ID) + { + + /* Yes, valid thread entry, proceed... */ + + /* Now go into an infinite loop to process timer expirations. */ + while (TX_LOOP_FOREVER) + { + + /* First, move the current list pointer and clear the timer + expired value. This allows the interrupt handling portion + to continue looking for timer expirations. */ + TX_DISABLE + + /* Save the current timer expiration list pointer. */ + expired_timers = *_tx_timer_current_ptr; + + /* Modify the head pointer in the first timer in the list, if there + is one! */ + if (expired_timers != TX_NULL) + { + + expired_timers -> tx_timer_internal_list_head = &expired_timers; + + /* Pickup the current core exclusion bit map for this timer. */ + core_exclusion = expired_timers -> tx_timer_internal_smp_cores_excluded; + } + else + { + + /* Pickup the current core exclusion bit map for the timer thread. */ + core_exclusion = _tx_timer_thread.tx_thread_smp_cores_excluded; + } + + /* Set the current list pointer to NULL. */ + *_tx_timer_current_ptr = TX_NULL; + + /* Move the current pointer up one timer entry wrap if we get to + the end of the list. */ + _tx_timer_current_ptr = TX_TIMER_POINTER_ADD(_tx_timer_current_ptr, 1); + if (_tx_timer_current_ptr == _tx_timer_list_end) + { + + _tx_timer_current_ptr = _tx_timer_list_start; + } + + /* Clear the expired flag. */ + _tx_timer_expired = TX_FALSE; + + /* Restore interrupts temporarily. */ + TX_RESTORE + + /* Determine if we need to change the processor exclusion setting. */ + if ((_tx_timer_thread.tx_thread_smp_cores_excluded & ((ULONG) TX_THREAD_SMP_CORE_MASK)) != core_exclusion) + { + +#ifdef TX_MISRA_ENABLE + do + { + + /* Setup the new core exclusion for execution this timer. */ + status = _tx_thread_smp_core_exclude(&_tx_timer_thread, core_exclusion); + } while (status != TX_SUCCESS); +#else + /* Setup the new core exclusion for execution this timer. */ + _tx_thread_smp_core_exclude(&_tx_timer_thread, core_exclusion); +#endif + + /* When we get to this point, the system timer thread is executing on one of the allowed cores. */ + } + + /* Disable interrupts again. */ + TX_DISABLE + + /* Next, process the expiration of the associated timers at this + time slot. */ + while (expired_timers != TX_NULL) + { + + /* Something is on the list. Remove it and process the expiration. */ + current_timer = expired_timers; + + /* Pickup the next timer. */ + next_timer = expired_timers -> tx_timer_internal_active_next; + + /* Set the reactivate_timer to NULL. */ + reactivate_timer = TX_NULL; + + /* Determine if this is the only timer. */ + if (current_timer == next_timer) + { + + /* Yes, this is the only timer in the list. */ + + /* Set the head pointer to NULL. */ + expired_timers = TX_NULL; + + /* Pickup the excluded core(s) for the timer thread. */ + core_exclusion = _tx_timer_thread.tx_thread_smp_cores_excluded; + } + else + { + + /* No, not the only expired timer. */ + + /* Remove this timer from the expired list. */ + previous_timer = current_timer -> tx_timer_internal_active_previous; + next_timer -> tx_timer_internal_active_previous = previous_timer; + previous_timer -> tx_timer_internal_active_next = next_timer; + + /* Modify the next timer's list head to point at the current list head. */ + next_timer -> tx_timer_internal_list_head = &expired_timers; + + /* Set the list head pointer. */ + expired_timers = next_timer; + + /* Pickup the excluded core(s) for this timer. */ + core_exclusion = ((expired_timers -> tx_timer_internal_smp_cores_excluded) & ((ULONG) TX_THREAD_SMP_CORE_MASK)); + } + + /* In any case, the timer is now off of the expired list. */ + + /* Determine if the timer has expired or if it is just a really + big timer that needs to be placed in the list again. */ + if (current_timer -> tx_timer_internal_remaining_ticks > TX_TIMER_ENTRIES) + { + + /* Timer is bigger than the timer entries and must be + rescheduled. */ + +#ifdef TX_TIMER_ENABLE_PERFORMANCE_INFO + + /* Increment the total expiration adjustments counter. */ + _tx_timer_performance__expiration_adjust_count++; + + /* Determine if this is an application timer. */ + if (current_timer -> tx_timer_internal_timeout_function != &_tx_thread_timeout) + { + + /* Derive the application timer pointer. */ + + /* Pickup the application timer pointer. */ + TX_USER_TIMER_POINTER_GET(current_timer, timer_ptr) + + /* Increment the number of expiration adjustments on this timer. */ + if (timer_ptr -> tx_timer_id == TX_TIMER_ID) + { + + timer_ptr -> tx_timer_performance__expiration_adjust_count++; + } + } +#endif + + /* Decrement the remaining ticks of the timer. */ + current_timer -> tx_timer_internal_remaining_ticks = + current_timer -> tx_timer_internal_remaining_ticks - TX_TIMER_ENTRIES; + + /* Set the timeout function to NULL in order to bypass the + expiration. */ + timeout_function = TX_NULL; + + /* Make the timer appear that it is still active while interrupts + are enabled. This will permit proper processing of a timer + deactivate from an ISR. */ + current_timer -> tx_timer_internal_list_head = &reactivate_timer; + current_timer -> tx_timer_internal_active_next = current_timer; + + /* Setup the temporary timer list head pointer. */ + reactivate_timer = current_timer; + } + else + { + + /* Timer did expire. */ + +#ifdef TX_TIMER_ENABLE_PERFORMANCE_INFO + + /* Increment the total expirations counter. */ + _tx_timer_performance_expiration_count++; + + /* Determine if this is an application timer. */ + if (current_timer -> tx_timer_internal_timeout_function != &_tx_thread_timeout) + { + + /* Derive the application timer pointer. */ + + /* Pickup the application timer pointer. */ + TX_USER_TIMER_POINTER_GET(current_timer, timer_ptr) + + /* Increment the number of expirations on this timer. */ + if (timer_ptr -> tx_timer_id == TX_TIMER_ID) + { + + timer_ptr -> tx_timer_performance_expiration_count++; + } + } +#endif + + /* Copy the calling function and ID into local variables before interrupts + are re-enabled. */ + timeout_function = current_timer -> tx_timer_internal_timeout_function; + timeout_param = current_timer -> tx_timer_internal_timeout_param; + + /* Copy the reinitialize ticks into the remaining ticks. */ + current_timer -> tx_timer_internal_remaining_ticks = current_timer -> tx_timer_internal_re_initialize_ticks; + + /* Determine if the timer should be reactivated. */ + if (current_timer -> tx_timer_internal_remaining_ticks != ((ULONG) 0)) + { + + /* Make the timer appear that it is still active while processing + the expiration routine and with interrupts enabled. This will + permit proper processing of a timer deactivate from both the + expiration routine and an ISR. */ + current_timer -> tx_timer_internal_list_head = &reactivate_timer; + current_timer -> tx_timer_internal_active_next = current_timer; + + /* Setup the temporary timer list head pointer. */ + reactivate_timer = current_timer; + } + else + { + + /* Set the list pointer of this timer to NULL. This is used to indicate + the timer is no longer active. */ + current_timer -> tx_timer_internal_list_head = TX_NULL; + } + } + + /* Set pointer to indicate the expired timer that is currently being processed. */ + _tx_timer_expired_timer_ptr = current_timer; + +#ifndef TX_PROCESS_TIMER_WITH_PROTECTION + + /* Restore interrupts for timer expiration call. */ + TX_RESTORE +#endif + + /* Call the timer-expiration function, if non-NULL. */ + if (timeout_function != TX_NULL) + { + + (timeout_function) (timeout_param); + } + +#ifndef TX_PROCESS_TIMER_WITH_PROTECTION + + /* Lockout interrupts again. */ + TX_DISABLE +#endif + + /* Clear expired timer pointer. */ + _tx_timer_expired_timer_ptr = TX_NULL; + + /* Determine if the timer needs to be reactivated. */ + if (reactivate_timer == current_timer) + { + + /* Reactivate the timer. */ + +#ifdef TX_TIMER_ENABLE_PERFORMANCE_INFO + + /* Determine if this timer expired. */ + if (timeout_function != TX_NULL) + { + + /* Increment the total reactivations counter. */ + _tx_timer_performance_reactivate_count++; + + /* Determine if this is an application timer. */ + if (current_timer -> tx_timer_internal_timeout_function != &_tx_thread_timeout) + { + + /* Derive the application timer pointer. */ + + /* Pickup the application timer pointer. */ + TX_USER_TIMER_POINTER_GET(current_timer, timer_ptr) + + /* Increment the number of expirations on this timer. */ + if (timer_ptr -> tx_timer_id == TX_TIMER_ID) + { + + timer_ptr -> tx_timer_performance_reactivate_count++; + } + } + } +#endif + +#ifdef TX_REACTIVATE_INLINE + + /* Calculate the amount of time remaining for the timer. */ + if (current_timer -> tx_timer_internal_remaining_ticks > TX_TIMER_ENTRIES) + { + + /* Set expiration time to the maximum number of entries. */ + expiration_time = TX_TIMER_ENTRIES - ((UINT) 1); + } + else + { + + /* Timer value fits in the timer entries. */ + + /* Set the expiration time. */ + expiration_time = ((UINT) current_timer -> tx_timer_internal_remaining_ticks) - ((UINT) 1); + } + + /* At this point, we are ready to put the timer back on one of + the timer lists. */ + + /* Calculate the proper place for the timer. */ + timer_list = TX_TIMER_POINTER_ADD(_tx_timer_current_ptr, expiration_time); + if (TX_TIMER_INDIRECT_TO_VOID_POINTER_CONVERT(timer_list) >= TX_TIMER_INDIRECT_TO_VOID_POINTER_CONVERT(_tx_timer_list_end)) + { + + /* Wrap from the beginning of the list. */ + delta = TX_TIMER_POINTER_DIF(timer_list, _tx_timer_list_end); + timer_list = TX_TIMER_POINTER_ADD(_tx_timer_list_start, delta); + } + + /* Now put the timer on this list. */ + if ((*timer_list) == TX_NULL) + { + + /* This list is NULL, just put the new timer on it. */ + + /* Setup the links in this timer. */ + current_timer -> tx_timer_internal_active_next = current_timer; + current_timer -> tx_timer_internal_active_previous = current_timer; + + /* Setup the list head pointer. */ + *timer_list = current_timer; + } + else + { + + /* This list is not NULL, add current timer to the end. */ + next_timer = *timer_list; + previous_timer = next_timer -> tx_timer_internal_active_previous; + previous_timer -> tx_timer_internal_active_next = current_timer; + next_timer -> tx_timer_internal_active_previous = current_timer; + current_timer -> tx_timer_internal_active_next = next_timer; + current_timer -> tx_timer_internal_active_previous = previous_timer; + } + + /* Setup list head pointer. */ + current_timer -> tx_timer_internal_list_head = timer_list; +#else + + /* Reactivate through the timer activate function. */ + + /* Clear the list head for the timer activate call. */ + current_timer -> tx_timer_internal_list_head = TX_NULL; + + /* Activate the current timer. */ + _tx_timer_system_activate(current_timer); +#endif + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Determine if we need to change the core exclusion setting. */ + if (_tx_timer_thread.tx_thread_smp_cores_excluded != core_exclusion) + { + +#ifdef TX_MISRA_ENABLE + do + { + + /* Setup the new core exclusion for execution this timer. */ + status = _tx_thread_smp_core_exclude(&_tx_timer_thread, core_exclusion); + } while (status != TX_SUCCESS); +#else + + /* Setup the new core exclusion for execution this timer. */ + _tx_thread_smp_core_exclude(&_tx_timer_thread, core_exclusion); +#endif + + /* When we get to this point, the system timer thread is executing on one of the allowed cores. */ + } + + /* Lockout interrupts again. */ + TX_DISABLE + } + + /* Finally, suspend this thread and wait for the next expiration. */ + + /* Determine if another expiration took place while we were in this + thread. If so, process another expiration. */ + if (_tx_timer_expired == TX_FALSE) + { + + /* Otherwise, no timer expiration, so suspend the thread. */ + + /* Build pointer to the timer thread. */ + thread_ptr = &_tx_timer_thread; + + /* Set the status to suspending, in order to indicate the + suspension is in progress. */ + thread_ptr -> tx_thread_state = TX_SUSPENDED; + +#ifdef TX_NOT_INTERRUPTABLE + + /* Call actual non-interruptable thread suspension routine. */ + _tx_thread_system_ni_suspend(thread_ptr, ((ULONG) 0)); + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Set the suspending flag. */ + thread_ptr -> tx_thread_suspending = TX_TRUE; + + /* Increment the preempt disable count prior to suspending. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Call actual thread suspension routine. */ + _tx_thread_system_suspend(thread_ptr); +#endif + } + else + { + + /* Restore interrupts. */ + TX_RESTORE + } + } + } + +#ifdef TX_SAFETY_CRITICAL + + /* If we ever get here, raise safety critical exception. */ + TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0); +#endif + +} +#endif + diff --git a/common_smp/src/tx_trace_buffer_full_notify.c b/common_smp/src/tx_trace_buffer_full_notify.c new file mode 100644 index 00000000..90a47e7f --- /dev/null +++ b/common_smp/src/tx_trace_buffer_full_notify.c @@ -0,0 +1,109 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Trace */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#ifndef TX_SOURCE_CODE +#define TX_SOURCE_CODE +#endif + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_trace_buffer_full_notify PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets up the application callback function that is */ +/* called whenever the trace buffer becomes full. The application */ +/* can then swap to a new trace buffer in order not to lose any */ +/* events. */ +/* */ +/* INPUT */ +/* */ +/* full_buffer_callback Full trace buffer processing */ +/* function */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_trace_buffer_full_notify(VOID (*full_buffer_callback)(VOID *buffer)) +{ + +#ifdef TX_ENABLE_EVENT_TRACE + + /* Setup the callback function pointer. */ + _tx_trace_full_notify_function = full_buffer_callback; + + /* Return success. */ + return(TX_SUCCESS); + +#else + +UINT status; + + + /* Access input arguments just for the sake of lint, MISRA, etc. */ + if (full_buffer_callback != TX_NULL) + { + + /* Trace not enabled, return an error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else + { + + /* Trace not enabled, return an error. */ + status = TX_FEATURE_NOT_ENABLED; + } + + /* Return completion status. */ + return(status); +#endif +} + diff --git a/common_smp/src/tx_trace_disable.c b/common_smp/src/tx_trace_disable.c new file mode 100644 index 00000000..1b65aa2a --- /dev/null +++ b/common_smp/src/tx_trace_disable.c @@ -0,0 +1,103 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Trace */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_trace_disable PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function disables trace inside of ThreadX. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_trace_disable(VOID) +{ + +#ifdef TX_ENABLE_EVENT_TRACE +UINT status; + + + /* Determine if trace is already disabled. */ + if (_tx_trace_buffer_current_ptr == TX_NULL) + { + + /* Yes, trace is already disabled. */ + status = TX_NOT_DONE; + } + else + { + + /* Otherwise, simply clear the current pointer and registery start pointer to disable the trace. */ + _tx_trace_buffer_current_ptr = TX_NULL; + _tx_trace_registry_start_ptr = TX_NULL; + + /* Successful completion. */ + status = TX_SUCCESS; + } + + /* Return completion status. */ + return(status); + +#else + + /* Trace not enabled, return an error. */ + return(TX_FEATURE_NOT_ENABLED); +#endif +} + diff --git a/common_smp/src/tx_trace_enable.c b/common_smp/src/tx_trace_enable.c new file mode 100644 index 00000000..ab90bf56 --- /dev/null +++ b/common_smp/src/tx_trace_enable.c @@ -0,0 +1,442 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Trace */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#ifdef TX_ENABLE_EVENT_TRACE +#include "tx_thread.h" +#include "tx_timer.h" +#include "tx_event_flags.h" +#include "tx_queue.h" +#include "tx_semaphore.h" +#include "tx_mutex.h" +#include "tx_block_pool.h" +#include "tx_byte_pool.h" +#endif +#include "tx_trace.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_trace_enable PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes the ThreadX trace buffer and the */ +/* associated control variables, enabling it for operation. */ +/* */ +/* INPUT */ +/* */ +/* trace_buffer_start Start of trace buffer */ +/* trace_buffer_size Size (bytes) of trace buffer */ +/* registry_entries Number of object registry */ +/* entries. */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_system_preempt_check Check for preemption */ +/* _tx_trace_object_register Register existing objects */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_trace_enable(VOID *trace_buffer_start, ULONG trace_buffer_size, ULONG registry_entries) +{ + +#ifdef TX_ENABLE_EVENT_TRACE + +TX_INTERRUPT_SAVE_AREA + +TX_THREAD *thread_ptr; +TX_TIMER *timer_ptr; +TX_EVENT_FLAGS_GROUP *event_flags_ptr; +TX_QUEUE *queue_ptr; +TX_SEMAPHORE *semaphore_ptr; +TX_MUTEX *mutex_ptr; +TX_BLOCK_POOL *block_pool_ptr; +TX_BYTE_POOL *byte_pool_ptr; +UCHAR *work_ptr; +UCHAR *event_start_ptr; +TX_TRACE_OBJECT_ENTRY *entry_ptr; +TX_TRACE_BUFFER_ENTRY *event_ptr; +ULONG i; +UINT status; + + + /* First, see if there is enough room for the control header, the registry entries, and at least one event in + memory supplied to this call. */ + if (trace_buffer_size < ((sizeof(TX_TRACE_HEADER)) + ((sizeof(TX_TRACE_OBJECT_ENTRY)) * registry_entries) + (sizeof(TX_TRACE_BUFFER_ENTRY)))) + { + + /* No, the memory isn't big enough to hold one trace buffer entry. Return an error. */ + status = TX_SIZE_ERROR; + } + + /* Determine if trace is already enabled. */ + else if (_tx_trace_buffer_current_ptr != TX_NULL) + { + + /* Yes, trace is already enabled. */ + status = TX_NOT_DONE; + } + else + { + + /* Set the enable bits for all events enabled. */ + _tx_trace_event_enable_bits = 0xFFFFFFFFUL; + + /* Setup working pointer to the supplied memory. */ + work_ptr = TX_VOID_TO_UCHAR_POINTER_CONVERT(trace_buffer_start); + + /* Setup pointer to the trace control area. */ + _tx_trace_header_ptr = TX_UCHAR_TO_HEADER_POINTER_CONVERT(work_ptr); + + /* Move the working pointer past the control area. */ + work_ptr = TX_UCHAR_POINTER_ADD(work_ptr, (sizeof(TX_TRACE_HEADER))); + + /* Save the start of the trace object registry. */ + _tx_trace_registry_start_ptr = TX_UCHAR_TO_OBJECT_POINTER_CONVERT(work_ptr); + + /* Setup the end of the trace object registry. */ + work_ptr = TX_UCHAR_POINTER_ADD(work_ptr, (sizeof(TX_TRACE_OBJECT_ENTRY))*registry_entries); + _tx_trace_registry_end_ptr = TX_UCHAR_TO_OBJECT_POINTER_CONVERT(work_ptr); + + /* Loop to make all trace object registry entries empty and valid. */ + for (i = ((ULONG) 0); i < registry_entries; i++) + { + + /* Setup the work pointer. */ + work_ptr = TX_OBJECT_TO_UCHAR_POINTER_CONVERT(_tx_trace_registry_start_ptr); + work_ptr = TX_UCHAR_POINTER_ADD(work_ptr, (sizeof(TX_TRACE_OBJECT_ENTRY))*i); + + /* Convert to a registry entry pointer. */ + entry_ptr = TX_UCHAR_TO_OBJECT_POINTER_CONVERT(work_ptr); + + /* Initialize object registry entry. */ + entry_ptr -> tx_trace_object_entry_available = (UCHAR) TX_TRUE; + entry_ptr -> tx_trace_object_entry_type = (UCHAR) TX_TRACE_OBJECT_TYPE_NOT_VALID; + entry_ptr -> tx_trace_object_entry_reserved1 = (UCHAR) 0; + entry_ptr -> tx_trace_object_entry_reserved2 = (UCHAR) 0; + entry_ptr -> tx_trace_object_entry_thread_pointer = (ULONG) 0; + } + + /* Setup the total number of registry entries. */ + _tx_trace_total_registry_entries = registry_entries; + + /* Setup the object registry available count to the total number of registry entries. */ + _tx_trace_available_registry_entries = registry_entries; + + /* Setup the search starting index to the first entry. */ + _tx_trace_registry_search_start = ((ULONG) 0); + + /* Setup the work pointer to after the trace object registry. */ + work_ptr = TX_OBJECT_TO_UCHAR_POINTER_CONVERT(_tx_trace_registry_end_ptr); + + /* Adjust the remaining trace buffer size. */ + trace_buffer_size = trace_buffer_size - ((sizeof(TX_TRACE_OBJECT_ENTRY)) * registry_entries) - (sizeof(TX_TRACE_HEADER)); + + /* Setup pointer to the start of the actual event trace log. */ + _tx_trace_buffer_start_ptr = TX_UCHAR_TO_ENTRY_POINTER_CONVERT(work_ptr); + + /* Save the event trace log start address. */ + event_start_ptr = work_ptr; + + /* Calculate the end of the trace buffer. */ + work_ptr = TX_UCHAR_POINTER_ADD(work_ptr, ((trace_buffer_size/(sizeof(TX_TRACE_BUFFER_ENTRY)))*(sizeof(TX_TRACE_BUFFER_ENTRY)))); + _tx_trace_buffer_end_ptr = TX_UCHAR_TO_ENTRY_POINTER_CONVERT(work_ptr); + + /* Loop to mark all entries in the trace buffer as invalid. */ + for (i = ((ULONG) 0); i < (trace_buffer_size/(sizeof(TX_TRACE_BUFFER_ENTRY))); i++) + { + + /* Setup the work pointer. */ + work_ptr = TX_UCHAR_POINTER_ADD(event_start_ptr, (sizeof(TX_TRACE_BUFFER_ENTRY))*i); + + /* Convert to a trace event pointer. */ + event_ptr = TX_UCHAR_TO_ENTRY_POINTER_CONVERT(work_ptr); + + /* Mark this trace event as invalid. */ + event_ptr -> tx_trace_buffer_entry_thread_pointer = ((ULONG) 0); + } + + /* Now, fill in the event trace control header. */ + _tx_trace_header_ptr -> tx_trace_header_id = TX_TRACE_VALID; + _tx_trace_header_ptr -> tx_trace_header_timer_valid_mask = TX_TRACE_TIME_MASK; + _tx_trace_header_ptr -> tx_trace_header_trace_base_address = TX_POINTER_TO_ULONG_CONVERT(trace_buffer_start); + _tx_trace_header_ptr -> tx_trace_header_registry_start_pointer = TX_POINTER_TO_ULONG_CONVERT(_tx_trace_registry_start_ptr); + _tx_trace_header_ptr -> tx_trace_header_reserved1 = ((USHORT) 0); + _tx_trace_header_ptr -> tx_trace_header_object_name_size = ((USHORT) TX_TRACE_OBJECT_REGISTRY_NAME); + _tx_trace_header_ptr -> tx_trace_header_registry_end_pointer = TX_POINTER_TO_ULONG_CONVERT(_tx_trace_registry_end_ptr); + _tx_trace_header_ptr -> tx_trace_header_buffer_start_pointer = TX_POINTER_TO_ULONG_CONVERT(_tx_trace_buffer_start_ptr); + _tx_trace_header_ptr -> tx_trace_header_buffer_end_pointer = TX_POINTER_TO_ULONG_CONVERT(_tx_trace_buffer_end_ptr); + _tx_trace_header_ptr -> tx_trace_header_buffer_current_pointer = TX_POINTER_TO_ULONG_CONVERT(_tx_trace_buffer_start_ptr); + _tx_trace_header_ptr -> tx_trace_header_reserved2 = 0xAAAAAAAAUL; + _tx_trace_header_ptr -> tx_trace_header_reserved3 = 0xBBBBBBBBUL; + _tx_trace_header_ptr -> tx_trace_header_reserved4 = 0xCCCCCCCCUL; + + /* Now, loop through all existing ThreadX objects and register them in the newly setup trace buffer. */ + + /* Disable interrupts. */ + TX_DISABLE + + /* First, disable preemption. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Pickup the first thread and the number of created threads. */ + thread_ptr = _tx_thread_created_ptr; + i = _tx_thread_created_count; + + /* Loop to register all threads. */ + while (i != ((ULONG) 0)) + { + + /* Decrement the counter. */ + i--; + + /* Register this thread. */ + _tx_trace_object_register(TX_TRACE_OBJECT_TYPE_THREAD, thread_ptr, thread_ptr -> tx_thread_name, + TX_POINTER_TO_ULONG_CONVERT(thread_ptr -> tx_thread_stack_start), (ULONG) thread_ptr -> tx_thread_stack_size); + + /* Move to the next thread. */ + thread_ptr = thread_ptr -> tx_thread_created_next; + } + + /* Pickup the first timer and the number of created timers. */ + timer_ptr = _tx_timer_created_ptr; + i = _tx_timer_created_count; + + /* Loop to register all timers. */ + while (i != ((ULONG) 0)) + { + + /* Decrement the counter. */ + i--; + + /* Register this timer. */ + _tx_trace_object_register(TX_TRACE_OBJECT_TYPE_TIMER, timer_ptr, timer_ptr -> tx_timer_name, + ((ULONG) 0), timer_ptr -> tx_timer_internal.tx_timer_internal_re_initialize_ticks); + + /* Move to the next timer. */ + timer_ptr = timer_ptr -> tx_timer_created_next; + } + + + /* Pickup the first event flag group and the number of created groups. */ + event_flags_ptr = _tx_event_flags_created_ptr; + i = _tx_event_flags_created_count; + + /* Loop to register all event flags groups. */ + while (i != ((ULONG) 0)) + { + + /* Decrement the counter. */ + i--; + + /* Register this event flags group. */ + _tx_trace_object_register(TX_TRACE_OBJECT_TYPE_EVENT_FLAGS, event_flags_ptr, event_flags_ptr -> tx_event_flags_group_name, ((ULONG) 0), ((ULONG) 0)); + + /* Move to the next event flags group. */ + event_flags_ptr = event_flags_ptr -> tx_event_flags_group_created_next; + } + + /* Pickup the first queue and the number of created queues. */ + queue_ptr = _tx_queue_created_ptr; + i = _tx_queue_created_count; + + /* Loop to register all queues. */ + while (i != ((ULONG) 0)) + { + + /* Decrement the counter. */ + i--; + + /* Register this queue. */ + _tx_trace_object_register(TX_TRACE_OBJECT_TYPE_QUEUE, queue_ptr, queue_ptr -> tx_queue_name, + (queue_ptr -> tx_queue_capacity * (sizeof(ULONG))), ((ULONG) 0)); + + /* Move to the next queue. */ + queue_ptr = queue_ptr -> tx_queue_created_next; + } + + /* Pickup the first semaphore and the number of created semaphores. */ + semaphore_ptr = _tx_semaphore_created_ptr; + i = _tx_semaphore_created_count; + + /* Loop to register all semaphores. */ + while (i != ((ULONG) 0)) + { + + /* Decrement the counter. */ + i--; + + /* Register this semaphore. */ + _tx_trace_object_register(TX_TRACE_OBJECT_TYPE_SEMAPHORE, semaphore_ptr, semaphore_ptr -> tx_semaphore_name, ((ULONG) 0), ((ULONG) 0)); + + /* Move to the next semaphore. */ + semaphore_ptr = semaphore_ptr -> tx_semaphore_created_next; + } + + /* Pickup the first mutex and the number of created mutexes. */ + mutex_ptr = _tx_mutex_created_ptr; + i = _tx_mutex_created_count; + + /* Loop to register all mutexes. */ + while (i != ((ULONG) 0)) + { + + /* Decrement the counter. */ + i--; + + /* Register this mutex. */ + _tx_trace_object_register(TX_TRACE_OBJECT_TYPE_MUTEX, mutex_ptr, mutex_ptr -> tx_mutex_name, + (ULONG) mutex_ptr -> tx_mutex_inherit, ((ULONG) 0)); + + /* Move to the next mutex. */ + mutex_ptr = mutex_ptr -> tx_mutex_created_next; + } + + /* Pickup the first block pool and the number of created block pools. */ + block_pool_ptr = _tx_block_pool_created_ptr; + i = _tx_block_pool_created_count; + + /* Loop to register all block pools. */ + while (i != ((ULONG) 0)) + { + + /* Decrement the counter. */ + i--; + + /* Register this block pool. */ + _tx_trace_object_register(TX_TRACE_OBJECT_TYPE_BLOCK_POOL, block_pool_ptr, block_pool_ptr -> tx_block_pool_name, + block_pool_ptr -> tx_block_pool_size, ((ULONG) 0)); + + /* Move to the next block pool. */ + block_pool_ptr = block_pool_ptr -> tx_block_pool_created_next; + } + + /* Pickup the first byte pool and the number of created byte pools. */ + byte_pool_ptr = _tx_byte_pool_created_ptr; + i = _tx_byte_pool_created_count; + + /* Loop to register all byte pools. */ + while (i != ((ULONG) 0)) + { + + /* Decrement the counter. */ + i--; + + /* Register this byte pool. */ + _tx_trace_object_register(TX_TRACE_OBJECT_TYPE_BYTE_POOL, byte_pool_ptr, byte_pool_ptr -> tx_byte_pool_name, + byte_pool_ptr -> tx_byte_pool_size, ((ULONG) 0)); + + /* Move to the next byte pool. */ + byte_pool_ptr = byte_pool_ptr -> tx_byte_pool_created_next; + } + + /* Disable interrupts. */ + TX_DISABLE + + /* Release the preeemption. */ + _tx_thread_preempt_disable--; + + /* Finally, setup the current buffer pointer, which effectively enables the trace! */ + _tx_trace_buffer_current_ptr = (TX_TRACE_BUFFER_ENTRY *) _tx_trace_buffer_start_ptr; + + /* Insert two RUNNING events so the buffer is not empty. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_RUNNING, 0, 0, 0, 0, TX_TRACE_INTERNAL_EVENTS) + TX_TRACE_IN_LINE_INSERT(TX_TRACE_RUNNING, 0, 0, 0, 0, TX_TRACE_INTERNAL_EVENTS) + + /* Restore interrupts. */ + TX_RESTORE + + /* Check for preemption. */ + _tx_thread_system_preempt_check(); + + /* Return successful completion. */ + status = TX_SUCCESS; + } + + /* Return completion status. */ + return(status); +#else + +UINT status; + + + /* Access input arguments just for the sake of lint, MISRA, etc. */ + if (trace_buffer_start != TX_NULL) + { + + /* Trace not enabled, return an error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (trace_buffer_size == ((ULONG) 0)) + { + + /* Trace not enabled, return an error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (registry_entries == ((ULONG) 0)) + { + + /* Trace not enabled, return an error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else + { + + /* Trace not enabled, return an error. */ + status = TX_FEATURE_NOT_ENABLED; + } + + /* Return completion status. */ + return(status); +#endif +} + + + diff --git a/common_smp/src/tx_trace_event_filter.c b/common_smp/src/tx_trace_event_filter.c new file mode 100644 index 00000000..b4e7f41f --- /dev/null +++ b/common_smp/src/tx_trace_event_filter.c @@ -0,0 +1,106 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Trace */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#ifndef TX_SOURCE_CODE +#define TX_SOURCE_CODE +#endif + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_trace_event_filter PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets up the event filter, which allows the */ +/* application to filter various trace events during run-time. */ +/* */ +/* INPUT */ +/* */ +/* event_filter_bits Trace filter event bit(s) */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_trace_event_filter(ULONG event_filter_bits) +{ + +#ifdef TX_ENABLE_EVENT_TRACE + + /* Apply the specified filter by clearing the enable bits. */ + _tx_trace_event_enable_bits = _tx_trace_event_enable_bits & (~event_filter_bits); + + /* Return success. */ + return(TX_SUCCESS); + +#else + +UINT status; + + + /* Access input arguments just for the sake of lint, MISRA, etc. */ + if (event_filter_bits != ((ULONG) 0)) + { + + /* Trace not enabled, return an error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else + { + + /* Trace not enabled, return an error. */ + status = TX_FEATURE_NOT_ENABLED; + } + + /* Return completion status. */ + return(status); +#endif +} + diff --git a/common_smp/src/tx_trace_event_unfilter.c b/common_smp/src/tx_trace_event_unfilter.c new file mode 100644 index 00000000..cb8bc74d --- /dev/null +++ b/common_smp/src/tx_trace_event_unfilter.c @@ -0,0 +1,106 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Trace */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#ifndef TX_SOURCE_CODE +#define TX_SOURCE_CODE +#endif + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_trace_event_unfilter PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function removes the event filter, which allows the */ +/* application to un-filter various trace events during run-time. */ +/* */ +/* INPUT */ +/* */ +/* event_unfilter_bits Trace un-filter event bit(s) */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_trace_event_unfilter(ULONG event_unfilter_bits) +{ + +#ifdef TX_ENABLE_EVENT_TRACE + + /* Make sure the specified bits are set in the event enable variable. */ + _tx_trace_event_enable_bits = _tx_trace_event_enable_bits | event_unfilter_bits; + + /* Return success. */ + return(TX_SUCCESS); + +#else + +UINT status; + + + /* Access input arguments just for the sake of lint, MISRA, etc. */ + if (event_unfilter_bits != ((ULONG) 0)) + { + + /* Trace not enabled, return an error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else + { + + /* Trace not enabled, return an error. */ + status = TX_FEATURE_NOT_ENABLED; + } + + /* Return completion status. */ + return(status); +#endif +} + diff --git a/common_smp/src/tx_trace_initialize.c b/common_smp/src/tx_trace_initialize.c new file mode 100644 index 00000000..16458b87 --- /dev/null +++ b/common_smp/src/tx_trace_initialize.c @@ -0,0 +1,152 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Trace */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#ifdef TX_ENABLE_EVENT_TRACE + + +/* Define the pointer to the start of the trace buffer control structure. */ + +TX_TRACE_HEADER *_tx_trace_header_ptr; + + +/* Define the pointer to the start of the trace object registry area in the trace buffer. */ + +TX_TRACE_OBJECT_ENTRY *_tx_trace_registry_start_ptr; + + +/* Define the pointer to the end of the trace object registry area in the trace buffer. */ + +TX_TRACE_OBJECT_ENTRY *_tx_trace_registry_end_ptr; + + +/* Define the pointer to the starting entry of the actual trace event area of the trace buffer. */ + +TX_TRACE_BUFFER_ENTRY *_tx_trace_buffer_start_ptr; + + +/* Define the pointer to the ending entry of the actual trace event area of the trace buffer. */ + +TX_TRACE_BUFFER_ENTRY *_tx_trace_buffer_end_ptr; + + +/* Define the pointer to the current entry of the actual trace event area of the trace buffer. */ + +TX_TRACE_BUFFER_ENTRY *_tx_trace_buffer_current_ptr; + + +/* Define the trace event enable bits, where each bit represents a type of event that can be enabled + or disabled dynamically by the application. */ + +ULONG _tx_trace_event_enable_bits; + + +/* Define a counter that is used in environments that don't have a timer source. This counter + is incremented on each use giving each event a unique timestamp. */ + +ULONG _tx_trace_simulated_time; + + +/* Define the function pointer used to call the application when the trace buffer wraps. If NULL, + the application has not registered a callback function. */ + +VOID (*_tx_trace_full_notify_function)(VOID *buffer); + + +/* Define the total number of registry entries. */ + +ULONG _tx_trace_total_registry_entries; + + +/* Define a counter that is used to track the number of available registry entries. */ + +ULONG _tx_trace_available_registry_entries; + + +/* Define an index that represents the start of the registry search. */ + +ULONG _tx_trace_registry_search_start; + +#endif + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_trace_initialize PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes the various control data structures for */ +/* the trace component. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_high_level High level initialization */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_trace_initialize(VOID) +{ + +#ifdef TX_ENABLE_EVENT_TRACE +#ifndef TX_DISABLE_REDUNDANT_CLEARING + + /* Initialize all the pointers to the trace buffer to NULL. */ + _tx_trace_header_ptr = TX_NULL; + _tx_trace_registry_start_ptr = TX_NULL; + _tx_trace_registry_end_ptr = TX_NULL; + _tx_trace_buffer_start_ptr = TX_NULL; + _tx_trace_buffer_end_ptr = TX_NULL; + _tx_trace_buffer_current_ptr = TX_NULL; +#endif +#endif +} + diff --git a/common_smp/src/tx_trace_interrupt_control.c b/common_smp/src/tx_trace_interrupt_control.c new file mode 100644 index 00000000..f07dfa50 --- /dev/null +++ b/common_smp/src/tx_trace_interrupt_control.c @@ -0,0 +1,104 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Trace */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_trace_interrupt_control PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function provides a shell for the tx_interrupt_control */ +/* function so that a trace event can be logged for its use. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt posture */ +/* */ +/* OUTPUT */ +/* */ +/* Previous Interrupt Posture */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_interrupt_control Interrupt control service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_trace_interrupt_control(UINT new_posture) +{ + +#ifdef TX_ENABLE_EVENT_TRACE + +TX_INTERRUPT_SAVE_AREA +UINT saved_posture; + + /* Disable interrupts. */ + TX_DISABLE + + /* Insert this event into the trace buffer. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_INTERRUPT_CONTROL, TX_ULONG_TO_POINTER_CONVERT(new_posture), TX_POINTER_TO_ULONG_CONVERT(&saved_posture), 0, 0, TX_TRACE_INTERRUPT_CONTROL_EVENT) + + /* Restore interrupts. */ + TX_RESTORE + + /* Perform the interrupt service. */ + saved_posture = _tx_thread_interrupt_control(new_posture); + + /* Return saved posture. */ + return(saved_posture); +#else + +UINT saved_posture; + + /* Perform the interrupt service. */ + saved_posture = _tx_thread_interrupt_control(new_posture); + + /* Return saved posture. */ + return(saved_posture); +#endif +} + diff --git a/common_smp/src/tx_trace_isr_enter_insert.c b/common_smp/src/tx_trace_isr_enter_insert.c new file mode 100644 index 00000000..08d758e5 --- /dev/null +++ b/common_smp/src/tx_trace_isr_enter_insert.c @@ -0,0 +1,108 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Trace */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#ifdef TX_ENABLE_EVENT_TRACE +#include "tx_thread.h" +#endif +#include "tx_trace.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_trace_isr_enter_insert PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function provides inserts an ISR entry event into the trace */ +/* buffer. */ +/* */ +/* INPUT */ +/* */ +/* isr_id User defined ISR ID */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_trace_isr_enter_insert(ULONG isr_id) +{ + +TX_INTERRUPT_SAVE_AREA + + +#ifdef TX_ENABLE_EVENT_TRACE + +UINT stack_address; +ULONG system_state; +UINT preempt_disable; + + + /* Disable interrupts. */ + TX_DISABLE + + /* Insert this event into the trace buffer. */ + system_state = TX_THREAD_GET_SYSTEM_STATE(); + preempt_disable = _tx_thread_preempt_disable; + TX_TRACE_IN_LINE_INSERT(TX_TRACE_ISR_ENTER, &stack_address, isr_id, system_state, preempt_disable, TX_TRACE_INTERNAL_EVENTS) + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Access input arguments just for the sake of lint, MISRA, etc. */ + if (isr_id != ((ULONG) 0)) + { + + /* NOP code. */ + TX_DISABLE + TX_RESTORE + } +#endif +} + diff --git a/common_smp/src/tx_trace_isr_exit_insert.c b/common_smp/src/tx_trace_isr_exit_insert.c new file mode 100644 index 00000000..f070491d --- /dev/null +++ b/common_smp/src/tx_trace_isr_exit_insert.c @@ -0,0 +1,108 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Trace */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#ifdef TX_ENABLE_EVENT_TRACE +#include "tx_thread.h" +#endif +#include "tx_trace.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_trace_isr_exit_insert PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function provides inserts an ISR exit event into the trace */ +/* buffer. */ +/* */ +/* INPUT */ +/* */ +/* isr_id User defined ISR ID */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_trace_isr_exit_insert(ULONG isr_id) +{ + +TX_INTERRUPT_SAVE_AREA + + +#ifdef TX_ENABLE_EVENT_TRACE + +UINT stack_address; +ULONG system_state; +UINT preempt_disable; + + + /* Disable interrupts. */ + TX_DISABLE + + /* Insert this event into the trace buffer. */ + system_state = TX_THREAD_GET_SYSTEM_STATE(); + preempt_disable = _tx_thread_preempt_disable; + TX_TRACE_IN_LINE_INSERT(TX_TRACE_ISR_EXIT, &stack_address, isr_id, system_state, preempt_disable, TX_TRACE_INTERNAL_EVENTS) + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Access input arguments just for the sake of lint, MISRA, etc. */ + if (isr_id != ((ULONG) 0)) + { + + /* NOP code. */ + TX_DISABLE + TX_RESTORE + } +#endif +} + diff --git a/common_smp/src/tx_trace_object_register.c b/common_smp/src/tx_trace_object_register.c new file mode 100644 index 00000000..de201edd --- /dev/null +++ b/common_smp/src/tx_trace_object_register.c @@ -0,0 +1,291 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Trace */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_trace_object_register PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers a ThreadX system object in the trace */ +/* registry area. This provides a mapping between the object pointers */ +/* stored in each trace event to the actual ThreadX objects. */ +/* */ +/* INPUT */ +/* */ +/* object_type Type of system object */ +/* object_ptr Address of system object */ +/* object_name Name of system object */ +/* parameter_1 Supplemental parameter 1 */ +/* parameter_2 Supplemental parameter 2 */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_trace_object_register(UCHAR object_type, VOID *object_ptr, CHAR *object_name, ULONG parameter_1, ULONG parameter_2) +{ + +#ifdef TX_ENABLE_EVENT_TRACE + +UINT i, entries; +UINT found, loop_break; +TX_THREAD *thread_ptr; +UCHAR *work_ptr; +TX_TRACE_OBJECT_ENTRY *entry_ptr; + + + /* Determine if the registry area is setup. */ + if (_tx_trace_registry_start_ptr != TX_NULL) + { + + /* Trace buffer is enabled, proceed. */ + + /* Pickup the total entries. */ + entries = _tx_trace_total_registry_entries; + + /* Determine if there are available entries in the registry. */ + if (_tx_trace_available_registry_entries != ((ULONG) 0)) + { + + /* There are more available entries, proceed. */ + + /* Initialize found to the max entries... indicating no space was found. */ + found = entries; + loop_break = TX_FALSE; + + /* Loop to find available entry. */ + i = _tx_trace_registry_search_start; + do + { + + /* Setup the registry entry pointer. */ + work_ptr = TX_OBJECT_TO_UCHAR_POINTER_CONVERT(_tx_trace_registry_start_ptr); + work_ptr = TX_UCHAR_POINTER_ADD(work_ptr, ((sizeof(TX_TRACE_OBJECT_ENTRY))*i)); + entry_ptr = TX_UCHAR_TO_OBJECT_POINTER_CONVERT(work_ptr); + + /* Determine if this is the first pass building the registry. A NULL object value indicates this part + of the registry has never been used. */ + if (entry_ptr -> tx_trace_object_entry_thread_pointer == (ULONG) 0) + { + + /* Set found to this index and break out of the loop. */ + found = i; + loop_break = TX_TRUE; + } + + /* Determine if this entry matches the object pointer... we must reuse old entries left in the + registry. */ + if (entry_ptr -> tx_trace_object_entry_thread_pointer == TX_POINTER_TO_ULONG_CONVERT(object_ptr)) + { + + /* Set found to this index and break out of the loop. */ + found = i; + loop_break = TX_TRUE; + } + + /* Determine if we should break out of the loop. */ + if (loop_break == TX_TRUE) + { + + /* Yes, break out of the loop. */ + break; + } + + /* Is this entry available? */ + if (entry_ptr -> tx_trace_object_entry_available == TX_TRUE) + { + + /* Yes, determine if we have not already found an empty slot. */ + if (found == entries) + { + found = i; + } + else + { + + /* Setup a pointer to the found entry. */ + work_ptr = TX_OBJECT_TO_UCHAR_POINTER_CONVERT(_tx_trace_registry_start_ptr); + work_ptr = TX_UCHAR_POINTER_ADD(work_ptr, ((sizeof(TX_TRACE_OBJECT_ENTRY))*found)); + entry_ptr = TX_UCHAR_TO_OBJECT_POINTER_CONVERT(work_ptr); + + if (entry_ptr -> tx_trace_object_entry_type != ((UCHAR) 0)) + { + found = i; + } + } + } + + /* Move to the next entry. */ + i++; + + /* Determine if we have wrapped the list. */ + if (i >= entries) + { + + /* Yes, wrap to the beginning of the list. */ + i = ((ULONG) 0); + } + + } while (i != _tx_trace_registry_search_start); + + /* Now determine if an empty or reuse entry has been found. */ + if (found < entries) + { + + /* Decrement the number of available entries. */ + _tx_trace_available_registry_entries--; + + /* Adjust the search index to the next entry. */ + if ((found + ((ULONG) 1)) < entries) + { + + /* Start searching from the next index. */ + _tx_trace_registry_search_start = found + ((ULONG) 1); + } + else + { + + /* Reset the search to the beginning of the list. */ + _tx_trace_registry_search_start = ((ULONG) 0); + } + + /* Yes, an entry has been found... */ + + /* Build a pointer to the found entry. */ + work_ptr = TX_OBJECT_TO_UCHAR_POINTER_CONVERT(_tx_trace_registry_start_ptr); + work_ptr = TX_UCHAR_POINTER_ADD(work_ptr, ((sizeof(TX_TRACE_OBJECT_ENTRY))*found)); + entry_ptr = TX_UCHAR_TO_OBJECT_POINTER_CONVERT(work_ptr); + + /* Populate the found entry! */ + entry_ptr -> tx_trace_object_entry_available = ((UCHAR) TX_FALSE); + entry_ptr -> tx_trace_object_entry_type = object_type; + entry_ptr -> tx_trace_object_entry_thread_pointer = TX_POINTER_TO_ULONG_CONVERT(object_ptr); + entry_ptr -> tx_trace_object_entry_param_1 = parameter_1; + entry_ptr -> tx_trace_object_entry_param_2 = parameter_2; + + /* Loop to copy the object name string... */ + for (i = ((ULONG) 0); i < (((ULONG) TX_TRACE_OBJECT_REGISTRY_NAME)-((ULONG) 1)); i++) + { + + /* Setup work pointer to the object name character. */ + work_ptr = TX_CHAR_TO_UCHAR_POINTER_CONVERT(object_name); + work_ptr = TX_UCHAR_POINTER_ADD(work_ptr, i); + + /* Copy a character of the name. */ + entry_ptr -> tx_trace_object_entry_name[i] = (UCHAR) *work_ptr; + + /* Determine if we are at the end. */ + if (*work_ptr == ((UCHAR) 0)) + { + break; + } + } + + /* Null terminate the object string. */ + entry_ptr -> tx_trace_object_entry_name[i] = (UCHAR) 0; + + /* Determine if a thread object type is present. */ + if (object_type == TX_TRACE_OBJECT_TYPE_THREAD) + { + + /* Yes, a thread object is present. */ + + /* Setup a pointer to the thread. */ + thread_ptr = TX_VOID_TO_THREAD_POINTER_CONVERT(object_ptr); + + /* Store the thread's priority in the reserved bits. */ + entry_ptr -> tx_trace_object_entry_reserved1 = ((UCHAR) 0x80) | ((UCHAR) (thread_ptr -> tx_thread_priority >> ((UCHAR) 8))); + entry_ptr -> tx_trace_object_entry_reserved2 = (UCHAR) (thread_ptr -> tx_thread_priority & ((UCHAR) 0xFF)); + } + else + { + + /* For all other objects, set the reserved bytes to 0. */ + entry_ptr -> tx_trace_object_entry_reserved1 = ((UCHAR) 0); + entry_ptr -> tx_trace_object_entry_reserved2 = ((UCHAR) 0); + } + } + } + } +#else + +TX_INTERRUPT_SAVE_AREA + + + /* Access input arguments just for the sake of lint, MISRA, etc. */ + if (object_type != ((UCHAR) 0)) + { + + if (object_ptr != TX_NULL) + { + + if (object_name != TX_NULL) + { + + if (parameter_1 != ((ULONG) 0)) + { + + if (parameter_2 != ((ULONG) 0)) + { + + /* NOP code. */ + TX_DISABLE + TX_RESTORE + } + } + } + } + } +#endif +} + diff --git a/common_smp/src/tx_trace_object_unregister.c b/common_smp/src/tx_trace_object_unregister.c new file mode 100644 index 00000000..e72e919c --- /dev/null +++ b/common_smp/src/tx_trace_object_unregister.c @@ -0,0 +1,131 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Trace */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_trace_object_unregister PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function unregisters a ThreadX system object from the trace */ +/* registry area. */ +/* */ +/* INPUT */ +/* */ +/* object_pointer Address of system object */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_trace_object_unregister(VOID *object_ptr) +{ + +#ifdef TX_ENABLE_EVENT_TRACE + +UINT i, entries; +UCHAR *work_ptr; +TX_TRACE_OBJECT_ENTRY *entry_ptr; + + + /* Determine if the registry area is setup. */ + if (_tx_trace_registry_start_ptr != TX_NULL) + { + + /* Registry is setup, proceed. */ + + /* Pickup the total entries. */ + entries = _tx_trace_total_registry_entries; + + /* Loop to find available entry. */ + for (i = ((ULONG) 0); i < entries; i++) + { + + /* Setup the registry entry pointer. */ + work_ptr = TX_OBJECT_TO_UCHAR_POINTER_CONVERT(_tx_trace_registry_start_ptr); + work_ptr = TX_UCHAR_POINTER_ADD(work_ptr, ((sizeof(TX_TRACE_OBJECT_ENTRY))*i)); + entry_ptr = TX_UCHAR_TO_OBJECT_POINTER_CONVERT(work_ptr); + + /* Determine if this entry matches the object pointer... */ + if (entry_ptr -> tx_trace_object_entry_thread_pointer == TX_POINTER_TO_ULONG_CONVERT(object_ptr)) + { + + /* Mark this entry as available, but leave the other information so that old trace entries can + still find it - if necessary! */ + entry_ptr -> tx_trace_object_entry_available = ((UCHAR) TX_TRUE); + + /* Increment the number of available registry entries. */ + _tx_trace_available_registry_entries++; + + /* Adjust the search index to this position. */ + _tx_trace_registry_search_start = i; + + break; + } + } + } +#else + +TX_INTERRUPT_SAVE_AREA + + + /* Access input arguments just for the sake of lint, MISRA, etc. */ + if (object_ptr != TX_NULL) + { + + /* NOP code. */ + TX_DISABLE + TX_RESTORE + } +#endif +} + diff --git a/common_smp/src/tx_trace_user_event_insert.c b/common_smp/src/tx_trace_user_event_insert.c new file mode 100644 index 00000000..09573ba9 --- /dev/null +++ b/common_smp/src/tx_trace_user_event_insert.c @@ -0,0 +1,160 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Trace */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_trace.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_trace_user_event_insert PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function inserts a user-defined event into the trace buffer. */ +/* */ +/* INPUT */ +/* */ +/* event_id User Event ID */ +/* info_field_1 First information field */ +/* info_field_2 First information field */ +/* info_field_3 First information field */ +/* info_field_4 First information field */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_trace_user_event_insert(ULONG event_id, ULONG info_field_1, ULONG info_field_2, ULONG info_field_3, ULONG info_field_4) +{ + +#ifdef TX_ENABLE_EVENT_TRACE + +TX_INTERRUPT_SAVE_AREA + +UINT status; + + + /* Disable interrupts. */ + TX_DISABLE + + /* Determine if trace is disabled. */ + if (_tx_trace_buffer_current_ptr == TX_NULL) + { + + /* Yes, trace is already disabled. */ + status = TX_NOT_DONE; + } + else + { + + /* Insert this event into the trace buffer. */ +#ifdef TX_MISRA_ENABLE + TX_TRACE_IN_LINE_INSERT(event_id, TX_ULONG_TO_POINTER_CONVERT(info_field_1), info_field_2, info_field_3, info_field_4, ((ULONG) TX_TRACE_USER_EVENTS)) +#else + TX_TRACE_IN_LINE_INSERT(event_id, info_field_1, info_field_2, info_field_3, info_field_4, TX_TRACE_USER_EVENTS) +#endif + + /* Return successful status. */ + status = TX_SUCCESS; + } + + /* Restore interrupts. */ + TX_RESTORE + + /* Return completion status. */ + return(status); + +#else + +UINT status; + + + /* Access input arguments just for the sake of lint, MISRA, etc. */ + if (event_id != ((ULONG) 0)) + { + + /* Trace not enabled, return an error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (info_field_1 != ((ULONG) 0)) + { + + /* Trace not enabled, return an error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (info_field_2 != ((ULONG) 0)) + { + + /* Trace not enabled, return an error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (info_field_3 != ((ULONG) 0)) + { + + /* Trace not enabled, return an error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else if (info_field_4 != ((ULONG) 0)) + { + + /* Trace not enabled, return an error. */ + status = TX_FEATURE_NOT_ENABLED; + } + else + { + + /* Trace not enabled, return an error. */ + status = TX_FEATURE_NOT_ENABLED; + } + + /* Return completion status. */ + return(status); +#endif +} + diff --git a/common_smp/src/txe_block_allocate.c b/common_smp/src/txe_block_allocate.c new file mode 100644 index 00000000..995e8028 --- /dev/null +++ b/common_smp/src/txe_block_allocate.c @@ -0,0 +1,160 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Block Pool */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +#include "tx_block_pool.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_block_allocate PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the allocate block memory */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* pool_ptr Pointer to pool control block */ +/* block_ptr Pointer to place allocated block */ +/* pointer */ +/* wait_option Suspension option */ +/* */ +/* OUTPUT */ +/* */ +/* TX_POOL_ERROR Invalid pool pointer */ +/* TX_PTR_ERROR Invalid destination pointer */ +/* TX_WAIT_ERROR Invalid wait option */ +/* status Actual Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_block_allocate Actual block allocate function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_block_allocate(TX_BLOCK_POOL *pool_ptr, VOID **block_ptr, ULONG wait_option) +{ + +UINT status; + +#ifndef TX_TIMER_PROCESS_IN_ISR + +TX_THREAD *current_thread; +#endif + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid pool pointer. */ + if (pool_ptr == TX_NULL) + { + + /* Pool pointer is invalid, return appropriate error code. */ + status = TX_POOL_ERROR; + } + + /* Check for an invalid pool pointer. */ + else if (pool_ptr -> tx_block_pool_id != TX_BLOCK_POOL_ID) + { + + /* Pool pointer is invalid, return appropriate error code. */ + status = TX_POOL_ERROR; + } + + /* Check for an invalid destination for return pointer. */ + else if (block_ptr == TX_NULL) + { + + /* Null destination pointer, return appropriate error. */ + status = TX_PTR_ERROR; + } + else + { + + /* Check for a wait option error. Only threads are allowed any form of + suspension. */ + if (wait_option != TX_NO_WAIT) + { + + /* Is the call from an ISR or Initialization? */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + + /* A non-thread is trying to suspend, return appropriate error code. */ + status = TX_WAIT_ERROR; + } + +#ifndef TX_TIMER_PROCESS_IN_ISR + else + { + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(current_thread) + + /* Is the current thread the timer thread? */ + if (current_thread == &_tx_timer_thread) + { + + /* A non-thread is trying to suspend, return appropriate error code. */ + status = TX_WAIT_ERROR; + } + } +#endif + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + + /* Call actual block allocate function. */ + status = _tx_block_allocate(pool_ptr, block_ptr, wait_option); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_block_pool_create.c b/common_smp/src/txe_block_pool_create.c new file mode 100644 index 00000000..04253534 --- /dev/null +++ b/common_smp/src/txe_block_pool_create.c @@ -0,0 +1,227 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Block Pool */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_timer.h" +#include "tx_block_pool.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_block_pool_create PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the create block memory pool */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* pool_ptr Pointer to pool control block */ +/* name_ptr Pointer to block pool name */ +/* block_size Number of bytes in each block */ +/* pool_start Address of beginning of pool area */ +/* pool_size Number of bytes in the block pool */ +/* pool_control_block_size Size of block pool control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_POOL_ERROR Invalid pool pointer */ +/* TX_PTR_ERROR Invalid starting address */ +/* TX_SIZE_ERROR Invalid pool size */ +/* TX_CALLER_ERROR Invalid caller of pool */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_block_pool_create Actual block pool create function */ +/* _tx_thread_system_preempt_check Check for preemption */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_block_pool_create(TX_BLOCK_POOL *pool_ptr, CHAR *name_ptr, ULONG block_size, + VOID *pool_start, ULONG pool_size, UINT pool_control_block_size) +{ + +TX_INTERRUPT_SAVE_AREA + +UINT status; +ULONG i; +TX_BLOCK_POOL *next_pool; +#ifndef TX_TIMER_PROCESS_IN_ISR +TX_THREAD *thread_ptr; +#endif + + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid pool pointer. */ + if (pool_ptr == TX_NULL) + { + + /* Pool pointer is invalid, return appropriate error code. */ + status = TX_POOL_ERROR; + } + + /* Check for invalid control block size. */ + else if (pool_control_block_size != (sizeof(TX_BLOCK_POOL))) + { + + /* Pool pointer is invalid, return appropriate error code. */ + status = TX_POOL_ERROR; + } + else + { + + /* Disable interrupts. */ + TX_DISABLE + + /* Increment the preempt disable flag. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Next see if it is already in the created list. */ + next_pool = _tx_block_pool_created_ptr; + for (i = ((ULONG) 0); i < _tx_block_pool_created_count; i++) + { + + /* Determine if this block pool matches the pool in the list. */ + if (pool_ptr == next_pool) + { + + break; + } + else + { + /* Move to the next pool. */ + next_pool = next_pool -> tx_block_pool_created_next; + } + } + + /* Disable interrupts. */ + TX_DISABLE + + /* Decrement the preempt disable flag. */ + _tx_thread_preempt_disable--; + + /* Restore interrupts. */ + TX_RESTORE + + /* Check for preemption. */ + _tx_thread_system_preempt_check(); + + /* At this point, check to see if there is a duplicate pool. */ + if (pool_ptr == next_pool) + { + + /* Pool is already created, return appropriate error code. */ + status = TX_POOL_ERROR; + } + + /* Check for an invalid starting address. */ + else if (pool_start == TX_NULL) + { + + /* Null starting address pointer, return appropriate error. */ + status = TX_PTR_ERROR; + } + else + { + + /* Check for invalid pool size. */ + if ((((block_size/(sizeof(void *)))*(sizeof(void *))) + (sizeof(void *))) > + ((pool_size/(sizeof(void *)))*(sizeof(void *)))) + { + + /* Not enough memory for one block, return appropriate error. */ + status = TX_SIZE_ERROR; + } + else + { + +#ifndef TX_TIMER_PROCESS_IN_ISR + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr) + + /* Check for invalid caller of this function. First check for a calling thread. */ + if (thread_ptr == &_tx_timer_thread) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } +#endif + + /* Check for interrupt call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + + /* Now, make sure the call is from an interrupt and not initialization. */ + if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } + } + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + + /* Call actual block pool create function. */ + status = _tx_block_pool_create(pool_ptr, name_ptr, block_size, pool_start, pool_size); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_block_pool_delete.c b/common_smp/src/txe_block_pool_delete.c new file mode 100644 index 00000000..91324624 --- /dev/null +++ b/common_smp/src/txe_block_pool_delete.c @@ -0,0 +1,146 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Block Pool */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +#include "tx_block_pool.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_block_pool_delete PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the delete block pool memory */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* pool_ptr Pointer to pool control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_POOL_ERROR Invalid memory block pool pointer */ +/* TX_CALLER_ERROR Invalid caller of this function */ +/* status Actual delete function status */ +/* */ +/* CALLS */ +/* */ +/* _tx_block_pool_delete Actual block pool delete function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_block_pool_delete(TX_BLOCK_POOL *pool_ptr) +{ + +UINT status; +#ifndef TX_TIMER_PROCESS_IN_ISR +TX_THREAD *thread_ptr; +#endif + + +#ifndef TX_TIMER_PROCESS_IN_ISR + + /* Default status to success. */ + status = TX_SUCCESS; +#endif + + /* Check for an invalid pool pointer. */ + if (pool_ptr == TX_NULL) + { + + /* Pool pointer is invalid, return appropriate error code. */ + status = TX_POOL_ERROR; + } + + /* Now check the pool ID. */ + else if (pool_ptr -> tx_block_pool_id != TX_BLOCK_POOL_ID) + { + + /* Pool pointer is invalid, return appropriate error code. */ + status = TX_POOL_ERROR; + } + + /* Check for invalid caller of this function. */ + + /* Is the call from an ISR or initialization? */ + else if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + else + { + +#ifndef TX_TIMER_PROCESS_IN_ISR + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr) + + /* Is the call from the system timer thread? */ + if (thread_ptr == &_tx_timer_thread) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { +#endif + + /* Call actual block pool delete function. */ + status = _tx_block_pool_delete(pool_ptr); + +#ifndef TX_TIMER_PROCESS_IN_ISR + } +#endif + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_block_pool_info_get.c b/common_smp/src/txe_block_pool_info_get.c new file mode 100644 index 00000000..3486363d --- /dev/null +++ b/common_smp/src/txe_block_pool_info_get.c @@ -0,0 +1,114 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Block Memory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_block_pool.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_block_pool_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the block pool information get */ +/* service. */ +/* */ +/* INPUT */ +/* */ +/* pool_ptr Pointer to block pool control blk */ +/* name Destination for the pool name */ +/* available_blocks Number of free blocks in pool */ +/* total_blocks Total number of blocks in pool */ +/* first_suspended Destination for pointer of first */ +/* thread suspended on block pool */ +/* suspended_count Destination for suspended count */ +/* next_pool Destination for pointer to next */ +/* block pool on the created list */ +/* */ +/* OUTPUT */ +/* */ +/* TX_POOL_ERROR Invalid block pool pointer */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_block_pool_info_get Actual block pool info get service*/ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_block_pool_info_get(TX_BLOCK_POOL *pool_ptr, CHAR **name, ULONG *available_blocks, + ULONG *total_blocks, TX_THREAD **first_suspended, + ULONG *suspended_count, TX_BLOCK_POOL **next_pool) +{ + + +UINT status; + + + /* Check for an invalid block pool pointer. */ + if (pool_ptr == TX_NULL) + { + + /* Block pool pointer is invalid, return appropriate error code. */ + status = TX_POOL_ERROR; + } + + /* Now check the pool ID. */ + else if (pool_ptr -> tx_block_pool_id != TX_BLOCK_POOL_ID) + { + + /* Block pool pointer is invalid, return appropriate error code. */ + status = TX_POOL_ERROR; + } + else + { + + /* Otherwise, call the actual block pool information get service. */ + status = _tx_block_pool_info_get(pool_ptr, name, available_blocks, + total_blocks, first_suspended, suspended_count, next_pool); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_block_pool_prioritize.c b/common_smp/src/txe_block_pool_prioritize.c new file mode 100644 index 00000000..b5331595 --- /dev/null +++ b/common_smp/src/txe_block_pool_prioritize.c @@ -0,0 +1,101 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Block Pool */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_block_pool.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_block_pool_prioritize PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the block pool prioritize call. */ +/* */ +/* INPUT */ +/* */ +/* pool_ptr Pointer to pool control block */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_block_pool_prioritize Actual block pool prioritize */ +/* function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_block_pool_prioritize(TX_BLOCK_POOL *pool_ptr) +{ + +UINT status; + + + /* Check for an invalid block memory pool pointer. */ + if (pool_ptr == TX_NULL) + { + + /* Block memory pointer is invalid, return appropriate error code. */ + status = TX_POOL_ERROR; + } + + /* Now check for invalid pool ID. */ + else if (pool_ptr -> tx_block_pool_id != TX_BLOCK_POOL_ID) + { + + /* Block memory pointer is invalid, return appropriate error code. */ + status = TX_POOL_ERROR; + } + else + { + + /* Call actual block pool prioritize function. */ + status = _tx_block_pool_prioritize(pool_ptr); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_block_release.c b/common_smp/src/txe_block_release.c new file mode 100644 index 00000000..60f2a9b0 --- /dev/null +++ b/common_smp/src/txe_block_release.c @@ -0,0 +1,123 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Block Pool */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_block_pool.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_block_release PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the block release function call. */ +/* */ +/* INPUT */ +/* */ +/* block_ptr Pointer to memory block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_PTR_ERROR Invalid memory block pointer */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_block_release Actual block release function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_block_release(VOID *block_ptr) +{ + +UINT status; +TX_BLOCK_POOL *pool_ptr; +UCHAR **indirect_ptr; +UCHAR *work_ptr; + + + /* First check the supplied pointer. */ + if (block_ptr == TX_NULL) + { + + /* The block pointer is invalid, return appropriate status. */ + status = TX_PTR_ERROR; + } + else + { + + /* Pickup the pool pointer which is just previous to the starting + address of block that the caller sees. */ + work_ptr = TX_VOID_TO_UCHAR_POINTER_CONVERT(block_ptr); + work_ptr = TX_UCHAR_POINTER_SUB(work_ptr, (sizeof(UCHAR *))); + indirect_ptr = TX_UCHAR_TO_INDIRECT_UCHAR_POINTER_CONVERT(work_ptr); + work_ptr = *indirect_ptr; + pool_ptr = TX_UCHAR_TO_BLOCK_POOL_POINTER_CONVERT(work_ptr); + + /* Check for an invalid pool pointer. */ + if (pool_ptr == TX_NULL) + { + + /* Pool pointer is invalid, return appropriate error code. */ + status = TX_PTR_ERROR; + } + + /* Now check for invalid pool ID. */ + else if (pool_ptr -> tx_block_pool_id != TX_BLOCK_POOL_ID) + { + + /* Pool pointer is invalid, return appropriate error code. */ + status = TX_PTR_ERROR; + } + else + { + + /* Call actual block release function. */ + status = _tx_block_release(block_ptr); + } + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_byte_allocate.c b/common_smp/src/txe_byte_allocate.c new file mode 100644 index 00000000..a93fac01 --- /dev/null +++ b/common_smp/src/txe_byte_allocate.c @@ -0,0 +1,199 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Byte Memory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_timer.h" +#include "tx_byte_pool.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_byte_allocate PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in allocate bytes function call. */ +/* */ +/* INPUT */ +/* */ +/* pool_ptr Pointer to pool control block */ +/* memory_ptr Pointer to place allocated bytes */ +/* pointer */ +/* memory_size Number of bytes to allocate */ +/* wait_option Suspension option */ +/* */ +/* OUTPUT */ +/* */ +/* TX_POOL_ERROR Invalid memory pool pointer */ +/* TX_PTR_ERROR Invalid destination pointer */ +/* TX_WAIT_ERROR Invalid wait option */ +/* TX_CALLER_ERROR Invalid caller of this function */ +/* TX_SIZE_ERROR Invalid size of memory request */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_byte_allocate Actual byte allocate function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_byte_allocate(TX_BYTE_POOL *pool_ptr, VOID **memory_ptr, + ULONG memory_size, ULONG wait_option) +{ + +UINT status; +#ifndef TX_TIMER_PROCESS_IN_ISR +TX_THREAD *thread_ptr; +#endif + + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid byte pool pointer. */ + if (pool_ptr == TX_NULL) + { + + /* Byte pool pointer is invalid, return appropriate error code. */ + status = TX_POOL_ERROR; + } + + /* Now check for invalid pool ID. */ + else if (pool_ptr -> tx_byte_pool_id != TX_BYTE_POOL_ID) + { + + /* Byte pool pointer is invalid, return appropriate error code. */ + status = TX_POOL_ERROR; + } + + /* Check for an invalid destination for return pointer. */ + else if (memory_ptr == TX_NULL) + { + + /* Null destination pointer, return appropriate error. */ + status = TX_PTR_ERROR; + } + + /* Check for an invalid memory size. */ + else if (memory_size == ((ULONG) 0)) + { + + /* Error in size, return appropriate error. */ + status = TX_SIZE_ERROR; + } + + /* Determine if the size is greater than the pool size. */ + else if (memory_size > pool_ptr -> tx_byte_pool_size) + { + + /* Error in size, return appropriate error. */ + status = TX_SIZE_ERROR; + } + + else + { + + /* Check for a wait option error. Only threads are allowed any form of + suspension. */ + if (wait_option != TX_NO_WAIT) + { + + /* Is call from ISR or Initialization? */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + + /* A non-thread is trying to suspend, return appropriate error code. */ + status = TX_WAIT_ERROR; + } + } + } +#ifndef TX_TIMER_PROCESS_IN_ISR + + /* Check for timer execution. */ + if (status == TX_SUCCESS) + { + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr) + + /* Check for invalid caller of this function. First check for a calling thread. */ + if (thread_ptr == &_tx_timer_thread) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } +#endif + + /* Is everything still okay? */ + if (status == TX_SUCCESS) + { + + /* Check for interrupt call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + + /* Now, make sure the call is from an interrupt and not initialization. */ + if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + + /* Call actual byte memory allocate function. */ + status = _tx_byte_allocate(pool_ptr, memory_ptr, memory_size, wait_option); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_byte_pool_create.c b/common_smp/src/txe_byte_pool_create.c new file mode 100644 index 00000000..429d401c --- /dev/null +++ b/common_smp/src/txe_byte_pool_create.c @@ -0,0 +1,222 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Byte Pool */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_timer.h" +#include "tx_byte_pool.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_byte_pool_create PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the create byte pool memory */ +/* function. */ +/* */ +/* INPUT */ +/* */ +/* pool_ptr Pointer to pool control block */ +/* name_ptr Pointer to byte pool name */ +/* pool_start Address of beginning of pool area */ +/* pool_size Number of bytes in the byte pool */ +/* pool_control_block_size Size of byte pool control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_POOL_ERROR Invalid byte pool pointer */ +/* TX_PTR_ERROR Invalid pool starting address */ +/* TX_SIZE_ERROR Invalid pool size */ +/* TX_CALLER_ERROR Invalid caller of this function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_byte_pool_create Actual byte pool create function */ +/* _tx_thread_system_preempt_check Check for preemption */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_byte_pool_create(TX_BYTE_POOL *pool_ptr, CHAR *name_ptr, VOID *pool_start, ULONG pool_size, UINT pool_control_block_size) +{ + +TX_INTERRUPT_SAVE_AREA + +UINT status; +ULONG i; +TX_BYTE_POOL *next_pool; +#ifndef TX_TIMER_PROCESS_IN_ISR +TX_THREAD *thread_ptr; +#endif + + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid byte pool pointer. */ + if (pool_ptr == TX_NULL) + { + + /* Byte pool pointer is invalid, return appropriate error code. */ + status = TX_POOL_ERROR; + } + + /* Now see if the pool control block size is valid. */ + else if (pool_control_block_size != (sizeof(TX_BYTE_POOL))) + { + + /* Byte pool pointer is invalid, return appropriate error code. */ + status = TX_POOL_ERROR; + } + else + { + + /* Disable interrupts. */ + TX_DISABLE + + /* Increment the preempt disable flag. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Next see if it is already in the created list. */ + next_pool = _tx_byte_pool_created_ptr; + for (i = ((ULONG) 0); i < _tx_byte_pool_created_count; i++) + { + + /* Determine if this byte pool matches the pool in the list. */ + if (pool_ptr == next_pool) + { + + break; + } + else + { + + /* Move to the next pool. */ + next_pool = next_pool -> tx_byte_pool_created_next; + } + } + + /* Disable interrupts. */ + TX_DISABLE + + /* Decrement the preempt disable flag. */ + _tx_thread_preempt_disable--; + + /* Restore interrupts. */ + TX_RESTORE + + /* Check for preemption. */ + _tx_thread_system_preempt_check(); + + /* At this point, check to see if there is a duplicate pool. */ + if (pool_ptr == next_pool) + { + + /* Pool is already created, return appropriate error code. */ + status = TX_POOL_ERROR; + } + + /* Check for an invalid starting address. */ + else if (pool_start == TX_NULL) + { + + /* Null starting address pointer, return appropriate error. */ + status = TX_PTR_ERROR; + } + + /* Check for invalid pool size. */ + else if (pool_size < TX_BYTE_POOL_MIN) + { + + /* Pool not big enough, return appropriate error. */ + status = TX_SIZE_ERROR; + } + else + { + +#ifndef TX_TIMER_PROCESS_IN_ISR + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr) + + /* Check for invalid caller of this function. First check for a calling thread. */ + if (thread_ptr == &_tx_timer_thread) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } +#endif + + /* Check for interrupt call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + + /* Now, make sure the call is from an interrupt and not initialization. */ + if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + + /* Call actual byte pool create function. */ + status = _tx_byte_pool_create(pool_ptr, name_ptr, pool_start, pool_size); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_byte_pool_delete.c b/common_smp/src/txe_byte_pool_delete.c new file mode 100644 index 00000000..22d2a347 --- /dev/null +++ b/common_smp/src/txe_byte_pool_delete.c @@ -0,0 +1,144 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Byte Pool */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +#include "tx_byte_pool.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_byte_pool_delete PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the delete byte pool function */ +/* call. */ +/* */ +/* INPUT */ +/* */ +/* pool_ptr Pointer to pool control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_POOL_ERROR Invalid pool pointer */ +/* TX_CALLER_ERROR Invalid caller of this function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_byte_pool_delete Actual byte pool delete function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_byte_pool_delete(TX_BYTE_POOL *pool_ptr) +{ + +UINT status; +#ifndef TX_TIMER_PROCESS_IN_ISR +TX_THREAD *thread_ptr; +#endif + + +#ifndef TX_TIMER_PROCESS_IN_ISR + + /* Default status to success. */ + status = TX_SUCCESS; +#endif + + /* Check for an invalid byte pool pointer. */ + if (pool_ptr == TX_NULL) + { + + /* Byte pool pointer is invalid, return appropriate error code. */ + status = TX_POOL_ERROR; + } + + /* Now check the pool ID. */ + else if (pool_ptr -> tx_byte_pool_id != TX_BYTE_POOL_ID) + { + + /* Byte pool pointer is invalid, return appropriate error code. */ + status = TX_POOL_ERROR; + } + + /* Check for interrupt or initialization. */ + else if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + else + { + +#ifndef TX_TIMER_PROCESS_IN_ISR + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr) + + /* Check for invalid caller of this function. First check for a calling thread. */ + if (thread_ptr == &_tx_timer_thread) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { +#endif + + /* Call actual byte pool delete function. */ + status = _tx_byte_pool_delete(pool_ptr); + +#ifndef TX_TIMER_PROCESS_IN_ISR + } +#endif + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_byte_pool_info_get.c b/common_smp/src/txe_byte_pool_info_get.c new file mode 100644 index 00000000..d7d33391 --- /dev/null +++ b/common_smp/src/txe_byte_pool_info_get.c @@ -0,0 +1,113 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Byte Memory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_byte_pool.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_byte_pool_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the byte pool information get */ +/* service. */ +/* */ +/* INPUT */ +/* */ +/* pool_ptr Pointer to byte pool control block*/ +/* name Destination for the pool name */ +/* available_bytes Number of free bytes in byte pool */ +/* fragments Number of fragments in byte pool */ +/* first_suspended Destination for pointer of first */ +/* thread suspended on byte pool */ +/* suspended_count Destination for suspended count */ +/* next_pool Destination for pointer to next */ +/* byte pool on the created list */ +/* */ +/* OUTPUT */ +/* */ +/* TX_POOL_ERROR Invalid byte pool pointer */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_byte_pool_info_get Actual byte pool info get service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_byte_pool_info_get(TX_BYTE_POOL *pool_ptr, CHAR **name, ULONG *available_bytes, + ULONG *fragments, TX_THREAD **first_suspended, + ULONG *suspended_count, TX_BYTE_POOL **next_pool) +{ + +UINT status; + + + /* Check for an invalid byte pool pointer. */ + if (pool_ptr == TX_NULL) + { + + /* Block pool pointer is invalid, return appropriate error code. */ + status = TX_POOL_ERROR; + } + + /* Now check for invalid pool ID. */ + else if (pool_ptr -> tx_byte_pool_id != TX_BYTE_POOL_ID) + { + + /* Block pool pointer is invalid, return appropriate error code. */ + status = TX_POOL_ERROR; + } + else + { + + /* Otherwise, call the actual byte pool information get service. */ + status = _tx_byte_pool_info_get(pool_ptr, name, available_bytes, + fragments, first_suspended, suspended_count, next_pool); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_byte_pool_prioritize.c b/common_smp/src/txe_byte_pool_prioritize.c new file mode 100644 index 00000000..9eec66a0 --- /dev/null +++ b/common_smp/src/txe_byte_pool_prioritize.c @@ -0,0 +1,101 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Byte Memory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_byte_pool.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_byte_pool_prioritize PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the byte pool prioritize call. */ +/* */ +/* INPUT */ +/* */ +/* pool_ptr Pointer to pool control block */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_byte_pool_prioritize Actual byte pool prioritize */ +/* function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_byte_pool_prioritize(TX_BYTE_POOL *pool_ptr) +{ + +UINT status; + + + /* Check for an invalid byte memory pool pointer. */ + if (pool_ptr == TX_NULL) + { + + /* Byte pool pointer is invalid, return appropriate error code. */ + status = TX_POOL_ERROR; + } + + /* Now check for invalid pool ID. */ + else if (pool_ptr -> tx_byte_pool_id != TX_BYTE_POOL_ID) + { + + /* Byte pool pointer is invalid, return appropriate error code. */ + status = TX_POOL_ERROR; + } + else + { + + /* Call actual byte pool prioritize function. */ + status = _tx_byte_pool_prioritize(pool_ptr); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_byte_release.c b/common_smp/src/txe_byte_release.c new file mode 100644 index 00000000..3e83a83c --- /dev/null +++ b/common_smp/src/txe_byte_release.c @@ -0,0 +1,135 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Byte Memory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_timer.h" +#include "tx_byte_pool.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_byte_release PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the release byte function call. */ +/* */ +/* INPUT */ +/* */ +/* memory_ptr Pointer to allocated memory */ +/* */ +/* OUTPUT */ +/* */ +/* TX_PTR_ERROR Invalid memory pointer */ +/* TX_CALLER_ERROR Invalid caller of this function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_byte_release Actual byte release function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_byte_release(VOID *memory_ptr) +{ + +UINT status; +#ifndef TX_TIMER_PROCESS_IN_ISR +TX_THREAD *thread_ptr; +#endif + + + /* Default status to success. */ + status = TX_SUCCESS; + + /* First check the supplied memory pointer. */ + if (memory_ptr == TX_NULL) + { + + /* The byte memory pointer is invalid, return appropriate status. */ + status = TX_PTR_ERROR; + } + else + { + +#ifndef TX_TIMER_PROCESS_IN_ISR + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr) + + /* Check for invalid caller of this function. First check for a calling thread. */ + if (thread_ptr == &_tx_timer_thread) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } +#endif + + /* Check for interrupt call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + + /* Now, make sure the call is from an interrupt and not initialization. */ + if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + + /* Call actual byte release function. */ + status = _tx_byte_release(memory_ptr); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_event_flags_create.c b/common_smp/src/txe_event_flags_create.c new file mode 100644 index 00000000..4a0805c9 --- /dev/null +++ b/common_smp/src/txe_event_flags_create.c @@ -0,0 +1,203 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Event Flags */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_timer.h" +#include "tx_event_flags.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_event_flags_create PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the event flag creation function */ +/* call. */ +/* */ +/* INPUT */ +/* */ +/* group_ptr Pointer to event flags group */ +/* control block */ +/* name_ptr Pointer to event flags name */ +/* event_control_block_size Size of event flags control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_GROUP_ERROR Invalid event flag group pointer */ +/* TX_CALLER_ERROR Invalid calling function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_event_flags_create Actual create function */ +/* _tx_thread_system_preempt_check Check for preemption */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_event_flags_create(TX_EVENT_FLAGS_GROUP *group_ptr, CHAR *name_ptr, UINT event_control_block_size) +{ + +TX_INTERRUPT_SAVE_AREA + +UINT status; +ULONG i; +TX_EVENT_FLAGS_GROUP *next_group; +#ifndef TX_TIMER_PROCESS_IN_ISR +TX_THREAD *thread_ptr; +#endif + + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid event flags group pointer. */ + if (group_ptr == TX_NULL) + { + + /* Event flags group pointer is invalid, return appropriate error code. */ + status = TX_GROUP_ERROR; + } + + /* Now check for proper control block size. */ + else if (event_control_block_size != (sizeof(TX_EVENT_FLAGS_GROUP))) + { + + /* Event flags group pointer is invalid, return appropriate error code. */ + status = TX_GROUP_ERROR; + } + else + { + + /* Disable interrupts. */ + TX_DISABLE + + /* Increment the preempt disable flag. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Next see if it is already in the created list. */ + next_group = _tx_event_flags_created_ptr; + for (i = ((ULONG) 0); i < _tx_event_flags_created_count; i++) + { + + /* Determine if this group matches the event flags group in the list. */ + if (group_ptr == next_group) + { + + break; + } + else + { + + /* Move to the next group. */ + next_group = next_group -> tx_event_flags_group_created_next; + } + } + + /* Disable interrupts. */ + TX_DISABLE + + /* Decrement the preempt disable flag. */ + _tx_thread_preempt_disable--; + + /* Restore interrupts. */ + TX_RESTORE + + /* Check for preemption. */ + _tx_thread_system_preempt_check(); + + /* At this point, check to see if there is a duplicate event flag group. */ + if (group_ptr == next_group) + { + + /* Group is already created, return appropriate error code. */ + status = TX_GROUP_ERROR; + } + else + { + +#ifndef TX_TIMER_PROCESS_IN_ISR + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr) + + /* Check for invalid caller of this function. First check for a calling thread. */ + if (thread_ptr == &_tx_timer_thread) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } +#endif + + /* Check for interrupt call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + + /* Now, make sure the call is from an interrupt and not initialization. */ + if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + + /* Call actual event flags create function. */ + status = _tx_event_flags_create(group_ptr, name_ptr); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_event_flags_delete.c b/common_smp/src/txe_event_flags_delete.c new file mode 100644 index 00000000..ac3548e3 --- /dev/null +++ b/common_smp/src/txe_event_flags_delete.c @@ -0,0 +1,146 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Event Flags */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +#include "tx_event_flags.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_event_flags_delete PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the delete event flags group */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* group_ptr Pointer to group control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_GROUP_ERROR Invalid event flag group pointer */ +/* TX_CALLER_ERROR Invalid caller of this function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_event_flags_delete Actual delete event flags function*/ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_event_flags_delete(TX_EVENT_FLAGS_GROUP *group_ptr) +{ + +UINT status; +#ifndef TX_TIMER_PROCESS_IN_ISR +TX_THREAD *thread_ptr; +#endif + + +#ifndef TX_TIMER_PROCESS_IN_ISR + + /* Default status to success. */ + status = TX_SUCCESS; +#endif + + /* Check for an invalid event flag group pointer. */ + if (group_ptr == TX_NULL) + { + + /* Event flags group pointer is invalid, return appropriate error code. */ + status = TX_GROUP_ERROR; + } + + /* Now check for invalid event flag group ID. */ + else if (group_ptr -> tx_event_flags_group_id != TX_EVENT_FLAGS_ID) + { + + /* Event flags group pointer is invalid, return appropriate error code. */ + status = TX_GROUP_ERROR; + } + + /* Check for invalid caller of this function. */ + + /* Is the caller an ISR or Initialization? */ + else if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + else + { + +#ifndef TX_TIMER_PROCESS_IN_ISR + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr) + + /* Is the caller the system timer thread? */ + if (thread_ptr == &_tx_timer_thread) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { +#endif + + /* Call actual event flag group delete function. */ + status = _tx_event_flags_delete(group_ptr); + +#ifndef TX_TIMER_PROCESS_IN_ISR + } +#endif + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_event_flags_get.c b/common_smp/src/txe_event_flags_get.c new file mode 100644 index 00000000..45aa735f --- /dev/null +++ b/common_smp/src/txe_event_flags_get.c @@ -0,0 +1,177 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Event Flags */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +#include "tx_event_flags.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_event_flags_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the event flags get function */ +/* call. */ +/* */ +/* INPUT */ +/* */ +/* group_ptr Pointer to group control block */ +/* requested_event_flags Event flags requested */ +/* get_option Specifies and/or and clear options*/ +/* actual_flags_ptr Pointer to place the actual flags */ +/* the service retrieved */ +/* wait_option Suspension option */ +/* */ +/* OUTPUT */ +/* */ +/* TX_GROUP_ERROR Invalid event flags group pointer */ +/* TX_PTR_ERROR Invalid actual flags pointer */ +/* TX_WAIT_ERROR Invalid wait option */ +/* TX_OPTION_ERROR Invalid get option */ +/* TX_CALLER_ERROR Invalid caller of this function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_event_flags_get Actual event flags get function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_event_flags_get(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG requested_flags, + UINT get_option, ULONG *actual_flags_ptr, ULONG wait_option) +{ + +UINT status; + +#ifndef TX_TIMER_PROCESS_IN_ISR +TX_THREAD *current_thread; +#endif + + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid event flag group pointer. */ + if (group_ptr == TX_NULL) + { + + /* Event flags group pointer is invalid, return appropriate error code. */ + status = TX_GROUP_ERROR; + } + + /* Now check for invalid event group ID. */ + else if (group_ptr -> tx_event_flags_group_id != TX_EVENT_FLAGS_ID) + { + + /* Event flags group pointer is invalid, return appropriate error code. */ + status = TX_GROUP_ERROR; + } + + /* Check for an invalid destination for actual flags. */ + else if (actual_flags_ptr == TX_NULL) + { + + /* Null destination pointer, return appropriate error. */ + status = TX_PTR_ERROR; + } + else + { + + /* Check for a wait option error. Only threads are allowed any form of + suspension. */ + if (wait_option != TX_NO_WAIT) + { + + /* Is the call from an ISR or Initialization? */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + + /* A non-thread is trying to suspend, return appropriate error code. */ + status = TX_WAIT_ERROR; + } +#ifndef TX_TIMER_PROCESS_IN_ISR + else + { + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(current_thread) + + /* Is the current thread the timer thread? */ + if (current_thread == &_tx_timer_thread) + { + + /* A non-thread is trying to suspend, return appropriate error code. */ + status = TX_WAIT_ERROR; + } + } +#endif + } + } + + /* Is everything still okay? */ + if (status == TX_SUCCESS) + { + + /* Check for invalid get option. */ + if (get_option > TX_AND_CLEAR) + { + + /* Invalid get events option, return appropriate error. */ + status = TX_OPTION_ERROR; + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + + /* Call actual event flags get function. */ + status = _tx_event_flags_get(group_ptr, requested_flags, get_option, actual_flags_ptr, wait_option); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_event_flags_info_get.c b/common_smp/src/txe_event_flags_info_get.c new file mode 100644 index 00000000..111da89e --- /dev/null +++ b/common_smp/src/txe_event_flags_info_get.c @@ -0,0 +1,115 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Event Flags */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_event_flags.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_event_flags_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the event flag information get */ +/* service. */ +/* */ +/* INPUT */ +/* */ +/* group_ptr Pointer to event flag group */ +/* name Destination for the event flags */ +/* group name */ +/* current_flags Current event flags */ +/* first_suspended Destination for pointer of first */ +/* thread suspended on event flags */ +/* suspended_count Destination for suspended count */ +/* next_group Destination for pointer to next */ +/* event flag group on the created */ +/* list */ +/* */ +/* OUTPUT */ +/* */ +/* TX_GROUP_ERROR Invalid event flag group pointer */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_event_flags_info_get Actual event flags group info */ +/* get service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_event_flags_info_get(TX_EVENT_FLAGS_GROUP *group_ptr, CHAR **name, ULONG *current_flags, + TX_THREAD **first_suspended, ULONG *suspended_count, + TX_EVENT_FLAGS_GROUP **next_group) +{ + +UINT status; + + + /* Check for an invalid event flag group pointer. */ + if (group_ptr == TX_NULL) + { + + /* Event flags group pointer is invalid, return appropriate error code. */ + status = TX_GROUP_ERROR; + } + + /* Now check for invalid event flag group ID. */ + else if (group_ptr -> tx_event_flags_group_id != TX_EVENT_FLAGS_ID) + { + + /* Event flags group pointer is invalid, return appropriate error code. */ + status = TX_GROUP_ERROR; + } + else + { + + /* Otherwise, call the actual event flags group information get service. */ + status = _tx_event_flags_info_get(group_ptr, name, current_flags, first_suspended, + suspended_count, next_group); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_event_flags_set.c b/common_smp/src/txe_event_flags_set.c new file mode 100644 index 00000000..a4a4b5e9 --- /dev/null +++ b/common_smp/src/txe_event_flags_set.c @@ -0,0 +1,126 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Event Flags */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_event_flags.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_event_flags_set PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the set event flags function */ +/* call. */ +/* */ +/* INPUT */ +/* */ +/* group_ptr Pointer to group control block */ +/* flags_to_set Event flags to set */ +/* set_option Specified either AND or OR */ +/* operation on the event flags */ +/* */ +/* OUTPUT */ +/* */ +/* TX_GROUP_ERROR Invalid event flags group pointer */ +/* TX_OPTION_ERROR Invalid set option */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_event_flags_set Actual set event flags function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_event_flags_set(TX_EVENT_FLAGS_GROUP *group_ptr, ULONG flags_to_set, UINT set_option) +{ + +UINT status; + + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid event flag group pointer. */ + if (group_ptr == TX_NULL) + { + + /* Event flags group pointer is invalid, return appropriate error code. */ + status = TX_GROUP_ERROR; + } + + /* Now check for invalid event flag group ID. */ + else if (group_ptr -> tx_event_flags_group_id != TX_EVENT_FLAGS_ID) + { + + /* Event flags group pointer is invalid, return appropriate error code. */ + status = TX_GROUP_ERROR; + } + else + { + + /* Check for invalid set option. */ + if (set_option != TX_AND) + { + + if (set_option != TX_OR) + { + + /* Invalid set events option, return appropriate error. */ + status = TX_OPTION_ERROR; + } + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + + /* Call actual event flags set function. */ + status = _tx_event_flags_set(group_ptr, flags_to_set, set_option); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_event_flags_set_notify.c b/common_smp/src/txe_event_flags_set_notify.c new file mode 100644 index 00000000..84f7fc3c --- /dev/null +++ b/common_smp/src/txe_event_flags_set_notify.c @@ -0,0 +1,104 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Event Flags */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_event_flags.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_event_flags_set_notify PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the event flags set notify */ +/* callback function call. */ +/* */ +/* INPUT */ +/* */ +/* group_ptr Pointer to group control block*/ +/* group_put_notify Application callback function */ +/* (TX_NULL disables notify) */ +/* */ +/* OUTPUT */ +/* */ +/* status Service return status */ +/* */ +/* CALLS */ +/* */ +/* _tx_event_flags_set_notify Actual event flags set notify */ +/* call */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_event_flags_set_notify(TX_EVENT_FLAGS_GROUP *group_ptr, VOID (*events_set_notify)(TX_EVENT_FLAGS_GROUP *notify_group_ptr)) +{ + +UINT status; + + + /* Check for an invalid group pointer. */ + if (group_ptr == TX_NULL) + { + + /* Event flags group pointer is invalid, return appropriate error code. */ + status = TX_GROUP_ERROR; + } + + /* Now check for invalid event group ID. */ + else if (group_ptr -> tx_event_flags_group_id != TX_EVENT_FLAGS_ID) + { + + /* Event flags group pointer is invalid, return appropriate error code. */ + status = TX_GROUP_ERROR; + } + else + { + + /* Call actual event flags set notify function. */ + status = _tx_event_flags_set_notify(group_ptr, events_set_notify); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_mutex_create.c b/common_smp/src/txe_mutex_create.c new file mode 100644 index 00000000..18f8ca9c --- /dev/null +++ b/common_smp/src/txe_mutex_create.c @@ -0,0 +1,221 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Mutex */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_timer.h" +#include "tx_mutex.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_mutex_create PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the create mutex function */ +/* call. */ +/* */ +/* INPUT */ +/* */ +/* mutex_ptr Pointer to mutex control block */ +/* name_ptr Pointer to mutex name */ +/* inherit Initial mutex count */ +/* mutex_control_block_size Size of mutex control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_MUTEX_ERROR Invalid mutex pointer */ +/* TX_CALLER_ERROR Invalid caller of this function */ +/* TX_INHERIT_ERROR Invalid inherit option */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_mutex_create Actual create mutex function */ +/* _tx_thread_system_preempt_check Check for preemption */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_mutex_create(TX_MUTEX *mutex_ptr, CHAR *name_ptr, UINT inherit, UINT mutex_control_block_size) +{ + +TX_INTERRUPT_SAVE_AREA + +UINT status; +ULONG i; +TX_MUTEX *next_mutex; +#ifndef TX_TIMER_PROCESS_IN_ISR +TX_THREAD *thread_ptr; +#endif + + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid mutex pointer. */ + if (mutex_ptr == TX_NULL) + { + + /* Mutex pointer is invalid, return appropriate error code. */ + status = TX_MUTEX_ERROR; + } + + /* Now check to make sure the control block is the correct size. */ + else if (mutex_control_block_size != (sizeof(TX_MUTEX))) + { + + /* Mutex pointer is invalid, return appropriate error code. */ + status = TX_MUTEX_ERROR; + } + else + { + + /* Disable interrupts. */ + TX_DISABLE + + /* Increment the preempt disable flag. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Next see if it is already in the created list. */ + next_mutex = _tx_mutex_created_ptr; + for (i = ((ULONG) 0); i < _tx_mutex_created_count; i++) + { + + /* Determine if this mutex matches the mutex in the list. */ + if (mutex_ptr == next_mutex) + { + + break; + } + else + { + + /* Move to the next mutex. */ + next_mutex = next_mutex -> tx_mutex_created_next; + } + } + + /* Disable interrupts. */ + TX_DISABLE + + /* Decrement the preempt disable flag. */ + _tx_thread_preempt_disable--; + + /* Restore interrupts. */ + TX_RESTORE + + /* Check for preemption. */ + _tx_thread_system_preempt_check(); + + /* At this point, check to see if there is a duplicate mutex. */ + if (mutex_ptr == next_mutex) + { + + /* Mutex is already created, return appropriate error code. */ + status = TX_MUTEX_ERROR; + } + else + { + + /* Check for a valid inherit option. */ + if (inherit != TX_INHERIT) + { + + if (inherit != TX_NO_INHERIT) + { + + /* Inherit option is illegal. */ + status = TX_INHERIT_ERROR; + } + } + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + +#ifndef TX_TIMER_PROCESS_IN_ISR + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr) + + /* Check for invalid caller of this function. First check for a calling thread. */ + if (thread_ptr == &_tx_timer_thread) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } +#endif + + /* Check for interrupt call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + + /* Now, make sure the call is from an interrupt and not initialization. */ + if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + + /* Call actual mutex create function. */ + status = _tx_mutex_create(mutex_ptr, name_ptr, inherit); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_mutex_delete.c b/common_smp/src/txe_mutex_delete.c new file mode 100644 index 00000000..83b6df14 --- /dev/null +++ b/common_smp/src/txe_mutex_delete.c @@ -0,0 +1,146 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Mutex */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +#include "tx_mutex.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_mutex_delete PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the mutex delete function */ +/* call. */ +/* */ +/* INPUT */ +/* */ +/* mutex_ptr Pointer to mutex control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_MUTEX_ERROR Invalid mutex pointer */ +/* TX_CALLER_ERROR Invalid caller of this function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_mutex_delete Actual delete mutex function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_mutex_delete(TX_MUTEX *mutex_ptr) +{ + +UINT status; +#ifndef TX_TIMER_PROCESS_IN_ISR +TX_THREAD *thread_ptr; +#endif + + +#ifndef TX_TIMER_PROCESS_IN_ISR + + /* Default status to success. */ + status = TX_SUCCESS; +#endif + + /* Check for an invalid mutex pointer. */ + if (mutex_ptr == TX_NULL) + { + + /* Mutex pointer is invalid, return appropriate error code. */ + status = TX_MUTEX_ERROR; + } + + /* Now check for a valid mutex ID. */ + else if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Mutex pointer is invalid, return appropriate error code. */ + status = TX_MUTEX_ERROR; + } + + /* Check for invalid caller of this function. */ + + /* Is the caller an ISR or Initialization? */ + else if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + else + { + +#ifndef TX_TIMER_PROCESS_IN_ISR + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr) + + /* Is the caller the system timer thread? */ + if (thread_ptr == &_tx_timer_thread) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { +#endif + + /* Call actual mutex delete function. */ + status = _tx_mutex_delete(mutex_ptr); + +#ifndef TX_TIMER_PROCESS_IN_ISR + } +#endif + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_mutex_get.c b/common_smp/src/txe_mutex_get.c new file mode 100644 index 00000000..b4fe3b8b --- /dev/null +++ b/common_smp/src/txe_mutex_get.c @@ -0,0 +1,168 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Mutex */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#ifndef TX_TIMER_PROCESS_IN_ISR +#include "tx_timer.h" +#endif +#include "tx_mutex.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_mutex_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the mutex get function call. */ +/* */ +/* INPUT */ +/* */ +/* mutex_ptr Pointer to mutex control block */ +/* wait_option Suspension option */ +/* */ +/* OUTPUT */ +/* */ +/* TX_MUTEX_ERROR Invalid mutex pointer */ +/* TX_WAIT_ERROR Invalid wait option */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_mutex_get Actual get mutex function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_mutex_get(TX_MUTEX *mutex_ptr, ULONG wait_option) +{ + +UINT status; +#ifndef TX_TIMER_PROCESS_IN_ISR +TX_THREAD *current_thread; +#endif + + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid mutex pointer. */ + if (mutex_ptr == TX_NULL) + { + + /* Mutex pointer is invalid, return appropriate error code. */ + status = TX_MUTEX_ERROR; + } + + /* Now check for a valid mutex ID. */ + else if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Mutex pointer is invalid, return appropriate error code. */ + status = TX_MUTEX_ERROR; + } + else + { + + /* Check for a wait option error. Only threads are allowed any form of + suspension. */ + if (wait_option != TX_NO_WAIT) + { + + /* Is the call from an ISR or Initialization? */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + + /* A non-thread is trying to suspend, return appropriate error code. */ + status = TX_WAIT_ERROR; + } + +#ifndef TX_TIMER_PROCESS_IN_ISR + else + { + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(current_thread) + + /* Is the current thread the timer thread? */ + if (current_thread == &_tx_timer_thread) + { + + /* A non-thread is trying to suspend, return appropriate error code. */ + status = TX_WAIT_ERROR; + } + } +#endif + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + + /* Check for interrupt call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + + /* Now, make sure the call is from an interrupt and not initialization. */ + if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS) + { + + /* Yes, invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + + /* Call actual get mutex function. */ + status = _tx_mutex_get(mutex_ptr, wait_option); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_mutex_info_get.c b/common_smp/src/txe_mutex_info_get.c new file mode 100644 index 00000000..5b27cafd --- /dev/null +++ b/common_smp/src/txe_mutex_info_get.c @@ -0,0 +1,114 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Mutex */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_mutex.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_mutex_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the mutex information get */ +/* service. */ +/* */ +/* INPUT */ +/* */ +/* mutex_ptr Pointer to mutex control block */ +/* name Destination for the mutex name */ +/* count Destination for the owner count */ +/* owner Destination for the owner's */ +/* thread control block pointer */ +/* first_suspended Destination for pointer of first */ +/* thread suspended on the mutex */ +/* suspended_count Destination for suspended count */ +/* next_mutex Destination for pointer to next */ +/* mutex on the created list */ +/* */ +/* OUTPUT */ +/* */ +/* TX_MUTEX_ERROR Invalid mutex pointer */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_mutex_info_get Actual mutex info get service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_mutex_info_get(TX_MUTEX *mutex_ptr, CHAR **name, ULONG *count, TX_THREAD **owner, + TX_THREAD **first_suspended, ULONG *suspended_count, + TX_MUTEX **next_mutex) +{ + +UINT status; + + + /* Check for an invalid mutex pointer. */ + if (mutex_ptr == TX_NULL) + { + + /* Mutex pointer is invalid, return appropriate error code. */ + status = TX_MUTEX_ERROR; + } + + /* Now check for invalid mutex ID. */ + else if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Mutex pointer is invalid, return appropriate error code. */ + status = TX_MUTEX_ERROR; + } + else + { + + /* Otherwise, call the actual mutex information get service. */ + status = _tx_mutex_info_get(mutex_ptr, name, count, owner, first_suspended, + suspended_count, next_mutex); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_mutex_prioritize.c b/common_smp/src/txe_mutex_prioritize.c new file mode 100644 index 00000000..e7bdc24a --- /dev/null +++ b/common_smp/src/txe_mutex_prioritize.c @@ -0,0 +1,101 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Mutex */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_mutex.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_mutex_prioritize PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the mutex prioritize call. */ +/* */ +/* INPUT */ +/* */ +/* mutex_ptr Pointer to mutex control block */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_mutex_prioritize Actual mutex prioritize */ +/* function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_mutex_prioritize(TX_MUTEX *mutex_ptr) +{ + +UINT status; + + + /* Check for an invalid mutex pointer. */ + if (mutex_ptr == TX_NULL) + { + + /* Mutex pointer is invalid, return appropriate error code. */ + status = TX_MUTEX_ERROR; + } + + /* Now check for invalid mutex ID. */ + else if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Mutex pointer is invalid, return appropriate error code. */ + status = TX_MUTEX_ERROR; + } + else + { + + /* Call actual mutex prioritize function. */ + status = _tx_mutex_prioritize(mutex_ptr); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_mutex_put.c b/common_smp/src/txe_mutex_put.c new file mode 100644 index 00000000..2f4e9712 --- /dev/null +++ b/common_smp/src/txe_mutex_put.c @@ -0,0 +1,124 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Mutex */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_mutex.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_mutex_put PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the mutex put function call. */ +/* */ +/* INPUT */ +/* */ +/* mutex_ptr Pointer to mutex control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_MUTEX_ERROR Invalid mutex pointer */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_mutex_put Actual put mutex function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_mutex_put(TX_MUTEX *mutex_ptr) +{ + +UINT status; + + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid mutex pointer. */ + if (mutex_ptr == TX_NULL) + { + + /* Mutex pointer is invalid, return appropriate error code. */ + status = TX_MUTEX_ERROR; + } + + /* Now check for invalid mutex ID. */ + else if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Mutex pointer is invalid, return appropriate error code. */ + status = TX_MUTEX_ERROR; + } + else + { + + /* Check for interrupt call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + + /* Now, make sure the call is from an interrupt and not initialization. */ + if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + + /* Call actual put mutex function. */ + status = _tx_mutex_put(mutex_ptr); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_queue_create.c b/common_smp/src/txe_queue_create.c new file mode 100644 index 00000000..5cd7e0ee --- /dev/null +++ b/common_smp/src/txe_queue_create.c @@ -0,0 +1,237 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Queue */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_timer.h" +#include "tx_thread.h" +#include "tx_queue.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_queue_create PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the queue create function call. */ +/* */ +/* INPUT */ +/* */ +/* queue_ptr Pointer to queue control block */ +/* name_ptr Pointer to queue name */ +/* message_size Size of each queue message */ +/* queue_start Starting address of the queue area*/ +/* queue_size Number of bytes in the queue */ +/* queue_control_block_size Size of queue control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_QUEUE_ERROR Invalid queue pointer */ +/* TX_PTR_ERROR Invalid starting address of queue */ +/* TX_SIZE_ERROR Invalid message queue size */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_queue_create Actual queue create function */ +/* _tx_thread_system_preempt_check Check for preemption */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_queue_create(TX_QUEUE *queue_ptr, CHAR *name_ptr, UINT message_size, + VOID *queue_start, ULONG queue_size, UINT queue_control_block_size) +{ + +TX_INTERRUPT_SAVE_AREA + +UINT status; +ULONG i; +TX_QUEUE *next_queue; +#ifndef TX_TIMER_PROCESS_IN_ISR +TX_THREAD *thread_ptr; +#endif + + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid queue pointer. */ + if (queue_ptr == TX_NULL) + { + + /* Queue pointer is invalid, return appropriate error code. */ + status = TX_QUEUE_ERROR; + } + + /* Now check for a valid control block size. */ + else if (queue_control_block_size != (sizeof(TX_QUEUE))) + { + + /* Queue pointer is invalid, return appropriate error code. */ + status = TX_QUEUE_ERROR; + } + else + { + + /* Disable interrupts. */ + TX_DISABLE + + /* Increment the preempt disable flag. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Next see if it is already in the created list. */ + next_queue = _tx_queue_created_ptr; + for (i = ((ULONG) 0); i < _tx_queue_created_count; i++) + { + + /* Determine if this queue matches the queue in the list. */ + if (queue_ptr == next_queue) + { + + break; + } + else + { + + /* Move to the next queue. */ + next_queue = next_queue -> tx_queue_created_next; + } + } + + /* Disable interrupts. */ + TX_DISABLE + + /* Decrement the preempt disable flag. */ + _tx_thread_preempt_disable--; + + /* Restore interrupts. */ + TX_RESTORE + + /* Check for preemption. */ + _tx_thread_system_preempt_check(); + + /* At this point, check to see if there is a duplicate queue. */ + if (queue_ptr == next_queue) + { + + /* Queue is already created, return appropriate error code. */ + status = TX_QUEUE_ERROR; + } + + /* Check the starting address of the queue. */ + else if (queue_start == TX_NULL) + { + + /* Invalid starting address of queue. */ + status = TX_PTR_ERROR; + } + + /* Check for an invalid message size - less than 1. */ + else if (message_size < TX_1_ULONG) + { + + /* Invalid message size specified. */ + status = TX_SIZE_ERROR; + } + + /* Check for an invalid message size - greater than 16. */ + else if (message_size > TX_16_ULONG) + { + + /* Invalid message size specified. */ + status = TX_SIZE_ERROR; + } + + /* Check on the queue size. */ + else if ((queue_size/(sizeof(ULONG))) < message_size) + { + + /* Invalid queue size specified. */ + status = TX_SIZE_ERROR; + } + else + { + +#ifndef TX_TIMER_PROCESS_IN_ISR + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr) + + /* Check for invalid caller of this function. First check for a calling thread. */ + if (thread_ptr == &_tx_timer_thread) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } +#endif + + /* Check for interrupt call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + + /* Now, make sure the call is from an interrupt and not initialization. */ + if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + + /* Call actual queue create function. */ + status = _tx_queue_create(queue_ptr, name_ptr, message_size, queue_start, queue_size); + } + + /* Return completion status. */ + return(status); +} diff --git a/common_smp/src/txe_queue_delete.c b/common_smp/src/txe_queue_delete.c new file mode 100644 index 00000000..32b730d5 --- /dev/null +++ b/common_smp/src/txe_queue_delete.c @@ -0,0 +1,142 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Queue */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_timer.h" +#include "tx_thread.h" +#include "tx_queue.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_queue_delete PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the queue delete function call. */ +/* */ +/* INPUT */ +/* */ +/* queue_ptr Pointer to queue control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_QUEUE_ERROR Invalid queue pointer */ +/* TX_CALLER_ERROR Invalid caller of this function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_queue_delete Actual queue delete function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_queue_delete(TX_QUEUE *queue_ptr) +{ + +UINT status; +#ifndef TX_TIMER_PROCESS_IN_ISR +TX_THREAD *thread_ptr; +#endif + + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid queue pointer. */ + if (queue_ptr == TX_NULL) + { + + /* Queue pointer is invalid, return appropriate error code. */ + status = TX_QUEUE_ERROR; + } + + /* Now check for a valid queue ID. */ + else if (queue_ptr -> tx_queue_id != TX_QUEUE_ID) + { + + /* Queue pointer is invalid, return appropriate error code. */ + status = TX_QUEUE_ERROR; + } + else + { + + /* Check for invalid caller of this function. */ + + /* Is the caller an ISR or Initialization? */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + +#ifndef TX_TIMER_PROCESS_IN_ISR + else + { + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr) + + /* Is the caller the system timer thread? */ + if (thread_ptr == &_tx_timer_thread) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } +#endif + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + + /* Call actual queue delete function. */ + status = _tx_queue_delete(queue_ptr); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_queue_flush.c b/common_smp/src/txe_queue_flush.c new file mode 100644 index 00000000..ad7be5f1 --- /dev/null +++ b/common_smp/src/txe_queue_flush.c @@ -0,0 +1,102 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Queue */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_queue.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_queue_flush PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the queue flush function call. */ +/* */ +/* INPUT */ +/* */ +/* queue_ptr Pointer to queue control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_QUEUE_ERROR Invalid queue pointer */ +/* TX_CALLER_ERROR Invalid caller of this function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_queue_flush Actual queue flush function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_queue_flush(TX_QUEUE *queue_ptr) +{ + +UINT status; + + + /* Check for an invalid queue pointer. */ + if (queue_ptr == TX_NULL) + { + + /* Queue pointer is invalid, return appropriate error code. */ + status = TX_QUEUE_ERROR; + } + + /* Now check for invalid queue ID. */ + else if (queue_ptr -> tx_queue_id != TX_QUEUE_ID) + { + + /* Queue pointer is invalid, return appropriate error code. */ + status = TX_QUEUE_ERROR; + } + else + { + + /* Call actual queue flush function. */ + status = _tx_queue_flush(queue_ptr); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_queue_front_send.c b/common_smp/src/txe_queue_front_send.c new file mode 100644 index 00000000..e9b6d4a4 --- /dev/null +++ b/common_smp/src/txe_queue_front_send.c @@ -0,0 +1,158 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Queue */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_timer.h" +#include "tx_thread.h" +#include "tx_queue.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_queue_front_send PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the queue send function call. */ +/* */ +/* INPUT */ +/* */ +/* queue_ptr Pointer to queue control block */ +/* source_ptr Pointer to message source */ +/* wait_option Suspension option */ +/* */ +/* OUTPUT */ +/* */ +/* TX_QUEUE_ERROR Invalid queue pointer */ +/* TX_PTR_ERROR Invalid source pointer - NULL */ +/* TX_WAIT_ERROR Invalid wait option - non thread */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_queue_front_send Actual queue send function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_queue_front_send(TX_QUEUE *queue_ptr, VOID *source_ptr, ULONG wait_option) +{ + +UINT status; + +#ifndef TX_TIMER_PROCESS_IN_ISR +TX_THREAD *current_thread; +#endif + + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid queue pointer. */ + if (queue_ptr == TX_NULL) + { + + /* Queue pointer is invalid, return appropriate error code. */ + status = TX_QUEUE_ERROR; + } + + /* Now check for invalid queue ID. */ + else if (queue_ptr -> tx_queue_id != TX_QUEUE_ID) + { + + /* Queue pointer is invalid, return appropriate error code. */ + status = TX_QUEUE_ERROR; + } + + /* Check for an invalid source for message. */ + else if (source_ptr == TX_NULL) + { + + /* Null source pointer, return appropriate error. */ + status = TX_PTR_ERROR; + } + else + { + + /* Check for a wait option error. Only threads are allowed any form of + suspension. */ + if (wait_option != TX_NO_WAIT) + { + + /* Is the call from an ISR or Initialization? */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + + /* A non-thread is trying to suspend, return appropriate error code. */ + status = TX_WAIT_ERROR; + } + +#ifndef TX_TIMER_PROCESS_IN_ISR + else + { + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(current_thread) + + /* Is the current thread the timer thread? */ + if (current_thread == &_tx_timer_thread) + { + + /* A non-thread is trying to suspend, return appropriate error code. */ + status = TX_WAIT_ERROR; + } + } +#endif + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + + /* Call actual queue front send function. */ + status = _tx_queue_front_send(queue_ptr, source_ptr, wait_option); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_queue_info_get.c b/common_smp/src/txe_queue_info_get.c new file mode 100644 index 00000000..2616749c --- /dev/null +++ b/common_smp/src/txe_queue_info_get.c @@ -0,0 +1,112 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Queue */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_queue.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_queue_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the queue information get */ +/* service. */ +/* */ +/* INPUT */ +/* */ +/* queue_ptr Pointer to queue control block */ +/* name Destination for the queue name */ +/* enqueued Destination for enqueued count */ +/* available_storage Destination for available storage */ +/* first_suspended Destination for pointer of first */ +/* thread suspended on this queue */ +/* suspended_count Destination for suspended count */ +/* next_queue Destination for pointer to next */ +/* queue on the created list */ +/* */ +/* OUTPUT */ +/* */ +/* TX_QUEUE_ERROR Invalid queue pointer */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_queue_info_get Actual information get service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_queue_info_get(TX_QUEUE *queue_ptr, CHAR **name, ULONG *enqueued, ULONG *available_storage, + TX_THREAD **first_suspended, ULONG *suspended_count, TX_QUEUE **next_queue) +{ + +UINT status; + + + /* Check for an invalid queue pointer. */ + if (queue_ptr == TX_NULL) + { + + /* Queue pointer is invalid, return appropriate error code. */ + status = TX_QUEUE_ERROR; + } + + /* Now check for a valid queue ID. */ + else if (queue_ptr -> tx_queue_id != TX_QUEUE_ID) + { + + /* Queue pointer is invalid, return appropriate error code. */ + status = TX_QUEUE_ERROR; + } + else + { + + /* Otherwise, call the actual queue information get service. */ + status = _tx_queue_info_get(queue_ptr, name, enqueued, available_storage, first_suspended, + suspended_count, next_queue); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_queue_prioritize.c b/common_smp/src/txe_queue_prioritize.c new file mode 100644 index 00000000..82e83b4c --- /dev/null +++ b/common_smp/src/txe_queue_prioritize.c @@ -0,0 +1,98 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Queue */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_queue.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_queue_prioritize PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the queue prioritize call. */ +/* */ +/* INPUT */ +/* */ +/* queue_ptr Pointer to queue control block */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_queue_prioritize Actual queue prioritize function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_queue_prioritize(TX_QUEUE *queue_ptr) +{ + +UINT status; + + + /* Check for an invalid queue pointer. */ + if (queue_ptr == TX_NULL) + { + /* Queue pointer is invalid, return appropriate error code. */ + status = TX_QUEUE_ERROR; + } + + /* Now check for invalid queue ID. */ + else if (queue_ptr -> tx_queue_id != TX_QUEUE_ID) + { + /* Queue pointer is invalid, return appropriate error code. */ + status = TX_QUEUE_ERROR; + } + else + { + + /* Call actual queue prioritize function. */ + status = _tx_queue_prioritize(queue_ptr); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_queue_receive.c b/common_smp/src/txe_queue_receive.c new file mode 100644 index 00000000..80f0f36d --- /dev/null +++ b/common_smp/src/txe_queue_receive.c @@ -0,0 +1,160 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Queue */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_timer.h" +#include "tx_thread.h" +#include "tx_queue.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_queue_receive PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the queue receive function call. */ +/* */ +/* INPUT */ +/* */ +/* queue_ptr Pointer to queue control block */ +/* destination_ptr Pointer to message destination */ +/* **** MUST BE LARGE ENOUGH TO */ +/* HOLD MESSAGE **** */ +/* wait_option Suspension option */ +/* */ +/* OUTPUT */ +/* */ +/* TX_QUEUE_ERROR Invalid queue pointer */ +/* TX_PTR_ERROR Invalid destination pointer (NULL)*/ +/* TX_WAIT_ERROR Invalid wait option */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_queue_receive Actual queue receive function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_queue_receive(TX_QUEUE *queue_ptr, VOID *destination_ptr, ULONG wait_option) +{ + +UINT status; + +#ifndef TX_TIMER_PROCESS_IN_ISR +TX_THREAD *current_thread; +#endif + + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid queue pointer. */ + if (queue_ptr == TX_NULL) + { + + /* Queue pointer is invalid, return appropriate error code. */ + status = TX_QUEUE_ERROR; + } + + /* Now check for invalid queue ID. */ + else if (queue_ptr -> tx_queue_id != TX_QUEUE_ID) + { + + /* Queue pointer is invalid, return appropriate error code. */ + status = TX_QUEUE_ERROR; + } + + /* Check for an invalid destination for message. */ + else if (destination_ptr == TX_NULL) + { + + /* Null destination pointer, return appropriate error. */ + status = TX_PTR_ERROR; + } + else + { + + /* Check for a wait option error. Only threads are allowed any form of + suspension. */ + if (wait_option != TX_NO_WAIT) + { + + /* Is the call from an ISR or Initialization? */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + + /* A non-thread is trying to suspend, return appropriate error code. */ + status = TX_WAIT_ERROR; + } + +#ifndef TX_TIMER_PROCESS_IN_ISR + else + { + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(current_thread) + + /* Is the current thread the timer thread? */ + if (current_thread == &_tx_timer_thread) + { + + /* A non-thread is trying to suspend, return appropriate error code. */ + status = TX_WAIT_ERROR; + } + } +#endif + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + + /* Call actual queue receive function. */ + status = _tx_queue_receive(queue_ptr, destination_ptr, wait_option); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_queue_send.c b/common_smp/src/txe_queue_send.c new file mode 100644 index 00000000..dc3f258a --- /dev/null +++ b/common_smp/src/txe_queue_send.c @@ -0,0 +1,158 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Queue */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_timer.h" +#include "tx_thread.h" +#include "tx_queue.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_queue_send PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the queue send function call. */ +/* */ +/* INPUT */ +/* */ +/* queue_ptr Pointer to queue control block */ +/* source_ptr Pointer to message source */ +/* wait_option Suspension option */ +/* */ +/* OUTPUT */ +/* */ +/* TX_QUEUE_ERROR Invalid queue pointer */ +/* TX_PTR_ERROR Invalid source pointer - NULL */ +/* TX_WAIT_ERROR Invalid wait option */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_queue_send Actual queue send function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_queue_send(TX_QUEUE *queue_ptr, VOID *source_ptr, ULONG wait_option) +{ + +UINT status; + +#ifndef TX_TIMER_PROCESS_IN_ISR +TX_THREAD *current_thread; +#endif + + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid queue pointer. */ + if (queue_ptr == TX_NULL) + { + + /* Queue pointer is invalid, return appropriate error code. */ + status = TX_QUEUE_ERROR; + } + + /* Now check for invalid queue ID. */ + else if (queue_ptr -> tx_queue_id != TX_QUEUE_ID) + { + + /* Queue pointer is invalid, return appropriate error code. */ + status = TX_QUEUE_ERROR; + } + + /* Check for an invalid source for message. */ + else if (source_ptr == TX_NULL) + { + + /* Null source pointer, return appropriate error. */ + status = TX_PTR_ERROR; + } + else + { + + /* Check for a wait option error. Only threads are allowed any form of + suspension. */ + if (wait_option != TX_NO_WAIT) + { + + /* Is the call from an ISR or Initialization? */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + + /* A non-thread is trying to suspend, return appropriate error code. */ + status = TX_WAIT_ERROR; + } + +#ifndef TX_TIMER_PROCESS_IN_ISR + else + { + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(current_thread) + + /* Is the current thread the timer thread? */ + if (current_thread == &_tx_timer_thread) + { + + /* A non-thread is trying to suspend, return appropriate error code. */ + status = TX_WAIT_ERROR; + } + } +#endif + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + + /* Call actual queue send function. */ + status = _tx_queue_send(queue_ptr, source_ptr, wait_option); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_queue_send_notify.c b/common_smp/src/txe_queue_send_notify.c new file mode 100644 index 00000000..d07dcc9c --- /dev/null +++ b/common_smp/src/txe_queue_send_notify.c @@ -0,0 +1,103 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Queue */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_queue.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_queue_send_notify PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the queue send notify */ +/* callback function call. */ +/* */ +/* INPUT */ +/* */ +/* queue_ptr Pointer to queue control block*/ +/* queue_send_notify Application callback function */ +/* (TX_NULL disables notify) */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_queue_send_notify Actual queue send notify call */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_queue_send_notify(TX_QUEUE *queue_ptr, VOID (*queue_send_notify)(TX_QUEUE *notify_queue_ptr)) +{ + +UINT status; + + + /* Check for an invalid queue pointer. */ + if (queue_ptr == TX_NULL) + { + + /* Queue pointer is invalid, return appropriate error code. */ + status = TX_QUEUE_ERROR; + } + + /* Now check for a valid queue ID. */ + else if (queue_ptr -> tx_queue_id != TX_QUEUE_ID) + { + + /* Queue pointer is invalid, return appropriate error code. */ + status = TX_QUEUE_ERROR; + } + else + { + + /* Call actual queue send notify function. */ + status = _tx_queue_send_notify(queue_ptr, queue_send_notify); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_semaphore_ceiling_put.c b/common_smp/src/txe_semaphore_ceiling_put.c new file mode 100644 index 00000000..1a6d7f74 --- /dev/null +++ b/common_smp/src/txe_semaphore_ceiling_put.c @@ -0,0 +1,113 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Semaphore */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_semaphore.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_semaphore_ceiling_put PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the semaphore ceiling put */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* semaphore_ptr Pointer to semaphore */ +/* ceiling Maximum value of semaphore */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SEMAPHORE_ERROR Invalid semaphore pointer */ +/* TX_INVALID_CEILING Invalid semaphore ceiling */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_semaphore_ceiling_put Actual semaphore ceiling put */ +/* function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_semaphore_ceiling_put(TX_SEMAPHORE *semaphore_ptr, ULONG ceiling) +{ + +UINT status; + + + /* Check for an invalid semaphore pointer. */ + if (semaphore_ptr == TX_NULL) + { + + /* Semaphore pointer is invalid, return appropriate error code. */ + status = TX_SEMAPHORE_ERROR; + } + + /* Now check for a valid semaphore ID. */ + else if (semaphore_ptr -> tx_semaphore_id != TX_SEMAPHORE_ID) + { + + /* Semaphore pointer is invalid, return appropriate error code. */ + status = TX_SEMAPHORE_ERROR; + } + + /* Determine if the ceiling is valid - must be greater than 1. */ + else if (ceiling == ((ULONG) 0)) + { + + /* Invalid ceiling, return error. */ + status = TX_INVALID_CEILING; + } + else + { + + /* Call actual semaphore ceiling put function. */ + status = _tx_semaphore_ceiling_put(semaphore_ptr, ceiling); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_semaphore_create.c b/common_smp/src/txe_semaphore_create.c new file mode 100644 index 00000000..92a18824 --- /dev/null +++ b/common_smp/src/txe_semaphore_create.c @@ -0,0 +1,208 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Semaphore */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_timer.h" +#include "tx_semaphore.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_semaphore_create PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the create semaphore function */ +/* call. */ +/* */ +/* INPUT */ +/* */ +/* semaphore_ptr Pointer to semaphore control block*/ +/* name_ptr Pointer to semaphore name */ +/* initial_count Initial semaphore count */ +/* semaphore_control_block_size Size of semaphore control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SEMAPHORE_ERROR Invalid semaphore pointer */ +/* TX_CALLER_ERROR Invalid caller of this function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_semaphore_create Actual create semaphore function */ +/* _tx_thread_system_preempt_check Check for preemption */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_semaphore_create(TX_SEMAPHORE *semaphore_ptr, CHAR *name_ptr, ULONG initial_count, UINT semaphore_control_block_size) +{ + +TX_INTERRUPT_SAVE_AREA + +UINT status; +ULONG i; +TX_SEMAPHORE *next_semaphore; +#ifndef TX_TIMER_PROCESS_IN_ISR +TX_THREAD *thread_ptr; +#endif + + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid semaphore pointer. */ + if (semaphore_ptr == TX_NULL) + { + + /* Semaphore pointer is invalid, return appropriate error code. */ + status = TX_SEMAPHORE_ERROR; + } + + /* Now check for a valid semaphore ID. */ + else if (semaphore_control_block_size != (sizeof(TX_SEMAPHORE))) + { + + /* Semaphore pointer is invalid, return appropriate error code. */ + status = TX_SEMAPHORE_ERROR; + } + else + { + + /* Disable interrupts. */ + TX_DISABLE + + /* Increment the preempt disable flag. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Next see if it is already in the created list. */ + next_semaphore = _tx_semaphore_created_ptr; + for (i = ((ULONG) 0); i < _tx_semaphore_created_count; i++) + { + + /* Determine if this semaphore matches the current semaphore in the list. */ + if (semaphore_ptr == next_semaphore) + { + + break; + } + else + { + + /* Move to next semaphore. */ + next_semaphore = next_semaphore -> tx_semaphore_created_next; + } + } + + /* Disable interrupts. */ + TX_DISABLE + + /* Decrement the preempt disable flag. */ + _tx_thread_preempt_disable--; + + /* Restore interrupts. */ + TX_RESTORE + + /* Check for preemption. */ + _tx_thread_system_preempt_check(); + + /* At this point, check to see if there is a duplicate semaphore. */ + if (semaphore_ptr == next_semaphore) + { + + /* Semaphore is already created, return appropriate error code. */ + status = TX_SEMAPHORE_ERROR; + } + +#ifndef TX_TIMER_PROCESS_IN_ISR + else + { + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr) + + /* Check for invalid caller of this function. First check for a calling thread. */ + if (thread_ptr == &_tx_timer_thread) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } +#endif + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + + /* Check for interrupt call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + + /* Now, make sure the call is from an interrupt and not initialization. */ + if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + + /* Call actual semaphore create function. */ + status = _tx_semaphore_create(semaphore_ptr, name_ptr, initial_count); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_semaphore_delete.c b/common_smp/src/txe_semaphore_delete.c new file mode 100644 index 00000000..ea08847b --- /dev/null +++ b/common_smp/src/txe_semaphore_delete.c @@ -0,0 +1,143 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Semaphore */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +#include "tx_semaphore.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_semaphore_delete PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the semaphore delete function */ +/* call. */ +/* */ +/* INPUT */ +/* */ +/* semaphore_ptr Pointer to semaphore control block*/ +/* */ +/* OUTPUT */ +/* */ +/* TX_SEMAPHORE_ERROR Invalid semaphore pointer */ +/* TX_CALLER_ERROR Invalid caller of this function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_semaphore_delete Actual delete semaphore function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_semaphore_delete(TX_SEMAPHORE *semaphore_ptr) +{ + +UINT status; +#ifndef TX_TIMER_PROCESS_IN_ISR +TX_THREAD *thread_ptr; +#endif + + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid semaphore pointer. */ + if (semaphore_ptr == TX_NULL) + { + + /* Semaphore pointer is invalid, return appropriate error code. */ + status = TX_SEMAPHORE_ERROR; + } + + /* Now check for invalid semaphore ID. */ + else if (semaphore_ptr -> tx_semaphore_id != TX_SEMAPHORE_ID) + { + + /* Semaphore pointer is invalid, return appropriate error code. */ + status = TX_SEMAPHORE_ERROR; + } + else + { + + /* Check for invalid caller of this function. */ + + /* Is the caller an ISR or Initialization? */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + +#ifndef TX_TIMER_PROCESS_IN_ISR + else + { + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr) + + /* Is the caller the system timer thread? */ + if (thread_ptr == &_tx_timer_thread) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } +#endif + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + + /* Call actual semaphore delete function. */ + status = _tx_semaphore_delete(semaphore_ptr); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_semaphore_get.c b/common_smp/src/txe_semaphore_get.c new file mode 100644 index 00000000..56e666db --- /dev/null +++ b/common_smp/src/txe_semaphore_get.c @@ -0,0 +1,148 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Semaphore */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +#include "tx_semaphore.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_semaphore_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the semaphore get function call. */ +/* */ +/* INPUT */ +/* */ +/* semaphore_ptr Pointer to semaphore control block*/ +/* wait_option Suspension option */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SEMAPHORE_ERROR Invalid semaphore pointer */ +/* TX_WAIT_ERROR Invalid wait option */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_semaphore_get Actual get semaphore function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_semaphore_get(TX_SEMAPHORE *semaphore_ptr, ULONG wait_option) +{ + +UINT status; + +#ifndef TX_TIMER_PROCESS_IN_ISR +TX_THREAD *current_thread; +#endif + + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid semaphore pointer. */ + if (semaphore_ptr == TX_NULL) + { + + /* Semaphore pointer is invalid, return appropriate error code. */ + status = TX_SEMAPHORE_ERROR; + } + + /* Now check for invalid semaphore ID. */ + else if (semaphore_ptr -> tx_semaphore_id != TX_SEMAPHORE_ID) + { + + /* Semaphore pointer is invalid, return appropriate error code. */ + status = TX_SEMAPHORE_ERROR; + } + else + { + + /* Check for a wait option error. Only threads are allowed any form of + suspension. */ + if (wait_option != TX_NO_WAIT) + { + + /* Is the call from an ISR or Initialization? */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + + /* A non-thread is trying to suspend, return appropriate error code. */ + status = TX_WAIT_ERROR; + } + +#ifndef TX_TIMER_PROCESS_IN_ISR + else + { + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(current_thread) + + /* Is the current thread the timer thread? */ + if (current_thread == &_tx_timer_thread) + { + + /* A non-thread is trying to suspend, return appropriate error code. */ + status = TX_WAIT_ERROR; + } + } +#endif + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + + /* Call actual get semaphore function. */ + status = _tx_semaphore_get(semaphore_ptr, wait_option); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_semaphore_info_get.c b/common_smp/src/txe_semaphore_info_get.c new file mode 100644 index 00000000..b0d466df --- /dev/null +++ b/common_smp/src/txe_semaphore_info_get.c @@ -0,0 +1,113 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Semaphore */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_semaphore.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_semaphore_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the semaphore information get */ +/* service. */ +/* */ +/* INPUT */ +/* */ +/* semaphore_ptr Pointer to semaphore control block*/ +/* name Destination for the semaphore name*/ +/* current_value Destination for current value of */ +/* the semaphore */ +/* first_suspended Destination for pointer of first */ +/* thread suspended on semaphore */ +/* suspended_count Destination for suspended count */ +/* next_semaphore Destination for pointer to next */ +/* semaphore on the created list */ +/* */ +/* OUTPUT */ +/* */ +/* TX_SEMAPHORE_ERROR Invalid semaphore pointer */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_semaphore_info_get Actual semaphore info get service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_semaphore_info_get(TX_SEMAPHORE *semaphore_ptr, CHAR **name, ULONG *current_value, + TX_THREAD **first_suspended, ULONG *suspended_count, + TX_SEMAPHORE **next_semaphore) +{ + +UINT status; + + + /* Check for an invalid semaphore pointer. */ + if (semaphore_ptr == TX_NULL) + { + + /* Semaphore pointer is invalid, return appropriate error code. */ + status = TX_SEMAPHORE_ERROR; + } + + /* Now check for a valid semaphore ID. */ + else if (semaphore_ptr -> tx_semaphore_id != TX_SEMAPHORE_ID) + { + + /* Semaphore pointer is invalid, return appropriate error code. */ + status = TX_SEMAPHORE_ERROR; + } + else + { + + /* Otherwise, call the actual semaphore information get service. */ + status = _tx_semaphore_info_get(semaphore_ptr, name, current_value, first_suspended, + suspended_count, next_semaphore); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_semaphore_prioritize.c b/common_smp/src/txe_semaphore_prioritize.c new file mode 100644 index 00000000..f7cea5c2 --- /dev/null +++ b/common_smp/src/txe_semaphore_prioritize.c @@ -0,0 +1,101 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Semaphore */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_semaphore.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_semaphore_prioritize PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the semaphore prioritize call. */ +/* */ +/* INPUT */ +/* */ +/* semaphore_ptr Pointer to semaphore control block*/ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_semaphore_prioritize Actual semaphore prioritize */ +/* function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_semaphore_prioritize(TX_SEMAPHORE *semaphore_ptr) +{ + +UINT status; + + + /* Check for an invalid semaphore pointer. */ + if (semaphore_ptr == TX_NULL) + { + + /* Semaphore pointer is invalid, return appropriate error code. */ + status = TX_SEMAPHORE_ERROR; + } + + /* Now check for a valid semaphore ID. */ + else if (semaphore_ptr -> tx_semaphore_id != TX_SEMAPHORE_ID) + { + + /* Semaphore pointer is invalid, return appropriate error code. */ + status = TX_SEMAPHORE_ERROR; + } + else + { + + /* Call actual semaphore prioritize function. */ + status = _tx_semaphore_prioritize(semaphore_ptr); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_semaphore_put.c b/common_smp/src/txe_semaphore_put.c new file mode 100644 index 00000000..6c8ab95b --- /dev/null +++ b/common_smp/src/txe_semaphore_put.c @@ -0,0 +1,101 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Semaphore */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_semaphore.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_semaphore_put PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the semaphore put function call. */ +/* */ +/* INPUT */ +/* */ +/* semaphore_ptr Pointer to semaphore control block*/ +/* */ +/* OUTPUT */ +/* */ +/* TX_SEMAPHORE_ERROR Invalid semaphore pointer */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_semaphore_put Actual put semaphore function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_semaphore_put(TX_SEMAPHORE *semaphore_ptr) +{ + +UINT status; + + + /* Check for an invalid semaphore pointer. */ + if (semaphore_ptr == TX_NULL) + { + + /* Semaphore pointer is invalid, return appropriate error code. */ + status = TX_SEMAPHORE_ERROR; + } + + /* Now check for invalid semaphore ID. */ + else if (semaphore_ptr -> tx_semaphore_id != TX_SEMAPHORE_ID) + { + + /* Semaphore pointer is invalid, return appropriate error code. */ + status = TX_SEMAPHORE_ERROR; + } + else + { + + /* Call actual put semaphore function. */ + status = _tx_semaphore_put(semaphore_ptr); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_semaphore_put_notify.c b/common_smp/src/txe_semaphore_put_notify.c new file mode 100644 index 00000000..133c1550 --- /dev/null +++ b/common_smp/src/txe_semaphore_put_notify.c @@ -0,0 +1,104 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Semaphore */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_semaphore.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_semaphore_put_notify PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the semaphore put notify */ +/* callback function call. */ +/* */ +/* INPUT */ +/* */ +/* semaphore_ptr Pointer to semaphore */ +/* semaphore_put_notify Application callback function */ +/* (TX_NULL disables notify) */ +/* */ +/* OUTPUT */ +/* */ +/* status Service return status */ +/* */ +/* CALLS */ +/* */ +/* _tx_semaphore_put_notify Actual semaphore put notify */ +/* call */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_semaphore_put_notify(TX_SEMAPHORE *semaphore_ptr, VOID (*semaphore_put_notify)(TX_SEMAPHORE *notify_semaphore_ptr)) +{ + +UINT status; + + + /* Check for an invalid semaphore pointer. */ + if (semaphore_ptr == TX_NULL) + { + + /* Semaphore pointer is invalid, return appropriate error code. */ + status = TX_SEMAPHORE_ERROR; + } + + /* Now check for invalid semaphore ID. */ + else if (semaphore_ptr -> tx_semaphore_id != TX_SEMAPHORE_ID) + { + + /* Semaphore pointer is invalid, return appropriate error code. */ + status = TX_SEMAPHORE_ERROR; + } + else + { + + /* Call actual semaphore put notify function. */ + status = _tx_semaphore_put_notify(semaphore_ptr, semaphore_put_notify); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_thread_create.c b/common_smp/src/txe_thread_create.c new file mode 100644 index 00000000..57b57013 --- /dev/null +++ b/common_smp/src/txe_thread_create.c @@ -0,0 +1,311 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_timer.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_create PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the thread create function call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* name Pointer to thread name string */ +/* entry_function Entry function of the thread */ +/* entry_input 32-bit input value to thread */ +/* stack_start Pointer to start of stack */ +/* stack_size Stack size in bytes */ +/* priority Priority of thread (0-31) */ +/* preempt_threshold Preemption threshold */ +/* time_slice Thread time-slice value */ +/* auto_start Automatic start selection */ +/* thread_control_block_size Size of thread control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_PTR_ERROR Invalid entry point or stack */ +/* address */ +/* TX_SIZE_ERROR Invalid stack size -too small */ +/* TX_PRIORITY_ERROR Invalid thread priority */ +/* TX_THRESH_ERROR Invalid preemption threshold */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_create Actual thread create function */ +/* _tx_thread_system_preempt_check Check for preemption */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_create(TX_THREAD *thread_ptr, CHAR *name_ptr, + VOID (*entry_function)(ULONG id), ULONG entry_input, + VOID *stack_start, ULONG stack_size, + UINT priority, UINT preempt_threshold, + ULONG time_slice, UINT auto_start, UINT thread_control_block_size) +{ + +TX_INTERRUPT_SAVE_AREA + +UINT status; +UINT break_flag; +ULONG i; +TX_THREAD *next_thread; +VOID *stack_end; +UCHAR *work_ptr; +#ifndef TX_TIMER_PROCESS_IN_ISR +TX_THREAD *current_thread; +#endif + + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid thread pointer. */ + if (thread_ptr == TX_NULL) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Now check for invalid thread control block size. */ + else if (thread_control_block_size != (sizeof(TX_THREAD))) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + else + { + + /* Disable interrupts. */ + TX_DISABLE + + /* Increment the preempt disable flag. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Next see if it is already in the created list. */ + break_flag = TX_FALSE; + next_thread = _tx_thread_created_ptr; + work_ptr = TX_VOID_TO_UCHAR_POINTER_CONVERT(stack_start); + work_ptr = TX_UCHAR_POINTER_ADD(work_ptr, (stack_size - ((ULONG) 1))); + stack_end = TX_UCHAR_TO_VOID_POINTER_CONVERT(work_ptr); + for (i = ((ULONG) 0); i < _tx_thread_created_count; i++) + { + + /* Determine if this thread matches the thread in the list. */ + if (thread_ptr == next_thread) + { + + /* Set the break flag. */ + break_flag = TX_TRUE; + } + + /* Determine if we need to break the loop. */ + if (break_flag == TX_TRUE) + { + + /* Yes, break out of the loop. */ + break; + } + + /* Check the stack pointer to see if it overlaps with this thread's stack. */ + if (stack_start >= next_thread -> tx_thread_stack_start) + { + + if (stack_start < next_thread -> tx_thread_stack_end) + { + + /* This stack overlaps with an existing thread, clear the stack pointer to + force a stack error below. */ + stack_start = TX_NULL; + + /* Set the break flag. */ + break_flag = TX_TRUE; + } + } + + /* Check the end of the stack to see if it is inside this thread's stack area as well. */ + if (stack_end >= next_thread -> tx_thread_stack_start) + { + + if (stack_end < next_thread -> tx_thread_stack_end) + { + + /* This stack overlaps with an existing thread, clear the stack pointer to + force a stack error below. */ + stack_start = TX_NULL; + + /* Set the break flag. */ + break_flag = TX_TRUE; + } + } + + /* Move to the next thread. */ + next_thread = next_thread -> tx_thread_created_next; + } + + /* Disable interrupts. */ + TX_DISABLE + + /* Decrement the preempt disable flag. */ + _tx_thread_preempt_disable--; + + /* Restore interrupts. */ + TX_RESTORE + + /* Check for preemption. */ + _tx_thread_system_preempt_check(); + + /* At this point, check to see if there is a duplicate thread. */ + if (thread_ptr == next_thread) + { + + /* Thread is already created, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Check for invalid starting address of stack. */ + else if (stack_start == TX_NULL) + { + + /* Invalid stack or entry point, return appropriate error code. */ + status = TX_PTR_ERROR; + } + + /* Check for invalid thread entry point. */ + else if (entry_function == TX_NULL) + { + + /* Invalid stack or entry point, return appropriate error code. */ + status = TX_PTR_ERROR; + } + + /* Check the stack size. */ + else if (stack_size < ((ULONG) TX_MINIMUM_STACK)) + { + + /* Stack is not big enough, return appropriate error code. */ + status = TX_SIZE_ERROR; + } + + /* Check the priority specified. */ + else if (priority >= ((UINT) TX_MAX_PRIORITIES)) + { + + /* Invalid priority selected, return appropriate error code. */ + status = TX_PRIORITY_ERROR; + } + + /* Check preemption threshold. */ + else if (preempt_threshold > priority) + { + + /* Invalid preempt threshold, return appropriate error code. */ + status = TX_THRESH_ERROR; + } + + /* Check the start selection. */ + else if (auto_start > TX_AUTO_START) + { + + /* Invalid auto start selection, return appropriate error code. */ + status = TX_START_ERROR; + } + else + { + +#ifndef TX_TIMER_PROCESS_IN_ISR + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(current_thread) + + /* Check for invalid caller of this function. First check for a calling thread. */ + if (current_thread == &_tx_timer_thread) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } +#endif + + /* Check for interrupt call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + + /* Now, make sure the call is from an interrupt and not initialization. */ + if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + + /* Call actual thread create function. */ + status = _tx_thread_create(thread_ptr, name_ptr, entry_function, entry_input, + stack_start, stack_size, priority, preempt_threshold, + time_slice, auto_start); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_thread_delete.c b/common_smp/src/txe_thread_delete.c new file mode 100644 index 00000000..6431d20e --- /dev/null +++ b/common_smp/src/txe_thread_delete.c @@ -0,0 +1,110 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_delete PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the thread delete function call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread to suspend */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_delete Actual thread delete function */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_delete(TX_THREAD *thread_ptr) +{ + +UINT status; + + + /* Check for invalid caller of this function. */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + + /* Check for an invalid thread pointer. */ + else if (thread_ptr == TX_NULL) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Now check for invalid thread ID. */ + else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + else + { + + /* Call actual thread delete function. */ + status = _tx_thread_delete(thread_ptr); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_thread_entry_exit_notify.c b/common_smp/src/txe_thread_entry_exit_notify.c new file mode 100644 index 00000000..efe635be --- /dev/null +++ b/common_smp/src/txe_thread_entry_exit_notify.c @@ -0,0 +1,104 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_entry_exit_notify PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the thread entry/exit notify */ +/* callback function call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread */ +/* thread_entry_exit_notify Pointer to notify callback */ +/* function, TX_NULL to disable*/ +/* */ +/* OUTPUT */ +/* */ +/* status Service return status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_entry_exit_notify Actual entry/exit notify */ +/* function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_entry_exit_notify(TX_THREAD *thread_ptr, VOID (*thread_entry_exit_notify)(TX_THREAD *notify_thread_ptr, UINT type)) +{ + +UINT status; + + + /* Check for an invalid thread pointer. */ + if (thread_ptr == TX_NULL) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Now check for invalid thread ID. */ + else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + else + { + + /* Call actual thread entry/exit notify function. */ + status = _tx_thread_entry_exit_notify(thread_ptr, thread_entry_exit_notify); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_thread_info_get.c b/common_smp/src/txe_thread_info_get.c new file mode 100644 index 00000000..7652c811 --- /dev/null +++ b/common_smp/src/txe_thread_info_get.c @@ -0,0 +1,117 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the thread information get */ +/* service. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control block */ +/* name Destination for the thread name */ +/* state Destination for thread state */ +/* run_count Destination for thread run count */ +/* priority Destination for thread priority */ +/* preemption_threshold Destination for thread preemption-*/ +/* threshold */ +/* time_slice Destination for thread time-slice */ +/* next_thread Destination for next created */ +/* thread */ +/* next_suspended_thread Destination for next suspended */ +/* thread */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_info_get Actual thread information get */ +/* service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_info_get(TX_THREAD *thread_ptr, CHAR **name, UINT *state, ULONG *run_count, + UINT *priority, UINT *preemption_threshold, ULONG *time_slice, + TX_THREAD **next_thread, TX_THREAD **next_suspended_thread) +{ + +UINT status; + + + /* Check for an invalid thread pointer. */ + if (thread_ptr == TX_NULL) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Now check for invalid thread ID. */ + else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + else + { + + /* Call the actual thread information get service. */ + status = _tx_thread_info_get(thread_ptr, name, state, run_count, priority, preemption_threshold, + time_slice, next_thread, next_suspended_thread); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_thread_preemption_change.c b/common_smp/src/txe_thread_preemption_change.c new file mode 100644 index 00000000..1b33e30d --- /dev/null +++ b/common_smp/src/txe_thread_preemption_change.c @@ -0,0 +1,130 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_preemption_change PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the preemption threshold change */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread */ +/* new_threshold New preemption threshold */ +/* old_threshold Old preemption threshold */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_PTR_ERROR Invalid old threshold pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_preemption_change Actual preempt change function*/ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_preemption_change(TX_THREAD *thread_ptr, UINT new_threshold, UINT *old_threshold) +{ + +UINT status; + + + /* Check for an invalid thread pointer. */ + if (thread_ptr == TX_NULL) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Now check for invalid thread ID. */ + else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Check for a valid old threshold pointer. */ + else if (old_threshold == TX_NULL) + { + + /* Invalid destination pointer, return appropriate error code. */ + status = TX_PTR_ERROR; + } + + /* Check for invalid caller of this function. */ + else if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + + /* Determine if the preemption-threshold is valid. */ + else if (new_threshold > thread_ptr -> tx_thread_user_priority) + { + + /* Return an error status. */ + status = TX_THRESH_ERROR; + } + else + { + + /* Call actual change thread preemption function. */ + status = _tx_thread_preemption_change(thread_ptr, new_threshold, old_threshold); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_thread_priority_change.c b/common_smp/src/txe_thread_priority_change.c new file mode 100644 index 00000000..63f27fa2 --- /dev/null +++ b/common_smp/src/txe_thread_priority_change.c @@ -0,0 +1,131 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_priority_change PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the change priority function */ +/* call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread to suspend */ +/* new_priority New thread priority */ +/* old_priority Old thread priority */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_PTR_ERROR Invalid old priority pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_priority_change Actual priority change */ +/* function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_priority_change(TX_THREAD *thread_ptr, UINT new_priority, UINT *old_priority) +{ + +UINT status; + + + /* Check for an invalid thread pointer. */ + if (thread_ptr == TX_NULL) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Now check for invalid thread ID. */ + else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Check for a valid old priority pointer. */ + else if (old_priority == TX_NULL) + { + + /* Invalid destination pointer, return appropriate error code. */ + status = TX_PTR_ERROR; + } + + /* Determine if the priority is legal. */ + else if (new_priority >= ((UINT) TX_MAX_PRIORITIES)) + { + + /* Return an error status. */ + status = TX_PRIORITY_ERROR; + } + + /* Check for invalid caller of this function. */ + else if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + else + { + + /* Call actual change thread priority function. */ + status = _tx_thread_priority_change(thread_ptr, new_priority, old_priority); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_thread_relinquish.c b/common_smp/src/txe_thread_relinquish.c new file mode 100644 index 00000000..696c19e0 --- /dev/null +++ b/common_smp/src/txe_thread_relinquish.c @@ -0,0 +1,92 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_relinquish PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks to make sure a thread is executing before the */ +/* relinquish is executed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_relinquish Actual thread relinquish call */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _txe_thread_relinquish(VOID) +{ + +TX_THREAD *current_thread; + + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(current_thread) + + /* Make sure a thread is executing. */ + if (current_thread != TX_NULL) + { + + /* Now make sure the call is not from an ISR or Initialization. */ + if (TX_THREAD_GET_SYSTEM_STATE() == ((ULONG) 0)) + { + + /* Okay to call the real relinquish function. */ + _tx_thread_relinquish(); + } + } +} + diff --git a/common_smp/src/txe_thread_reset.c b/common_smp/src/txe_thread_reset.c new file mode 100644 index 00000000..9ff00215 --- /dev/null +++ b/common_smp/src/txe_thread_reset.c @@ -0,0 +1,136 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_reset PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the thread reset function call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread to reset */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Service return status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_reset Actual thread reset function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_reset(TX_THREAD *thread_ptr) +{ + +UINT status; +#ifndef TX_TIMER_PROCESS_IN_ISR +TX_THREAD *current_thread; +#endif + + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid thread pointer. */ + if (thread_ptr == TX_NULL) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Now check for an invalid thread ID. */ + else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + else + { + +#ifndef TX_TIMER_PROCESS_IN_ISR + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(current_thread) + + /* Check for invalid caller of this function. First check for a calling thread. */ + if (current_thread == &_tx_timer_thread) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } +#endif + + /* Check for interrupt or initialization call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + + /* Call actual thread reset function. */ + status = _tx_thread_reset(thread_ptr); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_thread_resume.c b/common_smp/src/txe_thread_resume.c new file mode 100644 index 00000000..1fd65890 --- /dev/null +++ b/common_smp/src/txe_thread_resume.c @@ -0,0 +1,101 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_resume PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the resume thread function call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread to resume */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_resume Actual thread resume function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_resume(TX_THREAD *thread_ptr) +{ + +UINT status; + + + /* Check for an invalid thread pointer. */ + if (thread_ptr == TX_NULL) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Now check for invalid thread ID. */ + else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + else + { + + /* Call actual thread resume function. */ + status = _tx_thread_resume(thread_ptr); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_thread_suspend.c b/common_smp/src/txe_thread_suspend.c new file mode 100644 index 00000000..d8899c37 --- /dev/null +++ b/common_smp/src/txe_thread_suspend.c @@ -0,0 +1,103 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_suspend PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the thread suspend function */ +/* call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread to suspend */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_suspend Actual thread suspension */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_suspend(TX_THREAD *thread_ptr) +{ + +UINT status; + + + /* Check for an invalid thread pointer. */ + if (thread_ptr == TX_NULL) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Now check for invalid thread ID. */ + else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + else + { + + /* Call actual thread suspend function. */ + status = _tx_thread_suspend(thread_ptr); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_thread_terminate.c b/common_smp/src/txe_thread_terminate.c new file mode 100644 index 00000000..e20b0dd5 --- /dev/null +++ b/common_smp/src/txe_thread_terminate.c @@ -0,0 +1,112 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_terminate PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the thread terminate function */ +/* call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread to suspend */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_terminate Actual thread terminate */ +/* function */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_terminate(TX_THREAD *thread_ptr) +{ + +UINT status; + + + /* Check for an invalid thread pointer. */ + if (thread_ptr == TX_NULL) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Now check for invalid thread ID. */ + else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Check for invalid caller of this function. */ + else if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + else + { + + /* Call actual thread terminate function. */ + status = _tx_thread_terminate(thread_ptr); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_thread_time_slice_change.c b/common_smp/src/txe_thread_time_slice_change.c new file mode 100644 index 00000000..e4d1d69c --- /dev/null +++ b/common_smp/src/txe_thread_time_slice_change.c @@ -0,0 +1,122 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_time_slice_change PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the time slice change function */ +/* call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread */ +/* new_time_slice New time slice */ +/* old_time_slice Old time slice */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_time_slice_change Actual time-slice change */ +/* function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_time_slice_change(TX_THREAD *thread_ptr, ULONG new_time_slice, ULONG *old_time_slice) +{ + +UINT status; + + + /* Check for an invalid thread pointer. */ + if (thread_ptr == TX_NULL) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Now check for invalid thread ID. */ + else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Check for a valid old time-slice pointer. */ + else if (old_time_slice == TX_NULL) + { + + /* Invalid destination pointer, return appropriate error code. */ + status = TX_PTR_ERROR; + } + + /* Check for invalid caller of this function. */ + else if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + else + { + + /* Call actual change time slice function. */ + status = _tx_thread_time_slice_change(thread_ptr, new_time_slice, old_time_slice); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_thread_wait_abort.c b/common_smp/src/txe_thread_wait_abort.c new file mode 100644 index 00000000..e614b45a --- /dev/null +++ b/common_smp/src/txe_thread_wait_abort.c @@ -0,0 +1,101 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_wait_abort PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the thread wait abort function */ +/* call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread to abort the wait on */ +/* */ +/* OUTPUT */ +/* */ +/* status Return completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_wait_abort Actual wait abort function */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_wait_abort(TX_THREAD *thread_ptr) +{ + +UINT status; + + + /* Check for an invalid thread pointer. */ + if (thread_ptr == TX_NULL) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Now check for invalid thread ID. */ + else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + else + { + + /* Call actual thread wait abort function. */ + status = _tx_thread_wait_abort(thread_ptr); + } + + /* Return status to the caller. */ + return(status); +} + diff --git a/common_smp/src/txe_timer_activate.c b/common_smp/src/txe_timer_activate.c new file mode 100644 index 00000000..a0af5532 --- /dev/null +++ b/common_smp/src/txe_timer_activate.c @@ -0,0 +1,101 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_timer.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_timer_activate PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the activate application timer */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* timer_ptr Pointer to timer control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_TIMER_ERROR Invalid application timer */ +/* TX_ACTIVATE_ERROR Application timer already active */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_activate Actual application timer activate */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_timer_activate(TX_TIMER *timer_ptr) +{ + +UINT status; + + + /* Check for an invalid timer pointer. */ + if (timer_ptr == TX_NULL) + { + /* Timer pointer is invalid, return appropriate error code. */ + status = TX_TIMER_ERROR; + } + + /* Now check for invalid timer ID. */ + else if (timer_ptr -> tx_timer_id != TX_TIMER_ID) + { + /* Timer pointer is invalid, return appropriate error code. */ + status = TX_TIMER_ERROR; + } + else + { + + /* Call actual application timer activate function. */ + status = _tx_timer_activate(timer_ptr); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_timer_change.c b/common_smp/src/txe_timer_change.c new file mode 100644 index 00000000..a71e509f --- /dev/null +++ b/common_smp/src/txe_timer_change.c @@ -0,0 +1,124 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_timer.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_timer_change PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the application timer change */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* timer_ptr Pointer to timer control block */ +/* initial_ticks Initial expiration ticks */ +/* reschedule_ticks Reschedule ticks */ +/* */ +/* OUTPUT */ +/* */ +/* TX_TIMER_ERROR Invalid application timer pointer */ +/* TX_TICK_ERROR Invalid initial tick value of 0 */ +/* TX_CALLER_ERROR Invalid caller of this function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_change Actual timer change function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_timer_change(TX_TIMER *timer_ptr, ULONG initial_ticks, ULONG reschedule_ticks) +{ + +UINT status; + + + /* Check for an invalid timer pointer. */ + if (timer_ptr == TX_NULL) + { + + /* Timer pointer is invalid, return appropriate error code. */ + status = TX_TIMER_ERROR; + } + + /* Now check for invalid timer ID. */ + else if (timer_ptr -> tx_timer_id != TX_TIMER_ID) + { + + /* Timer pointer is invalid, return appropriate error code. */ + status = TX_TIMER_ERROR; + } + + /* Check for an illegal initial tick value. */ + else if (initial_ticks == ((ULONG) 0)) + { + + /* Invalid initial tick value, return appropriate error code. */ + status = TX_TICK_ERROR; + } + + /* Check for invalid caller of this function. */ + else if (TX_THREAD_GET_SYSTEM_STATE() >= TX_INITIALIZE_IN_PROGRESS) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + else + { + + /* Call actual application timer function. */ + status = _tx_timer_change(timer_ptr, initial_ticks, reschedule_ticks); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_timer_create.c b/common_smp/src/txe_timer_create.c new file mode 100644 index 00000000..5fe04bc2 --- /dev/null +++ b/common_smp/src/txe_timer_create.c @@ -0,0 +1,237 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_timer.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_timer_create PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the create application timer */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* timer_ptr Pointer to timer control block */ +/* name_ptr Pointer to timer name */ +/* expiration_function Application expiration function */ +/* initial_ticks Initial expiration ticks */ +/* reschedule_ticks Reschedule ticks */ +/* auto_activate Automatic activation flag */ +/* timer_control_block_size Size of timer control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_TIMER_ERROR Invalid timer control block */ +/* TX_TICK_ERROR Invalid initial expiration count */ +/* TX_ACTIVATE_ERROR Invalid timer activation option */ +/* TX_CALLER_ERROR Invalid caller of this function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_system_preempt_check Check for preemption */ +/* _tx_timer_create Actual timer create function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_timer_create(TX_TIMER *timer_ptr, CHAR *name_ptr, + VOID (*expiration_function)(ULONG id), ULONG expiration_input, + ULONG initial_ticks, ULONG reschedule_ticks, UINT auto_activate, UINT timer_control_block_size) +{ + +TX_INTERRUPT_SAVE_AREA + +UINT status; +ULONG i; +TX_TIMER *next_timer; +#ifndef TX_TIMER_PROCESS_IN_ISR +TX_THREAD *thread_ptr; +#endif + + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for a NULL timer pointer. */ + if (timer_ptr == TX_NULL) + { + + /* Timer pointer is invalid, return appropriate error code. */ + status = TX_TIMER_ERROR; + } + + /* Now check for invalid control block size. */ + else if (timer_control_block_size != (sizeof(TX_TIMER))) + { + + /* Timer pointer is invalid, return appropriate error code. */ + status = TX_TIMER_ERROR; + } + else + { + + /* Disable interrupts. */ + TX_DISABLE + + /* Increment the preempt disable flag. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Next see if it is already in the created list. */ + next_timer = _tx_timer_created_ptr; + for (i = ((ULONG) 0); i < _tx_timer_created_count; i++) + { + + /* Determine if this timer matches the current timer in the list. */ + if (timer_ptr == next_timer) + { + + break; + } + else + { + + /* Move to next timer. */ + next_timer = next_timer -> tx_timer_created_next; + } + } + + /* Disable interrupts. */ + TX_DISABLE + + /* Decrement the preempt disable flag. */ + _tx_thread_preempt_disable--; + + /* Restore interrupts. */ + TX_RESTORE + + /* Check for preemption. */ + _tx_thread_system_preempt_check(); + + /* At this point, check to see if there is a duplicate timer. */ + if (timer_ptr == next_timer) + { + + /* Timer is already created, return appropriate error code. */ + status = TX_TIMER_ERROR; + } + + /* Check for an illegal initial tick value. */ + else if (initial_ticks == ((ULONG) 0)) + { + + /* Invalid initial tick value, return appropriate error code. */ + status = TX_TICK_ERROR; + } + else + { + + /* Check for an illegal activation. */ + if (auto_activate != TX_AUTO_ACTIVATE) + { + + /* And activation is not the other value. */ + if (auto_activate != TX_NO_ACTIVATE) + { + + /* Invalid activation selected, return appropriate error code. */ + status = TX_ACTIVATE_ERROR; + } + } + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + +#ifndef TX_TIMER_PROCESS_IN_ISR + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr) + + /* Check for invalid caller of this function. First check for a calling thread. */ + if (thread_ptr == &_tx_timer_thread) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } +#endif + + /* Check for interrupt call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + + /* Now, make sure the call is from an interrupt and not initialization. */ + if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } + } + + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + + /* Call actual application timer create function. */ + status = _tx_timer_create(timer_ptr, name_ptr, expiration_function, expiration_input, + initial_ticks, reschedule_ticks, auto_activate); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_timer_deactivate.c b/common_smp/src/txe_timer_deactivate.c new file mode 100644 index 00000000..9becb629 --- /dev/null +++ b/common_smp/src/txe_timer_deactivate.c @@ -0,0 +1,102 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_timer.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_timer_deactivate PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the deactivate application timer */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* timer_ptr Pointer to timer control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_TIMER_ERROR Invalid application timer pointer */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_deactivate Actual timer deactivation function*/ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_timer_deactivate(TX_TIMER *timer_ptr) +{ + +UINT status; + + + /* Check for an invalid timer pointer. */ + if (timer_ptr == TX_NULL) + { + + /* Timer pointer is invalid, return appropriate error code. */ + status = TX_TIMER_ERROR; + } + + /* Now check for invalid timer ID. */ + else if (timer_ptr -> tx_timer_id != TX_TIMER_ID) + { + + /* Timer pointer is invalid, return appropriate error code. */ + status = TX_TIMER_ERROR; + } + else + { + + /* Call actual application timer deactivate function. */ + status = _tx_timer_deactivate(timer_ptr); + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_timer_delete.c b/common_smp/src/txe_timer_delete.c new file mode 100644 index 00000000..cfb0fd94 --- /dev/null +++ b/common_smp/src/txe_timer_delete.c @@ -0,0 +1,143 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_timer_delete PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the delete application timer */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* timer_ptr Pointer to timer control block */ +/* */ +/* OUTPUT */ +/* */ +/* TX_TIMER_ERROR Invalid application timer pointer */ +/* TX_CALLER_ERROR Invalid caller of this function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_delete Actual timer delete function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_timer_delete(TX_TIMER *timer_ptr) +{ + +UINT status; +#ifndef TX_TIMER_PROCESS_IN_ISR +TX_THREAD *thread_ptr; +#endif + + +#ifndef TX_TIMER_PROCESS_IN_ISR + + /* Default status to success. */ + status = TX_SUCCESS; +#endif + + /* Check for an invalid timer pointer. */ + if (timer_ptr == TX_NULL) + { + /* Timer pointer is invalid, return appropriate error code. */ + status = TX_TIMER_ERROR; + } + + /* Now check for invalid timer ID. */ + else if (timer_ptr -> tx_timer_id != TX_TIMER_ID) + { + /* Timer pointer is invalid, return appropriate error code. */ + status = TX_TIMER_ERROR; + } + + /* Check for invalid caller of this function. */ + + /* Is the caller an ISR or Initialization? */ + else if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + else + { + +#ifndef TX_TIMER_PROCESS_IN_ISR + + /* Pickup thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr) + + /* Is the caller the system timer thread? */ + if (thread_ptr == &_tx_timer_thread) + { + + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { +#endif + + /* Call actual application timer delete function. */ + status = _tx_timer_delete(timer_ptr); + +#ifndef TX_TIMER_PROCESS_IN_ISR + } +#endif + } + + /* Return completion status. */ + return(status); +} + diff --git a/common_smp/src/txe_timer_info_get.c b/common_smp/src/txe_timer_info_get.c new file mode 100644 index 00000000..7dc07cdc --- /dev/null +++ b/common_smp/src/txe_timer_info_get.c @@ -0,0 +1,110 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_timer.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_timer_info_get PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the timer information get */ +/* service. */ +/* */ +/* INPUT */ +/* */ +/* timer_ptr Pointer to timer control block */ +/* name Destination for the timer name */ +/* active Destination for active flag */ +/* remaining_ticks Destination for remaining ticks */ +/* before expiration */ +/* reschedule_ticks Destination for reschedule ticks */ +/* next_timer Destination for next timer on the */ +/* created list */ +/* */ +/* OUTPUT */ +/* */ +/* TX_TIMER_ERROR Invalid timer pointer */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_info_get Actual info get call */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_timer_info_get(TX_TIMER *timer_ptr, CHAR **name, UINT *active, ULONG *remaining_ticks, + ULONG *reschedule_ticks, TX_TIMER **next_timer) +{ + +UINT status; + + + /* Check for an invalid timer pointer. */ + if (timer_ptr == TX_NULL) + { + + /* Timer pointer is invalid, return appropriate error code. */ + status = TX_TIMER_ERROR; + } + + /* Now check for invalid timer ID. */ + else if (timer_ptr -> tx_timer_id != TX_TIMER_ID) + { + + /* Timer pointer is invalid, return appropriate error code. */ + status = TX_TIMER_ERROR; + } + else + { + + /* Otherwise, call the actual timer information get service. */ + status = _tx_timer_info_get(timer_ptr, name, active, remaining_ticks, reschedule_ticks, next_timer); + } + + /* Return completion status. */ + return(status); +} + diff --git a/ports/cortex_a15/ac6/example_build/sample_threadx/.cproject b/ports/cortex_a15/ac6/example_build/sample_threadx/.cproject new file mode 100644 index 00000000..d336562e --- /dev/null +++ b/ports/cortex_a15/ac6/example_build/sample_threadx/.cproject @@ -0,0 +1,242 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_a15/ac6/example_build/sample_threadx/.project b/ports/cortex_a15/ac6/example_build/sample_threadx/.project new file mode 100644 index 00000000..725328bd --- /dev/null +++ b/ports/cortex_a15/ac6/example_build/sample_threadx/.project @@ -0,0 +1,27 @@ + + + sample_threadx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.arm.debug.ds.nature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/ports/cortex_a15/ac6/example_build/sample_threadx/.settings/language.settings.xml b/ports/cortex_a15/ac6/example_build/sample_threadx/.settings/language.settings.xml new file mode 100644 index 00000000..b54c244b --- /dev/null +++ b/ports/cortex_a15/ac6/example_build/sample_threadx/.settings/language.settings.xml @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_a15/ac6/example_build/sample_threadx/cortex-a15_tx.launch b/ports/cortex_a15/ac6/example_build/sample_threadx/cortex-a15_tx.launch new file mode 100644 index 00000000..530c954d --- /dev/null +++ b/ports/cortex_a15/ac6/example_build/sample_threadx/cortex-a15_tx.launch @@ -0,0 +1,188 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_a15/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a15/ac6/example_build/sample_threadx/sample_threadx.c new file mode 100644 index 00000000..418ec634 --- /dev/null +++ b/ports/cortex_a15/ac6/example_build/sample_threadx/sample_threadx.c @@ -0,0 +1,369 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_a15/ac6/example_build/sample_threadx/sample_threadx.scat b/ports/cortex_a15/ac6/example_build/sample_threadx/sample_threadx.scat new file mode 100644 index 00000000..8e648890 --- /dev/null +++ b/ports/cortex_a15/ac6/example_build/sample_threadx/sample_threadx.scat @@ -0,0 +1,47 @@ +;************************************************** +; Copyright (c) 2011 Arm Limited (or its affiliates). All rights reserved. +; Use, modification and redistribution of this file is subject to your possession of a +; valid End User License Agreement for the Arm Product of which these examples are part of +; and your compliance with all applicable terms and conditions of such licence agreement. +;************************************************** + +; Scatter-file for bare-metal example on Versatile Express + +; This scatter-file places application code, data, stack and heap at suitable addresses in the Versatile Express Cortex-A15 Core memory map. + +; Versatile Express Cortex-A15 Core has SDRAM at 0x80000000, which this scatter-file uses. + + +SDRAM 0x80000000 +{ + VECTORS +0 + { + * (VECTORS, +FIRST) ; Vector table and other (assembler) startup code + * (InRoot$$Sections) ; All (library) code that must be in a root region + } + + RO_CODE +0 + { * (+RO-CODE) } ; Application RO code (.text) + + RO_DATA +0 + { * (+RO-DATA) } ; Application RO data (.constdata) + + RW_DATA +0 + { * (+RW) } ; Application RW data (.data) + + ZI_DATA +0 + { * (+ZI) } ; Application ZI data (.bss) + + ARM_LIB_HEAP 0x80040000 EMPTY 0x00040000 ; Application heap + { } + + ARM_LIB_STACK 0x80090000 EMPTY -0x00010000 ; Application (SVC mode) stack + { } + + ;IRQ_STACK 0x800A0000 EMPTY -0x00010000 ; IRQ mode stack + ;{ } + + TTB 0x80100000 EMPTY 0x4000 ; Level-1 Translation Table for MMU + { } + +} diff --git a/ports/cortex_a15/ac6/example_build/sample_threadx/startup.S b/ports/cortex_a15/ac6/example_build/sample_threadx/startup.S new file mode 100644 index 00000000..8bfa1982 --- /dev/null +++ b/ports/cortex_a15/ac6/example_build/sample_threadx/startup.S @@ -0,0 +1,384 @@ +//---------------------------------------------------------------- +// Cortex-A15 Embedded example - Startup Code +// +// Copyright (c) 2005-2018 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +//---------------------------------------------------------------- + + +// Standard definitions of mode bits and interrupt (I & F) flags in PSRs + +#define Mode_USR 0x10 +#define Mode_FIQ 0x11 +#define Mode_IRQ 0x12 +#define Mode_SVC 0x13 +#define Mode_ABT 0x17 +#define Mode_UND 0x1B +#define Mode_SYS 0x1F + +#define I_Bit 0x80 // When I bit is set, IRQ is disabled +#define F_Bit 0x40 // When F bit is set, FIQ is disabled + + + .section VECTORS, "ax" + .align 3 + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + +//---------------------------------------------------------------- +// Entry point for the Reset handler +//---------------------------------------------------------------- + + .global Vectors + +//---------------------------------------------------------------- +// Exception Vector Table +//---------------------------------------------------------------- +// Note: LDR PC instructions are used here, though branch (B) instructions +// could also be used, unless the exception handlers are >32MB away. + +Vectors: + LDR PC, Reset_Addr + LDR PC, Undefined_Addr + LDR PC, SVC_Addr + LDR PC, Prefetch_Addr + LDR PC, Abort_Addr + LDR PC, Hypervisor_Addr + LDR PC, IRQ_Addr + LDR PC, FIQ_Addr + + .balign 4 +Reset_Addr: + .word Reset_Handler +Undefined_Addr: + //.word Undefined_Handler + .word __tx_undefined +SVC_Addr: + //.word SVC_Handler + .word __tx_swi_interrupt +Prefetch_Addr: + //.word Prefetch_Handler + .word __tx_prefetch_handler +Abort_Addr: + //.word Abort_Handler + .word __tx_abort_handler +Hypervisor_Addr: + //.word Hypervisor_Handler + .word __tx_reserved_handler +IRQ_Addr: + //.word IRQ_Handler + .word __tx_irq_handler +FIQ_Addr: + //.word FIQ_Handler + .word __tx_fiq_handler + + +//---------------------------------------------------------------- +// Exception Handlers +//---------------------------------------------------------------- + +Undefined_Handler: + B Undefined_Handler +SVC_Handler: + B SVC_Handler +Prefetch_Handler: + B Prefetch_Handler +Abort_Handler: + B Abort_Handler +Hypervisor_Handler: + B Hypervisor_Handler +IRQ_Handler: + B IRQ_Handler +FIQ_Handler: + B FIQ_Handler + + +//---------------------------------------------------------------- +// Reset Handler +//---------------------------------------------------------------- +Reset_Handler: + +//---------------------------------------------------------------- +// Disable caches, MMU and branch prediction in case they were left enabled from an earlier run +// This does not need to be done from a cold reset +//---------------------------------------------------------------- + + MRC p15, 0, r0, c1, c0, 0 // Read System Control Register + BIC r0, r0, #(0x1 << 12) // Clear I bit 12 to disable I Cache + BIC r0, r0, #(0x1 << 2) // Clear C bit 2 to disable D Cache + BIC r0, r0, #0x1 // Clear M bit 0 to disable MMU + BIC r0, r0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction + MCR p15, 0, r0, c1, c0, 0 // Write System Control Register + ISB + +// The MMU is enabled later, before calling main(). Caches and branch prediction are enabled inside main(), +// after the MMU has been enabled and scatterloading has been performed. + +//---------------------------------------------------------------- +// ACTLR.SMP bit must be set before the caches and MMU are enabled, +// or any cache and TLB maintenance operations are performed, even for "AMP" CPUs. +// In the Cortex-A15 processor, the L1 data cache and L2 cache are always coherent, +// for shared or non-shared data, regardless of the value of the SMP bit. +//---------------------------------------------------------------- + MRC p15, 0, r0, c1, c0, 1 // Read ACTLR + ORR r0, r0, #(1 << 6) // Set ACTLR.SMP bit + MCR p15, 0, r0, c1, c0, 1 // Write ACTLR + ISB + +//---------------------------------------------------------------- +// Invalidate Data and Instruction TLBs and branch predictor in case they were left enabled from an earlier run +// This does not need to be done from a cold reset +//---------------------------------------------------------------- + + MOV r0,#0 + MCR p15, 0, r0, c8, c7, 0 // I-TLB and D-TLB invalidation + MCR p15, 0, r0, c7, c5, 6 // BPIALL - Invalidate entire branch predictor array + +//---------------------------------------------------------------- +// Initialize Supervisor Mode Stack +// Note stack must be 8 byte aligned. +//---------------------------------------------------------------- + + LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit + +//---------------------------------------------------------------- +// Disable loop-buffer to fix errata on A15 r0p0 +//---------------------------------------------------------------- + MRC p15, 0, r0, c0, c0, 0 // Read main ID register MIDR + MOV r1, r0, lsr #4 // Extract Primary Part Number + LDR r2, =0xFFF + AND r1, r1, r2 + LDR r2, =0xC0F + CMP r1, r2 // Is this an A15? + BNE notA15r0p0 // Jump if not A15 + AND r5, r0, #0x00f00000 // Variant + AND r6, r0, #0x0000000f // Revision + ORRS r6, r6, r5 // Combine variant and revision + BNE notA15r0p0 // Jump if not r0p0 + MRC p15, 0, r0, c1, c0, 1 // Read Aux Ctrl Reg + ORR r0, r0, #(1 << 1) // Set bit 1 to Disable Loop Buffer + MCR p15, 0, r0, c1, c0, 1 // Write Aux Ctrl Reg + ISB +notA15r0p0: + +//---------------------------------------------------------------- +// Set Vector Base Address Register (VBAR) to point to this application's vector table +//---------------------------------------------------------------- + + LDR r0, =Vectors + MCR p15, 0, r0, c12, c0, 0 + +//---------------------------------------------------------------- +// Cache Invalidation code for Cortex-A15 +// NOTE: Neither Caches, nor MMU, nor BTB need post-reset invalidation on Cortex-A15, +// but forcing a cache invalidation makes the code more portable to other CPUs (e.g. Cortex-A9) +//---------------------------------------------------------------- + + // Invalidate L1 Instruction Cache + + MRC p15, 1, r0, c0, c0, 1 // Read Cache Level ID Register (CLIDR) + TST r0, #0x3 // Harvard Cache? + MOV r0, #0 // SBZ + MCRNE p15, 0, r0, c7, c5, 0 // ICIALLU - Invalidate instruction cache and flush branch target cache + + // Invalidate Data/Unified Caches + + MRC p15, 1, r0, c0, c0, 1 // Read CLIDR + ANDS r3, r0, #0x07000000 // Extract coherency level + MOV r3, r3, LSR #23 // Total cache levels << 1 + BEQ Finished // If 0, no need to clean + + MOV r10, #0 // R10 holds current cache level << 1 +Loop1: ADD r2, r10, r10, LSR #1 // R2 holds cache "Set" position + MOV r1, r0, LSR r2 // Bottom 3 bits are the Cache-type for this level + AND r1, r1, #7 // Isolate those lower 3 bits + CMP r1, #2 + BLT Skip // No cache or only instruction cache at this level + + MCR p15, 2, r10, c0, c0, 0 // Write the Cache Size selection register + ISB // ISB to sync the change to the CacheSizeID reg + MRC p15, 1, r1, c0, c0, 0 // Reads current Cache Size ID register + AND r2, r1, #7 // Extract the line length field + ADD r2, r2, #4 // Add 4 for the line length offset (log2 16 bytes) + LDR r4, =0x3FF + ANDS r4, r4, r1, LSR #3 // R4 is the max number on the way size (right aligned) + CLZ r5, r4 // R5 is the bit position of the way size increment + LDR r7, =0x7FFF + ANDS r7, r7, r1, LSR #13 // R7 is the max number of the index size (right aligned) + +Loop2: MOV r9, r4 // R9 working copy of the max way size (right aligned) + +Loop3: ORR r11, r10, r9, LSL r5 // Factor in the Way number and cache number into R11 + ORR r11, r11, r7, LSL r2 // Factor in the Set number + MCR p15, 0, r11, c7, c6, 2 // Invalidate by Set/Way + SUBS r9, r9, #1 // Decrement the Way number + BGE Loop3 + SUBS r7, r7, #1 // Decrement the Set number + BGE Loop2 +Skip: ADD r10, r10, #2 // Increment the cache number + CMP r3, r10 + BGT Loop1 + +Finished: + + +//---------------------------------------------------------------- +// MMU Configuration +// Set translation table base +//---------------------------------------------------------------- + + // Two translation tables are supported, TTBR0 and TTBR1 + // Configure translation table base (TTB) control register cp15,c2 + // to a value of all zeros, indicates we are using TTB register 0. + + MOV r0,#0x0 + MCR p15, 0, r0, c2, c0, 2 + + // write the address of our page table base to TTB register 0 + LDR r0,=Image$$TTB$$ZI$$Base + MOV r1, #0x08 // RGN=b01 (outer cacheable write-back cached, write allocate) + // S=0 (translation table walk to non-shared memory) + ORR r1,r1,#0x40 // IRGN=b01 (inner cacheability for the translation table walk is Write-back Write-allocate) + + ORR r0,r0,r1 + MCR p15, 0, r0, c2, c0, 0 + + +//---------------------------------------------------------------- +// PAGE TABLE generation + +// Generate the page tables +// Build a flat translation table for the whole address space. +// ie: Create 4096 1MB sections from 0x000xxxxx to 0xFFFxxxxx + + +// 31 20 19 18 17 16 15 14 12 11 10 9 8 5 4 3 2 1 0 +// |section base address| 0 0 |nG| S |AP2| TEX | AP | P | Domain | XN | C B | 1 0| +// +// Bits[31:20] - Top 12 bits of VA is pointer into table +// nG[17]=0 - Non global, enables matching against ASID in the TLB when set. +// S[16]=0 - Indicates normal memory is shared when set. +// AP2[15]=0 +// AP[11:10]=11 - Configure for full read/write access in all modes +// TEX[14:12]=000 +// CB[3:2]= 00 - Set attributes to Strongly-ordered memory. +// (except for the code segment descriptor, see below) +// IMPP[9]=0 - Ignored +// Domain[5:8]=1111 - Set all pages to use domain 15 +// XN[4]=1 - Execute never on Strongly-ordered memory +// Bits[1:0]=10 - Indicate entry is a 1MB section +//---------------------------------------------------------------- + LDR r0, =Image$$TTB$$ZI$$Base + LDR r1,=0xfff // loop counter + LDR r2,=3554 + + // r0 contains the address of the translation table base + // r1 is loop counter + // r2 is level1 descriptor (bits 19:0) + + // use loop counter to create 4096 individual table entries. + // this writes from address 'Image$$TTB$$ZI$$Base' + + // offset 0x3FFC down to offset 0x0 in word steps (4 bytes) + +init_ttb_1: + ORR r3, r2, r1, LSL#20 // R3 now contains full level1 descriptor to write + ORR r3, r3, #16 // Set XN bit + STR r3, [r0, r1, LSL#2] // Str table entry at TTB base + loopcount*4 + SUBS r1, r1, #1 // Decrement loop counter + BPL init_ttb_1 + + // In this example, the 1MB section based at 'Image$$VECTORS$$Base' is setup specially as cacheable (write back mode). + // TEX[14:12]=001 and CB[3:2]= 11, Outer and inner write back, write allocate normal memory. + LDR r1, =Image$$VECTORS$$Base // Base physical address of code segment + LSR r1, #20 // Shift right to align to 1MB boundaries + ORR r3, r2, r1, LSL#20 // Setup the initial level1 descriptor again + ORR r3, r3, #12 // Set CB bits + ORR r3, r3, #4096 // Set TEX bit 12 + STR r3, [r0, r1, LSL#2] // str table entry + +//---------------------------------------------------------------- +// Setup domain control register - Enable all domains to client mode +//---------------------------------------------------------------- + + MRC p15, 0, r0, c3, c0, 0 // Read Domain Access Control Register + LDR r0, =0x55555555 // Initialize every domain entry to b01 (client) + MCR p15, 0, r0, c3, c0, 0 // Write Domain Access Control Register + +#if defined(__ARM_NEON) || defined(__ARM_FP) + +//---------------------------------------------------------------- +// Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11. +// Enables Full Access i.e. in both privileged and non privileged modes +//---------------------------------------------------------------- + + MRC p15, 0, r0, c1, c0, 2 // Read Coprocessor Access Control Register (CPACR) + ORR r0, r0, #(0xF << 20) // Enable access to CP 10 & 11 + MCR p15, 0, r0, c1, c0, 2 // Write Coprocessor Access Control Register (CPACR) + ISB + +//---------------------------------------------------------------- +// Switch on the VFP and NEON hardware +//---------------------------------------------------------------- + + MOV r0, #0x40000000 + VMSR FPEXC, r0 // Write FPEXC register, EN bit set +#endif + + +//---------------------------------------------------------------- +// Enable MMU and branch to __main +// Leaving the caches disabled until after scatter loading. +//---------------------------------------------------------------- + + LDR r12,=__main // Save this in register for possible long jump + +#if 0 + MRC p15, 0, r0, c1, c0, 0 // Read System Control Register + BIC r0, r0, #(0x1 << 12) // Clear I bit 12 to disable I Cache + BIC r0, r0, #(0x1 << 2) // Clear C bit 2 to disable D Cache + BIC r0, r0, #0x2 // Clear A bit 1 to disable strict alignment fault checking + ORR r0, r0, #0x1 // Set M bit 0 to enable MMU before scatter loading + MCR p15, 0, r0, c1, c0, 0 // Write System Control Register + ISB +#endif + +// Now the MMU is enabled, virtual to physical address translations will occur. This will affect the next +// instruction fetch. +// +// The two instructions currently in the pipeline will have been fetched before the MMU was enabled. +// The branch to __main is safe because the Virtual Address (VA) is the same as the Physical Address (PA) +// (flat mapping) of this code that enables the MMU and performs the branch + + BX r12 // Branch to __main C library entry point + + + +//---------------------------------------------------------------- +// Enable caches and branch prediction +// This code must be run from a privileged mode +//---------------------------------------------------------------- + + .section ENABLECACHES,"ax" + .align 3 + + .global enable_caches + .type enable_caches, "function" + .cfi_startproc +enable_caches: + +//---------------------------------------------------------------- +// Enable caches and branch prediction +//---------------------------------------------------------------- + + MRC p15, 0, r0, c1, c0, 0 // Read System Control Register + ORR r0, r0, #(0x1 << 12) // Set I bit 12 to enable I Cache + ORR r0, r0, #(0x1 << 2) // Set C bit 2 to enable D Cache + ORR r0, r0, #(0x1 << 11) // Set Z bit 11 to enable branch prediction + MCR p15, 0, r0, c1, c0, 0 // Write System Control Register + ISB + + BX lr + + .cfi_endproc + diff --git a/ports/cortex_a15/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_a15/ac6/example_build/sample_threadx/tx_initialize_low_level.S new file mode 100644 index 00000000..f8196b27 --- /dev/null +++ b/ports/cortex_a15/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -0,0 +1,345 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Initialize */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_initialize.h" +@#include "tx_thread.h" +@#include "tx_timer.h" + + .arm + +SVC_MODE = 0xD3 @ Disable IRQ/FIQ SVC mode +IRQ_MODE = 0xD2 @ Disable IRQ/FIQ IRQ mode +FIQ_MODE = 0xD1 @ Disable IRQ/FIQ FIQ mode +SYS_MODE = 0xDF @ Disable IRQ/FIQ SYS mode +FIQ_STACK_SIZE = 512 @ FIQ stack size +IRQ_STACK_SIZE = 1024 @ IRQ stack size +SYS_STACK_SIZE = 1024 @ System stack size +@ +@ + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global _tx_thread_context_save + .global _tx_thread_context_restore + .global _tx_timer_interrupt + +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_initialize_low_level for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .thumb + .global $_tx_initialize_low_level + .type $_tx_initialize_low_level,function +$_tx_initialize_low_level: + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_initialize_low_level @ Call _tx_initialize_low_level function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_initialize_low_level Cortex-A15/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for any low-level processor */ +@/* initialization, including setting up interrupt vectors, setting */ +@/* up a periodic timer interrupt source, saving the system stack */ +@/* pointer for use in ISR processing later, and finding the first */ +@/* available RAM memory address for tx_application_define. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_initialize_low_level(VOID) +@{ + .global _tx_initialize_low_level + .type _tx_initialize_low_level,function +_tx_initialize_low_level: +@ +@ /* We must be in SVC mode at this point! */ +@ +@ /* Setup various stack pointers. */ +@ + LDR r1, =Image$$ARM_LIB_STACK$$ZI$$Limit @ Get pointer to stack area + +#ifdef TX_ENABLE_IRQ_NESTING +@ +@ /* Setup the system mode stack for nested interrupt support */ +@ + LDR r2, =SYS_STACK_SIZE @ Pickup stack size + MOV r3, #SYS_MODE @ Build SYS mode CPSR + MSR CPSR_c, r3 @ Enter SYS mode + SUB r1, r1, #1 @ Backup 1 byte + BIC r1, r1, #7 @ Ensure 8-byte alignment + MOV sp, r1 @ Setup SYS stack pointer + SUB r1, r1, r2 @ Calculate start of next stack +#endif + + LDR r2, =FIQ_STACK_SIZE @ Pickup stack size + MOV r0, #FIQ_MODE @ Build FIQ mode CPSR + MSR CPSR, r0 @ Enter FIQ mode + SUB r1, r1, #1 @ Backup 1 byte + BIC r1, r1, #7 @ Ensure 8-byte alignment + MOV sp, r1 @ Setup FIQ stack pointer + SUB r1, r1, r2 @ Calculate start of next stack + LDR r2, =IRQ_STACK_SIZE @ Pickup IRQ stack size + MOV r0, #IRQ_MODE @ Build IRQ mode CPSR + MSR CPSR, r0 @ Enter IRQ mode + SUB r1, r1, #1 @ Backup 1 byte + BIC r1, r1, #7 @ Ensure 8-byte alignment + MOV sp, r1 @ Setup IRQ stack pointer + SUB r3, r1, r2 @ Calculate end of IRQ stack + MOV r0, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR, r0 @ Enter SVC mode + LDR r2, =Image$$ARM_LIB_STACK$$Base @ Pickup stack bottom + CMP r3, r2 @ Compare the current stack end with the bottom +_stack_error_loop: + BLT _stack_error_loop @ If the IRQ stack exceeds the stack bottom, just sit here! +@ +@ /* Save the system stack pointer. */ +@ _tx_thread_system_stack_ptr = (VOID_PTR) (sp); +@ + LDR r2, =_tx_thread_system_stack_ptr @ Pickup stack pointer + STR r1, [r2] @ Save the system stack +@ +@ /* Save the first available memory address. */ +@ _tx_initialize_unused_memory = (VOID_PTR) _end; +@ + LDR r1, =Image$$ZI_DATA$$ZI$$Limit @ Get end of non-initialized RAM area + LDR r2, =_tx_initialize_unused_memory @ Pickup unused memory ptr address + ADD r1, r1, #8 @ Increment to next free word + STR r1, [r2] @ Save first free memory address +@ +@ /* Setup Timer for periodic interrupts. */ +@ +@ /* Done, return to caller. */ +@ +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} +@ +@ +@/* Define shells for each of the interrupt vectors. */ +@ + .global __tx_undefined +__tx_undefined: + B __tx_undefined @ Undefined handler +@ + .global __tx_swi_interrupt +__tx_swi_interrupt: + B __tx_swi_interrupt @ Software interrupt handler +@ + .global __tx_prefetch_handler +__tx_prefetch_handler: + B __tx_prefetch_handler @ Prefetch exception handler +@ + .global __tx_abort_handler +__tx_abort_handler: + B __tx_abort_handler @ Abort exception handler +@ + .global __tx_reserved_handler +__tx_reserved_handler: + B __tx_reserved_handler @ Reserved exception handler +@ + .global __tx_irq_processing_return + .type __tx_irq_processing_return,function + .global __tx_irq_handler +__tx_irq_handler: +@ +@ /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return: +@ +@ /* At this point execution is still in the IRQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. In +@ addition, IRQ interrupts may be re-enabled - with certain restrictions - +@ if nested IRQ interrupts are desired. Interrupts may be re-enabled over +@ small code sequences where lr is saved before enabling interrupts and +@ restored after interrupts are again disabled. */ +@ +@ /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +@ from IRQ mode with interrupts disabled. This routine switches to the +@ system mode and returns with IRQ interrupts enabled. +@ +@ NOTE: It is very important to ensure all IRQ interrupts are cleared +@ prior to enabling nested IRQ interrupts. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_start +#endif +@ +@ /* For debug purpose, execute the timer interrupt processing here. In +@ a real system, some kind of status indication would have to be checked +@ before the timer interrupt handler could be called. */ +@ + BL _tx_timer_interrupt @ Timer interrupt handler +@ +@ +@ /* If interrupt nesting was started earlier, the end of interrupt nesting +@ service must be called before returning to _tx_thread_context_restore. +@ This routine returns in processing in IRQ mode with interrupts disabled. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_end +#endif +@ +@ /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore +@ +@ +@ /* This is an example of a vectored IRQ handler. */ +@ +@ .global __tx_example_vectored_irq_handler +@__tx_example_vectored_irq_handler: +@ +@ +@ /* Save initial context and call context save to prepare for +@ vectored ISR execution. */ +@ +@ STMDB sp!, {r0-r3} @ Save some scratch registers +@ MRS r0, SPSR @ Pickup saved SPSR +@ SUB lr, lr, #4 @ Adjust point of interrupt +@ STMDB sp!, {r0, r10, r12, lr} @ Store other scratch registers +@ BL _tx_thread_vectored_context_save @ Vectored context save +@ +@ /* At this point execution is still in the IRQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. In +@ addition, IRQ interrupts may be re-enabled - with certain restrictions - +@ if nested IRQ interrupts are desired. Interrupts may be re-enabled over +@ small code sequences where lr is saved before enabling interrupts and +@ restored after interrupts are again disabled. */ +@ +@ +@ /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +@ from IRQ mode with interrupts disabled. This routine switches to the +@ system mode and returns with IRQ interrupts enabled. +@ +@ NOTE: It is very important to ensure all IRQ interrupts are cleared +@ prior to enabling nested IRQ interrupts. */ +@#ifdef TX_ENABLE_IRQ_NESTING +@ BL _tx_thread_irq_nesting_start +@#endif +@ +@ /* Application IRQ handlers can be called here! */ +@ +@ /* If interrupt nesting was started earlier, the end of interrupt nesting +@ service must be called before returning to _tx_thread_context_restore. +@ This routine returns in processing in IRQ mode with interrupts disabled. */ +@#ifdef TX_ENABLE_IRQ_NESTING +@ BL _tx_thread_irq_nesting_end +@#endif +@ +@ /* Jump to context restore to restore system context. */ +@ B _tx_thread_context_restore +@ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + .global __tx_fiq_handler + .global __tx_fiq_processing_return +__tx_fiq_handler: +@ +@ /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +@ +@ /* At this point execution is still in the FIQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. */ +@ +@ /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +@ from FIQ mode with interrupts disabled. This routine switches to the +@ system mode and returns with FIQ interrupts enabled. +@ +@ NOTE: It is very important to ensure all FIQ interrupts are cleared +@ prior to enabling nested FIQ interrupts. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_start +#endif +@ +@ /* Application FIQ handlers can be called here! */ +@ +@ /* If interrupt nesting was started earlier, the end of interrupt nesting +@ service must be called before returning to _tx_thread_fiq_context_restore. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_end +#endif +@ +@ /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore +@ +@ +#else + .global __tx_fiq_handler +__tx_fiq_handler: + B __tx_fiq_handler @ FIQ interrupt handler +#endif +@ +@ +BUILD_OPTIONS: + .word _tx_build_options @ Reference to bring in +VERSION_ID: + .word _tx_version_id @ Reference to bring in + + + diff --git a/ports/cortex_a15/ac6/example_build/tx/.cproject b/ports/cortex_a15/ac6/example_build/tx/.cproject new file mode 100644 index 00000000..406b2695 --- /dev/null +++ b/ports/cortex_a15/ac6/example_build/tx/.cproject @@ -0,0 +1,212 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_a15/ac6/example_build/tx/.project b/ports/cortex_a15/ac6/example_build/tx/.project new file mode 100644 index 00000000..863ca5cb --- /dev/null +++ b/ports/cortex_a15/ac6/example_build/tx/.project @@ -0,0 +1,48 @@ + + + tx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + inc_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/inc + + + inc_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/inc + + + src_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/src + + + src_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/src + + + diff --git a/ports/cortex_a15/ac6/example_build/tx/.settings/language.settings.xml b/ports/cortex_a15/ac6/example_build/tx/.settings/language.settings.xml new file mode 100644 index 00000000..baea9af2 --- /dev/null +++ b/ports/cortex_a15/ac6/example_build/tx/.settings/language.settings.xml @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_a15/ac6/inc/tx_port.h b/ports/cortex_a15/ac6/inc/tx_port.h new file mode 100644 index 00000000..709e6151 --- /dev/null +++ b/ports/cortex_a15/ac6/inc/tx_port.h @@ -0,0 +1,323 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A15/AC6 */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#if __TARGET_ARCH_ARM > 4 + +#ifndef __thumb__ + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + asm volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); \ + b = 31 - b; +#endif +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifdef __thumb__ + +unsigned int _tx_thread_interrupt_disable(void); +unsigned int _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save, tx_temp; + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); +#else +#define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID i ": "=r" (interrupt_save) ); +#endif + +#define TX_RESTORE asm volatile (" MSR CPSR_c,%0 "::"r" (interrupt_save) ); + +#endif + + +/* Define VFP extension for the Cortex-A15. Each is assumed to be called in the context of the executing + thread. */ + +void tx_thread_vfp_enable(void); +void tx_thread_vfp_disable(void); + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A15/AC6 Version 6.0.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + diff --git a/ports/cortex_a15/ac6/readme_threadx.txt b/ports/cortex_a15/ac6/readme_threadx.txt new file mode 100644 index 00000000..3504587d --- /dev/null +++ b/ports/cortex_a15/ac6/readme_threadx.txt @@ -0,0 +1,342 @@ + Microsoft's Azure RTOS ThreadX for Cortex-A15 + + Using the AC6 Tools + +1. Import the ThreadX Projects + +In order to build the ThreadX library and the ThreadX demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +into your DS workspace. + + +2. Building the ThreadX run-time Library + +Building the ThreadX library is easy; simply right-click the Eclipse project +"tx" and then select the "Build Project" button. You should now observe the compilation +and assembly of the ThreadX library. This project build produces the ThreadX +library file tx.a. + + +3. Demonstration System + +The ThreadX demonstration is designed to execute under the DS debugger on the +VE_Cortex-A15 Bare Metal simulator. + +Building the demonstration is easy; simply right-click the Eclipse project +"sample_threadx" and then select the "Build Project" button. You should now observe +the compilation and assembly of the ThreadX demonstration. This project build produces +the ThreadX library file sample_threadx.axf. Next, expand the demo ThreadX project folder +in the Project Explorer window, right-click on the 'cortex-a15_tx.launch' file, click +'Debug As', and then click 'cortex-a15_tx' from the submenu. This will cause the +debugger to load the sample_threadx.axf ELF file and run to main. You are now ready +to execute the ThreadX demonstration. + + +4. System Initialization + +The entry point in ThreadX for the Cortex-A15 using ARM tools is at label +"Vectors". This is defined within startup.S in the sample_threadx project. In addition, +this is where all static and global pre-set C variable initialization processing +takes place. + +This is also where initialization of a periodic timer interrupt source should take +place. + +In addition, _tx_initialize_low_level defines the first available address +for use by the application, which is supplied as the sole input parameter +to your application definition function, tx_application_define. + + +5. Register Usage and Stack Frames + +The AC6 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread +is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 CPSR CPSR + 0x08 r0 (a1) a15 (v1) + 0x0C r1 (a2) r5 (v2) + 0x10 r2 (a3) r6 (v3) + 0x14 r3 (a4) r7 (v4) + 0x18 a15 (v1) r8 (v5) + 0x1C r5 (v2) r9 (v6) + 0x20 r6 (v3) r10 (v7) + 0x24 r7 (v4) r11 (fp) + 0x28 r8 (v5) r14 (lr) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) + 0x3C r14 (lr) + 0x40 PC + + +6. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-A15 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +7.1 Vector Area + +The Cortex-A15 vectors start at address zero. The demonstration system startup +reset.S file contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. + + +7.2 IRQ ISRs + +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports +nested IRQ interrupts. The following sub-sections define the IRQ capabilities. + + +7.2.1 Standard IRQ ISRs + +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +is the default IRQ handler defined in tx_initialize_low_level.S: + + .global __tx_irq_handler + .global __tx_irq_processing_return +__tx_irq_handler: +@ +@ /* Jump to context save to save system context. */ + B _tx_thread_context_save @ Jump to the context save +__tx_irq_processing_return: +@ +@ /* At this point execution is still in the IRQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. Note +@ that IRQ interrupts are still disabled upon return from the context +@ save function. */ +@ +@ /* Application ISR call(s) go here! */ +@ +@ /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.2 Vectored IRQ ISRs + +The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified +by the particular implementation. The following is an example IRQ handler defined in +tx_initialize_low_level.S: + + .global __tx_irq_example_handler +__tx_irq_example_handler: +@ +@ /* Call context save to save system context. */ + + STMDB sp!, {r0-r3} @ Save some scratch registers + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} @ Store other scratch registers + BL _tx_thread_vectored_context_save @ Call the vectored IRQ context save +@ +@ /* At this point execution is still in the IRQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. Note +@ that IRQ interrupts are still disabled upon return from the context +@ save function. */ +@ +@ /* Application ISR call goes here! */ +@ +@ /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.3 Nested IRQ Support + +By default, nested IRQ interrupt support is not enabled. To enable nested +IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING +defined. With this defined, two new IRQ interrupt management services are +available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. +These function should be called between the IRQ context save and restore +calls. + +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +by switching from IRQ mode to SYS mode and enabling IRQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.S. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in +preparation for the IRQ context restore service. + +The following is an example of enabling IRQ nested interrupts in a standard +IRQ handler: + + .global __tx_irq_handler + .global __tx_irq_processing_return +__tx_irq_handler: +@ +@ /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return: +@ +@ /* Enable nested IRQ interrupts. NOTE: Since this service returns +@ with IRQ interrupts enabled, all IRQ interrupt sources must be +@ cleared prior to calling this service. */ + BL _tx_thread_irq_nesting_start +@ +@ /* Application ISR call(s) go here! */ +@ +@ /* Disable nested IRQ interrupts. The mode is switched back to +@ IRQ mode and IRQ interrupts are disable upon return. */ + BL _tx_thread_irq_nesting_end +@ +@ /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.3 FIQ Interrupts + +By default, FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made +from default FIQ ISRs, which is located in tx_initialize_low_level.S. + + +7.3.1 Managed FIQ Interrupts + +Full ThreadX management of FIQ interrupts is provided if the ThreadX sources +are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built +this way, the FIQ interrupt handlers are very similar to the IRQ interrupt +handlers defined previously. The following is default FIQ handler +defined in tx_initialize_low_level.S: + + + .global __tx_fiq_handler + .global __tx_fiq_processing_return +__tx_fiq_handler: +@ +@ /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +@ +@ /* At this point execution is still in the FIQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. */ +@ +@ /* Application FIQ handlers can be called here! */ +@ +@ /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +7.3.1.1 Nested FIQ Support + +By default, nested FIQ interrupt support is not enabled. To enable nested +FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING +defined. With this defined, two new FIQ interrupt management services are +available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. +These function should be called between the FIQ context save and restore +calls. + +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +by switching from FIQ mode to SYS mode and enabling FIQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.S. When nested FIQ interrupts are no longer required, +calling the _tx_thread_fiq_nesting_end service disables nesting by disabling +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +context restore service. + +The following is an example of enabling FIQ nested interrupts in the +typical FIQ handler: + + + .global __tx_fiq_handler + .global __tx_fiq_processing_return +__tx_fiq_handler: +@ +@ /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +@ +@ /* At this point execution is still in the FIQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. */ +@ +@ /* Enable nested FIQ interrupts. NOTE: Since this service returns +@ with FIQ interrupts enabled, all FIQ interrupt sources must be +@ cleared prior to calling this service. */ + BL _tx_thread_fiq_nesting_start +@ +@ /* Application FIQ handlers can be called here! */ +@ +@ /* Disable nested FIQ interrupts. The mode is switched back to +@ FIQ mode and FIQ interrupts are disable upon return. */ + BL _tx_thread_fiq_nesting_end +@ +@ /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +8. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional but the remainder of +ThreadX will still run. + +To add the timer interrupt processing, simply make a call to +_tx_timer_interrupt in the IRQ processing. An example of this can be +found in the file tx_initialize_low_level.S for the demonstration system. + + +9. VFP Support + +By default, VFP support is disabled for each thread. If saving the context of the VFP registers +is needed, the following API call must be made from the context of the application thread - before +the VFP usage: + +void tx_thread_vfp_enable(void); + +After this API is called in the application, VFP registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the VFP registers +to be saved/restored. + +To disable VFP register context saving, simply call the following API: + +void tx_thread_vfp_disable(void); + + +10. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A15 using AC6 tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_a15/ac6/src/tx_thread_context_restore.S b/ports/cortex_a15/ac6/src/tx_thread_context_restore.S new file mode 100644 index 00000000..8244cb9e --- /dev/null +++ b/ports/cortex_a15/ac6/src/tx_thread_context_restore.S @@ -0,0 +1,256 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ + .arm + +#ifdef TX_ENABLE_FIQ_SUPPORT +SVC_MODE = 0xD3 @ Disable IRQ/FIQ, SVC mode +IRQ_MODE = 0xD2 @ Disable IRQ/FIQ, IRQ mode +#else +SVC_MODE = 0x93 @ Disable IRQ, SVC mode +IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode +#endif +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_restore Cortex-A15/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function restores the interrupt context if it is processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs Interrupt Service Routines */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_restore(VOID) +@{ + .global _tx_thread_context_restore + .type _tx_thread_context_restore,function +_tx_thread_context_restore: +@ +@ /* Lockout interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR exit function to indicate an ISR is complete. */ +@ + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif +@ +@ /* Determine if interrupts are nested. */ +@ if (--_tx_thread_system_state) +@ { +@ + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + SUB r2, r2, #1 @ Decrement the counter + STR r2, [r3] @ Store the counter + CMP r2, #0 @ Was this the first interrupt? + BEQ __tx_thread_not_nested_restore @ If so, not a nested restore +@ +@ /* Interrupts are nested. */ +@ +@ /* Just recover the saved registers and return to the point of +@ interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +__tx_thread_not_nested_restore: +@ +@ /* Determine if a thread was interrupted and no preemption is required. */ +@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +@ || (_tx_thread_preempt_disable)) +@ { +@ + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup actual current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_restore @ Yes, idle system was interrupted +@ + LDR r3, =_tx_thread_preempt_disable @ Pickup preempt disable address + LDR r2, [r3] @ Pickup actual preempt disable flag + CMP r2, #0 @ Is it set? + BNE __tx_thread_no_preempt_restore @ Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr @ Pickup address of execute thread ptr + LDR r2, [r3] @ Pickup actual execute thread pointer + CMP r0, r2 @ Is the same thread highest priority? + BNE __tx_thread_preempt_restore @ No, preemption needs to happen +@ +@ +__tx_thread_no_preempt_restore: +@ +@ /* Restore interrupted thread or ISR. */ +@ +@ /* Pickup the saved stack pointer. */ +@ tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +@ +@ /* Recover the saved context and return to the point of interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +@ else +@ { +__tx_thread_preempt_restore: +@ + LDMIA sp!, {r3, r10, r12, lr} @ Recover temporarily saved registers + MOV r1, lr @ Save lr (point of interrupt) + MOV r2, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r2 @ Enter SVC mode + STR r1, [sp, #-4]! @ Save point of interrupt + STMDB sp!, {r4-r12, lr} @ Save upper half of registers + MOV r4, r3 @ Save SPSR in r4 + MOV r2, #IRQ_MODE @ Build IRQ mode CPSR + MSR CPSR_c, r2 @ Enter IRQ mode + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOV r5, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r5 @ Enter SVC mode + STMDB sp!, {r0-r3} @ Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r2, [r0, #144] @ Pickup the VFP enabled flag + CMP r2, #0 @ Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save @ No, skip VFP IRQ save + VMRS r2, FPSCR @ Pickup the FPSCR + STR r2, [sp, #-4]! @ Save FPSCR + VSTMDB sp!, {D16-D31} @ Save D16-D31 + VSTMDB sp!, {D0-D15} @ Save D0-D15 +_tx_skip_irq_vfp_save: +#endif + + MOV r3, #1 @ Build interrupt stack type + STMDB sp!, {r3, r4} @ Save interrupt stack type and SPSR + STR sp, [r0, #8] @ Save stack pointer in thread control + @ block +@ +@ /* Save the remaining time-slice and disable it. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup time-slice variable address + LDR r2, [r3] @ Pickup time-slice + CMP r2, #0 @ Is it active? + BEQ __tx_thread_dont_save_ts @ No, don't save it +@ +@ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +@ _tx_timer_time_slice = 0; +@ + STR r2, [r0, #24] @ Save thread's time-slice + MOV r2, #0 @ Clear value + STR r2, [r3] @ Disable global time-slice flag +@ +@ } +__tx_thread_dont_save_ts: +@ +@ +@ /* Clear the current task pointer. */ +@ _tx_thread_current_ptr = TX_NULL; +@ + MOV r0, #0 @ NULL value + STR r0, [r1] @ Clear current thread pointer +@ +@ /* Return to the scheduler. */ +@ _tx_thread_schedule(); +@ + B _tx_thread_schedule @ Return to scheduler +@ } +@ +__tx_thread_idle_system_restore: +@ +@ /* Just return back to the scheduler! */ +@ + MOV r0, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r0 @ Enter SVC mode + B _tx_thread_schedule @ Return to scheduler +@} + + + diff --git a/ports/cortex_a15/ac6/src/tx_thread_context_save.S b/ports/cortex_a15/ac6/src/tx_thread_context_save.S new file mode 100644 index 00000000..2592ab22 --- /dev/null +++ b/ports/cortex_a15/ac6/src/tx_thread_context_save.S @@ -0,0 +1,202 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global __tx_irq_processing_return +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_save Cortex-A15/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_save(VOID) +@{ + .global _tx_thread_context_save + .type _tx_thread_context_save,function +_tx_thread_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state++) +@ { +@ + STMDB sp!, {r0-r3} @ Save some working registers +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable FIQ interrupts +#endif + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable +@ +@ /* Save the rest of the scratch registers on the stack and return to the +@ calling ISR. */ +@ + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} @ Store other registers +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_irq_processing_return @ Continue IRQ processing +@ +__tx_thread_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + @ scheduling loop - nothing needs saving! +@ +@ /* Save minimal context of interrupted thread. */ +@ + MRS r2, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r2, r10, r12, lr} @ Store other registers +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr@ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_irq_processing_return @ Continue IRQ processing +@ +@ } +@ else +@ { +@ +__tx_thread_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ processing. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + ADD sp, sp, #16 @ Recover saved registers + B __tx_irq_processing_return @ Continue IRQ processing +@ +@ } +@} + + + diff --git a/ports/cortex_a15/ac6/src/tx_thread_fiq_context_restore.S b/ports/cortex_a15/ac6/src/tx_thread_fiq_context_restore.S new file mode 100644 index 00000000..fb1b9069 --- /dev/null +++ b/ports/cortex_a15/ac6/src/tx_thread_fiq_context_restore.S @@ -0,0 +1,259 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ +SVC_MODE = 0xD3 @ SVC mode +FIQ_MODE = 0xD1 @ FIQ mode +MODE_MASK = 0x1F @ Mode mask +THUMB_MASK = 0x20 @ Thumb bit mask +IRQ_MODE_BITS = 0x12 @ IRQ mode bits +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_system_stack_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_context_restore +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_context_restore Cortex-A15/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function restores the fiq interrupt context when processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* FIQ ISR Interrupt Service Routines */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_fiq_context_restore(VOID) +@{ + .global _tx_thread_fiq_context_restore + .type _tx_thread_fiq_context_restore,function +_tx_thread_fiq_context_restore: +@ +@ /* Lockout interrupts. */ +@ + CPSID if @ Disable IRQ and FIQ interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR exit function to indicate an ISR is complete. */ +@ + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif +@ +@ /* Determine if interrupts are nested. */ +@ if (--_tx_thread_system_state) +@ { +@ + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + SUB r2, r2, #1 @ Decrement the counter + STR r2, [r3] @ Store the counter + CMP r2, #0 @ Was this the first interrupt? + BEQ __tx_thread_fiq_not_nested_restore @ If so, not a nested restore +@ +@ /* Interrupts are nested. */ +@ +@ /* Just recover the saved registers and return to the point of +@ interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +__tx_thread_fiq_not_nested_restore: +@ +@ /* Determine if a thread was interrupted and no preemption is required. */ +@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +@ || (_tx_thread_preempt_disable)) +@ { +@ + LDR r1, [sp] @ Pickup the saved SPSR + MOV r2, #MODE_MASK @ Build mask to isolate the interrupted mode + AND r1, r1, r2 @ Isolate mode bits + CMP r1, #IRQ_MODE_BITS @ Was an interrupt taken in IRQ mode before we + @ got to context save? */ + BEQ __tx_thread_fiq_no_preempt_restore @ Yes, just go back to point of interrupt + + + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup actual current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_fiq_idle_system_restore @ Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable @ Pickup preempt disable address + LDR r2, [r3] @ Pickup actual preempt disable flag + CMP r2, #0 @ Is it set? + BNE __tx_thread_fiq_no_preempt_restore @ Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr @ Pickup address of execute thread ptr + LDR r2, [r3] @ Pickup actual execute thread pointer + CMP r0, r2 @ Is the same thread highest priority? + BNE __tx_thread_fiq_preempt_restore @ No, preemption needs to happen + + +__tx_thread_fiq_no_preempt_restore: +@ +@ /* Restore interrupted thread or ISR. */ +@ +@ /* Pickup the saved stack pointer. */ +@ tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +@ +@ /* Recover the saved context and return to the point of interrupt. */ +@ + LDMIA sp!, {r0, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +@ else +@ { +__tx_thread_fiq_preempt_restore: +@ + LDMIA sp!, {r3, lr} @ Recover temporarily saved registers + MOV r1, lr @ Save lr (point of interrupt) + MOV r2, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r2 @ Enter SVC mode + STR r1, [sp, #-4]! @ Save point of interrupt + STMDB sp!, {r4-r12, lr} @ Save upper half of registers + MOV r4, r3 @ Save SPSR in r4 + MOV r2, #FIQ_MODE @ Build FIQ mode CPSR + MSR CPSR_c, r2 @ Reenter FIQ mode + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOV r5, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r5 @ Enter SVC mode + STMDB sp!, {r0-r3} @ Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r2, [r0, #144] @ Pickup the VFP enabled flag + CMP r2, #0 @ Is the VFP enabled? + BEQ _tx_skip_fiq_vfp_save @ No, skip VFP IRQ save + VMRS r2, FPSCR @ Pickup the FPSCR + STR r2, [sp, #-4]! @ Save FPSCR + VSTMDB sp!, {D16-D31} @ Save D16-D31 + VSTMDB sp!, {D0-D15} @ Save D0-D15 +_tx_skip_fiq_vfp_save: +#endif + + MOV r3, #1 @ Build interrupt stack type + STMDB sp!, {r3, r4} @ Save interrupt stack type and SPSR + STR sp, [r0, #8] @ Save stack pointer in thread control + @ block */ +@ +@ /* Save the remaining time-slice and disable it. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup time-slice variable address + LDR r2, [r3] @ Pickup time-slice + CMP r2, #0 @ Is it active? + BEQ __tx_thread_fiq_dont_save_ts @ No, don't save it +@ +@ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +@ _tx_timer_time_slice = 0; +@ + STR r2, [r0, #24] @ Save thread's time-slice + MOV r2, #0 @ Clear value + STR r2, [r3] @ Disable global time-slice flag +@ +@ } +__tx_thread_fiq_dont_save_ts: +@ +@ +@ /* Clear the current task pointer. */ +@ _tx_thread_current_ptr = TX_NULL; +@ + MOV r0, #0 @ NULL value + STR r0, [r1] @ Clear current thread pointer +@ +@ /* Return to the scheduler. */ +@ _tx_thread_schedule(); +@ + B _tx_thread_schedule @ Return to scheduler +@ } +@ +__tx_thread_fiq_idle_system_restore: +@ +@ /* Just return back to the scheduler! */ +@ + ADD sp, sp, #24 @ Recover FIQ stack space + MOV r3, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r3 @ Lockout interrupts + B _tx_thread_schedule @ Return to scheduler +@ +@} + diff --git a/ports/cortex_a15/ac6/src/tx_thread_fiq_context_save.S b/ports/cortex_a15/ac6/src/tx_thread_fiq_context_save.S new file mode 100644 index 00000000..435b9d6c --- /dev/null +++ b/ports/cortex_a15/ac6/src/tx_thread_fiq_context_save.S @@ -0,0 +1,203 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global __tx_fiq_processing_return +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_context_save +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_context_save Cortex-A15/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@ VOID _tx_thread_fiq_context_save(VOID) +@{ + .global _tx_thread_fiq_context_save + .type _tx_thread_fiq_context_save,function +_tx_thread_fiq_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state++) +@ { +@ + STMDB sp!, {r0-r3} @ Save some working registers + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_fiq_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable +@ +@ /* Save the rest of the scratch registers on the stack and return to the +@ calling ISR. */ +@ + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} @ Store other registers +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_fiq_processing_return @ Continue FIQ processing +@ +__tx_thread_fiq_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_fiq_idle_system_save @ If so, interrupt occurred in +@ @ scheduling loop - nothing needs saving! +@ +@ /* Save minimal context of interrupted thread. */ +@ + MRS r2, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r2, lr} @ Store other registers, Note that we don't +@ @ need to save sl and ip since FIQ has +@ @ copies of these registers. Nested +@ @ interrupt processing does need to save +@ @ these registers. +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr; +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_fiq_processing_return @ Continue FIQ processing +@ +@ } +@ else +@ { +@ +__tx_thread_fiq_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif +@ +@ /* Not much to do here, save the current SPSR and LR for possible +@ use in IRQ interrupted in idle system conditions, and return to +@ FIQ interrupt processing. */ +@ + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, lr} @ Store other registers that will get used +@ @ or stripped off the stack in context +@ @ restore + B __tx_fiq_processing_return @ Continue FIQ processing +@ +@ } +@} + diff --git a/ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_end.S new file mode 100644 index 00000000..2e904342 --- /dev/null +++ b/ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_end.S @@ -0,0 +1,116 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts +#else +DISABLE_INTS = 0x80 @ Disable IRQ interrupts +#endif +MODE_MASK = 0x1F @ Mode mask +FIQ_MODE_BITS = 0x11 @ FIQ mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_end +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_nesting_end Cortex-A15/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from FIQ mode after */ +@/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +@/* processing from system mode back to FIQ mode prior to the ISR */ +@/* calling _tx_thread_fiq_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with FIQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_fiq_nesting_end(VOID) +@{ + .global _tx_thread_fiq_nesting_end + .type _tx_thread_fiq_nesting_end,function +_tx_thread_fiq_nesting_end: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value + MSR CPSR_c, r0 @ Disable interrupts + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + @ 8-byte alignment logic) + BIC r0, r0, #MODE_MASK @ Clear mode bits + ORR r0, r0, #FIQ_MODE_BITS @ Build IRQ mode CPSR + MSR CPSR_c, r0 @ Reenter IRQ mode + +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_start.S new file mode 100644 index 00000000..093fdbd1 --- /dev/null +++ b/ports/cortex_a15/ac6/src/tx_thread_fiq_nesting_start.S @@ -0,0 +1,108 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +FIQ_DISABLE = 0x40 @ FIQ disable bit +MODE_MASK = 0x1F @ Mode mask +SYS_MODE_BITS = 0x1F @ System mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_start +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_nesting_start Cortex-A15/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from FIQ mode after */ +@/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +@/* processing to the system mode so nested FIQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with FIQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_fiq_nesting_start(VOID) +@{ + .global _tx_thread_fiq_nesting_start + .type _tx_thread_fiq_nesting_start,function +_tx_thread_fiq_nesting_start: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + BIC r0, r0, #MODE_MASK @ Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS @ Build system mode CPSR + MSR CPSR_c, r0 @ Enter system mode + STMDB sp!, {r1, lr} @ Push the system mode lr on the system mode stack + @ and push r1 just to keep 8-byte alignment + BIC r0, r0, #FIQ_DISABLE @ Build enable FIQ CPSR + MSR CPSR_c, r0 @ Enter system mode +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_a15/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a15/ac6/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..a2eaab23 --- /dev/null +++ b/ports/cortex_a15/ac6/src/tx_thread_interrupt_control.S @@ -0,0 +1,115 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" */ +@ + +INT_MASK = 0x03F + +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_control for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_interrupt_control +$_tx_thread_interrupt_control: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_interrupt_control @ Call _tx_thread_interrupt_control function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_control Cortex-A15/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for changing the interrupt lockout */ +@/* posture of the system. */ +@/* */ +@/* INPUT */ +@/* */ +@/* new_posture New interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_control(UINT new_posture) +@{ + .global _tx_thread_interrupt_control + .type _tx_thread_interrupt_control,function +_tx_thread_interrupt_control: +@ +@ /* Pickup current interrupt lockout posture. */ +@ + MRS r3, CPSR @ Pickup current CPSR + MOV r2, #INT_MASK @ Build interrupt mask + AND r1, r3, r2 @ Clear interrupt lockout bits + ORR r1, r1, r0 @ Or-in new interrupt lockout bits +@ +@ /* Apply the new interrupt posture. */ +@ + MSR CPSR_c, r1 @ Setup new CPSR + BIC r0, r3, r2 @ Return previous interrupt mask +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + diff --git a/ports/cortex_a15/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a15/ac6/src/tx_thread_interrupt_disable.S new file mode 100644 index 00000000..2e1b80b3 --- /dev/null +++ b/ports/cortex_a15/ac6/src/tx_thread_interrupt_disable.S @@ -0,0 +1,113 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_interrupt_disable +$_tx_thread_interrupt_disable: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_interrupt_disable @ Call _tx_thread_interrupt_disable function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_disable Cortex-A15/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for disabling interrupts */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_disable(void) +@{ + .global _tx_thread_interrupt_disable + .type _tx_thread_interrupt_disable,function +_tx_thread_interrupt_disable: +@ +@ /* Pickup current interrupt lockout posture. */ +@ + MRS r0, CPSR @ Pickup current CPSR +@ +@ /* Mask interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ +#else + CPSID i @ Disable IRQ +#endif + +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + + diff --git a/ports/cortex_a15/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a15/ac6/src/tx_thread_interrupt_restore.S new file mode 100644 index 00000000..e03d69e7 --- /dev/null +++ b/ports/cortex_a15/ac6/src/tx_thread_interrupt_restore.S @@ -0,0 +1,104 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_interrupt_restore +$_tx_thread_interrupt_restore: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_interrupt_restore @ Call _tx_thread_interrupt_restore function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_restore Cortex-A15/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for restoring interrupts to the state */ +@/* returned by a previous _tx_thread_interrupt_disable call. */ +@/* */ +@/* INPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_restore(UINT old_posture) +@{ + .global _tx_thread_interrupt_restore + .type _tx_thread_interrupt_restore,function +_tx_thread_interrupt_restore: +@ +@ /* Apply the new interrupt posture. */ +@ + MSR CPSR_c, r0 @ Setup new CPSR +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + diff --git a/ports/cortex_a15/ac6/src/tx_thread_irq_nesting_end.S b/ports/cortex_a15/ac6/src/tx_thread_irq_nesting_end.S new file mode 100644 index 00000000..a1c16c1a --- /dev/null +++ b/ports/cortex_a15/ac6/src/tx_thread_irq_nesting_end.S @@ -0,0 +1,115 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts +#else +DISABLE_INTS = 0x80 @ Disable IRQ interrupts +#endif +MODE_MASK = 0x1F @ Mode mask +IRQ_MODE_BITS = 0x12 @ IRQ mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_end +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_end Cortex-A15/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +@/* processing from system mode back to IRQ mode prior to the ISR */ +@/* calling _tx_thread_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_irq_nesting_end(VOID) +@{ + .global _tx_thread_irq_nesting_end + .type _tx_thread_irq_nesting_end,function +_tx_thread_irq_nesting_end: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value + MSR CPSR_c, r0 @ Disable interrupts + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + @ 8-byte alignment logic) + BIC r0, r0, #MODE_MASK @ Clear mode bits + ORR r0, r0, #IRQ_MODE_BITS @ Build IRQ mode CPSR + MSR CPSR_c, r0 @ Reenter IRQ mode +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_a15/ac6/src/tx_thread_irq_nesting_start.S b/ports/cortex_a15/ac6/src/tx_thread_irq_nesting_start.S new file mode 100644 index 00000000..34c18567 --- /dev/null +++ b/ports/cortex_a15/ac6/src/tx_thread_irq_nesting_start.S @@ -0,0 +1,108 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +IRQ_DISABLE = 0x80 @ IRQ disable bit +MODE_MASK = 0x1F @ Mode mask +SYS_MODE_BITS = 0x1F @ System mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_start +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_start Cortex-A15/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_context_save has been called and switches the IRQ */ +@/* processing to the system mode so nested IRQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_irq_nesting_start(VOID) +@{ + .global _tx_thread_irq_nesting_start + .type _tx_thread_irq_nesting_start,function +_tx_thread_irq_nesting_start: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + BIC r0, r0, #MODE_MASK @ Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS @ Build system mode CPSR + MSR CPSR_c, r0 @ Enter system mode + STMDB sp!, {r1, lr} @ Push the system mode lr on the system mode stack + @ and push r1 just to keep 8-byte alignment + BIC r0, r0, #IRQ_DISABLE @ Build enable IRQ CPSR + MSR CPSR_c, r0 @ Enter system mode +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_a15/ac6/src/tx_thread_schedule.S b/ports/cortex_a15/ac6/src/tx_thread_schedule.S new file mode 100644 index 00000000..4249d532 --- /dev/null +++ b/ports/cortex_a15/ac6/src/tx_thread_schedule.S @@ -0,0 +1,254 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_execute_ptr + .global _tx_thread_current_ptr + .global _tx_timer_time_slice +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_schedule for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_schedule + .type $_tx_thread_schedule,function +$_tx_thread_schedule: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_schedule @ Call _tx_thread_schedule function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_schedule Cortex-A15/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function waits for a thread control block pointer to appear in */ +@/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +@/* in the variable, the corresponding thread is resumed. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* _tx_thread_system_return Return to system from thread */ +@/* _tx_thread_context_restore Restore thread's context */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_schedule(VOID) +@{ + .global _tx_thread_schedule + .type _tx_thread_schedule,function +_tx_thread_schedule: +@ +@ /* Enable interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSIE if @ Enable IRQ and FIQ interrupts +#else + CPSIE i @ Enable IRQ interrupts +#endif +@ +@ /* Wait for a thread to execute. */ +@ do +@ { + LDR r1, =_tx_thread_execute_ptr @ Address of thread execute ptr +@ +__tx_thread_schedule_loop: +@ + LDR r0, [r1] @ Pickup next thread to execute + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_schedule_loop @ If so, keep looking for a thread +@ +@ } +@ while(_tx_thread_execute_ptr == TX_NULL); +@ +@ /* Yes! We have a thread to execute. Lockout interrupts and +@ transfer control to it. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif +@ +@ /* Setup the current thread pointer. */ +@ _tx_thread_current_ptr = _tx_thread_execute_ptr; +@ + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread + STR r0, [r1] @ Setup current thread pointer +@ +@ /* Increment the run count for this thread. */ +@ _tx_thread_current_ptr -> tx_thread_run_count++; +@ + LDR r2, [r0, #4] @ Pickup run counter + LDR r3, [r0, #24] @ Pickup time-slice for this thread + ADD r2, r2, #1 @ Increment thread run-counter + STR r2, [r0, #4] @ Store the new run counter +@ +@ /* Setup time-slice, if present. */ +@ _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; +@ + LDR r2, =_tx_timer_time_slice @ Pickup address of time-slice + @ variable + LDR sp, [r0, #8] @ Switch stack pointers + STR r3, [r2] @ Setup time-slice +@ +@ /* Switch to the thread's stack. */ +@ sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; +@ +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the thread entry function to indicate the thread is executing. */ +@ + MOV r5, r0 @ Save r0 + BL _tx_execution_thread_enter @ Call the thread execution enter function + MOV r0, r5 @ Restore r0 +#endif +@ +@ /* Determine if an interrupt frame or a synchronous task suspension frame +@ is present. */ +@ + LDMIA sp!, {r4, r5} @ Pickup the stack type and saved CPSR + CMP r4, #0 @ Check for synchronous context switch + BEQ _tx_solicited_return + MSR SPSR_cxsf, r5 @ Setup SPSR for return +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r1, [r0, #144] @ Pickup the VFP enabled flag + CMP r1, #0 @ Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore @ No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} @ Recover D0-D15 + VLDMIA sp!, {D16-D31} @ Recover D16-D31 + LDR r4, [sp], #4 @ Pickup FPSCR + VMSR FPSCR, r4 @ Restore FPSCR +_tx_skip_interrupt_vfp_restore: +#endif + LDMIA sp!, {r0-r12, lr, pc}^ @ Return to point of thread interrupt + +_tx_solicited_return: + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r1, [r0, #144] @ Pickup the VFP enabled flag + CMP r1, #0 @ Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore @ No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} @ Recover D8-D15 + VLDMIA sp!, {D16-D31} @ Recover D16-D31 + LDR r4, [sp], #4 @ Pickup FPSCR + VMSR FPSCR, r4 @ Restore FPSCR +_tx_skip_solicited_vfp_restore: +#endif + MSR CPSR_cxsf, r5 @ Recover CPSR + LDMIA sp!, {r4-r11, lr} @ Return to thread synchronously +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@ +@} +@ + +#ifdef TX_ENABLE_VFP_SUPPORT + + .global tx_thread_vfp_enable + .type tx_thread_vfp_enable,function +tx_thread_vfp_enable: + MRS r2, CPSR @ Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Enable IRQ and FIQ interrupts +#else + CPSID i @ Enable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address + LDR r1, [r0] @ Pickup current thread pointer + CMP r1, #0 @ Check for NULL thread pointer + BEQ __tx_no_thread_to_enable @ If NULL, skip VFP enable + MOV r0, #1 @ Build enable value + STR r0, [r1, #144] @ Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable: + MSR CPSR_cxsf, r2 @ Recover CPSR + BX LR @ Return to caller + + .global tx_thread_vfp_disable + .type tx_thread_vfp_disable,function +tx_thread_vfp_disable: + MRS r2, CPSR @ Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Enable IRQ and FIQ interrupts +#else + CPSID i @ Enable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address + LDR r1, [r0] @ Pickup current thread pointer + CMP r1, #0 @ Check for NULL thread pointer + BEQ __tx_no_thread_to_disable @ If NULL, skip VFP disable + MOV r0, #0 @ Build disable value + STR r0, [r1, #144] @ Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable: + MSR CPSR_cxsf, r2 @ Recover CPSR + BX LR @ Return to caller + +#endif + diff --git a/ports/cortex_a15/ac6/src/tx_thread_stack_build.S b/ports/cortex_a15/ac6/src/tx_thread_stack_build.S new file mode 100644 index 00000000..c09745df --- /dev/null +++ b/ports/cortex_a15/ac6/src/tx_thread_stack_build.S @@ -0,0 +1,178 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ + .arm + +SVC_MODE = 0x13 @ SVC mode +#ifdef TX_ENABLE_FIQ_SUPPORT +CPSR_MASK = 0xDF @ Mask initial CPSR, IRQ & FIQ interrupts enabled +#else +CPSR_MASK = 0x9F @ Mask initial CPSR, IRQ interrupts enabled +#endif +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_stack_build for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .thumb + .global $_tx_thread_stack_build + .type $_tx_thread_stack_build,function +$_tx_thread_stack_build: + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_stack_build @ Call _tx_thread_stack_build function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_stack_build Cortex-A15/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function builds a stack frame on the supplied thread's stack. */ +@/* The stack frame results in a fake interrupt return to the supplied */ +@/* function pointer. */ +@/* */ +@/* INPUT */ +@/* */ +@/* thread_ptr Pointer to thread control blk */ +@/* function_ptr Pointer to return function */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_thread_create Create thread service */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +@{ + .global _tx_thread_stack_build + .type _tx_thread_stack_build,function +_tx_thread_stack_build: +@ +@ +@ /* Build a fake interrupt frame. The form of the fake interrupt stack +@ on the Cortex-A15 should look like the following after it is built: +@ +@ Stack Top: 1 Interrupt stack frame type +@ CPSR Initial value for CPSR +@ a1 (r0) Initial value for a1 +@ a2 (r1) Initial value for a2 +@ a3 (r2) Initial value for a3 +@ a4 (r3) Initial value for a4 +@ v1 (r4) Initial value for v1 +@ v2 (r5) Initial value for v2 +@ v3 (r6) Initial value for v3 +@ v4 (r7) Initial value for v4 +@ v5 (r8) Initial value for v5 +@ sb (r9) Initial value for sb +@ sl (r10) Initial value for sl +@ fp (r11) Initial value for fp +@ ip (r12) Initial value for ip +@ lr (r14) Initial value for lr +@ pc (r15) Initial value for pc +@ 0 For stack backtracing +@ +@ Stack Bottom: (higher memory address) */ +@ + LDR r2, [r0, #16] @ Pickup end of stack area + BIC r2, r2, #7 @ Ensure 8-byte alignment + SUB r2, r2, #76 @ Allocate space for the stack frame +@ +@ /* Actually build the stack frame. */ +@ + MOV r3, #1 @ Build interrupt stack type + STR r3, [r2, #0] @ Store stack type + MOV r3, #0 @ Build initial register value + STR r3, [r2, #8] @ Store initial r0 + STR r3, [r2, #12] @ Store initial r1 + STR r3, [r2, #16] @ Store initial r2 + STR r3, [r2, #20] @ Store initial r3 + STR r3, [r2, #24] @ Store initial r4 + STR r3, [r2, #28] @ Store initial r5 + STR r3, [r2, #32] @ Store initial r6 + STR r3, [r2, #36] @ Store initial r7 + STR r3, [r2, #40] @ Store initial r8 + STR r3, [r2, #44] @ Store initial r9 + LDR r3, [r0, #12] @ Pickup stack starting address + STR r3, [r2, #48] @ Store initial r10 (sl) + LDR r3,=_tx_thread_schedule @ Pickup address of _tx_thread_schedule for GDB backtrace + STR r3, [r2, #60] @ Store initial r14 (lr) + MOV r3, #0 @ Build initial register value + STR r3, [r2, #52] @ Store initial r11 + STR r3, [r2, #56] @ Store initial r12 + STR r1, [r2, #64] @ Store initial pc + STR r3, [r2, #68] @ 0 for back-trace + MRS r1, CPSR @ Pickup CPSR + BIC r1, r1, #CPSR_MASK @ Mask mode bits of CPSR + ORR r3, r1, #SVC_MODE @ Build CPSR, SVC mode, interrupts enabled + STR r3, [r2, #4] @ Store initial CPSR +@ +@ /* Setup stack pointer. */ +@ thread_ptr -> tx_thread_stack_ptr = r2; +@ + STR r2, [r0, #8] @ Save stack pointer in thread's + @ control block +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + + diff --git a/ports/cortex_a15/ac6/src/tx_thread_system_return.S b/ports/cortex_a15/ac6/src/tx_thread_system_return.S new file mode 100644 index 00000000..7cb9450b --- /dev/null +++ b/ports/cortex_a15/ac6/src/tx_thread_system_return.S @@ -0,0 +1,179 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ + .arm +@ +@ + .global _tx_thread_current_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule +@ +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_system_return for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_system_return + .type $_tx_thread_system_return,function +$_tx_thread_system_return: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_system_return @ Call _tx_thread_system_return function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_system_return Cortex-A15/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is target processor specific. It is used to transfer */ +@/* control from a thread back to the ThreadX system. Only a */ +@/* minimal context is saved since the compiler assumes temp registers */ +@/* are going to get slicked by a function call anyway. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling loop */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX components */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_system_return(VOID) +@{ + .global _tx_thread_system_return + .type _tx_thread_system_return,function +_tx_thread_system_return: +@ +@ /* Save minimal context on the stack. */ +@ + STMDB sp!, {r4-r11, lr} @ Save minimal context + + LDR r4, =_tx_thread_current_ptr @ Pickup address of current ptr + LDR r5, [r4] @ Pickup current thread pointer + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r1, [r5, #144] @ Pickup the VFP enabled flag + CMP r1, #0 @ Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save @ No, skip VFP solicited save + VMRS r1, FPSCR @ Pickup the FPSCR + STR r1, [sp, #-4]! @ Save FPSCR + VSTMDB sp!, {D16-D31} @ Save D16-D31 + VSTMDB sp!, {D8-D15} @ Save D8-D15 +_tx_skip_solicited_vfp_save: +#endif + + MOV r0, #0 @ Build a solicited stack type + MRS r1, CPSR @ Pickup the CPSR + STMDB sp!, {r0-r1} @ Save type and CPSR +@ +@ /* Lockout interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the thread exit function to indicate the thread is no longer executing. */ +@ + BL _tx_execution_thread_exit @ Call the thread exit function +#endif + MOV r3, r4 @ Pickup address of current ptr + MOV r0, r5 @ Pickup current thread pointer + LDR r2, =_tx_timer_time_slice @ Pickup address of time slice + LDR r1, [r2] @ Pickup current time slice +@ +@ /* Save current stack and switch to system stack. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ sp = _tx_thread_system_stack_ptr; +@ + STR sp, [r0, #8] @ Save thread stack pointer +@ +@ /* Determine if the time-slice is active. */ +@ if (_tx_timer_time_slice) +@ { +@ + MOV r4, #0 @ Build clear value + CMP r1, #0 @ Is a time-slice active? + BEQ __tx_thread_dont_save_ts @ No, don't save the time-slice +@ +@ /* Save time-slice for the thread and clear the current time-slice. */ +@ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +@ _tx_timer_time_slice = 0; +@ + STR r4, [r2] @ Clear time-slice + STR r1, [r0, #24] @ Save current time-slice +@ +@ } +__tx_thread_dont_save_ts: +@ +@ /* Clear the current thread pointer. */ +@ _tx_thread_current_ptr = TX_NULL; +@ + STR r4, [r3] @ Clear current thread pointer + B _tx_thread_schedule @ Jump to scheduler! +@ +@} + diff --git a/ports/cortex_a15/ac6/src/tx_thread_vectored_context_save.S b/ports/cortex_a15/ac6/src/tx_thread_vectored_context_save.S new file mode 100644 index 00000000..91a9c7b8 --- /dev/null +++ b/ports/cortex_a15/ac6/src/tx_thread_vectored_context_save.S @@ -0,0 +1,189 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr +@ +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_vectored_context_save +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_vectored_context_save Cortex-A15/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_vectored_context_save(VOID) +@{ + .global _tx_thread_vectored_context_save + .type _tx_thread_vectored_context_save,function +_tx_thread_vectored_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state++) +@ { +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#endif + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3, #0] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3, #0] @ Store it back in the variable +@ +@ /* Note: Minimal context of interrupted thread is already saved. */ +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + MOV pc, lr @ Return to caller +@ +__tx_thread_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3, #0] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1, #0] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + @ scheduling loop - nothing needs saving! +@ +@ /* Note: Minimal context of interrupted thread is already saved. */ +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr; +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + MOV pc, lr @ Return to caller +@ +@ } +@ else +@ { +@ +__tx_thread_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ processing. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + ADD sp, sp, #32 @ Recover saved registers + MOV pc, lr @ Return to caller +@ +@ } +@} + diff --git a/ports/cortex_a15/ac6/src/tx_timer_interrupt.S b/ports/cortex_a15/ac6/src/tx_timer_interrupt.S new file mode 100644 index 00000000..41a7a83b --- /dev/null +++ b/ports/cortex_a15/ac6/src/tx_timer_interrupt.S @@ -0,0 +1,279 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Timer */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_timer.h" +@#include "tx_thread.h" +@ +@ + .arm + +@ +@/* Define Assembly language external references... */ +@ + .global _tx_timer_time_slice + .global _tx_timer_system_clock + .global _tx_timer_current_ptr + .global _tx_timer_list_start + .global _tx_timer_list_end + .global _tx_timer_expired_time_slice + .global _tx_timer_expired + .global _tx_thread_time_slice +@ +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_timer_interrupt for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .thumb + .global $_tx_timer_interrupt + .type $_tx_timer_interrupt,function +$_tx_timer_interrupt: + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_timer_interrupt @ Call _tx_timer_interrupt function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_timer_interrupt Cortex-A15/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function processes the hardware timer interrupt. This */ +@/* processing includes incrementing the system clock and checking for */ +@/* time slice and/or timer expiration. If either is found, the */ +@/* interrupt context save/restore functions are called along with the */ +@/* expiration functions. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_time_slice Time slice interrupted thread */ +@/* _tx_timer_expiration_process Timer expiration processing */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* interrupt vector */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_timer_interrupt(VOID) +@{ + .global _tx_timer_interrupt + .type _tx_timer_interrupt,function +_tx_timer_interrupt: +@ +@ /* Upon entry to this routine, it is assumed that context save has already +@ been called, and therefore the compiler scratch registers are available +@ for use. */ +@ +@ /* Increment the system clock. */ +@ _tx_timer_system_clock++; +@ + LDR r1, =_tx_timer_system_clock @ Pickup address of system clock + LDR r0, [r1] @ Pickup system clock + ADD r0, r0, #1 @ Increment system clock + STR r0, [r1] @ Store new system clock +@ +@ /* Test for time-slice expiration. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice + LDR r2, [r3] @ Pickup time-slice + CMP r2, #0 @ Is it non-active? + BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing +@ +@ /* Decrement the time_slice. */ +@ _tx_timer_time_slice--; +@ + SUB r2, r2, #1 @ Decrement the time-slice + STR r2, [r3] @ Store new time-slice value +@ +@ /* Check for expiration. */ +@ if (__tx_timer_time_slice == 0) +@ + CMP r2, #0 @ Has it expired? + BNE __tx_timer_no_time_slice @ No, skip expiration processing +@ +@ /* Set the time-slice expired flag. */ +@ _tx_timer_expired_time_slice = TX_TRUE; +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of expired flag + MOV r0, #1 @ Build expired value + STR r0, [r3] @ Set time-slice expiration flag +@ +@ } +@ +__tx_timer_no_time_slice: +@ +@ /* Test for timer expiration. */ +@ if (*_tx_timer_current_ptr) +@ { +@ + LDR r1, =_tx_timer_current_ptr @ Pickup current timer pointer address + LDR r0, [r1] @ Pickup current timer + LDR r2, [r0] @ Pickup timer list entry + CMP r2, #0 @ Is there anything in the list? + BEQ __tx_timer_no_timer @ No, just increment the timer +@ +@ /* Set expiration flag. */ +@ _tx_timer_expired = TX_TRUE; +@ + LDR r3, =_tx_timer_expired @ Pickup expiration flag address + MOV r2, #1 @ Build expired value + STR r2, [r3] @ Set expired flag + B __tx_timer_done @ Finished timer processing +@ +@ } +@ else +@ { +__tx_timer_no_timer: +@ +@ /* No timer expired, increment the timer pointer. */ +@ _tx_timer_current_ptr++; +@ + ADD r0, r0, #4 @ Move to next timer +@ +@ /* Check for wraparound. */ +@ if (_tx_timer_current_ptr == _tx_timer_list_end) +@ + LDR r3, =_tx_timer_list_end @ Pickup address of timer list end + LDR r2, [r3] @ Pickup list end + CMP r0, r2 @ Are we at list end? + BNE __tx_timer_skip_wrap @ No, skip wraparound logic +@ +@ /* Wrap to beginning of list. */ +@ _tx_timer_current_ptr = _tx_timer_list_start; +@ + LDR r3, =_tx_timer_list_start @ Pickup address of timer list start + LDR r0, [r3] @ Set current pointer to list start +@ +__tx_timer_skip_wrap: +@ + STR r0, [r1] @ Store new current timer pointer +@ } +@ +__tx_timer_done: +@ +@ +@ /* See if anything has expired. */ +@ if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +@ { +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of expired flag + LDR r2, [r3] @ Pickup time-slice expired flag + CMP r2, #0 @ Did a time-slice expire? + BNE __tx_something_expired @ If non-zero, time-slice expired + LDR r1, =_tx_timer_expired @ Pickup address of other expired flag + LDR r0, [r1] @ Pickup timer expired flag + CMP r0, #0 @ Did a timer expire? + BEQ __tx_timer_nothing_expired @ No, nothing expired +@ +__tx_something_expired: +@ +@ + STMDB sp!, {r0, lr} @ Save the lr register on the stack + @ and save r0 just to keep 8-byte alignment +@ +@ /* Did a timer expire? */ +@ if (_tx_timer_expired) +@ { +@ + LDR r1, =_tx_timer_expired @ Pickup address of expired flag + LDR r0, [r1] @ Pickup timer expired flag + CMP r0, #0 @ Check for timer expiration + BEQ __tx_timer_dont_activate @ If not set, skip timer activation +@ +@ /* Process timer expiration. */ +@ _tx_timer_expiration_process(); +@ + BL _tx_timer_expiration_process @ Call the timer expiration handling routine +@ +@ } +__tx_timer_dont_activate: +@ +@ /* Did time slice expire? */ +@ if (_tx_timer_expired_time_slice) +@ { +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of time-slice expired + LDR r2, [r3] @ Pickup the actual flag + CMP r2, #0 @ See if the flag is set + BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing +@ +@ /* Time slice interrupted thread. */ +@ _tx_thread_time_slice(); +@ + BL _tx_thread_time_slice @ Call time-slice processing +@ +@ } +@ +__tx_timer_not_ts_expiration: +@ + LDMIA sp!, {r0, lr} @ Recover lr register (r0 is just there for + @ the 8-byte stack alignment +@ +@ } +@ +__tx_timer_nothing_expired: +@ +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@ +@} + diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.lock b/ports/cortex_a5x/ac6/example_build/.metadata/.lock new file mode 100644 index 00000000..e69de29b diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.log b/ports/cortex_a5x/ac6/example_build/.metadata/.log new file mode 100644 index 00000000..74849e40 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.log @@ -0,0 +1,1195 @@ +!SESSION 2020-06-17 10:59:22.780 ----------------------------------------------- +eclipse.buildId=4.6.3.M20170301-0400 +java.version=1.8.0_45 +java.vendor=Oracle Corporation +BootLoader constants: OS=win32, ARCH=x86_64, WS=win32, NL=en_US +Framework arguments: -product com.arm.ds.ult +Command-line arguments: -os win32 -ws win32 -arch x86_64 -product com.arm.ds.ult + +!ENTRY org.eclipse.core.resources 4 567 2020-06-17 10:59:38.827 +!MESSAGE Workspace restored, but some problems occurred. +!SUBENTRY 1 org.eclipse.core.resources 4 567 2020-06-17 10:59:38.827 +!MESSAGE Could not read metadata for 'RemoteSystemsTempFiles'. +!STACK 1 +org.eclipse.core.internal.resources.ResourceException: The project description file (.project) for 'RemoteSystemsTempFiles' is missing. This file contains important information about the project. The project will not function properly until this file is restored. + at org.eclipse.core.internal.localstore.FileSystemResourceManager.read(FileSystemResourceManager.java:907) + at org.eclipse.core.internal.resources.SaveManager.restoreMetaInfo(SaveManager.java:904) + at org.eclipse.core.internal.resources.SaveManager.restoreMetaInfo(SaveManager.java:884) + at org.eclipse.core.internal.resources.SaveManager.restore(SaveManager.java:735) + at org.eclipse.core.internal.resources.SaveManager.startup(SaveManager.java:1587) + at org.eclipse.core.internal.resources.Workspace.startup(Workspace.java:2399) + at org.eclipse.core.internal.resources.Workspace.open(Workspace.java:2156) + at org.eclipse.core.resources.ResourcesPlugin.start(ResourcesPlugin.java:464) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(Native Method) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.sources.SingleSourcePackage.loadClass(SingleSourcePackage.java:36) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:419) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:357) + at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:139) + at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:388) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:243) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:497) + at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:673) + at org.eclipse.equinox.launcher.Main.basicRun(Main.java:610) + at org.eclipse.equinox.launcher.Main.run(Main.java:1519) + at com.arm.workbench.Hook.run(Hook.java:487) +!SUBENTRY 2 org.eclipse.core.resources 4 567 2020-06-17 10:59:38.829 +!MESSAGE The project description file (.project) for 'RemoteSystemsTempFiles' is missing. This file contains important information about the project. The project will not function properly until this file is restored. +!SUBENTRY 1 org.eclipse.core.resources 4 567 2020-06-17 10:59:38.829 +!MESSAGE Could not read metadata for 'sample_threadx'. +!STACK 1 +org.eclipse.core.internal.resources.ResourceException: The project description file (.project) for 'sample_threadx' is missing. This file contains important information about the project. The project will not function properly until this file is restored. + at org.eclipse.core.internal.localstore.FileSystemResourceManager.read(FileSystemResourceManager.java:907) + at org.eclipse.core.internal.resources.SaveManager.restoreMetaInfo(SaveManager.java:904) + at org.eclipse.core.internal.resources.SaveManager.restoreMetaInfo(SaveManager.java:884) + at org.eclipse.core.internal.resources.SaveManager.restore(SaveManager.java:735) + at org.eclipse.core.internal.resources.SaveManager.startup(SaveManager.java:1587) + at org.eclipse.core.internal.resources.Workspace.startup(Workspace.java:2399) + at org.eclipse.core.internal.resources.Workspace.open(Workspace.java:2156) + at org.eclipse.core.resources.ResourcesPlugin.start(ResourcesPlugin.java:464) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(Native Method) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.sources.SingleSourcePackage.loadClass(SingleSourcePackage.java:36) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:419) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:357) + at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:139) + at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:388) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:243) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:497) + at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:673) + at org.eclipse.equinox.launcher.Main.basicRun(Main.java:610) + at org.eclipse.equinox.launcher.Main.run(Main.java:1519) + at com.arm.workbench.Hook.run(Hook.java:487) +!SUBENTRY 2 org.eclipse.core.resources 4 567 2020-06-17 10:59:38.831 +!MESSAGE The project description file (.project) for 'sample_threadx' is missing. This file contains important information about the project. The project will not function properly until this file is restored. + +!ENTRY org.eclipse.cdt.core 1 0 2020-06-17 10:59:54.322 +!MESSAGE Indexed 'tx' (186 sources, 15 headers) in 5.58 sec: 2,675 declarations; 14,493 references; 0 unresolved inclusions; 6 syntax errors; 0 unresolved names (0%) + +!ENTRY org.python.pydev.shared_core 1 1 2020-06-17 11:00:05.237 +!MESSAGE Unable to track file that does not exist: C:\Program Files\DS-5 v5.24.0\sw\java\lib\charsets.jar +!STACK 0 +java.lang.RuntimeException: Unable to track file that does not exist: C:\Program Files\DS-5 v5.24.0\sw\java\lib\charsets.jar + at org.python.pydev.shared_core.log.Log.logInfo(Log.java:52) + at org.python.pydev.shared_core.path_watch.PathWatch.track(PathWatch.java:316) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:463) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:444) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.registerInterpreterManager(SyncSystemModulesManagerScheduler.java:67) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.start(SyncSystemModulesManagerScheduler.java:89) + at org.python.pydev.plugin.PydevPlugin$1.run(PydevPlugin.java:222) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) + +!ENTRY org.python.pydev.shared_core 1 1 2020-06-17 11:00:05.245 +!MESSAGE Unable to track file that does not exist: C:\Program Files\DS-5 v5.24.0\sw\java\lib\ext\access-bridge-64.jar +!STACK 0 +java.lang.RuntimeException: Unable to track file that does not exist: C:\Program Files\DS-5 v5.24.0\sw\java\lib\ext\access-bridge-64.jar + at org.python.pydev.shared_core.log.Log.logInfo(Log.java:52) + at org.python.pydev.shared_core.path_watch.PathWatch.track(PathWatch.java:316) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:463) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:444) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.registerInterpreterManager(SyncSystemModulesManagerScheduler.java:67) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.start(SyncSystemModulesManagerScheduler.java:89) + at org.python.pydev.plugin.PydevPlugin$1.run(PydevPlugin.java:222) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) + +!ENTRY org.python.pydev.shared_core 1 1 2020-06-17 11:00:05.249 +!MESSAGE Unable to track file that does not exist: C:\Program Files\DS-5 v5.24.0\sw\java\lib\ext\cldrdata.jar +!STACK 0 +java.lang.RuntimeException: Unable to track file that does not exist: C:\Program Files\DS-5 v5.24.0\sw\java\lib\ext\cldrdata.jar + at org.python.pydev.shared_core.log.Log.logInfo(Log.java:52) + at org.python.pydev.shared_core.path_watch.PathWatch.track(PathWatch.java:316) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:463) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:444) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.registerInterpreterManager(SyncSystemModulesManagerScheduler.java:67) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.start(SyncSystemModulesManagerScheduler.java:89) + at org.python.pydev.plugin.PydevPlugin$1.run(PydevPlugin.java:222) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) + +!ENTRY org.python.pydev.shared_core 1 1 2020-06-17 11:00:05.251 +!MESSAGE Unable to track file that does not exist: C:\Program Files\DS-5 v5.24.0\sw\java\lib\ext\dnsns.jar +!STACK 0 +java.lang.RuntimeException: Unable to track file that does not exist: C:\Program Files\DS-5 v5.24.0\sw\java\lib\ext\dnsns.jar + at org.python.pydev.shared_core.log.Log.logInfo(Log.java:52) + at org.python.pydev.shared_core.path_watch.PathWatch.track(PathWatch.java:316) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:463) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:444) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.registerInterpreterManager(SyncSystemModulesManagerScheduler.java:67) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.start(SyncSystemModulesManagerScheduler.java:89) + at org.python.pydev.plugin.PydevPlugin$1.run(PydevPlugin.java:222) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) + +!ENTRY org.python.pydev.shared_core 1 1 2020-06-17 11:00:05.253 +!MESSAGE Unable to track file that does not exist: C:\Program Files\DS-5 v5.24.0\sw\java\lib\ext\jaccess.jar +!STACK 0 +java.lang.RuntimeException: Unable to track file that does not exist: C:\Program Files\DS-5 v5.24.0\sw\java\lib\ext\jaccess.jar + at org.python.pydev.shared_core.log.Log.logInfo(Log.java:52) + at org.python.pydev.shared_core.path_watch.PathWatch.track(PathWatch.java:316) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:463) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:444) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.registerInterpreterManager(SyncSystemModulesManagerScheduler.java:67) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.start(SyncSystemModulesManagerScheduler.java:89) + at org.python.pydev.plugin.PydevPlugin$1.run(PydevPlugin.java:222) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) + +!ENTRY org.python.pydev.shared_core 1 1 2020-06-17 11:00:05.255 +!MESSAGE Unable to track file that does not exist: C:\Program Files\DS-5 v5.24.0\sw\java\lib\ext\jfxrt.jar +!STACK 0 +java.lang.RuntimeException: Unable to track file that does not exist: C:\Program Files\DS-5 v5.24.0\sw\java\lib\ext\jfxrt.jar + at org.python.pydev.shared_core.log.Log.logInfo(Log.java:52) + at org.python.pydev.shared_core.path_watch.PathWatch.track(PathWatch.java:316) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:463) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:444) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.registerInterpreterManager(SyncSystemModulesManagerScheduler.java:67) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.start(SyncSystemModulesManagerScheduler.java:89) + at org.python.pydev.plugin.PydevPlugin$1.run(PydevPlugin.java:222) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) + +!ENTRY org.python.pydev.shared_core 1 1 2020-06-17 11:00:05.259 +!MESSAGE Unable to track file that does not exist: C:\Program Files\DS-5 v5.24.0\sw\java\lib\ext\localedata.jar +!STACK 0 +java.lang.RuntimeException: Unable to track file that does not exist: C:\Program Files\DS-5 v5.24.0\sw\java\lib\ext\localedata.jar + at org.python.pydev.shared_core.log.Log.logInfo(Log.java:52) + at org.python.pydev.shared_core.path_watch.PathWatch.track(PathWatch.java:316) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:463) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:444) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.registerInterpreterManager(SyncSystemModulesManagerScheduler.java:67) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.start(SyncSystemModulesManagerScheduler.java:89) + at org.python.pydev.plugin.PydevPlugin$1.run(PydevPlugin.java:222) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) + +!ENTRY org.python.pydev.shared_core 1 1 2020-06-17 11:00:05.261 +!MESSAGE Unable to track file that does not exist: C:\Program Files\DS-5 v5.24.0\sw\java\lib\ext\nashorn.jar +!STACK 0 +java.lang.RuntimeException: Unable to track file that does not exist: C:\Program Files\DS-5 v5.24.0\sw\java\lib\ext\nashorn.jar + at org.python.pydev.shared_core.log.Log.logInfo(Log.java:52) + at org.python.pydev.shared_core.path_watch.PathWatch.track(PathWatch.java:316) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:463) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:444) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.registerInterpreterManager(SyncSystemModulesManagerScheduler.java:67) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.start(SyncSystemModulesManagerScheduler.java:89) + at org.python.pydev.plugin.PydevPlugin$1.run(PydevPlugin.java:222) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) + +!ENTRY org.python.pydev.shared_core 1 1 2020-06-17 11:00:05.263 +!MESSAGE Unable to track file that does not exist: C:\Program Files\DS-5 v5.24.0\sw\java\lib\ext\sunec.jar +!STACK 0 +java.lang.RuntimeException: Unable to track file that does not exist: C:\Program Files\DS-5 v5.24.0\sw\java\lib\ext\sunec.jar + at org.python.pydev.shared_core.log.Log.logInfo(Log.java:52) + at org.python.pydev.shared_core.path_watch.PathWatch.track(PathWatch.java:316) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:463) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:444) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.registerInterpreterManager(SyncSystemModulesManagerScheduler.java:67) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.start(SyncSystemModulesManagerScheduler.java:89) + at org.python.pydev.plugin.PydevPlugin$1.run(PydevPlugin.java:222) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) + +!ENTRY org.python.pydev.shared_core 1 1 2020-06-17 11:00:05.265 +!MESSAGE Unable to track file that does not exist: C:\Program Files\DS-5 v5.24.0\sw\java\lib\ext\sunjce_provider.jar +!STACK 0 +java.lang.RuntimeException: Unable to track file that does not exist: C:\Program Files\DS-5 v5.24.0\sw\java\lib\ext\sunjce_provider.jar + at org.python.pydev.shared_core.log.Log.logInfo(Log.java:52) + at org.python.pydev.shared_core.path_watch.PathWatch.track(PathWatch.java:316) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:463) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:444) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.registerInterpreterManager(SyncSystemModulesManagerScheduler.java:67) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.start(SyncSystemModulesManagerScheduler.java:89) + at org.python.pydev.plugin.PydevPlugin$1.run(PydevPlugin.java:222) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) + +!ENTRY org.python.pydev.shared_core 1 1 2020-06-17 11:00:05.267 +!MESSAGE Unable to track file that does not exist: C:\Program Files\DS-5 v5.24.0\sw\java\lib\ext\sunmscapi.jar +!STACK 0 +java.lang.RuntimeException: Unable to track file that does not exist: C:\Program Files\DS-5 v5.24.0\sw\java\lib\ext\sunmscapi.jar + at org.python.pydev.shared_core.log.Log.logInfo(Log.java:52) + at org.python.pydev.shared_core.path_watch.PathWatch.track(PathWatch.java:316) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:463) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:444) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.registerInterpreterManager(SyncSystemModulesManagerScheduler.java:67) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.start(SyncSystemModulesManagerScheduler.java:89) + at org.python.pydev.plugin.PydevPlugin$1.run(PydevPlugin.java:222) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) + +!ENTRY org.python.pydev.shared_core 1 1 2020-06-17 11:00:05.269 +!MESSAGE Unable to track file that does not exist: C:\Program Files\DS-5 v5.24.0\sw\java\lib\ext\sunpkcs11.jar +!STACK 0 +java.lang.RuntimeException: Unable to track file that does not exist: C:\Program Files\DS-5 v5.24.0\sw\java\lib\ext\sunpkcs11.jar + at org.python.pydev.shared_core.log.Log.logInfo(Log.java:52) + at org.python.pydev.shared_core.path_watch.PathWatch.track(PathWatch.java:316) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:463) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:444) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.registerInterpreterManager(SyncSystemModulesManagerScheduler.java:67) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.start(SyncSystemModulesManagerScheduler.java:89) + at org.python.pydev.plugin.PydevPlugin$1.run(PydevPlugin.java:222) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) + +!ENTRY org.python.pydev.shared_core 1 1 2020-06-17 11:00:05.272 +!MESSAGE Unable to track file that does not exist: C:\Program Files\DS-5 v5.24.0\sw\java\lib\ext\zipfs.jar +!STACK 0 +java.lang.RuntimeException: Unable to track file that does not exist: C:\Program Files\DS-5 v5.24.0\sw\java\lib\ext\zipfs.jar + at org.python.pydev.shared_core.log.Log.logInfo(Log.java:52) + at org.python.pydev.shared_core.path_watch.PathWatch.track(PathWatch.java:316) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:463) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:444) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.registerInterpreterManager(SyncSystemModulesManagerScheduler.java:67) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.start(SyncSystemModulesManagerScheduler.java:89) + at org.python.pydev.plugin.PydevPlugin$1.run(PydevPlugin.java:222) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) + +!ENTRY org.python.pydev.shared_core 1 1 2020-06-17 11:00:05.274 +!MESSAGE Unable to track file that does not exist: C:\Program Files\DS-5 v5.24.0\sw\java\lib\jce.jar +!STACK 0 +java.lang.RuntimeException: Unable to track file that does not exist: C:\Program Files\DS-5 v5.24.0\sw\java\lib\jce.jar + at org.python.pydev.shared_core.log.Log.logInfo(Log.java:52) + at org.python.pydev.shared_core.path_watch.PathWatch.track(PathWatch.java:316) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:463) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:444) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.registerInterpreterManager(SyncSystemModulesManagerScheduler.java:67) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.start(SyncSystemModulesManagerScheduler.java:89) + at org.python.pydev.plugin.PydevPlugin$1.run(PydevPlugin.java:222) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) + +!ENTRY org.python.pydev.shared_core 1 1 2020-06-17 11:00:05.276 +!MESSAGE Unable to track file that does not exist: C:\Program Files\DS-5 v5.24.0\sw\java\lib\jfr.jar +!STACK 0 +java.lang.RuntimeException: Unable to track file that does not exist: C:\Program Files\DS-5 v5.24.0\sw\java\lib\jfr.jar + at org.python.pydev.shared_core.log.Log.logInfo(Log.java:52) + at org.python.pydev.shared_core.path_watch.PathWatch.track(PathWatch.java:316) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:463) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:444) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.registerInterpreterManager(SyncSystemModulesManagerScheduler.java:67) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.start(SyncSystemModulesManagerScheduler.java:89) + at org.python.pydev.plugin.PydevPlugin$1.run(PydevPlugin.java:222) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) + +!ENTRY org.python.pydev.shared_core 1 1 2020-06-17 11:00:05.278 +!MESSAGE Unable to track file that does not exist: C:\Program Files\DS-5 v5.24.0\sw\java\lib\jsse.jar +!STACK 0 +java.lang.RuntimeException: Unable to track file that does not exist: C:\Program Files\DS-5 v5.24.0\sw\java\lib\jsse.jar + at org.python.pydev.shared_core.log.Log.logInfo(Log.java:52) + at org.python.pydev.shared_core.path_watch.PathWatch.track(PathWatch.java:316) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:463) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:444) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.registerInterpreterManager(SyncSystemModulesManagerScheduler.java:67) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.start(SyncSystemModulesManagerScheduler.java:89) + at org.python.pydev.plugin.PydevPlugin$1.run(PydevPlugin.java:222) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) + +!ENTRY org.python.pydev.shared_core 1 1 2020-06-17 11:00:05.280 +!MESSAGE Unable to track file that does not exist: C:\Program Files\DS-5 v5.24.0\sw\java\lib\resources.jar +!STACK 0 +java.lang.RuntimeException: Unable to track file that does not exist: C:\Program Files\DS-5 v5.24.0\sw\java\lib\resources.jar + at org.python.pydev.shared_core.log.Log.logInfo(Log.java:52) + at org.python.pydev.shared_core.path_watch.PathWatch.track(PathWatch.java:316) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:463) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:444) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.registerInterpreterManager(SyncSystemModulesManagerScheduler.java:67) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.start(SyncSystemModulesManagerScheduler.java:89) + at org.python.pydev.plugin.PydevPlugin$1.run(PydevPlugin.java:222) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) + +!ENTRY org.python.pydev.shared_core 1 1 2020-06-17 11:00:05.281 +!MESSAGE Unable to track file that does not exist: C:\Program Files\DS-5 v5.24.0\sw\java\lib\rt.jar +!STACK 0 +java.lang.RuntimeException: Unable to track file that does not exist: C:\Program Files\DS-5 v5.24.0\sw\java\lib\rt.jar + at org.python.pydev.shared_core.log.Log.logInfo(Log.java:52) + at org.python.pydev.shared_core.path_watch.PathWatch.track(PathWatch.java:316) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:463) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:444) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.registerInterpreterManager(SyncSystemModulesManagerScheduler.java:67) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.start(SyncSystemModulesManagerScheduler.java:89) + at org.python.pydev.plugin.PydevPlugin$1.run(PydevPlugin.java:222) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) + +!ENTRY org.python.pydev.shared_core 1 1 2020-06-17 11:00:05.282 +!MESSAGE Unable to track file that does not exist: C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.debug.interpreter.jython.api_5.27.0.20170426_161840 +!STACK 0 +java.lang.RuntimeException: Unable to track file that does not exist: C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.debug.interpreter.jython.api_5.27.0.20170426_161840 + at org.python.pydev.shared_core.log.Log.logInfo(Log.java:52) + at org.python.pydev.shared_core.path_watch.PathWatch.track(PathWatch.java:316) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:463) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:444) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.registerInterpreterManager(SyncSystemModulesManagerScheduler.java:67) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.start(SyncSystemModulesManagerScheduler.java:89) + at org.python.pydev.plugin.PydevPlugin$1.run(PydevPlugin.java:222) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) + +!ENTRY org.python.pydev.shared_core 1 1 2020-06-17 11:00:05.284 +!MESSAGE Unable to track file that does not exist: C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib +!STACK 0 +java.lang.RuntimeException: Unable to track file that does not exist: C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib + at org.python.pydev.shared_core.log.Log.logInfo(Log.java:52) + at org.python.pydev.shared_core.path_watch.PathWatch.track(PathWatch.java:316) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:463) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:444) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.registerInterpreterManager(SyncSystemModulesManagerScheduler.java:67) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.start(SyncSystemModulesManagerScheduler.java:89) + at org.python.pydev.plugin.PydevPlugin$1.run(PydevPlugin.java:222) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) + +!ENTRY org.python.pydev.shared_core 1 1 2020-06-17 11:00:05.286 +!MESSAGE Unable to track file that does not exist: C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc +!STACK 0 +java.lang.RuntimeException: Unable to track file that does not exist: C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc + at org.python.pydev.shared_core.log.Log.logInfo(Log.java:52) + at org.python.pydev.shared_core.path_watch.PathWatch.track(PathWatch.java:316) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:463) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:444) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.registerInterpreterManager(SyncSystemModulesManagerScheduler.java:67) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.start(SyncSystemModulesManagerScheduler.java:89) + at org.python.pydev.plugin.PydevPlugin$1.run(PydevPlugin.java:222) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) + +!ENTRY org.python.pydev.shared_core 1 1 2020-06-17 11:00:05.287 +!MESSAGE Unable to track file that does not exist: C:\Users\Bill\AppData\Roaming\ARM\DS-5_v5.27.0\workbench\configuration\org.eclipse.osgi\413\0\.cp +!STACK 0 +java.lang.RuntimeException: Unable to track file that does not exist: C:\Users\Bill\AppData\Roaming\ARM\DS-5_v5.27.0\workbench\configuration\org.eclipse.osgi\413\0\.cp + at org.python.pydev.shared_core.log.Log.logInfo(Log.java:52) + at org.python.pydev.shared_core.path_watch.PathWatch.track(PathWatch.java:316) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:463) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.afterSetInfos(SyncSystemModulesManagerScheduler.java:444) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.registerInterpreterManager(SyncSystemModulesManagerScheduler.java:67) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler.start(SyncSystemModulesManagerScheduler.java:89) + at org.python.pydev.plugin.PydevPlugin$1.run(PydevPlugin.java:222) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) + +!ENTRY org.eclipse.egit.ui 2 0 2020-06-17 11:00:05.358 +!MESSAGE Warning: The environment variable HOME is not set. The following directory will be used to store the Git +user global configuration and to define the default location to store repositories: 'C:\Users\nisohack'. If this is +not correct please set the HOME environment variable and restart Eclipse. Otherwise Git for Windows and +EGit might behave differently since they see different configuration options. +This warning can be switched off on the Team > Git > Confirmations and Warnings preference page. + +!ENTRY org.eclipse.jdt.launching 4 4 2020-06-17 11:00:08.584 +!MESSAGE C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_a5x\ac6\example_build\.metadata\.plugins\org.eclipse.jdt.launching\.install.xml (Access is denied) +!STACK 0 +java.io.FileNotFoundException: C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_a5x\ac6\example_build\.metadata\.plugins\org.eclipse.jdt.launching\.install.xml (Access is denied) + at java.io.FileOutputStream.open0(Native Method) + at java.io.FileOutputStream.open(FileOutputStream.java:270) + at java.io.FileOutputStream.(FileOutputStream.java:213) + at java.io.FileOutputStream.(FileOutputStream.java:162) + at org.eclipse.jdt.internal.launching.LaunchingPlugin.writeInstallInfo(LaunchingPlugin.java:1082) + at org.eclipse.jdt.internal.launching.LaunchingPlugin.timeStampChanged(LaunchingPlugin.java:992) + at org.eclipse.jdt.internal.launching.StandardVMType.getLibraryInfo(StandardVMType.java:205) + at org.eclipse.jdt.internal.launching.StandardVMType.getDefaultJavadocLocation(StandardVMType.java:748) + at org.eclipse.jdt.internal.launching.StandardVMType.getDefaultLibraryLocations(StandardVMType.java:429) + at org.eclipse.jdt.internal.launching.StandardVMType.canDetectDefaultSystemLibraries(StandardVMType.java:230) + at org.eclipse.jdt.internal.launching.StandardVMType.getJavaHomeLocation(StandardVMType.java:303) + at org.eclipse.jdt.internal.launching.StandardVMType.detectInstallLocation(StandardVMType.java:257) + at org.eclipse.jdt.launching.JavaRuntime.detectEclipseRuntime(JavaRuntime.java:1792) + at org.eclipse.jdt.launching.JavaRuntime.initializeVMs(JavaRuntime.java:2695) + at org.eclipse.jdt.launching.JavaRuntime.getDefaultVMId(JavaRuntime.java:548) + at org.eclipse.jdt.launching.JavaRuntime.getDefaultVMInstall(JavaRuntime.java:493) + at org.python.copiedfromeclipsesrc.JavaVmLocationFinder$1.call(JavaVmLocationFinder.java:69) + at org.python.copiedfromeclipsesrc.JavaVmLocationFinder.findDefaultJavaExecutable(JavaVmLocationFinder.java:41) + at org.python.pydev.runners.SimpleJythonRunner.runAndGetOutputWithJar(SimpleJythonRunner.java:53) + at org.python.pydev.ui.interpreters.JythonInterpreterManager.doCreateInterpreterInfo(JythonInterpreterManager.java:75) + at org.python.pydev.ui.interpreters.JythonInterpreterManager.internalCreateInterpreterInfo(JythonInterpreterManager.java:47) + at org.python.pydev.ui.interpreters.AbstractInterpreterManager.createInterpreterInfo(AbstractInterpreterManager.java:390) + at com.arm.pydev.StartupListener.updateConfig(StartupListener.java:131) + at com.arm.pydev.StartupListener.earlyStartup(StartupListener.java:81) + at org.eclipse.ui.internal.EarlyStartupRunnable.runEarlyStartup(EarlyStartupRunnable.java:77) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) + +!ENTRY org.python.pydev.shared_core 1 1 2020-06-17 11:00:13.164 +!MESSAGE Restoring info for: C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\lib\jython-2.7.0-standalone.jar +!STACK 0 +java.lang.RuntimeException: Restoring info for: C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\lib\jython-2.7.0-standalone.jar + at org.python.pydev.ui.interpreters.AbstractInterpreterManager.getInterpretersFromPersistedString(AbstractInterpreterManager.java:529) + at org.python.pydev.ui.interpreters.AbstractInterpreterManager.internalRecreateCacheGetInterpreterInfos(AbstractInterpreterManager.java:345) + at org.python.pydev.ui.interpreters.AbstractInterpreterManager.setInfos(AbstractInterpreterManager.java:655) + at com.arm.pydev.StartupListener.updateConfig(StartupListener.java:222) + at com.arm.pydev.StartupListener.earlyStartup(StartupListener.java:81) + at org.eclipse.ui.internal.EarlyStartupRunnable.runEarlyStartup(EarlyStartupRunnable.java:77) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +Caused by: java.io.IOException: Expecting: C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_a5x\ac6\example_build\.metadata\.plugins\org.python.pydev\v1_6mreyygygeqhdt73aqmeprc33\modulesKeys to exist (and be a file). + at org.python.pydev.editor.codecompletion.revisited.ModulesManager.loadFromFile(ModulesManager.java:293) + at org.python.pydev.editor.codecompletion.revisited.SystemModulesManager.load(SystemModulesManager.java:397) + at org.python.pydev.ui.interpreters.AbstractInterpreterManager.getInterpretersFromPersistedString(AbstractInterpreterManager.java:527) + ... 9 more + +!ENTRY org.python.pydev.shared_core 1 1 2020-06-17 11:00:13.724 +!MESSAGE Finished restoring information for: C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\lib\jython-2.7.0-standalone.jar at: C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_a5x\ac6\example_build\.metadata\.plugins\org.python.pydev\v1_6mreyygygeqhdt73aqmeprc33 +!STACK 0 +java.lang.RuntimeException: Finished restoring information for: C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\lib\jython-2.7.0-standalone.jar at: C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_a5x\ac6\example_build\.metadata\.plugins\org.python.pydev\v1_6mreyygygeqhdt73aqmeprc33 + at org.python.pydev.core.log.Log.logInfo(Log.java:66) + at org.python.pydev.ui.interpreters.AbstractInterpreterManager.getInterpretersFromPersistedString(AbstractInterpreterManager.java:574) + at org.python.pydev.ui.interpreters.AbstractInterpreterManager.internalRecreateCacheGetInterpreterInfos(AbstractInterpreterManager.java:345) + at org.python.pydev.ui.interpreters.AbstractInterpreterManager.setInfos(AbstractInterpreterManager.java:655) + at com.arm.pydev.StartupListener.updateConfig(StartupListener.java:222) + at com.arm.pydev.StartupListener.earlyStartup(StartupListener.java:81) + at org.eclipse.ui.internal.EarlyStartupRunnable.runEarlyStartup(EarlyStartupRunnable.java:77) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) + +!ENTRY org.python.pydev.shared_core 4 4 2020-06-17 11:00:14.267 +!MESSAGE Info: Rebuilding internal caches: C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_a5x\ac6\example_build\.metadata\.plugins\com.python.pydev.analysis\jython_v1_6mreyygygeqhdt73aqmeprc33\jython.pydevsysteminfo (Expected error to be provided and got no error!) + +!ENTRY org.eclipse.jdt.launching 4 4 2020-06-17 11:00:20.790 +!MESSAGE C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_a5x\ac6\example_build\.metadata\.plugins\org.eclipse.jdt.launching\.install.xml (Access is denied) +!STACK 0 +java.io.FileNotFoundException: C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_a5x\ac6\example_build\.metadata\.plugins\org.eclipse.jdt.launching\.install.xml (Access is denied) + at java.io.FileOutputStream.open0(Native Method) + at java.io.FileOutputStream.open(FileOutputStream.java:270) + at java.io.FileOutputStream.(FileOutputStream.java:213) + at java.io.FileOutputStream.(FileOutputStream.java:162) + at org.eclipse.jdt.internal.launching.LaunchingPlugin.writeInstallInfo(LaunchingPlugin.java:1082) + at org.eclipse.jdt.internal.launching.LaunchingPlugin.access$0(LaunchingPlugin.java:1055) + at org.eclipse.jdt.internal.launching.LaunchingPlugin$1.saving(LaunchingPlugin.java:550) + at org.eclipse.core.internal.resources.SaveManager.executeLifecycle(SaveManager.java:389) + at org.eclipse.core.internal.resources.SaveManager$1.run(SaveManager.java:198) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.core.internal.resources.SaveManager.broadcastLifecycle(SaveManager.java:201) + at org.eclipse.core.internal.resources.SaveManager.save(SaveManager.java:1186) + at org.eclipse.core.internal.resources.SaveManager.save(SaveManager.java:1165) + at org.eclipse.core.internal.resources.DelayedSnapshotJob.run(DelayedSnapshotJob.java:52) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) + +!ENTRY org.eclipse.jdt.launching 4 4 2020-06-17 11:00:38.365 +!MESSAGE C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_a5x\ac6\example_build\.metadata\.plugins\org.eclipse.jdt.launching\.install.xml (Access is denied) +!STACK 0 +java.io.FileNotFoundException: C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_a5x\ac6\example_build\.metadata\.plugins\org.eclipse.jdt.launching\.install.xml (Access is denied) + at java.io.FileOutputStream.open0(Native Method) + at java.io.FileOutputStream.open(FileOutputStream.java:270) + at java.io.FileOutputStream.(FileOutputStream.java:213) + at java.io.FileOutputStream.(FileOutputStream.java:162) + at org.eclipse.jdt.internal.launching.LaunchingPlugin.writeInstallInfo(LaunchingPlugin.java:1082) + at org.eclipse.jdt.internal.launching.LaunchingPlugin.access$0(LaunchingPlugin.java:1055) + at org.eclipse.jdt.internal.launching.LaunchingPlugin$1.saving(LaunchingPlugin.java:550) + at org.eclipse.core.internal.resources.SaveManager.executeLifecycle(SaveManager.java:389) + at org.eclipse.core.internal.resources.SaveManager$1.run(SaveManager.java:198) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.core.internal.resources.SaveManager.broadcastLifecycle(SaveManager.java:201) + at org.eclipse.core.internal.resources.SaveManager.save(SaveManager.java:1186) + at org.eclipse.core.internal.resources.SaveManager.save(SaveManager.java:1165) + at org.eclipse.core.internal.resources.DelayedSnapshotJob.run(DelayedSnapshotJob.java:52) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) + +!ENTRY org.eclipse.cdt.managedbuilder.core 4 0 2020-06-17 11:00:38.737 +!MESSAGE The resource tree is locked for modifications. +!STACK 1 +org.eclipse.core.internal.resources.ResourceException: The resource tree is locked for modifications. + at org.eclipse.core.internal.resources.WorkManager.checkIn(WorkManager.java:119) + at org.eclipse.core.internal.resources.Workspace.prepareOperation(Workspace.java:2188) + at org.eclipse.core.internal.resources.Resource.deleteMarkers(Resource.java:821) + at org.eclipse.cdt.managedbuilder.core.ToolchainManager.validateAndMark(ToolchainManager.java:126) + at org.eclipse.cdt.managedbuilder.core.ToolchainManager$1.handleEvent(ToolchainManager.java:63) + at org.eclipse.cdt.internal.core.settings.model.CProjectDescriptionManager.notifyListeners(CProjectDescriptionManager.java:2180) + at org.eclipse.cdt.internal.core.settings.model.AbstractCProjectDescriptionStorage.fireLoadedEvent(AbstractCProjectDescriptionStorage.java:268) + at org.eclipse.cdt.internal.core.settings.model.xml.XmlProjectDescriptionStorage.getProjectDescription(XmlProjectDescriptionStorage.java:264) + at org.eclipse.cdt.internal.core.settings.model.CProjectDescriptionManager.getProjectDescriptionInternal(CProjectDescriptionManager.java:426) + at org.eclipse.cdt.internal.core.settings.model.CProjectDescriptionManager.getProjectDescription(CProjectDescriptionManager.java:408) + at org.eclipse.cdt.internal.core.settings.model.CProjectDescriptionManager.getProjectDescription(CProjectDescriptionManager.java:402) + at org.eclipse.cdt.internal.core.settings.model.CProjectDescriptionManager.getProjectDescription(CProjectDescriptionManager.java:395) + at org.eclipse.cdt.internal.core.model.CProject.computeSourceRoots(CProject.java:608) + at org.eclipse.cdt.internal.core.model.CProject.computeChildren(CProject.java:629) + at org.eclipse.cdt.internal.core.model.CProject.buildStructure(CProject.java:593) + at org.eclipse.cdt.internal.core.model.Openable.generateInfos(Openable.java:261) + at org.eclipse.cdt.internal.core.model.CElement.openWhenClosed(CElement.java:427) + at org.eclipse.cdt.internal.core.model.CElement.getElementInfo(CElement.java:305) + at org.eclipse.cdt.internal.core.model.CElement.getElementInfo(CElement.java:295) + at org.eclipse.cdt.internal.core.model.Parent.getChildren(Parent.java:55) + at org.eclipse.cdt.internal.core.model.CProject.getSourceRoots(CProject.java:467) + at org.eclipse.cdt.internal.core.model.CModelManager.create(CModelManager.java:340) + at org.eclipse.cdt.internal.core.model.CModelManager.create(CModelManager.java:268) + at org.eclipse.cdt.internal.core.model.DeltaProcessor.createElement(DeltaProcessor.java:87) + at org.eclipse.cdt.internal.core.model.DeltaProcessor.traverseDelta(DeltaProcessor.java:453) + at org.eclipse.cdt.internal.core.model.DeltaProcessor.traverseDelta(DeltaProcessor.java:471) + at org.eclipse.cdt.internal.core.model.DeltaProcessor.processResourceDelta(DeltaProcessor.java:433) + at org.eclipse.cdt.internal.core.model.CModelManager.resourceChanged(CModelManager.java:922) + at org.eclipse.core.internal.events.NotificationManager$1.run(NotificationManager.java:299) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.core.internal.events.NotificationManager.notify(NotificationManager.java:289) + at org.eclipse.core.internal.events.NotificationManager.broadcastChanges(NotificationManager.java:152) + at org.eclipse.core.internal.resources.Workspace.broadcastPostChange(Workspace.java:374) + at org.eclipse.core.internal.resources.Workspace.endOperation(Workspace.java:1469) + at org.eclipse.core.internal.resources.InternalWorkspaceJob.run(InternalWorkspaceJob.java:46) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +!SUBENTRY 1 org.eclipse.core.resources 4 380 2020-06-17 11:00:38.737 +!MESSAGE The resource tree is locked for modifications. + +!ENTRY org.eclipse.cdt.core 1 0 2020-06-17 11:00:40.440 +!MESSAGE Indexed 'sample_threadx' (3 sources, 8 headers) in 0.286 sec: 1,757 declarations; 1,971 references; 0 unresolved inclusions; 0 syntax errors; 0 unresolved names (0%) + +!ENTRY org.python.pydev.shared_core 4 4 2020-06-17 11:00:41.672 +!MESSAGE The python client still hasn't connected back to the eclipse java vm (will retry...) +!STACK 0 +java.lang.RuntimeException: The python client still hasn't connected back to the eclipse java vm (will retry...) + at org.python.pydev.core.log.Log.log(Log.java:54) + at org.python.pydev.editor.codecompletion.shell.AbstractShell.startIt(AbstractShell.java:334) + at org.python.pydev.editor.codecompletion.shell.ShellsContainer.getServerShell(ShellsContainer.java:232) + at org.python.pydev.editor.codecompletion.shell.ShellsContainer.getServerShell(ShellsContainer.java:165) + at org.python.pydev.editor.codecompletion.shell.AbstractShell.getServerShell(AbstractShell.java:222) + at org.python.pydev.editor.codecompletion.revisited.modules.CompiledModule.createTokensFromServer(CompiledModule.java:372) + at org.python.pydev.editor.codecompletion.revisited.modules.CompiledModule.(CompiledModule.java:176) + at org.python.pydev.editor.codecompletion.revisited.SystemModulesManager.getBuiltinModule(SystemModulesManager.java:332) + at org.python.pydev.editor.codecompletion.revisited.SystemModulesManager.getModule(SystemModulesManager.java:371) + at com.python.pydev.analysis.additionalinfo.AbstractAdditionalDependencyInfo.updateKeysIfNeededAndSave(AbstractAdditionalDependencyInfo.java:256) + at com.python.pydev.analysis.system_info_builder.InterpreterInfoBuilder.syncInfoToPythonPath(InterpreterInfoBuilder.java:154) + at com.python.pydev.analysis.system_info_builder.InterpreterInfoBuilder.syncInfoToPythonPath(InterpreterInfoBuilder.java:80) + at org.python.pydev.editor.codecompletion.revisited.SynchSystemModulesManager.synchronizeManagerToNameToInfoPythonpath(SynchSystemModulesManager.java:390) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler$SynchJob.run(SyncSystemModulesManagerScheduler.java:261) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) + +!ENTRY org.python.pydev.shared_core 4 4 2020-06-17 11:00:46.704 +!MESSAGE Attempt: 2 of 5 failed, trying again...(socket connected: still null) +!STACK 0 +java.lang.RuntimeException: Attempt: 2 of 5 failed, trying again...(socket connected: still null) + at org.python.pydev.core.log.Log.log(Log.java:54) + at org.python.pydev.editor.codecompletion.shell.AbstractShell.startIt(AbstractShell.java:353) + at org.python.pydev.editor.codecompletion.shell.ShellsContainer.getServerShell(ShellsContainer.java:232) + at org.python.pydev.editor.codecompletion.shell.ShellsContainer.getServerShell(ShellsContainer.java:165) + at org.python.pydev.editor.codecompletion.shell.AbstractShell.getServerShell(AbstractShell.java:222) + at org.python.pydev.editor.codecompletion.revisited.modules.CompiledModule.createTokensFromServer(CompiledModule.java:372) + at org.python.pydev.editor.codecompletion.revisited.modules.CompiledModule.(CompiledModule.java:176) + at org.python.pydev.editor.codecompletion.revisited.SystemModulesManager.getBuiltinModule(SystemModulesManager.java:332) + at org.python.pydev.editor.codecompletion.revisited.SystemModulesManager.getModule(SystemModulesManager.java:371) + at com.python.pydev.analysis.additionalinfo.AbstractAdditionalDependencyInfo.updateKeysIfNeededAndSave(AbstractAdditionalDependencyInfo.java:256) + at com.python.pydev.analysis.system_info_builder.InterpreterInfoBuilder.syncInfoToPythonPath(InterpreterInfoBuilder.java:154) + at com.python.pydev.analysis.system_info_builder.InterpreterInfoBuilder.syncInfoToPythonPath(InterpreterInfoBuilder.java:80) + at org.python.pydev.editor.codecompletion.revisited.SynchSystemModulesManager.synchronizeManagerToNameToInfoPythonpath(SynchSystemModulesManager.java:390) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler$SynchJob.run(SyncSystemModulesManagerScheduler.java:261) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) + +!ENTRY org.eclipse.jdt.launching 4 4 2020-06-17 11:01:05.184 +!MESSAGE C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_a5x\ac6\example_build\.metadata\.plugins\org.eclipse.jdt.launching\.install.xml (Access is denied) +!STACK 0 +java.io.FileNotFoundException: C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_a5x\ac6\example_build\.metadata\.plugins\org.eclipse.jdt.launching\.install.xml (Access is denied) + at java.io.FileOutputStream.open0(Native Method) + at java.io.FileOutputStream.open(FileOutputStream.java:270) + at java.io.FileOutputStream.(FileOutputStream.java:213) + at java.io.FileOutputStream.(FileOutputStream.java:162) + at org.eclipse.jdt.internal.launching.LaunchingPlugin.writeInstallInfo(LaunchingPlugin.java:1082) + at org.eclipse.jdt.internal.launching.LaunchingPlugin.access$0(LaunchingPlugin.java:1055) + at org.eclipse.jdt.internal.launching.LaunchingPlugin$1.saving(LaunchingPlugin.java:550) + at org.eclipse.core.internal.resources.SaveManager.executeLifecycle(SaveManager.java:389) + at org.eclipse.core.internal.resources.SaveManager$1.run(SaveManager.java:198) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.core.internal.resources.SaveManager.broadcastLifecycle(SaveManager.java:201) + at org.eclipse.core.internal.resources.SaveManager.save(SaveManager.java:1186) + at org.eclipse.core.internal.resources.Workspace.save(Workspace.java:2283) + at org.eclipse.ui.internal.ide.application.IDEWorkbenchAdvisor$4.run(IDEWorkbenchAdvisor.java:456) + at org.eclipse.jface.operation.ModalContext$ModalContextThread.run(ModalContext.java:119) +!SESSION 2020-06-17 11:02:45.647 ----------------------------------------------- +eclipse.buildId=4.6.3.M20170301-0400 +java.version=1.8.0_45 +java.vendor=Oracle Corporation +BootLoader constants: OS=win32, ARCH=x86_64, WS=win32, NL=en_US +Framework arguments: -product com.arm.ds.ult +Command-line arguments: -os win32 -ws win32 -arch x86_64 -product com.arm.ds.ult + +!ENTRY org.eclipse.egit.ui 2 0 2020-06-17 11:03:07.493 +!MESSAGE Warning: The environment variable HOME is not set. The following directory will be used to store the Git +user global configuration and to define the default location to store repositories: 'C:\Users\nisohack'. If this is +not correct please set the HOME environment variable and restart Eclipse. Otherwise Git for Windows and +EGit might behave differently since they see different configuration options. +This warning can be switched off on the Team > Git > Confirmations and Warnings preference page. + +!ENTRY org.eclipse.jdt.launching 4 4 2020-06-17 11:03:42.902 +!MESSAGE C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_a5x\ac6\example_build\.metadata\.plugins\org.eclipse.jdt.launching\.install.xml (Access is denied) +!STACK 0 +java.io.FileNotFoundException: C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_a5x\ac6\example_build\.metadata\.plugins\org.eclipse.jdt.launching\.install.xml (Access is denied) + at java.io.FileOutputStream.open0(Native Method) + at java.io.FileOutputStream.open(FileOutputStream.java:270) + at java.io.FileOutputStream.(FileOutputStream.java:213) + at java.io.FileOutputStream.(FileOutputStream.java:162) + at org.eclipse.jdt.internal.launching.LaunchingPlugin.writeInstallInfo(LaunchingPlugin.java:1082) + at org.eclipse.jdt.internal.launching.LaunchingPlugin.timeStampChanged(LaunchingPlugin.java:992) + at org.eclipse.jdt.internal.launching.VMDefinitionsContainer.populateVMForType(VMDefinitionsContainer.java:557) + at org.eclipse.jdt.internal.launching.VMDefinitionsContainer.populateVMTypes(VMDefinitionsContainer.java:494) + at org.eclipse.jdt.internal.launching.VMDefinitionsContainer.parseXMLIntoContainer(VMDefinitionsContainer.java:473) + at org.eclipse.jdt.launching.JavaRuntime.addPersistedVMs(JavaRuntime.java:1499) + at org.eclipse.jdt.launching.JavaRuntime.initializeVMs(JavaRuntime.java:2671) + at org.eclipse.jdt.launching.JavaRuntime.getDefaultVMId(JavaRuntime.java:548) + at org.eclipse.jdt.launching.JavaRuntime.getDefaultVMInstall(JavaRuntime.java:493) + at org.python.copiedfromeclipsesrc.JavaVmLocationFinder$1.call(JavaVmLocationFinder.java:69) + at org.python.copiedfromeclipsesrc.JavaVmLocationFinder.findDefaultJavaExecutable(JavaVmLocationFinder.java:41) + at org.python.pydev.runners.SimpleJythonRunner.runAndGetOutputWithJar(SimpleJythonRunner.java:53) + at org.python.pydev.ui.interpreters.JythonInterpreterManager.doCreateInterpreterInfo(JythonInterpreterManager.java:75) + at org.python.pydev.ui.interpreters.JythonInterpreterManager.internalCreateInterpreterInfo(JythonInterpreterManager.java:47) + at org.python.pydev.ui.interpreters.AbstractInterpreterManager.createInterpreterInfo(AbstractInterpreterManager.java:390) + at org.python.pydev.editor.codecompletion.revisited.SynchSystemModulesManager$CreateInterpreterInfoCallback.createInterpreterInfo(SynchSystemModulesManager.java:173) + at org.python.pydev.editor.codecompletion.revisited.SynchSystemModulesManager.updateStructures(SynchSystemModulesManager.java:252) + at org.python.pydev.editor.codecompletion.revisited.SyncSystemModulesManagerScheduler$SynchJob.run(SyncSystemModulesManagerScheduler.java:238) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) + +!ENTRY org.eclipse.jdt.launching 4 4 2020-06-17 11:08:16.585 +!MESSAGE C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_a5x\ac6\example_build\.metadata\.plugins\org.eclipse.jdt.launching\.install.xml (Access is denied) +!STACK 0 +java.io.FileNotFoundException: C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_a5x\ac6\example_build\.metadata\.plugins\org.eclipse.jdt.launching\.install.xml (Access is denied) + at java.io.FileOutputStream.open0(Native Method) + at java.io.FileOutputStream.open(FileOutputStream.java:270) + at java.io.FileOutputStream.(FileOutputStream.java:213) + at java.io.FileOutputStream.(FileOutputStream.java:162) + at org.eclipse.jdt.internal.launching.LaunchingPlugin.writeInstallInfo(LaunchingPlugin.java:1082) + at org.eclipse.jdt.internal.launching.LaunchingPlugin.access$0(LaunchingPlugin.java:1055) + at org.eclipse.jdt.internal.launching.LaunchingPlugin$1.saving(LaunchingPlugin.java:550) + at org.eclipse.core.internal.resources.SaveManager.executeLifecycle(SaveManager.java:389) + at org.eclipse.core.internal.resources.SaveManager$1.run(SaveManager.java:198) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.core.internal.resources.SaveManager.broadcastLifecycle(SaveManager.java:201) + at org.eclipse.core.internal.resources.SaveManager.save(SaveManager.java:1186) + at org.eclipse.core.internal.resources.SaveManager.save(SaveManager.java:1165) + at org.eclipse.core.internal.resources.DelayedSnapshotJob.run(DelayedSnapshotJob.java:52) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) + +!ENTRY org.eclipse.jdt.launching 4 4 2020-06-17 13:52:12.068 +!MESSAGE C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_a5x\ac6\example_build\.metadata\.plugins\org.eclipse.jdt.launching\.install.xml (Access is denied) +!STACK 0 +java.io.FileNotFoundException: C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_a5x\ac6\example_build\.metadata\.plugins\org.eclipse.jdt.launching\.install.xml (Access is denied) + at java.io.FileOutputStream.open0(Native Method) + at java.io.FileOutputStream.open(FileOutputStream.java:270) + at java.io.FileOutputStream.(FileOutputStream.java:213) + at java.io.FileOutputStream.(FileOutputStream.java:162) + at org.eclipse.jdt.internal.launching.LaunchingPlugin.writeInstallInfo(LaunchingPlugin.java:1082) + at org.eclipse.jdt.internal.launching.LaunchingPlugin.access$0(LaunchingPlugin.java:1055) + at org.eclipse.jdt.internal.launching.LaunchingPlugin$1.saving(LaunchingPlugin.java:550) + at org.eclipse.core.internal.resources.SaveManager.executeLifecycle(SaveManager.java:389) + at org.eclipse.core.internal.resources.SaveManager$1.run(SaveManager.java:198) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.core.internal.resources.SaveManager.broadcastLifecycle(SaveManager.java:201) + at org.eclipse.core.internal.resources.SaveManager.save(SaveManager.java:1186) + at org.eclipse.core.internal.resources.SaveManager.save(SaveManager.java:1165) + at org.eclipse.core.internal.resources.DelayedSnapshotJob.run(DelayedSnapshotJob.java:52) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) + +!ENTRY org.eclipse.jdt.launching 4 4 2020-06-17 13:58:25.334 +!MESSAGE C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_a5x\ac6\example_build\.metadata\.plugins\org.eclipse.jdt.launching\.install.xml (Access is denied) +!STACK 0 +java.io.FileNotFoundException: C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_a5x\ac6\example_build\.metadata\.plugins\org.eclipse.jdt.launching\.install.xml (Access is denied) + at java.io.FileOutputStream.open0(Native Method) + at java.io.FileOutputStream.open(FileOutputStream.java:270) + at java.io.FileOutputStream.(FileOutputStream.java:213) + at java.io.FileOutputStream.(FileOutputStream.java:162) + at org.eclipse.jdt.internal.launching.LaunchingPlugin.writeInstallInfo(LaunchingPlugin.java:1082) + at org.eclipse.jdt.internal.launching.LaunchingPlugin.access$0(LaunchingPlugin.java:1055) + at org.eclipse.jdt.internal.launching.LaunchingPlugin$1.saving(LaunchingPlugin.java:550) + at org.eclipse.core.internal.resources.SaveManager.executeLifecycle(SaveManager.java:389) + at org.eclipse.core.internal.resources.SaveManager$1.run(SaveManager.java:198) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.core.internal.resources.SaveManager.broadcastLifecycle(SaveManager.java:201) + at org.eclipse.core.internal.resources.SaveManager.save(SaveManager.java:1186) + at org.eclipse.core.internal.resources.SaveManager.save(SaveManager.java:1165) + at org.eclipse.core.internal.resources.DelayedSnapshotJob.run(DelayedSnapshotJob.java:52) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) + +!ENTRY org.eclipse.jdt.launching 4 4 2020-06-17 14:29:32.344 +!MESSAGE C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_a5x\ac6\example_build\.metadata\.plugins\org.eclipse.jdt.launching\.install.xml (Access is denied) +!STACK 0 +java.io.FileNotFoundException: C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_a5x\ac6\example_build\.metadata\.plugins\org.eclipse.jdt.launching\.install.xml (Access is denied) + at java.io.FileOutputStream.open0(Native Method) + at java.io.FileOutputStream.open(FileOutputStream.java:270) + at java.io.FileOutputStream.(FileOutputStream.java:213) + at java.io.FileOutputStream.(FileOutputStream.java:162) + at org.eclipse.jdt.internal.launching.LaunchingPlugin.writeInstallInfo(LaunchingPlugin.java:1082) + at org.eclipse.jdt.internal.launching.LaunchingPlugin.access$0(LaunchingPlugin.java:1055) + at org.eclipse.jdt.internal.launching.LaunchingPlugin$1.saving(LaunchingPlugin.java:550) + at org.eclipse.core.internal.resources.SaveManager.executeLifecycle(SaveManager.java:389) + at org.eclipse.core.internal.resources.SaveManager$1.run(SaveManager.java:198) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.core.internal.resources.SaveManager.broadcastLifecycle(SaveManager.java:201) + at org.eclipse.core.internal.resources.SaveManager.save(SaveManager.java:1186) + at org.eclipse.core.internal.resources.Workspace.save(Workspace.java:2283) + at org.eclipse.ui.internal.ide.application.IDEWorkbenchAdvisor$4.run(IDEWorkbenchAdvisor.java:456) + at org.eclipse.jface.operation.ModalContext$ModalContextThread.run(ModalContext.java:119) +!SESSION 2020-07-24 13:46:29.714 ----------------------------------------------- +eclipse.buildId=4.6.3.M20170301-0400 +java.version=1.8.0_45 +java.vendor=Oracle Corporation +BootLoader constants: OS=win32, ARCH=x86_64, WS=win32, NL=en_US +Framework arguments: -product com.arm.ds.ult +Command-line arguments: -os win32 -ws win32 -arch x86_64 -product com.arm.ds.ult + +!ENTRY org.eclipse.core.resources 4 567 2020-07-24 13:46:36.836 +!MESSAGE Workspace restored, but some problems occurred. +!SUBENTRY 1 org.eclipse.core.resources 4 567 2020-07-24 13:46:36.836 +!MESSAGE Could not read metadata for 'RemoteSystemsTempFiles'. +!STACK 1 +org.eclipse.core.internal.resources.ResourceException(C:/Users/nisohack/Documents/work/x-ware_libs/threadx/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.resources/.projects/RemoteSystemsTempFiles/1.tree)[568]: java.io.FileNotFoundException: C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a5x\ac6\example_build\.metadata\.plugins\org.eclipse.core.resources\.projects\RemoteSystemsTempFiles\1.tree (The system cannot find the path specified) + at java.io.FileOutputStream.open0(Native Method) + at java.io.FileOutputStream.open(FileOutputStream.java:270) + at java.io.FileOutputStream.(FileOutputStream.java:213) + at java.io.FileOutputStream.(FileOutputStream.java:162) + at org.eclipse.core.internal.localstore.SafeFileOutputStream.(SafeFileOutputStream.java:51) + at org.eclipse.core.internal.resources.SaveManager.writeTree(SaveManager.java:2107) + at org.eclipse.core.internal.resources.SaveManager.restoreMetaInfo(SaveManager.java:924) + at org.eclipse.core.internal.resources.SaveManager.restoreMetaInfo(SaveManager.java:884) + at org.eclipse.core.internal.resources.SaveManager.restore(SaveManager.java:735) + at org.eclipse.core.internal.resources.SaveManager.startup(SaveManager.java:1587) + at org.eclipse.core.internal.resources.Workspace.startup(Workspace.java:2399) + at org.eclipse.core.internal.resources.Workspace.open(Workspace.java:2156) + at org.eclipse.core.resources.ResourcesPlugin.start(ResourcesPlugin.java:464) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(Native Method) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.sources.SingleSourcePackage.loadClass(SingleSourcePackage.java:36) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:419) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:357) + at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:139) + at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:388) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:243) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:497) + at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:673) + at org.eclipse.equinox.launcher.Main.basicRun(Main.java:610) + at org.eclipse.equinox.launcher.Main.run(Main.java:1519) + at com.arm.workbench.Hook.run(Hook.java:487) +!SUBENTRY 2 org.eclipse.core.resources 4 568 2020-07-24 13:46:36.836 +!MESSAGE Could not write metadata for '/RemoteSystemsTempFiles'. +!STACK 0 +java.io.FileNotFoundException: C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a5x\ac6\example_build\.metadata\.plugins\org.eclipse.core.resources\.projects\RemoteSystemsTempFiles\1.tree (The system cannot find the path specified) + at java.io.FileOutputStream.open0(Native Method) + at java.io.FileOutputStream.open(FileOutputStream.java:270) + at java.io.FileOutputStream.(FileOutputStream.java:213) + at java.io.FileOutputStream.(FileOutputStream.java:162) + at org.eclipse.core.internal.localstore.SafeFileOutputStream.(SafeFileOutputStream.java:51) + at org.eclipse.core.internal.resources.SaveManager.writeTree(SaveManager.java:2107) + at org.eclipse.core.internal.resources.SaveManager.restoreMetaInfo(SaveManager.java:924) + at org.eclipse.core.internal.resources.SaveManager.restoreMetaInfo(SaveManager.java:884) + at org.eclipse.core.internal.resources.SaveManager.restore(SaveManager.java:735) + at org.eclipse.core.internal.resources.SaveManager.startup(SaveManager.java:1587) + at org.eclipse.core.internal.resources.Workspace.startup(Workspace.java:2399) + at org.eclipse.core.internal.resources.Workspace.open(Workspace.java:2156) + at org.eclipse.core.resources.ResourcesPlugin.start(ResourcesPlugin.java:464) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(Native Method) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.sources.SingleSourcePackage.loadClass(SingleSourcePackage.java:36) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:419) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:357) + at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:139) + at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:388) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:243) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:497) + at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:673) + at org.eclipse.equinox.launcher.Main.basicRun(Main.java:610) + at org.eclipse.equinox.launcher.Main.run(Main.java:1519) + at com.arm.workbench.Hook.run(Hook.java:487) + +!ENTRY org.eclipse.core.resources 4 1 2020-07-24 13:46:42.164 +!MESSAGE Problems occurred while refreshing local changes +!SUBENTRY 1 org.eclipse.core.resources 4 1 2020-07-24 13:46:42.164 +!MESSAGE Problems occurred while refreshing local changes +!STACK 1 +org.eclipse.core.internal.resources.ResourceException: Errors occurred while refreshing resources with the local file system. + at org.eclipse.core.internal.localstore.FileSystemResourceManager.refreshResource(FileSystemResourceManager.java:977) + at org.eclipse.core.internal.localstore.FileSystemResourceManager.refresh(FileSystemResourceManager.java:960) + at org.eclipse.core.internal.resources.Resource.refreshLocal(Resource.java:1594) + at org.eclipse.core.internal.refresh.RefreshJob.runInWorkspace(RefreshJob.java:163) + at org.eclipse.core.internal.resources.InternalWorkspaceJob.run(InternalWorkspaceJob.java:39) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +Contains: The project description file (.project) for 'RemoteSystemsTempFiles' is missing. This file contains important information about the project. The project will not function properly until this file is restored. +!SUBENTRY 2 org.eclipse.core.resources 4 271 2020-07-24 13:46:42.164 +!MESSAGE Errors occurred while refreshing resources with the local file system. +!SUBENTRY 3 org.eclipse.core.resources 4 567 2020-07-24 13:46:42.164 +!MESSAGE The project description file (.project) for 'RemoteSystemsTempFiles' is missing. This file contains important information about the project. The project will not function properly until this file is restored. + +!ENTRY org.python.pydev.shared_core 1 1 2020-07-24 13:46:56.261 +!MESSAGE Restoring info for: C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\lib\jython-2.7.0-standalone.jar +!STACK 0 +java.lang.RuntimeException: Restoring info for: C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\lib\jython-2.7.0-standalone.jar + at org.python.pydev.ui.interpreters.AbstractInterpreterManager.getInterpretersFromPersistedString(AbstractInterpreterManager.java:529) + at org.python.pydev.ui.interpreters.AbstractInterpreterManager.internalRecreateCacheGetInterpreterInfos(AbstractInterpreterManager.java:345) + at org.python.pydev.ui.interpreters.AbstractInterpreterManager.getInterpreterInfos(AbstractInterpreterManager.java:332) + at org.python.pydev.ui.interpreters.AbstractInterpreterManager.(AbstractInterpreterManager.java:185) + at org.python.pydev.ui.interpreters.JythonInterpreterManager.(JythonInterpreterManager.java:31) + at org.python.pydev.plugin.PydevPlugin.start(PydevPlugin.java:246) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(Native Method) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:357) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.navigator.filters.CommonFilterDescriptor$1.run(CommonFilterDescriptor.java:139) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.navigator.filters.CommonFilterDescriptor.createFilter(CommonFilterDescriptor.java:119) + at org.eclipse.ui.internal.navigator.NavigatorFilterService.getViewerFilter(NavigatorFilterService.java:177) + at org.eclipse.ui.internal.navigator.NavigatorFilterService.getVisibleFilters(NavigatorFilterService.java:146) + at org.eclipse.ui.navigator.CommonNavigator.createPartControl(CommonNavigator.java:195) + at org.eclipse.ui.navigator.resources.ProjectExplorer.createPartControl(ProjectExplorer.java:88) + at org.eclipse.ui.internal.e4.compatibility.CompatibilityPart.createPartControl(CompatibilityPart.java:150) + at org.eclipse.ui.internal.e4.compatibility.CompatibilityView.createPartControl(CompatibilityView.java:143) + at org.eclipse.ui.internal.e4.compatibility.CompatibilityPart.create(CompatibilityPart.java:340) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:497) + at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:55) + at org.eclipse.e4.core.internal.di.InjectorImpl.processAnnotated(InjectorImpl.java:966) + at org.eclipse.e4.core.internal.di.InjectorImpl.processAnnotated(InjectorImpl.java:931) + at org.eclipse.e4.core.internal.di.InjectorImpl.inject(InjectorImpl.java:151) + at org.eclipse.e4.core.internal.di.InjectorImpl.internalMake(InjectorImpl.java:375) + at org.eclipse.e4.core.internal.di.InjectorImpl.make(InjectorImpl.java:294) + at org.eclipse.e4.core.contexts.ContextInjectionFactory.make(ContextInjectionFactory.java:162) + at org.eclipse.e4.ui.internal.workbench.ReflectionContributionFactory.createFromBundle(ReflectionContributionFactory.java:105) + at org.eclipse.e4.ui.internal.workbench.ReflectionContributionFactory.doCreate(ReflectionContributionFactory.java:74) + at org.eclipse.e4.ui.internal.workbench.ReflectionContributionFactory.create(ReflectionContributionFactory.java:56) + at org.eclipse.e4.ui.workbench.renderers.swt.ContributedPartRenderer.createWidget(ContributedPartRenderer.java:129) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createWidget(PartRenderingEngine.java:975) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:651) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$1.run(PartRenderingEngine.java:536) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:520) + at org.eclipse.e4.ui.workbench.renderers.swt.ElementReferenceRenderer.createWidget(ElementReferenceRenderer.java:70) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createWidget(PartRenderingEngine.java:975) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:651) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:757) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$0(PartRenderingEngine.java:728) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$2.run(PartRenderingEngine.java:722) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:706) + at org.eclipse.e4.ui.workbench.renderers.swt.StackRenderer.showTab(StackRenderer.java:1324) + at org.eclipse.e4.ui.workbench.renderers.swt.LazyStackRenderer.postProcess(LazyStackRenderer.java:103) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:669) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:757) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$0(PartRenderingEngine.java:728) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$2.run(PartRenderingEngine.java:722) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:706) + at org.eclipse.e4.ui.workbench.renderers.swt.SWTPartRenderer.processContents(SWTPartRenderer.java:70) + at org.eclipse.e4.ui.workbench.renderers.swt.SashRenderer.processContents(SashRenderer.java:142) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:665) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:757) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$0(PartRenderingEngine.java:728) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$2.run(PartRenderingEngine.java:722) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:706) + at org.eclipse.e4.ui.workbench.renderers.swt.SWTPartRenderer.processContents(SWTPartRenderer.java:70) + at org.eclipse.e4.ui.workbench.renderers.swt.PerspectiveRenderer.processContents(PerspectiveRenderer.java:49) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:665) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:757) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$0(PartRenderingEngine.java:728) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$2.run(PartRenderingEngine.java:722) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:706) + at org.eclipse.e4.ui.workbench.renderers.swt.PerspectiveStackRenderer.showTab(PerspectiveStackRenderer.java:82) + at org.eclipse.e4.ui.workbench.renderers.swt.LazyStackRenderer.postProcess(LazyStackRenderer.java:103) + at org.eclipse.e4.ui.workbench.renderers.swt.PerspectiveStackRenderer.postProcess(PerspectiveStackRenderer.java:63) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:669) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:757) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$0(PartRenderingEngine.java:728) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$2.run(PartRenderingEngine.java:722) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:706) + at org.eclipse.e4.ui.workbench.renderers.swt.SWTPartRenderer.processContents(SWTPartRenderer.java:70) + at org.eclipse.e4.ui.workbench.renderers.swt.SashRenderer.processContents(SashRenderer.java:142) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:665) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:757) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$0(PartRenderingEngine.java:728) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$2.run(PartRenderingEngine.java:722) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:706) + at org.eclipse.e4.ui.workbench.renderers.swt.SWTPartRenderer.processContents(SWTPartRenderer.java:70) + at org.eclipse.e4.ui.workbench.renderers.swt.WBWRenderer.processContents(WBWRenderer.java:725) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:665) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:757) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$0(PartRenderingEngine.java:728) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$2.run(PartRenderingEngine.java:722) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:706) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$4.run(PartRenderingEngine.java:1059) + at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:336) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.run(PartRenderingEngine.java:1022) + at org.eclipse.e4.ui.internal.workbench.E4Workbench.createAndRunUI(E4Workbench.java:150) + at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:693) + at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:336) + at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:610) + at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:148) + at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:138) + at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:388) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:243) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:497) + at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:673) + at org.eclipse.equinox.launcher.Main.basicRun(Main.java:610) + at org.eclipse.equinox.launcher.Main.run(Main.java:1519) + at com.arm.workbench.Hook.run(Hook.java:487) +Caused by: java.lang.RuntimeException: Could not load modules manager from C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a5x\ac6\example_build\.metadata\.plugins\org.python.pydev\v1_6mreyygygeqhdt73aqmeprc33\modulesKeys (version changed). + at org.python.pydev.editor.codecompletion.revisited.ModulesManager.loadFromFile(ModulesManager.java:301) + at org.python.pydev.editor.codecompletion.revisited.SystemModulesManager.load(SystemModulesManager.java:397) + at org.python.pydev.ui.interpreters.AbstractInterpreterManager.getInterpretersFromPersistedString(AbstractInterpreterManager.java:527) + ... 138 more + +!ENTRY org.python.pydev.shared_core 1 1 2020-07-24 13:46:57.027 +!MESSAGE Finished restoring information for: C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\lib\jython-2.7.0-standalone.jar at: C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a5x\ac6\example_build\.metadata\.plugins\org.python.pydev\v1_6mreyygygeqhdt73aqmeprc33 +!STACK 0 +java.lang.RuntimeException: Finished restoring information for: C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\lib\jython-2.7.0-standalone.jar at: C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a5x\ac6\example_build\.metadata\.plugins\org.python.pydev\v1_6mreyygygeqhdt73aqmeprc33 + at org.python.pydev.core.log.Log.logInfo(Log.java:66) + at org.python.pydev.ui.interpreters.AbstractInterpreterManager.getInterpretersFromPersistedString(AbstractInterpreterManager.java:574) + at org.python.pydev.ui.interpreters.AbstractInterpreterManager.internalRecreateCacheGetInterpreterInfos(AbstractInterpreterManager.java:345) + at org.python.pydev.ui.interpreters.AbstractInterpreterManager.getInterpreterInfos(AbstractInterpreterManager.java:332) + at org.python.pydev.ui.interpreters.AbstractInterpreterManager.(AbstractInterpreterManager.java:185) + at org.python.pydev.ui.interpreters.JythonInterpreterManager.(JythonInterpreterManager.java:31) + at org.python.pydev.plugin.PydevPlugin.start(PydevPlugin.java:246) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(Native Method) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:357) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.navigator.filters.CommonFilterDescriptor$1.run(CommonFilterDescriptor.java:139) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.navigator.filters.CommonFilterDescriptor.createFilter(CommonFilterDescriptor.java:119) + at org.eclipse.ui.internal.navigator.NavigatorFilterService.getViewerFilter(NavigatorFilterService.java:177) + at org.eclipse.ui.internal.navigator.NavigatorFilterService.getVisibleFilters(NavigatorFilterService.java:146) + at org.eclipse.ui.navigator.CommonNavigator.createPartControl(CommonNavigator.java:195) + at org.eclipse.ui.navigator.resources.ProjectExplorer.createPartControl(ProjectExplorer.java:88) + at org.eclipse.ui.internal.e4.compatibility.CompatibilityPart.createPartControl(CompatibilityPart.java:150) + at org.eclipse.ui.internal.e4.compatibility.CompatibilityView.createPartControl(CompatibilityView.java:143) + at org.eclipse.ui.internal.e4.compatibility.CompatibilityPart.create(CompatibilityPart.java:340) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:497) + at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:55) + at org.eclipse.e4.core.internal.di.InjectorImpl.processAnnotated(InjectorImpl.java:966) + at org.eclipse.e4.core.internal.di.InjectorImpl.processAnnotated(InjectorImpl.java:931) + at org.eclipse.e4.core.internal.di.InjectorImpl.inject(InjectorImpl.java:151) + at org.eclipse.e4.core.internal.di.InjectorImpl.internalMake(InjectorImpl.java:375) + at org.eclipse.e4.core.internal.di.InjectorImpl.make(InjectorImpl.java:294) + at org.eclipse.e4.core.contexts.ContextInjectionFactory.make(ContextInjectionFactory.java:162) + at org.eclipse.e4.ui.internal.workbench.ReflectionContributionFactory.createFromBundle(ReflectionContributionFactory.java:105) + at org.eclipse.e4.ui.internal.workbench.ReflectionContributionFactory.doCreate(ReflectionContributionFactory.java:74) + at org.eclipse.e4.ui.internal.workbench.ReflectionContributionFactory.create(ReflectionContributionFactory.java:56) + at org.eclipse.e4.ui.workbench.renderers.swt.ContributedPartRenderer.createWidget(ContributedPartRenderer.java:129) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createWidget(PartRenderingEngine.java:975) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:651) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$1.run(PartRenderingEngine.java:536) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:520) + at org.eclipse.e4.ui.workbench.renderers.swt.ElementReferenceRenderer.createWidget(ElementReferenceRenderer.java:70) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createWidget(PartRenderingEngine.java:975) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:651) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:757) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$0(PartRenderingEngine.java:728) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$2.run(PartRenderingEngine.java:722) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:706) + at org.eclipse.e4.ui.workbench.renderers.swt.StackRenderer.showTab(StackRenderer.java:1324) + at org.eclipse.e4.ui.workbench.renderers.swt.LazyStackRenderer.postProcess(LazyStackRenderer.java:103) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:669) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:757) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$0(PartRenderingEngine.java:728) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$2.run(PartRenderingEngine.java:722) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:706) + at org.eclipse.e4.ui.workbench.renderers.swt.SWTPartRenderer.processContents(SWTPartRenderer.java:70) + at org.eclipse.e4.ui.workbench.renderers.swt.SashRenderer.processContents(SashRenderer.java:142) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:665) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:757) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$0(PartRenderingEngine.java:728) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$2.run(PartRenderingEngine.java:722) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:706) + at org.eclipse.e4.ui.workbench.renderers.swt.SWTPartRenderer.processContents(SWTPartRenderer.java:70) + at org.eclipse.e4.ui.workbench.renderers.swt.PerspectiveRenderer.processContents(PerspectiveRenderer.java:49) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:665) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:757) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$0(PartRenderingEngine.java:728) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$2.run(PartRenderingEngine.java:722) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:706) + at org.eclipse.e4.ui.workbench.renderers.swt.PerspectiveStackRenderer.showTab(PerspectiveStackRenderer.java:82) + at org.eclipse.e4.ui.workbench.renderers.swt.LazyStackRenderer.postProcess(LazyStackRenderer.java:103) + at org.eclipse.e4.ui.workbench.renderers.swt.PerspectiveStackRenderer.postProcess(PerspectiveStackRenderer.java:63) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:669) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:757) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$0(PartRenderingEngine.java:728) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$2.run(PartRenderingEngine.java:722) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:706) + at org.eclipse.e4.ui.workbench.renderers.swt.SWTPartRenderer.processContents(SWTPartRenderer.java:70) + at org.eclipse.e4.ui.workbench.renderers.swt.SashRenderer.processContents(SashRenderer.java:142) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:665) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:757) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$0(PartRenderingEngine.java:728) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$2.run(PartRenderingEngine.java:722) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:706) + at org.eclipse.e4.ui.workbench.renderers.swt.SWTPartRenderer.processContents(SWTPartRenderer.java:70) + at org.eclipse.e4.ui.workbench.renderers.swt.WBWRenderer.processContents(WBWRenderer.java:725) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:665) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:757) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$0(PartRenderingEngine.java:728) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$2.run(PartRenderingEngine.java:722) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:706) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$4.run(PartRenderingEngine.java:1059) + at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:336) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.run(PartRenderingEngine.java:1022) + at org.eclipse.e4.ui.internal.workbench.E4Workbench.createAndRunUI(E4Workbench.java:150) + at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:693) + at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:336) + at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:610) + at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:148) + at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:138) + at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:388) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:243) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:497) + at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:673) + at org.eclipse.equinox.launcher.Main.basicRun(Main.java:610) + at org.eclipse.equinox.launcher.Main.run(Main.java:1519) + at com.arm.workbench.Hook.run(Hook.java:487) + +!ENTRY org.eclipse.egit.ui 2 0 2020-07-24 13:47:00.345 +!MESSAGE Warning: The environment variable HOME is not set. The following directory will be used to store the Git +user global configuration and to define the default location to store repositories: 'C:\Users\nisohack'. If this is +not correct please set the HOME environment variable and restart Eclipse. Otherwise Git for Windows and +EGit might behave differently since they see different configuration options. +This warning can be switched off on the Team > Git > Confirmations and Warnings preference page. + +!ENTRY org.eclipse.ui.ide 4 4 2020-07-24 13:50:25.662 +!MESSAGE Problems saving workspace + +!ENTRY org.eclipse.ui.ide 4 1 2020-07-24 13:50:25.662 +!MESSAGE Problems occurred while trying to save the state of the workbench. +!SUBENTRY 1 org.eclipse.core.resources 4 568 2020-07-24 13:50:25.662 +!MESSAGE Could not write metadata for '/RemoteSystemsTempFiles'. +!STACK 0 +java.io.FileNotFoundException: C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports\cortex_a5x\ac6\example_build\.metadata\.plugins\org.eclipse.core.resources\.projects\RemoteSystemsTempFiles\.markers (The system cannot find the path specified) + at java.io.FileOutputStream.open0(Native Method) + at java.io.FileOutputStream.open(FileOutputStream.java:270) + at java.io.FileOutputStream.(FileOutputStream.java:213) + at java.io.FileOutputStream.(FileOutputStream.java:162) + at org.eclipse.core.internal.localstore.SafeFileOutputStream.(SafeFileOutputStream.java:51) + at org.eclipse.core.internal.resources.SaveManager.visitAndSave(SaveManager.java:1657) + at org.eclipse.core.internal.resources.SaveManager.visitAndSave(SaveManager.java:1739) + at org.eclipse.core.internal.resources.SaveManager.save(SaveManager.java:1199) + at org.eclipse.core.internal.resources.Workspace.save(Workspace.java:2283) + at org.eclipse.ui.internal.ide.application.IDEWorkbenchAdvisor$4.run(IDEWorkbenchAdvisor.java:456) + at org.eclipse.jface.operation.ModalContext$ModalContextThread.run(ModalContext.java:119) diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/com.arm.ds/DTSL/ARM+FVP+%28Installed+with+DS-5%29+-+Cortex-A8/dtsl_config_script/DtslScript/default.dtslprops b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/com.arm.ds/DTSL/ARM+FVP+%28Installed+with+DS-5%29+-+Cortex-A8/dtsl_config_script/DtslScript/default.dtslprops new file mode 100644 index 00000000..b20b68ff --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/com.arm.ds/DTSL/ARM+FVP+%28Installed+with+DS-5%29+-+Cortex-A8/dtsl_config_script/DtslScript/default.dtslprops @@ -0,0 +1,6 @@ +#Fri Oct 16 15:52:42 PDT 2015 +options.traceBuffer.traceWrapMode=wrap +options.traceBuffer.clearTraceOnConnect=true +options.traceBuffer.bufferSize=Buffer16M +options.traceBuffer.traceCaptureDevice=None +options.traceBuffer.startTraceOnConnect=true diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/com.arm.ds/DTSL/ARM+FVP+%28Installed+with+DS-5%29+-+VE_AEMv8x1/dtsl_config_script/DtslScript/default.dtslprops b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/com.arm.ds/DTSL/ARM+FVP+%28Installed+with+DS-5%29+-+VE_AEMv8x1/dtsl_config_script/DtslScript/default.dtslprops new file mode 100644 index 00000000..382bea50 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/com.arm.ds/DTSL/ARM+FVP+%28Installed+with+DS-5%29+-+VE_AEMv8x1/dtsl_config_script/DtslScript/default.dtslprops @@ -0,0 +1,6 @@ +#Fri Oct 16 15:53:24 PDT 2015 +options.traceBuffer.traceWrapMode=wrap +options.traceBuffer.clearTraceOnConnect=true +options.traceBuffer.bufferSize=Buffer16M +options.traceBuffer.traceCaptureDevice=None +options.traceBuffer.startTraceOnConnect=true diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/com.arm.eclipse.licensemanager.ui/dialog_settings.xml b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/com.arm.eclipse.licensemanager.ui/dialog_settings.xml new file mode 100644 index 00000000..045bd42d --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/com.arm.eclipse.licensemanager.ui/dialog_settings.xml @@ -0,0 +1,10 @@ + +
+
+ + + + + +
+
diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/com.python.pydev.analysis/jython_v1_3o76x04a9rox164awcru9p1ls/jython.pydevsysteminfo b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/com.python.pydev.analysis/jython_v1_3o76x04a9rox164awcru9p1ls/jython.pydevsysteminfo new file mode 100644 index 00000000..9ef832c6 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/com.python.pydev.analysis/jython_v1_3o76x04a9rox164awcru9p1ls/jython.pydevsysteminfo @@ -0,0 +1,6737 @@ +-- VERSION_4 +-- START DISKCACHE_2 +C:\temp2149\.metadata\.plugins\com.python.pydev.analysis\jython_v1_3o76x04a9rox164awcru9p1ls\v2_indexcache +xml.dom.MessageSource|1493320058000000000|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\xml\dom\MessageSource.py +xml.etree.__init__|1493320058000000000|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\xml\etree\__init__.py +encodings.cp874|1493320056000000000|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\cp874.py +_pydevd_bundle.pydevd_cython_win32_34_32|1471547894000000000|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_cython_win32_34_32.pyd +encodings.cp875|1493320056000000000|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\cp875.py +unittest.signals|1493320058000000000|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\unittest\signals.py +arm_ds_launcher.targetcontrol|1494465759026747000|C:\Users\Bill\AppData\Roaming\ARM\DS-5_v5.27.0\workbench\configuration\org.eclipse.osgi\413\0\.cp\arm_ds_launcher\targetcontrol.py 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diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.cdt.ui/global-build.log b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.cdt.ui/global-build.log new file mode 100644 index 00000000..5d8249df --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.cdt.ui/global-build.log @@ -0,0 +1,7 @@ +13:49:41 **** Incremental Build of configuration Debug for project sample_threadx **** +make -j8 all +Building target: sample_threadx.axf +Invoking: ARM Linker 6 +armlink --entry=start64 --scatter="..\sample_threadx.txt" --map --verbose --info=sizes --info=totals --list="sample_threadx.map" -o "sample_threadx.axf" ./armv8_aarch64_SystemTimer.o ./el3_vectors.o ./gic400_gic.o ./hw_setup.o ./sample_threadx.o ./startup.o ../../tx/Debug/tx.a +Finished building target: sample_threadx.axf + diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.cdt.ui/sample_threadx.build.log b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.cdt.ui/sample_threadx.build.log new file mode 100644 index 00000000..bfb8c36f --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.cdt.ui/sample_threadx.build.log @@ -0,0 +1,10 @@ +13:49:41 **** Incremental Build of configuration Debug for project sample_threadx **** +make -j8 all +Building target: sample_threadx.axf +Invoking: ARM Linker 6 +armlink --entry=start64 --scatter="..\sample_threadx.txt" --map --verbose --info=sizes --info=totals --list="sample_threadx.map" -o "sample_threadx.axf" ./armv8_aarch64_SystemTimer.o ./el3_vectors.o ./gic400_gic.o ./hw_setup.o ./sample_threadx.o ./startup.o ../../tx/Debug/tx.a +Finished building target: sample_threadx.axf + + +13:49:42 Build Finished (took 847ms) + diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.cdt.ui/tx.build.log b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.cdt.ui/tx.build.log new file mode 100644 index 00000000..f4393a51 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.cdt.ui/tx.build.log @@ -0,0 +1,15 @@ +11:03:25 **** Incremental Build of configuration Debug for project tx **** +make all +Building file: ../tx_initialize_low_level.s +Invoking: ARM Assembler 6 +armclang -target aarch64-arm-none-eabi -mcpu=cortex-a53+fp -g -c -o "tx_initialize_low_level.o" "../tx_initialize_low_level.s" +Finished building: ../tx_initialize_low_level.s + +Building target: tx.a +Invoking: ARM Librarian 6 +armar --create "tx.a" ./tx_block_allocate.o ./tx_block_pool_cleanup.o ./tx_block_pool_create.o ./tx_block_pool_delete.o ./tx_block_pool_info_get.o ./tx_block_pool_initialize.o ./tx_block_pool_performance_info_get.o ./tx_block_pool_performance_system_info_get.o ./tx_block_pool_prioritize.o ./tx_block_release.o ./tx_byte_allocate.o ./tx_byte_pool_cleanup.o ./tx_byte_pool_create.o ./tx_byte_pool_delete.o ./tx_byte_pool_info_get.o ./tx_byte_pool_initialize.o ./tx_byte_pool_performance_info_get.o ./tx_byte_pool_performance_system_info_get.o ./tx_byte_pool_prioritize.o ./tx_byte_pool_search.o ./tx_byte_release.o ./tx_event_flags_cleanup.o ./tx_event_flags_create.o ./tx_event_flags_delete.o ./tx_event_flags_get.o ./tx_event_flags_info_get.o ./tx_event_flags_initialize.o ./tx_event_flags_performance_info_get.o ./tx_event_flags_performance_system_info_get.o ./tx_event_flags_set.o ./tx_event_flags_set_notify.o ./tx_initialize_high_level.o ./tx_initialize_kernel_enter.o ./tx_initialize_kernel_setup.o ./tx_initialize_low_level.o ./tx_mutex_cleanup.o ./tx_mutex_create.o ./tx_mutex_delete.o ./tx_mutex_get.o ./tx_mutex_info_get.o ./tx_mutex_initialize.o ./tx_mutex_performance_info_get.o ./tx_mutex_performance_system_info_get.o ./tx_mutex_prioritize.o ./tx_mutex_priority_change.o ./tx_mutex_put.o ./tx_queue_cleanup.o ./tx_queue_create.o ./tx_queue_delete.o ./tx_queue_flush.o ./tx_queue_front_send.o ./tx_queue_info_get.o ./tx_queue_initialize.o ./tx_queue_performance_info_get.o ./tx_queue_performance_system_info_get.o ./tx_queue_prioritize.o ./tx_queue_receive.o ./tx_queue_send.o ./tx_queue_send_notify.o ./tx_semaphore_ceiling_put.o ./tx_semaphore_cleanup.o ./tx_semaphore_create.o ./tx_semaphore_delete.o ./tx_semaphore_get.o ./tx_semaphore_info_get.o ./tx_semaphore_initialize.o ./tx_semaphore_performance_info_get.o ./tx_semaphore_performance_system_info_get.o ./tx_semaphore_prioritize.o ./tx_semaphore_put.o ./tx_semaphore_put_notify.o ./tx_thread_context_restore.o ./tx_thread_context_save.o ./tx_thread_create.o ./tx_thread_delete.o ./tx_thread_entry_exit_notify.o ./tx_thread_fp_disable.o ./tx_thread_fp_enable.o ./tx_thread_identify.o ./tx_thread_info_get.o ./tx_thread_initialize.o ./tx_thread_interrupt_control.o ./tx_thread_interrupt_disable.o ./tx_thread_interrupt_restore.o ./tx_thread_performance_info_get.o ./tx_thread_performance_system_info_get.o ./tx_thread_preemption_change.o ./tx_thread_priority_change.o ./tx_thread_relinquish.o ./tx_thread_reset.o ./tx_thread_resume.o ./tx_thread_schedule.o ./tx_thread_shell_entry.o ./tx_thread_sleep.o ./tx_thread_stack_analyze.o ./tx_thread_stack_build.o ./tx_thread_stack_error_handler.o ./tx_thread_stack_error_notify.o ./tx_thread_suspend.o ./tx_thread_system_preempt_check.o ./tx_thread_system_resume.o ./tx_thread_system_return.o ./tx_thread_system_suspend.o ./tx_thread_terminate.o ./tx_thread_time_slice.o ./tx_thread_time_slice_change.o ./tx_thread_timeout.o ./tx_thread_wait_abort.o ./tx_time_get.o ./tx_time_set.o ./tx_timer_activate.o ./tx_timer_change.o ./tx_timer_create.o ./tx_timer_deactivate.o ./tx_timer_delete.o ./tx_timer_expiration_process.o ./tx_timer_info_get.o ./tx_timer_initialize.o ./tx_timer_interrupt.o ./tx_timer_performance_info_get.o ./tx_timer_performance_system_info_get.o ./tx_timer_system_activate.o ./tx_timer_system_deactivate.o ./tx_timer_thread_entry.o ./tx_trace_buffer_full_notify.o ./tx_trace_disable.o ./tx_trace_enable.o ./tx_trace_event_filter.o ./tx_trace_event_unfilter.o ./tx_trace_initialize.o ./tx_trace_interrupt_control.o ./tx_trace_isr_enter_insert.o ./tx_trace_isr_exit_insert.o ./tx_trace_object_register.o ./tx_trace_object_unregister.o ./tx_trace_user_event_insert.o ./txe_block_allocate.o ./txe_block_pool_create.o ./txe_block_pool_delete.o ./txe_block_pool_info_get.o ./txe_block_pool_prioritize.o ./txe_block_release.o ./txe_byte_allocate.o ./txe_byte_pool_create.o ./txe_byte_pool_delete.o ./txe_byte_pool_info_get.o ./txe_byte_pool_prioritize.o ./txe_byte_release.o ./txe_event_flags_create.o ./txe_event_flags_delete.o ./txe_event_flags_get.o ./txe_event_flags_info_get.o ./txe_event_flags_set.o ./txe_event_flags_set_notify.o ./txe_mutex_create.o ./txe_mutex_delete.o ./txe_mutex_get.o ./txe_mutex_info_get.o ./txe_mutex_prioritize.o ./txe_mutex_put.o ./txe_queue_create.o ./txe_queue_delete.o ./txe_queue_flush.o ./txe_queue_front_send.o ./txe_queue_info_get.o ./txe_queue_prioritize.o ./txe_queue_receive.o ./txe_queue_send.o ./txe_queue_send_notify.o ./txe_semaphore_ceiling_put.o ./txe_semaphore_create.o ./txe_semaphore_delete.o ./txe_semaphore_get.o ./txe_semaphore_info_get.o ./txe_semaphore_prioritize.o ./txe_semaphore_put.o ./txe_semaphore_put_notify.o ./txe_thread_create.o ./txe_thread_delete.o ./txe_thread_entry_exit_notify.o ./txe_thread_info_get.o ./txe_thread_preemption_change.o ./txe_thread_priority_change.o ./txe_thread_relinquish.o ./txe_thread_reset.o ./txe_thread_resume.o ./txe_thread_suspend.o ./txe_thread_terminate.o ./txe_thread_time_slice_change.o ./txe_thread_wait_abort.o ./txe_timer_activate.o ./txe_timer_change.o ./txe_timer_create.o ./txe_timer_deactivate.o ./txe_timer_delete.o ./txe_timer_info_get.o +Finished building target: tx.a + + +11:03:27 Build Finished (took 2s.680ms) + diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.resources/.projects/sample_threadx/.indexes/properties.index b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.resources/.projects/sample_threadx/.indexes/properties.index new file mode 100644 index 00000000..030da0ba Binary files /dev/null and b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.resources/.projects/sample_threadx/.indexes/properties.index differ diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.resources/.projects/sample_threadx/org.eclipse.egit.core/GitProjectData.properties b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.resources/.projects/sample_threadx/org.eclipse.egit.core/GitProjectData.properties new file mode 100644 index 00000000..9ff39455 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.resources/.projects/sample_threadx/org.eclipse.egit.core/GitProjectData.properties @@ -0,0 +1,3 @@ +#GitProjectData +#Wed Jun 17 11:00:38 PDT 2020 +.gitdir=../../../../../.git diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.resources/.projects/tx/.indexes/42/properties.index b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.resources/.projects/tx/.indexes/42/properties.index new file mode 100644 index 00000000..f5cc7f58 Binary files /dev/null and b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.resources/.projects/tx/.indexes/42/properties.index differ diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.resources/.projects/tx/.indexes/properties.index b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.resources/.projects/tx/.indexes/properties.index new file mode 100644 index 00000000..81906748 Binary files /dev/null and b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.resources/.projects/tx/.indexes/properties.index differ diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/history.version b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/history.version new file mode 100644 index 00000000..25cb955b --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/history.version @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.index b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.index new file mode 100644 index 00000000..f1a07973 Binary files /dev/null and b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.index differ diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.version b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.version new file mode 100644 index 00000000..6b2aaa76 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.version @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.resources/.root/11.tree b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.resources/.root/11.tree new file mode 100644 index 00000000..318ec68a Binary files /dev/null and b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.resources/.root/11.tree differ diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.resources/.safetable/org.eclipse.core.resources b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.resources/.safetable/org.eclipse.core.resources new file mode 100644 index 00000000..7c3b44d4 Binary files /dev/null and b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.resources/.safetable/org.eclipse.core.resources differ diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.arm.debugger.launcher2.prefs b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.arm.debugger.launcher2.prefs new file mode 100644 index 00000000..5ca15012 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.arm.debugger.launcher2.prefs @@ -0,0 +1,5 @@ +config_db_path=C%3A\\Program Files\\DS-5 v5.29.3\\sw\\debugger\\configdb; +config_db_path0_defaultid=com.arm.ds\:0 +config_db_path0_enabled=true +eclipse.preferences.version=1 +enabled_config_db_path=C%3A\\Program Files\\DS-5 v5.29.3\\sw\\debugger\\configdb; diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.arm.debugger.ux.prefs b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.arm.debugger.ux.prefs new file mode 100644 index 00000000..f14fdd58 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.arm.debugger.ux.prefs @@ -0,0 +1,6 @@ +ConnectionManager.savedConnections=\n\n\tVE_AEMv8x1_Simulation\n\n +PreferredTargetHasBeenSet=true +UXContextManager.savedContexts=\n\n\tConnection|95hbfse4c\:gvv8gv0vpkmw|1445364262162|workspace\:\:VE_AEMv8x1_Simulation|VE_AEMv8x1_Simulation\n\n +debugger.perspective.switch.preference.break=never +debugger.perspective.switch.preference.launch=never +eclipse.preferences.version=1 diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.arm.eclipse.licensemanager.prefs b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.arm.eclipse.licensemanager.prefs new file mode 100644 index 00000000..6cf4fe3e --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.arm.eclipse.licensemanager.prefs @@ -0,0 +1,3 @@ +eclipse.preferences.version=1 +userEmail= +userPassword= diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.arm.eclipse.toolkit.prefs b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.arm.eclipse.toolkit.prefs new file mode 100644 index 00000000..b9162fb8 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.arm.eclipse.toolkit.prefs @@ -0,0 +1,3 @@ +analytics=[{"debugger_n_debug_capture_fvp"\:2,"debugger_s_host_os"\:"Windows 7","debugger_n_create_view_commands"\:5,"debugger_s_host_os_version"\:"6.1","debugger_n_create_view_registers"\:2,"debugger_s_java_version"\:"1.7.0_60","product"\:"debugger","debugger_n_create_view_app_console"\:5,"debugger_n_create_view_expressions"\:2,"debugger_n_create_view_disassembly"\:2,"debugger_s_eclipse_version"\:"3.106.0.v20140812-1751","debugger_s_toolkit"\:"ult","debugger_s_host_locale"\:"en_US","debugger_s_distribution"\:"ARM Development Studio 5","debugger_n_create_view_debug_control"\:1,"debugger_s_host_architecture"\:"amd64","debugger_n_create_view_variables"\:1}] +analytics_transmitted=1445363767810 +eclipse.preferences.version=1 diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.arm.ui.intro.prefs b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.arm.ui.intro.prefs new file mode 100644 index 00000000..697343e3 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.arm.ui.intro.prefs @@ -0,0 +1,2 @@ +WELCOME_PAGE_SHOWN_VERSIONS=5.24.0,5.25.0,5.27.0,5.29.3 +eclipse.preferences.version=1 diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prefs b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prefs new file mode 100644 index 00000000..77ca49ab --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +macros/workspace=\r\n\r\n diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-sample_threadx.prefs b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-sample_threadx.prefs new file mode 100644 index 00000000..9c00dc4e --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-sample_threadx.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +indexer/preferenceScope=0 diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-tx.prefs b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-tx.prefs new file mode 100644 index 00000000..9c00dc4e --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-tx.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +indexer/preferenceScope=0 diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.core.prefs b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.core.prefs new file mode 100644 index 00000000..aa2411de --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.core.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.debug.core.cDebug.default_source_containers=\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs new file mode 100644 index 00000000..bcc58be0 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs @@ -0,0 +1,5 @@ +eclipse.preferences.version=1 +properties/sample_threadx.com.arm.eclipse.build.project.v6.exe.1027551600/com.arm.eclipse.build.config.v6.exe.debug.1756493040=com.arm.tool.librarian.v6.1090597542\=rebuildState\\\=false\\r\\n\r\ncom.arm.tool.c.linker.v6.996475472\=rebuildState\\\=false\\r\\n\r\ncom.arm.tool.assembler.v6.1147311776\=rebuildState\\\=false\\r\\n\r\ncom.arm.eclipse.build.config.v6.exe.debug.1756493040\=rcState\\\=0\\r\\nrebuildState\\\=false\\r\\n\r\ncom.arm.tool.c.compiler.v6.1180490247\=rebuildState\\\=false\\r\\n\r\ncom.arm.tool.cpp.compiler.v6.757724458\=rebuildState\\\=false\\r\\n\r\ncom.arm.toolchain.v6.exe.debug.299888552\=rebuildState\\\=false\\r\\n\r\n +properties/sample_threadx.com.arm.eclipse.build.project.v6.exe.1027551600/com.arm.eclipse.build.config.v6.exe.release.1970372372=com.arm.tool.librarian.v6.1878811431\=rebuildState\\\=true\\r\\n\r\ncom.arm.tool.cpp.compiler.v6.1755515797\=rebuildState\\\=true\\r\\n\r\ncom.arm.toolchain.v6.exe.release.1208724479\=rebuildState\\\=true\\r\\n\r\ncom.arm.tool.c.linker.v6.1686707697\=rebuildState\\\=true\\r\\n\r\ncom.arm.tool.assembler.v6.759015076\=rebuildState\\\=true\\r\\n\r\ncom.arm.tool.c.compiler.v6.117703562\=rebuildState\\\=true\\r\\n\r\n +properties/tx.com.arm.eclipse.build.project.v6.lib.1209080418/com.arm.eclipse.build.config.v6.lib.debug.1636501669=com.arm.eclipse.build.config.v6.lib.debug.1636501669\=rcState\\\=0\\r\\nrebuildState\\\=false\\r\\n\r\ncom.arm.tool.c.compiler.v6.424515954\=rebuildState\\\=false\\r\\n\r\ncom.arm.tool.librarian.v6.1167637188\=rebuildState\\\=false\\r\\n\r\ncom.arm.toolchain.v6.lib.debug.372997136\=rebuildState\\\=false\\r\\n\r\ncom.arm.tool.cpp.compiler.v6.1361684972\=rebuildState\\\=false\\r\\n\r\ncom.arm.tool.assembler.v6.1230485781\=rebuildState\\\=false\\r\\n\r\ncom.arm.tool.c.linker.v6.1251436674\=rebuildState\\\=false\\r\\n\r\n +properties/tx.com.arm.eclipse.build.project.v6.lib.1209080418/com.arm.eclipse.build.config.v6.lib.release.1521587399=com.arm.tool.cpp.compiler.v6.2136467342\=rebuildState\\\=true\\r\\n\r\ncom.arm.toolchain.v6.lib.release.2074068559\=rebuildState\\\=true\\r\\n\r\ncom.arm.tool.librarian.v6.801428272\=rebuildState\\\=true\\r\\n\r\ncom.arm.tool.assembler.v6.1185271435\=rebuildState\\\=true\\r\\n\r\ncom.arm.tool.c.compiler.v6.910156028\=rebuildState\\\=true\\r\\n\r\ncom.arm.tool.c.linker.v6.1769504167\=rebuildState\\\=true\\r\\n\r\n diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs new file mode 100644 index 00000000..5e2da66d --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs @@ -0,0 +1,4 @@ +eclipse.preferences.version=1 +spelling_locale_initialized=true +useAnnotationsPrefPage=true +useQuickDiffPrefPage=true diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prj-tx.prefs b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prj-tx.prefs new file mode 100644 index 00000000..c4f76d0e --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prj-tx.prefs @@ -0,0 +1,3 @@ +buildConsole/keepLog=true +buildConsole/logLocation=C\:\\temp1702\\.metadata\\.plugins\\org.eclipse.cdt.ui\\tx.build.log +eclipse.preferences.version=1 diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 00000000..dffc6b51 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +version=1 diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.variables.prefs b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.variables.prefs new file mode 100644 index 00000000..b2acd9ca --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.variables.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.core.variables.valueVariables=\r\n\r\n diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs new file mode 100644 index 00000000..03da32b3 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs @@ -0,0 +1,4 @@ +//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.applicationLaunchType=org.eclipse.cdt.dsf.gdb.launch.localCLaunch,debug,;org.eclipse.cdt.cdi.launch.localCLaunch,run,; +//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.attachLaunchType=org.eclipse.cdt.dsf.gdb.launch.attachCLaunch,debug,; +//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.postmortemLaunchType=org.eclipse.cdt.dsf.gdb.launch.coreCLaunch,debug,; +eclipse.preferences.version=1 diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs new file mode 100644 index 00000000..87e219ab --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs @@ -0,0 +1,4 @@ +eclipse.preferences.version=1 +org.eclipse.debug.ui.PREF_LAUNCH_PERSPECTIVES=\r\n\r\n +org.eclipse.debug.ui.switch_to_perspective=prompt +preferredTargets=com.arm.debugger.ux.toggleARMBreakpointTarget\:com.arm.debugger.ux.toggleARMBreakpointTarget|com.arm.debugger.ux.toggleARMBreakpointTarget,org.eclipse.cdt.debug.ui.toggleCBreakpointTarget,org.eclipse.cdt.debug.ui.toggleCDynamicPrintfTarget\:com.arm.debugger.ux.toggleARMBreakpointTarget|com.arm.debugger.ux.toggleARMBreakpointTarget,default\:com.arm.debugger.ux.toggleARMBreakpointTarget| diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.egit.core.prefs b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.egit.core.prefs new file mode 100644 index 00000000..1be51a06 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.egit.core.prefs @@ -0,0 +1,3 @@ +GitRepositoriesView.GitDirectories=C\:\\Users\\nisohack\\Documents\\work\\x-ware_libs\\threadx_github\\.git; +GitRepositoriesView.GitDirectories.relative=C\:\\Users\\nisohack\\Documents\\work\\x-ware_libs\\threadx_github\\.git; +eclipse.preferences.version=1 diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.jdt.core.prefs b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.jdt.core.prefs new file mode 100644 index 00000000..f42de363 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.jdt.core.prefs @@ -0,0 +1,7 @@ +eclipse.preferences.version=1 +org.eclipse.jdt.core.compiler.codegen.inlineJsrBytecode=enabled +org.eclipse.jdt.core.compiler.codegen.targetPlatform=1.7 +org.eclipse.jdt.core.compiler.compliance=1.7 +org.eclipse.jdt.core.compiler.problem.assertIdentifier=error +org.eclipse.jdt.core.compiler.problem.enumIdentifier=error +org.eclipse.jdt.core.compiler.source=1.7 diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.jdt.launching.prefs b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.jdt.launching.prefs new file mode 100644 index 00000000..53088dcf --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.jdt.launching.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.jdt.launching.PREF_VM_XML=\r\n\r\n\r\n\r\n\r\n\r\n diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.jdt.ui.prefs b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.jdt.ui.prefs new file mode 100644 index 00000000..a0fcc985 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.jdt.ui.prefs @@ -0,0 +1,15 @@ +content_assist_proposals_background=255,255,255 +content_assist_proposals_foreground=0,0,0 +eclipse.preferences.version=1 +fontPropagated=true +org.eclipse.jdt.internal.ui.navigator.layout=2 +org.eclipse.jdt.internal.ui.navigator.librariesnode=true +org.eclipse.jdt.ui.editor.tab.width= +org.eclipse.jdt.ui.formatterprofiles.version=12 +org.eclipse.jdt.ui.javadoclocations.migrated=true +org.eclipse.jface.textfont=1|Consolas|10.0|0|WINDOWS|1|0|0|0|0|0|0|0|0|1|0|0|0|0|Consolas; +proposalOrderMigrated=true +spelling_locale_initialized=true +tabWidthPropagated=true +useAnnotationsPrefPage=true +useQuickDiffPrefPage=true diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.rse.core.prefs b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.rse.core.prefs new file mode 100644 index 00000000..26c1f191 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.rse.core.prefs @@ -0,0 +1,4 @@ +activeuserprofiles=Bill-PC;Team +eclipse.preferences.version=1 +org.eclipse.rse.systemtype.local.systemType.defaultUserId=Bill +useridperkey=Bill-PC.Local\=Bill; diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.rse.ui.prefs b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.rse.ui.prefs new file mode 100644 index 00000000..76e54f9e --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.rse.ui.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.rse.preferences.order.connections=Bill-PC.Local diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.search.prefs b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.search.prefs new file mode 100644 index 00000000..cec65c49 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.search.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.search.defaultPerspective=org.eclipse.search.defaultPerspective.none diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.team.ui.prefs b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.team.ui.prefs new file mode 100644 index 00000000..56cd496f --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.team.ui.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.team.ui.first_time=false diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.editors.prefs b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.editors.prefs new file mode 100644 index 00000000..61f3bb8b --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.editors.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +overviewRuler_migration=migrated_3.1 diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs new file mode 100644 index 00000000..57ce294d --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs @@ -0,0 +1,5 @@ +PROBLEMS_FILTERS_MIGRATE=true +eclipse.preferences.version=1 +platformState=1585091318863 +quickStart=false +tipsAndTricks=true diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs new file mode 100644 index 00000000..08076f23 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +showIntro=false diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs new file mode 100644 index 00000000..699e6a22 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs @@ -0,0 +1,2 @@ +//org.eclipse.ui.commands/state/org.eclipse.ui.navigator.resources.nested.changeProjectPresentation/org.eclipse.ui.commands.radioState=false +eclipse.preferences.version=1 diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.python.pydev.prefs b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.python.pydev.prefs new file mode 100644 index 00000000..c79862da --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.python.pydev.prefs @@ -0,0 +1,3 @@ +INTERPRETERS_CHECKED_ONCE=true +JYTHON_INTERPRETER_PATH=\nDS-5 Jython\n2.5\nC\:\\Program Files\\DS-5 v5.29.3\\sw\\eclipse\\dropins\\plugins\\com.arm.tpip.jython_2.7.0.20191002_110027\\lib\\jython-2.7.0-standalone.jar\nC\:\\Program Files\\DS-5 v5.29.3\\sw\\eclipse\\dropins\\plugins\\com.arm.debug.interpreter.jython.api_5.29.3.20191002_110027\nC\:\\Program Files\\DS-5 v5.29.3\\sw\\eclipse\\dropins\\plugins\\com.arm.tpip.jython_2.7.0.20191002_110027\\Jython\\Lib\nC\:\\Program Files\\DS-5 v5.29.3\\sw\\eclipse\\plugins\\org.python.pydev_5.7.0.201704111357\\pysrc\nC\:\\Program Files\\DS-5 v5.29.3\\sw\\java\\lib\\charsets.jar\nC\:\\Program Files\\DS-5 v5.29.3\\sw\\java\\lib\\ext\\access-bridge-64.jar\nC\:\\Program Files\\DS-5 v5.29.3\\sw\\java\\lib\\ext\\cldrdata.jar\nC\:\\Program Files\\DS-5 v5.29.3\\sw\\java\\lib\\ext\\dnsns.jar\nC\:\\Program Files\\DS-5 v5.29.3\\sw\\java\\lib\\ext\\jaccess.jar\nC\:\\Program Files\\DS-5 v5.29.3\\sw\\java\\lib\\ext\\jfxrt.jar\nC\:\\Program Files\\DS-5 v5.29.3\\sw\\java\\lib\\ext\\localedata.jar\nC\:\\Program Files\\DS-5 v5.29.3\\sw\\java\\lib\\ext\\nashorn.jar\nC\:\\Program Files\\DS-5 v5.29.3\\sw\\java\\lib\\ext\\sunec.jar\nC\:\\Program Files\\DS-5 v5.29.3\\sw\\java\\lib\\ext\\sunjce_provider.jar\nC\:\\Program Files\\DS-5 v5.29.3\\sw\\java\\lib\\ext\\sunmscapi.jar\nC\:\\Program Files\\DS-5 v5.29.3\\sw\\java\\lib\\ext\\sunpkcs11.jar\nC\:\\Program Files\\DS-5 v5.29.3\\sw\\java\\lib\\ext\\zipfs.jar\nC\:\\Program Files\\DS-5 v5.29.3\\sw\\java\\lib\\jce.jar\nC\:\\Program Files\\DS-5 v5.29.3\\sw\\java\\lib\\jfr.jar\nC\:\\Program Files\\DS-5 v5.29.3\\sw\\java\\lib\\jsse.jar\nC\:\\Program Files\\DS-5 v5.29.3\\sw\\java\\lib\\resources.jar\nC\:\\Program Files\\DS-5 v5.29.3\\sw\\java\\lib\\rt.jar\nC\:\\Users\\nisohack\\AppData\\Roaming\\ARM\\DS-5_v5.29.3\\workbench\\configuration\\org.eclipse.osgi\\420\\0\\.cp\nStringIO\n__builtin__\n_ast\n_codecs\n_collections\n_csv\n_functools\n_hashlib\n_marshal\n_py_compile\n_random\n_sre\n_systemrestart\n_threading\n_weakref\narray\nbinascii\ncPickle\ncStringIO\ncmath\ncom.ziclix.python.sql\nemail\nerrno\nexceptions\ngc\nhashlib\nimp\nitertools\njarray\njffi\nmath\nnt\noperator\nos\nos.path\npytest\nre\nstruct\nsynchronize\nsys\nthread\ntime\nucnhash\nzipimport\nDS5_HOMEC\:\\Program Files\\DS-5 v5.29.3\\sw\\..\nWORKSPACEC\:\\Users\\nisohack\\Documents\\work\\x-ware_libs\\threadx_github\\ports\\cortex_a5x\\ac6\\example_build\n&&&&& +eclipse.preferences.version=1 diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.debug.core/.launches/VE_AEMv8x1_Simulation.launch b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.debug.core/.launches/VE_AEMv8x1_Simulation.launch new file mode 100644 index 00000000..5075556d --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.debug.core/.launches/VE_AEMv8x1_Simulation.launch @@ -0,0 +1,246 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.debug.ui/dialog_settings.xml b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.debug.ui/dialog_settings.xml new file mode 100644 index 00000000..fc2330e5 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.debug.ui/dialog_settings.xml @@ -0,0 +1,11 @@ + +
+
+ + + + + + +
+
diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml new file mode 100644 index 00000000..eb303290 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml @@ -0,0 +1,21 @@ + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.e4.ui.workbench.swt/dialog_settings.xml b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.e4.ui.workbench.swt/dialog_settings.xml new file mode 100644 index 00000000..394f38b2 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.e4.ui.workbench.swt/dialog_settings.xml @@ -0,0 +1,15 @@ + +
+
+ + + + + + + + + + +
+
diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.e4.workbench/workbench.xmi b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.e4.workbench/workbench.xmi new file mode 100644 index 00000000..3703a41a --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.e4.workbench/workbench.xmi @@ -0,0 +1,3305 @@ + + + + activeSchemeId:org.eclipse.ui.defaultAcceleratorConfiguration + ModelMigrationProcessor.001 + com.arm.debugger.ux.debugPerspectivemodel_created + + + + + + + + topLevel + shellMaximized + + + + + persp.actionSet:org.eclipse.ui.actionSet.keyBindings + persp.actionSet:org.eclipse.ui.actionSet.openFiles + persp.actionSet:org.eclipse.ui.edit.text.actionSet.annotationNavigation + persp.actionSet:org.eclipse.ui.edit.text.actionSet.navigation + persp.actionSet:org.eclipse.ui.edit.text.actionSet.convertLineDelimitersTo + persp.actionSet:org.eclipse.ui.externaltools.ExternalToolsSet + persp.actionSet:org.eclipse.ui.cheatsheets.actionSet + persp.actionSet:org.eclipse.search.searchActionSet + persp.actionSet:org.eclipse.rse.core.search.searchActionSet + persp.actionSet:org.eclipse.cdt.ui.SearchActionSet + persp.actionSet:org.eclipse.cdt.ui.CElementCreationActionSet + persp.actionSet:org.eclipse.ui.NavigateActionSet + persp.viewSC:org.eclipse.ui.console.ConsoleView + persp.viewSC:org.eclipse.search.ui.views.SearchView + persp.viewSC:org.eclipse.ui.views.ContentOutline + persp.viewSC:org.eclipse.ui.views.ProblemView + persp.viewSC:org.eclipse.cdt.ui.CView + persp.viewSC:org.eclipse.ui.views.ResourceNavigator + persp.viewSC:org.eclipse.ui.views.PropertySheet + persp.viewSC:org.eclipse.ui.views.TaskList + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewCWizard1 + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewCWizard2 + persp.newWizSC:org.eclipse.cdt.ui.wizards.ConvertToMakeWizard + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewMakeFromExisting + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewSourceFolderCreationWizard + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewFolderCreationWizard + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewSourceFileCreationWizard + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewHeaderFileCreationWizard + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewFileCreationWizard + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewClassCreationWizard + persp.perspSC:com.arm.debugger.ux.debugPerspective + persp.viewSC:streamline.view.LauncherView + persp.showIn:org.eclipse.cdt.codan.internal.ui.views.ProblemDetails + persp.viewSC:org.eclipse.cdt.codan.internal.ui.views.ProblemDetails + persp.actionSet:org.eclipse.debug.ui.breakpointActionSet + persp.viewSC:org.eclipse.cdt.make.ui.views.MakeView + persp.actionSet:org.eclipse.cdt.make.ui.makeTargetActionSet + persp.perspSC:org.eclipse.debug.ui.DebugPerspective + persp.perspSC:org.eclipse.team.ui.TeamSynchronizingPerspective + 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b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.jdt.core/variablesAndContainers.dat differ diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.jdt.launching/.install.xml b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.jdt.launching/.install.xml new file mode 100644 index 00000000..298c1751 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.jdt.launching/.install.xml @@ -0,0 +1,6 @@ + + + + + + diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.jdt.launching/libraryInfos.xml b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.jdt.launching/libraryInfos.xml new file mode 100644 index 00000000..9c610d67 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.jdt.launching/libraryInfos.xml @@ -0,0 +1,60 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.jdt.ui/OpenTypeHistory.xml b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.jdt.ui/OpenTypeHistory.xml new file mode 100644 index 00000000..a4ee3cbc --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.jdt.ui/OpenTypeHistory.xml @@ -0,0 +1,2 @@ + + diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.jdt.ui/QualifiedTypeNameHistory.xml b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.jdt.ui/QualifiedTypeNameHistory.xml new file mode 100644 index 00000000..9e390f50 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.jdt.ui/QualifiedTypeNameHistory.xml @@ -0,0 +1,2 @@ + + diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.linuxtools.cdt.libhover/C/glibc_library.libhover b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.linuxtools.cdt.libhover/C/glibc_library.libhover new file mode 100644 index 00000000..c7dd0734 Binary files /dev/null and b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.linuxtools.cdt.libhover/C/glibc_library.libhover differ diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2020/6/25/refactorings.history b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2020/6/25/refactorings.history new file mode 100644 index 00000000..677c4743 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2020/6/25/refactorings.history @@ -0,0 +1,4 @@ + + + + \ No newline at end of file diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2020/6/25/refactorings.index b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2020/6/25/refactorings.index new file mode 100644 index 00000000..d46ae897 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2020/6/25/refactorings.index @@ -0,0 +1 @@ +1592416820529 Delete resource 'sample_threadx' diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/sample_threadx/2020/6/25/refactorings.history b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/sample_threadx/2020/6/25/refactorings.history new file mode 100644 index 00000000..4e4eecaf --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/sample_threadx/2020/6/25/refactorings.history @@ -0,0 +1,3 @@ + + + \ No newline at end of file diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/sample_threadx/2020/6/25/refactorings.index b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/sample_threadx/2020/6/25/refactorings.index new file mode 100644 index 00000000..77556716 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/sample_threadx/2020/6/25/refactorings.index @@ -0,0 +1,3 @@ +1592426832027 Rename resource 'startup.s' +1592426835970 Rename resource 'el3_vectors.s' +1592426839107 Rename resource 'armv8_aarch64_SystemTimer.s' diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.ltk.ui.refactoring/dialog_settings.xml b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.ltk.ui.refactoring/dialog_settings.xml new file mode 100644 index 00000000..aa267842 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.ltk.ui.refactoring/dialog_settings.xml @@ -0,0 +1,7 @@ + +
+
+ + +
+
diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.rse.core/.log b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.rse.core/.log new file mode 100644 index 00000000..e69de29b diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.rse.core/initializerMarks/org.eclipse.rse.internal.core.RSELocalConnectionInitializer.mark b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.rse.core/initializerMarks/org.eclipse.rse.internal.core.RSELocalConnectionInitializer.mark new file mode 100644 index 00000000..e69de29b diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.rse.core/profiles/PRF.bill-pc_67/FP.local.files_0/node.properties b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.rse.core/profiles/PRF.bill-pc_67/FP.local.files_0/node.properties new file mode 100644 index 00000000..505e5249 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.rse.core/profiles/PRF.bill-pc_67/FP.local.files_0/node.properties @@ -0,0 +1,57 @@ +# RSE DOM Node +00-name=Bill-PC\:local.files +01-type=FilterPool +03-attr.default=true +03-attr.deletable=true +03-attr.id=local.files +03-attr.nonRenamable=false +03-attr.owningParentName=null +03-attr.release=200 +03-attr.singleFilterStringOnly=false +03-attr.singleFilterStringOnlyESet=false +03-attr.stringsCaseSensitive=true +03-attr.supportsDuplicateFilterStrings=false +03-attr.supportsNestedFilters=true +03-attr.type=default +06-child.00000.00-name=My Home +06-child.00000.01-type=Filter +06-child.00000.03-attr.default=false +06-child.00000.03-attr.filterType=default +06-child.00000.03-attr.id=My Home +06-child.00000.03-attr.nonChangable=false +06-child.00000.03-attr.nonDeletable=false +06-child.00000.03-attr.nonRenamable=false +06-child.00000.03-attr.promptable=false +06-child.00000.03-attr.relativeOrder=0 +06-child.00000.03-attr.release=200 +06-child.00000.03-attr.singleFilterStringOnly=false +06-child.00000.03-attr.stringsCaseSensitive=false +06-child.00000.03-attr.stringsNonChangable=false +06-child.00000.03-attr.supportsDuplicateFilterStrings=false +06-child.00000.03-attr.supportsNestedFilters=true +06-child.00000.06-child.00000.00-name=C\:\\Users\\Bill\\* +06-child.00000.06-child.00000.01-type=FilterString +06-child.00000.06-child.00000.03-attr.default=false +06-child.00000.06-child.00000.03-attr.string=C\:\\Users\\Bill\\* +06-child.00000.06-child.00000.03-attr.type=default +06-child.00001.00-name=Drives +06-child.00001.01-type=Filter +06-child.00001.03-attr.default=false +06-child.00001.03-attr.filterType=default +06-child.00001.03-attr.id=Drives +06-child.00001.03-attr.nonChangable=false +06-child.00001.03-attr.nonDeletable=false +06-child.00001.03-attr.nonRenamable=false +06-child.00001.03-attr.promptable=false +06-child.00001.03-attr.relativeOrder=0 +06-child.00001.03-attr.release=200 +06-child.00001.03-attr.singleFilterStringOnly=false +06-child.00001.03-attr.stringsCaseSensitive=false +06-child.00001.03-attr.stringsNonChangable=false +06-child.00001.03-attr.supportsDuplicateFilterStrings=false +06-child.00001.03-attr.supportsNestedFilters=true +06-child.00001.06-child.00000.00-name=* +06-child.00001.06-child.00000.01-type=FilterString +06-child.00001.06-child.00000.03-attr.default=false +06-child.00001.06-child.00000.03-attr.string=* +06-child.00001.06-child.00000.03-attr.type=default diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.rse.core/profiles/PRF.bill-pc_67/H.local_16/node.properties b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.rse.core/profiles/PRF.bill-pc_67/H.local_16/node.properties new file mode 100644 index 00000000..698bf26d --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.rse.core/profiles/PRF.bill-pc_67/H.local_16/node.properties @@ -0,0 +1,25 @@ +# RSE DOM Node +00-name=Local +01-type=Host +03-attr.description= +03-attr.hostname=LOCALHOST +03-attr.offline=false +03-attr.promptable=false +03-attr.systemType=org.eclipse.rse.systemtype.local +03-attr.type=Local +06-child.00000.00-name=Local Connector Service +06-child.00000.01-type=ConnectorService +06-child.00000.03-attr.group=Local Connector Service +06-child.00000.03-attr.port=0 +06-child.00000.03-attr.useSSL=false +06-child.00000.06-child.00000.00-name=Local Files +06-child.00000.06-child.00000.01-type=SubSystem +06-child.00000.06-child.00000.03-attr.hidden=false +06-child.00000.06-child.00000.03-attr.type=local.files +06-child.00000.06-child.00000.06-child.00000.00-name=Bill-PC___Bill-PC\:local.files +06-child.00000.06-child.00000.06-child.00000.01-type=FilterPoolReference +06-child.00000.06-child.00000.06-child.00000.03-attr.refID=local.files +06-child.00000.06-child.00001.00-name=Local Shells +06-child.00000.06-child.00001.01-type=SubSystem +06-child.00000.06-child.00001.03-attr.hidden=false +06-child.00000.06-child.00001.03-attr.type=local.shells diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.rse.core/profiles/PRF.bill-pc_67/node.properties b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.rse.core/profiles/PRF.bill-pc_67/node.properties new file mode 100644 index 00000000..f87cb26d --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.rse.core/profiles/PRF.bill-pc_67/node.properties @@ -0,0 +1,7 @@ +# RSE DOM Node +00-name=Bill-PC +01-type=Profile +03-attr.defaultPrivate=true +03-attr.isActive=true +05-ref.00000=FP.local.files_0 +05-ref.00001=H.local_16 diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.rse.ui/.log b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.rse.ui/.log new file mode 100644 index 00000000..e69de29b diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.search/dialog_settings.xml b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.search/dialog_settings.xml new file mode 100644 index 00000000..41f63ea8 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.search/dialog_settings.xml @@ -0,0 +1,37 @@ + +
+
+ +
+
+ + + + + + + + + + + + + + + + +
+
+ +
+
+ +
+
+ + + + + +
+
diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.tm.terminal.connector.local/.executables/data.properties b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.tm.terminal.connector.local/.executables/data.properties new file mode 100644 index 00000000..82847953 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.tm.terminal.connector.local/.executables/data.properties @@ -0,0 +1,5 @@ +#Wed Jun 17 11:00:17 PDT 2020 +0.Path=C\:\\Program Files\\Git\\bin\\sh.exe +0.Name=Git Bash +0.Args=--login -i +0.Translate=true diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.ui.editors/dialog_settings.xml b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.ui.editors/dialog_settings.xml new file mode 100644 index 00000000..50f1edb3 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.ui.editors/dialog_settings.xml @@ -0,0 +1,5 @@ + +
+
+
+
diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml new file mode 100644 index 00000000..b9a1ae24 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml @@ -0,0 +1,14 @@ + +
+
+ + + + + + + + + +
+
diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml new file mode 100644 index 00000000..b51e34bf --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml @@ -0,0 +1,39 @@ + +
+
+ + +
+
+ + + + + + + + + + +
+
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+
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+
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+
diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml new file mode 100644 index 00000000..9ae7ae76 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml @@ -0,0 +1,4 @@ + + + + \ No newline at end of file diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.xtext.builder/builder.state b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.xtext.builder/builder.state new file mode 100644 index 00000000..8e25fe2a Binary files /dev/null and b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.eclipse.xtext.builder/builder.state differ diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.python.pydev/pyunit_tests/test_run_pin_info.txt b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.python.pydev/pyunit_tests/test_run_pin_info.txt new file mode 100644 index 00000000..27cc728d --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.python.pydev/pyunit_tests/test_run_pin_info.txt @@ -0,0 +1 @@ +|| \ No newline at end of file diff --git a/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.python.pydev/v1_3o76x04a9rox164awcru9p1ls/modulesKeys b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.python.pydev/v1_3o76x04a9rox164awcru9p1ls/modulesKeys new file mode 100644 index 00000000..3d82ecd9 --- /dev/null +++ b/ports/cortex_a5x/ac6/example_build/.metadata/.plugins/org.python.pydev/v1_3o76x04a9rox164awcru9p1ls/modulesKeys @@ -0,0 +1,31575 @@ +MODULES_MANAGER_V2 +--COMMON-- +15=C:\Program Files\DS-5 v5.24.0\sw\java\lib\ext\cldrdata.jar +12=C:\Program Files\DS-5 v5.24.0\sw\java\lib\ext\sunec.jar +1=C:\Program Files\DS-5 v5.24.0\sw\java\lib\jfr.jar +6=C:\Program Files\DS-5 v5.24.0\sw\java\lib\jsse.jar +0=C:\Program Files\DS-5 v5.24.0\sw\java\lib\ext\access-bridge-64.jar +16=C:\Program Files\DS-5 v5.24.0\sw\java\lib\ext\localedata.jar +8=C:\Program Files\DS-5 v5.24.0\sw\java\lib\jce.jar +13=C:\Program Files\DS-5 v5.24.0\sw\java\lib\ext\sunmscapi.jar +9=C:\Program Files\DS-5 v5.24.0\sw\java\lib\ext\nashorn.jar +10=C:\Program Files\DS-5 v5.24.0\sw\java\lib\charsets.jar +3=C:\Program Files\DS-5 v5.24.0\sw\java\lib\ext\sunjce_provider.jar +5=C:\Program Files\DS-5 v5.24.0\sw\java\lib\ext\jaccess.jar +2=C:\Program Files\DS-5 v5.24.0\sw\java\lib\rt.jar +7=C:\Program Files\DS-5 v5.24.0\sw\java\lib\ext\zipfs.jar +14=C:\Program Files\DS-5 v5.24.0\sw\java\lib\ext\sunpkcs11.jar +4=C:\Program Files\DS-5 v5.24.0\sw\java\lib\ext\jfxrt.jar +11=C:\Program Files\DS-5 v5.24.0\sw\java\lib\ext\dnsns.jar +--END-COMMON-- +MODULES_MANAGER_V2 +BaseHTTPServer|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\BaseHTTPServer.py +CGIHTTPServer|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\CGIHTTPServer.py +ConfigParser|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\ConfigParser.py +Cookie|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\Cookie.py +DocXMLRPCServer|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\DocXMLRPCServer.py +HTMLParser|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\HTMLParser.py +MimeWriter|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\MimeWriter.py +Queue|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\Queue.py +SimpleHTTPServer|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\SimpleHTTPServer.py +SimpleXMLRPCServer|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\SimpleXMLRPCServer.py +SocketServer|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\SocketServer.py +StringIO|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\StringIO.py +UserDict|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\UserDict.py +UserList|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\UserList.py +UserString|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\UserString.py +_LWPCookieJar|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\_LWPCookieJar.py +_MozillaCookieJar|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\_MozillaCookieJar.py +__builtin__ +__future__|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\__future__.py +_abcoll|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\_abcoll.py +_ast +_codecs +_collections +_csv +_fsum|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\_fsum.py +_functools +_google_ipaddr_r234|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\_google_ipaddr_r234.py +_hashlib +_jyio|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\_jyio.py +_marshal +_py_compile +_pydev_bundle.__init__|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_bundle\__init__.py +_pydev_bundle._pydev_completer|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_bundle\_pydev_completer.py +_pydev_bundle._pydev_filesystem_encoding|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_bundle\_pydev_filesystem_encoding.py +_pydev_bundle._pydev_getopt|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_bundle\_pydev_getopt.py +_pydev_bundle._pydev_imports_tipper|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_bundle\_pydev_imports_tipper.py +_pydev_bundle._pydev_jy_imports_tipper|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_bundle\_pydev_jy_imports_tipper.py +_pydev_bundle._pydev_log|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_bundle\_pydev_log.py +_pydev_bundle._pydev_tipper_common|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_bundle\_pydev_tipper_common.py +_pydev_bundle.fix_getpass|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_bundle\fix_getpass.py +_pydev_bundle.pydev_console_utils|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_bundle\pydev_console_utils.py +_pydev_bundle.pydev_import_hook|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_bundle\pydev_import_hook.py +_pydev_bundle.pydev_imports|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_bundle\pydev_imports.py +_pydev_bundle.pydev_ipython_console|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_bundle\pydev_ipython_console.py +_pydev_bundle.pydev_ipython_console_011|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_bundle\pydev_ipython_console_011.py +_pydev_bundle.pydev_is_thread_alive|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_bundle\pydev_is_thread_alive.py +_pydev_bundle.pydev_localhost|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_bundle\pydev_localhost.py +_pydev_bundle.pydev_log|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_bundle\pydev_log.py +_pydev_bundle.pydev_monkey|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_bundle\pydev_monkey.py +_pydev_bundle.pydev_monkey_qt|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_bundle\pydev_monkey_qt.py +_pydev_bundle.pydev_override|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_bundle\pydev_override.py +_pydev_bundle.pydev_umd|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_bundle\pydev_umd.py +_pydev_bundle.pydev_versioncheck|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_bundle\pydev_versioncheck.py +_pydev_imps.__init__|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_imps\__init__.py +_pydev_imps._pydev_BaseHTTPServer|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_imps\_pydev_BaseHTTPServer.py +_pydev_imps._pydev_SimpleXMLRPCServer|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_imps\_pydev_SimpleXMLRPCServer.py +_pydev_imps._pydev_SocketServer|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_imps\_pydev_SocketServer.py +_pydev_imps._pydev_execfile|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_imps\_pydev_execfile.py +_pydev_imps._pydev_inspect|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_imps\_pydev_inspect.py +_pydev_imps._pydev_pkgutil_old|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_imps\_pydev_pkgutil_old.py +_pydev_imps._pydev_saved_modules|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_imps\_pydev_saved_modules.py +_pydev_imps._pydev_sys_patch|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_imps\_pydev_sys_patch.py +_pydev_imps._pydev_uuid_old|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_imps\_pydev_uuid_old.py +_pydev_imps._pydev_xmlrpclib|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_imps\_pydev_xmlrpclib.py +_pydev_runfiles.__init__|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_runfiles\__init__.py +_pydev_runfiles.pydev_runfiles|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_runfiles\pydev_runfiles.py +_pydev_runfiles.pydev_runfiles_coverage|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_runfiles\pydev_runfiles_coverage.py +_pydev_runfiles.pydev_runfiles_nose|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_runfiles\pydev_runfiles_nose.py +_pydev_runfiles.pydev_runfiles_parallel|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_runfiles\pydev_runfiles_parallel.py +_pydev_runfiles.pydev_runfiles_parallel_client|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_runfiles\pydev_runfiles_parallel_client.py +_pydev_runfiles.pydev_runfiles_pytest2|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_runfiles\pydev_runfiles_pytest2.py +_pydev_runfiles.pydev_runfiles_unittest|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_runfiles\pydev_runfiles_unittest.py +_pydev_runfiles.pydev_runfiles_xml_rpc|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydev_runfiles\pydev_runfiles_xml_rpc.py +_pydevd_bundle.__init__|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\__init__.py +_pydevd_bundle.pydevconsole_code_for_ironpython|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevconsole_code_for_ironpython.py +_pydevd_bundle.pydevd_additional_thread_info|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_additional_thread_info.py +_pydevd_bundle.pydevd_additional_thread_info_regular|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_additional_thread_info_regular.py +_pydevd_bundle.pydevd_breakpoints|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_breakpoints.py +_pydevd_bundle.pydevd_comm|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_comm.py +_pydevd_bundle.pydevd_console|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_console.py +_pydevd_bundle.pydevd_constants|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_constants.py +_pydevd_bundle.pydevd_custom_frames|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_custom_frames.py +_pydevd_bundle.pydevd_cython|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_cython.pyx +_pydevd_bundle.pydevd_cython_win32_27_32|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_cython_win32_27_32.pyd +_pydevd_bundle.pydevd_cython_win32_27_64|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_cython_win32_27_64.pyd +_pydevd_bundle.pydevd_cython_win32_34_32|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_cython_win32_34_32.pyd +_pydevd_bundle.pydevd_cython_win32_34_64|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_cython_win32_34_64.pyd +_pydevd_bundle.pydevd_cython_wrapper|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_cython_wrapper.py +_pydevd_bundle.pydevd_dont_trace|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_dont_trace.py +_pydevd_bundle.pydevd_dont_trace_files|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_dont_trace_files.py +_pydevd_bundle.pydevd_exec|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_exec.py +_pydevd_bundle.pydevd_exec2|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_exec2.py +_pydevd_bundle.pydevd_frame|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_frame.py +_pydevd_bundle.pydevd_frame_utils|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_frame_utils.py +_pydevd_bundle.pydevd_import_class|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_import_class.py +_pydevd_bundle.pydevd_io|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_io.py +_pydevd_bundle.pydevd_kill_all_pydevd_threads|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_kill_all_pydevd_threads.py +_pydevd_bundle.pydevd_plugin_utils|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_plugin_utils.py +_pydevd_bundle.pydevd_process_net_command|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_process_net_command.py +_pydevd_bundle.pydevd_referrers|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_referrers.py +_pydevd_bundle.pydevd_reload|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_reload.py +_pydevd_bundle.pydevd_resolver|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_resolver.py +_pydevd_bundle.pydevd_save_locals|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_save_locals.py +_pydevd_bundle.pydevd_signature|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_signature.py +_pydevd_bundle.pydevd_stackless|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_stackless.py +_pydevd_bundle.pydevd_trace_api|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_trace_api.py +_pydevd_bundle.pydevd_trace_dispatch|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_trace_dispatch.py +_pydevd_bundle.pydevd_trace_dispatch_regular|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_trace_dispatch_regular.py +_pydevd_bundle.pydevd_traceproperty|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_traceproperty.py +_pydevd_bundle.pydevd_tracing|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_tracing.py +_pydevd_bundle.pydevd_utils|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_utils.py +_pydevd_bundle.pydevd_vars|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_vars.py +_pydevd_bundle.pydevd_vm_type|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_vm_type.py +_pydevd_bundle.pydevd_xml|C:\Program Files\DS-5 v5.27.0\sw\eclipse\plugins\org.python.pydev_5.1.2.201606231256\pysrc\_pydevd_bundle\pydevd_xml.py +_pyio|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\_pyio.py +_random +_rawffi|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\_rawffi.py +_socket|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\_socket.py +_sre +_sslcerts|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\_sslcerts.py +_strptime|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\_strptime.py +_systemrestart +_threading +_threading_local|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\_threading_local.py +_weakref +_weakrefset|C:\Program Files\DS-5 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v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\dbexts.py +decimal|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\decimal.py +difflib|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\difflib.py +dircache|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\dircache.py +dis|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\dis.py +distutils.__init__|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\__init__.py +distutils.archive_util|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\archive_util.py +distutils.bcppcompiler|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\bcppcompiler.py +distutils.ccompiler|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\ccompiler.py +distutils.cmd|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\cmd.py +distutils.command.__init__|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\command\__init__.py +distutils.command.bdist|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\command\bdist.py +distutils.command.bdist_dumb|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\command\bdist_dumb.py +distutils.command.bdist_msi|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\command\bdist_msi.py +distutils.command.bdist_rpm|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\command\bdist_rpm.py +distutils.command.bdist_wininst|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\command\bdist_wininst.py +distutils.command.build|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\command\build.py +distutils.command.build_clib|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\command\build_clib.py +distutils.command.build_ext|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\command\build_ext.py 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v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\command\register.py +distutils.command.sdist|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\command\sdist.py +distutils.command.upload|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\command\upload.py +distutils.config|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\config.py +distutils.core|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\core.py +distutils.cygwinccompiler|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\cygwinccompiler.py +distutils.debug|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\debug.py +distutils.dep_util|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\dep_util.py +distutils.dir_util|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\dir_util.py +distutils.dist|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\dist.py +distutils.emxccompiler|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\emxccompiler.py +distutils.errors|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\errors.py +distutils.extension|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\extension.py +distutils.fancy_getopt|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\fancy_getopt.py +distutils.file_util|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\file_util.py +distutils.filelist|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\filelist.py +distutils.jythoncompiler|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\jythoncompiler.py +distutils.log|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\log.py +distutils.msvc9compiler|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\msvc9compiler.py +distutils.msvccompiler|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\msvccompiler.py +distutils.spawn|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\spawn.py +distutils.sysconfig|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\sysconfig.py +distutils.tests.__init__|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\tests\__init__.py +distutils.tests.setuptools_build_ext|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\tests\setuptools_build_ext.py +distutils.tests.setuptools_extension|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\tests\setuptools_extension.py +distutils.tests.support|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\tests\support.py +distutils.tests.test_archive_util|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\tests\test_archive_util.py +distutils.tests.test_bdist|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\tests\test_bdist.py +distutils.tests.test_bdist_dumb|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\tests\test_bdist_dumb.py +distutils.tests.test_bdist_msi|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\tests\test_bdist_msi.py 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v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\tests\test_build_py.py +distutils.tests.test_build_scripts|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\tests\test_build_scripts.py +distutils.tests.test_ccompiler|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\tests\test_ccompiler.py +distutils.tests.test_check|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\tests\test_check.py +distutils.tests.test_clean|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\tests\test_clean.py +distutils.tests.test_cmd|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\tests\test_cmd.py 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v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\tests\test_dist.py +distutils.tests.test_file_util|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\tests\test_file_util.py +distutils.tests.test_filelist|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\tests\test_filelist.py +distutils.tests.test_install|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\tests\test_install.py +distutils.tests.test_install_data|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\tests\test_install_data.py +distutils.tests.test_install_headers|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\tests\test_install_headers.py +distutils.tests.test_install_lib|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\tests\test_install_lib.py +distutils.tests.test_install_scripts|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\tests\test_install_scripts.py +distutils.tests.test_msvc9compiler|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\tests\test_msvc9compiler.py +distutils.tests.test_register|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\tests\test_register.py +distutils.tests.test_sdist|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\tests\test_sdist.py +distutils.tests.test_spawn|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\tests\test_spawn.py +distutils.tests.test_sysconfig|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\tests\test_sysconfig.py +distutils.tests.test_text_file|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\tests\test_text_file.py +distutils.tests.test_unixccompiler|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\tests\test_unixccompiler.py +distutils.tests.test_upload|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\distutils\tests\test_upload.py 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v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\email\__init__.py +email._parseaddr|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\email\_parseaddr.py +email.base64mime|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\email\base64mime.py +email.charset|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\email\charset.py +email.encoders|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\email\encoders.py +email.errors|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\email\errors.py +email.feedparser|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\email\feedparser.py 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v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\email\mime\audio.py +email.mime.base|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\email\mime\base.py +email.mime.image|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\email\mime\image.py +email.mime.message|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\email\mime\message.py +email.mime.multipart|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\email\mime\multipart.py +email.mime.nonmultipart|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\email\mime\nonmultipart.py +email.mime.text|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\email\mime\text.py +email.parser|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\email\parser.py +email.quoprimime|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\email\quoprimime.py +email.test.__init__|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\email\test\__init__.py +email.test.test_email|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\email\test\test_email.py +email.test.test_email_codecs|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\email\test\test_email_codecs.py +email.test.test_email_codecs_renamed|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\email\test\test_email_codecs_renamed.py +email.test.test_email_renamed|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\email\test\test_email_renamed.py +email.test.test_email_torture|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\email\test\test_email_torture.py +email.utils|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\email\utils.py +encodings.__init__|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\__init__.py +encodings._java|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\_java.py +encodings.aliases|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\aliases.py +encodings.ascii|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\ascii.py +encodings.base64_codec|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\base64_codec.py +encodings.big5|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\big5.py +encodings.big5hkscs|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\big5hkscs.py +encodings.bz2_codec|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\bz2_codec.py +encodings.charmap|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\charmap.py +encodings.cp037|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\cp037.py +encodings.cp1006|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\cp1006.py +encodings.cp1026|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\cp1026.py +encodings.cp1140|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\cp1140.py +encodings.cp1250|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\cp1250.py +encodings.cp1251|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\cp1251.py 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v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\cp1258.py +encodings.cp424|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\cp424.py +encodings.cp437|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\cp437.py +encodings.cp500|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\cp500.py +encodings.cp720|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\cp720.py +encodings.cp737|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\cp737.py +encodings.cp775|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\cp775.py 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v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\cp860.py +encodings.cp861|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\cp861.py +encodings.cp862|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\cp862.py +encodings.cp863|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\cp863.py +encodings.cp864|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\cp864.py +encodings.cp865|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\cp865.py +encodings.cp866|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\cp866.py 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v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\euc_jis_2004.py +encodings.euc_jisx0213|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\euc_jisx0213.py +encodings.euc_jp|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\euc_jp.py +encodings.euc_kr|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\euc_kr.py +encodings.gb18030|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\gb18030.py +encodings.gb2312|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\gb2312.py +encodings.gbk|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\gbk.py +encodings.hex_codec|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\hex_codec.py +encodings.hp_roman8|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\hp_roman8.py +encodings.hz|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\hz.py +encodings.idna|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\idna.py +encodings.iso2022_jp|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\iso2022_jp.py +encodings.iso2022_jp_1|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\iso2022_jp_1.py +encodings.iso2022_jp_2|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\iso2022_jp_2.py +encodings.iso2022_jp_2004|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\iso2022_jp_2004.py +encodings.iso2022_jp_3|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\iso2022_jp_3.py +encodings.iso2022_jp_ext|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\iso2022_jp_ext.py +encodings.iso2022_kr|C:\Program Files\DS-5 v5.27.0\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20170426_161840\Jython\Lib\encodings\iso2022_kr.py +encodings.iso8859_1|C:\Program Files\DS-5 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v5.29.3\sw\eclipse\plugins\org.python.pydev_5.7.0.201704111357\pysrc\_pydev_bundle\pydev_localhost.py +_pydev_bundle.pydev_log|C:\Program Files\DS-5 v5.29.3\sw\eclipse\plugins\org.python.pydev_5.7.0.201704111357\pysrc\_pydev_bundle\pydev_log.py +_pydev_bundle.pydev_monkey|C:\Program Files\DS-5 v5.29.3\sw\eclipse\plugins\org.python.pydev_5.7.0.201704111357\pysrc\_pydev_bundle\pydev_monkey.py +_pydev_bundle.pydev_monkey_qt|C:\Program Files\DS-5 v5.29.3\sw\eclipse\plugins\org.python.pydev_5.7.0.201704111357\pysrc\_pydev_bundle\pydev_monkey_qt.py +_pydev_bundle.pydev_override|C:\Program Files\DS-5 v5.29.3\sw\eclipse\plugins\org.python.pydev_5.7.0.201704111357\pysrc\_pydev_bundle\pydev_override.py +_pydev_bundle.pydev_umd|C:\Program Files\DS-5 v5.29.3\sw\eclipse\plugins\org.python.pydev_5.7.0.201704111357\pysrc\_pydev_bundle\pydev_umd.py +_pydev_bundle.pydev_versioncheck|C:\Program Files\DS-5 v5.29.3\sw\eclipse\plugins\org.python.pydev_5.7.0.201704111357\pysrc\_pydev_bundle\pydev_versioncheck.py +_pydev_imps.__init__|C:\Program Files\DS-5 v5.29.3\sw\eclipse\plugins\org.python.pydev_5.7.0.201704111357\pysrc\_pydev_imps\__init__.py +_pydev_imps._pydev_BaseHTTPServer|C:\Program Files\DS-5 v5.29.3\sw\eclipse\plugins\org.python.pydev_5.7.0.201704111357\pysrc\_pydev_imps\_pydev_BaseHTTPServer.py +_pydev_imps._pydev_SimpleXMLRPCServer|C:\Program Files\DS-5 v5.29.3\sw\eclipse\plugins\org.python.pydev_5.7.0.201704111357\pysrc\_pydev_imps\_pydev_SimpleXMLRPCServer.py +_pydev_imps._pydev_SocketServer|C:\Program Files\DS-5 v5.29.3\sw\eclipse\plugins\org.python.pydev_5.7.0.201704111357\pysrc\_pydev_imps\_pydev_SocketServer.py +_pydev_imps._pydev_execfile|C:\Program Files\DS-5 v5.29.3\sw\eclipse\plugins\org.python.pydev_5.7.0.201704111357\pysrc\_pydev_imps\_pydev_execfile.py +_pydev_imps._pydev_inspect|C:\Program Files\DS-5 v5.29.3\sw\eclipse\plugins\org.python.pydev_5.7.0.201704111357\pysrc\_pydev_imps\_pydev_inspect.py +_pydev_imps._pydev_pkgutil_old|C:\Program Files\DS-5 v5.29.3\sw\eclipse\plugins\org.python.pydev_5.7.0.201704111357\pysrc\_pydev_imps\_pydev_pkgutil_old.py +_pydev_imps._pydev_saved_modules|C:\Program Files\DS-5 v5.29.3\sw\eclipse\plugins\org.python.pydev_5.7.0.201704111357\pysrc\_pydev_imps\_pydev_saved_modules.py +_pydev_imps._pydev_sys_patch|C:\Program Files\DS-5 v5.29.3\sw\eclipse\plugins\org.python.pydev_5.7.0.201704111357\pysrc\_pydev_imps\_pydev_sys_patch.py +_pydev_imps._pydev_uuid_old|C:\Program Files\DS-5 v5.29.3\sw\eclipse\plugins\org.python.pydev_5.7.0.201704111357\pysrc\_pydev_imps\_pydev_uuid_old.py +_pydev_imps._pydev_xmlrpclib|C:\Program Files\DS-5 v5.29.3\sw\eclipse\plugins\org.python.pydev_5.7.0.201704111357\pysrc\_pydev_imps\_pydev_xmlrpclib.py +_pydev_runfiles.__init__|C:\Program Files\DS-5 v5.29.3\sw\eclipse\plugins\org.python.pydev_5.7.0.201704111357\pysrc\_pydev_runfiles\__init__.py +_pydev_runfiles.pydev_runfiles|C:\Program Files\DS-5 v5.29.3\sw\eclipse\plugins\org.python.pydev_5.7.0.201704111357\pysrc\_pydev_runfiles\pydev_runfiles.py +_pydev_runfiles.pydev_runfiles_coverage|C:\Program Files\DS-5 v5.29.3\sw\eclipse\plugins\org.python.pydev_5.7.0.201704111357\pysrc\_pydev_runfiles\pydev_runfiles_coverage.py +_pydev_runfiles.pydev_runfiles_nose|C:\Program Files\DS-5 v5.29.3\sw\eclipse\plugins\org.python.pydev_5.7.0.201704111357\pysrc\_pydev_runfiles\pydev_runfiles_nose.py +_pydev_runfiles.pydev_runfiles_parallel|C:\Program Files\DS-5 v5.29.3\sw\eclipse\plugins\org.python.pydev_5.7.0.201704111357\pysrc\_pydev_runfiles\pydev_runfiles_parallel.py +_pydev_runfiles.pydev_runfiles_parallel_client|C:\Program Files\DS-5 v5.29.3\sw\eclipse\plugins\org.python.pydev_5.7.0.201704111357\pysrc\_pydev_runfiles\pydev_runfiles_parallel_client.py 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Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\contextlib.py +cookielib|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\cookielib.py +copy|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\copy.py +copy_reg|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\copy_reg.py +crypt|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\crypt.py +csv|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\csv.py +ctypes.__init__|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\ctypes\__init__.py +datetime|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\datetime.py +dbexts|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\dbexts.py +decimal|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\decimal.py +difflib|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\difflib.py +dircache|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\dircache.py +dis|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\dis.py +distutils.__init__|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\__init__.py +distutils.archive_util|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\archive_util.py +distutils.bcppcompiler|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\bcppcompiler.py +distutils.ccompiler|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\ccompiler.py +distutils.cmd|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\cmd.py +distutils.command.__init__|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\command\__init__.py +distutils.command.bdist|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\command\bdist.py +distutils.command.bdist_dumb|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\command\bdist_dumb.py +distutils.command.bdist_msi|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\command\bdist_msi.py +distutils.command.bdist_rpm|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\command\bdist_rpm.py +distutils.command.bdist_wininst|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\command\bdist_wininst.py +distutils.command.build|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\command\build.py +distutils.command.build_clib|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\command\build_clib.py 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v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\command\config.py +distutils.command.install|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\command\install.py +distutils.command.install_data|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\command\install_data.py +distutils.command.install_egg_info|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\command\install_egg_info.py +distutils.command.install_headers|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\command\install_headers.py +distutils.command.install_lib|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\command\install_lib.py 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v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\errors.py +distutils.extension|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\extension.py +distutils.fancy_getopt|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\fancy_getopt.py +distutils.file_util|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\file_util.py +distutils.filelist|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\filelist.py +distutils.jythoncompiler|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\jythoncompiler.py +distutils.log|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\log.py +distutils.msvc9compiler|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\msvc9compiler.py +distutils.msvccompiler|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\msvccompiler.py +distutils.spawn|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\spawn.py +distutils.sysconfig|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\sysconfig.py +distutils.tests.__init__|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\tests\__init__.py +distutils.tests.setuptools_build_ext|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\tests\setuptools_build_ext.py +distutils.tests.setuptools_extension|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\tests\setuptools_extension.py +distutils.tests.support|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\tests\support.py +distutils.tests.test_archive_util|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\tests\test_archive_util.py +distutils.tests.test_bdist|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\tests\test_bdist.py +distutils.tests.test_bdist_dumb|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\tests\test_bdist_dumb.py +distutils.tests.test_bdist_msi|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\tests\test_bdist_msi.py +distutils.tests.test_bdist_rpm|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\tests\test_bdist_rpm.py +distutils.tests.test_bdist_wininst|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\tests\test_bdist_wininst.py +distutils.tests.test_build|C:\Program Files\DS-5 v5.29.3\sw\eclipse\dropins\plugins\com.arm.tpip.jython_2.7.0.20191002_110027\Jython\Lib\distutils\tests\test_build.py +distutils.tests.test_build_clib|C:\Program Files\DS-5 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+org.eclipse.platform=4.6.3.v20170301-0400 diff --git a/ports/cortex_a5x/ac6/example_build/sample_threadx/.settings/language.settings.xml b/ports/cortex_a5x/ac6/example_build/sample_threadx/.settings/language.settings.xml index dd0920bb..fa9fc2a2 100644 --- a/ports/cortex_a5x/ac6/example_build/sample_threadx/.settings/language.settings.xml +++ b/ports/cortex_a5x/ac6/example_build/sample_threadx/.settings/language.settings.xml @@ -5,7 +5,7 @@ - + @@ -16,7 +16,7 @@ - + diff --git a/ports/cortex_a5x/ac6/example_build/tx/.settings/language.settings.xml b/ports/cortex_a5x/ac6/example_build/tx/.settings/language.settings.xml index 118220fc..96d0e56a 100644 --- a/ports/cortex_a5x/ac6/example_build/tx/.settings/language.settings.xml +++ b/ports/cortex_a5x/ac6/example_build/tx/.settings/language.settings.xml @@ -5,7 +5,7 @@ - + @@ -16,7 +16,7 @@ - + diff --git a/ports/cortex_a7/ac6/example_build/sample_threadx/.cproject b/ports/cortex_a7/ac6/example_build/sample_threadx/.cproject new file mode 100644 index 00000000..e5d3ef4b --- /dev/null +++ b/ports/cortex_a7/ac6/example_build/sample_threadx/.cproject @@ -0,0 +1,244 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_a7/ac6/example_build/sample_threadx/.project b/ports/cortex_a7/ac6/example_build/sample_threadx/.project new file mode 100644 index 00000000..a1b15572 --- /dev/null +++ b/ports/cortex_a7/ac6/example_build/sample_threadx/.project @@ -0,0 +1,26 @@ + + + sample_threadx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/ports/cortex_a7/ac6/example_build/sample_threadx/.settings/language.settings.xml b/ports/cortex_a7/ac6/example_build/sample_threadx/.settings/language.settings.xml new file mode 100644 index 00000000..1cd7d970 --- /dev/null +++ b/ports/cortex_a7/ac6/example_build/sample_threadx/.settings/language.settings.xml @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_a7/ac6/example_build/sample_threadx/cortex-a7_tx.launch b/ports/cortex_a7/ac6/example_build/sample_threadx/cortex-a7_tx.launch new file mode 100644 index 00000000..0bc5b11b --- /dev/null +++ b/ports/cortex_a7/ac6/example_build/sample_threadx/cortex-a7_tx.launch @@ -0,0 +1,188 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_a7/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a7/ac6/example_build/sample_threadx/sample_threadx.c new file mode 100644 index 00000000..418ec634 --- /dev/null +++ b/ports/cortex_a7/ac6/example_build/sample_threadx/sample_threadx.c @@ -0,0 +1,369 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_a7/ac6/example_build/sample_threadx/sample_threadx.scat b/ports/cortex_a7/ac6/example_build/sample_threadx/sample_threadx.scat new file mode 100644 index 00000000..82477876 --- /dev/null +++ b/ports/cortex_a7/ac6/example_build/sample_threadx/sample_threadx.scat @@ -0,0 +1,46 @@ +;******************************************************* +; Copyright (c) 2011-2016 Arm Limited (or its affiliates). All rights reserved. +; Use, modification and redistribution of this file is subject to your possession of a +; valid End User License Agreement for the Arm Product of which these examples are part of +; and your compliance with all applicable terms and conditions of such licence agreement. +;******************************************************* + +; Scatter-file for Cortex-A7 bare-metal example on Versatile Express + +; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map. + +; Versatile Express with Cortex-A7 has 1GB SDRAM at 0x60000000 to 0x9FFFFFFF, which this scatter-file uses. + + +SDRAM 0x80000000 0x20000000 +{ + VECTORS +0 + { + * (VECTORS, +FIRST) ; Vector table and other (assembler) startup code + * (InRoot$$Sections) ; All (library) code that must be in a root region + } + + RO_CODE +0 + { * (+RO-CODE) } ; Application RO code (.text) + + RO_DATA +0 + { * (+RO-DATA) } ; Application RO data (.constdata) + + RW_DATA +0 + { * (+RW) } ; Application RW data (.data) + + ZI_DATA +0 + { * (+ZI) } ; Application ZI data (.bss) + + ARM_LIB_HEAP 0x80040000 EMPTY 0x00040000 ; Application heap + { } + + ARM_LIB_STACK 0x80090000 EMPTY 0x00010000 ; Application (SVC mode) stack + { } + +; IRQ_STACK 0x800A0000 EMPTY -0x00010000 ; IRQ mode stack +; { } + + TTB 0x80100000 EMPTY 0x4000 ; Level-1 Translation Table for MMU + { } +} diff --git a/ports/cortex_a7/ac6/example_build/sample_threadx/startup.S b/ports/cortex_a7/ac6/example_build/sample_threadx/startup.S new file mode 100644 index 00000000..35be43cf --- /dev/null +++ b/ports/cortex_a7/ac6/example_build/sample_threadx/startup.S @@ -0,0 +1,355 @@ +//---------------------------------------------------------------- +// Cortex-A7 Embedded example - Startup Code +// +// Copyright (c) 2005-2018 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +//---------------------------------------------------------------- + + +// Standard definitions of mode bits and interrupt (I & F) flags in PSRs + +#define Mode_USR 0x10 +#define Mode_FIQ 0x11 +#define Mode_IRQ 0x12 +#define Mode_SVC 0x13 +#define Mode_ABT 0x17 +#define Mode_UND 0x1B +#define Mode_SYS 0x1F + +#define I_Bit 0x80 // When I bit is set, IRQ is disabled +#define F_Bit 0x40 // When F bit is set, FIQ is disabled + + + .section VECTORS, "ax" + .align 3 + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + + +//---------------------------------------------------------------- +// Entry point for the Reset handler +//---------------------------------------------------------------- + + .global Vectors + +//---------------------------------------------------------------- +// Exception Vector Table +//---------------------------------------------------------------- +// Note: LDR PC instructions are used here, though branch (B) instructions +// could also be used, unless the exception handlers are >32MB away. + +Vectors: + LDR PC, Reset_Addr + LDR PC, Undefined_Addr + LDR PC, SVC_Addr + LDR PC, Prefetch_Addr + LDR PC, Abort_Addr + LDR PC, Hypervisor_Addr + LDR PC, IRQ_Addr + LDR PC, FIQ_Addr + + + .balign 4 +Reset_Addr: + .word Reset_Handler +Undefined_Addr: + .word __tx_undefined +SVC_Addr: + .word __tx_swi_interrupt +Prefetch_Addr: + .word __tx_prefetch_handler +Abort_Addr: + .word __tx_abort_handler +Hypervisor_Addr: + .word __tx_reserved_handler +IRQ_Addr: + .word __tx_irq_handler +FIQ_Addr: + .word __tx_fiq_handler + + +//---------------------------------------------------------------- +// Exception Handlers +//---------------------------------------------------------------- + +Undefined_Handler: + B Undefined_Handler +SVC_Handler: + B SVC_Handler +Prefetch_Handler: + B Prefetch_Handler +Abort_Handler: + B Abort_Handler +Hypervisor_Handler: + B Hypervisor_Handler +IRQ_Handler: + B IRQ_Handler +FIQ_Handler: + B FIQ_Handler + + +//---------------------------------------------------------------- +// Reset Handler +//---------------------------------------------------------------- +Reset_Handler: + +//---------------------------------------------------------------- +// Disable caches and MMU in case they were left enabled from an earlier run +// This does not need to be done from a cold reset +//---------------------------------------------------------------- + + MRC p15, 0, r0, c1, c0, 0 // Read System Control Register + BIC r0, r0, #(0x1 << 12) // Clear I bit 12 to disable I Cache + BIC r0, r0, #(0x1 << 2) // Clear C bit 2 to disable D Cache + BIC r0, r0, #0x1 // Clear M bit 0 to disable MMU + MCR p15, 0, r0, c1, c0, 0 // Write System Control Register + ISB + +// The MMU is enabled later, before calling main(). Caches are enabled inside main(), +// after the MMU has been enabled and scatterloading has been performed. + +//---------------------------------------------------------------- +// ACTLR.SMP bit must be set before the caches and MMU are enabled, +// or any cache and TLB maintenance operations are performed, even for single-core +//---------------------------------------------------------------- + MRC p15, 0, r0, c1, c0, 1 // Read ACTLR + ORR r0, r0, #(1 << 6) // Set ACTLR.SMP bit + MCR p15, 0, r0, c1, c0, 1 // Write ACTLR + ISB + +//---------------------------------------------------------------- +// Invalidate Data and Instruction TLBs and branch predictor +// This does not need to be done from a cold reset +//---------------------------------------------------------------- + + MOV r0,#0 + MCR p15, 0, r0, c8, c7, 0 // I-TLB and D-TLB invalidation + MCR p15, 0, r0, c7, c5, 6 // BPIALL - Invalidate entire branch predictor array + +//---------------------------------------------------------------- +// Initialize Supervisor Mode Stack +// Note stack must be 8 byte aligned. +//---------------------------------------------------------------- + + LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit + +//---------------------------------------------------------------- +// Set Vector Base Address Register (VBAR) to point to this application's vector table +//---------------------------------------------------------------- + + LDR r0, =Vectors + MCR p15, 0, r0, c12, c0, 0 + +//---------------------------------------------------------------- +// Cache Invalidation code for Cortex-A7 +// The caches, MMU and BTB do not need post-reset invalidation on Cortex-A7, +// but forcing a cache invalidation makes the code more portable to other CPUs (e.g. Cortex-A9) +//---------------------------------------------------------------- + + // Invalidate L1 Instruction Cache + + MRC p15, 1, r0, c0, c0, 1 // Read Cache Level ID Register (CLIDR) + TST r0, #0x3 // Harvard Cache? + MOV r0, #0 // SBZ + MCRNE p15, 0, r0, c7, c5, 0 // ICIALLU - Invalidate instruction cache and flush branch target cache + + // Invalidate Data/Unified Caches + + MRC p15, 1, r0, c0, c0, 1 // Read CLIDR + ANDS r3, r0, #0x07000000 // Extract coherency level + MOV r3, r3, LSR #23 // Total cache levels << 1 + BEQ Finished // If 0, no need to clean + + MOV r10, #0 // R10 holds current cache level << 1 +Loop1: + ADD r2, r10, r10, LSR #1 // R2 holds cache "Set" position + MOV r1, r0, LSR r2 // Bottom 3 bits are the Cache-type for this level + AND r1, r1, #7 // Isolate those lower 3 bits + CMP r1, #2 + BLT Skip // No cache or only instruction cache at this level + + MCR p15, 2, r10, c0, c0, 0 // Write the Cache Size selection register + ISB // ISB to sync the change to the CacheSizeID reg + MRC p15, 1, r1, c0, c0, 0 // Reads current Cache Size ID register + AND r2, r1, #7 // Extract the line length field + ADD r2, r2, #4 // Add 4 for the line length offset (log2 16 bytes) + LDR r4, =0x3FF + ANDS r4, r4, r1, LSR #3 // R4 is the max number on the way size (right aligned) + CLZ r5, r4 // R5 is the bit position of the way size increment + LDR r7, =0x7FFF + ANDS r7, r7, r1, LSR #13 // R7 is the max number of the index size (right aligned) + +Loop2: + MOV r9, r4 // R9 working copy of the max way size (right aligned) + +Loop3: + ORR r11, r10, r9, LSL r5 // Factor in the Way number and cache number into R11 + ORR r11, r11, r7, LSL r2 // Factor in the Set number + MCR p15, 0, r11, c7, c6, 2 // Invalidate by Set/Way + SUBS r9, r9, #1 // Decrement the Way number + BGE Loop3 + SUBS r7, r7, #1 // Decrement the Set number + BGE Loop2 +Skip: + ADD r10, r10, #2 // Increment the cache number + CMP r3, r10 + BGT Loop1 + +Finished: + + +//---------------------------------------------------------------- +// MMU Configuration +// Set translation table base +//---------------------------------------------------------------- + + // Two translation tables are supported, TTBR0 and TTBR1 + // Configure translation table base (TTB) control register cp15,c2 + // to a value of all zeros, indicates we are using TTB register 0. + + MOV r0,#0x0 + MCR p15, 0, r0, c2, c0, 2 + + // write the address of our page table base to TTB register 0 + LDR r0,=Image$$TTB$$ZI$$Base + MOV r1, #0x08 // RGN=b01 (outer cacheable write-back cached, write allocate) + // S=0 (translation table walk to non-shared memory) + ORR r1,r1,#0x40 // IRGN=b01 (inner cacheability for the translation table walk is Write-back Write-allocate) + + ORR r0,r0,r1 + MCR p15, 0, r0, c2, c0, 0 + + +//---------------------------------------------------------------- +// PAGE TABLE generation + +// Generate the page tables +// Build a flat translation table for the whole address space. +// ie: Create 4096 1MB sections from 0x000xxxxx to 0xFFFxxxxx + + +// 31 20 19 18 17 16 15 14 12 11 10 9 8 5 4 3 2 1 0 +// |section base address| 0 0 |nG| S |AP2| TEX | AP | P | Domain | XN | C B | 1 0| +// +// Bits[31:20] - Top 12 bits of VA is pointer into table +// nG[17]=0 - Non global, enables matching against ASID in the TLB when set. +// S[16]=0 - Indicates normal memory is shared when set. +// AP2[15]=0 +// AP[11:10]=11 - Configure for full read/write access in all modes +// TEX[14:12]=000 +// CB[3:2]= 00 - Set attributes to Strongly-ordered memory. +// (except for the code segment descriptor, see below) +// IMPP[9]=0 - Ignored +// Domain[5:8]=1111 - Set all pages to use domain 15 +// XN[4]=1 - Execute never on Strongly-ordered memory +// Bits[1:0]=10 - Indicate entry is a 1MB section +//---------------------------------------------------------------- + LDR r0,=Image$$TTB$$ZI$$Base + LDR r1,=0xfff // loop counter + LDR r2,=0b00000000000000000000110111100010 + + // r0 contains the address of the translation table base + // r1 is loop counter + // r2 is level1 descriptor (bits 19:0) + + // use loop counter to create 4096 individual table entries. + // this writes from address 'Image$$TTB$$ZI$$Base' + + // offset 0x3FFC down to offset 0x0 in word steps (4 bytes) + +init_ttb_1: + ORR r3, r2, r1, LSL#20 // R3 now contains full level1 descriptor to write + ORR r3, r3, #0b0000000010000 // Set XN bit + STR r3, [r0, r1, LSL#2] // Str table entry at TTB base + loopcount*4 + SUBS r1, r1, #1 // Decrement loop counter + BPL init_ttb_1 + + // In this example, the 1MB section based at '__code_start' is setup specially as cacheable (write back mode). + // TEX[14:12]=001 and CB[3:2]= 11, Outer and inner write back, write allocate normal memory. + LDR r1,=Image$$VECTORS$$Base // Base physical address of code segment + LSR r1, #20 // Shift right to align to 1MB boundaries + ORR r3, r2, r1, LSL#20 // Setup the initial level1 descriptor again + ORR r3, r3, #0b0000000001100 // Set CB bits + ORR r3, r3, #0b1000000000000 // Set TEX bit 12 + STR r3, [r0, r1, LSL#2] // str table entry + +//---------------------------------------------------------------- +// Setup domain control register - Enable all domains to client mode +//---------------------------------------------------------------- + + MRC p15, 0, r0, c3, c0, 0 // Read Domain Access Control Register + LDR r0, =0x55555555 // Initialize every domain entry to b01 (client) + MCR p15, 0, r0, c3, c0, 0 // Write Domain Access Control Register + +#if defined(__ARM_NEON) || defined(__ARM_FP) +//---------------------------------------------------------------- +// Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11. +// Enables Full Access i.e. in both privileged and non privileged modes +//---------------------------------------------------------------- + + MRC p15, 0, r0, c1, c0, 2 // Read Coprocessor Access Control Register (CPACR) + ORR r0, r0, #(0xF << 20) // Enable access to CP 10 & 11 + MCR p15, 0, r0, c1, c0, 2 // Write Coprocessor Access Control Register (CPACR) + ISB + +//---------------------------------------------------------------- +// Switch on the VFP and NEON hardware +//---------------------------------------------------------------- + + MOV r0, #0x40000000 + VMSR FPEXC, r0 // Write FPEXC register, EN bit set +#endif + + +//---------------------------------------------------------------- +// Enable MMU and branch to __main +// Leaving the caches disabled until after scatter loading. +//---------------------------------------------------------------- + + LDR r12,=__main + + MRC p15, 0, r0, c1, c0, 0 // Read System Control Register + BIC r0, r0, #(0x1 << 12) // Clear I bit 12 to disable I Cache + BIC r0, r0, #(0x1 << 2) // Clear C bit 2 to disable D Cache + BIC r0, r0, #0x2 // Clear A bit 1 to disable strict alignment fault checking + ORR r0, r0, #0x1 // Set M bit 0 to enable MMU before scatter loading + MCR p15, 0, r0, c1, c0, 0 // Write System Control Register + ISB + +// Now the MMU is enabled, virtual to physical address translations will occur. This will affect the next +// instruction fetch. +// +// The two instructions currently in the pipeline will have been fetched before the MMU was enabled. +// The branch to __main is safe because the Virtual Address (VA) is the same as the Physical Address (PA) +// (flat mapping) of this code that enables the MMU and performs the branch + + BX r12 // Branch to __main C library entry point + + + +//---------------------------------------------------------------- +// Enable caches +// This code must be run from a privileged mode +//---------------------------------------------------------------- + + .section ENABLECACHES,"ax" + .align 3 + + .global enable_caches + .type enable_caches, "function" + .cfi_startproc +enable_caches: + +//---------------------------------------------------------------- +// Enable caches +//---------------------------------------------------------------- + + MRC p15, 0, r0, c1, c0, 0 // Read System Control Register + ORR r0, r0, #(0x1 << 12) // Set I bit 12 to enable I Cache + ORR r0, r0, #(0x1 << 2) // Set C bit 2 to enable D Cache + MCR p15, 0, r0, c1, c0, 0 // Write System Control Register + ISB + + BX lr + .cfi_endproc + diff --git a/ports/cortex_a7/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_a7/ac6/example_build/sample_threadx/tx_initialize_low_level.S new file mode 100644 index 00000000..c290d1c4 --- /dev/null +++ b/ports/cortex_a7/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -0,0 +1,344 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Initialize */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_initialize.h" +@#include "tx_thread.h" +@#include "tx_timer.h" + + .arm + +SVC_MODE = 0xD3 @ Disable IRQ/FIQ SVC mode +IRQ_MODE = 0xD2 @ Disable IRQ/FIQ IRQ mode +FIQ_MODE = 0xD1 @ Disable IRQ/FIQ FIQ mode +SYS_MODE = 0xDF @ Disable IRQ/FIQ SYS mode +FIQ_STACK_SIZE = 512 @ FIQ stack size +IRQ_STACK_SIZE = 1024 @ IRQ stack size +SYS_STACK_SIZE = 1024 @ System stack size +@ +@ + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global _tx_thread_context_save + .global _tx_thread_context_restore + .global _tx_timer_interrupt + +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_initialize_low_level for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .thumb + .global $_tx_initialize_low_level + .type $_tx_initialize_low_level,function +$_tx_initialize_low_level: + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_initialize_low_level @ Call _tx_initialize_low_level function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_initialize_low_level Cortex-A7/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for any low-level processor */ +@/* initialization, including setting up interrupt vectors, setting */ +@/* up a periodic timer interrupt source, saving the system stack */ +@/* pointer for use in ISR processing later, and finding the first */ +@/* available RAM memory address for tx_application_define. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_initialize_low_level(VOID) +@{ + .global _tx_initialize_low_level + .type _tx_initialize_low_level,function +_tx_initialize_low_level: +@ +@ /* We must be in SVC mode at this point! */ +@ +@ /* Setup various stack pointers. */ +@ + LDR r1, =Image$$ARM_LIB_STACK$$ZI$$Limit @ Get pointer to stack area + +#ifdef TX_ENABLE_IRQ_NESTING +@ +@ /* Setup the system mode stack for nested interrupt support */ +@ + LDR r2, =SYS_STACK_SIZE @ Pickup stack size + MOV r3, #SYS_MODE @ Build SYS mode CPSR + MSR CPSR_c, r3 @ Enter SYS mode + SUB r1, r1, #1 @ Backup 1 byte + BIC r1, r1, #7 @ Ensure 8-byte alignment + MOV sp, r1 @ Setup SYS stack pointer + SUB r1, r1, r2 @ Calculate start of next stack +#endif + + LDR r2, =FIQ_STACK_SIZE @ Pickup stack size + MOV r0, #FIQ_MODE @ Build FIQ mode CPSR + MSR CPSR, r0 @ Enter FIQ mode + SUB r1, r1, #1 @ Backup 1 byte + BIC r1, r1, #7 @ Ensure 8-byte alignment + MOV sp, r1 @ Setup FIQ stack pointer + SUB r1, r1, r2 @ Calculate start of next stack + LDR r2, =IRQ_STACK_SIZE @ Pickup IRQ stack size + MOV r0, #IRQ_MODE @ Build IRQ mode CPSR + MSR CPSR, r0 @ Enter IRQ mode + SUB r1, r1, #1 @ Backup 1 byte + BIC r1, r1, #7 @ Ensure 8-byte alignment + MOV sp, r1 @ Setup IRQ stack pointer + SUB r3, r1, r2 @ Calculate end of IRQ stack + MOV r0, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR, r0 @ Enter SVC mode + LDR r2, =Image$$ARM_LIB_STACK$$Base @ Pickup stack bottom + CMP r3, r2 @ Compare the current stack end with the bottom +_stack_error_loop: + BLT _stack_error_loop @ If the IRQ stack exceeds the stack bottom, just sit here! +@ +@ /* Save the system stack pointer. */ +@ _tx_thread_system_stack_ptr = (VOID_PTR) (sp); +@ + LDR r2, =_tx_thread_system_stack_ptr @ Pickup stack pointer + STR r1, [r2] @ Save the system stack +@ +@ /* Save the first available memory address. */ +@ _tx_initialize_unused_memory = (VOID_PTR) _end; +@ + LDR r1, =Image$$ZI_DATA$$ZI$$Limit @ Get end of non-initialized RAM area + LDR r2, =_tx_initialize_unused_memory @ Pickup unused memory ptr address + ADD r1, r1, #8 @ Increment to next free word + STR r1, [r2] @ Save first free memory address +@ +@ /* Setup Timer for periodic interrupts. */ +@ +@ /* Done, return to caller. */ +@ +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} +@ +@ +@/* Define shells for each of the interrupt vectors. */ +@ + .global __tx_undefined +__tx_undefined: + B __tx_undefined @ Undefined handler +@ + .global __tx_swi_interrupt +__tx_swi_interrupt: + B __tx_swi_interrupt @ Software interrupt handler +@ + .global __tx_prefetch_handler +__tx_prefetch_handler: + B __tx_prefetch_handler @ Prefetch exception handler +@ + .global __tx_abort_handler +__tx_abort_handler: + B __tx_abort_handler @ Abort exception handler +@ + .global __tx_reserved_handler +__tx_reserved_handler: + B __tx_reserved_handler @ Reserved exception handler +@ + .global __tx_irq_processing_return + .type __tx_irq_processing_return,function + .global __tx_irq_handler +__tx_irq_handler: +@ +@ /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return: +@ +@ /* At this point execution is still in the IRQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. In +@ addition, IRQ interrupts may be re-enabled - with certain restrictions - +@ if nested IRQ interrupts are desired. Interrupts may be re-enabled over +@ small code sequences where lr is saved before enabling interrupts and +@ restored after interrupts are again disabled. */ +@ +@ /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +@ from IRQ mode with interrupts disabled. This routine switches to the +@ system mode and returns with IRQ interrupts enabled. +@ +@ NOTE: It is very important to ensure all IRQ interrupts are cleared +@ prior to enabling nested IRQ interrupts. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_start +#endif +@ +@ /* For debug purpose, execute the timer interrupt processing here. In +@ a real system, some kind of status indication would have to be checked +@ before the timer interrupt handler could be called. */ +@ + BL _tx_timer_interrupt @ Timer interrupt handler +@ +@ +@ /* If interrupt nesting was started earlier, the end of interrupt nesting +@ service must be called before returning to _tx_thread_context_restore. +@ This routine returns in processing in IRQ mode with interrupts disabled. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_end +#endif +@ +@ /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore +@ +@ +@ /* This is an example of a vectored IRQ handler. */ +@ +@ .global __tx_example_vectored_irq_handler +@__tx_example_vectored_irq_handler: +@ +@ +@ /* Save initial context and call context save to prepare for +@ vectored ISR execution. */ +@ +@ STMDB sp!, {r0-r3} @ Save some scratch registers +@ MRS r0, SPSR @ Pickup saved SPSR +@ SUB lr, lr, #4 @ Adjust point of interrupt +@ STMDB sp!, {r0, r10, r12, lr} @ Store other scratch registers +@ BL _tx_thread_vectored_context_save @ Vectored context save +@ +@ /* At this point execution is still in the IRQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. In +@ addition, IRQ interrupts may be re-enabled - with certain restrictions - +@ if nested IRQ interrupts are desired. Interrupts may be re-enabled over +@ small code sequences where lr is saved before enabling interrupts and +@ restored after interrupts are again disabled. */ +@ +@ +@ /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +@ from IRQ mode with interrupts disabled. This routine switches to the +@ system mode and returns with IRQ interrupts enabled. +@ +@ NOTE: It is very important to ensure all IRQ interrupts are cleared +@ prior to enabling nested IRQ interrupts. */ +@#ifdef TX_ENABLE_IRQ_NESTING +@ BL _tx_thread_irq_nesting_start +@#endif +@ +@ /* Application IRQ handlers can be called here! */ +@ +@ /* If interrupt nesting was started earlier, the end of interrupt nesting +@ service must be called before returning to _tx_thread_context_restore. +@ This routine returns in processing in IRQ mode with interrupts disabled. */ +@#ifdef TX_ENABLE_IRQ_NESTING +@ BL _tx_thread_irq_nesting_end +@#endif +@ +@ /* Jump to context restore to restore system context. */ +@ B _tx_thread_context_restore +@ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + .global __tx_fiq_handler + .global __tx_fiq_processing_return +__tx_fiq_handler: +@ +@ /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +@ +@ /* At this point execution is still in the FIQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. */ +@ +@ /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +@ from FIQ mode with interrupts disabled. This routine switches to the +@ system mode and returns with FIQ interrupts enabled. +@ +@ NOTE: It is very important to ensure all FIQ interrupts are cleared +@ prior to enabling nested FIQ interrupts. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_start +#endif +@ +@ /* Application FIQ handlers can be called here! */ +@ +@ /* If interrupt nesting was started earlier, the end of interrupt nesting +@ service must be called before returning to _tx_thread_fiq_context_restore. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_end +#endif +@ +@ /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore +@ +@ +#else + .global __tx_fiq_handler +__tx_fiq_handler: + B __tx_fiq_handler @ FIQ interrupt handler +#endif +@ +@ +BUILD_OPTIONS: + .word _tx_build_options @ Reference to bring in +VERSION_ID: + .word _tx_version_id @ Reference to bring in + + diff --git a/ports/cortex_a7/ac6/example_build/tx/.cproject b/ports/cortex_a7/ac6/example_build/tx/.cproject new file mode 100644 index 00000000..306d5ecd --- /dev/null +++ b/ports/cortex_a7/ac6/example_build/tx/.cproject @@ -0,0 +1,212 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_a7/ac6/example_build/tx/.project b/ports/cortex_a7/ac6/example_build/tx/.project new file mode 100644 index 00000000..863ca5cb --- /dev/null +++ b/ports/cortex_a7/ac6/example_build/tx/.project @@ -0,0 +1,48 @@ + + + tx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + inc_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/inc + + + inc_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/inc + + + src_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/src + + + src_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/src + + + diff --git a/ports/cortex_a7/ac6/example_build/tx/.settings/language.settings.xml b/ports/cortex_a7/ac6/example_build/tx/.settings/language.settings.xml new file mode 100644 index 00000000..aec1b8ff --- /dev/null +++ b/ports/cortex_a7/ac6/example_build/tx/.settings/language.settings.xml @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_a7/ac6/inc/tx_port.h b/ports/cortex_a7/ac6/inc/tx_port.h new file mode 100644 index 00000000..282c5ed0 --- /dev/null +++ b/ports/cortex_a7/ac6/inc/tx_port.h @@ -0,0 +1,323 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A7/AC6 */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#if __TARGET_ARCH_ARM > 4 + +#ifndef __thumb__ + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + asm volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); \ + b = 31 - b; +#endif +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifdef __thumb__ + +unsigned int _tx_thread_interrupt_disable(void); +unsigned int _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save, tx_temp; + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); +#else +#define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID i ": "=r" (interrupt_save) ); +#endif + +#define TX_RESTORE asm volatile (" MSR CPSR_c,%0 "::"r" (interrupt_save) ); + +#endif + + +/* Define VFP extension for the Cortex-A7. Each is assumed to be called in the context of the executing + thread. */ + +void tx_thread_vfp_enable(void); +void tx_thread_vfp_disable(void); + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/AC6 Version 6.0.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + diff --git a/ports/cortex_a7/ac6/readme_threadx.txt b/ports/cortex_a7/ac6/readme_threadx.txt new file mode 100644 index 00000000..26861000 --- /dev/null +++ b/ports/cortex_a7/ac6/readme_threadx.txt @@ -0,0 +1,342 @@ + Microsoft's Azure RTOS ThreadX for Cortex-A7 + + Using ARM Compiler 6 & DS + +1. Import the ThreadX Projects + +In order to build the ThreadX library and the ThreadX demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +into your DS workspace. + + +2. Building the ThreadX run-time Library + +Building the ThreadX library is easy; simply right-click the Eclipse project +"tx" and then select the "Build Project" button. You should now observe the compilation +and assembly of the ThreadX library. This project build produces the ThreadX +library file tx.a. + + +3. Demonstration System + +The ThreadX demonstration is designed to execute under the DS debugger on the +VE_Cortex-A7 Bare Metal simulator. + +Building the demonstration is easy; simply right-click the Eclipse project +"sample_threadx" and then select the "Build Project" button. You should now observe +the compilation and assembly of the ThreadX demonstration. This project build produces +the ThreadX library file sample_threadx.axf. Next, expand the demo ThreadX project folder +in the Project Explorer window, right-click on the 'cortex-a7_tx.launch' file, click +'Debug As', and then click 'cortex-a7_tx' from the submenu. This will cause the +debugger to load the sample_threadx.axf ELF file and run to main. You are now ready +to execute the ThreadX demonstration. + + +4. System Initialization + +The entry point in ThreadX for the Cortex-A7 using ARM tools is at label +"Vectors". This is defined within startup.S in the sample_threadx project. In addition, +this is where all static and global pre-set C variable initialization processing +takes place. + +This is also where initialization of a periodic timer interrupt source should take +place. + +In addition, _tx_initialize_low_level defines the first available address +for use by the application, which is supplied as the sole input parameter +to your application definition function, tx_application_define. + + +5. Register Usage and Stack Frames + +The AC6 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread +is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 CPSR CPSR + 0x08 r0 (a1) r4 (v1) + 0x0C r1 (a2) r5 (v2) + 0x10 r2 (a3) r6 (v3) + 0x14 r3 (a4) r7 (v4) + 0x18 r4 (v1) r8 (v5) + 0x1C r5 (v2) r9 (v6) + 0x20 r6 (v3) r10 (v7) + 0x24 r7 (v4) r11 (fp) + 0x28 r8 (v5) r14 (lr) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) + 0x3C r14 (lr) + 0x40 PC + + +6. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-A7 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +7.1 Vector Area + +The Cortex-A7 vectors start at address zero. The demonstration system startup +reset.S file contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. + + +7.2 IRQ ISRs + +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports +nested IRQ interrupts. The following sub-sections define the IRQ capabilities. + + +7.2.1 Standard IRQ ISRs + +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +is the default IRQ handler defined in tx_initialize_low_level.S: + + .global __tx_irq_handler + .global __tx_irq_processing_return +__tx_irq_handler: +@ +@ /* Jump to context save to save system context. */ + B _tx_thread_context_save @ Jump to the context save +__tx_irq_processing_return: +@ +@ /* At this point execution is still in the IRQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. Note +@ that IRQ interrupts are still disabled upon return from the context +@ save function. */ +@ +@ /* Application ISR call(s) go here! */ +@ +@ /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.2 Vectored IRQ ISRs + +The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified +by the particular implementation. The following is an example IRQ handler defined in +tx_initialize_low_level.S: + + .global __tx_irq_example_handler +__tx_irq_example_handler: +@ +@ /* Call context save to save system context. */ + + STMDB sp!, {r0-r3} @ Save some scratch registers + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} @ Store other scratch registers + BL _tx_thread_vectored_context_save @ Call the vectored IRQ context save +@ +@ /* At this point execution is still in the IRQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. Note +@ that IRQ interrupts are still disabled upon return from the context +@ save function. */ +@ +@ /* Application ISR call goes here! */ +@ +@ /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.3 Nested IRQ Support + +By default, nested IRQ interrupt support is not enabled. To enable nested +IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING +defined. With this defined, two new IRQ interrupt management services are +available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. +These function should be called between the IRQ context save and restore +calls. + +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +by switching from IRQ mode to SYS mode and enabling IRQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.S. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in +preparation for the IRQ context restore service. + +The following is an example of enabling IRQ nested interrupts in a standard +IRQ handler: + + .global __tx_irq_handler + .global __tx_irq_processing_return +__tx_irq_handler: +@ +@ /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return: +@ +@ /* Enable nested IRQ interrupts. NOTE: Since this service returns +@ with IRQ interrupts enabled, all IRQ interrupt sources must be +@ cleared prior to calling this service. */ + BL _tx_thread_irq_nesting_start +@ +@ /* Application ISR call(s) go here! */ +@ +@ /* Disable nested IRQ interrupts. The mode is switched back to +@ IRQ mode and IRQ interrupts are disable upon return. */ + BL _tx_thread_irq_nesting_end +@ +@ /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.3 FIQ Interrupts + +By default, FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made +from default FIQ ISRs, which is located in tx_initialize_low_level.S. + + +7.3.1 Managed FIQ Interrupts + +Full ThreadX management of FIQ interrupts is provided if the ThreadX sources +are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built +this way, the FIQ interrupt handlers are very similar to the IRQ interrupt +handlers defined previously. The following is default FIQ handler +defined in tx_initialize_low_level.S: + + + .global __tx_fiq_handler + .global __tx_fiq_processing_return +__tx_fiq_handler: +@ +@ /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +@ +@ /* At this point execution is still in the FIQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. */ +@ +@ /* Application FIQ handlers can be called here! */ +@ +@ /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +7.3.1.1 Nested FIQ Support + +By default, nested FIQ interrupt support is not enabled. To enable nested +FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING +defined. With this defined, two new FIQ interrupt management services are +available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. +These function should be called between the FIQ context save and restore +calls. + +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +by switching from FIQ mode to SYS mode and enabling FIQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.S. When nested FIQ interrupts are no longer required, +calling the _tx_thread_fiq_nesting_end service disables nesting by disabling +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +context restore service. + +The following is an example of enabling FIQ nested interrupts in the +typical FIQ handler: + + + .global __tx_fiq_handler + .global __tx_fiq_processing_return +__tx_fiq_handler: +@ +@ /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +@ +@ /* At this point execution is still in the FIQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. */ +@ +@ /* Enable nested FIQ interrupts. NOTE: Since this service returns +@ with FIQ interrupts enabled, all FIQ interrupt sources must be +@ cleared prior to calling this service. */ + BL _tx_thread_fiq_nesting_start +@ +@ /* Application FIQ handlers can be called here! */ +@ +@ /* Disable nested FIQ interrupts. The mode is switched back to +@ FIQ mode and FIQ interrupts are disable upon return. */ + BL _tx_thread_fiq_nesting_end +@ +@ /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +8. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional but the remainder of +ThreadX will still run. + +To add the timer interrupt processing, simply make a call to +_tx_timer_interrupt in the IRQ processing. An example of this can be +found in the file tx_initialize_low_level.S for the demonstration system. + + +9. VFP Support + +By default, VFP support is disabled for each thread. If saving the context of the VFP registers +is needed, the following API call must be made from the context of the application thread - before +the VFP usage: + +void tx_thread_vfp_enable(void); + +After this API is called in the application, VFP registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the VFP registers +to be saved/restored. + +To disable VFP register context saving, simply call the following API: + +void tx_thread_vfp_disable(void); + + +10. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A7 using AC6 tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_a7/ac6/src/tx_thread_context_restore.S b/ports/cortex_a7/ac6/src/tx_thread_context_restore.S new file mode 100644 index 00000000..8611279e --- /dev/null +++ b/ports/cortex_a7/ac6/src/tx_thread_context_restore.S @@ -0,0 +1,256 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ + .arm + +#ifdef TX_ENABLE_FIQ_SUPPORT +SVC_MODE = 0xD3 @ Disable IRQ/FIQ, SVC mode +IRQ_MODE = 0xD2 @ Disable IRQ/FIQ, IRQ mode +#else +SVC_MODE = 0x93 @ Disable IRQ, SVC mode +IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode +#endif +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_restore Cortex-A7/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function restores the interrupt context if it is processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs Interrupt Service Routines */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_restore(VOID) +@{ + .global _tx_thread_context_restore + .type _tx_thread_context_restore,function +_tx_thread_context_restore: +@ +@ /* Lockout interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR exit function to indicate an ISR is complete. */ +@ + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif +@ +@ /* Determine if interrupts are nested. */ +@ if (--_tx_thread_system_state) +@ { +@ + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + SUB r2, r2, #1 @ Decrement the counter + STR r2, [r3] @ Store the counter + CMP r2, #0 @ Was this the first interrupt? + BEQ __tx_thread_not_nested_restore @ If so, not a nested restore +@ +@ /* Interrupts are nested. */ +@ +@ /* Just recover the saved registers and return to the point of +@ interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +__tx_thread_not_nested_restore: +@ +@ /* Determine if a thread was interrupted and no preemption is required. */ +@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +@ || (_tx_thread_preempt_disable)) +@ { +@ + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup actual current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_restore @ Yes, idle system was interrupted +@ + LDR r3, =_tx_thread_preempt_disable @ Pickup preempt disable address + LDR r2, [r3] @ Pickup actual preempt disable flag + CMP r2, #0 @ Is it set? + BNE __tx_thread_no_preempt_restore @ Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr @ Pickup address of execute thread ptr + LDR r2, [r3] @ Pickup actual execute thread pointer + CMP r0, r2 @ Is the same thread highest priority? + BNE __tx_thread_preempt_restore @ No, preemption needs to happen +@ +@ +__tx_thread_no_preempt_restore: +@ +@ /* Restore interrupted thread or ISR. */ +@ +@ /* Pickup the saved stack pointer. */ +@ tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +@ +@ /* Recover the saved context and return to the point of interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +@ else +@ { +__tx_thread_preempt_restore: +@ + LDMIA sp!, {r3, r10, r12, lr} @ Recover temporarily saved registers + MOV r1, lr @ Save lr (point of interrupt) + MOV r2, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r2 @ Enter SVC mode + STR r1, [sp, #-4]! @ Save point of interrupt + STMDB sp!, {r4-r12, lr} @ Save upper half of registers + MOV r4, r3 @ Save SPSR in r4 + MOV r2, #IRQ_MODE @ Build IRQ mode CPSR + MSR CPSR_c, r2 @ Enter IRQ mode + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOV r5, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r5 @ Enter SVC mode + STMDB sp!, {r0-r3} @ Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r2, [r0, #144] @ Pickup the VFP enabled flag + CMP r2, #0 @ Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save @ No, skip VFP IRQ save + VMRS r2, FPSCR @ Pickup the FPSCR + STR r2, [sp, #-4]! @ Save FPSCR + VSTMDB sp!, {D16-D31} @ Save D16-D31 + VSTMDB sp!, {D0-D15} @ Save D0-D15 +_tx_skip_irq_vfp_save: +#endif + + MOV r3, #1 @ Build interrupt stack type + STMDB sp!, {r3, r4} @ Save interrupt stack type and SPSR + STR sp, [r0, #8] @ Save stack pointer in thread control + @ block +@ +@ /* Save the remaining time-slice and disable it. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup time-slice variable address + LDR r2, [r3] @ Pickup time-slice + CMP r2, #0 @ Is it active? + BEQ __tx_thread_dont_save_ts @ No, don't save it +@ +@ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +@ _tx_timer_time_slice = 0; +@ + STR r2, [r0, #24] @ Save thread's time-slice + MOV r2, #0 @ Clear value + STR r2, [r3] @ Disable global time-slice flag +@ +@ } +__tx_thread_dont_save_ts: +@ +@ +@ /* Clear the current task pointer. */ +@ _tx_thread_current_ptr = TX_NULL; +@ + MOV r0, #0 @ NULL value + STR r0, [r1] @ Clear current thread pointer +@ +@ /* Return to the scheduler. */ +@ _tx_thread_schedule(); +@ + B _tx_thread_schedule @ Return to scheduler +@ } +@ +__tx_thread_idle_system_restore: +@ +@ /* Just return back to the scheduler! */ +@ + MOV r0, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r0 @ Enter SVC mode + B _tx_thread_schedule @ Return to scheduler +@} + + + diff --git a/ports/cortex_a7/ac6/src/tx_thread_context_save.S b/ports/cortex_a7/ac6/src/tx_thread_context_save.S new file mode 100644 index 00000000..126f5417 --- /dev/null +++ b/ports/cortex_a7/ac6/src/tx_thread_context_save.S @@ -0,0 +1,202 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global __tx_irq_processing_return +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_save Cortex-A7/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_save(VOID) +@{ + .global _tx_thread_context_save + .type _tx_thread_context_save,function +_tx_thread_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state++) +@ { +@ + STMDB sp!, {r0-r3} @ Save some working registers +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable FIQ interrupts +#endif + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable +@ +@ /* Save the rest of the scratch registers on the stack and return to the +@ calling ISR. */ +@ + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} @ Store other registers +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_irq_processing_return @ Continue IRQ processing +@ +__tx_thread_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + @ scheduling loop - nothing needs saving! +@ +@ /* Save minimal context of interrupted thread. */ +@ + MRS r2, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r2, r10, r12, lr} @ Store other registers +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr@ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_irq_processing_return @ Continue IRQ processing +@ +@ } +@ else +@ { +@ +__tx_thread_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ processing. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + ADD sp, sp, #16 @ Recover saved registers + B __tx_irq_processing_return @ Continue IRQ processing +@ +@ } +@} + + + diff --git a/ports/cortex_a7/ac6/src/tx_thread_fiq_context_restore.S b/ports/cortex_a7/ac6/src/tx_thread_fiq_context_restore.S new file mode 100644 index 00000000..3130be5a --- /dev/null +++ b/ports/cortex_a7/ac6/src/tx_thread_fiq_context_restore.S @@ -0,0 +1,259 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ +SVC_MODE = 0xD3 @ SVC mode +FIQ_MODE = 0xD1 @ FIQ mode +MODE_MASK = 0x1F @ Mode mask +THUMB_MASK = 0x20 @ Thumb bit mask +IRQ_MODE_BITS = 0x12 @ IRQ mode bits +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_system_stack_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_context_restore +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_context_restore Cortex-A7/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function restores the fiq interrupt context when processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* FIQ ISR Interrupt Service Routines */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_fiq_context_restore(VOID) +@{ + .global _tx_thread_fiq_context_restore + .type _tx_thread_fiq_context_restore,function +_tx_thread_fiq_context_restore: +@ +@ /* Lockout interrupts. */ +@ + CPSID if @ Disable IRQ and FIQ interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR exit function to indicate an ISR is complete. */ +@ + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif +@ +@ /* Determine if interrupts are nested. */ +@ if (--_tx_thread_system_state) +@ { +@ + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + SUB r2, r2, #1 @ Decrement the counter + STR r2, [r3] @ Store the counter + CMP r2, #0 @ Was this the first interrupt? + BEQ __tx_thread_fiq_not_nested_restore @ If so, not a nested restore +@ +@ /* Interrupts are nested. */ +@ +@ /* Just recover the saved registers and return to the point of +@ interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +__tx_thread_fiq_not_nested_restore: +@ +@ /* Determine if a thread was interrupted and no preemption is required. */ +@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +@ || (_tx_thread_preempt_disable)) +@ { +@ + LDR r1, [sp] @ Pickup the saved SPSR + MOV r2, #MODE_MASK @ Build mask to isolate the interrupted mode + AND r1, r1, r2 @ Isolate mode bits + CMP r1, #IRQ_MODE_BITS @ Was an interrupt taken in IRQ mode before we + @ got to context save? */ + BEQ __tx_thread_fiq_no_preempt_restore @ Yes, just go back to point of interrupt + + + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup actual current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_fiq_idle_system_restore @ Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable @ Pickup preempt disable address + LDR r2, [r3] @ Pickup actual preempt disable flag + CMP r2, #0 @ Is it set? + BNE __tx_thread_fiq_no_preempt_restore @ Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr @ Pickup address of execute thread ptr + LDR r2, [r3] @ Pickup actual execute thread pointer + CMP r0, r2 @ Is the same thread highest priority? + BNE __tx_thread_fiq_preempt_restore @ No, preemption needs to happen + + +__tx_thread_fiq_no_preempt_restore: +@ +@ /* Restore interrupted thread or ISR. */ +@ +@ /* Pickup the saved stack pointer. */ +@ tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +@ +@ /* Recover the saved context and return to the point of interrupt. */ +@ + LDMIA sp!, {r0, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +@ else +@ { +__tx_thread_fiq_preempt_restore: +@ + LDMIA sp!, {r3, lr} @ Recover temporarily saved registers + MOV r1, lr @ Save lr (point of interrupt) + MOV r2, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r2 @ Enter SVC mode + STR r1, [sp, #-4]! @ Save point of interrupt + STMDB sp!, {r4-r12, lr} @ Save upper half of registers + MOV r4, r3 @ Save SPSR in r4 + MOV r2, #FIQ_MODE @ Build FIQ mode CPSR + MSR CPSR_c, r2 @ Reenter FIQ mode + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOV r5, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r5 @ Enter SVC mode + STMDB sp!, {r0-r3} @ Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r2, [r0, #144] @ Pickup the VFP enabled flag + CMP r2, #0 @ Is the VFP enabled? + BEQ _tx_skip_fiq_vfp_save @ No, skip VFP IRQ save + VMRS r2, FPSCR @ Pickup the FPSCR + STR r2, [sp, #-4]! @ Save FPSCR + VSTMDB sp!, {D16-D31} @ Save D16-D31 + VSTMDB sp!, {D0-D15} @ Save D0-D15 +_tx_skip_fiq_vfp_save: +#endif + + MOV r3, #1 @ Build interrupt stack type + STMDB sp!, {r3, r4} @ Save interrupt stack type and SPSR + STR sp, [r0, #8] @ Save stack pointer in thread control + @ block */ +@ +@ /* Save the remaining time-slice and disable it. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup time-slice variable address + LDR r2, [r3] @ Pickup time-slice + CMP r2, #0 @ Is it active? + BEQ __tx_thread_fiq_dont_save_ts @ No, don't save it +@ +@ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +@ _tx_timer_time_slice = 0; +@ + STR r2, [r0, #24] @ Save thread's time-slice + MOV r2, #0 @ Clear value + STR r2, [r3] @ Disable global time-slice flag +@ +@ } +__tx_thread_fiq_dont_save_ts: +@ +@ +@ /* Clear the current task pointer. */ +@ _tx_thread_current_ptr = TX_NULL; +@ + MOV r0, #0 @ NULL value + STR r0, [r1] @ Clear current thread pointer +@ +@ /* Return to the scheduler. */ +@ _tx_thread_schedule(); +@ + B _tx_thread_schedule @ Return to scheduler +@ } +@ +__tx_thread_fiq_idle_system_restore: +@ +@ /* Just return back to the scheduler! */ +@ + ADD sp, sp, #24 @ Recover FIQ stack space + MOV r3, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r3 @ Lockout interrupts + B _tx_thread_schedule @ Return to scheduler +@ +@} + diff --git a/ports/cortex_a7/ac6/src/tx_thread_fiq_context_save.S b/ports/cortex_a7/ac6/src/tx_thread_fiq_context_save.S new file mode 100644 index 00000000..7ffdb84d --- /dev/null +++ b/ports/cortex_a7/ac6/src/tx_thread_fiq_context_save.S @@ -0,0 +1,203 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global __tx_fiq_processing_return +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_context_save +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_context_save Cortex-A7/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@ VOID _tx_thread_fiq_context_save(VOID) +@{ + .global _tx_thread_fiq_context_save + .type _tx_thread_fiq_context_save,function +_tx_thread_fiq_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state++) +@ { +@ + STMDB sp!, {r0-r3} @ Save some working registers + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_fiq_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable +@ +@ /* Save the rest of the scratch registers on the stack and return to the +@ calling ISR. */ +@ + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} @ Store other registers +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_fiq_processing_return @ Continue FIQ processing +@ +__tx_thread_fiq_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_fiq_idle_system_save @ If so, interrupt occurred in +@ @ scheduling loop - nothing needs saving! +@ +@ /* Save minimal context of interrupted thread. */ +@ + MRS r2, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r2, lr} @ Store other registers, Note that we don't +@ @ need to save sl and ip since FIQ has +@ @ copies of these registers. Nested +@ @ interrupt processing does need to save +@ @ these registers. +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr; +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_fiq_processing_return @ Continue FIQ processing +@ +@ } +@ else +@ { +@ +__tx_thread_fiq_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif +@ +@ /* Not much to do here, save the current SPSR and LR for possible +@ use in IRQ interrupted in idle system conditions, and return to +@ FIQ interrupt processing. */ +@ + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, lr} @ Store other registers that will get used +@ @ or stripped off the stack in context +@ @ restore + B __tx_fiq_processing_return @ Continue FIQ processing +@ +@ } +@} + diff --git a/ports/cortex_a7/ac6/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a7/ac6/src/tx_thread_fiq_nesting_end.S new file mode 100644 index 00000000..9965a19b --- /dev/null +++ b/ports/cortex_a7/ac6/src/tx_thread_fiq_nesting_end.S @@ -0,0 +1,116 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts +#else +DISABLE_INTS = 0x80 @ Disable IRQ interrupts +#endif +MODE_MASK = 0x1F @ Mode mask +FIQ_MODE_BITS = 0x11 @ FIQ mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_end +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_nesting_end Cortex-A7/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from FIQ mode after */ +@/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +@/* processing from system mode back to FIQ mode prior to the ISR */ +@/* calling _tx_thread_fiq_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with FIQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_fiq_nesting_end(VOID) +@{ + .global _tx_thread_fiq_nesting_end + .type _tx_thread_fiq_nesting_end,function +_tx_thread_fiq_nesting_end: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value + MSR CPSR_c, r0 @ Disable interrupts + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + @ 8-byte alignment logic) + BIC r0, r0, #MODE_MASK @ Clear mode bits + ORR r0, r0, #FIQ_MODE_BITS @ Build IRQ mode CPSR + MSR CPSR_c, r0 @ Reenter IRQ mode + +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_a7/ac6/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a7/ac6/src/tx_thread_fiq_nesting_start.S new file mode 100644 index 00000000..83082588 --- /dev/null +++ b/ports/cortex_a7/ac6/src/tx_thread_fiq_nesting_start.S @@ -0,0 +1,108 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +FIQ_DISABLE = 0x40 @ FIQ disable bit +MODE_MASK = 0x1F @ Mode mask +SYS_MODE_BITS = 0x1F @ System mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_start +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_nesting_start Cortex-A7/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from FIQ mode after */ +@/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +@/* processing to the system mode so nested FIQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with FIQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_fiq_nesting_start(VOID) +@{ + .global _tx_thread_fiq_nesting_start + .type _tx_thread_fiq_nesting_start,function +_tx_thread_fiq_nesting_start: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + BIC r0, r0, #MODE_MASK @ Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS @ Build system mode CPSR + MSR CPSR_c, r0 @ Enter system mode + STMDB sp!, {r1, lr} @ Push the system mode lr on the system mode stack + @ and push r1 just to keep 8-byte alignment + BIC r0, r0, #FIQ_DISABLE @ Build enable FIQ CPSR + MSR CPSR_c, r0 @ Enter system mode +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_a7/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a7/ac6/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..cabd14cc --- /dev/null +++ b/ports/cortex_a7/ac6/src/tx_thread_interrupt_control.S @@ -0,0 +1,115 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" */ +@ + +INT_MASK = 0x03F + +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_control for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_interrupt_control +$_tx_thread_interrupt_control: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_interrupt_control @ Call _tx_thread_interrupt_control function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_control Cortex-A7/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for changing the interrupt lockout */ +@/* posture of the system. */ +@/* */ +@/* INPUT */ +@/* */ +@/* new_posture New interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_control(UINT new_posture) +@{ + .global _tx_thread_interrupt_control + .type _tx_thread_interrupt_control,function +_tx_thread_interrupt_control: +@ +@ /* Pickup current interrupt lockout posture. */ +@ + MRS r3, CPSR @ Pickup current CPSR + MOV r2, #INT_MASK @ Build interrupt mask + AND r1, r3, r2 @ Clear interrupt lockout bits + ORR r1, r1, r0 @ Or-in new interrupt lockout bits +@ +@ /* Apply the new interrupt posture. */ +@ + MSR CPSR_c, r1 @ Setup new CPSR + BIC r0, r3, r2 @ Return previous interrupt mask +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + diff --git a/ports/cortex_a7/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a7/ac6/src/tx_thread_interrupt_disable.S new file mode 100644 index 00000000..3774e330 --- /dev/null +++ b/ports/cortex_a7/ac6/src/tx_thread_interrupt_disable.S @@ -0,0 +1,113 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_interrupt_disable +$_tx_thread_interrupt_disable: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_interrupt_disable @ Call _tx_thread_interrupt_disable function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_disable Cortex-A7/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for disabling interrupts */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_disable(void) +@{ + .global _tx_thread_interrupt_disable + .type _tx_thread_interrupt_disable,function +_tx_thread_interrupt_disable: +@ +@ /* Pickup current interrupt lockout posture. */ +@ + MRS r0, CPSR @ Pickup current CPSR +@ +@ /* Mask interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ +#else + CPSID i @ Disable IRQ +#endif + +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + + diff --git a/ports/cortex_a7/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a7/ac6/src/tx_thread_interrupt_restore.S new file mode 100644 index 00000000..ca9f64c1 --- /dev/null +++ b/ports/cortex_a7/ac6/src/tx_thread_interrupt_restore.S @@ -0,0 +1,104 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_interrupt_restore +$_tx_thread_interrupt_restore: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_interrupt_restore @ Call _tx_thread_interrupt_restore function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_restore Cortex-A7/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for restoring interrupts to the state */ +@/* returned by a previous _tx_thread_interrupt_disable call. */ +@/* */ +@/* INPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_restore(UINT old_posture) +@{ + .global _tx_thread_interrupt_restore + .type _tx_thread_interrupt_restore,function +_tx_thread_interrupt_restore: +@ +@ /* Apply the new interrupt posture. */ +@ + MSR CPSR_c, r0 @ Setup new CPSR +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + diff --git a/ports/cortex_a7/ac6/src/tx_thread_irq_nesting_end.S b/ports/cortex_a7/ac6/src/tx_thread_irq_nesting_end.S new file mode 100644 index 00000000..14a4ce8c --- /dev/null +++ b/ports/cortex_a7/ac6/src/tx_thread_irq_nesting_end.S @@ -0,0 +1,115 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts +#else +DISABLE_INTS = 0x80 @ Disable IRQ interrupts +#endif +MODE_MASK = 0x1F @ Mode mask +IRQ_MODE_BITS = 0x12 @ IRQ mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_end +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_end Cortex-A7/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +@/* processing from system mode back to IRQ mode prior to the ISR */ +@/* calling _tx_thread_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_irq_nesting_end(VOID) +@{ + .global _tx_thread_irq_nesting_end + .type _tx_thread_irq_nesting_end,function +_tx_thread_irq_nesting_end: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value + MSR CPSR_c, r0 @ Disable interrupts + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + @ 8-byte alignment logic) + BIC r0, r0, #MODE_MASK @ Clear mode bits + ORR r0, r0, #IRQ_MODE_BITS @ Build IRQ mode CPSR + MSR CPSR_c, r0 @ Reenter IRQ mode +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_a7/ac6/src/tx_thread_irq_nesting_start.S b/ports/cortex_a7/ac6/src/tx_thread_irq_nesting_start.S new file mode 100644 index 00000000..9126b19c --- /dev/null +++ b/ports/cortex_a7/ac6/src/tx_thread_irq_nesting_start.S @@ -0,0 +1,108 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +IRQ_DISABLE = 0x80 @ IRQ disable bit +MODE_MASK = 0x1F @ Mode mask +SYS_MODE_BITS = 0x1F @ System mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_start +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_start Cortex-A7/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_context_save has been called and switches the IRQ */ +@/* processing to the system mode so nested IRQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_irq_nesting_start(VOID) +@{ + .global _tx_thread_irq_nesting_start + .type _tx_thread_irq_nesting_start,function +_tx_thread_irq_nesting_start: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + BIC r0, r0, #MODE_MASK @ Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS @ Build system mode CPSR + MSR CPSR_c, r0 @ Enter system mode + STMDB sp!, {r1, lr} @ Push the system mode lr on the system mode stack + @ and push r1 just to keep 8-byte alignment + BIC r0, r0, #IRQ_DISABLE @ Build enable IRQ CPSR + MSR CPSR_c, r0 @ Enter system mode +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_a7/ac6/src/tx_thread_schedule.S b/ports/cortex_a7/ac6/src/tx_thread_schedule.S new file mode 100644 index 00000000..e2bdd523 --- /dev/null +++ b/ports/cortex_a7/ac6/src/tx_thread_schedule.S @@ -0,0 +1,254 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_execute_ptr + .global _tx_thread_current_ptr + .global _tx_timer_time_slice +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_schedule for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_schedule + .type $_tx_thread_schedule,function +$_tx_thread_schedule: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_schedule @ Call _tx_thread_schedule function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_schedule Cortex-A7/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function waits for a thread control block pointer to appear in */ +@/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +@/* in the variable, the corresponding thread is resumed. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* _tx_thread_system_return Return to system from thread */ +@/* _tx_thread_context_restore Restore thread's context */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_schedule(VOID) +@{ + .global _tx_thread_schedule + .type _tx_thread_schedule,function +_tx_thread_schedule: +@ +@ /* Enable interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSIE if @ Enable IRQ and FIQ interrupts +#else + CPSIE i @ Enable IRQ interrupts +#endif +@ +@ /* Wait for a thread to execute. */ +@ do +@ { + LDR r1, =_tx_thread_execute_ptr @ Address of thread execute ptr +@ +__tx_thread_schedule_loop: +@ + LDR r0, [r1] @ Pickup next thread to execute + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_schedule_loop @ If so, keep looking for a thread +@ +@ } +@ while(_tx_thread_execute_ptr == TX_NULL); +@ +@ /* Yes! We have a thread to execute. Lockout interrupts and +@ transfer control to it. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif +@ +@ /* Setup the current thread pointer. */ +@ _tx_thread_current_ptr = _tx_thread_execute_ptr; +@ + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread + STR r0, [r1] @ Setup current thread pointer +@ +@ /* Increment the run count for this thread. */ +@ _tx_thread_current_ptr -> tx_thread_run_count++; +@ + LDR r2, [r0, #4] @ Pickup run counter + LDR r3, [r0, #24] @ Pickup time-slice for this thread + ADD r2, r2, #1 @ Increment thread run-counter + STR r2, [r0, #4] @ Store the new run counter +@ +@ /* Setup time-slice, if present. */ +@ _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; +@ + LDR r2, =_tx_timer_time_slice @ Pickup address of time-slice + @ variable + LDR sp, [r0, #8] @ Switch stack pointers + STR r3, [r2] @ Setup time-slice +@ +@ /* Switch to the thread's stack. */ +@ sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; +@ +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the thread entry function to indicate the thread is executing. */ +@ + MOV r5, r0 @ Save r0 + BL _tx_execution_thread_enter @ Call the thread execution enter function + MOV r0, r5 @ Restore r0 +#endif +@ +@ /* Determine if an interrupt frame or a synchronous task suspension frame +@ is present. */ +@ + LDMIA sp!, {r4, r5} @ Pickup the stack type and saved CPSR + CMP r4, #0 @ Check for synchronous context switch + BEQ _tx_solicited_return + MSR SPSR_cxsf, r5 @ Setup SPSR for return +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r1, [r0, #144] @ Pickup the VFP enabled flag + CMP r1, #0 @ Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore @ No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} @ Recover D0-D15 + VLDMIA sp!, {D16-D31} @ Recover D16-D31 + LDR r4, [sp], #4 @ Pickup FPSCR + VMSR FPSCR, r4 @ Restore FPSCR +_tx_skip_interrupt_vfp_restore: +#endif + LDMIA sp!, {r0-r12, lr, pc}^ @ Return to point of thread interrupt + +_tx_solicited_return: + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r1, [r0, #144] @ Pickup the VFP enabled flag + CMP r1, #0 @ Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore @ No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} @ Recover D8-D15 + VLDMIA sp!, {D16-D31} @ Recover D16-D31 + LDR r4, [sp], #4 @ Pickup FPSCR + VMSR FPSCR, r4 @ Restore FPSCR +_tx_skip_solicited_vfp_restore: +#endif + MSR CPSR_cxsf, r5 @ Recover CPSR + LDMIA sp!, {r4-r11, lr} @ Return to thread synchronously +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@ +@} +@ + +#ifdef TX_ENABLE_VFP_SUPPORT + + .global tx_thread_vfp_enable + .type tx_thread_vfp_enable,function +tx_thread_vfp_enable: + MRS r2, CPSR @ Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Enable IRQ and FIQ interrupts +#else + CPSID i @ Enable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address + LDR r1, [r0] @ Pickup current thread pointer + CMP r1, #0 @ Check for NULL thread pointer + BEQ __tx_no_thread_to_enable @ If NULL, skip VFP enable + MOV r0, #1 @ Build enable value + STR r0, [r1, #144] @ Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable: + MSR CPSR_cxsf, r2 @ Recover CPSR + BX LR @ Return to caller + + .global tx_thread_vfp_disable + .type tx_thread_vfp_disable,function +tx_thread_vfp_disable: + MRS r2, CPSR @ Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Enable IRQ and FIQ interrupts +#else + CPSID i @ Enable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address + LDR r1, [r0] @ Pickup current thread pointer + CMP r1, #0 @ Check for NULL thread pointer + BEQ __tx_no_thread_to_disable @ If NULL, skip VFP disable + MOV r0, #0 @ Build disable value + STR r0, [r1, #144] @ Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable: + MSR CPSR_cxsf, r2 @ Recover CPSR + BX LR @ Return to caller + +#endif + diff --git a/ports/cortex_a7/ac6/src/tx_thread_stack_build.S b/ports/cortex_a7/ac6/src/tx_thread_stack_build.S new file mode 100644 index 00000000..1c5f597f --- /dev/null +++ b/ports/cortex_a7/ac6/src/tx_thread_stack_build.S @@ -0,0 +1,178 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ + .arm + +SVC_MODE = 0x13 @ SVC mode +#ifdef TX_ENABLE_FIQ_SUPPORT +CPSR_MASK = 0xDF @ Mask initial CPSR, IRQ & FIQ interrupts enabled +#else +CPSR_MASK = 0x9F @ Mask initial CPSR, IRQ interrupts enabled +#endif +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_stack_build for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .thumb + .global $_tx_thread_stack_build + .type $_tx_thread_stack_build,function +$_tx_thread_stack_build: + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_stack_build @ Call _tx_thread_stack_build function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_stack_build Cortex-A7/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function builds a stack frame on the supplied thread's stack. */ +@/* The stack frame results in a fake interrupt return to the supplied */ +@/* function pointer. */ +@/* */ +@/* INPUT */ +@/* */ +@/* thread_ptr Pointer to thread control blk */ +@/* function_ptr Pointer to return function */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_thread_create Create thread service */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +@{ + .global _tx_thread_stack_build + .type _tx_thread_stack_build,function +_tx_thread_stack_build: +@ +@ +@ /* Build a fake interrupt frame. The form of the fake interrupt stack +@ on the Cortex-A7 should look like the following after it is built: +@ +@ Stack Top: 1 Interrupt stack frame type +@ CPSR Initial value for CPSR +@ a1 (r0) Initial value for a1 +@ a2 (r1) Initial value for a2 +@ a3 (r2) Initial value for a3 +@ a4 (r3) Initial value for a4 +@ v1 (r4) Initial value for v1 +@ v2 (r5) Initial value for v2 +@ v3 (r6) Initial value for v3 +@ v4 (r7) Initial value for v4 +@ v5 (r8) Initial value for v5 +@ sb (r9) Initial value for sb +@ sl (r10) Initial value for sl +@ fp (r11) Initial value for fp +@ ip (r12) Initial value for ip +@ lr (r14) Initial value for lr +@ pc (r15) Initial value for pc +@ 0 For stack backtracing +@ +@ Stack Bottom: (higher memory address) */ +@ + LDR r2, [r0, #16] @ Pickup end of stack area + BIC r2, r2, #7 @ Ensure 8-byte alignment + SUB r2, r2, #76 @ Allocate space for the stack frame +@ +@ /* Actually build the stack frame. */ +@ + MOV r3, #1 @ Build interrupt stack type + STR r3, [r2, #0] @ Store stack type + MOV r3, #0 @ Build initial register value + STR r3, [r2, #8] @ Store initial r0 + STR r3, [r2, #12] @ Store initial r1 + STR r3, [r2, #16] @ Store initial r2 + STR r3, [r2, #20] @ Store initial r3 + STR r3, [r2, #24] @ Store initial r4 + STR r3, [r2, #28] @ Store initial r5 + STR r3, [r2, #32] @ Store initial r6 + STR r3, [r2, #36] @ Store initial r7 + STR r3, [r2, #40] @ Store initial r8 + STR r3, [r2, #44] @ Store initial r9 + LDR r3, [r0, #12] @ Pickup stack starting address + STR r3, [r2, #48] @ Store initial r10 (sl) + LDR r3,=_tx_thread_schedule @ Pickup address of _tx_thread_schedule for GDB backtrace + STR r3, [r2, #60] @ Store initial r14 (lr) + MOV r3, #0 @ Build initial register value + STR r3, [r2, #52] @ Store initial r11 + STR r3, [r2, #56] @ Store initial r12 + STR r1, [r2, #64] @ Store initial pc + STR r3, [r2, #68] @ 0 for back-trace + MRS r1, CPSR @ Pickup CPSR + BIC r1, r1, #CPSR_MASK @ Mask mode bits of CPSR + ORR r3, r1, #SVC_MODE @ Build CPSR, SVC mode, interrupts enabled + STR r3, [r2, #4] @ Store initial CPSR +@ +@ /* Setup stack pointer. */ +@ thread_ptr -> tx_thread_stack_ptr = r2; +@ + STR r2, [r0, #8] @ Save stack pointer in thread's + @ control block +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + + diff --git a/ports/cortex_a7/ac6/src/tx_thread_system_return.S b/ports/cortex_a7/ac6/src/tx_thread_system_return.S new file mode 100644 index 00000000..4aca258c --- /dev/null +++ b/ports/cortex_a7/ac6/src/tx_thread_system_return.S @@ -0,0 +1,179 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ + .arm +@ +@ + .global _tx_thread_current_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule +@ +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_system_return for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_system_return + .type $_tx_thread_system_return,function +$_tx_thread_system_return: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_system_return @ Call _tx_thread_system_return function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_system_return Cortex-A7/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is target processor specific. It is used to transfer */ +@/* control from a thread back to the ThreadX system. Only a */ +@/* minimal context is saved since the compiler assumes temp registers */ +@/* are going to get slicked by a function call anyway. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling loop */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX components */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_system_return(VOID) +@{ + .global _tx_thread_system_return + .type _tx_thread_system_return,function +_tx_thread_system_return: +@ +@ /* Save minimal context on the stack. */ +@ + STMDB sp!, {r4-r11, lr} @ Save minimal context + + LDR r4, =_tx_thread_current_ptr @ Pickup address of current ptr + LDR r5, [r4] @ Pickup current thread pointer + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r1, [r5, #144] @ Pickup the VFP enabled flag + CMP r1, #0 @ Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save @ No, skip VFP solicited save + VMRS r1, FPSCR @ Pickup the FPSCR + STR r1, [sp, #-4]! @ Save FPSCR + VSTMDB sp!, {D16-D31} @ Save D16-D31 + VSTMDB sp!, {D8-D15} @ Save D8-D15 +_tx_skip_solicited_vfp_save: +#endif + + MOV r0, #0 @ Build a solicited stack type + MRS r1, CPSR @ Pickup the CPSR + STMDB sp!, {r0-r1} @ Save type and CPSR +@ +@ /* Lockout interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the thread exit function to indicate the thread is no longer executing. */ +@ + BL _tx_execution_thread_exit @ Call the thread exit function +#endif + MOV r3, r4 @ Pickup address of current ptr + MOV r0, r5 @ Pickup current thread pointer + LDR r2, =_tx_timer_time_slice @ Pickup address of time slice + LDR r1, [r2] @ Pickup current time slice +@ +@ /* Save current stack and switch to system stack. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ sp = _tx_thread_system_stack_ptr; +@ + STR sp, [r0, #8] @ Save thread stack pointer +@ +@ /* Determine if the time-slice is active. */ +@ if (_tx_timer_time_slice) +@ { +@ + MOV r4, #0 @ Build clear value + CMP r1, #0 @ Is a time-slice active? + BEQ __tx_thread_dont_save_ts @ No, don't save the time-slice +@ +@ /* Save time-slice for the thread and clear the current time-slice. */ +@ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +@ _tx_timer_time_slice = 0; +@ + STR r4, [r2] @ Clear time-slice + STR r1, [r0, #24] @ Save current time-slice +@ +@ } +__tx_thread_dont_save_ts: +@ +@ /* Clear the current thread pointer. */ +@ _tx_thread_current_ptr = TX_NULL; +@ + STR r4, [r3] @ Clear current thread pointer + B _tx_thread_schedule @ Jump to scheduler! +@ +@} + diff --git a/ports/cortex_a7/ac6/src/tx_thread_vectored_context_save.S b/ports/cortex_a7/ac6/src/tx_thread_vectored_context_save.S new file mode 100644 index 00000000..140807c1 --- /dev/null +++ b/ports/cortex_a7/ac6/src/tx_thread_vectored_context_save.S @@ -0,0 +1,189 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr +@ +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_vectored_context_save +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_vectored_context_save Cortex-A7/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_vectored_context_save(VOID) +@{ + .global _tx_thread_vectored_context_save + .type _tx_thread_vectored_context_save,function +_tx_thread_vectored_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state++) +@ { +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#endif + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3, #0] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3, #0] @ Store it back in the variable +@ +@ /* Note: Minimal context of interrupted thread is already saved. */ +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + MOV pc, lr @ Return to caller +@ +__tx_thread_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3, #0] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1, #0] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + @ scheduling loop - nothing needs saving! +@ +@ /* Note: Minimal context of interrupted thread is already saved. */ +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr; +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + MOV pc, lr @ Return to caller +@ +@ } +@ else +@ { +@ +__tx_thread_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ processing. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + ADD sp, sp, #32 @ Recover saved registers + MOV pc, lr @ Return to caller +@ +@ } +@} + diff --git a/ports/cortex_a7/ac6/src/tx_timer_interrupt.S b/ports/cortex_a7/ac6/src/tx_timer_interrupt.S new file mode 100644 index 00000000..b057387c --- /dev/null +++ b/ports/cortex_a7/ac6/src/tx_timer_interrupt.S @@ -0,0 +1,279 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Timer */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_timer.h" +@#include "tx_thread.h" +@ +@ + .arm + +@ +@/* Define Assembly language external references... */ +@ + .global _tx_timer_time_slice + .global _tx_timer_system_clock + .global _tx_timer_current_ptr + .global _tx_timer_list_start + .global _tx_timer_list_end + .global _tx_timer_expired_time_slice + .global _tx_timer_expired + .global _tx_thread_time_slice +@ +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_timer_interrupt for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .thumb + .global $_tx_timer_interrupt + .type $_tx_timer_interrupt,function +$_tx_timer_interrupt: + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_timer_interrupt @ Call _tx_timer_interrupt function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_timer_interrupt Cortex-A7/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function processes the hardware timer interrupt. This */ +@/* processing includes incrementing the system clock and checking for */ +@/* time slice and/or timer expiration. If either is found, the */ +@/* interrupt context save/restore functions are called along with the */ +@/* expiration functions. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_time_slice Time slice interrupted thread */ +@/* _tx_timer_expiration_process Timer expiration processing */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* interrupt vector */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_timer_interrupt(VOID) +@{ + .global _tx_timer_interrupt + .type _tx_timer_interrupt,function +_tx_timer_interrupt: +@ +@ /* Upon entry to this routine, it is assumed that context save has already +@ been called, and therefore the compiler scratch registers are available +@ for use. */ +@ +@ /* Increment the system clock. */ +@ _tx_timer_system_clock++; +@ + LDR r1, =_tx_timer_system_clock @ Pickup address of system clock + LDR r0, [r1] @ Pickup system clock + ADD r0, r0, #1 @ Increment system clock + STR r0, [r1] @ Store new system clock +@ +@ /* Test for time-slice expiration. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice + LDR r2, [r3] @ Pickup time-slice + CMP r2, #0 @ Is it non-active? + BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing +@ +@ /* Decrement the time_slice. */ +@ _tx_timer_time_slice--; +@ + SUB r2, r2, #1 @ Decrement the time-slice + STR r2, [r3] @ Store new time-slice value +@ +@ /* Check for expiration. */ +@ if (__tx_timer_time_slice == 0) +@ + CMP r2, #0 @ Has it expired? + BNE __tx_timer_no_time_slice @ No, skip expiration processing +@ +@ /* Set the time-slice expired flag. */ +@ _tx_timer_expired_time_slice = TX_TRUE; +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of expired flag + MOV r0, #1 @ Build expired value + STR r0, [r3] @ Set time-slice expiration flag +@ +@ } +@ +__tx_timer_no_time_slice: +@ +@ /* Test for timer expiration. */ +@ if (*_tx_timer_current_ptr) +@ { +@ + LDR r1, =_tx_timer_current_ptr @ Pickup current timer pointer address + LDR r0, [r1] @ Pickup current timer + LDR r2, [r0] @ Pickup timer list entry + CMP r2, #0 @ Is there anything in the list? + BEQ __tx_timer_no_timer @ No, just increment the timer +@ +@ /* Set expiration flag. */ +@ _tx_timer_expired = TX_TRUE; +@ + LDR r3, =_tx_timer_expired @ Pickup expiration flag address + MOV r2, #1 @ Build expired value + STR r2, [r3] @ Set expired flag + B __tx_timer_done @ Finished timer processing +@ +@ } +@ else +@ { +__tx_timer_no_timer: +@ +@ /* No timer expired, increment the timer pointer. */ +@ _tx_timer_current_ptr++; +@ + ADD r0, r0, #4 @ Move to next timer +@ +@ /* Check for wraparound. */ +@ if (_tx_timer_current_ptr == _tx_timer_list_end) +@ + LDR r3, =_tx_timer_list_end @ Pickup address of timer list end + LDR r2, [r3] @ Pickup list end + CMP r0, r2 @ Are we at list end? + BNE __tx_timer_skip_wrap @ No, skip wraparound logic +@ +@ /* Wrap to beginning of list. */ +@ _tx_timer_current_ptr = _tx_timer_list_start; +@ + LDR r3, =_tx_timer_list_start @ Pickup address of timer list start + LDR r0, [r3] @ Set current pointer to list start +@ +__tx_timer_skip_wrap: +@ + STR r0, [r1] @ Store new current timer pointer +@ } +@ +__tx_timer_done: +@ +@ +@ /* See if anything has expired. */ +@ if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +@ { +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of expired flag + LDR r2, [r3] @ Pickup time-slice expired flag + CMP r2, #0 @ Did a time-slice expire? + BNE __tx_something_expired @ If non-zero, time-slice expired + LDR r1, =_tx_timer_expired @ Pickup address of other expired flag + LDR r0, [r1] @ Pickup timer expired flag + CMP r0, #0 @ Did a timer expire? + BEQ __tx_timer_nothing_expired @ No, nothing expired +@ +__tx_something_expired: +@ +@ + STMDB sp!, {r0, lr} @ Save the lr register on the stack + @ and save r0 just to keep 8-byte alignment +@ +@ /* Did a timer expire? */ +@ if (_tx_timer_expired) +@ { +@ + LDR r1, =_tx_timer_expired @ Pickup address of expired flag + LDR r0, [r1] @ Pickup timer expired flag + CMP r0, #0 @ Check for timer expiration + BEQ __tx_timer_dont_activate @ If not set, skip timer activation +@ +@ /* Process timer expiration. */ +@ _tx_timer_expiration_process(); +@ + BL _tx_timer_expiration_process @ Call the timer expiration handling routine +@ +@ } +__tx_timer_dont_activate: +@ +@ /* Did time slice expire? */ +@ if (_tx_timer_expired_time_slice) +@ { +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of time-slice expired + LDR r2, [r3] @ Pickup the actual flag + CMP r2, #0 @ See if the flag is set + BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing +@ +@ /* Time slice interrupted thread. */ +@ _tx_thread_time_slice(); +@ + BL _tx_thread_time_slice @ Call time-slice processing +@ +@ } +@ +__tx_timer_not_ts_expiration: +@ + LDMIA sp!, {r0, lr} @ Recover lr register (r0 is just there for + @ the 8-byte stack alignment +@ +@ } +@ +__tx_timer_nothing_expired: +@ +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@ +@} + diff --git a/ports/cortex_a8/ac6/example_build/sample_threadx/.cproject b/ports/cortex_a8/ac6/example_build/sample_threadx/.cproject new file mode 100644 index 00000000..a43a7156 --- /dev/null +++ b/ports/cortex_a8/ac6/example_build/sample_threadx/.cproject @@ -0,0 +1,240 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_a8/ac6/example_build/sample_threadx/.project b/ports/cortex_a8/ac6/example_build/sample_threadx/.project new file mode 100644 index 00000000..a1b15572 --- /dev/null +++ b/ports/cortex_a8/ac6/example_build/sample_threadx/.project @@ -0,0 +1,26 @@ + + + sample_threadx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/ports/cortex_a8/ac6/example_build/sample_threadx/.settings/language.settings.xml b/ports/cortex_a8/ac6/example_build/sample_threadx/.settings/language.settings.xml new file mode 100644 index 00000000..2ba37bac --- /dev/null +++ b/ports/cortex_a8/ac6/example_build/sample_threadx/.settings/language.settings.xml @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_a8/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a8/ac6/example_build/sample_threadx/sample_threadx.c new file mode 100644 index 00000000..418ec634 --- /dev/null +++ b/ports/cortex_a8/ac6/example_build/sample_threadx/sample_threadx.c @@ -0,0 +1,369 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_a8/ac6/example_build/sample_threadx/sample_threadx.scat b/ports/cortex_a8/ac6/example_build/sample_threadx/sample_threadx.scat new file mode 100644 index 00000000..013e9f8f --- /dev/null +++ b/ports/cortex_a8/ac6/example_build/sample_threadx/sample_threadx.scat @@ -0,0 +1,41 @@ +;******************************************************* +; Copyright (c) 2010-2011 Arm Limited (or its affiliates). All rights reserved. +; Use, modification and redistribution of this file is subject to your possession of a +; valid End User License Agreement for the Arm Product of which these examples are part of +; and your compliance with all applicable terms and conditions of such licence agreement. +;******************************************************* + +; Scatter-file for bare-metal example on BeagleBoard + +; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map. + +; BeagleBoard has 256MB DDR SDRAM in its POP device at 0x80000000 to 0x8FFFFFFF, which this scatter-file uses. +; Alternatively, OMAP3530 has 64KB internal SRAM, from 0x40200000 to 0x4020FFFF, which could be used for some regions instead. + +SDRAM 0x80000000 0x10000000 +{ + APP_CODE +0 + { + * (VECTORS, +FIRST) ; Vector table and other (assembler) startup code + * (+RO-CODE) ; Application RO code (.text) + * (+RO-DATA) ; Application RO data (.constdata) + * (InRoot$$Sections) ; All library code that must be in a root region + } + + APP_DATA +0 + { + * (+RW, +ZI) ; Application RW (.data) and ZI (.bss) data + } + + ARM_LIB_HEAP 0x80040000 EMPTY 0x00040000 ; Application heap + { } + + ARM_LIB_STACK 0x80090000 EMPTY 0x00010000 ; Application (SVC mode) stack + { } + + ;IRQ_STACK 0x800A0000 EMPTY 0x00010000 ; IRQ mode stack + ;{ } + + TTB 0x80100000 EMPTY 0x4000 ; Level-1 Translation Table for MMU + { } +} diff --git a/ports/cortex_a8/ac6/example_build/sample_threadx/startup.S b/ports/cortex_a8/ac6/example_build/sample_threadx/startup.S new file mode 100644 index 00000000..376629d5 --- /dev/null +++ b/ports/cortex_a8/ac6/example_build/sample_threadx/startup.S @@ -0,0 +1,373 @@ +//---------------------------------------------------------------- +// Cortex-A8 Embedded example - Startup Code +// +// Copyright (c) 2005-2018 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +//---------------------------------------------------------------- + + +// Standard definitions of mode bits and interrupt (I & F) flags in PSRs + +#define Mode_USR 0x10 +#define Mode_FIQ 0x11 +#define Mode_IRQ 0x12 +#define Mode_SVC 0x13 +#define Mode_ABT 0x17 +#define Mode_UND 0x1B +#define Mode_SYS 0x1F + +#define I_Bit 0x80 // When I bit is set, IRQ is disabled +#define F_Bit 0x40 // When F bit is set, FIQ is disabled + + + .section VECTORS, "ax" + .align 3 + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + +//---------------------------------------------------------------- +// Entry point for the Reset handler +//---------------------------------------------------------------- + + .global Vectors + +//---------------------------------------------------------------- +// Exception Vector Table +//---------------------------------------------------------------- +// Note: LDR PC instructions are used here, though branch (B) instructions +// could also be used, unless the exception handlers are >32MB away. + +Vectors: + LDR PC, Reset_Addr + LDR PC, Undefined_Addr + LDR PC, SVC_Addr + LDR PC, Prefetch_Addr + LDR PC, Abort_Addr + B . // Reserved vector + LDR PC, IRQ_Addr + LDR PC, FIQ_Addr + + + .balign 4 +Reset_Addr: + .word Reset_Handler +Undefined_Addr: + //.word Undefined_Handler + .word __tx_undefined +SVC_Addr: + //.word SVC_Handler + .word __tx_swi_interrupt +Prefetch_Addr: + //.word Prefetch_Handler + .word __tx_prefetch_handler +Abort_Addr: + //.word Abort_Handler + .word __tx_abort_handler +IRQ_Addr: + //.word IRQ_Handler + .word __tx_irq_handler +FIQ_Addr: + //.word FIQ_Handler + .word __tx_fiq_handler + + +//---------------------------------------------------------------- +// Exception Handlers +//---------------------------------------------------------------- + +Undefined_Handler: + B Undefined_Handler +SVC_Handler: + B SVC_Handler +Prefetch_Handler: + B Prefetch_Handler +Abort_Handler: + B Abort_Handler +IRQ_Handler: + B IRQ_Handler +FIQ_Handler: + B FIQ_Handler + + +//---------------------------------------------------------------- +// Reset Handler +//---------------------------------------------------------------- +Reset_Handler: + +//---------------------------------------------------------------- +// Disable caches, MMU and branch prediction in case they were left enabled from an earlier run +// This does not need to be done from a cold reset +//---------------------------------------------------------------- + + MRC p15, 0, r0, c1, c0, 0 // Read System Control Register + BIC r0, r0, #(0x1 << 12) // Clear I bit 12 to disable I Cache + BIC r0, r0, #(0x1 << 2) // Clear C bit 2 to disable D Cache + BIC r0, r0, #0x1 // Clear M bit 0 to disable MMU + BIC r0, r0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction + MCR p15, 0, r0, c1, c0, 0 // Write System Control Register + ISB + +// The MMU is enabled later, before calling main(). Caches and branch prediction are enabled inside main(), +// after the MMU has been enabled and scatterloading has been performed. + +//---------------------------------------------------------------- +// Initialize Supervisor Mode Stack +// Note stack must be 8 byte aligned. +//---------------------------------------------------------------- + + LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit + +//---------------------------------------------------------------- +// Invalidate Data and Instruction TLBs and branch predictor +//---------------------------------------------------------------- + + MOV r0,#0 + MCR p15, 0, r0, c8, c7, 0 // I-TLB and D-TLB invalidation + MCR p15, 0, r0, c7, c5, 6 // BPIALL - Invalidate entire branch predictor array + + +//---------------------------------------------------------------- +// Set Vector Base Address Register (VBAR) to point to this application's vector table +//---------------------------------------------------------------- + + LDR r0, =Vectors + MCR p15, 0, r0, c12, c0, 0 + +//---------------------------------------------------------------- +// Cache Invalidation code for Cortex-A8 +//---------------------------------------------------------------- + + // Invalidate L1 Instruction Cache + + MRC p15, 1, r0, c0, c0, 1 // Read Cache Level ID Register (CLIDR) + TST r0, #0x3 // Harvard Cache? + MOV r0, #0 // SBZ + MCRNE p15, 0, r0, c7, c5, 0 // ICIALLU - Invalidate instruction cache and flush branch target cache + + // Invalidate Data/Unified Caches + + MRC p15, 1, r0, c0, c0, 1 // Read CLIDR + ANDS r3, r0, #0x07000000 // Extract coherency level + MOV r3, r3, LSR #23 // Total cache levels << 1 + BEQ Finished // If 0, no need to clean + + MOV r10, #0 // R10 holds current cache level << 1 +Loop1: ADD r2, r10, r10, LSR #1 // R2 holds cache "Set" position + MOV r1, r0, LSR r2 // Bottom 3 bits are the Cache-type for this level + AND r1, r1, #7 // Isolate those lower 3 bits + CMP r1, #2 + BLT Skip // No cache or only instruction cache at this level + + MCR p15, 2, r10, c0, c0, 0 // Write the Cache Size selection register + ISB // ISB to sync the change to the CacheSizeID reg + MRC p15, 1, r1, c0, c0, 0 // Reads current Cache Size ID register + AND r2, r1, #7 // Extract the line length field + ADD r2, r2, #4 // Add 4 for the line length offset (log2 16 bytes) + LDR r4, =0x3FF + ANDS r4, r4, r1, LSR #3 // R4 is the max number on the way size (right aligned) + CLZ r5, r4 // R5 is the bit position of the way size increment + LDR r7, =0x7FFF + ANDS r7, r7, r1, LSR #13 // R7 is the max number of the index size (right aligned) + +Loop2: MOV r9, r4 // R9 working copy of the max way size (right aligned) + +Loop3: ORR r11, r10, r9, LSL r5 // Factor in the Way number and cache number into R11 + ORR r11, r11, r7, LSL r2 // Factor in the Set number + MCR p15, 0, r11, c7, c6, 2 // Invalidate by Set/Way + SUBS r9, r9, #1 // Decrement the Way number + BGE Loop3 + SUBS r7, r7, #1 // Decrement the Set number + BGE Loop2 +Skip: ADD r10, r10, #2 // Increment the cache number + CMP r3, r10 + BGT Loop1 + +Finished: +//---------------------------------------------------------------- +// MMU Configuration +// Set translation table base +//---------------------------------------------------------------- + + // Two translation tables are supported, TTBR0 and TTBR1 + // Configure translation table base (TTB) control register cp15,c2 + // to a value of all zeros, indicates we are using TTB register 0. + + MOV r0,#0x0 + MCR p15, 0, r0, c2, c0, 2 + + + // write the address of our page table base to TTB register 0 + + LDR r0,=Image$$TTB$$ZI$$Base + MCR p15, 0, r0, c2, c0, 0 + //MSR TTBR0, r0 + +//---------------------------------------------------------------- +// PAGE TABLE generation + +// Generate the page tables +// Build a flat translation table for the whole address space. +// ie: Create 4096 1MB sections from 0x000xxxxx to 0xFFFxxxxx + + +// 31 20 19 18 17 16 15 14 12 11 10 9 8 5 4 3 2 1 0 +// |section base address| 0 0 |nG| S |AP2| TEX | AP | P | Domain | XN | C B | 1 0| +// +// Bits[31:20] - Top 12 bits of VA is pointer into table +// nG[17]=0 - Non global, enables matching against ASID in the TLB when set. +// S[16]=0 - Indicates normal memory is shared when set. +// AP2[15]=0 +// AP[11:10]=11 - Configure for full read/write access in all modes +// TEX[14:12]=000 +// CB[3:2]= 00 - Set attributes to Strongly-ordered memory. +// (except for the code segment descriptor, see below) +// IMPP[9]=0 - Ignored +// Domain[5:8]=1111 - Set all pages to use domain 15 +// XN[4]=1 - Execute never on Strongly-ordered memory +// Bits[1:0]=10 - Indicate entry is a 1MB section +//---------------------------------------------------------------- + + LDR r1,=0xfff // Loop counter + LDR r2,=3554 + + // r0 contains the address of the translation table base + // r1 is loop counter + // r2 is level1 descriptor (bits 19:0) + + // Use loop counter to create 4096 individual table entries. + // This writes from address 'Image$$TTB$$ZI$$Base' + + // Offset 0x3FFC down to offset 0x0 in word steps (4 bytes) + +init_ttb_1: + ORR r3, r2, r1, LSL#20 // R3 now contains full level1 descriptor to write + ORR r3, r3, #16 // Set XN bit + STR r3, [r0, r1, LSL#2] // Str table entry at TTB base + loopcount*4 + SUBS r1, r1, #1 // Decrement loop counter + BPL init_ttb_1 + + // In this example, the 1MB section based at '||Image$$APP_CODE$$Base||' is setup specially as cacheable (write back mode). + // TEX[14:12]=000 and CB[3:2]= 11, Outer and inner write back, no Write-allocate normal memory. + + LDR r1,=Image$$APP_CODE$$Base // Base physical address of code segment + LSR r1, #20 // Shift right to align to 1MB boundaries + ORR r3, r2, r1, LSL#20 // Setup the initial level1 descriptor again + ORR r3, r3, #12 // Set CB bits + STR r3, [r0, r1, LSL#2] // str table entry + +//---------------------------------------------------------------- +// Setup domain control register - Enable all domains to client mode +//---------------------------------------------------------------- + + MRC p15, 0, r0, c3, c0, 0 // Read Domain Access Control Register + LDR r0, =0x55555555 // Initialize every domain entry to b01 (client) + MCR p15, 0, r0, c3, c0, 0 // Write Domain Access Control Register + +//---------------------------------------------------------------- +// Setup L2 Cache - L2 Cache Auxiliary Control +//---------------------------------------------------------------- + +//// Seems to undef on Beagle ? +//// MOV r0, #0 +//// MCR p15, 1, r0, c9, c0, 2 // Write L2 Auxilary Control Register + + +#if defined(__ARM_NEON) || defined(__ARM_FP) +//---------------------------------------------------------------- +// Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11. +// Enables Full Access i.e. in both privileged and non privileged modes +//---------------------------------------------------------------- + + MRC p15, 0, r0, c1, c0, 2 // Read Coprocessor Access Control Register (CPACR) + ORR r0, r0, #(0xF << 20) // Enable access to CP 10 & 11 + MCR p15, 0, r0, c1, c0, 2 // Write Coprocessor Access Control Register (CPACR) + ISB + +//---------------------------------------------------------------- +// Switch on the VFP and NEON hardware +//---------------------------------------------------------------- + + MOV r0, #0x40000000 + VMSR FPEXC, r0 // Write FPEXC register, EN bit set +#endif + + +//---------------------------------------------------------------- +// Enable MMU and Branch to __main +// Leaving the caches disabled until after scatter loading. +//---------------------------------------------------------------- + + LDR r12,=__main // Save this in register for possible long jump + + + MRC p15, 0, r0, c1, c0, 0 // Read System Control Register + BIC r0, r0, #(0x1 << 12) // Clear I bit 12 to disable I Cache + BIC r0, r0, #(0x1 << 2) // Clear C bit 2 to disable D Cache + BIC r0, r0, #0x2 // Clear A bit 1 to disable strict alignment fault checking + ORR r0, r0, #0x1 // Set M bit 0 to enable MMU before scatter loading + MCR p15, 0, r0, c1, c0, 0 // Write System Control Register + ISB + + +// Now the MMU is enabled, virtual to physical address translations will occur. +// This will affect the next instruction fetches. +// +// The two instructions currently in the pipeline will have been fetched before the MMU was enabled. +// The branch to __main is safe because the Virtual Address (VA) is the same as the Physical Address (PA) +// (flat mapping) of this code that enables the MMU and performs the branch + + BX r12 // Branch to __main() C library entry point + + + +//---------------------------------------------------------------- +// Enable caches and branch prediction +// This code must be run from a privileged mode +//---------------------------------------------------------------- + + .section ENABLECACHES,"ax" + .align 3 + + .global enable_caches + .type enable_caches, "function" + .cfi_startproc +enable_caches: + +//---------------------------------------------------------------- +// Enable caches and branch prediction +//---------------------------------------------------------------- + + MRC p15, 0, r0, c1, c0, 0 // Read System Control Register + ORR r0, r0, #(0x1 << 12) // Set I bit 12 to enable I Cache + ORR r0, r0, #(0x1 << 2) // Set C bit 2 to enable D Cache + ORR r0, r0, #(0x1 << 11) // Set Z bit 11 to enable branch prediction + MCR p15, 0, r0, c1, c0, 0 // Write System Control Register + ISB + + +//---------------------------------------------------------------- +// Enable Cortex-A8 Level2 Unified Cache +//---------------------------------------------------------------- + + MRC p15, 0, r0, c1, c0, 1 // Read Auxiliary Control Register + ORR r0, #2 // L2EN bit, enable L2 cache + MCR p15, 0, r0, c1, c0, 1 // Write Auxiliary Control Register + ISB + + BX lr + + .cfi_endproc + + + .global disable_caches + .type disable_caches, "function" +disable_caches: + + MRC p15, 0, r0, c1, c0, 0 // Read System Control Register + BIC r0, r0, #(0x1 << 12) // Clear I bit 12 to disable I Cache + BIC r0, r0, #(0x1 << 2) // Clear C bit 2 to disable D Cache + MCR p15, 0, r0, c1, c0, 0 // Write System Control Register + ISB + + BX lr + diff --git a/ports/cortex_a8/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_a8/ac6/example_build/sample_threadx/tx_initialize_low_level.S new file mode 100644 index 00000000..9dfb7a25 --- /dev/null +++ b/ports/cortex_a8/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -0,0 +1,345 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Initialize */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_initialize.h" +@#include "tx_thread.h" +@#include "tx_timer.h" + + .arm + +SVC_MODE = 0xD3 @ Disable IRQ/FIQ SVC mode +IRQ_MODE = 0xD2 @ Disable IRQ/FIQ IRQ mode +FIQ_MODE = 0xD1 @ Disable IRQ/FIQ FIQ mode +SYS_MODE = 0xDF @ Disable IRQ/FIQ SYS mode +FIQ_STACK_SIZE = 512 @ FIQ stack size +IRQ_STACK_SIZE = 1024 @ IRQ stack size +SYS_STACK_SIZE = 1024 @ System stack size +@ +@ + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global _tx_thread_context_save + .global _tx_thread_context_restore + .global _tx_timer_interrupt + +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_initialize_low_level for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .thumb + .global $_tx_initialize_low_level + .type $_tx_initialize_low_level,function +$_tx_initialize_low_level: + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_initialize_low_level @ Call _tx_initialize_low_level function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_initialize_low_level Cortex-A8/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for any low-level processor */ +@/* initialization, including setting up interrupt vectors, setting */ +@/* up a periodic timer interrupt source, saving the system stack */ +@/* pointer for use in ISR processing later, and finding the first */ +@/* available RAM memory address for tx_application_define. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_initialize_low_level(VOID) +@{ + .global _tx_initialize_low_level + .type _tx_initialize_low_level,function +_tx_initialize_low_level: +@ +@ /* We must be in SVC mode at this point! */ +@ +@ /* Setup various stack pointers. */ +@ + LDR r1, =Image$$ARM_LIB_STACK$$ZI$$Limit @ Get pointer to stack area + +#ifdef TX_ENABLE_IRQ_NESTING +@ +@ /* Setup the system mode stack for nested interrupt support */ +@ + LDR r2, =SYS_STACK_SIZE @ Pickup stack size + MOV r3, #SYS_MODE @ Build SYS mode CPSR + MSR CPSR_c, r3 @ Enter SYS mode + SUB r1, r1, #1 @ Backup 1 byte + BIC r1, r1, #7 @ Ensure 8-byte alignment + MOV sp, r1 @ Setup SYS stack pointer + SUB r1, r1, r2 @ Calculate start of next stack +#endif + + LDR r2, =FIQ_STACK_SIZE @ Pickup stack size + MOV r0, #FIQ_MODE @ Build FIQ mode CPSR + MSR CPSR, r0 @ Enter FIQ mode + SUB r1, r1, #1 @ Backup 1 byte + BIC r1, r1, #7 @ Ensure 8-byte alignment + MOV sp, r1 @ Setup FIQ stack pointer + SUB r1, r1, r2 @ Calculate start of next stack + LDR r2, =IRQ_STACK_SIZE @ Pickup IRQ stack size + MOV r0, #IRQ_MODE @ Build IRQ mode CPSR + MSR CPSR, r0 @ Enter IRQ mode + SUB r1, r1, #1 @ Backup 1 byte + BIC r1, r1, #7 @ Ensure 8-byte alignment + MOV sp, r1 @ Setup IRQ stack pointer + SUB r3, r1, r2 @ Calculate end of IRQ stack + MOV r0, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR, r0 @ Enter SVC mode + LDR r2, =Image$$ARM_LIB_STACK$$Base @ Pickup stack bottom + CMP r3, r2 @ Compare the current stack end with the bottom +_stack_error_loop: + BLT _stack_error_loop @ If the IRQ stack exceeds the stack bottom, just sit here! +@ +@ /* Save the system stack pointer. */ +@ _tx_thread_system_stack_ptr = (VOID_PTR) (sp); +@ + LDR r2, =_tx_thread_system_stack_ptr @ Pickup stack pointer + STR r1, [r2] @ Save the system stack +@ +@ /* Save the first available memory address. */ +@ _tx_initialize_unused_memory = (VOID_PTR) _end; +@ + LDR r1, =Image$$APP_DATA$$ZI$$Limit @ Get end of non-initialized RAM area + LDR r2, =_tx_initialize_unused_memory @ Pickup unused memory ptr address + ADD r1, r1, #8 @ Increment to next free word + STR r1, [r2] @ Save first free memory address +@ +@ /* Setup Timer for periodic interrupts. */ +@ +@ /* Done, return to caller. */ +@ +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} +@ +@ +@/* Define shells for each of the interrupt vectors. */ +@ + .global __tx_undefined +__tx_undefined: + B __tx_undefined @ Undefined handler +@ + .global __tx_swi_interrupt +__tx_swi_interrupt: + B __tx_swi_interrupt @ Software interrupt handler +@ + .global __tx_prefetch_handler +__tx_prefetch_handler: + B __tx_prefetch_handler @ Prefetch exception handler +@ + .global __tx_abort_handler +__tx_abort_handler: + B __tx_abort_handler @ Abort exception handler +@ + .global __tx_reserved_handler +__tx_reserved_handler: + B __tx_reserved_handler @ Reserved exception handler +@ + .global __tx_irq_processing_return + .type __tx_irq_processing_return,function + .global __tx_irq_handler +__tx_irq_handler: +@ +@ /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return: +@ +@ /* At this point execution is still in the IRQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. In +@ addition, IRQ interrupts may be re-enabled - with certain restrictions - +@ if nested IRQ interrupts are desired. Interrupts may be re-enabled over +@ small code sequences where lr is saved before enabling interrupts and +@ restored after interrupts are again disabled. */ +@ +@ /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +@ from IRQ mode with interrupts disabled. This routine switches to the +@ system mode and returns with IRQ interrupts enabled. +@ +@ NOTE: It is very important to ensure all IRQ interrupts are cleared +@ prior to enabling nested IRQ interrupts. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_start +#endif +@ +@ /* For debug purpose, execute the timer interrupt processing here. In +@ a real system, some kind of status indication would have to be checked +@ before the timer interrupt handler could be called. */ +@ + BL _tx_timer_interrupt @ Timer interrupt handler +@ +@ +@ /* If interrupt nesting was started earlier, the end of interrupt nesting +@ service must be called before returning to _tx_thread_context_restore. +@ This routine returns in processing in IRQ mode with interrupts disabled. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_end +#endif +@ +@ /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore +@ +@ +@ /* This is an example of a vectored IRQ handler. */ +@ +@ .global __tx_example_vectored_irq_handler +@__tx_example_vectored_irq_handler: +@ +@ +@ /* Save initial context and call context save to prepare for +@ vectored ISR execution. */ +@ +@ STMDB sp!, {r0-r3} @ Save some scratch registers +@ MRS r0, SPSR @ Pickup saved SPSR +@ SUB lr, lr, #4 @ Adjust point of interrupt +@ STMDB sp!, {r0, r10, r12, lr} @ Store other scratch registers +@ BL _tx_thread_vectored_context_save @ Vectored context save +@ +@ /* At this point execution is still in the IRQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. In +@ addition, IRQ interrupts may be re-enabled - with certain restrictions - +@ if nested IRQ interrupts are desired. Interrupts may be re-enabled over +@ small code sequences where lr is saved before enabling interrupts and +@ restored after interrupts are again disabled. */ +@ +@ +@ /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +@ from IRQ mode with interrupts disabled. This routine switches to the +@ system mode and returns with IRQ interrupts enabled. +@ +@ NOTE: It is very important to ensure all IRQ interrupts are cleared +@ prior to enabling nested IRQ interrupts. */ +@#ifdef TX_ENABLE_IRQ_NESTING +@ BL _tx_thread_irq_nesting_start +@#endif +@ +@ /* Application IRQ handlers can be called here! */ +@ +@ /* If interrupt nesting was started earlier, the end of interrupt nesting +@ service must be called before returning to _tx_thread_context_restore. +@ This routine returns in processing in IRQ mode with interrupts disabled. */ +@#ifdef TX_ENABLE_IRQ_NESTING +@ BL _tx_thread_irq_nesting_end +@#endif +@ +@ /* Jump to context restore to restore system context. */ +@ B _tx_thread_context_restore +@ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + .global __tx_fiq_handler + .global __tx_fiq_processing_return +__tx_fiq_handler: +@ +@ /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +@ +@ /* At this point execution is still in the FIQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. */ +@ +@ /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +@ from FIQ mode with interrupts disabled. This routine switches to the +@ system mode and returns with FIQ interrupts enabled. +@ +@ NOTE: It is very important to ensure all FIQ interrupts are cleared +@ prior to enabling nested FIQ interrupts. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_start +#endif +@ +@ /* Application FIQ handlers can be called here! */ +@ +@ /* If interrupt nesting was started earlier, the end of interrupt nesting +@ service must be called before returning to _tx_thread_fiq_context_restore. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_end +#endif +@ +@ /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore +@ +@ +#else + .global __tx_fiq_handler +__tx_fiq_handler: + B __tx_fiq_handler @ FIQ interrupt handler +#endif +@ +@ +BUILD_OPTIONS: + .word _tx_build_options @ Reference to bring in +VERSION_ID: + .word _tx_version_id @ Reference to bring in + + + diff --git a/ports/cortex_a8/ac6/example_build/tx/.cproject b/ports/cortex_a8/ac6/example_build/tx/.cproject new file mode 100644 index 00000000..5dff4107 --- /dev/null +++ b/ports/cortex_a8/ac6/example_build/tx/.cproject @@ -0,0 +1,212 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_a8/ac6/example_build/tx/.project b/ports/cortex_a8/ac6/example_build/tx/.project new file mode 100644 index 00000000..863ca5cb --- /dev/null +++ b/ports/cortex_a8/ac6/example_build/tx/.project @@ -0,0 +1,48 @@ + + + tx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + inc_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/inc + + + inc_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/inc + + + src_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/src + + + src_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/src + + + diff --git a/ports/cortex_a8/ac6/example_build/tx/.settings/language.settings.xml b/ports/cortex_a8/ac6/example_build/tx/.settings/language.settings.xml new file mode 100644 index 00000000..e0d7b5f6 --- /dev/null +++ b/ports/cortex_a8/ac6/example_build/tx/.settings/language.settings.xml @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_a8/ac6/inc/tx_port.h b/ports/cortex_a8/ac6/inc/tx_port.h new file mode 100644 index 00000000..cdd68ecd --- /dev/null +++ b/ports/cortex_a8/ac6/inc/tx_port.h @@ -0,0 +1,323 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A8/AC6 */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#if __TARGET_ARCH_ARM > 4 + +#ifndef __thumb__ + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + asm volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); \ + b = 31 - b; +#endif +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifdef __thumb__ + +unsigned int _tx_thread_interrupt_disable(void); +unsigned int _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save, tx_temp; + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); +#else +#define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID i ": "=r" (interrupt_save) ); +#endif + +#define TX_RESTORE asm volatile (" MSR CPSR_c,%0 "::"r" (interrupt_save) ); + +#endif + + +/* Define VFP extension for the Cortex-A8. Each is assumed to be called in the context of the executing + thread. */ + +void tx_thread_vfp_enable(void); +void tx_thread_vfp_disable(void); + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A8/AC6 Version 6.0.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + diff --git a/ports/cortex_a8/ac6/readme_threadx.txt b/ports/cortex_a8/ac6/readme_threadx.txt new file mode 100644 index 00000000..a3f367ab --- /dev/null +++ b/ports/cortex_a8/ac6/readme_threadx.txt @@ -0,0 +1,339 @@ + Microsoft's Azure RTOS ThreadX for Cortex-A8 + + Using ARM Compiler 6 & DS + +1. Import the ThreadX Projects + +In order to build the ThreadX library and the ThreadX demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +into your DS workspace. + + +2. Building the ThreadX run-time Library + +Building the ThreadX library is easy; simply right-click the Eclipse project +"tx" and then select the "Build Project" button. You should now observe the compilation +and assembly of the ThreadX library. This project build produces the ThreadX +library file tx.a. + + +3. Demonstration System + +Since there is no ARM Cortex-A8 FVP, there are no instructions here for running +the demonstration; users are expected to run the demonstration on their platform +of choice. + +Building the demonstration is easy; simply right-click the Eclipse project +"sample_threadx" and then select the "Build Project" button. You should now observe +the compilation and assembly of the ThreadX demonstration. This project build produces +the ThreadX library file sample_threadx.axf. + + +4. System Initialization + +The entry point in ThreadX for the Cortex-A8 using ARM tools is at label +"Vectors". This is defined within startup.S in the sample_threadx project. In addition, +this is where all static and global pre-set C variable initialization processing +takes place. + +This is also where initialization of a periodic timer interrupt source should take +place. + +In addition, _tx_initialize_low_level defines the first available address +for use by the application, which is supplied as the sole input parameter +to your application definition function, tx_application_define. + + +5. Register Usage and Stack Frames + +The AC6 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread +is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 CPSR CPSR + 0x08 r0 (a1) a8 (v1) + 0x0C r1 (a2) r5 (v2) + 0x10 r2 (a3) r6 (v3) + 0x14 r3 (a4) r7 (v4) + 0x18 a8 (v1) r8 (v5) + 0x1C r5 (v2) r9 (v6) + 0x20 r6 (v3) r10 (v7) + 0x24 r7 (v4) r11 (fp) + 0x28 r8 (v5) r14 (lr) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) + 0x3C r14 (lr) + 0x40 PC + + +6. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-A8 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +7.1 Vector Area + +The Cortex-A8 vectors start at address zero. The demonstration system startup +reset.S file contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. + + +7.2 IRQ ISRs + +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports +nested IRQ interrupts. The following sub-sections define the IRQ capabilities. + + +7.2.1 Standard IRQ ISRs + +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +is the default IRQ handler defined in tx_initialize_low_level.S: + + .global __tx_irq_handler + .global __tx_irq_processing_return +__tx_irq_handler: +@ +@ /* Jump to context save to save system context. */ + B _tx_thread_context_save @ Jump to the context save +__tx_irq_processing_return: +@ +@ /* At this point execution is still in the IRQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. Note +@ that IRQ interrupts are still disabled upon return from the context +@ save function. */ +@ +@ /* Application ISR call(s) go here! */ +@ +@ /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.2 Vectored IRQ ISRs + +The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified +by the particular implementation. The following is an example IRQ handler defined in +tx_initialize_low_level.S: + + .global __tx_irq_example_handler +__tx_irq_example_handler: +@ +@ /* Call context save to save system context. */ + + STMDB sp!, {r0-r3} @ Save some scratch registers + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} @ Store other scratch registers + BL _tx_thread_vectored_context_save @ Call the vectored IRQ context save +@ +@ /* At this point execution is still in the IRQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. Note +@ that IRQ interrupts are still disabled upon return from the context +@ save function. */ +@ +@ /* Application ISR call goes here! */ +@ +@ /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.3 Nested IRQ Support + +By default, nested IRQ interrupt support is not enabled. To enable nested +IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING +defined. With this defined, two new IRQ interrupt management services are +available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. +These function should be called between the IRQ context save and restore +calls. + +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +by switching from IRQ mode to SYS mode and enabling IRQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.S. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in +preparation for the IRQ context restore service. + +The following is an example of enabling IRQ nested interrupts in a standard +IRQ handler: + + .global __tx_irq_handler + .global __tx_irq_processing_return +__tx_irq_handler: +@ +@ /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return: +@ +@ /* Enable nested IRQ interrupts. NOTE: Since this service returns +@ with IRQ interrupts enabled, all IRQ interrupt sources must be +@ cleared prior to calling this service. */ + BL _tx_thread_irq_nesting_start +@ +@ /* Application ISR call(s) go here! */ +@ +@ /* Disable nested IRQ interrupts. The mode is switched back to +@ IRQ mode and IRQ interrupts are disable upon return. */ + BL _tx_thread_irq_nesting_end +@ +@ /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.3 FIQ Interrupts + +By default, FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made +from default FIQ ISRs, which is located in tx_initialize_low_level.S. + + +7.3.1 Managed FIQ Interrupts + +Full ThreadX management of FIQ interrupts is provided if the ThreadX sources +are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built +this way, the FIQ interrupt handlers are very similar to the IRQ interrupt +handlers defined previously. The following is default FIQ handler +defined in tx_initialize_low_level.S: + + + .global __tx_fiq_handler + .global __tx_fiq_processing_return +__tx_fiq_handler: +@ +@ /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +@ +@ /* At this point execution is still in the FIQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. */ +@ +@ /* Application FIQ handlers can be called here! */ +@ +@ /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +7.3.1.1 Nested FIQ Support + +By default, nested FIQ interrupt support is not enabled. To enable nested +FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING +defined. With this defined, two new FIQ interrupt management services are +available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. +These function should be called between the FIQ context save and restore +calls. + +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +by switching from FIQ mode to SYS mode and enabling FIQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.S. When nested FIQ interrupts are no longer required, +calling the _tx_thread_fiq_nesting_end service disables nesting by disabling +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +context restore service. + +The following is an example of enabling FIQ nested interrupts in the +typical FIQ handler: + + + .global __tx_fiq_handler + .global __tx_fiq_processing_return +__tx_fiq_handler: +@ +@ /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +@ +@ /* At this point execution is still in the FIQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. */ +@ +@ /* Enable nested FIQ interrupts. NOTE: Since this service returns +@ with FIQ interrupts enabled, all FIQ interrupt sources must be +@ cleared prior to calling this service. */ + BL _tx_thread_fiq_nesting_start +@ +@ /* Application FIQ handlers can be called here! */ +@ +@ /* Disable nested FIQ interrupts. The mode is switched back to +@ FIQ mode and FIQ interrupts are disable upon return. */ + BL _tx_thread_fiq_nesting_end +@ +@ /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +8. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional but the remainder of +ThreadX will still run. + +To add the timer interrupt processing, simply make a call to +_tx_timer_interrupt in the IRQ processing. An example of this can be +found in the file tx_initialize_low_level.S for the demonstration system. + + +9. VFP Support + +By default, VFP support is disabled for each thread. If saving the context of the VFP registers +is needed, the following API call must be made from the context of the application thread - before +the VFP usage: + +void tx_thread_vfp_enable(void); + +After this API is called in the application, VFP registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the VFP registers +to be saved/restored. + +To disable VFP register context saving, simply call the following API: + +void tx_thread_vfp_disable(void); + + +10. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A8 using AC6 tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_a8/ac6/src/tx_thread_context_restore.S b/ports/cortex_a8/ac6/src/tx_thread_context_restore.S new file mode 100644 index 00000000..6c32d0b8 --- /dev/null +++ b/ports/cortex_a8/ac6/src/tx_thread_context_restore.S @@ -0,0 +1,256 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ + .arm + +#ifdef TX_ENABLE_FIQ_SUPPORT +SVC_MODE = 0xD3 @ Disable IRQ/FIQ, SVC mode +IRQ_MODE = 0xD2 @ Disable IRQ/FIQ, IRQ mode +#else +SVC_MODE = 0x93 @ Disable IRQ, SVC mode +IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode +#endif +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_restore Cortex-A8/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function restores the interrupt context if it is processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs Interrupt Service Routines */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_restore(VOID) +@{ + .global _tx_thread_context_restore + .type _tx_thread_context_restore,function +_tx_thread_context_restore: +@ +@ /* Lockout interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR exit function to indicate an ISR is complete. */ +@ + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif +@ +@ /* Determine if interrupts are nested. */ +@ if (--_tx_thread_system_state) +@ { +@ + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + SUB r2, r2, #1 @ Decrement the counter + STR r2, [r3] @ Store the counter + CMP r2, #0 @ Was this the first interrupt? + BEQ __tx_thread_not_nested_restore @ If so, not a nested restore +@ +@ /* Interrupts are nested. */ +@ +@ /* Just recover the saved registers and return to the point of +@ interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +__tx_thread_not_nested_restore: +@ +@ /* Determine if a thread was interrupted and no preemption is required. */ +@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +@ || (_tx_thread_preempt_disable)) +@ { +@ + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup actual current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_restore @ Yes, idle system was interrupted +@ + LDR r3, =_tx_thread_preempt_disable @ Pickup preempt disable address + LDR r2, [r3] @ Pickup actual preempt disable flag + CMP r2, #0 @ Is it set? + BNE __tx_thread_no_preempt_restore @ Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr @ Pickup address of execute thread ptr + LDR r2, [r3] @ Pickup actual execute thread pointer + CMP r0, r2 @ Is the same thread highest priority? + BNE __tx_thread_preempt_restore @ No, preemption needs to happen +@ +@ +__tx_thread_no_preempt_restore: +@ +@ /* Restore interrupted thread or ISR. */ +@ +@ /* Pickup the saved stack pointer. */ +@ tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +@ +@ /* Recover the saved context and return to the point of interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +@ else +@ { +__tx_thread_preempt_restore: +@ + LDMIA sp!, {r3, r10, r12, lr} @ Recover temporarily saved registers + MOV r1, lr @ Save lr (point of interrupt) + MOV r2, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r2 @ Enter SVC mode + STR r1, [sp, #-4]! @ Save point of interrupt + STMDB sp!, {r4-r12, lr} @ Save upper half of registers + MOV r4, r3 @ Save SPSR in r4 + MOV r2, #IRQ_MODE @ Build IRQ mode CPSR + MSR CPSR_c, r2 @ Enter IRQ mode + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOV r5, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r5 @ Enter SVC mode + STMDB sp!, {r0-r3} @ Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r2, [r0, #144] @ Pickup the VFP enabled flag + CMP r2, #0 @ Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save @ No, skip VFP IRQ save + VMRS r2, FPSCR @ Pickup the FPSCR + STR r2, [sp, #-4]! @ Save FPSCR + VSTMDB sp!, {D16-D31} @ Save D16-D31 + VSTMDB sp!, {D0-D15} @ Save D0-D15 +_tx_skip_irq_vfp_save: +#endif + + MOV r3, #1 @ Build interrupt stack type + STMDB sp!, {r3, r4} @ Save interrupt stack type and SPSR + STR sp, [r0, #8] @ Save stack pointer in thread control + @ block +@ +@ /* Save the remaining time-slice and disable it. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup time-slice variable address + LDR r2, [r3] @ Pickup time-slice + CMP r2, #0 @ Is it active? + BEQ __tx_thread_dont_save_ts @ No, don't save it +@ +@ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +@ _tx_timer_time_slice = 0; +@ + STR r2, [r0, #24] @ Save thread's time-slice + MOV r2, #0 @ Clear value + STR r2, [r3] @ Disable global time-slice flag +@ +@ } +__tx_thread_dont_save_ts: +@ +@ +@ /* Clear the current task pointer. */ +@ _tx_thread_current_ptr = TX_NULL; +@ + MOV r0, #0 @ NULL value + STR r0, [r1] @ Clear current thread pointer +@ +@ /* Return to the scheduler. */ +@ _tx_thread_schedule(); +@ + B _tx_thread_schedule @ Return to scheduler +@ } +@ +__tx_thread_idle_system_restore: +@ +@ /* Just return back to the scheduler! */ +@ + MOV r0, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r0 @ Enter SVC mode + B _tx_thread_schedule @ Return to scheduler +@} + + + diff --git a/ports/cortex_a8/ac6/src/tx_thread_context_save.S b/ports/cortex_a8/ac6/src/tx_thread_context_save.S new file mode 100644 index 00000000..fd4c9199 --- /dev/null +++ b/ports/cortex_a8/ac6/src/tx_thread_context_save.S @@ -0,0 +1,202 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global __tx_irq_processing_return +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_save Cortex-A8/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_save(VOID) +@{ + .global _tx_thread_context_save + .type _tx_thread_context_save,function +_tx_thread_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state++) +@ { +@ + STMDB sp!, {r0-r3} @ Save some working registers +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable FIQ interrupts +#endif + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable +@ +@ /* Save the rest of the scratch registers on the stack and return to the +@ calling ISR. */ +@ + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} @ Store other registers +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_irq_processing_return @ Continue IRQ processing +@ +__tx_thread_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + @ scheduling loop - nothing needs saving! +@ +@ /* Save minimal context of interrupted thread. */ +@ + MRS r2, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r2, r10, r12, lr} @ Store other registers +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr@ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_irq_processing_return @ Continue IRQ processing +@ +@ } +@ else +@ { +@ +__tx_thread_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ processing. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + ADD sp, sp, #16 @ Recover saved registers + B __tx_irq_processing_return @ Continue IRQ processing +@ +@ } +@} + + + diff --git a/ports/cortex_a8/ac6/src/tx_thread_fiq_context_restore.S b/ports/cortex_a8/ac6/src/tx_thread_fiq_context_restore.S new file mode 100644 index 00000000..6d94d5cb --- /dev/null +++ b/ports/cortex_a8/ac6/src/tx_thread_fiq_context_restore.S @@ -0,0 +1,259 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ +SVC_MODE = 0xD3 @ SVC mode +FIQ_MODE = 0xD1 @ FIQ mode +MODE_MASK = 0x1F @ Mode mask +THUMB_MASK = 0x20 @ Thumb bit mask +IRQ_MODE_BITS = 0x12 @ IRQ mode bits +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_system_stack_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_context_restore +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_context_restore Cortex-A8/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function restores the fiq interrupt context when processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* FIQ ISR Interrupt Service Routines */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_fiq_context_restore(VOID) +@{ + .global _tx_thread_fiq_context_restore + .type _tx_thread_fiq_context_restore,function +_tx_thread_fiq_context_restore: +@ +@ /* Lockout interrupts. */ +@ + CPSID if @ Disable IRQ and FIQ interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR exit function to indicate an ISR is complete. */ +@ + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif +@ +@ /* Determine if interrupts are nested. */ +@ if (--_tx_thread_system_state) +@ { +@ + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + SUB r2, r2, #1 @ Decrement the counter + STR r2, [r3] @ Store the counter + CMP r2, #0 @ Was this the first interrupt? + BEQ __tx_thread_fiq_not_nested_restore @ If so, not a nested restore +@ +@ /* Interrupts are nested. */ +@ +@ /* Just recover the saved registers and return to the point of +@ interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +__tx_thread_fiq_not_nested_restore: +@ +@ /* Determine if a thread was interrupted and no preemption is required. */ +@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +@ || (_tx_thread_preempt_disable)) +@ { +@ + LDR r1, [sp] @ Pickup the saved SPSR + MOV r2, #MODE_MASK @ Build mask to isolate the interrupted mode + AND r1, r1, r2 @ Isolate mode bits + CMP r1, #IRQ_MODE_BITS @ Was an interrupt taken in IRQ mode before we + @ got to context save? */ + BEQ __tx_thread_fiq_no_preempt_restore @ Yes, just go back to point of interrupt + + + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup actual current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_fiq_idle_system_restore @ Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable @ Pickup preempt disable address + LDR r2, [r3] @ Pickup actual preempt disable flag + CMP r2, #0 @ Is it set? + BNE __tx_thread_fiq_no_preempt_restore @ Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr @ Pickup address of execute thread ptr + LDR r2, [r3] @ Pickup actual execute thread pointer + CMP r0, r2 @ Is the same thread highest priority? + BNE __tx_thread_fiq_preempt_restore @ No, preemption needs to happen + + +__tx_thread_fiq_no_preempt_restore: +@ +@ /* Restore interrupted thread or ISR. */ +@ +@ /* Pickup the saved stack pointer. */ +@ tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +@ +@ /* Recover the saved context and return to the point of interrupt. */ +@ + LDMIA sp!, {r0, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +@ else +@ { +__tx_thread_fiq_preempt_restore: +@ + LDMIA sp!, {r3, lr} @ Recover temporarily saved registers + MOV r1, lr @ Save lr (point of interrupt) + MOV r2, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r2 @ Enter SVC mode + STR r1, [sp, #-4]! @ Save point of interrupt + STMDB sp!, {r4-r12, lr} @ Save upper half of registers + MOV r4, r3 @ Save SPSR in r4 + MOV r2, #FIQ_MODE @ Build FIQ mode CPSR + MSR CPSR_c, r2 @ Reenter FIQ mode + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOV r5, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r5 @ Enter SVC mode + STMDB sp!, {r0-r3} @ Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r2, [r0, #144] @ Pickup the VFP enabled flag + CMP r2, #0 @ Is the VFP enabled? + BEQ _tx_skip_fiq_vfp_save @ No, skip VFP IRQ save + VMRS r2, FPSCR @ Pickup the FPSCR + STR r2, [sp, #-4]! @ Save FPSCR + VSTMDB sp!, {D16-D31} @ Save D16-D31 + VSTMDB sp!, {D0-D15} @ Save D0-D15 +_tx_skip_fiq_vfp_save: +#endif + + MOV r3, #1 @ Build interrupt stack type + STMDB sp!, {r3, r4} @ Save interrupt stack type and SPSR + STR sp, [r0, #8] @ Save stack pointer in thread control + @ block */ +@ +@ /* Save the remaining time-slice and disable it. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup time-slice variable address + LDR r2, [r3] @ Pickup time-slice + CMP r2, #0 @ Is it active? + BEQ __tx_thread_fiq_dont_save_ts @ No, don't save it +@ +@ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +@ _tx_timer_time_slice = 0; +@ + STR r2, [r0, #24] @ Save thread's time-slice + MOV r2, #0 @ Clear value + STR r2, [r3] @ Disable global time-slice flag +@ +@ } +__tx_thread_fiq_dont_save_ts: +@ +@ +@ /* Clear the current task pointer. */ +@ _tx_thread_current_ptr = TX_NULL; +@ + MOV r0, #0 @ NULL value + STR r0, [r1] @ Clear current thread pointer +@ +@ /* Return to the scheduler. */ +@ _tx_thread_schedule(); +@ + B _tx_thread_schedule @ Return to scheduler +@ } +@ +__tx_thread_fiq_idle_system_restore: +@ +@ /* Just return back to the scheduler! */ +@ + ADD sp, sp, #24 @ Recover FIQ stack space + MOV r3, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r3 @ Lockout interrupts + B _tx_thread_schedule @ Return to scheduler +@ +@} + diff --git a/ports/cortex_a8/ac6/src/tx_thread_fiq_context_save.S b/ports/cortex_a8/ac6/src/tx_thread_fiq_context_save.S new file mode 100644 index 00000000..521128a7 --- /dev/null +++ b/ports/cortex_a8/ac6/src/tx_thread_fiq_context_save.S @@ -0,0 +1,203 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global __tx_fiq_processing_return +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_context_save +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_context_save Cortex-A8/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@ VOID _tx_thread_fiq_context_save(VOID) +@{ + .global _tx_thread_fiq_context_save + .type _tx_thread_fiq_context_save,function +_tx_thread_fiq_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state++) +@ { +@ + STMDB sp!, {r0-r3} @ Save some working registers + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_fiq_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable +@ +@ /* Save the rest of the scratch registers on the stack and return to the +@ calling ISR. */ +@ + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} @ Store other registers +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_fiq_processing_return @ Continue FIQ processing +@ +__tx_thread_fiq_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_fiq_idle_system_save @ If so, interrupt occurred in +@ @ scheduling loop - nothing needs saving! +@ +@ /* Save minimal context of interrupted thread. */ +@ + MRS r2, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r2, lr} @ Store other registers, Note that we don't +@ @ need to save sl and ip since FIQ has +@ @ copies of these registers. Nested +@ @ interrupt processing does need to save +@ @ these registers. +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr; +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_fiq_processing_return @ Continue FIQ processing +@ +@ } +@ else +@ { +@ +__tx_thread_fiq_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif +@ +@ /* Not much to do here, save the current SPSR and LR for possible +@ use in IRQ interrupted in idle system conditions, and return to +@ FIQ interrupt processing. */ +@ + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, lr} @ Store other registers that will get used +@ @ or stripped off the stack in context +@ @ restore + B __tx_fiq_processing_return @ Continue FIQ processing +@ +@ } +@} + diff --git a/ports/cortex_a8/ac6/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a8/ac6/src/tx_thread_fiq_nesting_end.S new file mode 100644 index 00000000..3bfb4134 --- /dev/null +++ b/ports/cortex_a8/ac6/src/tx_thread_fiq_nesting_end.S @@ -0,0 +1,116 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts +#else +DISABLE_INTS = 0x80 @ Disable IRQ interrupts +#endif +MODE_MASK = 0x1F @ Mode mask +FIQ_MODE_BITS = 0x11 @ FIQ mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_end +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_nesting_end Cortex-A8/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from FIQ mode after */ +@/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +@/* processing from system mode back to FIQ mode prior to the ISR */ +@/* calling _tx_thread_fiq_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with FIQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_fiq_nesting_end(VOID) +@{ + .global _tx_thread_fiq_nesting_end + .type _tx_thread_fiq_nesting_end,function +_tx_thread_fiq_nesting_end: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value + MSR CPSR_c, r0 @ Disable interrupts + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + @ 8-byte alignment logic) + BIC r0, r0, #MODE_MASK @ Clear mode bits + ORR r0, r0, #FIQ_MODE_BITS @ Build IRQ mode CPSR + MSR CPSR_c, r0 @ Reenter IRQ mode + +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_a8/ac6/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a8/ac6/src/tx_thread_fiq_nesting_start.S new file mode 100644 index 00000000..632be482 --- /dev/null +++ b/ports/cortex_a8/ac6/src/tx_thread_fiq_nesting_start.S @@ -0,0 +1,108 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +FIQ_DISABLE = 0x40 @ FIQ disable bit +MODE_MASK = 0x1F @ Mode mask +SYS_MODE_BITS = 0x1F @ System mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_start +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_nesting_start Cortex-A8/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from FIQ mode after */ +@/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +@/* processing to the system mode so nested FIQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with FIQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_fiq_nesting_start(VOID) +@{ + .global _tx_thread_fiq_nesting_start + .type _tx_thread_fiq_nesting_start,function +_tx_thread_fiq_nesting_start: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + BIC r0, r0, #MODE_MASK @ Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS @ Build system mode CPSR + MSR CPSR_c, r0 @ Enter system mode + STMDB sp!, {r1, lr} @ Push the system mode lr on the system mode stack + @ and push r1 just to keep 8-byte alignment + BIC r0, r0, #FIQ_DISABLE @ Build enable FIQ CPSR + MSR CPSR_c, r0 @ Enter system mode +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_a8/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a8/ac6/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..d7c0071e --- /dev/null +++ b/ports/cortex_a8/ac6/src/tx_thread_interrupt_control.S @@ -0,0 +1,115 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" */ +@ + +INT_MASK = 0x03F + +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_control for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_interrupt_control +$_tx_thread_interrupt_control: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_interrupt_control @ Call _tx_thread_interrupt_control function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_control Cortex-A8/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for changing the interrupt lockout */ +@/* posture of the system. */ +@/* */ +@/* INPUT */ +@/* */ +@/* new_posture New interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_control(UINT new_posture) +@{ + .global _tx_thread_interrupt_control + .type _tx_thread_interrupt_control,function +_tx_thread_interrupt_control: +@ +@ /* Pickup current interrupt lockout posture. */ +@ + MRS r3, CPSR @ Pickup current CPSR + MOV r2, #INT_MASK @ Build interrupt mask + AND r1, r3, r2 @ Clear interrupt lockout bits + ORR r1, r1, r0 @ Or-in new interrupt lockout bits +@ +@ /* Apply the new interrupt posture. */ +@ + MSR CPSR_c, r1 @ Setup new CPSR + BIC r0, r3, r2 @ Return previous interrupt mask +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + diff --git a/ports/cortex_a8/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a8/ac6/src/tx_thread_interrupt_disable.S new file mode 100644 index 00000000..fd002635 --- /dev/null +++ b/ports/cortex_a8/ac6/src/tx_thread_interrupt_disable.S @@ -0,0 +1,113 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_interrupt_disable +$_tx_thread_interrupt_disable: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_interrupt_disable @ Call _tx_thread_interrupt_disable function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_disable Cortex-A8/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for disabling interrupts */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_disable(void) +@{ + .global _tx_thread_interrupt_disable + .type _tx_thread_interrupt_disable,function +_tx_thread_interrupt_disable: +@ +@ /* Pickup current interrupt lockout posture. */ +@ + MRS r0, CPSR @ Pickup current CPSR +@ +@ /* Mask interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ +#else + CPSID i @ Disable IRQ +#endif + +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + + diff --git a/ports/cortex_a8/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a8/ac6/src/tx_thread_interrupt_restore.S new file mode 100644 index 00000000..8ee63b2c --- /dev/null +++ b/ports/cortex_a8/ac6/src/tx_thread_interrupt_restore.S @@ -0,0 +1,104 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_interrupt_restore +$_tx_thread_interrupt_restore: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_interrupt_restore @ Call _tx_thread_interrupt_restore function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_restore Cortex-A8/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for restoring interrupts to the state */ +@/* returned by a previous _tx_thread_interrupt_disable call. */ +@/* */ +@/* INPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_restore(UINT old_posture) +@{ + .global _tx_thread_interrupt_restore + .type _tx_thread_interrupt_restore,function +_tx_thread_interrupt_restore: +@ +@ /* Apply the new interrupt posture. */ +@ + MSR CPSR_c, r0 @ Setup new CPSR +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + diff --git a/ports/cortex_a8/ac6/src/tx_thread_irq_nesting_end.S b/ports/cortex_a8/ac6/src/tx_thread_irq_nesting_end.S new file mode 100644 index 00000000..aeac7b99 --- /dev/null +++ b/ports/cortex_a8/ac6/src/tx_thread_irq_nesting_end.S @@ -0,0 +1,115 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts +#else +DISABLE_INTS = 0x80 @ Disable IRQ interrupts +#endif +MODE_MASK = 0x1F @ Mode mask +IRQ_MODE_BITS = 0x12 @ IRQ mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_end +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_end Cortex-A8/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +@/* processing from system mode back to IRQ mode prior to the ISR */ +@/* calling _tx_thread_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_irq_nesting_end(VOID) +@{ + .global _tx_thread_irq_nesting_end + .type _tx_thread_irq_nesting_end,function +_tx_thread_irq_nesting_end: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value + MSR CPSR_c, r0 @ Disable interrupts + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + @ 8-byte alignment logic) + BIC r0, r0, #MODE_MASK @ Clear mode bits + ORR r0, r0, #IRQ_MODE_BITS @ Build IRQ mode CPSR + MSR CPSR_c, r0 @ Reenter IRQ mode +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_a8/ac6/src/tx_thread_irq_nesting_start.S b/ports/cortex_a8/ac6/src/tx_thread_irq_nesting_start.S new file mode 100644 index 00000000..e1eb663d --- /dev/null +++ b/ports/cortex_a8/ac6/src/tx_thread_irq_nesting_start.S @@ -0,0 +1,108 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +IRQ_DISABLE = 0x80 @ IRQ disable bit +MODE_MASK = 0x1F @ Mode mask +SYS_MODE_BITS = 0x1F @ System mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_start +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_start Cortex-A8/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_context_save has been called and switches the IRQ */ +@/* processing to the system mode so nested IRQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_irq_nesting_start(VOID) +@{ + .global _tx_thread_irq_nesting_start + .type _tx_thread_irq_nesting_start,function +_tx_thread_irq_nesting_start: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + BIC r0, r0, #MODE_MASK @ Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS @ Build system mode CPSR + MSR CPSR_c, r0 @ Enter system mode + STMDB sp!, {r1, lr} @ Push the system mode lr on the system mode stack + @ and push r1 just to keep 8-byte alignment + BIC r0, r0, #IRQ_DISABLE @ Build enable IRQ CPSR + MSR CPSR_c, r0 @ Enter system mode +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_a8/ac6/src/tx_thread_schedule.S b/ports/cortex_a8/ac6/src/tx_thread_schedule.S new file mode 100644 index 00000000..c6c4a8be --- /dev/null +++ b/ports/cortex_a8/ac6/src/tx_thread_schedule.S @@ -0,0 +1,254 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_execute_ptr + .global _tx_thread_current_ptr + .global _tx_timer_time_slice +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_schedule for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_schedule + .type $_tx_thread_schedule,function +$_tx_thread_schedule: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_schedule @ Call _tx_thread_schedule function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_schedule Cortex-A8/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function waits for a thread control block pointer to appear in */ +@/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +@/* in the variable, the corresponding thread is resumed. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* _tx_thread_system_return Return to system from thread */ +@/* _tx_thread_context_restore Restore thread's context */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_schedule(VOID) +@{ + .global _tx_thread_schedule + .type _tx_thread_schedule,function +_tx_thread_schedule: +@ +@ /* Enable interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSIE if @ Enable IRQ and FIQ interrupts +#else + CPSIE i @ Enable IRQ interrupts +#endif +@ +@ /* Wait for a thread to execute. */ +@ do +@ { + LDR r1, =_tx_thread_execute_ptr @ Address of thread execute ptr +@ +__tx_thread_schedule_loop: +@ + LDR r0, [r1] @ Pickup next thread to execute + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_schedule_loop @ If so, keep looking for a thread +@ +@ } +@ while(_tx_thread_execute_ptr == TX_NULL); +@ +@ /* Yes! We have a thread to execute. Lockout interrupts and +@ transfer control to it. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif +@ +@ /* Setup the current thread pointer. */ +@ _tx_thread_current_ptr = _tx_thread_execute_ptr; +@ + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread + STR r0, [r1] @ Setup current thread pointer +@ +@ /* Increment the run count for this thread. */ +@ _tx_thread_current_ptr -> tx_thread_run_count++; +@ + LDR r2, [r0, #4] @ Pickup run counter + LDR r3, [r0, #24] @ Pickup time-slice for this thread + ADD r2, r2, #1 @ Increment thread run-counter + STR r2, [r0, #4] @ Store the new run counter +@ +@ /* Setup time-slice, if present. */ +@ _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; +@ + LDR r2, =_tx_timer_time_slice @ Pickup address of time-slice + @ variable + LDR sp, [r0, #8] @ Switch stack pointers + STR r3, [r2] @ Setup time-slice +@ +@ /* Switch to the thread's stack. */ +@ sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; +@ +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the thread entry function to indicate the thread is executing. */ +@ + MOV r5, r0 @ Save r0 + BL _tx_execution_thread_enter @ Call the thread execution enter function + MOV r0, r5 @ Restore r0 +#endif +@ +@ /* Determine if an interrupt frame or a synchronous task suspension frame +@ is present. */ +@ + LDMIA sp!, {r4, r5} @ Pickup the stack type and saved CPSR + CMP r4, #0 @ Check for synchronous context switch + BEQ _tx_solicited_return + MSR SPSR_cxsf, r5 @ Setup SPSR for return +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r1, [r0, #144] @ Pickup the VFP enabled flag + CMP r1, #0 @ Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore @ No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} @ Recover D0-D15 + VLDMIA sp!, {D16-D31} @ Recover D16-D31 + LDR r4, [sp], #4 @ Pickup FPSCR + VMSR FPSCR, r4 @ Restore FPSCR +_tx_skip_interrupt_vfp_restore: +#endif + LDMIA sp!, {r0-r12, lr, pc}^ @ Return to point of thread interrupt + +_tx_solicited_return: + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r1, [r0, #144] @ Pickup the VFP enabled flag + CMP r1, #0 @ Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore @ No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} @ Recover D8-D15 + VLDMIA sp!, {D16-D31} @ Recover D16-D31 + LDR r4, [sp], #4 @ Pickup FPSCR + VMSR FPSCR, r4 @ Restore FPSCR +_tx_skip_solicited_vfp_restore: +#endif + MSR CPSR_cxsf, r5 @ Recover CPSR + LDMIA sp!, {r4-r11, lr} @ Return to thread synchronously +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@ +@} +@ + +#ifdef TX_ENABLE_VFP_SUPPORT + + .global tx_thread_vfp_enable + .type tx_thread_vfp_enable,function +tx_thread_vfp_enable: + MRS r2, CPSR @ Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Enable IRQ and FIQ interrupts +#else + CPSID i @ Enable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address + LDR r1, [r0] @ Pickup current thread pointer + CMP r1, #0 @ Check for NULL thread pointer + BEQ __tx_no_thread_to_enable @ If NULL, skip VFP enable + MOV r0, #1 @ Build enable value + STR r0, [r1, #144] @ Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable: + MSR CPSR_cxsf, r2 @ Recover CPSR + BX LR @ Return to caller + + .global tx_thread_vfp_disable + .type tx_thread_vfp_disable,function +tx_thread_vfp_disable: + MRS r2, CPSR @ Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Enable IRQ and FIQ interrupts +#else + CPSID i @ Enable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address + LDR r1, [r0] @ Pickup current thread pointer + CMP r1, #0 @ Check for NULL thread pointer + BEQ __tx_no_thread_to_disable @ If NULL, skip VFP disable + MOV r0, #0 @ Build disable value + STR r0, [r1, #144] @ Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable: + MSR CPSR_cxsf, r2 @ Recover CPSR + BX LR @ Return to caller + +#endif + diff --git a/ports/cortex_a8/ac6/src/tx_thread_stack_build.S b/ports/cortex_a8/ac6/src/tx_thread_stack_build.S new file mode 100644 index 00000000..51d783ff --- /dev/null +++ b/ports/cortex_a8/ac6/src/tx_thread_stack_build.S @@ -0,0 +1,178 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ + .arm + +SVC_MODE = 0x13 @ SVC mode +#ifdef TX_ENABLE_FIQ_SUPPORT +CPSR_MASK = 0xDF @ Mask initial CPSR, IRQ & FIQ interrupts enabled +#else +CPSR_MASK = 0x9F @ Mask initial CPSR, IRQ interrupts enabled +#endif +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_stack_build for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .thumb + .global $_tx_thread_stack_build + .type $_tx_thread_stack_build,function +$_tx_thread_stack_build: + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_stack_build @ Call _tx_thread_stack_build function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_stack_build Cortex-A8/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function builds a stack frame on the supplied thread's stack. */ +@/* The stack frame results in a fake interrupt return to the supplied */ +@/* function pointer. */ +@/* */ +@/* INPUT */ +@/* */ +@/* thread_ptr Pointer to thread control blk */ +@/* function_ptr Pointer to return function */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_thread_create Create thread service */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +@{ + .global _tx_thread_stack_build + .type _tx_thread_stack_build,function +_tx_thread_stack_build: +@ +@ +@ /* Build a fake interrupt frame. The form of the fake interrupt stack +@ on the Cortex-A8 should look like the following after it is built: +@ +@ Stack Top: 1 Interrupt stack frame type +@ CPSR Initial value for CPSR +@ a1 (r0) Initial value for a1 +@ a2 (r1) Initial value for a2 +@ a3 (r2) Initial value for a3 +@ a4 (r3) Initial value for a4 +@ v1 (r4) Initial value for v1 +@ v2 (r5) Initial value for v2 +@ v3 (r6) Initial value for v3 +@ v4 (r7) Initial value for v4 +@ v5 (r8) Initial value for v5 +@ sb (r9) Initial value for sb +@ sl (r10) Initial value for sl +@ fp (r11) Initial value for fp +@ ip (r12) Initial value for ip +@ lr (r14) Initial value for lr +@ pc (r15) Initial value for pc +@ 0 For stack backtracing +@ +@ Stack Bottom: (higher memory address) */ +@ + LDR r2, [r0, #16] @ Pickup end of stack area + BIC r2, r2, #7 @ Ensure 8-byte alignment + SUB r2, r2, #76 @ Allocate space for the stack frame +@ +@ /* Actually build the stack frame. */ +@ + MOV r3, #1 @ Build interrupt stack type + STR r3, [r2, #0] @ Store stack type + MOV r3, #0 @ Build initial register value + STR r3, [r2, #8] @ Store initial r0 + STR r3, [r2, #12] @ Store initial r1 + STR r3, [r2, #16] @ Store initial r2 + STR r3, [r2, #20] @ Store initial r3 + STR r3, [r2, #24] @ Store initial r4 + STR r3, [r2, #28] @ Store initial r5 + STR r3, [r2, #32] @ Store initial r6 + STR r3, [r2, #36] @ Store initial r7 + STR r3, [r2, #40] @ Store initial r8 + STR r3, [r2, #44] @ Store initial r9 + LDR r3, [r0, #12] @ Pickup stack starting address + STR r3, [r2, #48] @ Store initial r10 (sl) + LDR r3,=_tx_thread_schedule @ Pickup address of _tx_thread_schedule for GDB backtrace + STR r3, [r2, #60] @ Store initial r14 (lr) + MOV r3, #0 @ Build initial register value + STR r3, [r2, #52] @ Store initial r11 + STR r3, [r2, #56] @ Store initial r12 + STR r1, [r2, #64] @ Store initial pc + STR r3, [r2, #68] @ 0 for back-trace + MRS r1, CPSR @ Pickup CPSR + BIC r1, r1, #CPSR_MASK @ Mask mode bits of CPSR + ORR r3, r1, #SVC_MODE @ Build CPSR, SVC mode, interrupts enabled + STR r3, [r2, #4] @ Store initial CPSR +@ +@ /* Setup stack pointer. */ +@ thread_ptr -> tx_thread_stack_ptr = r2; +@ + STR r2, [r0, #8] @ Save stack pointer in thread's + @ control block +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + + diff --git a/ports/cortex_a8/ac6/src/tx_thread_system_return.S b/ports/cortex_a8/ac6/src/tx_thread_system_return.S new file mode 100644 index 00000000..07044996 --- /dev/null +++ b/ports/cortex_a8/ac6/src/tx_thread_system_return.S @@ -0,0 +1,179 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ + .arm +@ +@ + .global _tx_thread_current_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule +@ +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_system_return for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_system_return + .type $_tx_thread_system_return,function +$_tx_thread_system_return: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_system_return @ Call _tx_thread_system_return function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_system_return Cortex-A8/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is target processor specific. It is used to transfer */ +@/* control from a thread back to the ThreadX system. Only a */ +@/* minimal context is saved since the compiler assumes temp registers */ +@/* are going to get slicked by a function call anyway. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling loop */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX components */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_system_return(VOID) +@{ + .global _tx_thread_system_return + .type _tx_thread_system_return,function +_tx_thread_system_return: +@ +@ /* Save minimal context on the stack. */ +@ + STMDB sp!, {r4-r11, lr} @ Save minimal context + + LDR r4, =_tx_thread_current_ptr @ Pickup address of current ptr + LDR r5, [r4] @ Pickup current thread pointer + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r1, [r5, #144] @ Pickup the VFP enabled flag + CMP r1, #0 @ Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save @ No, skip VFP solicited save + VMRS r1, FPSCR @ Pickup the FPSCR + STR r1, [sp, #-4]! @ Save FPSCR + VSTMDB sp!, {D16-D31} @ Save D16-D31 + VSTMDB sp!, {D8-D15} @ Save D8-D15 +_tx_skip_solicited_vfp_save: +#endif + + MOV r0, #0 @ Build a solicited stack type + MRS r1, CPSR @ Pickup the CPSR + STMDB sp!, {r0-r1} @ Save type and CPSR +@ +@ /* Lockout interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the thread exit function to indicate the thread is no longer executing. */ +@ + BL _tx_execution_thread_exit @ Call the thread exit function +#endif + MOV r3, r4 @ Pickup address of current ptr + MOV r0, r5 @ Pickup current thread pointer + LDR r2, =_tx_timer_time_slice @ Pickup address of time slice + LDR r1, [r2] @ Pickup current time slice +@ +@ /* Save current stack and switch to system stack. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ sp = _tx_thread_system_stack_ptr; +@ + STR sp, [r0, #8] @ Save thread stack pointer +@ +@ /* Determine if the time-slice is active. */ +@ if (_tx_timer_time_slice) +@ { +@ + MOV r4, #0 @ Build clear value + CMP r1, #0 @ Is a time-slice active? + BEQ __tx_thread_dont_save_ts @ No, don't save the time-slice +@ +@ /* Save time-slice for the thread and clear the current time-slice. */ +@ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +@ _tx_timer_time_slice = 0; +@ + STR r4, [r2] @ Clear time-slice + STR r1, [r0, #24] @ Save current time-slice +@ +@ } +__tx_thread_dont_save_ts: +@ +@ /* Clear the current thread pointer. */ +@ _tx_thread_current_ptr = TX_NULL; +@ + STR r4, [r3] @ Clear current thread pointer + B _tx_thread_schedule @ Jump to scheduler! +@ +@} + diff --git a/ports/cortex_a8/ac6/src/tx_thread_vectored_context_save.S b/ports/cortex_a8/ac6/src/tx_thread_vectored_context_save.S new file mode 100644 index 00000000..97ab8427 --- /dev/null +++ b/ports/cortex_a8/ac6/src/tx_thread_vectored_context_save.S @@ -0,0 +1,189 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr +@ +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_vectored_context_save +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_vectored_context_save Cortex-A8/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_vectored_context_save(VOID) +@{ + .global _tx_thread_vectored_context_save + .type _tx_thread_vectored_context_save,function +_tx_thread_vectored_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state++) +@ { +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#endif + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3, #0] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3, #0] @ Store it back in the variable +@ +@ /* Note: Minimal context of interrupted thread is already saved. */ +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + MOV pc, lr @ Return to caller +@ +__tx_thread_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3, #0] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1, #0] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + @ scheduling loop - nothing needs saving! +@ +@ /* Note: Minimal context of interrupted thread is already saved. */ +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr; +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + MOV pc, lr @ Return to caller +@ +@ } +@ else +@ { +@ +__tx_thread_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ processing. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + ADD sp, sp, #32 @ Recover saved registers + MOV pc, lr @ Return to caller +@ +@ } +@} + diff --git a/ports/cortex_a8/ac6/src/tx_timer_interrupt.S b/ports/cortex_a8/ac6/src/tx_timer_interrupt.S new file mode 100644 index 00000000..84e057a0 --- /dev/null +++ b/ports/cortex_a8/ac6/src/tx_timer_interrupt.S @@ -0,0 +1,279 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Timer */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_timer.h" +@#include "tx_thread.h" +@ +@ + .arm + +@ +@/* Define Assembly language external references... */ +@ + .global _tx_timer_time_slice + .global _tx_timer_system_clock + .global _tx_timer_current_ptr + .global _tx_timer_list_start + .global _tx_timer_list_end + .global _tx_timer_expired_time_slice + .global _tx_timer_expired + .global _tx_thread_time_slice +@ +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_timer_interrupt for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .thumb + .global $_tx_timer_interrupt + .type $_tx_timer_interrupt,function +$_tx_timer_interrupt: + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_timer_interrupt @ Call _tx_timer_interrupt function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_timer_interrupt Cortex-A8/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function processes the hardware timer interrupt. This */ +@/* processing includes incrementing the system clock and checking for */ +@/* time slice and/or timer expiration. If either is found, the */ +@/* interrupt context save/restore functions are called along with the */ +@/* expiration functions. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_time_slice Time slice interrupted thread */ +@/* _tx_timer_expiration_process Timer expiration processing */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* interrupt vector */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_timer_interrupt(VOID) +@{ + .global _tx_timer_interrupt + .type _tx_timer_interrupt,function +_tx_timer_interrupt: +@ +@ /* Upon entry to this routine, it is assumed that context save has already +@ been called, and therefore the compiler scratch registers are available +@ for use. */ +@ +@ /* Increment the system clock. */ +@ _tx_timer_system_clock++; +@ + LDR r1, =_tx_timer_system_clock @ Pickup address of system clock + LDR r0, [r1] @ Pickup system clock + ADD r0, r0, #1 @ Increment system clock + STR r0, [r1] @ Store new system clock +@ +@ /* Test for time-slice expiration. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice + LDR r2, [r3] @ Pickup time-slice + CMP r2, #0 @ Is it non-active? + BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing +@ +@ /* Decrement the time_slice. */ +@ _tx_timer_time_slice--; +@ + SUB r2, r2, #1 @ Decrement the time-slice + STR r2, [r3] @ Store new time-slice value +@ +@ /* Check for expiration. */ +@ if (__tx_timer_time_slice == 0) +@ + CMP r2, #0 @ Has it expired? + BNE __tx_timer_no_time_slice @ No, skip expiration processing +@ +@ /* Set the time-slice expired flag. */ +@ _tx_timer_expired_time_slice = TX_TRUE; +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of expired flag + MOV r0, #1 @ Build expired value + STR r0, [r3] @ Set time-slice expiration flag +@ +@ } +@ +__tx_timer_no_time_slice: +@ +@ /* Test for timer expiration. */ +@ if (*_tx_timer_current_ptr) +@ { +@ + LDR r1, =_tx_timer_current_ptr @ Pickup current timer pointer address + LDR r0, [r1] @ Pickup current timer + LDR r2, [r0] @ Pickup timer list entry + CMP r2, #0 @ Is there anything in the list? + BEQ __tx_timer_no_timer @ No, just increment the timer +@ +@ /* Set expiration flag. */ +@ _tx_timer_expired = TX_TRUE; +@ + LDR r3, =_tx_timer_expired @ Pickup expiration flag address + MOV r2, #1 @ Build expired value + STR r2, [r3] @ Set expired flag + B __tx_timer_done @ Finished timer processing +@ +@ } +@ else +@ { +__tx_timer_no_timer: +@ +@ /* No timer expired, increment the timer pointer. */ +@ _tx_timer_current_ptr++; +@ + ADD r0, r0, #4 @ Move to next timer +@ +@ /* Check for wraparound. */ +@ if (_tx_timer_current_ptr == _tx_timer_list_end) +@ + LDR r3, =_tx_timer_list_end @ Pickup address of timer list end + LDR r2, [r3] @ Pickup list end + CMP r0, r2 @ Are we at list end? + BNE __tx_timer_skip_wrap @ No, skip wraparound logic +@ +@ /* Wrap to beginning of list. */ +@ _tx_timer_current_ptr = _tx_timer_list_start; +@ + LDR r3, =_tx_timer_list_start @ Pickup address of timer list start + LDR r0, [r3] @ Set current pointer to list start +@ +__tx_timer_skip_wrap: +@ + STR r0, [r1] @ Store new current timer pointer +@ } +@ +__tx_timer_done: +@ +@ +@ /* See if anything has expired. */ +@ if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +@ { +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of expired flag + LDR r2, [r3] @ Pickup time-slice expired flag + CMP r2, #0 @ Did a time-slice expire? + BNE __tx_something_expired @ If non-zero, time-slice expired + LDR r1, =_tx_timer_expired @ Pickup address of other expired flag + LDR r0, [r1] @ Pickup timer expired flag + CMP r0, #0 @ Did a timer expire? + BEQ __tx_timer_nothing_expired @ No, nothing expired +@ +__tx_something_expired: +@ +@ + STMDB sp!, {r0, lr} @ Save the lr register on the stack + @ and save r0 just to keep 8-byte alignment +@ +@ /* Did a timer expire? */ +@ if (_tx_timer_expired) +@ { +@ + LDR r1, =_tx_timer_expired @ Pickup address of expired flag + LDR r0, [r1] @ Pickup timer expired flag + CMP r0, #0 @ Check for timer expiration + BEQ __tx_timer_dont_activate @ If not set, skip timer activation +@ +@ /* Process timer expiration. */ +@ _tx_timer_expiration_process(); +@ + BL _tx_timer_expiration_process @ Call the timer expiration handling routine +@ +@ } +__tx_timer_dont_activate: +@ +@ /* Did time slice expire? */ +@ if (_tx_timer_expired_time_slice) +@ { +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of time-slice expired + LDR r2, [r3] @ Pickup the actual flag + CMP r2, #0 @ See if the flag is set + BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing +@ +@ /* Time slice interrupted thread. */ +@ _tx_thread_time_slice(); +@ + BL _tx_thread_time_slice @ Call time-slice processing +@ +@ } +@ +__tx_timer_not_ts_expiration: +@ + LDMIA sp!, {r0, lr} @ Recover lr register (r0 is just there for + @ the 8-byte stack alignment +@ +@ } +@ +__tx_timer_nothing_expired: +@ +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@ +@} + diff --git a/ports/cortex_a9/ac6/example_build/sample_threadx/.cproject b/ports/cortex_a9/ac6/example_build/sample_threadx/.cproject new file mode 100644 index 00000000..b466ad17 --- /dev/null +++ b/ports/cortex_a9/ac6/example_build/sample_threadx/.cproject @@ -0,0 +1,238 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_a9/ac6/example_build/sample_threadx/.project b/ports/cortex_a9/ac6/example_build/sample_threadx/.project new file mode 100644 index 00000000..725328bd --- /dev/null +++ b/ports/cortex_a9/ac6/example_build/sample_threadx/.project @@ -0,0 +1,27 @@ + + + sample_threadx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.arm.debug.ds.nature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/ports/cortex_a9/ac6/example_build/sample_threadx/.settings/language.settings.xml b/ports/cortex_a9/ac6/example_build/sample_threadx/.settings/language.settings.xml new file mode 100644 index 00000000..e92c23dd --- /dev/null +++ b/ports/cortex_a9/ac6/example_build/sample_threadx/.settings/language.settings.xml @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_a9/ac6/example_build/sample_threadx/cortex-a9_tx.launch b/ports/cortex_a9/ac6/example_build/sample_threadx/cortex-a9_tx.launch new file mode 100644 index 00000000..92ab47e5 --- /dev/null +++ b/ports/cortex_a9/ac6/example_build/sample_threadx/cortex-a9_tx.launch @@ -0,0 +1,152 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_a9/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_a9/ac6/example_build/sample_threadx/sample_threadx.c new file mode 100644 index 00000000..418ec634 --- /dev/null +++ b/ports/cortex_a9/ac6/example_build/sample_threadx/sample_threadx.c @@ -0,0 +1,369 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_a9/ac6/example_build/sample_threadx/sample_threadx.scat b/ports/cortex_a9/ac6/example_build/sample_threadx/sample_threadx.scat new file mode 100644 index 00000000..71410dbc --- /dev/null +++ b/ports/cortex_a9/ac6/example_build/sample_threadx/sample_threadx.scat @@ -0,0 +1,46 @@ +;******************************************************* +; Copyright (c) 2011-2016 Arm Limited (or its affiliates). All rights reserved. +; Use, modification and redistribution of this file is subject to your possession of a +; valid End User License Agreement for the Arm Product of which these examples are part of +; and your compliance with all applicable terms and conditions of such licence agreement. +;******************************************************* + +; Scatter-file for Cortex-A9 bare-metal example on Versatile Express + +; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map. + +; Versatile Express with Cortex-A9 has 1GB SDRAM at 0x60000000 to 0x9FFFFFFF, which this scatter-file uses. + + +SDRAM 0x80000000 0x20000000 +{ + VECTORS +0 + { + * (VECTORS, +FIRST) ; Vector table and other (assembler) startup code + * (InRoot$$Sections) ; All (library) code that must be in a root region + } + + RO_CODE +0 + { * (+RO-CODE) } ; Application RO code (.text) + + RO_DATA +0 + { * (+RO-DATA) } ; Application RO data (.constdata) + + RW_DATA +0 + { * (+RW) } ; Application RW data (.data) + + ZI_DATA +0 + { * (+ZI) } ; Application ZI data (.bss) + + ARM_LIB_HEAP 0x80040000 EMPTY 0x00040000 ; Application heap + { } + + ARM_LIB_STACK 0x80090000 EMPTY 0x00010000 ; Application (SVC mode) stack + { } + + ;IRQ_STACK 0x800A0000 EMPTY -0x00010000 ; IRQ mode stack + ;{ } + + TTB 0x80100000 EMPTY 0x4000 ; Level-1 Translation Table for MMU + { } +} diff --git a/ports/cortex_a9/ac6/example_build/sample_threadx/startup.S b/ports/cortex_a9/ac6/example_build/sample_threadx/startup.S new file mode 100644 index 00000000..76ad6539 --- /dev/null +++ b/ports/cortex_a9/ac6/example_build/sample_threadx/startup.S @@ -0,0 +1,359 @@ +//---------------------------------------------------------------- +// Cortex-A9 Embedded example - Startup Code +// +// Copyright (c) 2005-2018 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +//---------------------------------------------------------------- + + +// Standard definitions of mode bits and interrupt (I & F) flags in PSRs + +#define Mode_USR 0x10 +#define Mode_FIQ 0x11 +#define Mode_IRQ 0x12 +#define Mode_SVC 0x13 +#define Mode_ABT 0x17 +#define Mode_UND 0x1B +#define Mode_SYS 0x1F + +#define I_Bit 0x80 // When I bit is set, IRQ is disabled +#define F_Bit 0x40 // When F bit is set, FIQ is disabled + + + .section VECTORS, "ax" + .align 3 + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + + +//---------------------------------------------------------------- +// Entry point for the Reset handler +//---------------------------------------------------------------- + + .global Vectors + +//---------------------------------------------------------------- +// Exception Vector Table +//---------------------------------------------------------------- +// Note: LDR PC instructions are used here, though branch (B) instructions +// could also be used, unless the exception handlers are >32MB away. + +Vectors: + LDR PC, Reset_Addr + LDR PC, Undefined_Addr + LDR PC, SVC_Addr + LDR PC, Prefetch_Addr + LDR PC, Abort_Addr + B . // Reserved vector + LDR PC, IRQ_Addr + LDR PC, FIQ_Addr + + + .balign 4 +Reset_Addr: + .word Reset_Handler +Undefined_Addr: + //.word Undefined_Handler + .word __tx_undefined +SVC_Addr: + //.word SVC_Handler + .word __tx_swi_interrupt +Prefetch_Addr: + //.word Prefetch_Handler + .word __tx_prefetch_handler +Abort_Addr: + //.word Abort_Handler + .word __tx_abort_handler +IRQ_Addr: + //.word IRQ_Handler + .word __tx_irq_handler +FIQ_Addr: + //.word FIQ_Handler + .word __tx_fiq_handler + + +//---------------------------------------------------------------- +// Exception Handlers +//---------------------------------------------------------------- + +Undefined_Handler: + B Undefined_Handler +SVC_Handler: + B SVC_Handler +Prefetch_Handler: + B Prefetch_Handler +Abort_Handler: + B Abort_Handler +IRQ_Handler: + B IRQ_Handler +FIQ_Handler: + B FIQ_Handler + + + + +//---------------------------------------------------------------- +// Reset Handler +//---------------------------------------------------------------- +Reset_Handler: + +//---------------------------------------------------------------- +// Disable caches, MMU and branch prediction in case they were left enabled from an earlier run +// This does not need to be done from a cold reset +//---------------------------------------------------------------- + + MRC p15, 0, r0, c1, c0, 0 // Read System Control Register + BIC r0, r0, #(0x1 << 12) // Clear I bit 12 to disable I Cache + BIC r0, r0, #(0x1 << 2) // Clear C bit 2 to disable D Cache + BIC r0, r0, #0x1 // Clear M bit 0 to disable MMU + BIC r0, r0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction + MCR p15, 0, r0, c1, c0, 0 // Write System Control Register + ISB + +// The MMU is enabled later, before calling main(). Caches and branch prediction are enabled inside main(), +// after the MMU has been enabled and scatterloading has been performed. + +//---------------------------------------------------------------- +// Initialize Supervisor Mode Stack +// Note stack must be 8 byte aligned. +//---------------------------------------------------------------- + + LDR SP, =Image$$ARM_LIB_STACK$$ZI$$Limit + +//---------------------------------------------------------------- +// Invalidate Data and Instruction TLBs and branch predictor +//---------------------------------------------------------------- + + MOV r0,#0 + MCR p15, 0, r0, c8, c7, 0 // I-TLB and D-TLB invalidation + MCR p15, 0, r0, c7, c5, 6 // BPIALL - Invalidate entire branch predictor array + +//---------------------------------------------------------------- +// Set Vector Base Address Register (VBAR) to point to this application's vector table +//---------------------------------------------------------------- + + LDR r0, =Vectors + MCR p15, 0, r0, c12, c0, 0 + +//---------------------------------------------------------------- +// Cache Invalidation code for Cortex-A9 +//---------------------------------------------------------------- + + // Invalidate L1 Instruction Cache + + MRC p15, 1, r0, c0, c0, 1 // Read Cache Level ID Register (CLIDR) + TST r0, #0x3 // Harvard Cache? + MOV r0, #0 // SBZ + MCRNE p15, 0, r0, c7, c5, 0 // ICIALLU - Invalidate instruction cache and flush branch target cache + + // Invalidate Data/Unified Caches + + MRC p15, 1, r0, c0, c0, 1 // Read CLIDR + ANDS r3, r0, #0x07000000 // Extract coherency level + MOV r3, r3, LSR #23 // Total cache levels << 1 + BEQ Finished // If 0, no need to clean + + MOV r10, #0 // R10 holds current cache level << 1 +Loop1: + ADD r2, r10, r10, LSR #1 // R2 holds cache "Set" position + MOV r1, r0, LSR r2 // Bottom 3 bits are the Cache-type for this level + AND r1, r1, #7 // Isolate those lower 3 bits + CMP r1, #2 + BLT Skip // No cache or only instruction cache at this level + + MCR p15, 2, r10, c0, c0, 0 // Write the Cache Size selection register + ISB // ISB to sync the change to the CacheSizeID reg + MRC p15, 1, r1, c0, c0, 0 // Reads current Cache Size ID register + AND r2, r1, #7 // Extract the line length field + ADD r2, r2, #4 // Add 4 for the line length offset (log2 16 bytes) + LDR r4, =0x3FF + ANDS r4, r4, r1, LSR #3 // R4 is the max number on the way size (right aligned) + CLZ r5, r4 // R5 is the bit position of the way size increment + LDR r7, =0x7FFF + ANDS r7, r7, r1, LSR #13 // R7 is the max number of the index size (right aligned) + +Loop2: + MOV r9, r4 // R9 working copy of the max way size (right aligned) + +Loop3: + ORR r11, r10, r9, LSL r5 // Factor in the Way number and cache number into R11 + ORR r11, r11, r7, LSL r2 // Factor in the Set number + MCR p15, 0, r11, c7, c6, 2 // Invalidate by Set/Way + SUBS r9, r9, #1 // Decrement the Way number + BGE Loop3 + SUBS r7, r7, #1 // Decrement the Set number + BGE Loop2 +Skip: + ADD r10, r10, #2 // Increment the cache number + CMP r3, r10 + BGT Loop1 + +Finished: + + +//---------------------------------------------------------------- +// MMU Configuration +// Set translation table base +//---------------------------------------------------------------- + + // Two translation tables are supported, TTBR0 and TTBR1 + // Configure translation table base (TTB) control register cp15,c2 + // to a value of all zeros, indicates we are using TTB register 0. + + MOV r0,#0x0 + MCR p15, 0, r0, c2, c0, 2 + + // write the address of our page table base to TTB register 0 + LDR r0,=Image$$TTB$$ZI$$Base + MOV r1, #0x08 // RGN=b01 (outer cacheable write-back cached, write allocate) + // S=0 (translation table walk to non-shared memory) + ORR r1,r1,#0x40 // IRGN=b01 (inner cacheability for the translation table walk is Write-back Write-allocate) + + ORR r0,r0,r1 + MCR p15, 0, r0, c2, c0, 0 + + +//---------------------------------------------------------------- +// PAGE TABLE generation + +// Generate the page tables +// Build a flat translation table for the whole address space. +// ie: Create 4096 1MB sections from 0x000xxxxx to 0xFFFxxxxx + + +// 31 20 19 18 17 16 15 14 12 11 10 9 8 5 4 3 2 1 0 +// |section base address| 0 0 |nG| S |AP2| TEX | AP | P | Domain | XN | C B | 1 0| +// +// Bits[31:20] - Top 12 bits of VA is pointer into table +// nG[17]=0 - Non global, enables matching against ASID in the TLB when set. +// S[16]=0 - Indicates normal memory is shared when set. +// AP2[15]=0 +// AP[11:10]=11 - Configure for full read/write access in all modes +// TEX[14:12]=000 +// CB[3:2]= 00 - Set attributes to Strongly-ordered memory. +// (except for the code segment descriptor, see below) +// IMPP[9]=0 - Ignored +// Domain[5:8]=1111 - Set all pages to use domain 15 +// XN[4]=1 - Execute never on Strongly-ordered memory +// Bits[1:0]=10 - Indicate entry is a 1MB section +//---------------------------------------------------------------- + LDR r0,=Image$$TTB$$ZI$$Base + LDR r1,=0xfff // loop counter + LDR r2,=0b00000000000000000000110111100010 + + // r0 contains the address of the translation table base + // r1 is loop counter + // r2 is level1 descriptor (bits 19:0) + + // use loop counter to create 4096 individual table entries. + // this writes from address 'Image$$TTB$$ZI$$Base' + + // offset 0x3FFC down to offset 0x0 in word steps (4 bytes) + +init_ttb_1: + ORR r3, r2, r1, LSL#20 // R3 now contains full level1 descriptor to write + ORR r3, r3, #0b0000000010000 // Set XN bit + STR r3, [r0, r1, LSL#2] // Str table entry at TTB base + loopcount*4 + SUBS r1, r1, #1 // Decrement loop counter + BPL init_ttb_1 + + // In this example, the 1MB section based at '__code_start' is setup specially as cacheable (write back mode). + // TEX[14:12]=001 and CB[3:2]= 11, Outer and inner write back, write allocate normal memory. + LDR r1,=Image$$VECTORS$$Base // Base physical address of code segment + LSR r1, #20 // Shift right to align to 1MB boundaries + ORR r3, r2, r1, LSL#20 // Setup the initial level1 descriptor again + ORR r3, r3, #0b0000000001100 // Set CB bits + ORR r3, r3, #0b1000000000000 // Set TEX bit 12 + STR r3, [r0, r1, LSL#2] // str table entry + +//---------------------------------------------------------------- +// Setup domain control register - Enable all domains to client mode +//---------------------------------------------------------------- + + MRC p15, 0, r0, c3, c0, 0 // Read Domain Access Control Register + LDR r0, =0x55555555 // Initialize every domain entry to b01 (client) + MCR p15, 0, r0, c3, c0, 0 // Write Domain Access Control Register + +#if defined(__ARM_NEON) || defined(__ARM_FP) +//---------------------------------------------------------------- +// Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11. +// Enables Full Access i.e. in both privileged and non privileged modes +//---------------------------------------------------------------- + + MRC p15, 0, r0, c1, c0, 2 // Read Coprocessor Access Control Register (CPACR) + ORR r0, r0, #(0xF << 20) // Enable access to CP 10 & 11 + MCR p15, 0, r0, c1, c0, 2 // Write Coprocessor Access Control Register (CPACR) + ISB + +//---------------------------------------------------------------- +// Switch on the VFP and NEON hardware +//---------------------------------------------------------------- + + MOV r0, #0x40000000 + VMSR FPEXC, r0 // Write FPEXC register, EN bit set +#endif + + +//---------------------------------------------------------------- +// Enable MMU and branch to __main +// Leaving the caches disabled until after scatter loading. +//---------------------------------------------------------------- + + LDR r12,=__main + + MRC p15, 0, r0, c1, c0, 0 // Read System Control Register + BIC r0, r0, #(0x1 << 12) // Clear I bit 12 to disable I Cache + BIC r0, r0, #(0x1 << 2) // Clear C bit 2 to disable D Cache + BIC r0, r0, #0x2 // Clear A bit 1 to disable strict alignment fault checking + ORR r0, r0, #0x1 // Set M bit 0 to enable MMU before scatter loading + MCR p15, 0, r0, c1, c0, 0 // Write System Control Register + ISB + +// Now the MMU is enabled, virtual to physical address translations will occur. This will affect the next +// instruction fetch. +// +// The two instructions currently in the pipeline will have been fetched before the MMU was enabled. +// The branch to __main is safe because the Virtual Address (VA) is the same as the Physical Address (PA) +// (flat mapping) of this code that enables the MMU and performs the branch + + BX r12 // Branch to __main C library entry point + + + +//---------------------------------------------------------------- +// Enable caches and branch prediction +// This code must be run from a privileged mode +//---------------------------------------------------------------- + + .section ENABLECACHES,"ax" + .align 3 + + .global enable_caches + .type enable_caches, "function" + .cfi_startproc +enable_caches: + +//---------------------------------------------------------------- +// Enable caches and branch prediction +//---------------------------------------------------------------- + + MRC p15, 0, r0, c1, c0, 0 // Read System Control Register + ORR r0, r0, #(0x1 << 12) // Set I bit 12 to enable I Cache + ORR r0, r0, #(0x1 << 2) // Set C bit 2 to enable D Cache + ORR r0, r0, #(0x1 << 11) // Set Z bit 11 to enable branch prediction + MCR p15, 0, r0, c1, c0, 0 // Write System Control Register + ISB + + +//---------------------------------------------------------------- +// Enable L1 D-side prefetch (A9 specific) +//---------------------------------------------------------------- + + MRC p15, 0, r0, c1, c0, 1 // Read Auxiliary Control Register + ORR r0, r0, #(0x1 << 2) // Set DP bit 2 to enable L1 Dside prefetch + MCR p15, 0, r0, c1, c0, 1 // Write Auxiliary Control Register + ISB + + BX lr + .cfi_endproc + diff --git a/ports/cortex_a9/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_a9/ac6/example_build/sample_threadx/tx_initialize_low_level.S new file mode 100644 index 00000000..b7a3ef98 --- /dev/null +++ b/ports/cortex_a9/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -0,0 +1,345 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Initialize */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_initialize.h" +@#include "tx_thread.h" +@#include "tx_timer.h" + + .arm + +SVC_MODE = 0xD3 @ Disable IRQ/FIQ SVC mode +IRQ_MODE = 0xD2 @ Disable IRQ/FIQ IRQ mode +FIQ_MODE = 0xD1 @ Disable IRQ/FIQ FIQ mode +SYS_MODE = 0xDF @ Disable IRQ/FIQ SYS mode +FIQ_STACK_SIZE = 512 @ FIQ stack size +IRQ_STACK_SIZE = 1024 @ IRQ stack size +SYS_STACK_SIZE = 1024 @ System stack size +@ +@ + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global _tx_thread_context_save + .global _tx_thread_context_restore + .global _tx_timer_interrupt + +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_initialize_low_level for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .thumb + .global $_tx_initialize_low_level + .type $_tx_initialize_low_level,function +$_tx_initialize_low_level: + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_initialize_low_level @ Call _tx_initialize_low_level function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_initialize_low_level Cortex-A9/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for any low-level processor */ +@/* initialization, including setting up interrupt vectors, setting */ +@/* up a periodic timer interrupt source, saving the system stack */ +@/* pointer for use in ISR processing later, and finding the first */ +@/* available RAM memory address for tx_application_define. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_initialize_low_level(VOID) +@{ + .global _tx_initialize_low_level + .type _tx_initialize_low_level,function +_tx_initialize_low_level: +@ +@ /* We must be in SVC mode at this point! */ +@ +@ /* Setup various stack pointers. */ +@ + LDR r1, =Image$$ARM_LIB_STACK$$ZI$$Limit @ Get pointer to stack area + +#ifdef TX_ENABLE_IRQ_NESTING +@ +@ /* Setup the system mode stack for nested interrupt support */ +@ + LDR r2, =SYS_STACK_SIZE @ Pickup stack size + MOV r3, #SYS_MODE @ Build SYS mode CPSR + MSR CPSR_c, r3 @ Enter SYS mode + SUB r1, r1, #1 @ Backup 1 byte + BIC r1, r1, #7 @ Ensure 8-byte alignment + MOV sp, r1 @ Setup SYS stack pointer + SUB r1, r1, r2 @ Calculate start of next stack +#endif + + LDR r2, =FIQ_STACK_SIZE @ Pickup stack size + MOV r0, #FIQ_MODE @ Build FIQ mode CPSR + MSR CPSR, r0 @ Enter FIQ mode + SUB r1, r1, #1 @ Backup 1 byte + BIC r1, r1, #7 @ Ensure 8-byte alignment + MOV sp, r1 @ Setup FIQ stack pointer + SUB r1, r1, r2 @ Calculate start of next stack + LDR r2, =IRQ_STACK_SIZE @ Pickup IRQ stack size + MOV r0, #IRQ_MODE @ Build IRQ mode CPSR + MSR CPSR, r0 @ Enter IRQ mode + SUB r1, r1, #1 @ Backup 1 byte + BIC r1, r1, #7 @ Ensure 8-byte alignment + MOV sp, r1 @ Setup IRQ stack pointer + SUB r3, r1, r2 @ Calculate end of IRQ stack + MOV r0, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR, r0 @ Enter SVC mode + LDR r2, =Image$$ARM_LIB_STACK$$Base @ Pickup stack bottom + CMP r3, r2 @ Compare the current stack end with the bottom +_stack_error_loop: + BLT _stack_error_loop @ If the IRQ stack exceeds the stack bottom, just sit here! +@ +@ /* Save the system stack pointer. */ +@ _tx_thread_system_stack_ptr = (VOID_PTR) (sp); +@ + LDR r2, =_tx_thread_system_stack_ptr @ Pickup stack pointer + STR r1, [r2] @ Save the system stack +@ +@ /* Save the first available memory address. */ +@ _tx_initialize_unused_memory = (VOID_PTR) _end; +@ + LDR r1, =Image$$ZI_DATA$$ZI$$Limit @ Get end of non-initialized RAM area + LDR r2, =_tx_initialize_unused_memory @ Pickup unused memory ptr address + ADD r1, r1, #8 @ Increment to next free word + STR r1, [r2] @ Save first free memory address +@ +@ /* Setup Timer for periodic interrupts. */ +@ +@ /* Done, return to caller. */ +@ +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} +@ +@ +@/* Define shells for each of the interrupt vectors. */ +@ + .global __tx_undefined +__tx_undefined: + B __tx_undefined @ Undefined handler +@ + .global __tx_swi_interrupt +__tx_swi_interrupt: + B __tx_swi_interrupt @ Software interrupt handler +@ + .global __tx_prefetch_handler +__tx_prefetch_handler: + B __tx_prefetch_handler @ Prefetch exception handler +@ + .global __tx_abort_handler +__tx_abort_handler: + B __tx_abort_handler @ Abort exception handler +@ + .global __tx_reserved_handler +__tx_reserved_handler: + B __tx_reserved_handler @ Reserved exception handler +@ + .global __tx_irq_processing_return + .type __tx_irq_processing_return,function + .global __tx_irq_handler +__tx_irq_handler: +@ +@ /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return: +@ +@ /* At this point execution is still in the IRQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. In +@ addition, IRQ interrupts may be re-enabled - with certain restrictions - +@ if nested IRQ interrupts are desired. Interrupts may be re-enabled over +@ small code sequences where lr is saved before enabling interrupts and +@ restored after interrupts are again disabled. */ +@ +@ /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +@ from IRQ mode with interrupts disabled. This routine switches to the +@ system mode and returns with IRQ interrupts enabled. +@ +@ NOTE: It is very important to ensure all IRQ interrupts are cleared +@ prior to enabling nested IRQ interrupts. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_start +#endif +@ +@ /* For debug purpose, execute the timer interrupt processing here. In +@ a real system, some kind of status indication would have to be checked +@ before the timer interrupt handler could be called. */ +@ + BL _tx_timer_interrupt @ Timer interrupt handler +@ +@ +@ /* If interrupt nesting was started earlier, the end of interrupt nesting +@ service must be called before returning to _tx_thread_context_restore. +@ This routine returns in processing in IRQ mode with interrupts disabled. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_end +#endif +@ +@ /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore +@ +@ +@ /* This is an example of a vectored IRQ handler. */ +@ +@ .global __tx_example_vectored_irq_handler +@__tx_example_vectored_irq_handler: +@ +@ +@ /* Save initial context and call context save to prepare for +@ vectored ISR execution. */ +@ +@ STMDB sp!, {r0-r3} @ Save some scratch registers +@ MRS r0, SPSR @ Pickup saved SPSR +@ SUB lr, lr, #4 @ Adjust point of interrupt +@ STMDB sp!, {r0, r10, r12, lr} @ Store other scratch registers +@ BL _tx_thread_vectored_context_save @ Vectored context save +@ +@ /* At this point execution is still in the IRQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. In +@ addition, IRQ interrupts may be re-enabled - with certain restrictions - +@ if nested IRQ interrupts are desired. Interrupts may be re-enabled over +@ small code sequences where lr is saved before enabling interrupts and +@ restored after interrupts are again disabled. */ +@ +@ +@ /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +@ from IRQ mode with interrupts disabled. This routine switches to the +@ system mode and returns with IRQ interrupts enabled. +@ +@ NOTE: It is very important to ensure all IRQ interrupts are cleared +@ prior to enabling nested IRQ interrupts. */ +@#ifdef TX_ENABLE_IRQ_NESTING +@ BL _tx_thread_irq_nesting_start +@#endif +@ +@ /* Application IRQ handlers can be called here! */ +@ +@ /* If interrupt nesting was started earlier, the end of interrupt nesting +@ service must be called before returning to _tx_thread_context_restore. +@ This routine returns in processing in IRQ mode with interrupts disabled. */ +@#ifdef TX_ENABLE_IRQ_NESTING +@ BL _tx_thread_irq_nesting_end +@#endif +@ +@ /* Jump to context restore to restore system context. */ +@ B _tx_thread_context_restore +@ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + .global __tx_fiq_handler + .global __tx_fiq_processing_return +__tx_fiq_handler: +@ +@ /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +@ +@ /* At this point execution is still in the FIQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. */ +@ +@ /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +@ from FIQ mode with interrupts disabled. This routine switches to the +@ system mode and returns with FIQ interrupts enabled. +@ +@ NOTE: It is very important to ensure all FIQ interrupts are cleared +@ prior to enabling nested FIQ interrupts. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_start +#endif +@ +@ /* Application FIQ handlers can be called here! */ +@ +@ /* If interrupt nesting was started earlier, the end of interrupt nesting +@ service must be called before returning to _tx_thread_fiq_context_restore. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_end +#endif +@ +@ /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore +@ +@ +#else + .global __tx_fiq_handler +__tx_fiq_handler: + B __tx_fiq_handler @ FIQ interrupt handler +#endif +@ +@ +BUILD_OPTIONS: + .word _tx_build_options @ Reference to bring in +VERSION_ID: + .word _tx_version_id @ Reference to bring in + + + diff --git a/ports/cortex_a9/ac6/example_build/tx/.cproject b/ports/cortex_a9/ac6/example_build/tx/.cproject new file mode 100644 index 00000000..8aeecb9f --- /dev/null +++ b/ports/cortex_a9/ac6/example_build/tx/.cproject @@ -0,0 +1,212 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_a9/ac6/example_build/tx/.project b/ports/cortex_a9/ac6/example_build/tx/.project new file mode 100644 index 00000000..863ca5cb --- /dev/null +++ b/ports/cortex_a9/ac6/example_build/tx/.project @@ -0,0 +1,48 @@ + + + tx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + inc_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/inc + + + inc_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/inc + + + src_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/src + + + src_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/src + + + diff --git a/ports/cortex_a9/ac6/example_build/tx/.settings/language.settings.xml b/ports/cortex_a9/ac6/example_build/tx/.settings/language.settings.xml new file mode 100644 index 00000000..b475702e --- /dev/null +++ b/ports/cortex_a9/ac6/example_build/tx/.settings/language.settings.xml @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_a9/ac6/inc/tx_port.h b/ports/cortex_a9/ac6/inc/tx_port.h new file mode 100644 index 00000000..94990c28 --- /dev/null +++ b/ports/cortex_a9/ac6/inc/tx_port.h @@ -0,0 +1,323 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A9/AC6 */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#if __TARGET_ARCH_ARM > 4 + +#ifndef __thumb__ + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + asm volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); \ + b = 31 - b; +#endif +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifdef __thumb__ + +unsigned int _tx_thread_interrupt_disable(void); +unsigned int _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save, tx_temp; + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); +#else +#define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID i ": "=r" (interrupt_save) ); +#endif + +#define TX_RESTORE asm volatile (" MSR CPSR_c,%0 "::"r" (interrupt_save) ); + +#endif + + +/* Define VFP extension for the Cortex-A9. Each is assumed to be called in the context of the executing + thread. */ + +void tx_thread_vfp_enable(void); +void tx_thread_vfp_disable(void); + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A9/AC6 Version 6.0.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + diff --git a/ports/cortex_a9/ac6/readme_threadx.txt b/ports/cortex_a9/ac6/readme_threadx.txt new file mode 100644 index 00000000..1360697d --- /dev/null +++ b/ports/cortex_a9/ac6/readme_threadx.txt @@ -0,0 +1,342 @@ + Microsoft's Azure RTOS ThreadX for Cortex-A9 + + Using ARM Compiler 6 & DS + +1. Import the ThreadX Projects + +In order to build the ThreadX library and the ThreadX demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +into your DS workspace. + + +2. Building the ThreadX run-time Library + +Building the ThreadX library is easy; simply right-click the Eclipse project +"tx" and then select the "Build Project" button. You should now observe the compilation +and assembly of the ThreadX library. This project build produces the ThreadX +library file tx.a. + + +3. Demonstration System + +The ThreadX demonstration is designed to execute under the DS debugger on the +VE_Cortex-A9 Bare Metal simulator. + +Building the demonstration is easy; simply right-click the Eclipse project +"sample_threadx" and then select the "Build Project" button. You should now observe +the compilation and assembly of the ThreadX demonstration. This project build produces +the ThreadX library file sample_threadx.axf. Next, expand the demo ThreadX project folder +in the Project Explorer window, right-click on the 'cortex-a9_tx.launch' file, click +'Debug As', and then click 'cortex-a9_tx' from the submenu. This will cause the +debugger to load the sample_threadx.axf ELF file and run to main. You are now ready +to execute the ThreadX demonstration. + + +4. System Initialization + +The entry point in ThreadX for the Cortex-A9 using ARM tools is at label +"Vectors". This is defined within startup.S in the sample_threadx project. In addition, +this is where all static and global pre-set C variable initialization processing +takes place. + +This is also where initialization of a periodic timer interrupt source should take +place. + +In addition, _tx_initialize_low_level defines the first available address +for use by the application, which is supplied as the sole input parameter +to your application definition function, tx_application_define. + + +5. Register Usage and Stack Frames + +The AC6 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread +is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 CPSR CPSR + 0x08 r0 (a1) a9 (v1) + 0x0C r1 (a2) r5 (v2) + 0x10 r2 (a3) r6 (v3) + 0x14 r3 (a4) r7 (v4) + 0x18 a9 (v1) r8 (v5) + 0x1C r5 (v2) r9 (v6) + 0x20 r6 (v3) r10 (v7) + 0x24 r7 (v4) r11 (fp) + 0x28 r8 (v5) r14 (lr) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) + 0x3C r14 (lr) + 0x40 PC + + +6. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-A9 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +7.1 Vector Area + +The Cortex-A9 vectors start at address zero. The demonstration system startup +reset.S file contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. + + +7.2 IRQ ISRs + +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports +nested IRQ interrupts. The following sub-sections define the IRQ capabilities. + + +7.2.1 Standard IRQ ISRs + +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +is the default IRQ handler defined in tx_initialize_low_level.S: + + .global __tx_irq_handler + .global __tx_irq_processing_return +__tx_irq_handler: +@ +@ /* Jump to context save to save system context. */ + B _tx_thread_context_save @ Jump to the context save +__tx_irq_processing_return: +@ +@ /* At this point execution is still in the IRQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. Note +@ that IRQ interrupts are still disabled upon return from the context +@ save function. */ +@ +@ /* Application ISR call(s) go here! */ +@ +@ /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.2 Vectored IRQ ISRs + +The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified +by the particular implementation. The following is an example IRQ handler defined in +tx_initialize_low_level.S: + + .global __tx_irq_example_handler +__tx_irq_example_handler: +@ +@ /* Call context save to save system context. */ + + STMDB sp!, {r0-r3} @ Save some scratch registers + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} @ Store other scratch registers + BL _tx_thread_vectored_context_save @ Call the vectored IRQ context save +@ +@ /* At this point execution is still in the IRQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. Note +@ that IRQ interrupts are still disabled upon return from the context +@ save function. */ +@ +@ /* Application ISR call goes here! */ +@ +@ /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.3 Nested IRQ Support + +By default, nested IRQ interrupt support is not enabled. To enable nested +IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING +defined. With this defined, two new IRQ interrupt management services are +available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. +These function should be called between the IRQ context save and restore +calls. + +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +by switching from IRQ mode to SYS mode and enabling IRQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.S. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in +preparation for the IRQ context restore service. + +The following is an example of enabling IRQ nested interrupts in a standard +IRQ handler: + + .global __tx_irq_handler + .global __tx_irq_processing_return +__tx_irq_handler: +@ +@ /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return: +@ +@ /* Enable nested IRQ interrupts. NOTE: Since this service returns +@ with IRQ interrupts enabled, all IRQ interrupt sources must be +@ cleared prior to calling this service. */ + BL _tx_thread_irq_nesting_start +@ +@ /* Application ISR call(s) go here! */ +@ +@ /* Disable nested IRQ interrupts. The mode is switched back to +@ IRQ mode and IRQ interrupts are disable upon return. */ + BL _tx_thread_irq_nesting_end +@ +@ /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.3 FIQ Interrupts + +By default, FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made +from default FIQ ISRs, which is located in tx_initialize_low_level.S. + + +7.3.1 Managed FIQ Interrupts + +Full ThreadX management of FIQ interrupts is provided if the ThreadX sources +are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built +this way, the FIQ interrupt handlers are very similar to the IRQ interrupt +handlers defined previously. The following is default FIQ handler +defined in tx_initialize_low_level.S: + + + .global __tx_fiq_handler + .global __tx_fiq_processing_return +__tx_fiq_handler: +@ +@ /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +@ +@ /* At this point execution is still in the FIQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. */ +@ +@ /* Application FIQ handlers can be called here! */ +@ +@ /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +7.3.1.1 Nested FIQ Support + +By default, nested FIQ interrupt support is not enabled. To enable nested +FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING +defined. With this defined, two new FIQ interrupt management services are +available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. +These function should be called between the FIQ context save and restore +calls. + +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +by switching from FIQ mode to SYS mode and enabling FIQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.S. When nested FIQ interrupts are no longer required, +calling the _tx_thread_fiq_nesting_end service disables nesting by disabling +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +context restore service. + +The following is an example of enabling FIQ nested interrupts in the +typical FIQ handler: + + + .global __tx_fiq_handler + .global __tx_fiq_processing_return +__tx_fiq_handler: +@ +@ /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +@ +@ /* At this point execution is still in the FIQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. */ +@ +@ /* Enable nested FIQ interrupts. NOTE: Since this service returns +@ with FIQ interrupts enabled, all FIQ interrupt sources must be +@ cleared prior to calling this service. */ + BL _tx_thread_fiq_nesting_start +@ +@ /* Application FIQ handlers can be called here! */ +@ +@ /* Disable nested FIQ interrupts. The mode is switched back to +@ FIQ mode and FIQ interrupts are disable upon return. */ + BL _tx_thread_fiq_nesting_end +@ +@ /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +8. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional but the remainder of +ThreadX will still run. + +To add the timer interrupt processing, simply make a call to +_tx_timer_interrupt in the IRQ processing. An example of this can be +found in the file tx_initialize_low_level.S for the demonstration system. + + +9. VFP Support + +By default, VFP support is disabled for each thread. If saving the context of the VFP registers +is needed, the following API call must be made from the context of the application thread - before +the VFP usage: + +void tx_thread_vfp_enable(void); + +After this API is called in the application, VFP registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the VFP registers +to be saved/restored. + +To disable VFP register context saving, simply call the following API: + +void tx_thread_vfp_disable(void); + + +10. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A9 using AC6 tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_a9/ac6/src/tx_thread_context_restore.S b/ports/cortex_a9/ac6/src/tx_thread_context_restore.S new file mode 100644 index 00000000..b710b81c --- /dev/null +++ b/ports/cortex_a9/ac6/src/tx_thread_context_restore.S @@ -0,0 +1,256 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ + .arm + +#ifdef TX_ENABLE_FIQ_SUPPORT +SVC_MODE = 0xD3 @ Disable IRQ/FIQ, SVC mode +IRQ_MODE = 0xD2 @ Disable IRQ/FIQ, IRQ mode +#else +SVC_MODE = 0x93 @ Disable IRQ, SVC mode +IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode +#endif +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_restore Cortex-A9/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function restores the interrupt context if it is processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs Interrupt Service Routines */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_restore(VOID) +@{ + .global _tx_thread_context_restore + .type _tx_thread_context_restore,function +_tx_thread_context_restore: +@ +@ /* Lockout interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR exit function to indicate an ISR is complete. */ +@ + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif +@ +@ /* Determine if interrupts are nested. */ +@ if (--_tx_thread_system_state) +@ { +@ + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + SUB r2, r2, #1 @ Decrement the counter + STR r2, [r3] @ Store the counter + CMP r2, #0 @ Was this the first interrupt? + BEQ __tx_thread_not_nested_restore @ If so, not a nested restore +@ +@ /* Interrupts are nested. */ +@ +@ /* Just recover the saved registers and return to the point of +@ interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +__tx_thread_not_nested_restore: +@ +@ /* Determine if a thread was interrupted and no preemption is required. */ +@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +@ || (_tx_thread_preempt_disable)) +@ { +@ + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup actual current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_restore @ Yes, idle system was interrupted +@ + LDR r3, =_tx_thread_preempt_disable @ Pickup preempt disable address + LDR r2, [r3] @ Pickup actual preempt disable flag + CMP r2, #0 @ Is it set? + BNE __tx_thread_no_preempt_restore @ Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr @ Pickup address of execute thread ptr + LDR r2, [r3] @ Pickup actual execute thread pointer + CMP r0, r2 @ Is the same thread highest priority? + BNE __tx_thread_preempt_restore @ No, preemption needs to happen +@ +@ +__tx_thread_no_preempt_restore: +@ +@ /* Restore interrupted thread or ISR. */ +@ +@ /* Pickup the saved stack pointer. */ +@ tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +@ +@ /* Recover the saved context and return to the point of interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +@ else +@ { +__tx_thread_preempt_restore: +@ + LDMIA sp!, {r3, r10, r12, lr} @ Recover temporarily saved registers + MOV r1, lr @ Save lr (point of interrupt) + MOV r2, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r2 @ Enter SVC mode + STR r1, [sp, #-4]! @ Save point of interrupt + STMDB sp!, {r4-r12, lr} @ Save upper half of registers + MOV r4, r3 @ Save SPSR in r4 + MOV r2, #IRQ_MODE @ Build IRQ mode CPSR + MSR CPSR_c, r2 @ Enter IRQ mode + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOV r5, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r5 @ Enter SVC mode + STMDB sp!, {r0-r3} @ Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r2, [r0, #144] @ Pickup the VFP enabled flag + CMP r2, #0 @ Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save @ No, skip VFP IRQ save + VMRS r2, FPSCR @ Pickup the FPSCR + STR r2, [sp, #-4]! @ Save FPSCR + VSTMDB sp!, {D16-D31} @ Save D16-D31 + VSTMDB sp!, {D0-D15} @ Save D0-D15 +_tx_skip_irq_vfp_save: +#endif + + MOV r3, #1 @ Build interrupt stack type + STMDB sp!, {r3, r4} @ Save interrupt stack type and SPSR + STR sp, [r0, #8] @ Save stack pointer in thread control + @ block +@ +@ /* Save the remaining time-slice and disable it. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup time-slice variable address + LDR r2, [r3] @ Pickup time-slice + CMP r2, #0 @ Is it active? + BEQ __tx_thread_dont_save_ts @ No, don't save it +@ +@ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +@ _tx_timer_time_slice = 0; +@ + STR r2, [r0, #24] @ Save thread's time-slice + MOV r2, #0 @ Clear value + STR r2, [r3] @ Disable global time-slice flag +@ +@ } +__tx_thread_dont_save_ts: +@ +@ +@ /* Clear the current task pointer. */ +@ _tx_thread_current_ptr = TX_NULL; +@ + MOV r0, #0 @ NULL value + STR r0, [r1] @ Clear current thread pointer +@ +@ /* Return to the scheduler. */ +@ _tx_thread_schedule(); +@ + B _tx_thread_schedule @ Return to scheduler +@ } +@ +__tx_thread_idle_system_restore: +@ +@ /* Just return back to the scheduler! */ +@ + MOV r0, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r0 @ Enter SVC mode + B _tx_thread_schedule @ Return to scheduler +@} + + + diff --git a/ports/cortex_a9/ac6/src/tx_thread_context_save.S b/ports/cortex_a9/ac6/src/tx_thread_context_save.S new file mode 100644 index 00000000..112b0961 --- /dev/null +++ b/ports/cortex_a9/ac6/src/tx_thread_context_save.S @@ -0,0 +1,202 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global __tx_irq_processing_return +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_save Cortex-A9/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_save(VOID) +@{ + .global _tx_thread_context_save + .type _tx_thread_context_save,function +_tx_thread_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state++) +@ { +@ + STMDB sp!, {r0-r3} @ Save some working registers +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable FIQ interrupts +#endif + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable +@ +@ /* Save the rest of the scratch registers on the stack and return to the +@ calling ISR. */ +@ + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} @ Store other registers +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_irq_processing_return @ Continue IRQ processing +@ +__tx_thread_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + @ scheduling loop - nothing needs saving! +@ +@ /* Save minimal context of interrupted thread. */ +@ + MRS r2, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r2, r10, r12, lr} @ Store other registers +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr@ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_irq_processing_return @ Continue IRQ processing +@ +@ } +@ else +@ { +@ +__tx_thread_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ processing. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + ADD sp, sp, #16 @ Recover saved registers + B __tx_irq_processing_return @ Continue IRQ processing +@ +@ } +@} + + + diff --git a/ports/cortex_a9/ac6/src/tx_thread_fiq_context_restore.S b/ports/cortex_a9/ac6/src/tx_thread_fiq_context_restore.S new file mode 100644 index 00000000..36d0e349 --- /dev/null +++ b/ports/cortex_a9/ac6/src/tx_thread_fiq_context_restore.S @@ -0,0 +1,259 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ +SVC_MODE = 0xD3 @ SVC mode +FIQ_MODE = 0xD1 @ FIQ mode +MODE_MASK = 0x1F @ Mode mask +THUMB_MASK = 0x20 @ Thumb bit mask +IRQ_MODE_BITS = 0x12 @ IRQ mode bits +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_system_stack_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_context_restore +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_context_restore Cortex-A9/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function restores the fiq interrupt context when processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* FIQ ISR Interrupt Service Routines */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_fiq_context_restore(VOID) +@{ + .global _tx_thread_fiq_context_restore + .type _tx_thread_fiq_context_restore,function +_tx_thread_fiq_context_restore: +@ +@ /* Lockout interrupts. */ +@ + CPSID if @ Disable IRQ and FIQ interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR exit function to indicate an ISR is complete. */ +@ + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif +@ +@ /* Determine if interrupts are nested. */ +@ if (--_tx_thread_system_state) +@ { +@ + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + SUB r2, r2, #1 @ Decrement the counter + STR r2, [r3] @ Store the counter + CMP r2, #0 @ Was this the first interrupt? + BEQ __tx_thread_fiq_not_nested_restore @ If so, not a nested restore +@ +@ /* Interrupts are nested. */ +@ +@ /* Just recover the saved registers and return to the point of +@ interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +__tx_thread_fiq_not_nested_restore: +@ +@ /* Determine if a thread was interrupted and no preemption is required. */ +@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +@ || (_tx_thread_preempt_disable)) +@ { +@ + LDR r1, [sp] @ Pickup the saved SPSR + MOV r2, #MODE_MASK @ Build mask to isolate the interrupted mode + AND r1, r1, r2 @ Isolate mode bits + CMP r1, #IRQ_MODE_BITS @ Was an interrupt taken in IRQ mode before we + @ got to context save? */ + BEQ __tx_thread_fiq_no_preempt_restore @ Yes, just go back to point of interrupt + + + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup actual current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_fiq_idle_system_restore @ Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable @ Pickup preempt disable address + LDR r2, [r3] @ Pickup actual preempt disable flag + CMP r2, #0 @ Is it set? + BNE __tx_thread_fiq_no_preempt_restore @ Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr @ Pickup address of execute thread ptr + LDR r2, [r3] @ Pickup actual execute thread pointer + CMP r0, r2 @ Is the same thread highest priority? + BNE __tx_thread_fiq_preempt_restore @ No, preemption needs to happen + + +__tx_thread_fiq_no_preempt_restore: +@ +@ /* Restore interrupted thread or ISR. */ +@ +@ /* Pickup the saved stack pointer. */ +@ tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +@ +@ /* Recover the saved context and return to the point of interrupt. */ +@ + LDMIA sp!, {r0, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +@ else +@ { +__tx_thread_fiq_preempt_restore: +@ + LDMIA sp!, {r3, lr} @ Recover temporarily saved registers + MOV r1, lr @ Save lr (point of interrupt) + MOV r2, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r2 @ Enter SVC mode + STR r1, [sp, #-4]! @ Save point of interrupt + STMDB sp!, {r4-r12, lr} @ Save upper half of registers + MOV r4, r3 @ Save SPSR in r4 + MOV r2, #FIQ_MODE @ Build FIQ mode CPSR + MSR CPSR_c, r2 @ Reenter FIQ mode + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOV r5, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r5 @ Enter SVC mode + STMDB sp!, {r0-r3} @ Save r0-r3 on thread's stack + + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r2, [r0, #144] @ Pickup the VFP enabled flag + CMP r2, #0 @ Is the VFP enabled? + BEQ _tx_skip_fiq_vfp_save @ No, skip VFP IRQ save + VMRS r2, FPSCR @ Pickup the FPSCR + STR r2, [sp, #-4]! @ Save FPSCR + VSTMDB sp!, {D16-D31} @ Save D16-D31 + VSTMDB sp!, {D0-D15} @ Save D0-D15 +_tx_skip_fiq_vfp_save: +#endif + + MOV r3, #1 @ Build interrupt stack type + STMDB sp!, {r3, r4} @ Save interrupt stack type and SPSR + STR sp, [r0, #8] @ Save stack pointer in thread control + @ block */ +@ +@ /* Save the remaining time-slice and disable it. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup time-slice variable address + LDR r2, [r3] @ Pickup time-slice + CMP r2, #0 @ Is it active? + BEQ __tx_thread_fiq_dont_save_ts @ No, don't save it +@ +@ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +@ _tx_timer_time_slice = 0; +@ + STR r2, [r0, #24] @ Save thread's time-slice + MOV r2, #0 @ Clear value + STR r2, [r3] @ Disable global time-slice flag +@ +@ } +__tx_thread_fiq_dont_save_ts: +@ +@ +@ /* Clear the current task pointer. */ +@ _tx_thread_current_ptr = TX_NULL; +@ + MOV r0, #0 @ NULL value + STR r0, [r1] @ Clear current thread pointer +@ +@ /* Return to the scheduler. */ +@ _tx_thread_schedule(); +@ + B _tx_thread_schedule @ Return to scheduler +@ } +@ +__tx_thread_fiq_idle_system_restore: +@ +@ /* Just return back to the scheduler! */ +@ + ADD sp, sp, #24 @ Recover FIQ stack space + MOV r3, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r3 @ Lockout interrupts + B _tx_thread_schedule @ Return to scheduler +@ +@} + diff --git a/ports/cortex_a9/ac6/src/tx_thread_fiq_context_save.S b/ports/cortex_a9/ac6/src/tx_thread_fiq_context_save.S new file mode 100644 index 00000000..0798ff9b --- /dev/null +++ b/ports/cortex_a9/ac6/src/tx_thread_fiq_context_save.S @@ -0,0 +1,203 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global __tx_fiq_processing_return +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_context_save +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_context_save Cortex-A9/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@ VOID _tx_thread_fiq_context_save(VOID) +@{ + .global _tx_thread_fiq_context_save + .type _tx_thread_fiq_context_save,function +_tx_thread_fiq_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state++) +@ { +@ + STMDB sp!, {r0-r3} @ Save some working registers + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_fiq_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable +@ +@ /* Save the rest of the scratch registers on the stack and return to the +@ calling ISR. */ +@ + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} @ Store other registers +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_fiq_processing_return @ Continue FIQ processing +@ +__tx_thread_fiq_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_fiq_idle_system_save @ If so, interrupt occurred in +@ @ scheduling loop - nothing needs saving! +@ +@ /* Save minimal context of interrupted thread. */ +@ + MRS r2, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r2, lr} @ Store other registers, Note that we don't +@ @ need to save sl and ip since FIQ has +@ @ copies of these registers. Nested +@ @ interrupt processing does need to save +@ @ these registers. +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr; +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_fiq_processing_return @ Continue FIQ processing +@ +@ } +@ else +@ { +@ +__tx_thread_fiq_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif +@ +@ /* Not much to do here, save the current SPSR and LR for possible +@ use in IRQ interrupted in idle system conditions, and return to +@ FIQ interrupt processing. */ +@ + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, lr} @ Store other registers that will get used +@ @ or stripped off the stack in context +@ @ restore + B __tx_fiq_processing_return @ Continue FIQ processing +@ +@ } +@} + diff --git a/ports/cortex_a9/ac6/src/tx_thread_fiq_nesting_end.S b/ports/cortex_a9/ac6/src/tx_thread_fiq_nesting_end.S new file mode 100644 index 00000000..c5f1913d --- /dev/null +++ b/ports/cortex_a9/ac6/src/tx_thread_fiq_nesting_end.S @@ -0,0 +1,116 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts +#else +DISABLE_INTS = 0x80 @ Disable IRQ interrupts +#endif +MODE_MASK = 0x1F @ Mode mask +FIQ_MODE_BITS = 0x11 @ FIQ mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_end +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_nesting_end Cortex-A9/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from FIQ mode after */ +@/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +@/* processing from system mode back to FIQ mode prior to the ISR */ +@/* calling _tx_thread_fiq_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with FIQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_fiq_nesting_end(VOID) +@{ + .global _tx_thread_fiq_nesting_end + .type _tx_thread_fiq_nesting_end,function +_tx_thread_fiq_nesting_end: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value + MSR CPSR_c, r0 @ Disable interrupts + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + @ 8-byte alignment logic) + BIC r0, r0, #MODE_MASK @ Clear mode bits + ORR r0, r0, #FIQ_MODE_BITS @ Build IRQ mode CPSR + MSR CPSR_c, r0 @ Reenter IRQ mode + +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_a9/ac6/src/tx_thread_fiq_nesting_start.S b/ports/cortex_a9/ac6/src/tx_thread_fiq_nesting_start.S new file mode 100644 index 00000000..51153ce4 --- /dev/null +++ b/ports/cortex_a9/ac6/src/tx_thread_fiq_nesting_start.S @@ -0,0 +1,108 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +FIQ_DISABLE = 0x40 @ FIQ disable bit +MODE_MASK = 0x1F @ Mode mask +SYS_MODE_BITS = 0x1F @ System mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_start +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_nesting_start Cortex-A9/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from FIQ mode after */ +@/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +@/* processing to the system mode so nested FIQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with FIQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_fiq_nesting_start(VOID) +@{ + .global _tx_thread_fiq_nesting_start + .type _tx_thread_fiq_nesting_start,function +_tx_thread_fiq_nesting_start: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + BIC r0, r0, #MODE_MASK @ Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS @ Build system mode CPSR + MSR CPSR_c, r0 @ Enter system mode + STMDB sp!, {r1, lr} @ Push the system mode lr on the system mode stack + @ and push r1 just to keep 8-byte alignment + BIC r0, r0, #FIQ_DISABLE @ Build enable FIQ CPSR + MSR CPSR_c, r0 @ Enter system mode +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_a9/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_a9/ac6/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..95eab866 --- /dev/null +++ b/ports/cortex_a9/ac6/src/tx_thread_interrupt_control.S @@ -0,0 +1,115 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" */ +@ + +INT_MASK = 0x03F + +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_control for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_interrupt_control +$_tx_thread_interrupt_control: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_interrupt_control @ Call _tx_thread_interrupt_control function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_control Cortex-A9/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for changing the interrupt lockout */ +@/* posture of the system. */ +@/* */ +@/* INPUT */ +@/* */ +@/* new_posture New interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_control(UINT new_posture) +@{ + .global _tx_thread_interrupt_control + .type _tx_thread_interrupt_control,function +_tx_thread_interrupt_control: +@ +@ /* Pickup current interrupt lockout posture. */ +@ + MRS r3, CPSR @ Pickup current CPSR + MOV r2, #INT_MASK @ Build interrupt mask + AND r1, r3, r2 @ Clear interrupt lockout bits + ORR r1, r1, r0 @ Or-in new interrupt lockout bits +@ +@ /* Apply the new interrupt posture. */ +@ + MSR CPSR_c, r1 @ Setup new CPSR + BIC r0, r3, r2 @ Return previous interrupt mask +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + diff --git a/ports/cortex_a9/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_a9/ac6/src/tx_thread_interrupt_disable.S new file mode 100644 index 00000000..2e2e6268 --- /dev/null +++ b/ports/cortex_a9/ac6/src/tx_thread_interrupt_disable.S @@ -0,0 +1,113 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_interrupt_disable +$_tx_thread_interrupt_disable: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_interrupt_disable @ Call _tx_thread_interrupt_disable function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_disable Cortex-A9/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for disabling interrupts */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_disable(void) +@{ + .global _tx_thread_interrupt_disable + .type _tx_thread_interrupt_disable,function +_tx_thread_interrupt_disable: +@ +@ /* Pickup current interrupt lockout posture. */ +@ + MRS r0, CPSR @ Pickup current CPSR +@ +@ /* Mask interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ +#else + CPSID i @ Disable IRQ +#endif + +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + + diff --git a/ports/cortex_a9/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_a9/ac6/src/tx_thread_interrupt_restore.S new file mode 100644 index 00000000..dcc6ccfd --- /dev/null +++ b/ports/cortex_a9/ac6/src/tx_thread_interrupt_restore.S @@ -0,0 +1,104 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_interrupt_restore +$_tx_thread_interrupt_restore: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_interrupt_restore @ Call _tx_thread_interrupt_restore function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_restore Cortex-A9/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for restoring interrupts to the state */ +@/* returned by a previous _tx_thread_interrupt_disable call. */ +@/* */ +@/* INPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_restore(UINT old_posture) +@{ + .global _tx_thread_interrupt_restore + .type _tx_thread_interrupt_restore,function +_tx_thread_interrupt_restore: +@ +@ /* Apply the new interrupt posture. */ +@ + MSR CPSR_c, r0 @ Setup new CPSR +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + diff --git a/ports/cortex_a9/ac6/src/tx_thread_irq_nesting_end.S b/ports/cortex_a9/ac6/src/tx_thread_irq_nesting_end.S new file mode 100644 index 00000000..5c9a6fea --- /dev/null +++ b/ports/cortex_a9/ac6/src/tx_thread_irq_nesting_end.S @@ -0,0 +1,115 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts +#else +DISABLE_INTS = 0x80 @ Disable IRQ interrupts +#endif +MODE_MASK = 0x1F @ Mode mask +IRQ_MODE_BITS = 0x12 @ IRQ mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_end +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_end Cortex-A9/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +@/* processing from system mode back to IRQ mode prior to the ISR */ +@/* calling _tx_thread_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_irq_nesting_end(VOID) +@{ + .global _tx_thread_irq_nesting_end + .type _tx_thread_irq_nesting_end,function +_tx_thread_irq_nesting_end: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value + MSR CPSR_c, r0 @ Disable interrupts + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + @ 8-byte alignment logic) + BIC r0, r0, #MODE_MASK @ Clear mode bits + ORR r0, r0, #IRQ_MODE_BITS @ Build IRQ mode CPSR + MSR CPSR_c, r0 @ Reenter IRQ mode +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_a9/ac6/src/tx_thread_irq_nesting_start.S b/ports/cortex_a9/ac6/src/tx_thread_irq_nesting_start.S new file mode 100644 index 00000000..19b76019 --- /dev/null +++ b/ports/cortex_a9/ac6/src/tx_thread_irq_nesting_start.S @@ -0,0 +1,108 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +IRQ_DISABLE = 0x80 @ IRQ disable bit +MODE_MASK = 0x1F @ Mode mask +SYS_MODE_BITS = 0x1F @ System mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_start +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_start Cortex-A9/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_context_save has been called and switches the IRQ */ +@/* processing to the system mode so nested IRQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_irq_nesting_start(VOID) +@{ + .global _tx_thread_irq_nesting_start + .type _tx_thread_irq_nesting_start,function +_tx_thread_irq_nesting_start: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + BIC r0, r0, #MODE_MASK @ Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS @ Build system mode CPSR + MSR CPSR_c, r0 @ Enter system mode + STMDB sp!, {r1, lr} @ Push the system mode lr on the system mode stack + @ and push r1 just to keep 8-byte alignment + BIC r0, r0, #IRQ_DISABLE @ Build enable IRQ CPSR + MSR CPSR_c, r0 @ Enter system mode +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_a9/ac6/src/tx_thread_schedule.S b/ports/cortex_a9/ac6/src/tx_thread_schedule.S new file mode 100644 index 00000000..c3f6e260 --- /dev/null +++ b/ports/cortex_a9/ac6/src/tx_thread_schedule.S @@ -0,0 +1,254 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_execute_ptr + .global _tx_thread_current_ptr + .global _tx_timer_time_slice +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_schedule for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_schedule + .type $_tx_thread_schedule,function +$_tx_thread_schedule: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_schedule @ Call _tx_thread_schedule function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_schedule Cortex-A9/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function waits for a thread control block pointer to appear in */ +@/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +@/* in the variable, the corresponding thread is resumed. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* _tx_thread_system_return Return to system from thread */ +@/* _tx_thread_context_restore Restore thread's context */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_schedule(VOID) +@{ + .global _tx_thread_schedule + .type _tx_thread_schedule,function +_tx_thread_schedule: +@ +@ /* Enable interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSIE if @ Enable IRQ and FIQ interrupts +#else + CPSIE i @ Enable IRQ interrupts +#endif +@ +@ /* Wait for a thread to execute. */ +@ do +@ { + LDR r1, =_tx_thread_execute_ptr @ Address of thread execute ptr +@ +__tx_thread_schedule_loop: +@ + LDR r0, [r1] @ Pickup next thread to execute + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_schedule_loop @ If so, keep looking for a thread +@ +@ } +@ while(_tx_thread_execute_ptr == TX_NULL); +@ +@ /* Yes! We have a thread to execute. Lockout interrupts and +@ transfer control to it. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif +@ +@ /* Setup the current thread pointer. */ +@ _tx_thread_current_ptr = _tx_thread_execute_ptr; +@ + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread + STR r0, [r1] @ Setup current thread pointer +@ +@ /* Increment the run count for this thread. */ +@ _tx_thread_current_ptr -> tx_thread_run_count++; +@ + LDR r2, [r0, #4] @ Pickup run counter + LDR r3, [r0, #24] @ Pickup time-slice for this thread + ADD r2, r2, #1 @ Increment thread run-counter + STR r2, [r0, #4] @ Store the new run counter +@ +@ /* Setup time-slice, if present. */ +@ _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; +@ + LDR r2, =_tx_timer_time_slice @ Pickup address of time-slice + @ variable + LDR sp, [r0, #8] @ Switch stack pointers + STR r3, [r2] @ Setup time-slice +@ +@ /* Switch to the thread's stack. */ +@ sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; +@ +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the thread entry function to indicate the thread is executing. */ +@ + MOV r5, r0 @ Save r0 + BL _tx_execution_thread_enter @ Call the thread execution enter function + MOV r0, r5 @ Restore r0 +#endif +@ +@ /* Determine if an interrupt frame or a synchronous task suspension frame +@ is present. */ +@ + LDMIA sp!, {r4, r5} @ Pickup the stack type and saved CPSR + CMP r4, #0 @ Check for synchronous context switch + BEQ _tx_solicited_return + MSR SPSR_cxsf, r5 @ Setup SPSR for return +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r1, [r0, #144] @ Pickup the VFP enabled flag + CMP r1, #0 @ Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore @ No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} @ Recover D0-D15 + VLDMIA sp!, {D16-D31} @ Recover D16-D31 + LDR r4, [sp], #4 @ Pickup FPSCR + VMSR FPSCR, r4 @ Restore FPSCR +_tx_skip_interrupt_vfp_restore: +#endif + LDMIA sp!, {r0-r12, lr, pc}^ @ Return to point of thread interrupt + +_tx_solicited_return: + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r1, [r0, #144] @ Pickup the VFP enabled flag + CMP r1, #0 @ Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore @ No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} @ Recover D8-D15 + VLDMIA sp!, {D16-D31} @ Recover D16-D31 + LDR r4, [sp], #4 @ Pickup FPSCR + VMSR FPSCR, r4 @ Restore FPSCR +_tx_skip_solicited_vfp_restore: +#endif + MSR CPSR_cxsf, r5 @ Recover CPSR + LDMIA sp!, {r4-r11, lr} @ Return to thread synchronously +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@ +@} +@ + +#ifdef TX_ENABLE_VFP_SUPPORT + + .global tx_thread_vfp_enable + .type tx_thread_vfp_enable,function +tx_thread_vfp_enable: + MRS r2, CPSR @ Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Enable IRQ and FIQ interrupts +#else + CPSID i @ Enable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address + LDR r1, [r0] @ Pickup current thread pointer + CMP r1, #0 @ Check for NULL thread pointer + BEQ __tx_no_thread_to_enable @ If NULL, skip VFP enable + MOV r0, #1 @ Build enable value + STR r0, [r1, #144] @ Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable: + MSR CPSR_cxsf, r2 @ Recover CPSR + BX LR @ Return to caller + + .global tx_thread_vfp_disable + .type tx_thread_vfp_disable,function +tx_thread_vfp_disable: + MRS r2, CPSR @ Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Enable IRQ and FIQ interrupts +#else + CPSID i @ Enable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address + LDR r1, [r0] @ Pickup current thread pointer + CMP r1, #0 @ Check for NULL thread pointer + BEQ __tx_no_thread_to_disable @ If NULL, skip VFP disable + MOV r0, #0 @ Build disable value + STR r0, [r1, #144] @ Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable: + MSR CPSR_cxsf, r2 @ Recover CPSR + BX LR @ Return to caller + +#endif + diff --git a/ports/cortex_a9/ac6/src/tx_thread_stack_build.S b/ports/cortex_a9/ac6/src/tx_thread_stack_build.S new file mode 100644 index 00000000..226a6586 --- /dev/null +++ b/ports/cortex_a9/ac6/src/tx_thread_stack_build.S @@ -0,0 +1,178 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ + .arm + +SVC_MODE = 0x13 @ SVC mode +#ifdef TX_ENABLE_FIQ_SUPPORT +CPSR_MASK = 0xDF @ Mask initial CPSR, IRQ & FIQ interrupts enabled +#else +CPSR_MASK = 0x9F @ Mask initial CPSR, IRQ interrupts enabled +#endif +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_stack_build for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .thumb + .global $_tx_thread_stack_build + .type $_tx_thread_stack_build,function +$_tx_thread_stack_build: + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_stack_build @ Call _tx_thread_stack_build function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_stack_build Cortex-A9/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function builds a stack frame on the supplied thread's stack. */ +@/* The stack frame results in a fake interrupt return to the supplied */ +@/* function pointer. */ +@/* */ +@/* INPUT */ +@/* */ +@/* thread_ptr Pointer to thread control blk */ +@/* function_ptr Pointer to return function */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_thread_create Create thread service */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +@{ + .global _tx_thread_stack_build + .type _tx_thread_stack_build,function +_tx_thread_stack_build: +@ +@ +@ /* Build a fake interrupt frame. The form of the fake interrupt stack +@ on the Cortex-A9 should look like the following after it is built: +@ +@ Stack Top: 1 Interrupt stack frame type +@ CPSR Initial value for CPSR +@ a1 (r0) Initial value for a1 +@ a2 (r1) Initial value for a2 +@ a3 (r2) Initial value for a3 +@ a4 (r3) Initial value for a4 +@ v1 (r4) Initial value for v1 +@ v2 (r5) Initial value for v2 +@ v3 (r6) Initial value for v3 +@ v4 (r7) Initial value for v4 +@ v5 (r8) Initial value for v5 +@ sb (r9) Initial value for sb +@ sl (r10) Initial value for sl +@ fp (r11) Initial value for fp +@ ip (r12) Initial value for ip +@ lr (r14) Initial value for lr +@ pc (r15) Initial value for pc +@ 0 For stack backtracing +@ +@ Stack Bottom: (higher memory address) */ +@ + LDR r2, [r0, #16] @ Pickup end of stack area + BIC r2, r2, #7 @ Ensure 8-byte alignment + SUB r2, r2, #76 @ Allocate space for the stack frame +@ +@ /* Actually build the stack frame. */ +@ + MOV r3, #1 @ Build interrupt stack type + STR r3, [r2, #0] @ Store stack type + MOV r3, #0 @ Build initial register value + STR r3, [r2, #8] @ Store initial r0 + STR r3, [r2, #12] @ Store initial r1 + STR r3, [r2, #16] @ Store initial r2 + STR r3, [r2, #20] @ Store initial r3 + STR r3, [r2, #24] @ Store initial r4 + STR r3, [r2, #28] @ Store initial r5 + STR r3, [r2, #32] @ Store initial r6 + STR r3, [r2, #36] @ Store initial r7 + STR r3, [r2, #40] @ Store initial r8 + STR r3, [r2, #44] @ Store initial r9 + LDR r3, [r0, #12] @ Pickup stack starting address + STR r3, [r2, #48] @ Store initial r10 (sl) + LDR r3,=_tx_thread_schedule @ Pickup address of _tx_thread_schedule for GDB backtrace + STR r3, [r2, #60] @ Store initial r14 (lr) + MOV r3, #0 @ Build initial register value + STR r3, [r2, #52] @ Store initial r11 + STR r3, [r2, #56] @ Store initial r12 + STR r1, [r2, #64] @ Store initial pc + STR r3, [r2, #68] @ 0 for back-trace + MRS r1, CPSR @ Pickup CPSR + BIC r1, r1, #CPSR_MASK @ Mask mode bits of CPSR + ORR r3, r1, #SVC_MODE @ Build CPSR, SVC mode, interrupts enabled + STR r3, [r2, #4] @ Store initial CPSR +@ +@ /* Setup stack pointer. */ +@ thread_ptr -> tx_thread_stack_ptr = r2; +@ + STR r2, [r0, #8] @ Save stack pointer in thread's + @ control block +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + + diff --git a/ports/cortex_a9/ac6/src/tx_thread_system_return.S b/ports/cortex_a9/ac6/src/tx_thread_system_return.S new file mode 100644 index 00000000..1b7bb949 --- /dev/null +++ b/ports/cortex_a9/ac6/src/tx_thread_system_return.S @@ -0,0 +1,179 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ + .arm +@ +@ + .global _tx_thread_current_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule +@ +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_system_return for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_system_return + .type $_tx_thread_system_return,function +$_tx_thread_system_return: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_system_return @ Call _tx_thread_system_return function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_system_return Cortex-A9/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is target processor specific. It is used to transfer */ +@/* control from a thread back to the ThreadX system. Only a */ +@/* minimal context is saved since the compiler assumes temp registers */ +@/* are going to get slicked by a function call anyway. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling loop */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX components */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_system_return(VOID) +@{ + .global _tx_thread_system_return + .type _tx_thread_system_return,function +_tx_thread_system_return: +@ +@ /* Save minimal context on the stack. */ +@ + STMDB sp!, {r4-r11, lr} @ Save minimal context + + LDR r4, =_tx_thread_current_ptr @ Pickup address of current ptr + LDR r5, [r4] @ Pickup current thread pointer + +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r1, [r5, #144] @ Pickup the VFP enabled flag + CMP r1, #0 @ Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save @ No, skip VFP solicited save + VMRS r1, FPSCR @ Pickup the FPSCR + STR r1, [sp, #-4]! @ Save FPSCR + VSTMDB sp!, {D16-D31} @ Save D16-D31 + VSTMDB sp!, {D8-D15} @ Save D8-D15 +_tx_skip_solicited_vfp_save: +#endif + + MOV r0, #0 @ Build a solicited stack type + MRS r1, CPSR @ Pickup the CPSR + STMDB sp!, {r0-r1} @ Save type and CPSR +@ +@ /* Lockout interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the thread exit function to indicate the thread is no longer executing. */ +@ + BL _tx_execution_thread_exit @ Call the thread exit function +#endif + MOV r3, r4 @ Pickup address of current ptr + MOV r0, r5 @ Pickup current thread pointer + LDR r2, =_tx_timer_time_slice @ Pickup address of time slice + LDR r1, [r2] @ Pickup current time slice +@ +@ /* Save current stack and switch to system stack. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ sp = _tx_thread_system_stack_ptr; +@ + STR sp, [r0, #8] @ Save thread stack pointer +@ +@ /* Determine if the time-slice is active. */ +@ if (_tx_timer_time_slice) +@ { +@ + MOV r4, #0 @ Build clear value + CMP r1, #0 @ Is a time-slice active? + BEQ __tx_thread_dont_save_ts @ No, don't save the time-slice +@ +@ /* Save time-slice for the thread and clear the current time-slice. */ +@ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +@ _tx_timer_time_slice = 0; +@ + STR r4, [r2] @ Clear time-slice + STR r1, [r0, #24] @ Save current time-slice +@ +@ } +__tx_thread_dont_save_ts: +@ +@ /* Clear the current thread pointer. */ +@ _tx_thread_current_ptr = TX_NULL; +@ + STR r4, [r3] @ Clear current thread pointer + B _tx_thread_schedule @ Jump to scheduler! +@ +@} + diff --git a/ports/cortex_a9/ac6/src/tx_thread_vectored_context_save.S b/ports/cortex_a9/ac6/src/tx_thread_vectored_context_save.S new file mode 100644 index 00000000..bc52d3ff --- /dev/null +++ b/ports/cortex_a9/ac6/src/tx_thread_vectored_context_save.S @@ -0,0 +1,189 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr +@ +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_vectored_context_save +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_vectored_context_save Cortex-A9/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_vectored_context_save(VOID) +@{ + .global _tx_thread_vectored_context_save + .type _tx_thread_vectored_context_save,function +_tx_thread_vectored_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state++) +@ { +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#endif + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3, #0] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3, #0] @ Store it back in the variable +@ +@ /* Note: Minimal context of interrupted thread is already saved. */ +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + MOV pc, lr @ Return to caller +@ +__tx_thread_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3, #0] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1, #0] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + @ scheduling loop - nothing needs saving! +@ +@ /* Note: Minimal context of interrupted thread is already saved. */ +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr; +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + MOV pc, lr @ Return to caller +@ +@ } +@ else +@ { +@ +__tx_thread_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ processing. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + ADD sp, sp, #32 @ Recover saved registers + MOV pc, lr @ Return to caller +@ +@ } +@} + diff --git a/ports/cortex_a9/ac6/src/tx_timer_interrupt.S b/ports/cortex_a9/ac6/src/tx_timer_interrupt.S new file mode 100644 index 00000000..06659120 --- /dev/null +++ b/ports/cortex_a9/ac6/src/tx_timer_interrupt.S @@ -0,0 +1,279 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Timer */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_timer.h" +@#include "tx_thread.h" +@ +@ + .arm + +@ +@/* Define Assembly language external references... */ +@ + .global _tx_timer_time_slice + .global _tx_timer_system_clock + .global _tx_timer_current_ptr + .global _tx_timer_list_start + .global _tx_timer_list_end + .global _tx_timer_expired_time_slice + .global _tx_timer_expired + .global _tx_thread_time_slice +@ +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_timer_interrupt for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .thumb + .global $_tx_timer_interrupt + .type $_tx_timer_interrupt,function +$_tx_timer_interrupt: + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_timer_interrupt @ Call _tx_timer_interrupt function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_timer_interrupt Cortex-A9/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function processes the hardware timer interrupt. This */ +@/* processing includes incrementing the system clock and checking for */ +@/* time slice and/or timer expiration. If either is found, the */ +@/* interrupt context save/restore functions are called along with the */ +@/* expiration functions. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_time_slice Time slice interrupted thread */ +@/* _tx_timer_expiration_process Timer expiration processing */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* interrupt vector */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_timer_interrupt(VOID) +@{ + .global _tx_timer_interrupt + .type _tx_timer_interrupt,function +_tx_timer_interrupt: +@ +@ /* Upon entry to this routine, it is assumed that context save has already +@ been called, and therefore the compiler scratch registers are available +@ for use. */ +@ +@ /* Increment the system clock. */ +@ _tx_timer_system_clock++; +@ + LDR r1, =_tx_timer_system_clock @ Pickup address of system clock + LDR r0, [r1] @ Pickup system clock + ADD r0, r0, #1 @ Increment system clock + STR r0, [r1] @ Store new system clock +@ +@ /* Test for time-slice expiration. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice + LDR r2, [r3] @ Pickup time-slice + CMP r2, #0 @ Is it non-active? + BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing +@ +@ /* Decrement the time_slice. */ +@ _tx_timer_time_slice--; +@ + SUB r2, r2, #1 @ Decrement the time-slice + STR r2, [r3] @ Store new time-slice value +@ +@ /* Check for expiration. */ +@ if (__tx_timer_time_slice == 0) +@ + CMP r2, #0 @ Has it expired? + BNE __tx_timer_no_time_slice @ No, skip expiration processing +@ +@ /* Set the time-slice expired flag. */ +@ _tx_timer_expired_time_slice = TX_TRUE; +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of expired flag + MOV r0, #1 @ Build expired value + STR r0, [r3] @ Set time-slice expiration flag +@ +@ } +@ +__tx_timer_no_time_slice: +@ +@ /* Test for timer expiration. */ +@ if (*_tx_timer_current_ptr) +@ { +@ + LDR r1, =_tx_timer_current_ptr @ Pickup current timer pointer address + LDR r0, [r1] @ Pickup current timer + LDR r2, [r0] @ Pickup timer list entry + CMP r2, #0 @ Is there anything in the list? + BEQ __tx_timer_no_timer @ No, just increment the timer +@ +@ /* Set expiration flag. */ +@ _tx_timer_expired = TX_TRUE; +@ + LDR r3, =_tx_timer_expired @ Pickup expiration flag address + MOV r2, #1 @ Build expired value + STR r2, [r3] @ Set expired flag + B __tx_timer_done @ Finished timer processing +@ +@ } +@ else +@ { +__tx_timer_no_timer: +@ +@ /* No timer expired, increment the timer pointer. */ +@ _tx_timer_current_ptr++; +@ + ADD r0, r0, #4 @ Move to next timer +@ +@ /* Check for wraparound. */ +@ if (_tx_timer_current_ptr == _tx_timer_list_end) +@ + LDR r3, =_tx_timer_list_end @ Pickup address of timer list end + LDR r2, [r3] @ Pickup list end + CMP r0, r2 @ Are we at list end? + BNE __tx_timer_skip_wrap @ No, skip wraparound logic +@ +@ /* Wrap to beginning of list. */ +@ _tx_timer_current_ptr = _tx_timer_list_start; +@ + LDR r3, =_tx_timer_list_start @ Pickup address of timer list start + LDR r0, [r3] @ Set current pointer to list start +@ +__tx_timer_skip_wrap: +@ + STR r0, [r1] @ Store new current timer pointer +@ } +@ +__tx_timer_done: +@ +@ +@ /* See if anything has expired. */ +@ if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +@ { +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of expired flag + LDR r2, [r3] @ Pickup time-slice expired flag + CMP r2, #0 @ Did a time-slice expire? + BNE __tx_something_expired @ If non-zero, time-slice expired + LDR r1, =_tx_timer_expired @ Pickup address of other expired flag + LDR r0, [r1] @ Pickup timer expired flag + CMP r0, #0 @ Did a timer expire? + BEQ __tx_timer_nothing_expired @ No, nothing expired +@ +__tx_something_expired: +@ +@ + STMDB sp!, {r0, lr} @ Save the lr register on the stack + @ and save r0 just to keep 8-byte alignment +@ +@ /* Did a timer expire? */ +@ if (_tx_timer_expired) +@ { +@ + LDR r1, =_tx_timer_expired @ Pickup address of expired flag + LDR r0, [r1] @ Pickup timer expired flag + CMP r0, #0 @ Check for timer expiration + BEQ __tx_timer_dont_activate @ If not set, skip timer activation +@ +@ /* Process timer expiration. */ +@ _tx_timer_expiration_process(); +@ + BL _tx_timer_expiration_process @ Call the timer expiration handling routine +@ +@ } +__tx_timer_dont_activate: +@ +@ /* Did time slice expire? */ +@ if (_tx_timer_expired_time_slice) +@ { +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of time-slice expired + LDR r2, [r3] @ Pickup the actual flag + CMP r2, #0 @ See if the flag is set + BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing +@ +@ /* Time slice interrupted thread. */ +@ _tx_thread_time_slice(); +@ + BL _tx_thread_time_slice @ Call time-slice processing +@ +@ } +@ +__tx_timer_not_ts_expiration: +@ + LDMIA sp!, {r0, lr} @ Recover lr register (r0 is just there for + @ the 8-byte stack alignment +@ +@ } +@ +__tx_timer_nothing_expired: +@ +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@ +@} + diff --git a/ports/cortex_m0/ac6/example_build/sample_threadx/.cproject b/ports/cortex_m0/ac6/example_build/sample_threadx/.cproject new file mode 100644 index 00000000..c450d130 --- /dev/null +++ b/ports/cortex_m0/ac6/example_build/sample_threadx/.cproject @@ -0,0 +1,238 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_m0/ac6/example_build/sample_threadx/.project b/ports/cortex_m0/ac6/example_build/sample_threadx/.project new file mode 100644 index 00000000..725328bd --- /dev/null +++ b/ports/cortex_m0/ac6/example_build/sample_threadx/.project @@ -0,0 +1,27 @@ + + + sample_threadx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.arm.debug.ds.nature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/ports/cortex_m0/ac6/example_build/sample_threadx/.settings/language.settings.xml b/ports/cortex_m0/ac6/example_build/sample_threadx/.settings/language.settings.xml new file mode 100644 index 00000000..ee684d51 --- /dev/null +++ b/ports/cortex_m0/ac6/example_build/sample_threadx/.settings/language.settings.xml @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_m0/ac6/example_build/sample_threadx/cortex-m0_tx.launch b/ports/cortex_m0/ac6/example_build/sample_threadx/cortex-m0_tx.launch new file mode 100644 index 00000000..0b0520f1 --- /dev/null +++ b/ports/cortex_m0/ac6/example_build/sample_threadx/cortex-m0_tx.launch @@ -0,0 +1,174 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_m0/ac6/example_build/sample_threadx/exceptions.c b/ports/cortex_m0/ac6/example_build/sample_threadx/exceptions.c new file mode 100644 index 00000000..96597048 --- /dev/null +++ b/ports/cortex_m0/ac6/example_build/sample_threadx/exceptions.c @@ -0,0 +1,83 @@ +/* +** Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. +** Use, modification and redistribution of this file is subject to your possession of a +** valid End User License Agreement for the Arm Product of which these examples are part of +** and your compliance with all applicable terms and conditions of such licence agreement. +*/ + +/* This file contains the default exception handlers and vector table. +All exceptions are handled in Handler mode. Processor state is automatically +pushed onto the stack when an exception occurs, and popped from the stack at +the end of the handler */ + + +/* Exception Handlers */ +/* Marking as __attribute__((interrupt)) avoids them being accidentally called from elsewhere */ + +__attribute__((interrupt)) void NMIException(void) +{ while(1); } + +__attribute__((interrupt)) void HardFaultException(void) +{ while(1); } + +void __tx_SVCallHandler(void); + +void __tx_PendSVHandler(void); + +/* For SysTick, use handler in timer.c */ +void SysTick_Handler(void); + +__attribute__((interrupt)) void InterruptHandler(void) +{ while(1); } + + +/* typedef for the function pointers in the vector table */ +typedef void(* const ExecFuncPtr)(void) __attribute__((interrupt)); + +/* Linker-generated Stack Base address */ +#ifdef TWO_REGION +extern unsigned int Image$$ARM_LIB_STACK$$ZI$$Limit; /* for Two Region model */ +#else +extern unsigned int Image$$ARM_LIB_STACKHEAP$$ZI$$Limit; /* for (default) One Region model */ +#endif + +/* Entry point for C run-time initialization */ +extern int __main(void); + + +/* Vector table +Create a named ELF section for the vector table that can be placed in a scatter file. +The first two entries are: + Initial SP = |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit| for (default) One Region model + or |Image$$ARM_LIB_STACK$$ZI$$Limit| for Two Region model + Initial PC= &__main (with LSB set to indicate Thumb) +*/ + +ExecFuncPtr vector_table[] __attribute__((section("vectors"))) = { + /* Configure Initial Stack Pointer using linker-generated symbol */ +#ifdef TWO_REGION + #pragma import(__use_two_region_memory) + (ExecFuncPtr)&Image$$ARM_LIB_STACK$$ZI$$Limit, +#else /* (default) One Region model */ + (ExecFuncPtr)&Image$$ARM_LIB_STACKHEAP$$ZI$$Limit, +#endif + (ExecFuncPtr)__main, /* Initial PC, set to entry point */ + NMIException, + HardFaultException, + 0, 0, 0, /* Reserved */ + 0, 0, 0, 0, /* Reserved */ + __tx_SVCallHandler, + 0, /* Reserved */ + 0, /* Reserved */ + __tx_PendSVHandler, + SysTick_Handler, + + /* Add up to 32 interrupt handlers, starting here... */ + InterruptHandler, + InterruptHandler, /* Some dummy interrupt handlers */ + InterruptHandler + /* + : + */ +}; + diff --git a/ports/cortex_m0/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_m0/ac6/example_build/sample_threadx/sample_threadx.c new file mode 100644 index 00000000..f400736a --- /dev/null +++ b/ports/cortex_m0/ac6/example_build/sample_threadx/sample_threadx.c @@ -0,0 +1,372 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 12000 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +UCHAR memory_area[DEMO_BYTE_POOL_SIZE]; + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", &memory_area[0], DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_m0/ac6/example_build/sample_threadx/sample_threadx.scat b/ports/cortex_m0/ac6/example_build/sample_threadx/sample_threadx.scat new file mode 100644 index 00000000..8578282d --- /dev/null +++ b/ports/cortex_m0/ac6/example_build/sample_threadx/sample_threadx.scat @@ -0,0 +1,46 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m0 -xc + +;******************************************************* +; Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. +; Use, modification and redistribution of this file is subject to your possession of a +; valid End User License Agreement for the Arm Product of which these examples are part of +; and your compliance with all applicable terms and conditions of such licence agreement. +;******************************************************* + +; Scatter-file for Cortex-M0 bare-metal example + +; This scatter-file places the vector table, application code, data, stacks and heap at suitable addresses in the memory map. + +; The vector table is placed first at the start of the image. +; Code starts after the last entry in the vector table. +; Data is placed at an address that must correspond to RAM. +; Stack and Heap are placed using ARM_LIB_STACKHEAP, to eliminate the need to set stack-base or heap-base in the debugger. +; System Control Space registers appear at their architecturally-defined addresses, based at 0xE000E000. + + +LOAD_REGION 0x00000000 +{ + VECTORS +0 0xC0 ; 16 exceptions + up to 32 interrupts, 4 bytes each entry == 0xC0 + { + exceptions.o (vectors, +FIRST) ; from exceptions.c + } + + ; Code is placed immediately (+0) after the previous root region + ; (so code region will also be a root region) + CODE +0 + { + * (+RO) ; All program code, including library code + } + + DATA +0 + { + * (+RW, +ZI) ; All RW and ZI data + } + + ; Heap grows upwards from start of this region and + ; Stack grows downwards from end of this region + ; The Main Stack Pointer is initialized on reset to the top addresses of this region + ARM_LIB_STACKHEAP +0 EMPTY 0x1000 + { + } +} diff --git a/ports/cortex_m0/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_m0/ac6/example_build/sample_threadx/tx_initialize_low_level.S new file mode 100644 index 00000000..b561aaca --- /dev/null +++ b/ports/cortex_m0/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -0,0 +1,183 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Initialize */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_initialize.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global _tx_thread_context_save + .global _tx_thread_context_restore + .global _tx_timer_interrupt +@ +@ +SYSTEM_CLOCK = 8000000 +SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) + + .text + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_initialize_low_level Cortex-M0/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for any low-level processor */ +@/* initialization, including setting up interrupt vectors, setting */ +@/* up a periodic timer interrupt source, saving the system stack */ +@/* pointer for use in ISR processing later, and finding the first */ +@/* available RAM memory address for tx_application_define. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_initialize_low_level(VOID) +@{ + .global _tx_initialize_low_level + .thumb_func +_tx_initialize_low_level: +@ +@ /* Disable interrupts during ThreadX initialization. */ +@ + CPSID i +@ +@ /* Set base of available memory to end of non-initialised RAM area. */ +@ + LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer + LDR r1, =Image$$ARM_LIB_STACKHEAP$$ZI$$Limit @ Build first free address + ADDS r1, r1, #4 @ + STR r1, [r0] @ Setup first unused memory pointer +@ +@ /* Enable the cycle count register. */ +@ + LDR r0, =0xE0001000 @ Build address of DWT register + LDR r1, [r0] @ Pickup the current value + MOVS r2, #1 + ORRS r1, r1, r2 @ Set the CYCCNTENA bit + STR r1, [r0] @ Enable the cycle count register +@ +@ /* Setup Vector Table Offset Register. */ +@ + LDR r0, =0xE000E000 @ Build address of NVIC registers + LDR r2, =0xD08 @ Offset to vector base register + ADD r0, r0, r2 @ Build vector base register + LDR r1, =vector_table @ Pickup address of vector table + STR r1, [r0] @ Set vector table address +@ +@ /* Set system stack pointer from vector value. */ +@ + LDR r0, =_tx_thread_system_stack_ptr @ Build address of system stack pointer + LDR r1, =vector_table @ Pickup address of vector table + LDR r1, [r1] @ Pickup reset stack pointer + STR r1, [r0] @ Save system stack pointer +@ +@ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ +@ + LDR r0, =0xE000E000 @ Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] @ Setup SysTick Reload Value + LDR r1, =0x7 @ Build SysTick Control Enable Value + STR r1, [r0, #0x10] @ Setup SysTick Control +@ +@ /* Configure handler priorities. */ +@ + LDR r1, =0x00000000 @ Rsrv, UsgF, BusF, MemM + LDR r0, =0xE000E000 @ Build address of NVIC registers + LDR r2, =0xD18 @ + ADD r0, r0, r2 @ + STR r1, [r0] @ Setup System Handlers 4-7 Priority Registers + LDR r1, =0xFF000000 @ SVCl, Rsrv, Rsrv, Rsrv + LDR r0, =0xE000E000 @ Build address of NVIC registers + LDR r2, =0xD1C @ + ADD r0, r0, r2 @ + STR r1, [r0] @ Setup System Handlers 8-11 Priority Registers + @ Note: SVC must be lowest priority, which is 0xFF + LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM + LDR r0, =0xE000E000 @ Build address of NVIC registers + LDR r2, =0xD20 @ + ADD r0, r0, r2 @ + STR r1, [r0] @ Setup System Handlers 12-15 Priority Registers + @ Note: PnSV must be lowest priority, which is 0xFF + +@ +@ /* Return to caller. */ +@ + BX lr +@} +@ +@ /* System Tick timer interrupt handler */ + .global __tx_SysTickHandler + .global SysTick_Handler + .thumb_func +__tx_SysTickHandler: + .thumb_func +SysTick_Handler: +@ VOID SysTick_Handler (VOID) +@ { +@ + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter @ Call the ISR enter function +#endif + BL _tx_timer_interrupt +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif + POP {r0, r1} + MOV lr, r1 + BX lr +@ } diff --git a/ports/cortex_m0/ac6/example_build/tx/.cproject b/ports/cortex_m0/ac6/example_build/tx/.cproject new file mode 100644 index 00000000..03730c3b --- /dev/null +++ b/ports/cortex_m0/ac6/example_build/tx/.cproject @@ -0,0 +1,212 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_m0/ac6/example_build/tx/.project b/ports/cortex_m0/ac6/example_build/tx/.project new file mode 100644 index 00000000..863ca5cb --- /dev/null +++ b/ports/cortex_m0/ac6/example_build/tx/.project @@ -0,0 +1,48 @@ + + + tx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + inc_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/inc + + + inc_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/inc + + + src_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/src + + + src_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/src + + + diff --git a/ports/cortex_m0/ac6/example_build/tx/.settings/language.settings.xml b/ports/cortex_m0/ac6/example_build/tx/.settings/language.settings.xml new file mode 100644 index 00000000..ffbac370 --- /dev/null +++ b/ports/cortex_m0/ac6/example_build/tx/.settings/language.settings.xml @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_m0/ac6/inc/tx_port.h b/ports/cortex_m0/ac6/inc/tx_port.h new file mode 100644 index 00000000..10e7557c --- /dev/null +++ b/ports/cortex_m0/ac6/inc/tx_port.h @@ -0,0 +1,371 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-M0/AC6 */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the TX_MEMSET macro to remove library reference. */ + +#define TX_MEMSET(a,b,c) { \ + UCHAR *ptr; \ + UCHAR value; \ + UINT i, size; \ + ptr = (UCHAR *) ((VOID *) a); \ + value = (UCHAR) b; \ + size = (UINT) c; \ + for (i = 0; i < size; i++) \ + { \ + *ptr++ = value; \ + } \ + } + + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX Cortex-M0 port. */ + +#define TX_INT_DISABLE 1 /* Disable interrupts */ +#define TX_INT_ENABLE 0 /* Enable interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) +#endif +#else +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define the get system state macro. */ + +#ifndef TX_THREAD_GET_SYSTEM_STATE +#ifndef TX_MISRA_ENABLE + +__attribute__( ( always_inline ) ) static inline unsigned int __get_ipsr_value(void) +{ + +unsigned int ipsr_value; + + __asm__ volatile (" MRS %0,IPSR ": "=r" (ipsr_value) ); + return(ipsr_value); +} + + +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | __get_ipsr_value()) +#else +ULONG _tx_misra_ipsr_get(VOID); +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get()) +#endif +#endif + + +/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value + indicates that _tx_thread_system_return should not be called. */ + +#ifndef TX_THREAD_SYSTEM_RETURN_CHECK +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#endif + +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to + prevent early scheduling on Cortex-M parts. */ + +#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; + + +#ifndef TX_DISABLE_INLINE + +/* Define AC6 specific macros, with in-line assembly for performance. */ + +__attribute__( ( always_inline ) ) static inline unsigned int __disable_interrupts(void) +{ + +unsigned int primask_value; + + __asm__ volatile (" MRS %0,PRIMASK ": "=r" (primask_value) ); + __asm__ volatile (" CPSID i" : : : "memory" ); + return(primask_value); +} + +__attribute__( ( always_inline ) ) static inline void __restore_interrupts(unsigned int primask_value) +{ + + __asm__ volatile (" MSR PRIMASK,%0": : "r" (primask_value): "memory" ); +} + +__attribute__( ( always_inline ) ) static inline unsigned int __get_primask_value(void) +{ + +unsigned int primask_value; + + __asm__ volatile (" MRS %0,PRIMASK ": "=r" (primask_value) ); + return(primask_value); +} + +__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void) +{ + + __asm__ volatile (" CPSIE i": : : "memory" ); +} + + +__attribute__( ( always_inline ) ) static inline void _tx_thread_system_return_inline(void) +{ +unsigned int interrupt_save; + + *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + if (__get_ipsr_value() == 0) + { + interrupt_save = __get_primask_value(); + __enable_interrupts(); + __restore_interrupts(interrupt_save); + } +} + + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = __disable_interrupts(); +#define TX_RESTORE __restore_interrupts(interrupt_save); + + +/* Redefine _tx_thread_system_return for improved performance. */ + +#define _tx_thread_system_return _tx_thread_system_return_inline + + +#else + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); +#define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); +#endif + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0/AC6 Version 6.0.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + + + diff --git a/ports/cortex_m0/ac6/readme_threadx.txt b/ports/cortex_m0/ac6/readme_threadx.txt new file mode 100644 index 00000000..fb6e237d --- /dev/null +++ b/ports/cortex_m0/ac6/readme_threadx.txt @@ -0,0 +1,158 @@ + Microsoft's Azure RTOS ThreadX for Cortex-M0 + + Using ARM Compiler 6 & DS + +1. Import the ThreadX Projects + +In order to build the ThreadX library and the ThreadX demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +into your DS workspace. + + +2. Building the ThreadX run-time Library + +Building the ThreadX library is easy; simply right-click the Eclipse project +"tx" and then select the "Build Project" button. You should now observe the compilation +and assembly of the ThreadX library. This project build produces the ThreadX +library file tx.a. + + +3. Demonstration System + +The ThreadX demonstration is designed to execute under the DS debugger on the +MPS2_Cortex_M0 Bare Metal simulator. + +Building the demonstration is easy; simply right-click the Eclipse project +"sample_threadx" and then select the "Build Project" button. You should now observe +the compilation and assembly of the ThreadX demonstration. This project build produces +the ThreadX library file sample_threadx.axf. Next, expand the demo ThreadX project folder +in the Project Explorer window, right-click on the 'cortex-m0_tx.launch' file, click +'Debug As', and then click 'cortex-m0_tx' from the submenu. This will cause the +debugger to load the sample_threadx.axf ELF file and run to main. You are now ready +to execute the ThreadX demonstration. + + +4. System Initialization + +The entry point in ThreadX for the Cortex-M0 using AC6 tools uses the standard AC6 +Cortex-M0 reset sequence. From the reset vector the C runtime will be initialized. + +The ThreadX tx_initialize_low_level.S file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. + +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input +parameter to your application definition function, tx_application_define. + + +5. Register Usage and Stack Frames + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have the same stack frame in the Cortex-M0 version of +ThreadX. The top of the suspended thread's stack is pointed to by +tx_thread_stack_ptr in the associated thread control block TX_THREAD. + + + Stack Offset Stack Contents + + 0x00 r8 + 0x04 r9 + 0x08 r10 + 0x0C r11 + 0x10 r4 + 0x14 r5 + 0x18 r6 + 0x1C r7 + 0x20 r0 (Hardware stack starts here!!) + 0x24 r1 + 0x28 r2 + 0x2C r3 + 0x30 r12 + 0x34 lr + 0x38 pc + 0x3C xPSR + + +6. Improving Performance + +The distribution version of ThreadX is built without any compiler optimizations. +This makes it easy to debug because you can trace or set breakpoints inside of +ThreadX itself. Of course, this costs some performance. To make it run faster, +you can change the build_threadx.bat file to remove the -g option and enable +all compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-M0 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +7.1 Vector Area + +The Cortex-M0 vectors start at the label __tx_vectors or similar. The application may modify +the vector area according to its needs. There is code in tx_initialize_low_level() that will +configure the vector base register. + + +7.2 Managed Interrupts + +ISRs can be written completely in C (or assembly language) without any calls to +_tx_thread_context_save or _tx_thread_context_restore. These ISRs are allowed access to the +ThreadX API that is available to ISRs. + +ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table): + +void your_C_isr(void) +{ + + /* ISR processing goes here, including any needed function calls. */ +} + +ISRs written in assembly language will take the form: + + + .global your_assembly_isr + .thumb_func +your_assembly_isr: +; VOID your_assembly_isr(VOID) +; { + PUSH {r0, lr} +; +; /* Do interrupt handler work here */ +; /* BL */ + + POP {r0, r1} + MOV lr, r1 + BX lr +; } + + +Note: the Cortex-M0 requires exception handlers to be thumb labels, this implies bit 0 set. +To accomplish this, the declaration of the label has to be preceded by the assembler directive +.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to +be inserted in the correct location in the interrupt vector table. This table is typically +located in either your runtime startup file or in the tx_initialize_low_level.S file. + + +8. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M0 using AC6 tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_m0/ac6/src/tx_thread_context_restore.S b/ports/cortex_m0/ac6/src/tx_thread_context_restore.S new file mode 100644 index 00000000..80d41fd5 --- /dev/null +++ b/ports/cortex_m0/ac6/src/tx_thread_context_restore.S @@ -0,0 +1,95 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_system_stack_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable +@ +@ + .text 32 + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_restore Cortex-M0/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function restores the interrupt context if it is processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs Interrupt Service Routines */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_restore(VOID) +@{ + .global _tx_thread_context_restore + .thumb_func +_tx_thread_context_restore: +@ +@ /* Not needed for this port - just return! */ + BX lr +@} + diff --git a/ports/cortex_m0/ac6/src/tx_thread_context_save.S b/ports/cortex_m0/ac6/src/tx_thread_context_save.S new file mode 100644 index 00000000..476fbbcb --- /dev/null +++ b/ports/cortex_m0/ac6/src/tx_thread_context_save.S @@ -0,0 +1,89 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr +@ +@ + .text 32 + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_save Cortex-M0/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_save(VOID) +@{ + .global _tx_thread_context_save + .thumb_func +_tx_thread_context_save: +@ +@ /* Not needed for this port - just return! */ + BX lr +@} + diff --git a/ports/cortex_m0/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_m0/ac6/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..f16dd873 --- /dev/null +++ b/ports/cortex_m0/ac6/src/tx_thread_interrupt_control.S @@ -0,0 +1,94 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ + + +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ + +@/* #define TX_SOURCE_CODE */ + + +@/* Include necessary system files. */ + +@/* #include "tx_api.h" + #include "tx_thread.h" */ + + + .text 32 + .align 4 + .syntax unified + +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_control Cortex-M0/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for changing the interrupt lockout */ +@/* posture of the system. */ +@/* */ +@/* INPUT */ +@/* */ +@/* new_posture New interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@/* UINT _tx_thread_interrupt_control(UINT new_posture) +{ */ + .global _tx_thread_interrupt_control + .thumb_func +_tx_thread_interrupt_control: + +@/* Pickup current interrupt lockout posture. */ + + MRS r1, PRIMASK @ Pickup current interrupt lockout + + +@/* Apply the new interrupt posture. */ + + MSR PRIMASK, r0 @ Apply the new interrupt lockout + MOV r0, r1 @ Transfer old to return register + BX lr @ Return to caller + +@/* } */ + + + diff --git a/ports/cortex_m0/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_m0/ac6/src/tx_thread_interrupt_disable.S new file mode 100644 index 00000000..d5ce5e56 --- /dev/null +++ b/ports/cortex_m0/ac6/src/tx_thread_interrupt_disable.S @@ -0,0 +1,88 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ + + +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ + +@/* #define TX_SOURCE_CODE */ + + +@/* Include necessary system files. */ + +@/* #include "tx_api.h" + #include "tx_thread.h" */ + + + .text 32 + .align 4 + .syntax unified + +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_disable Cortex-M0/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for disabling interrupts. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@/* UINT _tx_thread_interrupt_disable(VOID) +{ */ + .global _tx_thread_interrupt_disable + .thumb_func +_tx_thread_interrupt_disable: + +@/* Pickup current interrupt lockout posture. */ + + MRS r0, PRIMASK + CPSID i + BX lr + +@/* } */ + + + diff --git a/ports/cortex_m0/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_m0/ac6/src/tx_thread_interrupt_restore.S new file mode 100644 index 00000000..d3dcff80 --- /dev/null +++ b/ports/cortex_m0/ac6/src/tx_thread_interrupt_restore.S @@ -0,0 +1,86 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ + + +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ + +@/* #define TX_SOURCE_CODE */ + + +@/* Include necessary system files. */ + +@/* #include "tx_api.h" + #include "tx_thread.h" */ + + + .text 32 + .align 4 + .syntax unified + +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_restore Cortex-M0/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for restoring the interrupt lockout */ +@/* posture of the system. */ +@/* */ +@/* INPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@/* VOID _tx_thread_interrupt_restore(UINT old_posture) +{ */ + .global _tx_thread_interrupt_restore + .thumb_func +_tx_thread_interrupt_restore: + + MSR PRIMASK, r0 + BX lr + +@/* } */ + + + diff --git a/ports/cortex_m0/ac6/src/tx_thread_schedule.S b/ports/cortex_m0/ac6/src/tx_thread_schedule.S new file mode 100644 index 00000000..70f3292c --- /dev/null +++ b/ports/cortex_m0/ac6/src/tx_thread_schedule.S @@ -0,0 +1,276 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ + .global _tx_thread_current_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_system_stack_ptr +@ +@ + .text + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_schedule Cortex-M0/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function waits for a thread control block pointer to appear in */ +@/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +@/* in the variable, the corresponding thread is resumed. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* _tx_thread_system_return Return to system from thread */ +@/* _tx_thread_context_restore Restore thread's context */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_schedule(VOID) +@{ + .global _tx_thread_schedule + .thumb_func +_tx_thread_schedule: +@ +@ /* This function should only ever be called on Cortex-M0 +@ from the first schedule request. Subsequent scheduling occurs +@ from the PendSV handling routines below. */ +@ +@ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ +@ + MOVS r0, #0 @ Build value for TX_FALSE + LDR r2, =_tx_thread_preempt_disable @ Build address of preempt disable flag + STR r0, [r2, #0] @ Clear preempt disable flag +@ +@ /* Enable interrupts */ +@ + CPSIE i +@ +@ /* Enter the scheduler for the first time. */ +@ + LDR r0, =0x10000000 @ Load PENDSVSET bit + LDR r1, =0xE000ED04 @ Load NVIC base + STR r0, [r1] @ Set PENDSVBIT in ICSR + DSB @ Complete all memory accesses + ISB @ Flush pipeline +@ +@ /* Wait here for the PendSV to take place. */ +@ +__tx_wait_here: + B __tx_wait_here @ Wait for the PendSV to happen +@} +@ +@ /* Generic context switch-out switch-in handler... Note that this handler is +@ common for both PendSV and SVCall. */ +@ + .global PendSV_Handler +.thumb_func +.thumb_func +PendSV_Handler: + .global __tx_PendSVHandler + .global __tx_SVCallHandler + .thumb_func +__tx_PendSVHandler: + .thumb_func +__tx_SVCallHandler: +@ +@ /* Get current thread value and new thread pointer. */ +@ + .thumb_func +__tx_ts_handler: + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the thread exit function to indicate the thread is no longer executing. */ +@ + CPSID i @ Disable interrupts + PUSH {r0, lr} @ Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit @ Call the thread exit function + POP {r0, r1} @ Recover LR + MOV lr, r1 @ + CPSIE i @ Enable interrupts +#endif + LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address + LDR r2, =_tx_thread_execute_ptr @ Build execute thread pointer address + MOVS r3, #0 @ Build NULL value + LDR r1, [r0] @ Pickup current thread pointer +@ +@ /* Determine if there is a current thread to finish preserving. */ +@ + CMP r1,#0 @ If NULL, skip preservation + BEQ __tx_ts_new @ +@ +@ /* Recover PSP and preserve current thread context. */ +@ + STR r3, [r0] @ Set _tx_thread_current_ptr to NULL + MRS r3, PSP @ Pickup PSP pointer (thread's stack pointer) + SUBS r3, r3, #16 @ Allocate stack space + STM r3!, {r4-r7} @ Save its remaining registers (M3 Instruction: STMDB r12!, {r4-r11}) + MOV r4,r8 @ + MOV r5,r9 @ + MOV r6,r10 @ + MOV r7,r11 @ + SUBS r3, r3, #32 @ Allocate stack space + STM r3!,{r4-r7} @ + SUBS r3, r3, #20 @ Allocate stack space + MOV r5, lr @ Move LR into R4 + STR r5, [r3] @ Save LR + STR r3, [r1, #8] @ Save its stack pointer +@ +@ /* Determine if time-slice is active. If it isn't, skip time handling processing. */ +@ + LDR r4, =_tx_timer_time_slice @ Build address of time-slice variable + LDR r5, [r4] @ Pickup current time-slice + CMP r5, #0 @ If not active, skip processing + BEQ __tx_ts_new @ +@ +@ /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ +@ + STR r5, [r1, #24] @ Save current time-slice +@ +@ /* Clear the global time-slice. */ +@ + MOVS r5, #0 @ Build clear value + STR r5, [r4] @ Clear time-slice +@ +@ /* Executing thread is now completely preserved!!! */ +@ +__tx_ts_new: +@ +@ /* Now we are looking for a new thread to execute! */ +@ + CPSID i @ Disable interrupts + LDR r1, [r2] @ Is there another thread ready to execute? + CMP r1, #0 @ + BEQ __tx_ts_wait @ No, skip to the wait processing +@ +@ /* Yes, another thread is ready for else, make the current thread the new thread. */ +@ + STR r1, [r0] @ Setup the current thread pointer to the new thread + CPSIE i @ Enable interrupts +@ +@ /* Increment the thread run count. */ +@ +__tx_ts_restore: + LDR r7, [r1, #4] @ Pickup the current thread run count + LDR r4, =_tx_timer_time_slice @ Build address of time-slice variable + LDR r5, [r1, #24] @ Pickup thread's current time-slice + ADDS r7, r7, #1 @ Increment the thread run count + STR r7, [r1, #4] @ Store the new run count +@ +@ /* Setup global time-slice with thread's current time-slice. */ +@ + STR r5, [r4] @ Setup global time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the thread entry function to indicate the thread is executing. */ +@ + PUSH {r0, r1} @ Save r0/r1 + BL _tx_execution_thread_enter @ Call the thread execution enter function + POP {r0, r1} @ Recover r3 +#endif +@ +@ /* Restore the thread context and PSP. */ +@ + LDR r3, [r1, #8] @ Pickup thread's stack pointer + LDR r5, [r3] @ Recover saved LR + ADDS r3, r3, #4 @ Position past LR + MOV lr, r5 @ Restore LR + LDM r3!,{r4-r7} @ Recover thread's registers (r4-r11) + MOV r11,r7 @ + MOV r10,r6 @ + MOV r9,r5 @ + MOV r8,r4 @ + LDM r3!,{r4-r7} @ + MSR PSP, r3 @ Setup the thread's stack pointer +@ +@ /* Return to thread. */ +@ + BX lr @ Return to thread! +@ +@ /* The following is the idle wait processing... in this case, no threads are ready for execution and the +@ system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +@ are disabled to allow use of WFI for waiting for a thread to arrive. */ +@ +__tx_ts_wait: + CPSID i @ Disable interrupts + LDR r1, [r2] @ Pickup the next thread to execute pointer + STR r1, [r0] @ Store it in the current pointer + CMP r1, #0 @ If non-NULL, a new thread is ready! + BNE __tx_ts_ready @ +#ifdef TX_ENABLE_WFI + DSB @ Ensure no outstanding memory transactions + WFI @ Wait for interrupt + ISB @ Ensure pipeline is flushed +#endif + CPSIE i @ Enable interrupts + B __tx_ts_wait @ Loop to continue waiting +@ +@ /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +@ already in the handler! */ +@ +__tx_ts_ready: + LDR r7, =0x08000000 @ Build clear PendSV value + LDR r5, =0xE000ED04 @ Build base NVIC address + STR r7, [r5] @ Clear any PendSV +@ +@ /* Re-enable interrupts and restore new thread. */ +@ + CPSIE i @ Enable interrupts + B __tx_ts_restore @ Restore the thread + diff --git a/ports/cortex_m0/ac6/src/tx_thread_stack_build.S b/ports/cortex_m0/ac6/src/tx_thread_stack_build.S new file mode 100644 index 00000000..b12ad10a --- /dev/null +++ b/ports/cortex_m0/ac6/src/tx_thread_stack_build.S @@ -0,0 +1,147 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ + .text + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_stack_build Cortex-M0/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function builds a stack frame on the supplied thread's stack. */ +@/* The stack frame results in a fake interrupt return to the supplied */ +@/* function pointer. */ +@/* */ +@/* INPUT */ +@/* */ +@/* thread_ptr Pointer to thread control blk */ +@/* function_ptr Pointer to return function */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_thread_create Create thread service */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +@{ + .global _tx_thread_stack_build + .thumb_func +_tx_thread_stack_build: +@ +@ +@ /* Build a fake interrupt frame. The form of the fake interrupt stack +@ on the Cortex-M0 should look like the following after it is built: +@ +@ Stack Top: +@ LR Interrupted LR (LR at time of PENDSV) +@ r8 Initial value for r8 +@ r9 Initial value for r9 +@ r10 Initial value for r10 +@ r11 Initial value for r11 +@ r4 Initial value for r4 +@ r5 Initial value for r5 +@ r6 Initial value for r6 +@ r7 Initial value for r7 +@ r0 Initial value for r0 (Hardware stack starts here!!) +@ r1 Initial value for r1 +@ r2 Initial value for r2 +@ r3 Initial value for r3 +@ r12 Initial value for r12 +@ lr Initial value for lr +@ pc Initial value for pc +@ xPSR Initial value for xPSR +@ +@ Stack Bottom: (higher memory address) */ +@ + LDR r2, [r0, #16] @ Pickup end of stack area + MOVS r3, #0x7 @ + BICS r2, r2, r3 @ Align frame for 8-byte alignment + SUBS r2, r2, #68 @ Subtract frame size + LDR r3, =0xFFFFFFFD @ Build initial LR value + STR r3, [r2, #0] @ Save on the stack +@ +@ /* Actually build the stack frame. */ +@ + MOVS r3, #0 @ Build initial register value + STR r3, [r2, #4] @ Store initial r8 + STR r3, [r2, #8] @ Store initial r9 + STR r3, [r2, #12] @ Store initial r10 + STR r3, [r2, #16] @ Store initial r11 + STR r3, [r2, #20] @ Store initial r4 + STR r3, [r2, #24] @ Store initial r5 + STR r3, [r2, #28] @ Store initial r6 + STR r3, [r2, #32] @ Store initial r7 +@ +@ /* Hardware stack follows. */ +@ + STR r3, [r2, #36] @ Store initial r0 + STR r3, [r2, #40] @ Store initial r1 + STR r3, [r2, #44] @ Store initial r2 + STR r3, [r2, #48] @ Store initial r3 + STR r3, [r2, #52] @ Store initial r12 + LDR r3, =0xFFFFFFFF @ Poison EXC_RETURN value + STR r3, [r2, #56] @ Store initial lr + STR r1, [r2, #60] @ Store initial pc + LDR r3, =0x01000000 @ Only T-bit need be set + STR r3, [r2, #64] @ Store initial xPSR +@ +@ /* Setup stack pointer. */ +@ thread_ptr -> tx_thread_stack_ptr = r2; +@ + STR r2, [r0, #8] @ Save stack pointer in thread's + @ control block + BX lr @ Return to caller +@} + + diff --git a/ports/cortex_m0/ac6/src/tx_thread_system_return.S b/ports/cortex_m0/ac6/src/tx_thread_system_return.S new file mode 100644 index 00000000..c11d15ac --- /dev/null +++ b/ports/cortex_m0/ac6/src/tx_thread_system_return.S @@ -0,0 +1,97 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@/* #define TX_SOURCE_CODE */ +@ +@ +@/* Include necessary system files. */ +@ +@/* #include "tx_api.h" +@ #include "tx_thread.h" +@ #include "tx_timer.h" */ + + + .text + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_system_return Cortex-M0/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is target processor specific. It is used to transfer */ +@/* control from a thread back to the ThreadX system. Only a */ +@/* minimal context is saved since the compiler assumes temp registers */ +@/* are going to get slicked by a function call anyway. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling loop */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX components */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@/* VOID _tx_thread_system_return(VOID) +@{ */ + .global _tx_thread_system_return + .thumb_func +_tx_thread_system_return: +@ +@ /* Return to real scheduler via PendSV. Note that this routine is often +@ replaced with in-line assembly in tx_port.h to improved performance. */ +@ + LDR r0, =0x10000000 @ Load PENDSVSET bit + LDR r1, =0xE000ED04 @ Load NVIC base + STR r0, [r1] @ Set PENDSVBIT in ICSR + MRS r0, IPSR @ Pickup IPSR + CMP r0, #0 @ Is it a thread returning? + BNE _isr_context @ If ISR, skip interrupt enable + MRS r1, PRIMASK @ Thread context returning, pickup PRIMASK + CPSIE i @ Enable interrupts + MSR PRIMASK, r1 @ Restore original interrupt posture +_isr_context: + BX lr @ Return to caller +@/* } */ + diff --git a/ports/cortex_m0/ac6/src/tx_timer_interrupt.S b/ports/cortex_m0/ac6/src/tx_timer_interrupt.S new file mode 100644 index 00000000..4894d9ae --- /dev/null +++ b/ports/cortex_m0/ac6/src/tx_timer_interrupt.S @@ -0,0 +1,271 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Timer */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_timer.h" +@#include "tx_thread.h" +@ +@ +@Define Assembly language external references... +@ + .global _tx_timer_time_slice + .global _tx_timer_system_clock + .global _tx_timer_current_ptr + .global _tx_timer_list_start + .global _tx_timer_list_end + .global _tx_timer_expired_time_slice + .global _tx_timer_expired + .global _tx_thread_time_slice + .global _tx_timer_expiration_process +@ +@ + .text + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_timer_interrupt Cortex-M0/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function processes the hardware timer interrupt. This */ +@/* processing includes incrementing the system clock and checking for */ +@/* time slice and/or timer expiration. If either is found, the */ +@/* interrupt context save/restore functions are called along with the */ +@/* expiration functions. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_timer_expiration_process Timer expiration processing */ +@/* _tx_thread_time_slice Time slice interrupted thread */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* interrupt vector */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_timer_interrupt(VOID) +@{ + .global _tx_timer_interrupt + .thumb_func +_tx_timer_interrupt: +@ +@ /* Upon entry to this routine, it is assumed that context save has already +@ been called, and therefore the compiler scratch registers are available +@ for use. */ +@ +@ /* Increment the system clock. */ +@ _tx_timer_system_clock++; +@ + LDR r1, =_tx_timer_system_clock @ Pickup address of system clock + LDR r0, [r1, #0] @ Pickup system clock + ADDS r0, r0, #1 @ Increment system clock + STR r0, [r1, #0] @ Store new system clock +@ +@ /* Test for time-slice expiration. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice + LDR r2, [r3, #0] @ Pickup time-slice + CMP r2, #0 @ Is it non-active? + BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing +@ +@ /* Decrement the time_slice. */ +@ _tx_timer_time_slice--; +@ + SUBS r2, r2, #1 @ Decrement the time-slice + STR r2, [r3, #0] @ Store new time-slice value +@ +@ /* Check for expiration. */ +@ if (__tx_timer_time_slice == 0) +@ + CMP r2, #0 @ Has it expired? + BNE __tx_timer_no_time_slice @ No, skip expiration processing +@ +@ /* Set the time-slice expired flag. */ +@ _tx_timer_expired_time_slice = TX_TRUE; +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of expired flag + MOVS r0, #1 @ Build expired value + STR r0, [r3, #0] @ Set time-slice expiration flag +@ +@ } +@ +__tx_timer_no_time_slice: +@ +@ /* Test for timer expiration. */ +@ if (*_tx_timer_current_ptr) +@ { +@ + LDR r1, =_tx_timer_current_ptr @ Pickup current timer pointer address + LDR r0, [r1, #0] @ Pickup current timer + LDR r2, [r0, #0] @ Pickup timer list entry + CMP r2, #0 @ Is there anything in the list? + BEQ __tx_timer_no_timer @ No, just increment the timer +@ +@ /* Set expiration flag. */ +@ _tx_timer_expired = TX_TRUE; +@ + LDR r3, =_tx_timer_expired @ Pickup expiration flag address + MOVS r2, #1 @ Build expired value + STR r2, [r3, #0] @ Set expired flag + B __tx_timer_done @ Finished timer processing +@ +@ } +@ else +@ { +__tx_timer_no_timer: +@ +@ /* No timer expired, increment the timer pointer. */ +@ _tx_timer_current_ptr++; +@ + ADDS r0, r0, #4 @ Move to next timer +@ +@ /* Check for wrap-around. */ +@ if (_tx_timer_current_ptr == _tx_timer_list_end) +@ + LDR r3, =_tx_timer_list_end @ Pickup addr of timer list end + LDR r2, [r3, #0] @ Pickup list end + CMP r0, r2 @ Are we at list end? + BNE __tx_timer_skip_wrap @ No, skip wrap-around logic +@ +@ /* Wrap to beginning of list. */ +@ _tx_timer_current_ptr = _tx_timer_list_start; +@ + LDR r3, =_tx_timer_list_start @ Pickup addr of timer list start + LDR r0, [r3, #0] @ Set current pointer to list start +@ +__tx_timer_skip_wrap: +@ + STR r0, [r1, #0] @ Store new current timer pointer +@ } +@ +__tx_timer_done: +@ +@ +@ /* See if anything has expired. */ +@ if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +@ { +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of expired flag + LDR r2, [r3, #0] @ Pickup time-slice expired flag + CMP r2, #0 @ Did a time-slice expire? + BNE __tx_something_expired @ If non-zero, time-slice expired + LDR r1, =_tx_timer_expired @ Pickup addr of other expired flag + LDR r0, [r1, #0] @ Pickup timer expired flag + CMP r0, #0 @ Did a timer expire? + BEQ __tx_timer_nothing_expired @ No, nothing expired +@ +__tx_something_expired: +@ +@ + PUSH {r0, lr} @ Save the lr register on the stack + @ and save r0 just to keep 8-byte alignment +@ +@ /* Did a timer expire? */ +@ if (_tx_timer_expired) +@ { +@ + LDR r1, =_tx_timer_expired @ Pickup addr of expired flag + LDR r0, [r1, #0] @ Pickup timer expired flag + CMP r0, #0 @ Check for timer expiration + BEQ __tx_timer_dont_activate @ If not set, skip timer activation +@ +@ /* Process timer expiration. */ +@ _tx_timer_expiration_process()@ +@ + BL _tx_timer_expiration_process @ Call the timer expiration handling routine +@ +@ } +__tx_timer_dont_activate: +@ +@ /* Did time slice expire? */ +@ if (_tx_timer_expired_time_slice) +@ { +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired + LDR r2, [r3, #0] @ Pickup the actual flag + CMP r2, #0 @ See if the flag is set + BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing +@ +@ /* Time slice interrupted thread. */ +@ _tx_thread_time_slice(); + + BL _tx_thread_time_slice @ Call time-slice processing + LDR r0, =_tx_thread_preempt_disable @ Build address of preempt disable flag + LDR r1, [r0] @ Is the preempt disable flag set? + CMP r1, #0 @ + BNE __tx_timer_skip_time_slice @ Yes, skip the PendSV logic + LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address + LDR r1, [r0] @ Pickup the current thread pointer + LDR r2, =_tx_thread_execute_ptr @ Build execute thread pointer address + LDR r3, [r2] @ Pickup the execute thread pointer + LDR r0, =0xE000ED04 @ Build address of control register + LDR r2, =0x10000000 @ Build value for PendSV bit + CMP r1, r3 @ Are they the same? + BEQ __tx_timer_skip_time_slice @ If the same, there was no time-slice performed + STR r2, [r0] @ Not the same, issue the PendSV for preemption +__tx_timer_skip_time_slice: +@ +@ } +@ +__tx_timer_not_ts_expiration: +@ + POP {r0, r1} @ Recover lr register (r0 is just there for + MOV lr, r1 @ the 8-byte stack alignment +@ +@ } +@ +__tx_timer_nothing_expired: + + DSB @ Complete all memory access + BX lr @ Return to caller +@ +@} + + diff --git a/ports/cortex_m0/keil/example_build/sample_threadx.c b/ports/cortex_m0/keil/example_build/sample_threadx.c new file mode 100644 index 00000000..4d95c2ed --- /dev/null +++ b/ports/cortex_m0/keil/example_build/sample_threadx.c @@ -0,0 +1,369 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_m0/keil/example_build/sample_threadx.uvoptx b/ports/cortex_m0/keil/example_build/sample_threadx.uvoptx new file mode 100644 index 00000000..6ff0dbc9 --- /dev/null +++ b/ports/cortex_m0/keil/example_build/sample_threadx.uvoptx @@ -0,0 +1,281 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + sample_threadx + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 5 + + + + + + + + + + + BIN\DbgFM.DLL + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + + 0 + 1 + thread_0_counter + + + 1 + 1 + thread_1_counter + + + 2 + 1 + thread_2_counter + + + 3 + 1 + thread_3_counter + + + 4 + 1 + thread_4_counter + + + 5 + 1 + thread_5_counter + + + 6 + 1 + thread_6_counter + + + 7 + 1 + thread_7_counter + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + src + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + .\sample_threadx.c + sample_threadx.c + 0 + 0 + + + 1 + 2 + 2 + 0 + 0 + 0 + .\tx_initialize_low_level.s + tx_initialize_low_level.s + 0 + 0 + + + + + lib + 1 + 0 + 0 + 0 + + 2 + 3 + 4 + 0 + 0 + 0 + .\Objects\tx.lib + tx.lib + 0 + 0 + + + + diff --git a/ports/cortex_m0/keil/example_build/sample_threadx.uvprojx b/ports/cortex_m0/keil/example_build/sample_threadx.uvprojx new file mode 100644 index 00000000..a0e27af8 --- /dev/null +++ b/ports/cortex_m0/keil/example_build/sample_threadx.uvprojx @@ -0,0 +1,433 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + sample_threadx + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::.\ARMCC + 0 + + + ARMCM0 + ARM + ARM.CMSIS.5.7.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM0$Device\ARM\ARMCM0\Include\ARMCM0.h + + + + + + + + + + + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + sample_threadx + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 0 + -1 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + + + + ..\inc;..\..\..\..\common\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0x00000000 + 0x20000000 + + + + + --first __tx_vectors --entry=__main + + + + + + + + src + + + sample_threadx.c + 1 + .\sample_threadx.c + + + tx_initialize_low_level.s + 2 + .\tx_initialize_low_level.s + + + + + lib + + + tx.lib + 4 + .\Objects\tx.lib + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/ports/cortex_m0/keil/example_build/tx.uvoptx b/ports/cortex_m0/keil/example_build/tx.uvoptx new file mode 100644 index 00000000..d481141d --- /dev/null +++ b/ports/cortex_m0/keil/example_build/tx.uvoptx @@ -0,0 +1,2672 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + tx + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + + + BIN\UL2CM3.DLL + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + inc + 0 + 0 + 0 + 0 + + 1 + 1 + 5 + 0 + 0 + 0 + ..\inc\tx_port.h + tx_port.h + 0 + 0 + + + 1 + 2 + 5 + 0 + 0 + 0 + ..\..\..\..\common\inc\tx_api.h + tx_api.h + 0 + 0 + + + 1 + 3 + 5 + 0 + 0 + 0 + ..\..\..\..\common\inc\tx_block_pool.h + tx_block_pool.h + 0 + 0 + + + 1 + 4 + 5 + 0 + 0 + 0 + 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a/ports/cortex_m0/keil/example_build/tx.uvprojx b/ports/cortex_m0/keil/example_build/tx.uvprojx new file mode 100644 index 00000000..bd00f482 --- /dev/null +++ b/ports/cortex_m0/keil/example_build/tx.uvprojx @@ -0,0 +1,1453 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + tx + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::.\ARMCC + 0 + + + ARMCM0 + ARM + ARM.CMSIS.5.7.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM0$Device\ARM\ARMCM0\Include\ARMCM0.h + + + + + + + + + + + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + tx + 0 + 1 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 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..\..\..\..\common\src\tx_queue_performance_system_info_get.c + + + tx_queue_prioritize.c + 1 + ..\..\..\..\common\src\tx_queue_prioritize.c + + + tx_queue_receive.c + 1 + ..\..\..\..\common\src\tx_queue_receive.c + + + tx_queue_send.c + 1 + ..\..\..\..\common\src\tx_queue_send.c + + + tx_queue_send_notify.c + 1 + ..\..\..\..\common\src\tx_queue_send_notify.c + + + tx_semaphore_ceiling_put.c + 1 + ..\..\..\..\common\src\tx_semaphore_ceiling_put.c + + + tx_semaphore_cleanup.c + 1 + ..\..\..\..\common\src\tx_semaphore_cleanup.c + + + tx_semaphore_create.c + 1 + ..\..\..\..\common\src\tx_semaphore_create.c + + + tx_semaphore_delete.c + 1 + ..\..\..\..\common\src\tx_semaphore_delete.c + + + tx_semaphore_get.c + 1 + ..\..\..\..\common\src\tx_semaphore_get.c + + + tx_semaphore_info_get.c + 1 + ..\..\..\..\common\src\tx_semaphore_info_get.c + + + tx_semaphore_initialize.c + 1 + ..\..\..\..\common\src\tx_semaphore_initialize.c + + + tx_semaphore_performance_info_get.c + 1 + ..\..\..\..\common\src\tx_semaphore_performance_info_get.c + + + tx_semaphore_performance_system_info_get.c + 1 + ..\..\..\..\common\src\tx_semaphore_performance_system_info_get.c + + + tx_semaphore_prioritize.c + 1 + ..\..\..\..\common\src\tx_semaphore_prioritize.c + + + tx_semaphore_put.c + 1 + ..\..\..\..\common\src\tx_semaphore_put.c + + + tx_semaphore_put_notify.c + 1 + ..\..\..\..\common\src\tx_semaphore_put_notify.c + + + tx_thread_create.c + 1 + ..\..\..\..\common\src\tx_thread_create.c + + + tx_thread_delete.c + 1 + ..\..\..\..\common\src\tx_thread_delete.c + + + tx_thread_entry_exit_notify.c + 1 + ..\..\..\..\common\src\tx_thread_entry_exit_notify.c + + + tx_thread_identify.c + 1 + ..\..\..\..\common\src\tx_thread_identify.c + + + tx_thread_info_get.c + 1 + ..\..\..\..\common\src\tx_thread_info_get.c + + + tx_thread_initialize.c + 1 + ..\..\..\..\common\src\tx_thread_initialize.c + + + tx_thread_performance_info_get.c + 1 + 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..\..\..\..\common\src\tx_thread_stack_error_notify.c + + + tx_thread_suspend.c + 1 + ..\..\..\..\common\src\tx_thread_suspend.c + + + tx_thread_system_preempt_check.c + 1 + ..\..\..\..\common\src\tx_thread_system_preempt_check.c + + + tx_thread_system_resume.c + 1 + ..\..\..\..\common\src\tx_thread_system_resume.c + + + tx_thread_system_suspend.c + 1 + ..\..\..\..\common\src\tx_thread_system_suspend.c + + + tx_thread_terminate.c + 1 + ..\..\..\..\common\src\tx_thread_terminate.c + + + tx_thread_time_slice.c + 1 + ..\..\..\..\common\src\tx_thread_time_slice.c + + + tx_thread_time_slice_change.c + 1 + ..\..\..\..\common\src\tx_thread_time_slice_change.c + + + tx_thread_timeout.c + 1 + ..\..\..\..\common\src\tx_thread_timeout.c + + + tx_thread_wait_abort.c + 1 + ..\..\..\..\common\src\tx_thread_wait_abort.c + + + tx_time_get.c + 1 + ..\..\..\..\common\src\tx_time_get.c + + + tx_time_set.c + 1 + ..\..\..\..\common\src\tx_time_set.c + + + tx_timer_activate.c + 1 + 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tx_timer_thread_entry.c + 1 + ..\..\..\..\common\src\tx_timer_thread_entry.c + + + tx_trace_buffer_full_notify.c + 1 + ..\..\..\..\common\src\tx_trace_buffer_full_notify.c + + + tx_trace_disable.c + 1 + ..\..\..\..\common\src\tx_trace_disable.c + + + tx_trace_enable.c + 1 + ..\..\..\..\common\src\tx_trace_enable.c + + + tx_trace_event_filter.c + 1 + ..\..\..\..\common\src\tx_trace_event_filter.c + + + tx_trace_event_unfilter.c + 1 + ..\..\..\..\common\src\tx_trace_event_unfilter.c + + + tx_trace_initialize.c + 1 + ..\..\..\..\common\src\tx_trace_initialize.c + + + tx_trace_interrupt_control.c + 1 + ..\..\..\..\common\src\tx_trace_interrupt_control.c + + + tx_trace_isr_enter_insert.c + 1 + ..\..\..\..\common\src\tx_trace_isr_enter_insert.c + + + tx_trace_isr_exit_insert.c + 1 + ..\..\..\..\common\src\tx_trace_isr_exit_insert.c + + + tx_trace_object_register.c + 1 + ..\..\..\..\common\src\tx_trace_object_register.c + + + tx_trace_object_unregister.c + 1 + ..\..\..\..\common\src\tx_trace_object_unregister.c + + + tx_trace_user_event_insert.c + 1 + ..\..\..\..\common\src\tx_trace_user_event_insert.c + + + txe_block_allocate.c + 1 + ..\..\..\..\common\src\txe_block_allocate.c + + + txe_block_pool_create.c + 1 + ..\..\..\..\common\src\txe_block_pool_create.c + + + txe_block_pool_delete.c + 1 + ..\..\..\..\common\src\txe_block_pool_delete.c + + + txe_block_pool_info_get.c + 1 + ..\..\..\..\common\src\txe_block_pool_info_get.c + + + txe_block_pool_prioritize.c + 1 + ..\..\..\..\common\src\txe_block_pool_prioritize.c + + + txe_block_release.c + 1 + ..\..\..\..\common\src\txe_block_release.c + + + txe_byte_allocate.c + 1 + ..\..\..\..\common\src\txe_byte_allocate.c + + + txe_byte_pool_create.c + 1 + ..\..\..\..\common\src\txe_byte_pool_create.c + + + txe_byte_pool_delete.c + 1 + ..\..\..\..\common\src\txe_byte_pool_delete.c + + + txe_byte_pool_info_get.c + 1 + ..\..\..\..\common\src\txe_byte_pool_info_get.c + + + txe_byte_pool_prioritize.c + 1 + ..\..\..\..\common\src\txe_byte_pool_prioritize.c + + + txe_byte_release.c + 1 + ..\..\..\..\common\src\txe_byte_release.c + + + txe_event_flags_create.c + 1 + ..\..\..\..\common\src\txe_event_flags_create.c + + + txe_event_flags_delete.c + 1 + ..\..\..\..\common\src\txe_event_flags_delete.c + + + txe_event_flags_get.c + 1 + ..\..\..\..\common\src\txe_event_flags_get.c + + + txe_event_flags_info_get.c + 1 + ..\..\..\..\common\src\txe_event_flags_info_get.c + + + txe_event_flags_set.c + 1 + ..\..\..\..\common\src\txe_event_flags_set.c + + + txe_event_flags_set_notify.c + 1 + ..\..\..\..\common\src\txe_event_flags_set_notify.c + + + txe_mutex_create.c + 1 + ..\..\..\..\common\src\txe_mutex_create.c + + + txe_mutex_delete.c + 1 + ..\..\..\..\common\src\txe_mutex_delete.c + + + txe_mutex_get.c + 1 + ..\..\..\..\common\src\txe_mutex_get.c + + + txe_mutex_info_get.c + 1 + ..\..\..\..\common\src\txe_mutex_info_get.c + + + txe_mutex_prioritize.c + 1 + ..\..\..\..\common\src\txe_mutex_prioritize.c + + + txe_mutex_put.c + 1 + ..\..\..\..\common\src\txe_mutex_put.c + + + txe_queue_create.c + 1 + ..\..\..\..\common\src\txe_queue_create.c + + + txe_queue_delete.c + 1 + ..\..\..\..\common\src\txe_queue_delete.c + + + txe_queue_flush.c + 1 + ..\..\..\..\common\src\txe_queue_flush.c + + + txe_queue_front_send.c + 1 + ..\..\..\..\common\src\txe_queue_front_send.c + + + txe_queue_info_get.c + 1 + ..\..\..\..\common\src\txe_queue_info_get.c + + + txe_queue_prioritize.c + 1 + ..\..\..\..\common\src\txe_queue_prioritize.c + + + txe_queue_receive.c + 1 + ..\..\..\..\common\src\txe_queue_receive.c + + + txe_queue_send.c + 1 + ..\..\..\..\common\src\txe_queue_send.c + + + txe_queue_send_notify.c + 1 + ..\..\..\..\common\src\txe_queue_send_notify.c + + + txe_semaphore_ceiling_put.c + 1 + ..\..\..\..\common\src\txe_semaphore_ceiling_put.c + + + txe_semaphore_create.c + 1 + ..\..\..\..\common\src\txe_semaphore_create.c + + + txe_semaphore_delete.c + 1 + ..\..\..\..\common\src\txe_semaphore_delete.c + + + txe_semaphore_get.c + 1 + ..\..\..\..\common\src\txe_semaphore_get.c + + + txe_semaphore_info_get.c + 1 + ..\..\..\..\common\src\txe_semaphore_info_get.c + + + txe_semaphore_prioritize.c + 1 + ..\..\..\..\common\src\txe_semaphore_prioritize.c + + + txe_semaphore_put.c + 1 + ..\..\..\..\common\src\txe_semaphore_put.c + + + txe_semaphore_put_notify.c + 1 + ..\..\..\..\common\src\txe_semaphore_put_notify.c + + + txe_thread_create.c + 1 + ..\..\..\..\common\src\txe_thread_create.c + + + txe_thread_delete.c + 1 + ..\..\..\..\common\src\txe_thread_delete.c + + + txe_thread_entry_exit_notify.c + 1 + ..\..\..\..\common\src\txe_thread_entry_exit_notify.c + + + txe_thread_info_get.c + 1 + ..\..\..\..\common\src\txe_thread_info_get.c + + + txe_thread_preemption_change.c + 1 + ..\..\..\..\common\src\txe_thread_preemption_change.c + + + txe_thread_priority_change.c + 1 + ..\..\..\..\common\src\txe_thread_priority_change.c + + + txe_thread_relinquish.c + 1 + ..\..\..\..\common\src\txe_thread_relinquish.c + + + txe_thread_reset.c + 1 + ..\..\..\..\common\src\txe_thread_reset.c + + + txe_thread_resume.c + 1 + ..\..\..\..\common\src\txe_thread_resume.c + + + txe_thread_suspend.c + 1 + ..\..\..\..\common\src\txe_thread_suspend.c + + + txe_thread_terminate.c + 1 + ..\..\..\..\common\src\txe_thread_terminate.c + + + txe_thread_time_slice_change.c + 1 + ..\..\..\..\common\src\txe_thread_time_slice_change.c + + + txe_thread_wait_abort.c + 1 + ..\..\..\..\common\src\txe_thread_wait_abort.c + + + txe_timer_activate.c + 1 + ..\..\..\..\common\src\txe_timer_activate.c + + + txe_timer_change.c + 1 + ..\..\..\..\common\src\txe_timer_change.c + + + txe_timer_create.c + 1 + ..\..\..\..\common\src\txe_timer_create.c + + + txe_timer_deactivate.c + 1 + ..\..\..\..\common\src\txe_timer_deactivate.c + + + txe_timer_delete.c + 1 + ..\..\..\..\common\src\txe_timer_delete.c + + + txe_timer_info_get.c + 1 + ..\..\..\..\common\src\txe_timer_info_get.c + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/ports/cortex_m0/keil/example_build/tx_initialize_low_level.s b/ports/cortex_m0/keil/example_build/tx_initialize_low_level.s new file mode 100644 index 00000000..61c57b5f --- /dev/null +++ b/ports/cortex_m0/keil/example_build/tx_initialize_low_level.s @@ -0,0 +1,284 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_initialize.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IMPORT _tx_thread_system_stack_ptr + IMPORT _tx_initialize_unused_memory + IMPORT _tx_timer_interrupt + IMPORT __main + IMPORT |Image$$RO$$Limit| + IMPORT |Image$$RW$$Base| + IMPORT |Image$$ZI$$Base| + IMPORT |Image$$ZI$$Limit| + IMPORT __tx_PendSVHandler +; +; +SYSTEM_CLOCK EQU 6000000 +SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1) +; +; +;/* Setup the stack and heap areas. */ +; +STACK_SIZE EQU 0x00000400 +HEAP_SIZE EQU 0x00000000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +StackMem + SPACE STACK_SIZE +__initial_sp + + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +HeapMem + SPACE HEAP_SIZE +__heap_limit + + + AREA RESET, CODE, READONLY +; + EXPORT __tx_vectors +__tx_vectors + DCD __initial_sp ; Reset and system stack ptr + DCD Reset_Handler ; Reset goes to startup function + DCD __tx_NMIHandler ; NMI + DCD __tx_BadHandler ; HardFault + DCD 0 ; MemManage + DCD 0 ; BusFault + DCD 0 ; UsageFault + DCD 0 ; 7 + DCD 0 ; 8 + DCD 0 ; 9 + DCD 0 ; 10 + DCD __tx_SVCallHandler ; SVCall + DCD __tx_DBGHandler ; Monitor + DCD 0 ; 13 + DCD __tx_PendSVHandler ; PendSV + DCD __tx_SysTickHandler ; SysTick + DCD __tx_IntHandler ; Int 0 + DCD __tx_IntHandler ; Int 1 + DCD __tx_IntHandler ; Int 2 + DCD __tx_IntHandler ; Int 3 +; +; + AREA ||.text||, CODE, READONLY + EXPORT Reset_Handler +Reset_Handler + CPSID i + LDR R0, =__main + BX R0 + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-M0/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + EXPORT _tx_initialize_low_level +_tx_initialize_low_level +; +; /* Ensure that interrupts are disabled. */ +; + CPSID i ; Disable interrupts +; +; /* Set base of available memory to end of non-initialised RAM area. */ +; + LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer + LDR r1, =|Image$$ZI$$Limit| ; Build first free address + ADDS r1, r1, #4 ; + STR r1, [r0] ; Setup first unused memory pointer +; +; /* Setup Vector Table Offset Register. */ +; + LDR r0, =0xE000ED08 ; Build address of NVIC registers + LDR r1, =__tx_vectors ; Pickup address of vector table + STR r1, [r0] ; Set vector table address +; +; /* Enable the cycle count register. */ +; +; LDR r0, =0xE0001000 ; Build address of DWT register +; LDR r1, [r0] ; Pickup the current value +; MOVS r2, #1 +; ORRS r1, r1, r2 ; Set the CYCCNTENA bit +; STR r1, [r0] ; Enable the cycle count register +; +; /* Setup Vector Table Offset Register. */ +; + LDR r0, =0xE000E000 ; Build address of NVIC registers + LDR r2, =0xD08 ; Offset to vector base register + ADD r0, r0, r2 ; Build vector base register + LDR r1, =__tx_vectors ; Pickup address of vector table + STR r1, [r0] ; Set vector table address +; +; /* Set system stack pointer from vector value. */ +; + LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer + LDR r1, =__tx_vectors ; Pickup address of vector table + LDR r1, [r1] ; Pickup reset stack pointer + STR r1, [r0] ; Save system stack pointer +; +; /* Configure SysTick. */ +; + LDR r0, =0xE000E000 ; Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] ; Setup SysTick Reload Value + MOVS r1, #0x7 ; Build SysTick Control Enable Value + STR r1, [r0, #0x10] ; Setup SysTick Control +; +; /* Configure handler priorities. */ +; + LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM + LDR r0, =0xE000E000 ; Build address of NVIC registers + LDR r2, =0xD18 ; + ADD r0, r0, r2 ; + STR r1, [r0] ; Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv + LDR r0, =0xE000E000 ; Build address of NVIC registers + LDR r2, =0xD1C ; + ADD r0, r0, r2 ; + STR r1, [r0] ; Setup System Handlers 8-11 Priority Registers + ; Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM + LDR r0, =0xE000E000 ; Build address of NVIC registers + LDR r2, =0xD20 ; + ADD r0, r0, r2 ; + STR r1, [r0] ; Setup System Handlers 12-15 Priority Registers + ; Note: PnSV must be lowest priority, which is 0xFF +; +; /* Return to caller. */ +; + BX lr +;} +; +; +;/* Define initial heap/stack routine for the ARM RVCT startup code. +; This routine will set the initial stack and heap locations */ +; + EXPORT __user_initial_stackheap +__user_initial_stackheap + LDR R0, =HeapMem + LDR R1, =(StackMem + STACK_SIZE) + LDR R2, =(HeapMem + HEAP_SIZE) + LDR R3, =StackMem + BX LR +; +; +;/* Define shells for each of the unused vectors. */ +; + EXPORT __tx_BadHandler +__tx_BadHandler + B __tx_BadHandler + + EXPORT __tx_SVCallHandler +__tx_SVCallHandler + B __tx_SVCallHandler + + EXPORT __tx_IntHandler +__tx_IntHandler +; VOID InterruptHandler (VOID) +; { + PUSH {r0, lr} + +; /* Do interrupt handler work here */ +; /* .... */ + + POP {r0, r1} + MOV lr, r1 + BX lr +; } + + EXPORT SysTick_Handler + EXPORT __tx_SysTickHandler +__tx_SysTickHandler +SysTick_Handler +; VOID TimerInterruptHandler (VOID) +; { +; + PUSH {r0, lr} + BL _tx_timer_interrupt + POP {r0, r1} + MOV lr, r1 + BX lr +; } + + EXPORT __tx_NMIHandler +__tx_NMIHandler + B __tx_NMIHandler + + EXPORT __tx_DBGHandler +__tx_DBGHandler + B __tx_DBGHandler + + ALIGN + LTORG + END + + diff --git a/ports/cortex_m0/keil/inc/tx_port.h b/ports/cortex_m0/keil/inc/tx_port.h new file mode 100644 index 00000000..104fc4de --- /dev/null +++ b/ports/cortex_m0/keil/inc/tx_port.h @@ -0,0 +1,335 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-M0/AC5 */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX Cortex-M0 port. */ + +#define TX_INT_DISABLE 1 /* Disable interrupts */ +#define TX_INT_ENABLE 0 /* Enable interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) +#endif +#else +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif + +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +#ifndef TX_MISRA_ENABLE + +register unsigned int _ipsr __asm("ipsr"); + +#endif + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define the get system state macro. */ + +#ifndef TX_THREAD_GET_SYSTEM_STATE +#ifndef TX_MISRA_ENABLE +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _ipsr) +#else +ULONG _tx_misra_ipsr_get(VOID); +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get()) +#endif +#endif + + +/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value + indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h + for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always + zero after initialization for Cortex-M ports. */ + +#ifndef TX_THREAD_SYSTEM_RETURN_CHECK +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#endif + + +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to + prevent early scheduling on Cortex-M parts. */ + +#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifdef TX_DISABLE_INLINE + +UINT _tx_thread_interrupt_disable(VOID); +VOID _tx_thread_interrupt_restore(UINT previous_posture); + +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); + +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA unsigned int was_masked; +#define TX_DISABLE was_masked = __disable_irq(); +#define TX_RESTORE if (was_masked == 0) __enable_irq(); + +#define _tx_thread_system_return _tx_thread_system_return_inline + + +static void _tx_thread_system_return_inline(void) +{ +unsigned int was_masked; + + + /* Set PendSV to invoke ThreadX scheduler. */ + *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + if (_ipsr == 0) + { + was_masked = __disable_irq(); + __enable_irq(); + if (was_masked != 0) + __disable_irq(); + } +} +#endif + + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0/AC5 Version 6.0.1 *"; +#else +#ifdef TX_MISRA_ENABLE +extern CHAR _tx_version_id[100]; +#else +extern CHAR _tx_version_id[]; +#endif +#endif + + +#endif + + + + diff --git a/ports/cortex_m0/keil/readme_threadx.txt b/ports/cortex_m0/keil/readme_threadx.txt new file mode 100644 index 00000000..e34bd0e7 --- /dev/null +++ b/ports/cortex_m0/keil/readme_threadx.txt @@ -0,0 +1,149 @@ + Microsoft's Azure RTOS ThreadX for Cortex-M0 + + Using ARM Compiler 5 (AC5) and Keil Microcontroller Development Kit + +1. Building the ThreadX run-time Library + +Building the ThreadX library is easy, simply load the project file +tx.uvprojx, which is located inside the "example_build" directory. + +Once the ThreadX library files are displayed in the project window, +select the "Build Target" operation and observe the compilation and assembly +of the ThreadX library. This project build produces the ThreadX library +file tx.lib. + + +2. Demonstration System + +The ThreadX demonstration is designed to execute under the Keil simulator or +Cortex-M0 hardware. This demonstration is slightly smaller than typical ThreadX +demonstrations, and thus requires less than 7KB of Flash and less than 4KB of RAM. + +Building the demonstration is easy; simply open the ThreadX demonstration +project file sample_threadx.uvprojx, which is located inside the "example_build" +directory. + +Once open, select the "Build Target" operation and observe the compilation of +sample_threadx.c (which is the demonstration application) and linking with +tx.lib. The resulting file sample_threadx.axf is a binary file that can be downloaded +and executed under the uVision simulator or Cortex-M0 hardware. + +For simulator execution, the following memory regions need to be defined via +the "Debug -> Memory Map" dialog: + +0x20000000, 0x20080000 [check read and write access] +0xE0000000, 0xE8000000 [check read and write access] + + +3. System Initialization + +The entry point in ThreadX for the Cortex-M0 using AC5 tools is at label +__main. This is defined within the AC5 compiler's startup code. In +addition, this is where all static and global pre-set C variable +initialization processing takes place. + +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. + +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input +parameter to your application definition function, tx_application_define. + + +4. Register Usage and Stack Frames + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have the same stack frame in the Cortex-M0 version of +ThreadX. The top of the suspended thread's stack is pointed to by +tx_thread_stack_ptr in the associated thread control block TX_THREAD. + + + Stack Offset Stack Contents + + 0x00 r8 + 0x04 r9 + 0x08 r10 + 0x0C r11 + 0x10 r4 + 0x14 r5 + 0x18 r6 + 0x1C r7 + 0x20 r0 (Hardware stack starts here!!) + 0x24 r1 + 0x28 r2 + 0x2C r3 + 0x30 r12 + 0x34 lr + 0x38 pc + 0x3C xPSR + + +5. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the build_threadx.bat file to +remove the -g option and enable all compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +6. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-M0 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +6.1 Vector Area + +The Cortex-M0 vectors start at the label __tx_vectors. The application may modify +the vector area according to its needs. + +6.2 Managed Interrupts + +ISRs for Cortex-M can be written completely in C (or assembly language) without any +calls to _tx_thread_context_save or _tx_thread_context_restore. These ISRs are allowed +access to the ThreadX API that is available to ISRs. + +ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table): + +void your_C_isr(void) +{ + + /* ISR processing goes here, including any needed function calls. */ +} + +ISRs written in assembly language will take the form: + + EXPORT your_assembly_isr +your_assembly_isr + + PUSH {r0, lr} + + ; ISR processing goes here, including any needed function calls. + + POP {r0, r1} + MOV lr, r1 + BX lr + + +7. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M0 using AC5 tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_m0/keil/src/tx_thread_context_restore.s b/ports/cortex_m0/keil/src/tx_thread_context_restore.s new file mode 100644 index 00000000..4ef66308 --- /dev/null +++ b/ports/cortex_m0/keil/src/tx_thread_context_restore.s @@ -0,0 +1,101 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_exit + ENDIF +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-M0/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + EXPORT _tx_thread_context_restore +_tx_thread_context_restore + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + BL _tx_execution_isr_exit ; Call the ISR exit function + ENDIF +; +; /* Preemption has already been addressed - just return! */ +; + POP {r0} + MOV lr, r0 + BX lr +;} + ALIGN + LTORG + END + diff --git a/ports/cortex_m0/keil/src/tx_thread_context_save.s b/ports/cortex_m0/keil/src/tx_thread_context_save.s new file mode 100644 index 00000000..52fd2828 --- /dev/null +++ b/ports/cortex_m0/keil/src/tx_thread_context_save.s @@ -0,0 +1,101 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-M0/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + EXPORT _tx_thread_context_save +_tx_thread_context_save + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {r0, lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {r0, r1} ; Recover ISR lr + MOV lr, r1 + ENDIF +; +; /* Return to interrupt processing. */ +; + BX lr ; Return to interrupt processing caller +;} + ALIGN + LTORG + END + diff --git a/ports/cortex_m0/keil/src/tx_thread_interrupt_control.s b/ports/cortex_m0/keil/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..7b360417 --- /dev/null +++ b/ports/cortex_m0/keil/src/tx_thread_interrupt_control.s @@ -0,0 +1,87 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-M0/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + EXPORT _tx_thread_interrupt_control +_tx_thread_interrupt_control +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r1, PRIMASK + MSR PRIMASK, r0 + MOV r0, r1 + BX lr +; +;} + ALIGN + LTORG + END + diff --git a/ports/cortex_m0/keil/src/tx_thread_interrupt_disable.s b/ports/cortex_m0/keil/src/tx_thread_interrupt_disable.s new file mode 100644 index 00000000..b28496d6 --- /dev/null +++ b/ports/cortex_m0/keil/src/tx_thread_interrupt_disable.s @@ -0,0 +1,83 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-M0/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts and returning */ +;/* the previous interrupt lockout posture. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(UINT new_posture) +;{ + EXPORT _tx_thread_interrupt_disable +_tx_thread_interrupt_disable +; +; /* Return current interrupt lockout posture. */ +; + MRS r0, PRIMASK + CPSID i + BX lr +; +;} + END diff --git a/ports/cortex_m0/keil/src/tx_thread_interrupt_restore.s b/ports/cortex_m0/keil/src/tx_thread_interrupt_restore.s new file mode 100644 index 00000000..29d0f590 --- /dev/null +++ b/ports/cortex_m0/keil/src/tx_thread_interrupt_restore.s @@ -0,0 +1,82 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-M0/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for restoring the previous */ +;/* interrupt lockout posture. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* previous_posture Previous interrupt posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_interrupt_restore(UINT new_posture) +;{ + EXPORT _tx_thread_interrupt_restore +_tx_thread_interrupt_restore +; +; /* Restore previous interrupt lockout posture. */ +; + MSR PRIMASK, r0 + BX lr +; +;} + END diff --git a/ports/cortex_m0/keil/src/tx_thread_schedule.s b/ports/cortex_m0/keil/src/tx_thread_schedule.s new file mode 100644 index 00000000..abcb7c2c --- /dev/null +++ b/ports/cortex_m0/keil/src/tx_thread_schedule.s @@ -0,0 +1,278 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_execute_ptr + IMPORT _tx_timer_time_slice + IMPORT _tx_thread_system_stack_ptr + IMPORT _tx_thread_preempt_disable + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_thread_enter + IMPORT _tx_execution_thread_exit + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-M0/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + EXPORT _tx_thread_schedule +_tx_thread_schedule +; +; /* This function should only ever be called on Cortex-M0 +; from the first schedule request. Subsequent scheduling occurs +; from the PendSV handling routines below. */ +; +; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ +; + MOVS r0, #0 ; Build value for TX_FALSE + LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag + STR r0, [r2, #0] ; Clear preempt disable flag +; +; /* Enable interrupts */ +; + CPSIE i +; +; /* Enter the scheduler for the first time. */ +; + LDR r0, =0x10000000 ; Load PENDSVSET bit + LDR r1, =0xE000ED04 ; Load ICSR address + STR r0, [r1] ; Set PENDSVBIT in ICSR + DSB ; Complete all memory accesses + ISB ; Flush pipeline +; +; /* Wait here for the PendSV to take place. */ +; +__tx_wait_here + B __tx_wait_here ; Wait for the PendSV to happen +;} +; +; /* Generic context switch-out switch-in handler... Note that this handler is +; common for both PendSV and SVCall. */ +; + EXPORT PendSV_Handler + EXPORT __tx_PendSVHandler +PendSV_Handler +__tx_PendSVHandler +; +; /* Get current thread value and new thread pointer. */ +; +__tx_ts_handler + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + CPSID i ; Disable interrupts + PUSH {r0, lr} ; Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit ; Call the thread exit function + POP {r0, r1} ; Recover LR + MOV lr, r1 ; + CPSIE i ; Enable interrupts + ENDIF + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r2, =_tx_thread_execute_ptr ; Build execute thread pointer address + MOVS r3, #0 ; Build NULL value + LDR r1, [r0] ; Pickup current thread pointer +; +; /* Determine if there is a current thread to finish preserving. */ +; + CMP r1,#0 ; If NULL, skip preservation + BEQ __tx_ts_new ; +; +; /* Recover PSP and preserve current thread context. */ +; + STR r3, [r0] ; Set _tx_thread_current_ptr to NULL + MRS r3, PSP ; Pickup PSP pointer (thread's stack pointer) + SUBS r3, r3, #16 ; Allocate stack space + STM r3!, {r4-r7} ; Save its remaining registers (M3 Instruction: STMDB r12!, {r4-r11}) + MOV r4,r8 ; + MOV r5,r9 ; + MOV r6,r10 ; + MOV r7,r11 ; + SUBS r3, r3, #32 ; Allocate stack space + STM r3!, {r4-r7} ; + SUBS r3, r3, #20 ; Allocate stack space + MOV r5, LR ; + STR r5, [r3] ; Save LR on the stack + STR r3, [r1, #8] ; Save its stack pointer +; +; /* Determine if time-slice is active. If it isn't, skip time handling processing. */ +; + LDR r4, =_tx_timer_time_slice ; Build address of time-slice variable + LDR r5, [r4] ; Pickup current time-slice + CMP r5, #0 ; If not active, skip processing + BEQ __tx_ts_new ; +; +; /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ +; + STR r5, [r1, #24] ; Save current time-slice +; +; /* Clear the global time-slice. */ +; + MOVS r5, #0 ; Build clear value + STR r5, [r4] ; Clear time-slice +; +; +; /* Executing thread is now completely preserved!!! */ +; +__tx_ts_new +; +; /* Now we are looking for a new thread to execute! */ +; + CPSID i ; Disable interrupts + LDR r1, [r2] ; Is there another thread ready to execute? + CMP r1, #0 ; + BEQ __tx_ts_wait ; No, skip to the wait processing +; +; /* Yes, another thread is ready for else, make the current thread the new thread. */ +; + STR r1, [r0] ; Setup the current thread pointer to the new thread + CPSIE i ; Enable interrupts +; +; /* Increment the thread run count. */ +; +__tx_ts_restore + LDR r7, [r1, #4] ; Pickup the current thread run count + LDR r4, =_tx_timer_time_slice ; Build address of time-slice variable + LDR r5, [r1, #24] ; Pickup thread's current time-slice + ADDS r7, r7, #1 ; Increment the thread run count + STR r7, [r1, #4] ; Store the new run count +; +; /* Setup global time-slice with thread's current time-slice. */ +; + STR r5, [r4] ; Setup global time-slice + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + PUSH {r0, r1} ; Save r0/r1 + BL _tx_execution_thread_enter ; Call the thread execution enter function + POP {r0, r1} ; Recover r0/r1 + ENDIF +; +; /* Restore the thread context and PSP. */ +; + LDR r3, [r1, #8] ; Pickup thread's stack pointer + LDR r5, [r3] ; Recover saved LR + ADDS r3, r3, #4 ; Position past LR + MOV lr, r5 ; Restore LR + LDM r3!,{r4-r7} ; Recover thread's registers (r4-r11) + MOV r11,r7 ; + MOV r10,r6 ; + MOV r9,r5 ; + MOV r8,r4 ; + LDM r3!,{r4-r7} ; + MSR PSP, r3 ; Setup the thread's stack pointer +; +; /* Return to thread. */ +; + BX lr ; Return to thread! +; +; /* The following is the idle wait processing... in this case, no threads are ready for execution and the +; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +; are disabled to allow use of WFI for waiting for a thread to arrive. */ +; +__tx_ts_wait + CPSID i ; Disable interrupts + LDR r1, [r2] ; Pickup the next thread to execute pointer + STR r1, [r0] ; Store it in the current pointer + CMP r1, #0 ; If non-NULL, a new thread is ready! + BNE __tx_ts_ready ; + IF :DEF:TX_ENABLE_WFI + DSB ; Ensure no outstanding memory transactions + WFI ; Wait for interrupt + ISB ; Ensure pipeline is flushed + ENDIF +__tx_ts_ISB + CPSIE i ; Enable interrupts + B __tx_ts_wait ; Loop to continue waiting +; +; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +; already in the handler! */ +; +__tx_ts_ready + LDR r7, =0x08000000 ; Build clear PendSV value + LDR r5, =0xE000ED04 ; Build base NVIC address + STR r7, [r5] ; Clear any PendSV +; +; /* Re-enable interrupts and restore new thread. */ +; + CPSIE i ; Enable interrupts + B __tx_ts_restore ; Restore the thread + + ALIGN + LTORG + END + diff --git a/ports/cortex_m0/keil/src/tx_thread_stack_build.s b/ports/cortex_m0/keil/src/tx_thread_stack_build.s new file mode 100644 index 00000000..524eb9f5 --- /dev/null +++ b/ports/cortex_m0/keil/src/tx_thread_stack_build.s @@ -0,0 +1,146 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-M0/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + EXPORT _tx_thread_stack_build +_tx_thread_stack_build +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-M0 should look like the following after it is built: +; +; Stack Top: +; LR Interrupted LR (LR at time of PENDSV) +; r8 Initial value for r8 +; r9 Initial value for r9 +; r10 Initial value for r10 +; r11 Initial value for r11 +; r4 Initial value for r4 +; r5 Initial value for r5 +; r6 Initial value for r6 +; r7 Initial value for r7 +; r0 Initial value for r0 (Hardware stack starts here!!) +; r1 Initial value for r1 +; r2 Initial value for r2 +; r3 Initial value for r3 +; r12 Initial value for r12 +; lr Initial value for lr +; pc Initial value for pc +; xPSR Initial value for xPSR +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + MOVS r3, #0x7 ; + BICS r2, r2, r3 ; Align frame for 8-byte alignment + SUBS r2, r2, #68 ; Subtract frame size + LDR r3, =0xFFFFFFFD ; Build initial LR value + STR r3, [r2, #0] ; Save on the stack +; +; /* Actually build the stack frame. */ +; + MOVS r3, #0 ; Build initial register value + STR r3, [r2, #4] ; Store initial r8 + STR r3, [r2, #8] ; Store initial r9 + STR r3, [r2, #12] ; Store initial r10 + STR r3, [r2, #16] ; Store initial r11 + STR r3, [r2, #20] ; Store initial r4 + STR r3, [r2, #24] ; Store initial r5 + STR r3, [r2, #28] ; Store initial r6 + STR r3, [r2, #32] ; Store initial r7 +; +; /* Hardware stack follows. */ +; + STR r3, [r2, #36] ; Store initial r0 + STR r3, [r2, #40] ; Store initial r1 + STR r3, [r2, #44] ; Store initial r2 + STR r3, [r2, #48] ; Store initial r3 + STR r3, [r2, #52] ; Store initial r12 + LDR r3, =0xFFFFFFFF ; Poison EXC_RETURN value + STR r3, [r2, #56] ; Store initial lr + STR r1, [r2, #60] ; Store initial pc + LDR r3, =0x01000000 ; Only T-bit need be set + STR r3, [r2, #64] ; Store initial xPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block + BX lr ; Return to caller +;} + ALIGN + LTORG + END + diff --git a/ports/cortex_m0/keil/src/tx_thread_system_return.s b/ports/cortex_m0/keil/src/tx_thread_system_return.s new file mode 100644 index 00000000..a1e11054 --- /dev/null +++ b/ports/cortex_m0/keil/src/tx_thread_system_return.s @@ -0,0 +1,97 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-M0/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + EXPORT _tx_thread_system_return +_tx_thread_system_return +; +; /* Return to real scheduler via PendSV. Note that this routine is often +; replaced with in-line assembly in tx_port.h to improved performance. */ +; + LDR r0, =0x10000000 ; Load PENDSVSET bit + LDR r1, =0xE000ED04 ; Load NVIC base + STR r0, [r1] ; Set PENDSVBIT in ICSR + MRS r0, IPSR ; Pickup IPSR + CMP r0, #0 ; Is it a thread returning? + BNE _isr_context ; If ISR, skip interrupt enable + MRS r1, PRIMASK ; Thread context returning, pickup PRIMASK + CPSIE i ; Enable interrupts + MSR PRIMASK, r1 ; Restore original interrupt posture +_isr_context + BX lr ; Return to caller + NOP +;} + END + diff --git a/ports/cortex_m0/keil/src/tx_timer_interrupt.s b/ports/cortex_m0/keil/src/tx_timer_interrupt.s new file mode 100644 index 00000000..d5844d9c --- /dev/null +++ b/ports/cortex_m0/keil/src/tx_timer_interrupt.s @@ -0,0 +1,274 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_timer.h" +;#include "tx_thread.h" +; +; +;Define Assembly language external references... +; + IMPORT _tx_timer_time_slice + IMPORT _tx_timer_system_clock + IMPORT _tx_timer_current_ptr + IMPORT _tx_timer_list_start + IMPORT _tx_timer_list_end + IMPORT _tx_timer_expired_time_slice + IMPORT _tx_timer_expired + IMPORT _tx_thread_time_slice + IMPORT _tx_timer_expiration_process + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_execute_ptr + IMPORT _tx_thread_preempt_disable +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-M0/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + EXPORT _tx_timer_interrupt +_tx_timer_interrupt +; +; /* Upon entry to this routine, it is assumed that context save has already +; been called, and therefore the compiler scratch registers are available +; for use. */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + LDR r1, =_tx_timer_system_clock ; Pickup address of system clock + LDR r0, [r1, #0] ; Pickup system clock + ADDS r0, r0, #1 ; Increment system clock + STR r0, [r1, #0] ; Store new system clock +; +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice + LDR r2, [r3, #0] ; Pickup time-slice + CMP r2, #0 ; Is it non-active? + BEQ __tx_timer_no_time_slice ; Yes, skip time-slice processing +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; + SUBS r2, r2, #1 ; Decrement the time-slice + STR r2, [r3, #0] ; Store new time-slice value +; +; /* Check for expiration. */ +; if (__tx_timer_time_slice == 0) +; + CMP r2, #0 ; Has it expired? + BNE __tx_timer_no_time_slice ; No, skip expiration processing +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup address of expired flag + MOVS r0, #1 ; Build expired value + STR r0, [r3, #0] ; Set time-slice expiration flag +; +; } +; +__tx_timer_no_time_slice +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + LDR r1, =_tx_timer_current_ptr ; Pickup current timer pointer address + LDR r0, [r1, #0] ; Pickup current timer + LDR r2, [r0, #0] ; Pickup timer list entry + CMP r2, #0 ; Is there anything in the list? + BEQ __tx_timer_no_timer ; No, just increment the timer +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + LDR r3, =_tx_timer_expired ; Pickup expiration flag address + MOVS r2, #1 ; Build expired value + STR r2, [r3, #0] ; Set expired flag + B __tx_timer_done ; Finished timer processing +; +; } +; else +; { +__tx_timer_no_timer +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ADDS r0, r0, #4 ; Move to next timer +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + LDR r3, =_tx_timer_list_end ; Pickup addr of timer list end + LDR r2, [r3, #0] ; Pickup list end + CMP r0, r2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, skip wrap-around logic +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + LDR r3, =_tx_timer_list_start ; Pickup addr of timer list start + LDR r0, [r3, #0] ; Set current pointer to list start +; +__tx_timer_skip_wrap +; + STR r0, [r1, #0] ; Store new current timer pointer +; } +; +__tx_timer_done +; +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of expired flag + LDR r2, [r3, #0] ; Pickup time-slice expired flag + CMP r2, #0 ; Did a time-slice expire? + BNE __tx_something_expired ; If non-zero, time-slice expired + LDR r1, =_tx_timer_expired ; Pickup addr of other expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Did a timer expire? + BEQ __tx_timer_nothing_expired ; No, nothing expired +; +__tx_something_expired +; +; + PUSH {r0, lr} ; Save the lr register on the stack + ; and save r0 just to keep 8-byte alignment +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + LDR r1, =_tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Check for timer expiration + BEQ __tx_timer_dont_activate ; If not set, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BL _tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r2, [r3, #0] ; Pickup the actual flag + CMP r2, #0 ; See if the flag is set + BEQ __tx_timer_not_ts_expiration ; No, skip time-slice processing +; +; /* Time slice interrupted thread. */ +; _tx_thread_time_slice(); +; + BL _tx_thread_time_slice ; Call time-slice processing + LDR r0, =_tx_thread_preempt_disable ; Build address of preempt disable flag + LDR r1, [r0] ; Is the preempt disable flag set? + CMP r1, #0 ; + BNE __tx_timer_skip_time_slice ; Yes, skip the PendSV logic + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup the current thread pointer + LDR r2, =_tx_thread_execute_ptr ; Build execute thread pointer address + LDR r3, [r2] ; Pickup the execute thread pointer + LDR r0, =0xE000ED04 ; Build address of control register + LDR r2, =0x10000000 ; Build value for PendSV bit + CMP r1, r3 ; Are they the same? + BEQ __tx_timer_skip_time_slice ; If the same, there was no time-slice performed + STR r2, [r0] ; Not the same, issue the PendSV for preemption +__tx_timer_skip_time_slice +; +; } +; +__tx_timer_not_ts_expiration +; + POP {r0, r1} ; Recover lr register (r0 is just there for + MOV lr, r1 ; the 8-byte stack alignment +; +; } +; +__tx_timer_nothing_expired + + DSB ; Complete all memory access + BX lr ; Return to caller +; +;} + ALIGN + LTORG + END + diff --git a/ports/cortex_m3/ac6/example_build/sample_threadx/.cproject b/ports/cortex_m3/ac6/example_build/sample_threadx/.cproject new file mode 100644 index 00000000..30ce5816 --- /dev/null +++ b/ports/cortex_m3/ac6/example_build/sample_threadx/.cproject @@ -0,0 +1,238 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_m3/ac6/example_build/sample_threadx/.project b/ports/cortex_m3/ac6/example_build/sample_threadx/.project new file mode 100644 index 00000000..725328bd --- /dev/null +++ b/ports/cortex_m3/ac6/example_build/sample_threadx/.project @@ -0,0 +1,27 @@ + + + sample_threadx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.arm.debug.ds.nature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/ports/cortex_m3/ac6/example_build/sample_threadx/.settings/language.settings.xml b/ports/cortex_m3/ac6/example_build/sample_threadx/.settings/language.settings.xml new file mode 100644 index 00000000..9b2533da --- /dev/null +++ b/ports/cortex_m3/ac6/example_build/sample_threadx/.settings/language.settings.xml @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_m3/ac6/example_build/sample_threadx/cortex-m3_tx.launch b/ports/cortex_m3/ac6/example_build/sample_threadx/cortex-m3_tx.launch new file mode 100644 index 00000000..086c28d2 --- /dev/null +++ b/ports/cortex_m3/ac6/example_build/sample_threadx/cortex-m3_tx.launch @@ -0,0 +1,160 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_m3/ac6/example_build/sample_threadx/exceptions.c b/ports/cortex_m3/ac6/example_build/sample_threadx/exceptions.c new file mode 100644 index 00000000..94c87d7a --- /dev/null +++ b/ports/cortex_m3/ac6/example_build/sample_threadx/exceptions.c @@ -0,0 +1,96 @@ +/* +** Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. +** Use, modification and redistribution of this file is subject to your possession of a +** valid End User License Agreement for the Arm Product of which these examples are part of +** and your compliance with all applicable terms and conditions of such licence agreement. +*/ + +/* This file contains the default exception handlers and vector table. +All exceptions are handled in Handler mode. Processor state is automatically +pushed onto the stack when an exception occurs, and popped from the stack at +the end of the handler */ + + +/* Exception Handlers */ +/* Marking as __attribute__((interrupt)) avoids them being accidentally called from elsewhere */ + +__attribute__((interrupt)) void NMIException(void) +{ while(1); } + +__attribute__((interrupt)) void HardFaultException(void) +{ while(1); } + +__attribute__((interrupt)) void MemManageException(void) +{ while(1); } + +__attribute__((interrupt)) void BusFaultException(void) +{ while(1); } + +__attribute__((interrupt)) void UsageFaultException(void) +{ while(1); } + +__attribute__((interrupt)) void DebugMonitor(void) +{ while(1); } + +void __tx_SVCallHandler(void); + +void __tx_PendSVHandler(void); + +void SysTick_Handler(void); + +__attribute__((interrupt)) void InterruptHandler(void) +{ while(1); } + + +/* typedef for the function pointers in the vector table */ +typedef void(* const ExecFuncPtr)(void) __attribute__((interrupt)); + +/* Linker-generated Stack Base address */ +#ifdef TWO_REGION +extern unsigned int Image$$ARM_LIB_STACK$$ZI$$Limit; /* for Two Region model */ +#else +extern unsigned int Image$$ARM_LIB_STACKHEAP$$ZI$$Limit; /* for (default) One Region model */ +#endif + +/* Entry point for C run-time initialization */ +extern int __main(void); + + +/* Vector table +Create a named ELF section for the vector table that can be placed in a scatter file. +The first two entries are: + Initial SP = |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit| for (default) One Region model + or |Image$$ARM_LIB_STACK$$ZI$$Limit| for Two Region model + Initial PC= &__main (with LSB set to indicate Thumb) +*/ + +ExecFuncPtr vector_table[] __attribute__((section("vectors"))) = { + /* Configure Initial Stack Pointer using linker-generated symbol */ +#ifdef TWO_REGION + #pragma import(__use_two_region_memory) + (ExecFuncPtr)&Image$$ARM_LIB_STACK$$ZI$$Limit, +#else /* (default) One Region model */ + (ExecFuncPtr)&Image$$ARM_LIB_STACKHEAP$$ZI$$Limit, +#endif + (ExecFuncPtr)__main, /* Initial PC, set to entry point */ + NMIException, + HardFaultException, + MemManageException, + BusFaultException, + UsageFaultException, + 0, 0, 0, 0, /* Reserved */ + __tx_SVCallHandler, + DebugMonitor, + 0, /* Reserved */ + __tx_PendSVHandler, + SysTick_Handler, + + /* Add up to 240 interrupt handlers, starting here... */ + InterruptHandler, + InterruptHandler, /* Some dummy interrupt handlers */ + InterruptHandler + /* + : + */ +}; + diff --git a/ports/cortex_m3/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_m3/ac6/example_build/sample_threadx/sample_threadx.c new file mode 100644 index 00000000..597f373c --- /dev/null +++ b/ports/cortex_m3/ac6/example_build/sample_threadx/sample_threadx.c @@ -0,0 +1,370 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; +UCHAR memory_area[DEMO_BYTE_POOL_SIZE]; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_m3/ac6/example_build/sample_threadx/sample_threadx.scat b/ports/cortex_m3/ac6/example_build/sample_threadx/sample_threadx.scat new file mode 100644 index 00000000..8578282d --- /dev/null +++ b/ports/cortex_m3/ac6/example_build/sample_threadx/sample_threadx.scat @@ -0,0 +1,46 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m0 -xc + +;******************************************************* +; Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. +; Use, modification and redistribution of this file is subject to your possession of a +; valid End User License Agreement for the Arm Product of which these examples are part of +; and your compliance with all applicable terms and conditions of such licence agreement. +;******************************************************* + +; Scatter-file for Cortex-M0 bare-metal example + +; This scatter-file places the vector table, application code, data, stacks and heap at suitable addresses in the memory map. + +; The vector table is placed first at the start of the image. +; Code starts after the last entry in the vector table. +; Data is placed at an address that must correspond to RAM. +; Stack and Heap are placed using ARM_LIB_STACKHEAP, to eliminate the need to set stack-base or heap-base in the debugger. +; System Control Space registers appear at their architecturally-defined addresses, based at 0xE000E000. + + +LOAD_REGION 0x00000000 +{ + VECTORS +0 0xC0 ; 16 exceptions + up to 32 interrupts, 4 bytes each entry == 0xC0 + { + exceptions.o (vectors, +FIRST) ; from exceptions.c + } + + ; Code is placed immediately (+0) after the previous root region + ; (so code region will also be a root region) + CODE +0 + { + * (+RO) ; All program code, including library code + } + + DATA +0 + { + * (+RW, +ZI) ; All RW and ZI data + } + + ; Heap grows upwards from start of this region and + ; Stack grows downwards from end of this region + ; The Main Stack Pointer is initialized on reset to the top addresses of this region + ARM_LIB_STACKHEAP +0 EMPTY 0x1000 + { + } +} diff --git a/ports/cortex_m3/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_m3/ac6/example_build/sample_threadx/tx_initialize_low_level.S new file mode 100644 index 00000000..058d4981 --- /dev/null +++ b/ports/cortex_m3/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -0,0 +1,242 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Initialize */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_initialize.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global _tx_timer_interrupt + .global __main + .global __tx_SVCallHandler + .global __tx_PendSVHandler + .global __tx_NMIHandler @ NMI + .global __tx_BadHandler @ HardFault + .global __tx_SVCallHandler @ SVCall + .global __tx_DBGHandler @ Monitor + .global __tx_PendSVHandler @ PendSV + .global __tx_SysTickHandler @ SysTick + .global __tx_IntHandler @ Int 0 +@ +@ +SYSTEM_CLOCK = 6000000 +SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) + + .text 32 + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_initialize_low_level Cortex-M3/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for any low-level processor */ +@/* initialization, including setting up interrupt vectors, setting */ +@/* up a periodic timer interrupt source, saving the system stack */ +@/* pointer for use in ISR processing later, and finding the first */ +@/* available RAM memory address for tx_application_define. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_initialize_low_level(VOID) +@{ + .global _tx_initialize_low_level + .thumb_func +_tx_initialize_low_level: +@ +@ /* Disable interrupts during ThreadX initialization. */ +@ + CPSID i +@ +@ /* Set base of available memory to end of non-initialised RAM area. */ +@ + LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer + LDR r1, =Image$$ARM_LIB_STACKHEAP$$ZI$$Limit @ Build first free address + ADD r1, r1, #4 @ + STR r1, [r0] @ Setup first unused memory pointer +@ +@ /* Setup Vector Table Offset Register. */ +@ + MOV r0, #0xE000E000 @ Build address of NVIC registers + LDR r1, =vector_table @ Pickup address of vector table + STR r1, [r0, #0xD08] @ Set vector table address +@ +@ /* Set system stack pointer from vector value. */ +@ + LDR r0, =_tx_thread_system_stack_ptr @ Build address of system stack pointer + LDR r1, =vector_table @ Pickup address of vector table + LDR r1, [r1] @ Pickup reset stack pointer + STR r1, [r0] @ Save system stack pointer +@ +@ /* Enable the cycle count register. */ +@ + LDR r0, =0xE0001000 @ Build address of DWT register + LDR r1, [r0] @ Pickup the current value + ORR r1, r1, #1 @ Set the CYCCNTENA bit + STR r1, [r0] @ Enable the cycle count register +@ +@ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ +@ + MOV r0, #0xE000E000 @ Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] @ Setup SysTick Reload Value + MOV r1, #0x7 @ Build SysTick Control Enable Value + STR r1, [r0, #0x10] @ Setup SysTick Control +@ +@ /* Configure handler priorities. */ +@ + LDR r1, =0x00000000 @ Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] @ Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 @ SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] @ Setup System Handlers 8-11 Priority Registers + @ Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] @ Setup System Handlers 12-15 Priority Registers + @ Note: PnSV must be lowest priority, which is 0xFF + +@ +@ /* Return to caller. */ +@ + BX lr +@} +@ + +@/* Define shells for each of the unused vectors. */ +@ + .global __tx_BadHandler + .thumb_func +__tx_BadHandler: + B __tx_BadHandler + +@ /* added to catch the hardfault */ + + .global __tx_HardfaultHandler + .thumb_func +__tx_HardfaultHandler: + B __tx_HardfaultHandler + + +@ /* added to catch the SVC */ + + .global __tx_SVCallHandler + .thumb_func +__tx_SVCallHandler: + B __tx_SVCallHandler + + +@ /* Generic interrupt handler template */ + .global __tx_IntHandler + .thumb_func +__tx_IntHandler: +@ VOID InterruptHandler (VOID) +@ { + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter @ Call the ISR enter function +#endif + +@ /* Do interrupt handler work here */ +@ /* BL .... */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif + POP {r0, lr} + BX LR +@ } + +@ /* System Tick timer interrupt handler */ + .global __tx_SysTickHandler + .global SysTick_Handler + .thumb_func +__tx_SysTickHandler: + .thumb_func +SysTick_Handler: +@ VOID TimerInterruptHandler (VOID) +@ { +@ + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter @ Call the ISR enter function +#endif + BL _tx_timer_interrupt +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif + POP {r0, lr} + BX LR +@ } + + +@ /* NMI, DBG handlers */ + .global __tx_NMIHandler + .thumb_func +__tx_NMIHandler: + B __tx_NMIHandler + + .global __tx_DBGHandler + .thumb_func +__tx_DBGHandler: + B __tx_DBGHandler + + + + + diff --git a/ports/cortex_m3/ac6/example_build/tx/.cproject b/ports/cortex_m3/ac6/example_build/tx/.cproject new file mode 100644 index 00000000..c3508895 --- /dev/null +++ b/ports/cortex_m3/ac6/example_build/tx/.cproject @@ -0,0 +1,212 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_m3/ac6/example_build/tx/.project b/ports/cortex_m3/ac6/example_build/tx/.project new file mode 100644 index 00000000..863ca5cb --- /dev/null +++ b/ports/cortex_m3/ac6/example_build/tx/.project @@ -0,0 +1,48 @@ + + + tx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + inc_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/inc + + + inc_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/inc + + + src_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/src + + + src_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/src + + + diff --git a/ports/cortex_m3/ac6/example_build/tx/.settings/language.settings.xml b/ports/cortex_m3/ac6/example_build/tx/.settings/language.settings.xml new file mode 100644 index 00000000..3a8e2610 --- /dev/null +++ b/ports/cortex_m3/ac6/example_build/tx/.settings/language.settings.xml @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_m3/ac6/inc/tx_port.h b/ports/cortex_m3/ac6/inc/tx_port.h new file mode 100644 index 00000000..fcf9412f --- /dev/null +++ b/ports/cortex_m3/ac6/inc/tx_port.h @@ -0,0 +1,357 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-M3/AC6 */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX Cortex-M7 port. */ + +#define TX_INT_DISABLE 1 /* Disable interrupts */ +#define TX_INT_ENABLE 0 /* Enable interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0 + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define the get system state macro. */ + +#ifndef TX_THREAD_GET_SYSTEM_STATE +#ifndef TX_MISRA_ENABLE + +__attribute__( ( always_inline ) ) static inline unsigned int __get_ipsr_value(void) +{ + +unsigned int ipsr_value; + + __asm__ volatile (" MRS %0,IPSR ": "=r" (ipsr_value) ); + return(ipsr_value); +} + + +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | __get_ipsr_value()) +#else +ULONG _tx_misra_ipsr_get(VOID); +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get()) +#endif +#endif + + +/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value + indicates that _tx_thread_system_return should not be called. */ + +#ifndef TX_THREAD_SYSTEM_RETURN_CHECK +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#endif + +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to + prevent early scheduling on Cortex-M parts. */ + +#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; + + +/* This ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + +#endif + + +#ifndef TX_DISABLE_INLINE + +/* Define AC6 specific macros, with in-line assembly for performance. */ + +__attribute__( ( always_inline ) ) static inline unsigned int __disable_interrupts(void) +{ + +unsigned int primask_value; + + __asm__ volatile (" MRS %0,PRIMASK ": "=r" (primask_value) ); + __asm__ volatile (" CPSID i" : : : "memory" ); + return(primask_value); +} + +__attribute__( ( always_inline ) ) static inline void __restore_interrupts(unsigned int primask_value) +{ + + __asm__ volatile (" MSR PRIMASK,%0": : "r" (primask_value): "memory" ); +} + +__attribute__( ( always_inline ) ) static inline unsigned int __get_primask_value(void) +{ + +unsigned int primask_value; + + __asm__ volatile (" MRS %0,PRIMASK ": "=r" (primask_value) ); + return(primask_value); +} + +__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void) +{ + + __asm__ volatile (" CPSIE i": : : "memory" ); +} + + +__attribute__( ( always_inline ) ) static inline void _tx_thread_system_return_inline(void) +{ +unsigned int interrupt_save; + + *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + if (__get_ipsr_value() == 0) + { + interrupt_save = __get_primask_value(); + __enable_interrupts(); + __restore_interrupts(interrupt_save); + } +} + + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = __disable_interrupts(); +#define TX_RESTORE __restore_interrupts(interrupt_save); + + +/* Redefine _tx_thread_system_return for improved performance. */ + +#define _tx_thread_system_return _tx_thread_system_return_inline + + +#else + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); +#define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); +#endif + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/AC6 Version 6.0.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + + + + + diff --git a/ports/cortex_m3/ac6/readme_threadx.txt b/ports/cortex_m3/ac6/readme_threadx.txt new file mode 100644 index 00000000..d248b45f --- /dev/null +++ b/ports/cortex_m3/ac6/readme_threadx.txt @@ -0,0 +1,156 @@ + Microsoft's Azure RTOS ThreadX for Cortex-M3 + + Using the AC6 Tools + +1. Import the ThreadX Projects + +In order to build the ThreadX library and the ThreadX demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +into your DS workspace. + + +2. Building the ThreadX run-time Library + +Building the ThreadX library is easy; simply right-click the Eclipse project +"tx" and then select the "Build Project" button. You should now observe the compilation +and assembly of the ThreadX library. This project build produces the ThreadX +library file tx.a. + + +3. Demonstration System + +The ThreadX demonstration is designed to execute under the DS debugger on the +MPS2_Cortex_M3 Bare Metal simulator. + +Building the demonstration is easy; simply right-click the Eclipse project +"sample_threadx" and then select the "Build Project" button. You should now observe +the compilation and assembly of the ThreadX demonstration. This project build produces +the ThreadX library file sample_threadx.axf. Next, expand the demo ThreadX project folder +in the Project Explorer window, right-click on the 'cortex-m3_tx.launch' file, click +'Debug As', and then click 'cortex-m3_tx' from the submenu. This will cause the +debugger to load the sample_threadx.axf ELF file and run to main. You are now ready +to execute the ThreadX demonstration. + + +4. System Initialization + +The entry point in ThreadX for the Cortex-M3 using AC6 tools uses the standard AC6 +Cortex-M3 reset sequence. From the reset vector the C runtime will be initialized. + +The ThreadX tx_initialize_low_level.S file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. + +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input +parameter to your application definition function, tx_application_define. + + +5. Register Usage and Stack Frames + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have the same stack frame in the Cortex-M3 version of +ThreadX. The top of the suspended thread's stack is pointed to by +tx_thread_stack_ptr in the associated thread control block TX_THREAD. + + + Stack Offset Stack Contents + + 0x00 r4 + 0x04 r5 + 0x08 r6 + 0x0C r7 + 0x10 r8 + 0x14 r9 + 0x18 r10 + 0x1C r11 + 0x20 r0 (Hardware stack starts here!!) + 0x24 r1 + 0x28 r2 + 0x2C r3 + 0x30 r12 + 0x34 lr + 0x38 pc + 0x3C xPSR + + +6. Improving Performance + +The distribution version of ThreadX is built without any compiler optimizations. +This makes it easy to debug because you can trace or set breakpoints inside of +ThreadX itself. Of course, this costs some performance. To make it run faster, +you can change the build_threadx.bat file to remove the -g option and enable +all compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-M3 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +7.1 Vector Area + +The Cortex-M3 vectors start at the label __tx_vectors or similar. The application may modify +the vector area according to its needs. There is code in tx_initialize_low_level() that will +configure the vector base register. + + +7.2 Managed Interrupts + +ISRs can be written completely in C (or assembly language) without any calls to +_tx_thread_context_save or _tx_thread_context_restore. These ISRs are allowed access to the +ThreadX API that is available to ISRs. + +ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table): + +void your_C_isr(void) +{ + + /* ISR processing goes here, including any needed function calls. */ +} + +ISRs written in assembly language will take the form: + + + .global your_assembly_isr + .thumb_func +your_assembly_isr: +; VOID your_assembly_isr(VOID) +; { + PUSH {r0, lr} +; +; /* Do interrupt handler work here */ +; /* BL */ + + POP {r0, lr} + BX lr +; } + +Note: the Cortex-M3 requires exception handlers to be thumb labels, this implies bit 0 set. +To accomplish this, the declaration of the label has to be preceded by the assembler directive +.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to +be inserted in the correct location in the interrupt vector table. This table is typically +located in either your runtime startup file or in the tx_initialize_low_level.S file. + + +8. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M3 using AC6 tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_m3/ac6/src/tx_thread_context_restore.S b/ports/cortex_m3/ac6/src/tx_thread_context_restore.S new file mode 100644 index 00000000..a4e0b8e2 --- /dev/null +++ b/ports/cortex_m3/ac6/src/tx_thread_context_restore.S @@ -0,0 +1,95 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_system_stack_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable +@ +@ + .text + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_restore Cortex-M3/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function restores the interrupt context if it is processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs Interrupt Service Routines */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_restore(VOID) +@{ + .global _tx_thread_context_restore + .thumb_func +_tx_thread_context_restore: +@ +@ /* Not needed for this port - just return! */ + BX lr +@} + diff --git a/ports/cortex_m3/ac6/src/tx_thread_context_save.S b/ports/cortex_m3/ac6/src/tx_thread_context_save.S new file mode 100644 index 00000000..24e73026 --- /dev/null +++ b/ports/cortex_m3/ac6/src/tx_thread_context_save.S @@ -0,0 +1,88 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr +@ +@ + .text + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_save Cortex-M3/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_save(VOID) +@{ + .global _tx_thread_context_save + .thumb_func +_tx_thread_context_save: +@ +@ /* Not needed for this port - just return! */ + BX lr +@} diff --git a/ports/cortex_m3/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_m3/ac6/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..e24e3200 --- /dev/null +++ b/ports/cortex_m3/ac6/src/tx_thread_interrupt_control.S @@ -0,0 +1,92 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ + + +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ + +@/* #define TX_SOURCE_CODE */ + + +@/* Include necessary system files. */ + +@/* #include "tx_api.h" + #include "tx_thread.h" */ + + + .text 32 + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_control Cortex-M3/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for changing the interrupt lockout */ +@/* posture of the system. */ +@/* */ +@/* INPUT */ +@/* */ +@/* new_posture New interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@/* UINT _tx_thread_interrupt_control(UINT new_posture) +{ */ + .global _tx_thread_interrupt_control + .thumb_func +_tx_thread_interrupt_control: + +@/* Pickup current interrupt lockout posture. */ + + MRS r1, PRIMASK @ Pickup current interrupt lockout + +@/* Apply the new interrupt posture. */ + + MSR PRIMASK, r0 @ Apply the new interrupt lockout + MOV r0, r1 @ Transfer old to return register + BX lr @ Return to caller + +@/* } */ + + + diff --git a/ports/cortex_m3/ac6/src/tx_thread_schedule.S b/ports/cortex_m3/ac6/src/tx_thread_schedule.S new file mode 100644 index 00000000..71f2a673 --- /dev/null +++ b/ports/cortex_m3/ac6/src/tx_thread_schedule.S @@ -0,0 +1,250 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ + .global _tx_thread_current_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_system_stack_ptr +@ +@ + .text + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_schedule Cortex-M3/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function waits for a thread control block pointer to appear in */ +@/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +@/* in the variable, the corresponding thread is resumed. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* _tx_thread_system_return Return to system from thread */ +@/* _tx_thread_context_restore Restore thread's context */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_schedule(VOID) +@{ + .global _tx_thread_schedule + .thumb_func +_tx_thread_schedule: +@ +@ /* This function should only ever be called on Cortex-M3 +@ from the first schedule request. Subsequent scheduling occurs +@ from the PendSV handling routines below. */ +@ +@ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ +@ + MOV r0, #0 @ Build value for TX_FALSE + LDR r2, =_tx_thread_preempt_disable @ Build address of preempt disable flag + STR r0, [r2, #0] @ Clear preempt disable flag +@ +@ /* Enable interrupts */ +@ + CPSIE i +@ +@ /* Enter the scheduler for the first time. */ +@ + MOV r0, #0x10000000 @ Load PENDSVSET bit + MOV r1, #0xE000E000 @ Load NVIC base + STR r0, [r1, #0xD04] @ Set PENDSVBIT in ICSR + DSB @ Complete all memory accesses + ISB @ Flush pipeline +@ +@ /* Wait here for the PendSV to take place. */ +@ +__tx_wait_here: + B __tx_wait_here @ Wait for the PendSV to happen +@} +@ +@ /* Generic context switch-out switch-in handler... Note that this handler is +@ common for both PendSV and SVCall. */ +@ + .global PendSV_Handler + .global __tx_PendSVHandler + .thumb_func +PendSV_Handler: + .thumb_func +__tx_PendSVHandler: +@ +@ /* Get current thread value and new thread pointer. */ +@ +__tx_ts_handler: + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the thread exit function to indicate the thread is no longer executing. */ +@ + CPSID i @ Disable interrupts + PUSH {r0, lr} @ Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit @ Call the thread exit function + POP {r0, lr} @ Recover LR + CPSIE i @ Enable interrupts +#endif + LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address + LDR r2, =_tx_thread_execute_ptr @ Build execute thread pointer address + MOV r3, #0 @ Build NULL value + LDR r1, [r0] @ Pickup current thread pointer +@ +@ /* Determine if there is a current thread to finish preserving. */ +@ + CBZ r1, __tx_ts_new @ If NULL, skip preservation +@ +@ /* Recover PSP and preserve current thread context. */ +@ + STR r3, [r0] @ Set _tx_thread_current_ptr to NULL + MRS r12, PSP @ Pickup PSP pointer (thread's stack pointer) + STMDB r12!, {r4-r11} @ Save its remaining registers + LDR r4, =_tx_timer_time_slice @ Build address of time-slice variable + STMDB r12!, {LR} @ Save LR on the stack +@ +@ /* Determine if time-slice is active. If it isn't, skip time handling processing. */ +@ + LDR r5, [r4] @ Pickup current time-slice + STR r12, [r1, #8] @ Save the thread stack pointer + CBZ r5, __tx_ts_new @ If not active, skip processing +@ +@ /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ +@ + STR r5, [r1, #24] @ Save current time-slice +@ +@ /* Clear the global time-slice. */ +@ + STR r3, [r4] @ Clear time-slice +@ +@ +@ /* Executing thread is now completely preserved!!! */ +@ +__tx_ts_new: +@ +@ /* Now we are looking for a new thread to execute! */ +@ + CPSID i @ Disable interrupts + LDR r1, [r2] @ Is there another thread ready to execute? + CBZ r1, __tx_ts_wait @ No, skip to the wait processing +@ +@ /* Yes, another thread is ready for else, make the current thread the new thread. */ +@ + STR r1, [r0] @ Setup the current thread pointer to the new thread + CPSIE i @ Enable interrupts +@ +@ /* Increment the thread run count. */ +@ +__tx_ts_restore: + LDR r7, [r1, #4] @ Pickup the current thread run count + LDR r4, =_tx_timer_time_slice @ Build address of time-slice variable + LDR r5, [r1, #24] @ Pickup thread's current time-slice + ADD r7, r7, #1 @ Increment the thread run count + STR r7, [r1, #4] @ Store the new run count +@ +@ /* Setup global time-slice with thread's current time-slice. */ +@ + STR r5, [r4] @ Setup global time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the thread entry function to indicate the thread is executing. */ +@ + PUSH {r0, r1} @ Save r0/r1 + BL _tx_execution_thread_enter @ Call the thread execution enter function + POP {r0, r1} @ Recover r3 +#endif +@ +@ /* Restore the thread context and PSP. */ +@ + LDR r12, [r1, #8] @ Pickup thread's stack pointer + LDMIA r12!, {LR} @ Pickup LR + LDMIA r12!, {r4-r11} @ Recover thread's registers + MSR PSP, r12 @ Setup the thread's stack pointer +@ +@ /* Return to thread. */ +@ + BX lr @ Return to thread! +@ +@ /* The following is the idle wait processing... in this case, no threads are ready for execution and the +@ system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +@ are disabled to allow use of WFI for waiting for a thread to arrive. */ +@ +__tx_ts_wait: + CPSID i @ Disable interrupts + LDR r1, [r2] @ Pickup the next thread to execute pointer + STR r1, [r0] @ Store it in the current pointer + CBNZ r1, __tx_ts_ready @ If non-NULL, a new thread is ready! +#ifdef TX_ENABLE_WFI + DSB @ Ensure no outstanding memory transactions + WFI @ Wait for interrupt + ISB @ Ensure pipeline is flushed +#endif + CPSIE i @ Enable interrupts + B __tx_ts_wait @ Loop to continue waiting +@ +@ /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +@ already in the handler! */ +@ +__tx_ts_ready: + MOV r7, #0x08000000 @ Build clear PendSV value + MOV r8, #0xE000E000 @ Build base NVIC address + STR r7, [r8, #0xD04] @ Clear any PendSV +@ +@ /* Re-enable interrupts and restore new thread. */ +@ + CPSIE i @ Enable interrupts + B __tx_ts_restore @ Restore the thread + diff --git a/ports/cortex_m3/ac6/src/tx_thread_stack_build.S b/ports/cortex_m3/ac6/src/tx_thread_stack_build.S new file mode 100644 index 00000000..c863e873 --- /dev/null +++ b/ports/cortex_m3/ac6/src/tx_thread_stack_build.S @@ -0,0 +1,146 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ + .text + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_stack_build Cortex-M3/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function builds a stack frame on the supplied thread's stack. */ +@/* The stack frame results in a fake interrupt return to the supplied */ +@/* function pointer. */ +@/* */ +@/* INPUT */ +@/* */ +@/* thread_ptr Pointer to thread control blk */ +@/* function_ptr Pointer to return function */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_thread_create Create thread service */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +@{ + .global _tx_thread_stack_build + .thumb_func +_tx_thread_stack_build: +@ +@ +@ /* Build a fake interrupt frame. The form of the fake interrupt stack +@ on the Cortex-M3 should look like the following after it is built: +@ +@ Stack Top: +@ LR Interrupted LR (LR at time of PENDSV) +@ r4 Initial value for r4 +@ r5 Initial value for r5 +@ r6 Initial value for r6 +@ r7 Initial value for r7 +@ r8 Initial value for r8 +@ r9 Initial value for r9 +@ r10 Initial value for r10 +@ r11 Initial value for r11 +@ r0 Initial value for r0 (Hardware stack starts here!!) +@ r1 Initial value for r1 +@ r2 Initial value for r2 +@ r3 Initial value for r3 +@ r12 Initial value for r12 +@ lr Initial value for lr +@ pc Initial value for pc +@ xPSR Initial value for xPSR +@ +@ Stack Bottom: (higher memory address) */ +@ + LDR r2, [r0, #16] @ Pickup end of stack area + BIC r2, r2, #0x7 @ Align frame + SUB r2, r2, #68 @ Subtract frame size + LDR r3, =0xFFFFFFFD @ Build initial LR value + STR r3, [r2, #0] @ Save on the stack +@ +@ /* Actually build the stack frame. */ +@ + MOV r3, #0 @ Build initial register value + STR r3, [r2, #4] @ Store initial r4 + STR r3, [r2, #8] @ Store initial r5 + STR r3, [r2, #12] @ Store initial r6 + STR r3, [r2, #16] @ Store initial r7 + STR r3, [r2, #20] @ Store initial r8 + STR r3, [r2, #24] @ Store initial r9 + STR r3, [r2, #28] @ Store initial r10 + STR r3, [r2, #32] @ Store initial r11 +@ +@ /* Hardware stack follows. */ +@ + STR r3, [r2, #36] @ Store initial r0 + STR r3, [r2, #40] @ Store initial r1 + STR r3, [r2, #44] @ Store initial r2 + STR r3, [r2, #48] @ Store initial r3 + STR r3, [r2, #52] @ Store initial r12 + MOV r3, #0xFFFFFFFF @ Poison EXC_RETURN value + STR r3, [r2, #56] @ Store initial lr + STR r1, [r2, #60] @ Store initial pc + MOV r3, #0x01000000 @ Only T-bit need be set + STR r3, [r2, #64] @ Store initial xPSR +@ +@ /* Setup stack pointer. */ +@ thread_ptr -> tx_thread_stack_ptr = r2; +@ + STR r2, [r0, #8] @ Save stack pointer in thread's + @ control block + BX lr @ Return to caller +@} + + diff --git a/ports/cortex_m3/ac6/src/tx_thread_system_return.S b/ports/cortex_m3/ac6/src/tx_thread_system_return.S new file mode 100644 index 00000000..3fc5f646 --- /dev/null +++ b/ports/cortex_m3/ac6/src/tx_thread_system_return.S @@ -0,0 +1,98 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@/* #define TX_SOURCE_CODE */ +@ +@ +@/* Include necessary system files. */ +@ +@/* #include "tx_api.h" +@ #include "tx_thread.h" +@ #include "tx_timer.h" */ + + + .text 32 + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_system_return Cortex-M3/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is target processor specific. It is used to transfer */ +@/* control from a thread back to the ThreadX system. Only a */ +@/* minimal context is saved since the compiler assumes temp registers */ +@/* are going to get slicked by a function call anyway. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling loop */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX components */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@/* VOID _tx_thread_system_return(VOID) +@{ */ + .thumb_func + .global _tx_thread_system_return +_tx_thread_system_return: +@ +@ /* Return to real scheduler via PendSV. Note that this routine is often +@ replaced with in-line assembly in tx_port.h to improved performance. */ +@ + MOV r0, #0x10000000 @ Load PENDSVSET bit + MOV r1, #0xE000E000 @ Load NVIC base + STR r0, [r1, #0xD04] @ Set PENDSVBIT in ICSR + MRS r0, IPSR @ Pickup IPSR + CMP r0, #0 @ Is it a thread returning? + BNE _isr_context @ If ISR, skip interrupt enable + MRS r1, PRIMASK @ Thread context returning, pickup PRIMASK + CPSIE i @ Enable interrupts + MSR PRIMASK, r1 @ Restore original interrupt posture +_isr_context: + BX lr @ Return to caller + +@/* } */ + diff --git a/ports/cortex_m3/ac6/src/tx_timer_interrupt.S b/ports/cortex_m3/ac6/src/tx_timer_interrupt.S new file mode 100644 index 00000000..e703f54d --- /dev/null +++ b/ports/cortex_m3/ac6/src/tx_timer_interrupt.S @@ -0,0 +1,270 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Timer */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_timer.h" +@#include "tx_thread.h" +@ +@ +@Define Assembly language external references... +@ + .global _tx_timer_time_slice + .global _tx_timer_system_clock + .global _tx_timer_current_ptr + .global _tx_timer_list_start + .global _tx_timer_list_end + .global _tx_timer_expired_time_slice + .global _tx_timer_expired + .global _tx_thread_time_slice + .global _tx_timer_expiration_process +@ +@ + .text + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_timer_interrupt Cortex-M3/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function processes the hardware timer interrupt. This */ +@/* processing includes incrementing the system clock and checking for */ +@/* time slice and/or timer expiration. If either is found, the */ +@/* interrupt context save/restore functions are called along with the */ +@/* expiration functions. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_timer_expiration_process Timer expiration processing */ +@/* _tx_thread_time_slice Time slice interrupted thread */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* interrupt vector */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_timer_interrupt(VOID) +@{ + .global _tx_timer_interrupt + .thumb_func +_tx_timer_interrupt: +@ +@ /* Upon entry to this routine, it is assumed that context save has already +@ been called, and therefore the compiler scratch registers are available +@ for use. */ +@ +@ /* Increment the system clock. */ +@ _tx_timer_system_clock++; +@ + LDR r1, =_tx_timer_system_clock @ Pickup address of system clock + LDR r0, [r1, #0] @ Pickup system clock + ADD r0, r0, #1 @ Increment system clock + STR r0, [r1, #0] @ Store new system clock +@ +@ /* Test for time-slice expiration. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice + LDR r2, [r3, #0] @ Pickup time-slice + CMP r2, #0 @ Is it non-active? + BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing +@ +@ /* Decrement the time_slice. */ +@ _tx_timer_time_slice--; +@ + SUB r2, r2, #1 @ Decrement the time-slice + STR r2, [r3, #0] @ Store new time-slice value +@ +@ /* Check for expiration. */ +@ if (__tx_timer_time_slice == 0) +@ + CMP r2, #0 @ Has it expired? + BNE __tx_timer_no_time_slice @ No, skip expiration processing +@ +@ /* Set the time-slice expired flag. */ +@ _tx_timer_expired_time_slice = TX_TRUE; +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of expired flag + MOV r0, #1 @ Build expired value + STR r0, [r3, #0] @ Set time-slice expiration flag +@ +@ } +@ +__tx_timer_no_time_slice: +@ +@ /* Test for timer expiration. */ +@ if (*_tx_timer_current_ptr) +@ { +@ + LDR r1, =_tx_timer_current_ptr @ Pickup current timer pointer address + LDR r0, [r1, #0] @ Pickup current timer + LDR r2, [r0, #0] @ Pickup timer list entry + CMP r2, #0 @ Is there anything in the list? + BEQ __tx_timer_no_timer @ No, just increment the timer +@ +@ /* Set expiration flag. */ +@ _tx_timer_expired = TX_TRUE; +@ + LDR r3, =_tx_timer_expired @ Pickup expiration flag address + MOV r2, #1 @ Build expired value + STR r2, [r3, #0] @ Set expired flag + B __tx_timer_done @ Finished timer processing +@ +@ } +@ else +@ { +__tx_timer_no_timer: +@ +@ /* No timer expired, increment the timer pointer. */ +@ _tx_timer_current_ptr++; +@ + ADD r0, r0, #4 @ Move to next timer +@ +@ /* Check for wrap-around. */ +@ if (_tx_timer_current_ptr == _tx_timer_list_end) +@ + LDR r3, =_tx_timer_list_end @ Pickup addr of timer list end + LDR r2, [r3, #0] @ Pickup list end + CMP r0, r2 @ Are we at list end? + BNE __tx_timer_skip_wrap @ No, skip wrap-around logic +@ +@ /* Wrap to beginning of list. */ +@ _tx_timer_current_ptr = _tx_timer_list_start; +@ + LDR r3, =_tx_timer_list_start @ Pickup addr of timer list start + LDR r0, [r3, #0] @ Set current pointer to list start +@ +__tx_timer_skip_wrap: +@ + STR r0, [r1, #0] @ Store new current timer pointer +@ } +@ +__tx_timer_done: +@ +@ +@ /* See if anything has expired. */ +@ if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +@ { +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of expired flag + LDR r2, [r3, #0] @ Pickup time-slice expired flag + CMP r2, #0 @ Did a time-slice expire? + BNE __tx_something_expired @ If non-zero, time-slice expired + LDR r1, =_tx_timer_expired @ Pickup addr of other expired flag + LDR r0, [r1, #0] @ Pickup timer expired flag + CMP r0, #0 @ Did a timer expire? + BEQ __tx_timer_nothing_expired @ No, nothing expired +@ +__tx_something_expired: +@ +@ + STMDB sp!, {r0, lr} @ Save the lr register on the stack + @ and save r0 just to keep 8-byte alignment +@ +@ /* Did a timer expire? */ +@ if (_tx_timer_expired) +@ { +@ + LDR r1, =_tx_timer_expired @ Pickup addr of expired flag + LDR r0, [r1, #0] @ Pickup timer expired flag + CMP r0, #0 @ Check for timer expiration + BEQ __tx_timer_dont_activate @ If not set, skip timer activation +@ +@ /* Process timer expiration. */ +@ _tx_timer_expiration_process(); +@ + BL _tx_timer_expiration_process @ Call the timer expiration handling routine +@ +@ } +__tx_timer_dont_activate: +@ +@ /* Did time slice expire? */ +@ if (_tx_timer_expired_time_slice) +@ { +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired + LDR r2, [r3, #0] @ Pickup the actual flag + CMP r2, #0 @ See if the flag is set + BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing +@ +@ /* Time slice interrupted thread. */ +@ _tx_thread_time_slice(); +@ + BL _tx_thread_time_slice @ Call time-slice processing + LDR r0, =_tx_thread_preempt_disable @ Build address of preempt disable flag + LDR r1, [r0] @ Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice @ Yes, skip the PendSV logic + LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address + LDR r1, [r0] @ Pickup the current thread pointer + LDR r2, =_tx_thread_execute_ptr @ Build execute thread pointer address + LDR r3, [r2] @ Pickup the execute thread pointer + LDR r0, =0xE000ED04 @ Build address of control register + LDR r2, =0x10000000 @ Build value for PendSV bit + CMP r1, r3 @ Are they the same? + BEQ __tx_timer_skip_time_slice @ If the same, there was no time-slice performed + STR r2, [r0] @ Not the same, issue the PendSV for preemption +__tx_timer_skip_time_slice: +@ +@ } +@ +__tx_timer_not_ts_expiration: +@ + LDMIA sp!, {r0, lr} @ Recover lr register (r0 is just there for + @ the 8-byte stack alignment +@ +@ } +@ +__tx_timer_nothing_expired: + + DSB @ Complete all memory access + BX lr @ Return to caller +@ +@} + + diff --git a/ports/cortex_m33/ac6/example_build/ARMCM33_DSP_FP_TZ_config.txt b/ports/cortex_m33/ac6/example_build/ARMCM33_DSP_FP_TZ_config.txt new file mode 100644 index 00000000..04e32d1f --- /dev/null +++ b/ports/cortex_m33/ac6/example_build/ARMCM33_DSP_FP_TZ_config.txt @@ -0,0 +1,24 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] +cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] +cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included +cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] +cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode +cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] +cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] +cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] +cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset +cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set +idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write +cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write +cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write +cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included +cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +#---------------------------------------------------------------------------------------------- diff --git a/ports/cortex_m33/ac6/example_build/AzureRTOS.uvmpw b/ports/cortex_m33/ac6/example_build/AzureRTOS.uvmpw new file mode 100644 index 00000000..860a1c52 --- /dev/null +++ b/ports/cortex_m33/ac6/example_build/AzureRTOS.uvmpw @@ -0,0 +1,26 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + WorkSpace + + + .\demo_secure_zone\demo_secure_zone.uvprojx + 1 + + + + .\demo_threadx_non-secure_zone\demo_threadx_non-secure_zone.uvprojx + 1 + + + + .\ThreadX_Library.uvprojx + 1 + 1 + + + diff --git a/ports/cortex_m33/ac6/example_build/Debug.ini b/ports/cortex_m33/ac6/example_build/Debug.ini new file mode 100644 index 00000000..2a9dfba0 --- /dev/null +++ b/ports/cortex_m33/ac6/example_build/Debug.ini @@ -0,0 +1,4 @@ +LOAD "..\\demo_threadx_non-secure_zone\\Objects\\demo_threadx_non-secure_zone.axf" incremental +LOAD "..\\demo_secure_zone\\Objects\\demo_secure_zone.axf" incremental +RESET +g, \\demo_secure_zone\main_s\main \ No newline at end of file diff --git a/ports/cortex_m33/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h b/ports/cortex_m33/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h new file mode 100644 index 00000000..1eb74752 --- /dev/null +++ b/ports/cortex_m33/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'ThreadX_Library' + * Target: 'ThreadX_Library_Project' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/ports/cortex_m33/ac6/example_build/RTOS.uvmpw.uvgui b/ports/cortex_m33/ac6/example_build/RTOS.uvmpw.uvgui new file mode 100644 index 00000000..5c23c31f --- /dev/null +++ b/ports/cortex_m33/ac6/example_build/RTOS.uvmpw.uvgui @@ -0,0 +1,1777 @@ + + + + -6.1 + +
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..\..\..\..\common\src\tx_timer_performance_info_get.c + + + tx_timer_performance_system_info_get.c + 1 + ..\..\..\..\common\src\tx_timer_performance_system_info_get.c + + + tx_timer_system_activate.c + 1 + ..\..\..\..\common\src\tx_timer_system_activate.c + + + tx_timer_system_deactivate.c + 1 + ..\..\..\..\common\src\tx_timer_system_deactivate.c + + + tx_timer_thread_entry.c + 1 + ..\..\..\..\common\src\tx_timer_thread_entry.c + + + tx_trace_disable.c + 1 + ..\..\..\..\common\src\tx_trace_disable.c + + + tx_trace_enable.c + 1 + ..\..\..\..\common\src\tx_trace_enable.c + + + tx_trace_initialize.c + 1 + ..\..\..\..\common\src\tx_trace_initialize.c + + + tx_trace_interrupt_control.c + 1 + ..\..\..\..\common\src\tx_trace_interrupt_control.c + + + tx_trace_isr_enter_insert.c + 1 + ..\..\..\..\common\src\tx_trace_isr_enter_insert.c + + + tx_trace_isr_exit_insert.c + 1 + ..\..\..\..\common\src\tx_trace_isr_exit_insert.c + + + tx_trace_object_register.c + 1 + ..\..\..\..\common\src\tx_trace_object_register.c + + + tx_trace_object_unregister.c + 1 + ..\..\..\..\common\src\tx_trace_object_unregister.c + + + tx_trace_user_event_insert.c + 1 + ..\..\..\..\common\src\tx_trace_user_event_insert.c + + + txe_block_allocate.c + 1 + ..\..\..\..\common\src\txe_block_allocate.c + + + txe_block_pool_create.c + 1 + ..\..\..\..\common\src\txe_block_pool_create.c + + + txe_block_pool_delete.c + 1 + ..\..\..\..\common\src\txe_block_pool_delete.c + + + txe_block_pool_info_get.c + 1 + ..\..\..\..\common\src\txe_block_pool_info_get.c + + + txe_block_pool_prioritize.c + 1 + ..\..\..\..\common\src\txe_block_pool_prioritize.c + + + txe_block_release.c + 1 + ..\..\..\..\common\src\txe_block_release.c + + + txe_byte_allocate.c + 1 + ..\..\..\..\common\src\txe_byte_allocate.c + + + txe_byte_pool_create.c + 1 + ..\..\..\..\common\src\txe_byte_pool_create.c + + + txe_byte_pool_delete.c + 1 + ..\..\..\..\common\src\txe_byte_pool_delete.c + + + txe_byte_pool_info_get.c + 1 + ..\..\..\..\common\src\txe_byte_pool_info_get.c + + + txe_byte_pool_prioritize.c + 1 + ..\..\..\..\common\src\txe_byte_pool_prioritize.c + + + txe_byte_release.c + 1 + ..\..\..\..\common\src\txe_byte_release.c + + + txe_event_flags_create.c + 1 + ..\..\..\..\common\src\txe_event_flags_create.c + + + txe_event_flags_delete.c + 1 + ..\..\..\..\common\src\txe_event_flags_delete.c + + + txe_event_flags_get.c + 1 + ..\..\..\..\common\src\txe_event_flags_get.c + + + txe_event_flags_info_get.c + 1 + ..\..\..\..\common\src\txe_event_flags_info_get.c + + + txe_event_flags_set.c + 1 + ..\..\..\..\common\src\txe_event_flags_set.c + + + txe_event_flags_set_notify.c + 1 + ..\..\..\..\common\src\txe_event_flags_set_notify.c + + + txe_mutex_create.c + 1 + ..\..\..\..\common\src\txe_mutex_create.c + + + txe_mutex_delete.c + 1 + ..\..\..\..\common\src\txe_mutex_delete.c + + + txe_mutex_get.c + 1 + ..\..\..\..\common\src\txe_mutex_get.c + + + txe_mutex_info_get.c + 1 + ..\..\..\..\common\src\txe_mutex_info_get.c + + + txe_mutex_prioritize.c + 1 + ..\..\..\..\common\src\txe_mutex_prioritize.c + + + txe_mutex_put.c + 1 + ..\..\..\..\common\src\txe_mutex_put.c + + + txe_queue_create.c + 1 + ..\..\..\..\common\src\txe_queue_create.c + + + txe_queue_delete.c + 1 + ..\..\..\..\common\src\txe_queue_delete.c + + + txe_queue_flush.c + 1 + ..\..\..\..\common\src\txe_queue_flush.c + + + txe_queue_front_send.c + 1 + ..\..\..\..\common\src\txe_queue_front_send.c + + + txe_queue_info_get.c + 1 + ..\..\..\..\common\src\txe_queue_info_get.c + + + txe_queue_prioritize.c + 1 + ..\..\..\..\common\src\txe_queue_prioritize.c + + + txe_queue_receive.c + 1 + ..\..\..\..\common\src\txe_queue_receive.c + + + txe_queue_send.c + 1 + ..\..\..\..\common\src\txe_queue_send.c + + + txe_queue_send_notify.c + 1 + ..\..\..\..\common\src\txe_queue_send_notify.c + + + txe_semaphore_ceiling_put.c + 1 + ..\..\..\..\common\src\txe_semaphore_ceiling_put.c + + + txe_semaphore_create.c + 1 + ..\..\..\..\common\src\txe_semaphore_create.c + + + txe_semaphore_delete.c + 1 + ..\..\..\..\common\src\txe_semaphore_delete.c + + + txe_semaphore_get.c + 1 + ..\..\..\..\common\src\txe_semaphore_get.c + + + txe_semaphore_info_get.c + 1 + ..\..\..\..\common\src\txe_semaphore_info_get.c + + + txe_semaphore_prioritize.c + 1 + ..\..\..\..\common\src\txe_semaphore_prioritize.c + + + txe_semaphore_put.c + 1 + ..\..\..\..\common\src\txe_semaphore_put.c + + + txe_semaphore_put_notify.c + 1 + ..\..\..\..\common\src\txe_semaphore_put_notify.c + + + txe_thread_create.c + 1 + ..\..\..\..\common\src\txe_thread_create.c + + + txe_thread_delete.c + 1 + ..\..\..\..\common\src\txe_thread_delete.c + + + txe_thread_entry_exit_notify.c + 1 + ..\..\..\..\common\src\txe_thread_entry_exit_notify.c + + + txe_thread_info_get.c + 1 + ..\..\..\..\common\src\txe_thread_info_get.c + + + txe_thread_preemption_change.c + 1 + ..\..\..\..\common\src\txe_thread_preemption_change.c + + + txe_thread_priority_change.c + 1 + ..\..\..\..\common\src\txe_thread_priority_change.c + + + txe_thread_relinquish.c + 1 + ..\..\..\..\common\src\txe_thread_relinquish.c + + + txe_thread_reset.c + 1 + ..\..\..\..\common\src\txe_thread_reset.c + + + txe_thread_resume.c + 1 + ..\..\..\..\common\src\txe_thread_resume.c + + + txe_thread_suspend.c + 1 + ..\..\..\..\common\src\txe_thread_suspend.c + + + txe_thread_terminate.c + 1 + ..\..\..\..\common\src\txe_thread_terminate.c + + + txe_thread_time_slice_change.c + 1 + ..\..\..\..\common\src\txe_thread_time_slice_change.c + + + txe_thread_wait_abort.c + 1 + ..\..\..\..\common\src\txe_thread_wait_abort.c + + + txe_timer_activate.c + 1 + ..\..\..\..\common\src\txe_timer_activate.c + + + txe_timer_change.c + 1 + ..\..\..\..\common\src\txe_timer_change.c + + + txe_timer_create.c + 1 + ..\..\..\..\common\src\txe_timer_create.c + + + txe_timer_deactivate.c + 1 + ..\..\..\..\common\src\txe_timer_deactivate.c + + + txe_timer_delete.c + 1 + ..\..\..\..\common\src\txe_timer_delete.c + + + txe_timer_info_get.c + 1 + ..\..\..\..\common\src\txe_timer_info_get.c + + + tx_trace_buffer_full_notify.c + 1 + ..\..\..\..\common\src\tx_trace_buffer_full_notify.c + + + tx_trace_event_filter.c + 1 + ..\..\..\..\common\src\tx_trace_event_filter.c + + + tx_trace_event_unfilter.c + 1 + ..\..\..\..\common\src\tx_trace_event_unfilter.c + + + txe_thread_secure_stack_allocate.c + 1 + ..\src\txe_thread_secure_stack_allocate.c + + + txe_thread_secure_stack_free.c + 1 + ..\src\txe_thread_secure_stack_free.c + + + tx_thread_stack_error_handler.c + 1 + ..\src\tx_thread_stack_error_handler.c + + + tx_thread_stack_error_notify.c + 1 + ..\src\tx_thread_stack_error_notify.c + + + tx_thread_context_restore.S + 2 + ..\src\tx_thread_context_restore.S + + + tx_thread_context_save.S + 2 + ..\src\tx_thread_context_save.S + + + tx_thread_interrupt_control.S + 2 + ..\src\tx_thread_interrupt_control.S + + + tx_thread_interrupt_disable.S + 2 + ..\src\tx_thread_interrupt_disable.S + + + tx_thread_interrupt_restore.S + 2 + ..\src\tx_thread_interrupt_restore.S + + + tx_thread_schedule.S + 2 + ..\src\tx_thread_schedule.S + + + tx_thread_secure_stack_allocate.S + 2 + ..\src\tx_thread_secure_stack_allocate.S + + + tx_thread_secure_stack_free.S + 2 + ..\src\tx_thread_secure_stack_free.S + + + tx_thread_stack_build.S + 2 + ..\src\tx_thread_stack_build.S + + + tx_thread_system_return.S + 2 + ..\src\tx_thread_system_return.S + + + tx_timer_interrupt.S + 2 + ..\src\tx_timer_interrupt.S + + + tx_initialize_low_level.S + 2 + .\tx_initialize_low_level.S + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/ports/cortex_m33/ac6/example_build/demo_secure_zone/Abstract.txt b/ports/cortex_m33/ac6/example_build/demo_secure_zone/Abstract.txt new file mode 100644 index 00000000..0d1d8c52 --- /dev/null +++ b/ports/cortex_m33/ac6/example_build/demo_secure_zone/Abstract.txt @@ -0,0 +1,19 @@ +This ARM Cortex-M33 secure/non-secure example project that +shows the setup of the CMSIS-RTOS2 RTX for TrustZone for +ARMv8-M applications. + +The application uses CMSIS and can be executed on a Fixed +Virtual Platform (FVP) simulation model. The application +demonstrates three RTOS threads. + + +Secure application: + - Setup code and start non-secure application. + +Non-secure application: + - Calls a secure function from non-secure state. + - Calls a secure function that call back to a non-secure function. + +Output: +Variables used in this application can be viewed in the Debugger +Watch window. \ No newline at end of file diff --git a/ports/cortex_m33/ac6/example_build/demo_secure_zone/Objects/ExtDll.iex b/ports/cortex_m33/ac6/example_build/demo_secure_zone/Objects/ExtDll.iex new file mode 100644 index 00000000..6c0896e1 --- /dev/null +++ b/ports/cortex_m33/ac6/example_build/demo_secure_zone/Objects/ExtDll.iex @@ -0,0 +1,2 @@ +[EXTDLL] +Count=0 diff --git a/ports/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_AC6.sct b/ports/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_AC6.sct new file mode 100644 index 00000000..3baa3455 --- /dev/null +++ b/ports/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_AC6.sct @@ -0,0 +1,74 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc +; command above MUST be in first line (no comment above!) + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x00000000 +#define __ROM_SIZE 0x00200000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00020000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000400 +#define __HEAP_SIZE 0x00000C00 + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundery definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ +#define __RO_BASE __ROM_BASE +#define __RO_SIZE __ROM_SIZE + +#define __RW_BASE (__RAM_BASE ) +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) + + + +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) +; *(Veneer$$CMSE) ; uncomment for secure applications + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } +} diff --git a/ports/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h b/ports/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h new file mode 100644 index 00000000..a7cb0d73 --- /dev/null +++ b/ports/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h @@ -0,0 +1,1260 @@ +/**************************************************************************//** + * @file partition_ARMCM33.h + * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33 + * @version V1.1.1 + * @date 12. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PARTITION_ARMCM33_H +#define PARTITION_ARMCM33_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 1 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x00200000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x003FFFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x20200000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x203FFFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x40040000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 1 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 1 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 1 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x80-0xFF +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 1 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// Interrupt 0 <0=> Secure state <1=> Non-Secure state +// Interrupt 1 <0=> Secure state <1=> Non-Secure state +// Interrupt 2 <0=> Secure state <1=> Non-Secure state +// Interrupt 3 <0=> Secure state <1=> Non-Secure state +// Interrupt 4 <0=> Secure state <1=> Non-Secure state +// Interrupt 5 <0=> Secure state <1=> Non-Secure state +// Interrupt 6 <0=> Secure state <1=> Non-Secure state +// Interrupt 7 <0=> Secure state <1=> Non-Secure state +// Interrupt 8 <0=> Secure state <1=> Non-Secure state +// Interrupt 9 <0=> Secure state <1=> Non-Secure state +// Interrupt 10 <0=> Secure state <1=> Non-Secure state +// Interrupt 11 <0=> Secure state <1=> Non-Secure state +// Interrupt 12 <0=> Secure state <1=> Non-Secure state +// Interrupt 13 <0=> Secure state <1=> Non-Secure state +// Interrupt 14 <0=> Secure state <1=> Non-Secure state +// Interrupt 15 <0=> Secure state <1=> Non-Secure state +// Interrupt 16 <0=> Secure state <1=> Non-Secure state +// Interrupt 17 <0=> Secure state <1=> Non-Secure state +// Interrupt 18 <0=> Secure state <1=> Non-Secure state +// Interrupt 19 <0=> Secure state <1=> Non-Secure state +// Interrupt 20 <0=> Secure state <1=> Non-Secure state +// Interrupt 21 <0=> Secure state <1=> Non-Secure state +// Interrupt 22 <0=> Secure state <1=> Non-Secure state +// Interrupt 23 <0=> Secure state <1=> Non-Secure state +// Interrupt 24 <0=> Secure state <1=> Non-Secure state +// Interrupt 25 <0=> Secure state <1=> Non-Secure state +// Interrupt 26 <0=> Secure state <1=> Non-Secure state +// Interrupt 27 <0=> Secure state <1=> Non-Secure state +// Interrupt 28 <0=> Secure state <1=> Non-Secure state +// Interrupt 29 <0=> Secure state <1=> Non-Secure state +// Interrupt 30 <0=> Secure state <1=> Non-Secure state +// Interrupt 31 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// Interrupt 32 <0=> Secure state <1=> Non-Secure state +// Interrupt 33 <0=> Secure state <1=> Non-Secure state +// Interrupt 34 <0=> Secure state <1=> Non-Secure state +// Interrupt 35 <0=> Secure state <1=> Non-Secure state +// Interrupt 36 <0=> Secure state <1=> Non-Secure state +// Interrupt 37 <0=> Secure state <1=> Non-Secure state +// Interrupt 38 <0=> Secure state <1=> Non-Secure state +// Interrupt 39 <0=> Secure state <1=> Non-Secure state +// Interrupt 40 <0=> Secure state <1=> Non-Secure state +// Interrupt 41 <0=> Secure state <1=> Non-Secure state +// Interrupt 42 <0=> Secure state <1=> Non-Secure state +// Interrupt 43 <0=> Secure state <1=> Non-Secure state +// Interrupt 44 <0=> Secure state <1=> Non-Secure state +// Interrupt 45 <0=> Secure state <1=> Non-Secure state +// Interrupt 46 <0=> Secure state <1=> Non-Secure state +// Interrupt 47 <0=> Secure state <1=> Non-Secure state +// Interrupt 48 <0=> Secure state <1=> Non-Secure state +// Interrupt 49 <0=> Secure state <1=> Non-Secure state +// Interrupt 50 <0=> Secure state <1=> Non-Secure state +// Interrupt 51 <0=> Secure state <1=> Non-Secure state +// Interrupt 52 <0=> Secure state <1=> Non-Secure state +// Interrupt 53 <0=> Secure state <1=> Non-Secure state +// Interrupt 54 <0=> Secure state <1=> Non-Secure state +// Interrupt 55 <0=> Secure state <1=> Non-Secure state +// Interrupt 56 <0=> Secure state <1=> Non-Secure state +// Interrupt 57 <0=> Secure state <1=> Non-Secure state +// Interrupt 58 <0=> Secure state <1=> Non-Secure state +// Interrupt 59 <0=> Secure state <1=> Non-Secure state +// Interrupt 60 <0=> Secure state <1=> Non-Secure state +// Interrupt 61 <0=> Secure state <1=> Non-Secure state +// Interrupt 62 <0=> Secure state <1=> Non-Secure state +// Interrupt 63 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 0 + +/* +// Interrupts 64..95 +// Interrupt 64 <0=> Secure state <1=> Non-Secure state +// Interrupt 65 <0=> Secure state <1=> Non-Secure state +// Interrupt 66 <0=> Secure state <1=> Non-Secure state +// Interrupt 67 <0=> Secure state <1=> Non-Secure state +// Interrupt 68 <0=> Secure state <1=> Non-Secure state +// Interrupt 69 <0=> Secure state <1=> Non-Secure state +// Interrupt 70 <0=> Secure state <1=> Non-Secure state +// Interrupt 71 <0=> Secure state <1=> Non-Secure state +// Interrupt 72 <0=> Secure state <1=> Non-Secure state +// Interrupt 73 <0=> Secure state <1=> Non-Secure state +// Interrupt 74 <0=> Secure state <1=> Non-Secure state +// Interrupt 75 <0=> Secure state <1=> Non-Secure state +// Interrupt 76 <0=> Secure state <1=> Non-Secure state +// Interrupt 77 <0=> Secure state <1=> Non-Secure state +// Interrupt 78 <0=> Secure state <1=> Non-Secure state +// Interrupt 79 <0=> Secure state <1=> Non-Secure state +// Interrupt 80 <0=> Secure state <1=> Non-Secure state +// Interrupt 81 <0=> Secure state <1=> Non-Secure state +// Interrupt 82 <0=> Secure state <1=> Non-Secure state +// Interrupt 83 <0=> Secure state <1=> Non-Secure state +// Interrupt 84 <0=> Secure state <1=> Non-Secure state +// Interrupt 85 <0=> Secure state <1=> Non-Secure state +// Interrupt 86 <0=> Secure state <1=> Non-Secure state +// Interrupt 87 <0=> Secure state <1=> Non-Secure state +// Interrupt 88 <0=> Secure state <1=> Non-Secure state +// Interrupt 89 <0=> Secure state <1=> Non-Secure state +// Interrupt 90 <0=> Secure state <1=> Non-Secure state +// Interrupt 91 <0=> Secure state <1=> Non-Secure state +// Interrupt 92 <0=> Secure state <1=> Non-Secure state +// Interrupt 93 <0=> Secure state <1=> Non-Secure state +// Interrupt 94 <0=> Secure state <1=> Non-Secure state +// Interrupt 95 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 0 + +/* +// Interrupts 96..127 +// Interrupt 96 <0=> Secure state <1=> Non-Secure state +// Interrupt 97 <0=> Secure state <1=> Non-Secure state +// Interrupt 98 <0=> Secure state <1=> Non-Secure state +// Interrupt 99 <0=> Secure state <1=> Non-Secure state +// Interrupt 100 <0=> Secure state <1=> Non-Secure state +// Interrupt 101 <0=> Secure state <1=> Non-Secure state +// Interrupt 102 <0=> Secure state <1=> Non-Secure state +// Interrupt 103 <0=> Secure state <1=> Non-Secure state +// Interrupt 104 <0=> Secure state <1=> Non-Secure state +// Interrupt 105 <0=> Secure state <1=> Non-Secure state +// Interrupt 106 <0=> Secure state <1=> Non-Secure state +// Interrupt 107 <0=> Secure state <1=> Non-Secure state +// Interrupt 108 <0=> Secure state <1=> Non-Secure state +// Interrupt 109 <0=> Secure state <1=> Non-Secure state +// Interrupt 110 <0=> Secure state <1=> Non-Secure state +// Interrupt 111 <0=> Secure state <1=> Non-Secure state +// Interrupt 112 <0=> Secure state <1=> Non-Secure state +// Interrupt 113 <0=> Secure state <1=> Non-Secure state +// Interrupt 114 <0=> Secure state <1=> Non-Secure state +// Interrupt 115 <0=> Secure state <1=> Non-Secure state +// Interrupt 116 <0=> Secure state <1=> Non-Secure state +// Interrupt 117 <0=> Secure state <1=> Non-Secure state +// Interrupt 118 <0=> Secure state <1=> Non-Secure state +// Interrupt 119 <0=> Secure state <1=> Non-Secure state +// Interrupt 120 <0=> Secure state <1=> Non-Secure state +// Interrupt 121 <0=> Secure state <1=> Non-Secure state +// Interrupt 122 <0=> Secure state <1=> Non-Secure state +// Interrupt 123 <0=> Secure state <1=> Non-Secure state +// Interrupt 124 <0=> Secure state <1=> Non-Secure state +// Interrupt 125 <0=> Secure state <1=> Non-Secure state +// Interrupt 126 <0=> Secure state <1=> Non-Secure state +// Interrupt 127 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..159) +*/ +#define NVIC_INIT_ITNS4 0 + +/* +// Interrupts 128..159 +// Interrupt 128 <0=> Secure state <1=> Non-Secure state +// Interrupt 129 <0=> Secure state <1=> Non-Secure state +// Interrupt 130 <0=> Secure state <1=> Non-Secure state +// Interrupt 131 <0=> Secure state <1=> Non-Secure state +// Interrupt 132 <0=> Secure state <1=> Non-Secure state +// Interrupt 133 <0=> Secure state <1=> Non-Secure state +// Interrupt 134 <0=> Secure state <1=> Non-Secure state +// Interrupt 135 <0=> Secure state <1=> Non-Secure state +// Interrupt 136 <0=> Secure state <1=> Non-Secure state +// Interrupt 137 <0=> Secure state <1=> Non-Secure state +// Interrupt 138 <0=> Secure state <1=> Non-Secure state +// Interrupt 139 <0=> Secure state <1=> Non-Secure state +// Interrupt 140 <0=> Secure state <1=> Non-Secure state +// Interrupt 141 <0=> Secure state <1=> Non-Secure state +// Interrupt 142 <0=> Secure state <1=> Non-Secure state +// Interrupt 143 <0=> Secure state <1=> Non-Secure state +// Interrupt 144 <0=> Secure state <1=> Non-Secure state +// Interrupt 145 <0=> Secure state <1=> Non-Secure state +// Interrupt 146 <0=> Secure state <1=> Non-Secure state +// Interrupt 147 <0=> Secure state <1=> Non-Secure state +// Interrupt 148 <0=> Secure state <1=> Non-Secure state +// Interrupt 149 <0=> Secure state <1=> Non-Secure state +// Interrupt 150 <0=> Secure state <1=> Non-Secure state +// Interrupt 151 <0=> Secure state <1=> Non-Secure state +// Interrupt 152 <0=> Secure state <1=> Non-Secure state +// Interrupt 153 <0=> Secure state <1=> Non-Secure state +// Interrupt 154 <0=> Secure state <1=> Non-Secure state +// Interrupt 155 <0=> Secure state <1=> Non-Secure state +// Interrupt 156 <0=> Secure state <1=> Non-Secure state +// Interrupt 157 <0=> Secure state <1=> Non-Secure state +// Interrupt 158 <0=> Secure state <1=> Non-Secure state +// Interrupt 159 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 5 (Interrupts 160..191) +*/ +#define NVIC_INIT_ITNS5 0 + +/* +// Interrupts 160..191 +// Interrupt 160 <0=> Secure state <1=> Non-Secure state +// Interrupt 161 <0=> Secure state <1=> Non-Secure state +// Interrupt 162 <0=> Secure state <1=> Non-Secure state +// Interrupt 163 <0=> Secure state <1=> Non-Secure state +// Interrupt 164 <0=> Secure state <1=> Non-Secure state +// Interrupt 165 <0=> Secure state <1=> Non-Secure state +// Interrupt 166 <0=> Secure state <1=> Non-Secure state +// Interrupt 167 <0=> Secure state <1=> Non-Secure state +// Interrupt 168 <0=> Secure state <1=> Non-Secure state +// Interrupt 169 <0=> Secure state <1=> Non-Secure state +// Interrupt 170 <0=> Secure state <1=> Non-Secure state +// Interrupt 171 <0=> Secure state <1=> Non-Secure state +// Interrupt 172 <0=> Secure state <1=> Non-Secure state +// Interrupt 173 <0=> Secure state <1=> Non-Secure state +// Interrupt 174 <0=> Secure state <1=> Non-Secure state +// Interrupt 175 <0=> Secure state <1=> Non-Secure state +// Interrupt 176 <0=> Secure state <1=> Non-Secure state +// Interrupt 177 <0=> Secure state <1=> Non-Secure state +// Interrupt 178 <0=> Secure state <1=> Non-Secure state +// Interrupt 179 <0=> Secure state <1=> Non-Secure state +// Interrupt 180 <0=> Secure state <1=> Non-Secure state +// Interrupt 181 <0=> Secure state <1=> Non-Secure state +// Interrupt 182 <0=> Secure state <1=> Non-Secure state +// Interrupt 183 <0=> Secure state <1=> Non-Secure state +// Interrupt 184 <0=> Secure state <1=> Non-Secure state +// Interrupt 185 <0=> Secure state <1=> Non-Secure state +// Interrupt 186 <0=> Secure state <1=> Non-Secure state +// Interrupt 187 <0=> Secure state <1=> Non-Secure state +// Interrupt 188 <0=> Secure state <1=> Non-Secure state +// Interrupt 189 <0=> Secure state <1=> Non-Secure state +// Interrupt 190 <0=> Secure state <1=> Non-Secure state +// Interrupt 191 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS5_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 6 (Interrupts 192..223) +*/ +#define NVIC_INIT_ITNS6 0 + +/* +// Interrupts 192..223 +// Interrupt 192 <0=> Secure state <1=> Non-Secure state +// Interrupt 193 <0=> Secure state <1=> Non-Secure state +// Interrupt 194 <0=> Secure state <1=> Non-Secure state +// Interrupt 195 <0=> Secure state <1=> Non-Secure state +// Interrupt 196 <0=> Secure state <1=> Non-Secure state +// Interrupt 197 <0=> Secure state <1=> Non-Secure state +// Interrupt 198 <0=> Secure state <1=> Non-Secure state +// Interrupt 199 <0=> Secure state <1=> Non-Secure state +// Interrupt 200 <0=> Secure state <1=> Non-Secure state +// Interrupt 201 <0=> Secure state <1=> Non-Secure state +// Interrupt 202 <0=> Secure state <1=> Non-Secure state +// Interrupt 203 <0=> Secure state <1=> Non-Secure state +// Interrupt 204 <0=> Secure state <1=> Non-Secure state +// Interrupt 205 <0=> Secure state <1=> Non-Secure state +// Interrupt 206 <0=> Secure state <1=> Non-Secure state +// Interrupt 207 <0=> Secure state <1=> Non-Secure state +// Interrupt 208 <0=> Secure state <1=> Non-Secure state +// Interrupt 209 <0=> Secure state <1=> Non-Secure state +// Interrupt 210 <0=> Secure state <1=> Non-Secure state +// Interrupt 211 <0=> Secure state <1=> Non-Secure state +// Interrupt 212 <0=> Secure state <1=> Non-Secure state +// Interrupt 213 <0=> Secure state <1=> Non-Secure state +// Interrupt 214 <0=> Secure state <1=> Non-Secure state +// Interrupt 215 <0=> Secure state <1=> Non-Secure state +// Interrupt 216 <0=> Secure state <1=> Non-Secure state +// Interrupt 217 <0=> Secure state <1=> Non-Secure state +// Interrupt 218 <0=> Secure state <1=> Non-Secure state +// Interrupt 219 <0=> Secure state <1=> Non-Secure state +// Interrupt 220 <0=> Secure state <1=> Non-Secure state +// Interrupt 221 <0=> Secure state <1=> Non-Secure state +// Interrupt 222 <0=> Secure state <1=> Non-Secure state +// Interrupt 223 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS6_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 7 (Interrupts 224..255) +*/ +#define NVIC_INIT_ITNS7 0 + +/* +// Interrupts 224..255 +// Interrupt 224 <0=> Secure state <1=> Non-Secure state +// Interrupt 225 <0=> Secure state <1=> Non-Secure state +// Interrupt 226 <0=> Secure state <1=> Non-Secure state +// Interrupt 227 <0=> Secure state <1=> Non-Secure state +// Interrupt 228 <0=> Secure state <1=> Non-Secure state +// Interrupt 229 <0=> Secure state <1=> Non-Secure state +// Interrupt 230 <0=> Secure state <1=> Non-Secure state +// Interrupt 231 <0=> Secure state <1=> Non-Secure state +// Interrupt 232 <0=> Secure state <1=> Non-Secure state +// Interrupt 233 <0=> Secure state <1=> Non-Secure state +// Interrupt 234 <0=> Secure state <1=> Non-Secure state +// Interrupt 235 <0=> Secure state <1=> Non-Secure state +// Interrupt 236 <0=> Secure state <1=> Non-Secure state +// Interrupt 237 <0=> Secure state <1=> Non-Secure state +// Interrupt 238 <0=> Secure state <1=> Non-Secure state +// Interrupt 239 <0=> Secure state <1=> Non-Secure state +// Interrupt 240 <0=> Secure state <1=> Non-Secure state +// Interrupt 241 <0=> Secure state <1=> Non-Secure state +// Interrupt 242 <0=> Secure state <1=> Non-Secure state +// Interrupt 243 <0=> Secure state <1=> Non-Secure state +// Interrupt 244 <0=> Secure state <1=> Non-Secure state +// Interrupt 245 <0=> Secure state <1=> Non-Secure state +// Interrupt 246 <0=> Secure state <1=> Non-Secure state +// Interrupt 247 <0=> Secure state <1=> Non-Secure state +// Interrupt 248 <0=> Secure state <1=> Non-Secure state +// Interrupt 249 <0=> Secure state <1=> Non-Secure state +// Interrupt 250 <0=> Secure state <1=> Non-Secure state +// Interrupt 251 <0=> Secure state <1=> Non-Secure state +// Interrupt 252 <0=> Secure state <1=> Non-Secure state +// Interrupt 253 <0=> Secure state <1=> Non-Secure state +// Interrupt 254 <0=> Secure state <1=> Non-Secure state +// Interrupt 255 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS7_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 8 (Interrupts 256..287) +*/ +#define NVIC_INIT_ITNS8 0 + +/* +// Interrupts 256..287 +// Interrupt 256 <0=> Secure state <1=> Non-Secure state +// Interrupt 257 <0=> Secure state <1=> Non-Secure state +// Interrupt 258 <0=> Secure state <1=> Non-Secure state +// Interrupt 259 <0=> Secure state <1=> Non-Secure state +// Interrupt 260 <0=> Secure state <1=> Non-Secure state +// Interrupt 261 <0=> Secure state <1=> Non-Secure state +// Interrupt 262 <0=> Secure state <1=> Non-Secure state +// Interrupt 263 <0=> Secure state <1=> Non-Secure state +// Interrupt 264 <0=> Secure state <1=> Non-Secure state +// Interrupt 265 <0=> Secure state <1=> Non-Secure state +// Interrupt 266 <0=> Secure state <1=> Non-Secure state +// Interrupt 267 <0=> Secure state <1=> Non-Secure state +// Interrupt 268 <0=> Secure state <1=> Non-Secure state +// Interrupt 269 <0=> Secure state <1=> Non-Secure state +// Interrupt 270 <0=> Secure state <1=> Non-Secure state +// Interrupt 271 <0=> Secure state <1=> Non-Secure state +// Interrupt 272 <0=> Secure state <1=> Non-Secure state +// Interrupt 273 <0=> Secure state <1=> Non-Secure state +// Interrupt 274 <0=> Secure state <1=> Non-Secure state +// Interrupt 275 <0=> Secure state <1=> Non-Secure state +// Interrupt 276 <0=> Secure state <1=> Non-Secure state +// Interrupt 277 <0=> Secure state <1=> Non-Secure state +// Interrupt 278 <0=> Secure state <1=> Non-Secure state +// Interrupt 279 <0=> Secure state <1=> Non-Secure state +// Interrupt 280 <0=> Secure state <1=> Non-Secure state +// Interrupt 281 <0=> Secure state <1=> Non-Secure state +// Interrupt 282 <0=> Secure state <1=> Non-Secure state +// Interrupt 283 <0=> Secure state <1=> Non-Secure state +// Interrupt 284 <0=> Secure state <1=> Non-Secure state +// Interrupt 285 <0=> Secure state <1=> Non-Secure state +// Interrupt 286 <0=> Secure state <1=> Non-Secure state +// Interrupt 287 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS8_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 9 (Interrupts 288..319) +*/ +#define NVIC_INIT_ITNS9 0 + +/* +// Interrupts 288..319 +// Interrupt 288 <0=> Secure state <1=> Non-Secure state +// Interrupt 289 <0=> Secure state <1=> Non-Secure state +// Interrupt 290 <0=> Secure state <1=> Non-Secure state +// Interrupt 291 <0=> Secure state <1=> Non-Secure state +// Interrupt 292 <0=> Secure state <1=> Non-Secure state +// Interrupt 293 <0=> Secure state <1=> Non-Secure state +// Interrupt 294 <0=> Secure state <1=> Non-Secure state +// Interrupt 295 <0=> Secure state <1=> Non-Secure state +// Interrupt 296 <0=> Secure state <1=> Non-Secure state +// Interrupt 297 <0=> Secure state <1=> Non-Secure state +// Interrupt 298 <0=> Secure state <1=> Non-Secure state +// Interrupt 299 <0=> Secure state <1=> Non-Secure state +// Interrupt 300 <0=> Secure state <1=> Non-Secure state +// Interrupt 301 <0=> Secure state <1=> Non-Secure state +// Interrupt 302 <0=> Secure state <1=> Non-Secure state +// Interrupt 303 <0=> Secure state <1=> Non-Secure state +// Interrupt 304 <0=> Secure state <1=> Non-Secure state +// Interrupt 305 <0=> Secure state <1=> Non-Secure state +// Interrupt 306 <0=> Secure state <1=> Non-Secure state +// Interrupt 307 <0=> Secure state <1=> Non-Secure state +// Interrupt 308 <0=> Secure state <1=> Non-Secure state +// Interrupt 309 <0=> Secure state <1=> Non-Secure state +// Interrupt 310 <0=> Secure state <1=> Non-Secure state +// Interrupt 311 <0=> Secure state <1=> Non-Secure state +// Interrupt 312 <0=> Secure state <1=> Non-Secure state +// Interrupt 313 <0=> Secure state <1=> Non-Secure state +// Interrupt 314 <0=> Secure state <1=> Non-Secure state +// Interrupt 315 <0=> Secure state <1=> Non-Secure state +// Interrupt 316 <0=> Secure state <1=> Non-Secure state +// Interrupt 317 <0=> Secure state <1=> Non-Secure state +// Interrupt 318 <0=> Secure state <1=> Non-Secure state +// Interrupt 319 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS9_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 10 (Interrupts 320..351) +*/ +#define NVIC_INIT_ITNS10 0 + +/* +// Interrupts 320..351 +// Interrupt 320 <0=> Secure state <1=> Non-Secure state +// Interrupt 321 <0=> Secure state <1=> Non-Secure state +// Interrupt 322 <0=> Secure state <1=> Non-Secure state +// Interrupt 323 <0=> Secure state <1=> Non-Secure state +// Interrupt 324 <0=> Secure state <1=> Non-Secure state +// Interrupt 325 <0=> Secure state <1=> Non-Secure state +// Interrupt 326 <0=> Secure state <1=> Non-Secure state +// Interrupt 327 <0=> Secure state <1=> Non-Secure state +// Interrupt 328 <0=> Secure state <1=> Non-Secure state +// Interrupt 329 <0=> Secure state <1=> Non-Secure state +// Interrupt 330 <0=> Secure state <1=> Non-Secure state +// Interrupt 331 <0=> Secure state <1=> Non-Secure state +// Interrupt 332 <0=> Secure state <1=> Non-Secure state +// Interrupt 333 <0=> Secure state <1=> Non-Secure state +// Interrupt 334 <0=> Secure state <1=> Non-Secure state +// Interrupt 335 <0=> Secure state <1=> Non-Secure state +// Interrupt 336 <0=> Secure state <1=> Non-Secure state +// Interrupt 337 <0=> Secure state <1=> Non-Secure state +// Interrupt 338 <0=> Secure state <1=> Non-Secure state +// Interrupt 339 <0=> Secure state <1=> Non-Secure state +// Interrupt 340 <0=> Secure state <1=> Non-Secure state +// Interrupt 341 <0=> Secure state <1=> Non-Secure state +// Interrupt 342 <0=> Secure state <1=> Non-Secure state +// Interrupt 343 <0=> Secure state <1=> Non-Secure state +// Interrupt 344 <0=> Secure state <1=> Non-Secure state +// Interrupt 345 <0=> Secure state <1=> Non-Secure state +// Interrupt 346 <0=> Secure state <1=> Non-Secure state +// Interrupt 347 <0=> Secure state <1=> Non-Secure state +// Interrupt 348 <0=> Secure state <1=> Non-Secure state +// Interrupt 349 <0=> Secure state <1=> Non-Secure state +// Interrupt 350 <0=> Secure state <1=> Non-Secure state +// Interrupt 351 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS10_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 11 (Interrupts 352..383) +*/ +#define NVIC_INIT_ITNS11 0 + +/* +// Interrupts 352..383 +// Interrupt 352 <0=> Secure state <1=> Non-Secure state +// Interrupt 353 <0=> Secure state <1=> Non-Secure state +// Interrupt 354 <0=> Secure state <1=> Non-Secure state +// Interrupt 355 <0=> Secure state <1=> Non-Secure state +// Interrupt 356 <0=> Secure state <1=> Non-Secure state +// Interrupt 357 <0=> Secure state <1=> Non-Secure state +// Interrupt 358 <0=> Secure state <1=> Non-Secure state +// Interrupt 359 <0=> Secure state <1=> Non-Secure state +// Interrupt 360 <0=> Secure state <1=> Non-Secure state +// Interrupt 361 <0=> Secure state <1=> Non-Secure state +// Interrupt 362 <0=> Secure state <1=> Non-Secure state +// Interrupt 363 <0=> Secure state <1=> Non-Secure state +// Interrupt 364 <0=> Secure state <1=> Non-Secure state +// Interrupt 365 <0=> Secure state <1=> Non-Secure state +// Interrupt 366 <0=> Secure state <1=> Non-Secure state +// Interrupt 367 <0=> Secure state <1=> Non-Secure state +// Interrupt 368 <0=> Secure state <1=> Non-Secure state +// Interrupt 369 <0=> Secure state <1=> Non-Secure state +// Interrupt 370 <0=> Secure state <1=> Non-Secure state +// Interrupt 371 <0=> Secure state <1=> Non-Secure state +// Interrupt 372 <0=> Secure state <1=> Non-Secure state +// Interrupt 373 <0=> Secure state <1=> Non-Secure state +// Interrupt 374 <0=> Secure state <1=> Non-Secure state +// Interrupt 375 <0=> Secure state <1=> Non-Secure state +// Interrupt 376 <0=> Secure state <1=> Non-Secure state +// Interrupt 377 <0=> Secure state <1=> Non-Secure state +// Interrupt 378 <0=> Secure state <1=> Non-Secure state +// Interrupt 379 <0=> Secure state <1=> Non-Secure state +// Interrupt 380 <0=> Secure state <1=> Non-Secure state +// Interrupt 381 <0=> Secure state <1=> Non-Secure state +// Interrupt 382 <0=> Secure state <1=> Non-Secure state +// Interrupt 383 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS11_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 12 (Interrupts 384..415) +*/ +#define NVIC_INIT_ITNS12 0 + +/* +// Interrupts 384..415 +// Interrupt 384 <0=> Secure state <1=> Non-Secure state +// Interrupt 385 <0=> Secure state <1=> Non-Secure state +// Interrupt 386 <0=> Secure state <1=> Non-Secure state +// Interrupt 387 <0=> Secure state <1=> Non-Secure state +// Interrupt 388 <0=> Secure state <1=> Non-Secure state +// Interrupt 389 <0=> Secure state <1=> Non-Secure state +// Interrupt 390 <0=> Secure state <1=> Non-Secure state +// Interrupt 391 <0=> Secure state <1=> Non-Secure state +// Interrupt 392 <0=> Secure state <1=> Non-Secure state +// Interrupt 393 <0=> Secure state <1=> Non-Secure state +// Interrupt 394 <0=> Secure state <1=> Non-Secure state +// Interrupt 395 <0=> Secure state <1=> Non-Secure state +// Interrupt 396 <0=> Secure state <1=> Non-Secure state +// Interrupt 397 <0=> Secure state <1=> Non-Secure state +// Interrupt 398 <0=> Secure state <1=> Non-Secure state +// Interrupt 399 <0=> Secure state <1=> Non-Secure state +// Interrupt 400 <0=> Secure state <1=> Non-Secure state +// Interrupt 401 <0=> Secure state <1=> Non-Secure state +// Interrupt 402 <0=> Secure state <1=> Non-Secure state +// Interrupt 403 <0=> Secure state <1=> Non-Secure state +// Interrupt 404 <0=> Secure state <1=> Non-Secure state +// Interrupt 405 <0=> Secure state <1=> Non-Secure state +// Interrupt 406 <0=> Secure state <1=> Non-Secure state +// Interrupt 407 <0=> Secure state <1=> Non-Secure state +// Interrupt 408 <0=> Secure state <1=> Non-Secure state +// Interrupt 409 <0=> Secure state <1=> Non-Secure state +// Interrupt 410 <0=> Secure state <1=> Non-Secure state +// Interrupt 411 <0=> Secure state <1=> Non-Secure state +// Interrupt 412 <0=> Secure state <1=> Non-Secure state +// Interrupt 413 <0=> Secure state <1=> Non-Secure state +// Interrupt 414 <0=> Secure state <1=> Non-Secure state +// Interrupt 415 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS12_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 13 (Interrupts 416..447) +*/ +#define NVIC_INIT_ITNS13 0 + +/* +// Interrupts 416..447 +// Interrupt 416 <0=> Secure state <1=> Non-Secure state +// Interrupt 417 <0=> Secure state <1=> Non-Secure state +// Interrupt 418 <0=> Secure state <1=> Non-Secure state +// Interrupt 419 <0=> Secure state <1=> Non-Secure state +// Interrupt 420 <0=> Secure state <1=> Non-Secure state +// Interrupt 421 <0=> Secure state <1=> Non-Secure state +// Interrupt 422 <0=> Secure state <1=> Non-Secure state +// Interrupt 423 <0=> Secure state <1=> Non-Secure state +// Interrupt 424 <0=> Secure state <1=> Non-Secure state +// Interrupt 425 <0=> Secure state <1=> Non-Secure state +// Interrupt 426 <0=> Secure state <1=> Non-Secure state +// Interrupt 427 <0=> Secure state <1=> Non-Secure state +// Interrupt 428 <0=> Secure state <1=> Non-Secure state +// Interrupt 429 <0=> Secure state <1=> Non-Secure state +// Interrupt 430 <0=> Secure state <1=> Non-Secure state +// Interrupt 431 <0=> Secure state <1=> Non-Secure state +// Interrupt 432 <0=> Secure state <1=> Non-Secure state +// Interrupt 433 <0=> Secure state <1=> Non-Secure state +// Interrupt 434 <0=> Secure state <1=> Non-Secure state +// Interrupt 435 <0=> Secure state <1=> Non-Secure state +// Interrupt 436 <0=> Secure state <1=> Non-Secure state +// Interrupt 437 <0=> Secure state <1=> Non-Secure state +// Interrupt 438 <0=> Secure state <1=> Non-Secure state +// Interrupt 439 <0=> Secure state <1=> Non-Secure state +// Interrupt 440 <0=> Secure state <1=> Non-Secure state +// Interrupt 441 <0=> Secure state <1=> Non-Secure state +// Interrupt 442 <0=> Secure state <1=> Non-Secure state +// Interrupt 443 <0=> Secure state <1=> Non-Secure state +// Interrupt 444 <0=> Secure state <1=> Non-Secure state +// Interrupt 445 <0=> Secure state <1=> Non-Secure state +// Interrupt 446 <0=> Secure state <1=> Non-Secure state +// Interrupt 447 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS13_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 14 (Interrupts 448..479) +*/ +#define NVIC_INIT_ITNS14 0 + +/* +// Interrupts 448..479 +// Interrupt 448 <0=> Secure state <1=> Non-Secure state +// Interrupt 449 <0=> Secure state <1=> Non-Secure state +// Interrupt 450 <0=> Secure state <1=> Non-Secure state +// Interrupt 451 <0=> Secure state <1=> Non-Secure state +// Interrupt 452 <0=> Secure state <1=> Non-Secure state +// Interrupt 453 <0=> Secure state <1=> Non-Secure state +// Interrupt 454 <0=> Secure state <1=> Non-Secure state +// Interrupt 455 <0=> Secure state <1=> Non-Secure state +// Interrupt 456 <0=> Secure state <1=> Non-Secure state +// Interrupt 457 <0=> Secure state <1=> Non-Secure state +// Interrupt 458 <0=> Secure state <1=> Non-Secure state +// Interrupt 459 <0=> Secure state <1=> Non-Secure state +// Interrupt 460 <0=> Secure state <1=> Non-Secure state +// Interrupt 461 <0=> Secure state <1=> Non-Secure state +// Interrupt 462 <0=> Secure state <1=> Non-Secure state +// Interrupt 463 <0=> Secure state <1=> Non-Secure state +// Interrupt 464 <0=> Secure state <1=> Non-Secure state +// Interrupt 465 <0=> Secure state <1=> Non-Secure state +// Interrupt 466 <0=> Secure state <1=> Non-Secure state +// Interrupt 467 <0=> Secure state <1=> Non-Secure state +// Interrupt 468 <0=> Secure state <1=> Non-Secure state +// Interrupt 469 <0=> Secure state <1=> Non-Secure state +// Interrupt 470 <0=> Secure state <1=> Non-Secure state +// Interrupt 471 <0=> Secure state <1=> Non-Secure state +// Interrupt 472 <0=> Secure state <1=> Non-Secure state +// Interrupt 473 <0=> Secure state <1=> Non-Secure state +// Interrupt 474 <0=> Secure state <1=> Non-Secure state +// Interrupt 475 <0=> Secure state <1=> Non-Secure state +// Interrupt 476 <0=> Secure state <1=> Non-Secure state +// Interrupt 477 <0=> Secure state <1=> Non-Secure state +// Interrupt 478 <0=> Secure state <1=> Non-Secure state +// Interrupt 479 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS14_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 15 (Interrupts 480..511) +*/ +#define NVIC_INIT_ITNS15 0 + +/* +// Interrupts 480..511 +// Interrupt 480 <0=> Secure state <1=> Non-Secure state +// Interrupt 481 <0=> Secure state <1=> Non-Secure state +// Interrupt 482 <0=> Secure state <1=> Non-Secure state +// Interrupt 483 <0=> Secure state <1=> Non-Secure state +// Interrupt 484 <0=> Secure state <1=> Non-Secure state +// Interrupt 485 <0=> Secure state <1=> Non-Secure state +// Interrupt 486 <0=> Secure state <1=> Non-Secure state +// Interrupt 487 <0=> Secure state <1=> Non-Secure state +// Interrupt 488 <0=> Secure state <1=> Non-Secure state +// Interrupt 489 <0=> Secure state <1=> Non-Secure state +// Interrupt 490 <0=> Secure state <1=> Non-Secure state +// Interrupt 491 <0=> Secure state <1=> Non-Secure state +// Interrupt 492 <0=> Secure state <1=> Non-Secure state +// Interrupt 493 <0=> Secure state <1=> Non-Secure state +// Interrupt 494 <0=> Secure state <1=> Non-Secure state +// Interrupt 495 <0=> Secure state <1=> Non-Secure state +// Interrupt 496 <0=> Secure state <1=> Non-Secure state +// Interrupt 497 <0=> Secure state <1=> Non-Secure state +// Interrupt 498 <0=> Secure state <1=> Non-Secure state +// Interrupt 499 <0=> Secure state <1=> Non-Secure state +// Interrupt 500 <0=> Secure state <1=> Non-Secure state +// Interrupt 501 <0=> Secure state <1=> Non-Secure state +// Interrupt 502 <0=> Secure state <1=> Non-Secure state +// Interrupt 503 <0=> Secure state <1=> Non-Secure state +// Interrupt 504 <0=> Secure state <1=> Non-Secure state +// Interrupt 505 <0=> Secure state <1=> Non-Secure state +// Interrupt 506 <0=> Secure state <1=> Non-Secure state +// Interrupt 507 <0=> Secure state <1=> Non-Secure state +// Interrupt 508 <0=> Secure state <1=> Non-Secure state +// Interrupt 509 <0=> Secure state <1=> Non-Secure state +// Interrupt 510 <0=> Secure state <1=> Non-Secure state +// Interrupt 511 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS15_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + + + +/* + max 128 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + + #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) + NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; + #endif + + #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) + NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; + #endif + + #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) + NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; + #endif + + #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) + NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; + #endif + + #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) + NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; + #endif + + #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) + NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; + #endif + + #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) + NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; + #endif + + #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) + NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; + #endif + + #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) + NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; + #endif + + #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) + NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; + #endif + + #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) + NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; + #endif + + /* repeat this for all possible ITNS elements */ + +} + +#endif /* PARTITION_ARMCM33_H */ diff --git a/ports/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c b/ports/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c new file mode 100644 index 00000000..5ee4322c --- /dev/null +++ b/ports/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c @@ -0,0 +1,138 @@ +/****************************************************************************** + * @file startup_ARMCM33.c + * @brief CMSIS Core Device Startup File for Cortex-M33 Device + * @version V2.0.0 + * @date 20. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM33) + #include "ARMCM33.h" +#elif defined (ARMCM33_TZ) + #include "ARMCM33_TZ.h" +#elif defined (ARMCM33_DSP_FP) + #include "ARMCM33_DSP_FP.h" +#elif defined (ARMCM33_DSP_FP_TZ) + #include "ARMCM33_DSP_FP_TZ.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler Function Prototype + *----------------------------------------------------------------------------*/ +typedef void( *pFunc )( void ); + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern void __PROGRAM_START(void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Default_Handler(void) __NO_RETURN; +void Reset_Handler (void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const pFunc __VECTOR_TABLE[496]; + const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/ports/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c b/ports/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c new file mode 100644 index 00000000..9e1fcd22 --- /dev/null +++ b/ports/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c @@ -0,0 +1,116 @@ +/**************************************************************************//** + * @file system_ARMCM33.c + * @brief CMSIS Device System Source File for + * ARMCM33 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM33) + #include "ARMCM33.h" +#elif defined (ARMCM33_TZ) + #include "ARMCM33_TZ.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM33.h" + #endif +#elif defined (ARMCM33_DSP_FP) + #include "ARMCM33_DSP_FP.h" +#elif defined (ARMCM33_DSP_FP_TZ) + #include "ARMCM33_DSP_FP_TZ.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM33.h" + #endif +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; + + *(uint32_t *)0xE000ED24 = 0x000F0000; /* S: enable secure, usage, bus, mem faults */ + *(uint32_t *)0xE002ED24 = 0x000F0000; /* NS: enable secure, usage, bus, mem faults */ + +} + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +void HardFault_Handler(void) +{ + while(1); + +} + +void UsageFault_Handler(void) +{ + while(1); +} +#endif diff --git a/ports/cortex_m33/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h b/ports/cortex_m33/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h new file mode 100644 index 00000000..65bfdcd7 --- /dev/null +++ b/ports/cortex_m33/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'demo_secure_zone' + * Target: 'FVP Simulation Model' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/ports/cortex_m33/ac6/example_build/demo_secure_zone/demo_secure_zone.uvoptx b/ports/cortex_m33/ac6/example_build/demo_secure_zone/demo_secure_zone.uvoptx new file mode 100644 index 00000000..ec69bc69 --- /dev/null +++ b/ports/cortex_m33/ac6/example_build/demo_secure_zone/demo_secure_zone.uvoptx @@ -0,0 +1,328 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + FVP Simulation Model + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 15 + + + + + + + + + + ..\Debug.ini + BIN\DbgFMv8M.DLL + + + + 0 + DLGTARM + (6010=1267,114,1744,710,0)(6018=-1,-1,-1,-1,0)(6019=105,137,294,473,0)(6008=1877,-377,2171,-192,0)(6009=-1,-1,-1,-1,0)(6014=1814,-131,2072,600,0)(6015=-1,-1,-1,-1,0)(6003=-1,-1,-1,-1,0)(6000=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0) + + + 0 + DbgFMv8M + -I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMCM33_DSP_FP_TZ_config.txt" -MA + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + + 0 + 1 + thread_0_counter + + + 1 + 1 + thread_1_counter + + + 2 + 1 + thread_2_counter + + + 3 + 1 + thread_3_counter + + + 4 + 1 + thread_4_counter + + + 5 + 1 + thread_5_counter + + + 6 + 1 + thread_6_counter + + + 7 + 1 + thread_7_counter + + + 8 + 1 + _tx_thread_current_ptr + + + 9 + 1 + _tx_thread_execute_ptr + + + + + 1 + 2 + 0x2001ffd8 + 0 + + + + + 2 + 2 + 0xE000ED28 + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Secure Code + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + .\main_s.c + main_s.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\src\tx_thread_secure_stack.c + tx_thread_secure_stack.c + 0 + 0 + + + + + Interface + 1 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + .\interface.c + interface.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 1 + 0 + 0 + 1 + + + diff --git a/ports/cortex_m33/ac6/example_build/demo_secure_zone/demo_secure_zone.uvprojx b/ports/cortex_m33/ac6/example_build/demo_secure_zone/demo_secure_zone.uvprojx new file mode 100644 index 00000000..c2fac3e4 --- /dev/null +++ b/ports/cortex_m33/ac6/example_build/demo_secure_zone/demo_secure_zone.uvprojx @@ -0,0 +1,497 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + FVP Simulation Model + 0x4 + ARM-ADS + 6140000::V6.14::ARMCLANG + 1 + + + ARMCM33_DSP_FP_TZ + ARM + ARM.CMSIS.5.7.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ESEL ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM33_DSP_FP_TZ$Device\ARM\ARMCM33\Include\ARMCM33_DSP_FP_TZ.h + + + + + + + + + + $$Device:ARMCM33_DSP_FP_TZ$Device\ARM\SVD\ARMCM33.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + demo_secure_zone + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU + TCM.DLL + -pCM33 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 0 + -1 + + 1 + BIN\UL2V8M.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M33" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 1 + 1 + 8 + 1 + 1 + 0 + 1 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x200000 + + + 1 + 0x200000 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x20200000 + 0x20000 + + + + + + 1 + 7 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 0 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\..\common\inc, ..\..\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\RTE\Device\ARMCM33_DSP_FP_TZ\ARMCM33_AC6.sct + + + + + + + + + + + Secure Code + + + main_s.c + 1 + .\main_s.c + + + tx_thread_secure_stack.c + 1 + ..\..\src\tx_thread_secure_stack.c + + + + + Interface + + + interface.c + 1 + .\interface.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\ARMCM33_ac6.sct + + + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\partition_ARMCM33.h + + + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.c + + + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.s + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\system_ARMCM33.c + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/ports/cortex_m33/ac6/example_build/demo_secure_zone/interface.c b/ports/cortex_m33/ac6/example_build/demo_secure_zone/interface.c new file mode 100644 index 00000000..4e6e8eee --- /dev/null +++ b/ports/cortex_m33/ac6/example_build/demo_secure_zone/interface.c @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * interface.c Secure/non-secure callable application code + * + * Version 1.0 + * Initial Release + *---------------------------------------------------------------------------*/ + + +#include // CMSE definitions +#include "interface.h" // Header file with secure interface API + +/* typedef for non-secure callback functions */ +typedef funcptr funcptr_NS __attribute__((cmse_nonsecure_call)); + +/* Non-secure callable (entry) function */ +int func1(int x) __attribute__((cmse_nonsecure_entry)) { + return x+3; +} + +/* Non-secure callable (entry) function, calling a non-secure callback function */ +int func2(funcptr callback, int x) __attribute__((cmse_nonsecure_entry)) { + funcptr_NS callback_NS; // non-secure callback function pointer + int y; + + /* return function pointer with cleared LSB */ + callback_NS = (funcptr_NS)cmse_nsfptr_create(callback); + + y = callback_NS (x+1); + + return (y+2); +} diff --git a/ports/cortex_m33/ac6/example_build/demo_secure_zone/interface.h b/ports/cortex_m33/ac6/example_build/demo_secure_zone/interface.h new file mode 100644 index 00000000..8215d5a3 --- /dev/null +++ b/ports/cortex_m33/ac6/example_build/demo_secure_zone/interface.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * interface.h API definition for the non-secure state + * + * Version 1.0 + * Initial Release + *---------------------------------------------------------------------------*/ + +/* Function pointer declaration */ +typedef int (*funcptr)(int); + +/* Non-secure callable functions */ +extern int func1(int x); +extern int func2(funcptr callback, int x); diff --git a/ports/cortex_m33/ac6/example_build/demo_secure_zone/main_ns.c b/ports/cortex_m33/ac6/example_build/demo_secure_zone/main_ns.c new file mode 100644 index 00000000..a65b6880 --- /dev/null +++ b/ports/cortex_m33/ac6/example_build/demo_secure_zone/main_ns.c @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * main_ns.c Non-secure main function - RTOS demo + * + * Version 1.0 + * Initial Release + *---------------------------------------------------------------------------*/ + +#include "..\demo_secure_zone\interface.h" // Interface API +//#include "cmsis_os2.h" // ARM::CMSIS:RTOS2:Keil RTX5 + +//static osStatus_t Status; + +//static osThreadId_t ThreadA_Id; +//static osThreadId_t ThreadB_Id; +//static osThreadId_t ThreadC_Id; + +void ThreadA (void *argument); +void ThreadB (void *argument); +void ThreadC (void *argument); + + +extern volatile int counterA; +extern volatile int counterB; +extern volatile int counterC; + +volatile int counterA; +volatile int counterB; +volatile int counterC; + +/* +static int callbackA (int val) { + return (val); +} + +__attribute__((noreturn)) +void ThreadA (void *argument) { + (void)argument; + + for (;;) { + counterA = func1 (counterA); + counterA = func2 (callbackA, counterA); + osDelay(2U); + } +} + +static int callbackB (int val) { + uint32_t flags; + + flags = osThreadFlagsWait (1U, osFlagsWaitAny, osWaitForever); + if (flags == 1U) { + return (val+1); + } else { + return (0); + } +} + + +__attribute__((noreturn)) +void ThreadB (void *argument) { + (void)argument; + + for (;;) { + counterB = func1 (counterB); + counterB = func2 (callbackB, counterB); + } +} + +__attribute__((noreturn)) +void ThreadC (void *argument) { + (void)argument; + + for (;;) { + counterC = counterC + 1; + if ((counterC % 0x10) == 0) { + osThreadFlagsSet (ThreadB_Id, 1); + } + osDelay(1U); + } +} + +static const osThreadAttr_t ThreadAttr = { + .tz_module = 1U, // indicate calls to secure mode +}; +*/ +#if 1 +int main (void) { + + //Status = osKernelInitialize(); + + //ThreadA_Id = osThreadNew(ThreadA, NULL, &ThreadAttr); + //ThreadB_Id = osThreadNew(ThreadB, NULL, &ThreadAttr); + //ThreadC_Id = osThreadNew(ThreadC, NULL, NULL); + + //Status = osKernelStart(); + + for (;;); +} +#endif diff --git a/ports/cortex_m33/ac6/example_build/demo_secure_zone/main_s.c b/ports/cortex_m33/ac6/example_build/demo_secure_zone/main_s.c new file mode 100644 index 00000000..2c667821 --- /dev/null +++ b/ports/cortex_m33/ac6/example_build/demo_secure_zone/main_s.c @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 15. October 2016 + * $Revision: 1.1.0 + * + * Project: TrustZone for ARMv8-M + * Title: Code template for secure main function + * + *---------------------------------------------------------------------------*/ + +/* Use CMSE intrinsics */ +#include + #include +#include "RTE_Components.h" +#include CMSIS_device_header + +/* TZ_START_NS: Start address of non-secure application */ +#ifndef TZ_START_NS +#define TZ_START_NS (0x200000U) +#endif + +/* typedef for non-secure callback functions */ +typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call)); + +/* Secure main() */ +int main(void) { + funcptr_void NonSecure_ResetHandler; + + /* Add user setup code for secure part here*/ + + /* Set non-secure main stack (MSP_NS) */ + __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS))); + + /* Get non-secure reset handler */ + NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U))); + + /* Start non-secure state software application */ + NonSecure_ResetHandler(); + + /* Non-secure software does not return, this code is not executed */ + while (1) { + __NOP(); + } +} diff --git a/ports/cortex_m33/ac6/example_build/demo_secure_zone/tz_context.c b/ports/cortex_m33/ac6/example_build/demo_secure_zone/tz_context.c new file mode 100644 index 00000000..f3152890 --- /dev/null +++ b/ports/cortex_m33/ac6/example_build/demo_secure_zone/tz_context.c @@ -0,0 +1,203 @@ +/* + * Copyright (c) 2015-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------------- + * + * $Date: 15. October 2016 + * $Revision: 1.1.0 + * + * Project: TrustZone for ARMv8-M + * Title: Context Management for ARMv8-M TrustZone - Sample implementation + * + *---------------------------------------------------------------------------*/ + +#include "RTE_Components.h" +#include CMSIS_device_header +#include "tz_context.h" + +/// Number of process slots (threads may call secure library code) +#ifndef TZ_PROCESS_STACK_SLOTS +#define TZ_PROCESS_STACK_SLOTS 8U +#endif + +/// Stack size of the secure library code +#ifndef TZ_PROCESS_STACK_SIZE +#define TZ_PROCESS_STACK_SIZE 256U +#endif + +typedef struct { + uint32_t sp_top; // stack space top + uint32_t sp_limit; // stack space limit + uint32_t sp; // current stack pointer +} stack_info_t; + +static stack_info_t ProcessStackInfo [TZ_PROCESS_STACK_SLOTS]; +static uint64_t ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U]; +static uint32_t ProcessStackFreeSlot = 0xFFFFFFFFU; + + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_InitContextSystem_S (void) { + uint32_t n; + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) { + ProcessStackInfo[n].sp = 0U; + ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n]; + ProcessStackInfo[n].sp_top = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE; + *((uint32_t *)ProcessStackMemory[n]) = n + 1U; + } + *((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU; + + ProcessStackFreeSlot = 0U; + + // Default process stack pointer and stack limit + __set_PSPLIM((uint32_t)ProcessStackMemory); + __set_PSP ((uint32_t)ProcessStackMemory); + + // Privileged Thread Mode using PSP + __set_CONTROL(0x02U); + + return 1U; // Success +} + + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +__attribute__((cmse_nonsecure_entry)) +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) { + uint32_t slot; + + (void)module; // Ignore (fixed Stack size) + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + if (ProcessStackFreeSlot == 0xFFFFFFFFU) { + return 0U; // No slot available + } + + slot = ProcessStackFreeSlot; + ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]); + + ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top; + + return (slot + 1U); +} + + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) { + uint32_t slot; + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + ProcessStackInfo[slot].sp = 0U; + + *((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot; + ProcessStackFreeSlot = slot; + + return 1U; // Success +} + + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id) { + uint32_t slot; + + if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { + return 0U; // Thread Mode or using Main Stack for threads + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + + // Setup process stack pointer and stack limit + __set_PSPLIM(ProcessStackInfo[slot].sp_limit); + __set_PSP (ProcessStackInfo[slot].sp); + + return 1U; // Success +} + + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id) { + uint32_t slot; + uint32_t sp; + + if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { + return 0U; // Thread Mode or using Main Stack for threads + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + + sp = __get_PSP(); + if ((sp < ProcessStackInfo[slot].sp_limit) || + (sp > ProcessStackInfo[slot].sp_top)) { + return 0U; // SP out of range + } + ProcessStackInfo[slot].sp = sp; + + // Default process stack pointer and stack limit + __set_PSPLIM((uint32_t)ProcessStackMemory); + __set_PSP ((uint32_t)ProcessStackMemory); + + return 1U; // Success +} diff --git a/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/Objects/ExtDll.iex b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/Objects/ExtDll.iex new file mode 100644 index 00000000..6c0896e1 --- /dev/null +++ b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/Objects/ExtDll.iex @@ -0,0 +1,2 @@ +[EXTDLL] +Count=0 diff --git a/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c new file mode 100644 index 00000000..e4871014 --- /dev/null +++ b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + + for (;;) {} +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; + + switch (code) { + case osRtxErrorStackUnderflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +} diff --git a/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h new file mode 100644 index 00000000..3021efbc --- /dev/null +++ b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,578 @@ +/* + * Copyright (c) 2013-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.5.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 4096 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 4096 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 0 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 1 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 0 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 256 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 256 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 256 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 256 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch. +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 256 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 256 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial recording level applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Recording levels for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Recording level for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_LEVEL +#define OS_EVR_MEMORY_LEVEL 0x01U +#endif + +// Kernel +// Recording level for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_LEVEL +#define OS_EVR_KERNEL_LEVEL 0x01U +#endif + +// Thread +// Recording level for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_LEVEL +#define OS_EVR_THREAD_LEVEL 0x05U +#endif + +// Generic Wait +// Recording level for Generic Wait events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_WAIT_LEVEL +#define OS_EVR_WAIT_LEVEL 0x01U +#endif + +// Thread Flags +// Recording level for Thread Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THFLAGS_LEVEL +#define OS_EVR_THFLAGS_LEVEL 0x01U +#endif + +// Event Flags +// Recording level for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_LEVEL +#define OS_EVR_EVFLAGS_LEVEL 0x01U +#endif + +// Timer +// Recording level for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_LEVEL +#define OS_EVR_TIMER_LEVEL 0x01U +#endif + +// Mutex +// Recording level for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_LEVEL +#define OS_EVR_MUTEX_LEVEL 0x01U +#endif + +// Semaphore +// Recording level for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_LEVEL +#define OS_EVR_SEMAPHORE_LEVEL 0x01U +#endif + +// Memory Pool +// Recording level for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_LEVEL +#define OS_EVR_MEMPOOL_LEVEL 0x01U +#endif + +// Message Queue +// Recording level for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_LEVEL +#define OS_EVR_MSGQUEUE_LEVEL 0x01U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Generic Wait +// Enables Generic Wait event generation. +#ifndef OS_EVR_WAIT +#define OS_EVR_WAIT 1 +#endif + +// Thread Flags +// Enables Thread Flags event generation. +#ifndef OS_EVR_THFLAGS +#define OS_EVR_THFLAGS 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#define OS_THREAD_LIBSPACE_NUM 4 +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_AC6.sct b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_AC6.sct new file mode 100644 index 00000000..3480c921 --- /dev/null +++ b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/ARMCM33_AC6.sct @@ -0,0 +1,74 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc +; command above MUST be in first line (no comment above!) + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x00200000 +#define __ROM_SIZE 0x00200000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20200000 +#define __RAM_SIZE 0x00020000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000400 +#define __HEAP_SIZE 0x00000C00 + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundery definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ +#define __RO_BASE __ROM_BASE +#define __RO_SIZE __ROM_SIZE + +#define __RW_BASE (__RAM_BASE ) +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) + + + +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) +; *(Veneer$$CMSE) ; uncomment for secure applications + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } +} diff --git a/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h new file mode 100644 index 00000000..a7cb0d73 --- /dev/null +++ b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/partition_ARMCM33.h @@ -0,0 +1,1260 @@ +/**************************************************************************//** + * @file partition_ARMCM33.h + * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM33 + * @version V1.1.1 + * @date 12. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PARTITION_ARMCM33_H +#define PARTITION_ARMCM33_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 1 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x00200000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x003FFFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x20200000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x203FFFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x40040000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 1 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 1 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 1 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x80-0xFF +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 1 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// Interrupt 0 <0=> Secure state <1=> Non-Secure state +// Interrupt 1 <0=> Secure state <1=> Non-Secure state +// Interrupt 2 <0=> Secure state <1=> Non-Secure state +// Interrupt 3 <0=> Secure state <1=> Non-Secure state +// Interrupt 4 <0=> Secure state <1=> Non-Secure state +// Interrupt 5 <0=> Secure state <1=> Non-Secure state +// Interrupt 6 <0=> Secure state <1=> Non-Secure state +// Interrupt 7 <0=> Secure state <1=> Non-Secure state +// Interrupt 8 <0=> Secure state <1=> Non-Secure state +// Interrupt 9 <0=> Secure state <1=> Non-Secure state +// Interrupt 10 <0=> Secure state <1=> Non-Secure state +// Interrupt 11 <0=> Secure state <1=> Non-Secure state +// Interrupt 12 <0=> Secure state <1=> Non-Secure state +// Interrupt 13 <0=> Secure state <1=> Non-Secure state +// Interrupt 14 <0=> Secure state <1=> Non-Secure state +// Interrupt 15 <0=> Secure state <1=> Non-Secure state +// Interrupt 16 <0=> Secure state <1=> Non-Secure state +// Interrupt 17 <0=> Secure state <1=> Non-Secure state +// Interrupt 18 <0=> Secure state <1=> Non-Secure state +// Interrupt 19 <0=> Secure state <1=> Non-Secure state +// Interrupt 20 <0=> Secure state <1=> Non-Secure state +// Interrupt 21 <0=> Secure state <1=> Non-Secure state +// Interrupt 22 <0=> Secure state <1=> Non-Secure state +// Interrupt 23 <0=> Secure state <1=> Non-Secure state +// Interrupt 24 <0=> Secure state <1=> Non-Secure state +// Interrupt 25 <0=> Secure state <1=> Non-Secure state +// Interrupt 26 <0=> Secure state <1=> Non-Secure state +// Interrupt 27 <0=> Secure state <1=> Non-Secure state +// Interrupt 28 <0=> Secure state <1=> Non-Secure state +// Interrupt 29 <0=> Secure state <1=> Non-Secure state +// Interrupt 30 <0=> Secure state <1=> Non-Secure state +// Interrupt 31 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// Interrupt 32 <0=> Secure state <1=> Non-Secure state +// Interrupt 33 <0=> Secure state <1=> Non-Secure state +// Interrupt 34 <0=> Secure state <1=> Non-Secure state +// Interrupt 35 <0=> Secure state <1=> Non-Secure state +// Interrupt 36 <0=> Secure state <1=> Non-Secure state +// Interrupt 37 <0=> Secure state <1=> Non-Secure state +// Interrupt 38 <0=> Secure state <1=> Non-Secure state +// Interrupt 39 <0=> Secure state <1=> Non-Secure state +// Interrupt 40 <0=> Secure state <1=> Non-Secure state +// Interrupt 41 <0=> Secure state <1=> Non-Secure state +// Interrupt 42 <0=> Secure state <1=> Non-Secure state +// Interrupt 43 <0=> Secure state <1=> Non-Secure state +// Interrupt 44 <0=> Secure state <1=> Non-Secure state +// Interrupt 45 <0=> Secure state <1=> Non-Secure state +// Interrupt 46 <0=> Secure state <1=> Non-Secure state +// Interrupt 47 <0=> Secure state <1=> Non-Secure state +// Interrupt 48 <0=> Secure state <1=> Non-Secure state +// Interrupt 49 <0=> Secure state <1=> Non-Secure state +// Interrupt 50 <0=> Secure state <1=> Non-Secure state +// Interrupt 51 <0=> Secure state <1=> Non-Secure state +// Interrupt 52 <0=> Secure state <1=> Non-Secure state +// Interrupt 53 <0=> Secure state <1=> Non-Secure state +// Interrupt 54 <0=> Secure state <1=> Non-Secure state +// Interrupt 55 <0=> Secure state <1=> Non-Secure state +// Interrupt 56 <0=> Secure state <1=> Non-Secure state +// Interrupt 57 <0=> Secure state <1=> Non-Secure state +// Interrupt 58 <0=> Secure state <1=> Non-Secure state +// Interrupt 59 <0=> Secure state <1=> Non-Secure state +// Interrupt 60 <0=> Secure state <1=> Non-Secure state +// Interrupt 61 <0=> Secure state <1=> Non-Secure state +// Interrupt 62 <0=> Secure state <1=> Non-Secure state +// Interrupt 63 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 0 + +/* +// Interrupts 64..95 +// Interrupt 64 <0=> Secure state <1=> Non-Secure state +// Interrupt 65 <0=> Secure state <1=> Non-Secure state +// Interrupt 66 <0=> Secure state <1=> Non-Secure state +// Interrupt 67 <0=> Secure state <1=> Non-Secure state +// Interrupt 68 <0=> Secure state <1=> Non-Secure state +// Interrupt 69 <0=> Secure state <1=> Non-Secure state +// Interrupt 70 <0=> Secure state <1=> Non-Secure state +// Interrupt 71 <0=> Secure state <1=> Non-Secure state +// Interrupt 72 <0=> Secure state <1=> Non-Secure state +// Interrupt 73 <0=> Secure state <1=> Non-Secure state +// Interrupt 74 <0=> Secure state <1=> Non-Secure state +// Interrupt 75 <0=> Secure state <1=> Non-Secure state +// Interrupt 76 <0=> Secure state <1=> Non-Secure state +// Interrupt 77 <0=> Secure state <1=> Non-Secure state +// Interrupt 78 <0=> Secure state <1=> Non-Secure state +// Interrupt 79 <0=> Secure state <1=> Non-Secure state +// Interrupt 80 <0=> Secure state <1=> Non-Secure state +// Interrupt 81 <0=> Secure state <1=> Non-Secure state +// Interrupt 82 <0=> Secure state <1=> Non-Secure state +// Interrupt 83 <0=> Secure state <1=> Non-Secure state +// Interrupt 84 <0=> Secure state <1=> Non-Secure state +// Interrupt 85 <0=> Secure state <1=> Non-Secure state +// Interrupt 86 <0=> Secure state <1=> Non-Secure state +// Interrupt 87 <0=> Secure state <1=> Non-Secure state +// Interrupt 88 <0=> Secure state <1=> Non-Secure state +// Interrupt 89 <0=> Secure state <1=> Non-Secure state +// Interrupt 90 <0=> Secure state <1=> Non-Secure state +// Interrupt 91 <0=> Secure state <1=> Non-Secure state +// Interrupt 92 <0=> Secure state <1=> Non-Secure state +// Interrupt 93 <0=> Secure state <1=> Non-Secure state +// Interrupt 94 <0=> Secure state <1=> Non-Secure state +// Interrupt 95 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 0 + +/* +// Interrupts 96..127 +// Interrupt 96 <0=> Secure state <1=> Non-Secure state +// Interrupt 97 <0=> Secure state <1=> Non-Secure state +// Interrupt 98 <0=> Secure state <1=> Non-Secure state +// Interrupt 99 <0=> Secure state <1=> Non-Secure state +// Interrupt 100 <0=> Secure state <1=> Non-Secure state +// Interrupt 101 <0=> Secure state <1=> Non-Secure state +// Interrupt 102 <0=> Secure state <1=> Non-Secure state +// Interrupt 103 <0=> Secure state <1=> Non-Secure state +// Interrupt 104 <0=> Secure state <1=> Non-Secure state +// Interrupt 105 <0=> Secure state <1=> Non-Secure state +// Interrupt 106 <0=> Secure state <1=> Non-Secure state +// Interrupt 107 <0=> Secure state <1=> Non-Secure state +// Interrupt 108 <0=> Secure state <1=> Non-Secure state +// Interrupt 109 <0=> Secure state <1=> Non-Secure state +// Interrupt 110 <0=> Secure state <1=> Non-Secure state +// Interrupt 111 <0=> Secure state <1=> Non-Secure state +// Interrupt 112 <0=> Secure state <1=> Non-Secure state +// Interrupt 113 <0=> Secure state <1=> Non-Secure state +// Interrupt 114 <0=> Secure state <1=> Non-Secure state +// Interrupt 115 <0=> Secure state <1=> Non-Secure state +// Interrupt 116 <0=> Secure state <1=> Non-Secure state +// Interrupt 117 <0=> Secure state <1=> Non-Secure state +// Interrupt 118 <0=> Secure state <1=> Non-Secure state +// Interrupt 119 <0=> Secure state <1=> Non-Secure state +// Interrupt 120 <0=> Secure state <1=> Non-Secure state +// Interrupt 121 <0=> Secure state <1=> Non-Secure state +// Interrupt 122 <0=> Secure state <1=> Non-Secure state +// Interrupt 123 <0=> Secure state <1=> Non-Secure state +// Interrupt 124 <0=> Secure state <1=> Non-Secure state +// Interrupt 125 <0=> Secure state <1=> Non-Secure state +// Interrupt 126 <0=> Secure state <1=> Non-Secure state +// Interrupt 127 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..159) +*/ +#define NVIC_INIT_ITNS4 0 + +/* +// Interrupts 128..159 +// Interrupt 128 <0=> Secure state <1=> Non-Secure state +// Interrupt 129 <0=> Secure state <1=> Non-Secure state +// Interrupt 130 <0=> Secure state <1=> Non-Secure state +// Interrupt 131 <0=> Secure state <1=> Non-Secure state +// Interrupt 132 <0=> Secure state <1=> Non-Secure state +// Interrupt 133 <0=> Secure state <1=> Non-Secure state +// Interrupt 134 <0=> Secure state <1=> Non-Secure state +// Interrupt 135 <0=> Secure state <1=> Non-Secure state +// Interrupt 136 <0=> Secure state <1=> Non-Secure state +// Interrupt 137 <0=> Secure state <1=> Non-Secure state +// Interrupt 138 <0=> Secure state <1=> Non-Secure state +// Interrupt 139 <0=> Secure state <1=> Non-Secure state +// Interrupt 140 <0=> Secure state <1=> Non-Secure state +// Interrupt 141 <0=> Secure state <1=> Non-Secure state +// Interrupt 142 <0=> Secure state <1=> Non-Secure state +// Interrupt 143 <0=> Secure state <1=> Non-Secure state +// Interrupt 144 <0=> Secure state <1=> Non-Secure state +// Interrupt 145 <0=> Secure state <1=> Non-Secure state +// Interrupt 146 <0=> Secure state <1=> Non-Secure state +// Interrupt 147 <0=> Secure state <1=> Non-Secure state +// Interrupt 148 <0=> Secure state <1=> Non-Secure state +// Interrupt 149 <0=> Secure state <1=> Non-Secure state +// Interrupt 150 <0=> Secure state <1=> Non-Secure state +// Interrupt 151 <0=> Secure state <1=> Non-Secure state +// Interrupt 152 <0=> Secure state <1=> Non-Secure state +// Interrupt 153 <0=> Secure state <1=> Non-Secure state +// Interrupt 154 <0=> Secure state <1=> Non-Secure state +// Interrupt 155 <0=> Secure state <1=> Non-Secure state +// Interrupt 156 <0=> Secure state <1=> Non-Secure state +// Interrupt 157 <0=> Secure state <1=> Non-Secure state +// Interrupt 158 <0=> Secure state <1=> Non-Secure state +// Interrupt 159 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 5 (Interrupts 160..191) +*/ +#define NVIC_INIT_ITNS5 0 + +/* +// Interrupts 160..191 +// Interrupt 160 <0=> Secure state <1=> Non-Secure state +// Interrupt 161 <0=> Secure state <1=> Non-Secure state +// Interrupt 162 <0=> Secure state <1=> Non-Secure state +// Interrupt 163 <0=> Secure state <1=> Non-Secure state +// Interrupt 164 <0=> Secure state <1=> Non-Secure state +// Interrupt 165 <0=> Secure state <1=> Non-Secure state +// Interrupt 166 <0=> Secure state <1=> Non-Secure state +// Interrupt 167 <0=> Secure state <1=> Non-Secure state +// Interrupt 168 <0=> Secure state <1=> Non-Secure state +// Interrupt 169 <0=> Secure state <1=> Non-Secure state +// Interrupt 170 <0=> Secure state <1=> Non-Secure state +// Interrupt 171 <0=> Secure state <1=> Non-Secure state +// Interrupt 172 <0=> Secure state <1=> Non-Secure state +// Interrupt 173 <0=> Secure state <1=> Non-Secure state +// Interrupt 174 <0=> Secure state <1=> Non-Secure state +// Interrupt 175 <0=> Secure state <1=> Non-Secure state +// Interrupt 176 <0=> Secure state <1=> Non-Secure state +// Interrupt 177 <0=> Secure state <1=> Non-Secure state +// Interrupt 178 <0=> Secure state <1=> Non-Secure state +// Interrupt 179 <0=> Secure state <1=> Non-Secure state +// Interrupt 180 <0=> Secure state <1=> Non-Secure state +// Interrupt 181 <0=> Secure state <1=> Non-Secure state +// Interrupt 182 <0=> Secure state <1=> Non-Secure state +// Interrupt 183 <0=> Secure state <1=> Non-Secure state +// Interrupt 184 <0=> Secure state <1=> Non-Secure state +// Interrupt 185 <0=> Secure state <1=> Non-Secure state +// Interrupt 186 <0=> Secure state <1=> Non-Secure state +// Interrupt 187 <0=> Secure state <1=> Non-Secure state +// Interrupt 188 <0=> Secure state <1=> Non-Secure state +// Interrupt 189 <0=> Secure state <1=> Non-Secure state +// Interrupt 190 <0=> Secure state <1=> Non-Secure state +// Interrupt 191 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS5_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 6 (Interrupts 192..223) +*/ +#define NVIC_INIT_ITNS6 0 + +/* +// Interrupts 192..223 +// Interrupt 192 <0=> Secure state <1=> Non-Secure state +// Interrupt 193 <0=> Secure state <1=> Non-Secure state +// Interrupt 194 <0=> Secure state <1=> Non-Secure state +// Interrupt 195 <0=> Secure state <1=> Non-Secure state +// Interrupt 196 <0=> Secure state <1=> Non-Secure state +// Interrupt 197 <0=> Secure state <1=> Non-Secure state +// Interrupt 198 <0=> Secure state <1=> Non-Secure state +// Interrupt 199 <0=> Secure state <1=> Non-Secure state +// Interrupt 200 <0=> Secure state <1=> Non-Secure state +// Interrupt 201 <0=> Secure state <1=> Non-Secure state +// Interrupt 202 <0=> Secure state <1=> Non-Secure state +// Interrupt 203 <0=> Secure state <1=> Non-Secure state +// Interrupt 204 <0=> Secure state <1=> Non-Secure state +// Interrupt 205 <0=> Secure state <1=> Non-Secure state +// Interrupt 206 <0=> Secure state <1=> Non-Secure state +// Interrupt 207 <0=> Secure state <1=> Non-Secure state +// Interrupt 208 <0=> Secure state <1=> Non-Secure state +// Interrupt 209 <0=> Secure state <1=> Non-Secure state +// Interrupt 210 <0=> Secure state <1=> Non-Secure state +// Interrupt 211 <0=> Secure state <1=> Non-Secure state +// Interrupt 212 <0=> Secure state <1=> Non-Secure state +// Interrupt 213 <0=> Secure state <1=> Non-Secure state +// Interrupt 214 <0=> Secure state <1=> Non-Secure state +// Interrupt 215 <0=> Secure state <1=> Non-Secure state +// Interrupt 216 <0=> Secure state <1=> Non-Secure state +// Interrupt 217 <0=> Secure state <1=> Non-Secure state +// Interrupt 218 <0=> Secure state <1=> Non-Secure state +// Interrupt 219 <0=> Secure state <1=> Non-Secure state +// Interrupt 220 <0=> Secure state <1=> Non-Secure state +// Interrupt 221 <0=> Secure state <1=> Non-Secure state +// Interrupt 222 <0=> Secure state <1=> Non-Secure state +// Interrupt 223 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS6_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 7 (Interrupts 224..255) +*/ +#define NVIC_INIT_ITNS7 0 + +/* +// Interrupts 224..255 +// Interrupt 224 <0=> Secure state <1=> Non-Secure state +// Interrupt 225 <0=> Secure state <1=> Non-Secure state +// Interrupt 226 <0=> Secure state <1=> Non-Secure state +// Interrupt 227 <0=> Secure state <1=> Non-Secure state +// Interrupt 228 <0=> Secure state <1=> Non-Secure state +// Interrupt 229 <0=> Secure state <1=> Non-Secure state +// Interrupt 230 <0=> Secure state <1=> Non-Secure state +// Interrupt 231 <0=> Secure state <1=> Non-Secure state +// Interrupt 232 <0=> Secure state <1=> Non-Secure state +// Interrupt 233 <0=> Secure state <1=> Non-Secure state +// Interrupt 234 <0=> Secure state <1=> Non-Secure state +// Interrupt 235 <0=> Secure state <1=> Non-Secure state +// Interrupt 236 <0=> Secure state <1=> Non-Secure state +// Interrupt 237 <0=> Secure state <1=> Non-Secure state +// Interrupt 238 <0=> Secure state <1=> Non-Secure state +// Interrupt 239 <0=> Secure state <1=> Non-Secure state +// Interrupt 240 <0=> Secure state <1=> Non-Secure state +// Interrupt 241 <0=> Secure state <1=> Non-Secure state +// Interrupt 242 <0=> Secure state <1=> Non-Secure state +// Interrupt 243 <0=> Secure state <1=> Non-Secure state +// Interrupt 244 <0=> Secure state <1=> Non-Secure state +// Interrupt 245 <0=> Secure state <1=> Non-Secure state +// Interrupt 246 <0=> Secure state <1=> Non-Secure state +// Interrupt 247 <0=> Secure state <1=> Non-Secure state +// Interrupt 248 <0=> Secure state <1=> Non-Secure state +// Interrupt 249 <0=> Secure state <1=> Non-Secure state +// Interrupt 250 <0=> Secure state <1=> Non-Secure state +// Interrupt 251 <0=> Secure state <1=> Non-Secure state +// Interrupt 252 <0=> Secure state <1=> Non-Secure state +// Interrupt 253 <0=> Secure state <1=> Non-Secure state +// Interrupt 254 <0=> Secure state <1=> Non-Secure state +// Interrupt 255 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS7_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 8 (Interrupts 256..287) +*/ +#define NVIC_INIT_ITNS8 0 + +/* +// Interrupts 256..287 +// Interrupt 256 <0=> Secure state <1=> Non-Secure state +// Interrupt 257 <0=> Secure state <1=> Non-Secure state +// Interrupt 258 <0=> Secure state <1=> Non-Secure state +// Interrupt 259 <0=> Secure state <1=> Non-Secure state +// Interrupt 260 <0=> Secure state <1=> Non-Secure state +// Interrupt 261 <0=> Secure state <1=> Non-Secure state +// Interrupt 262 <0=> Secure state <1=> Non-Secure state +// Interrupt 263 <0=> Secure state <1=> Non-Secure state +// Interrupt 264 <0=> Secure state <1=> Non-Secure state +// Interrupt 265 <0=> Secure state <1=> Non-Secure state +// Interrupt 266 <0=> Secure state <1=> Non-Secure state +// Interrupt 267 <0=> Secure state <1=> Non-Secure state +// Interrupt 268 <0=> Secure state <1=> Non-Secure state +// Interrupt 269 <0=> Secure state <1=> Non-Secure state +// Interrupt 270 <0=> Secure state <1=> Non-Secure state +// Interrupt 271 <0=> Secure state <1=> Non-Secure state +// Interrupt 272 <0=> Secure state <1=> Non-Secure state +// Interrupt 273 <0=> Secure state <1=> Non-Secure state +// Interrupt 274 <0=> Secure state <1=> Non-Secure state +// Interrupt 275 <0=> Secure state <1=> Non-Secure state +// Interrupt 276 <0=> Secure state <1=> Non-Secure state +// Interrupt 277 <0=> Secure state <1=> Non-Secure state +// Interrupt 278 <0=> Secure state <1=> Non-Secure state +// Interrupt 279 <0=> Secure state <1=> Non-Secure state +// Interrupt 280 <0=> Secure state <1=> Non-Secure state +// Interrupt 281 <0=> Secure state <1=> Non-Secure state +// Interrupt 282 <0=> Secure state <1=> Non-Secure state +// Interrupt 283 <0=> Secure state <1=> Non-Secure state +// Interrupt 284 <0=> Secure state <1=> Non-Secure state +// Interrupt 285 <0=> Secure state <1=> Non-Secure state +// Interrupt 286 <0=> Secure state <1=> Non-Secure state +// Interrupt 287 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS8_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 9 (Interrupts 288..319) +*/ +#define NVIC_INIT_ITNS9 0 + +/* +// Interrupts 288..319 +// Interrupt 288 <0=> Secure state <1=> Non-Secure state +// Interrupt 289 <0=> Secure state <1=> Non-Secure state +// Interrupt 290 <0=> Secure state <1=> Non-Secure state +// Interrupt 291 <0=> Secure state <1=> Non-Secure state +// Interrupt 292 <0=> Secure state <1=> Non-Secure state +// Interrupt 293 <0=> Secure state <1=> Non-Secure state +// Interrupt 294 <0=> Secure state <1=> Non-Secure state +// Interrupt 295 <0=> Secure state <1=> Non-Secure state +// Interrupt 296 <0=> Secure state <1=> Non-Secure state +// Interrupt 297 <0=> Secure state <1=> Non-Secure state +// Interrupt 298 <0=> Secure state <1=> Non-Secure state +// Interrupt 299 <0=> Secure state <1=> Non-Secure state +// Interrupt 300 <0=> Secure state <1=> Non-Secure state +// Interrupt 301 <0=> Secure state <1=> Non-Secure state +// Interrupt 302 <0=> Secure state <1=> Non-Secure state +// Interrupt 303 <0=> Secure state <1=> Non-Secure state +// Interrupt 304 <0=> Secure state <1=> Non-Secure state +// Interrupt 305 <0=> Secure state <1=> Non-Secure state +// Interrupt 306 <0=> Secure state <1=> Non-Secure state +// Interrupt 307 <0=> Secure state <1=> Non-Secure state +// Interrupt 308 <0=> Secure state <1=> Non-Secure state +// Interrupt 309 <0=> Secure state <1=> Non-Secure state +// Interrupt 310 <0=> Secure state <1=> Non-Secure state +// Interrupt 311 <0=> Secure state <1=> Non-Secure state +// Interrupt 312 <0=> Secure state <1=> Non-Secure state +// Interrupt 313 <0=> Secure state <1=> Non-Secure state +// Interrupt 314 <0=> Secure state <1=> Non-Secure state +// Interrupt 315 <0=> Secure state <1=> Non-Secure state +// Interrupt 316 <0=> Secure state <1=> Non-Secure state +// Interrupt 317 <0=> Secure state <1=> Non-Secure state +// Interrupt 318 <0=> Secure state <1=> Non-Secure state +// Interrupt 319 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS9_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 10 (Interrupts 320..351) +*/ +#define NVIC_INIT_ITNS10 0 + +/* +// Interrupts 320..351 +// Interrupt 320 <0=> Secure state <1=> Non-Secure state +// Interrupt 321 <0=> Secure state <1=> Non-Secure state +// Interrupt 322 <0=> Secure state <1=> Non-Secure state +// Interrupt 323 <0=> Secure state <1=> Non-Secure state +// Interrupt 324 <0=> Secure state <1=> Non-Secure state +// Interrupt 325 <0=> Secure state <1=> Non-Secure state +// Interrupt 326 <0=> Secure state <1=> Non-Secure state +// Interrupt 327 <0=> Secure state <1=> Non-Secure state +// Interrupt 328 <0=> Secure state <1=> Non-Secure state +// Interrupt 329 <0=> Secure state <1=> Non-Secure state +// Interrupt 330 <0=> Secure state <1=> Non-Secure state +// Interrupt 331 <0=> Secure state <1=> Non-Secure state +// Interrupt 332 <0=> Secure state <1=> Non-Secure state +// Interrupt 333 <0=> Secure state <1=> Non-Secure state +// Interrupt 334 <0=> Secure state <1=> Non-Secure state +// Interrupt 335 <0=> Secure state <1=> Non-Secure state +// Interrupt 336 <0=> Secure state <1=> Non-Secure state +// Interrupt 337 <0=> Secure state <1=> Non-Secure state +// Interrupt 338 <0=> Secure state <1=> Non-Secure state +// Interrupt 339 <0=> Secure state <1=> Non-Secure state +// Interrupt 340 <0=> Secure state <1=> Non-Secure state +// Interrupt 341 <0=> Secure state <1=> Non-Secure state +// Interrupt 342 <0=> Secure state <1=> Non-Secure state +// Interrupt 343 <0=> Secure state <1=> Non-Secure state +// Interrupt 344 <0=> Secure state <1=> Non-Secure state +// Interrupt 345 <0=> Secure state <1=> Non-Secure state +// Interrupt 346 <0=> Secure state <1=> Non-Secure state +// Interrupt 347 <0=> Secure state <1=> Non-Secure state +// Interrupt 348 <0=> Secure state <1=> Non-Secure state +// Interrupt 349 <0=> Secure state <1=> Non-Secure state +// Interrupt 350 <0=> Secure state <1=> Non-Secure state +// Interrupt 351 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS10_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 11 (Interrupts 352..383) +*/ +#define NVIC_INIT_ITNS11 0 + +/* +// Interrupts 352..383 +// Interrupt 352 <0=> Secure state <1=> Non-Secure state +// Interrupt 353 <0=> Secure state <1=> Non-Secure state +// Interrupt 354 <0=> Secure state <1=> Non-Secure state +// Interrupt 355 <0=> Secure state <1=> Non-Secure state +// Interrupt 356 <0=> Secure state <1=> Non-Secure state +// Interrupt 357 <0=> Secure state <1=> Non-Secure state +// Interrupt 358 <0=> Secure state <1=> Non-Secure state +// Interrupt 359 <0=> Secure state <1=> Non-Secure state +// Interrupt 360 <0=> Secure state <1=> Non-Secure state +// Interrupt 361 <0=> Secure state <1=> Non-Secure state +// Interrupt 362 <0=> Secure state <1=> Non-Secure state +// Interrupt 363 <0=> Secure state <1=> Non-Secure state +// Interrupt 364 <0=> Secure state <1=> Non-Secure state +// Interrupt 365 <0=> Secure state <1=> Non-Secure state +// Interrupt 366 <0=> Secure state <1=> Non-Secure state +// Interrupt 367 <0=> Secure state <1=> Non-Secure state +// Interrupt 368 <0=> Secure state <1=> Non-Secure state +// Interrupt 369 <0=> Secure state <1=> Non-Secure state +// Interrupt 370 <0=> Secure state <1=> Non-Secure state +// Interrupt 371 <0=> Secure state <1=> Non-Secure state +// Interrupt 372 <0=> Secure state <1=> Non-Secure state +// Interrupt 373 <0=> Secure state <1=> Non-Secure state +// Interrupt 374 <0=> Secure state <1=> Non-Secure state +// Interrupt 375 <0=> Secure state <1=> Non-Secure state +// Interrupt 376 <0=> Secure state <1=> Non-Secure state +// Interrupt 377 <0=> Secure state <1=> Non-Secure state +// Interrupt 378 <0=> Secure state <1=> Non-Secure state +// Interrupt 379 <0=> Secure state <1=> Non-Secure state +// Interrupt 380 <0=> Secure state <1=> Non-Secure state +// Interrupt 381 <0=> Secure state <1=> Non-Secure state +// Interrupt 382 <0=> Secure state <1=> Non-Secure state +// Interrupt 383 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS11_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 12 (Interrupts 384..415) +*/ +#define NVIC_INIT_ITNS12 0 + +/* +// Interrupts 384..415 +// Interrupt 384 <0=> Secure state <1=> Non-Secure state +// Interrupt 385 <0=> Secure state <1=> Non-Secure state +// Interrupt 386 <0=> Secure state <1=> Non-Secure state +// Interrupt 387 <0=> Secure state <1=> Non-Secure state +// Interrupt 388 <0=> Secure state <1=> Non-Secure state +// Interrupt 389 <0=> Secure state <1=> Non-Secure state +// Interrupt 390 <0=> Secure state <1=> Non-Secure state +// Interrupt 391 <0=> Secure state <1=> Non-Secure state +// Interrupt 392 <0=> Secure state <1=> Non-Secure state +// Interrupt 393 <0=> Secure state <1=> Non-Secure state +// Interrupt 394 <0=> Secure state <1=> Non-Secure state +// Interrupt 395 <0=> Secure state <1=> Non-Secure state +// Interrupt 396 <0=> Secure state <1=> Non-Secure state +// Interrupt 397 <0=> Secure state <1=> Non-Secure state +// Interrupt 398 <0=> Secure state <1=> Non-Secure state +// Interrupt 399 <0=> Secure state <1=> Non-Secure state +// Interrupt 400 <0=> Secure state <1=> Non-Secure state +// Interrupt 401 <0=> Secure state <1=> Non-Secure state +// Interrupt 402 <0=> Secure state <1=> Non-Secure state +// Interrupt 403 <0=> Secure state <1=> Non-Secure state +// Interrupt 404 <0=> Secure state <1=> Non-Secure state +// Interrupt 405 <0=> Secure state <1=> Non-Secure state +// Interrupt 406 <0=> Secure state <1=> Non-Secure state +// Interrupt 407 <0=> Secure state <1=> Non-Secure state +// Interrupt 408 <0=> Secure state <1=> Non-Secure state +// Interrupt 409 <0=> Secure state <1=> Non-Secure state +// Interrupt 410 <0=> Secure state <1=> Non-Secure state +// Interrupt 411 <0=> Secure state <1=> Non-Secure state +// Interrupt 412 <0=> Secure state <1=> Non-Secure state +// Interrupt 413 <0=> Secure state <1=> Non-Secure state +// Interrupt 414 <0=> Secure state <1=> Non-Secure state +// Interrupt 415 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS12_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 13 (Interrupts 416..447) +*/ +#define NVIC_INIT_ITNS13 0 + +/* +// Interrupts 416..447 +// Interrupt 416 <0=> Secure state <1=> Non-Secure state +// Interrupt 417 <0=> Secure state <1=> Non-Secure state +// Interrupt 418 <0=> Secure state <1=> Non-Secure state +// Interrupt 419 <0=> Secure state <1=> Non-Secure state +// Interrupt 420 <0=> Secure state <1=> Non-Secure state +// Interrupt 421 <0=> Secure state <1=> Non-Secure state +// Interrupt 422 <0=> Secure state <1=> Non-Secure state +// Interrupt 423 <0=> Secure state <1=> Non-Secure state +// Interrupt 424 <0=> Secure state <1=> Non-Secure state +// Interrupt 425 <0=> Secure state <1=> Non-Secure state +// Interrupt 426 <0=> Secure state <1=> Non-Secure state +// Interrupt 427 <0=> Secure state <1=> Non-Secure state +// Interrupt 428 <0=> Secure state <1=> Non-Secure state +// Interrupt 429 <0=> Secure state <1=> Non-Secure state +// Interrupt 430 <0=> Secure state <1=> Non-Secure state +// Interrupt 431 <0=> Secure state <1=> Non-Secure state +// Interrupt 432 <0=> Secure state <1=> Non-Secure state +// Interrupt 433 <0=> Secure state <1=> Non-Secure state +// Interrupt 434 <0=> Secure state <1=> Non-Secure state +// Interrupt 435 <0=> Secure state <1=> Non-Secure state +// Interrupt 436 <0=> Secure state <1=> Non-Secure state +// Interrupt 437 <0=> Secure state <1=> Non-Secure state +// Interrupt 438 <0=> Secure state <1=> Non-Secure state +// Interrupt 439 <0=> Secure state <1=> Non-Secure state +// Interrupt 440 <0=> Secure state <1=> Non-Secure state +// Interrupt 441 <0=> Secure state <1=> Non-Secure state +// Interrupt 442 <0=> Secure state <1=> Non-Secure state +// Interrupt 443 <0=> Secure state <1=> Non-Secure state +// Interrupt 444 <0=> Secure state <1=> Non-Secure state +// Interrupt 445 <0=> Secure state <1=> Non-Secure state +// Interrupt 446 <0=> Secure state <1=> Non-Secure state +// Interrupt 447 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS13_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 14 (Interrupts 448..479) +*/ +#define NVIC_INIT_ITNS14 0 + +/* +// Interrupts 448..479 +// Interrupt 448 <0=> Secure state <1=> Non-Secure state +// Interrupt 449 <0=> Secure state <1=> Non-Secure state +// Interrupt 450 <0=> Secure state <1=> Non-Secure state +// Interrupt 451 <0=> Secure state <1=> Non-Secure state +// Interrupt 452 <0=> Secure state <1=> Non-Secure state +// Interrupt 453 <0=> Secure state <1=> Non-Secure state +// Interrupt 454 <0=> Secure state <1=> Non-Secure state +// Interrupt 455 <0=> Secure state <1=> Non-Secure state +// Interrupt 456 <0=> Secure state <1=> Non-Secure state +// Interrupt 457 <0=> Secure state <1=> Non-Secure state +// Interrupt 458 <0=> Secure state <1=> Non-Secure state +// Interrupt 459 <0=> Secure state <1=> Non-Secure state +// Interrupt 460 <0=> Secure state <1=> Non-Secure state +// Interrupt 461 <0=> Secure state <1=> Non-Secure state +// Interrupt 462 <0=> Secure state <1=> Non-Secure state +// Interrupt 463 <0=> Secure state <1=> Non-Secure state +// Interrupt 464 <0=> Secure state <1=> Non-Secure state +// Interrupt 465 <0=> Secure state <1=> Non-Secure state +// Interrupt 466 <0=> Secure state <1=> Non-Secure state +// Interrupt 467 <0=> Secure state <1=> Non-Secure state +// Interrupt 468 <0=> Secure state <1=> Non-Secure state +// Interrupt 469 <0=> Secure state <1=> Non-Secure state +// Interrupt 470 <0=> Secure state <1=> Non-Secure state +// Interrupt 471 <0=> Secure state <1=> Non-Secure state +// Interrupt 472 <0=> Secure state <1=> Non-Secure state +// Interrupt 473 <0=> Secure state <1=> Non-Secure state +// Interrupt 474 <0=> Secure state <1=> Non-Secure state +// Interrupt 475 <0=> Secure state <1=> Non-Secure state +// Interrupt 476 <0=> Secure state <1=> Non-Secure state +// Interrupt 477 <0=> Secure state <1=> Non-Secure state +// Interrupt 478 <0=> Secure state <1=> Non-Secure state +// Interrupt 479 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS14_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 15 (Interrupts 480..511) +*/ +#define NVIC_INIT_ITNS15 0 + +/* +// Interrupts 480..511 +// Interrupt 480 <0=> Secure state <1=> Non-Secure state +// Interrupt 481 <0=> Secure state <1=> Non-Secure state +// Interrupt 482 <0=> Secure state <1=> Non-Secure state +// Interrupt 483 <0=> Secure state <1=> Non-Secure state +// Interrupt 484 <0=> Secure state <1=> Non-Secure state +// Interrupt 485 <0=> Secure state <1=> Non-Secure state +// Interrupt 486 <0=> Secure state <1=> Non-Secure state +// Interrupt 487 <0=> Secure state <1=> Non-Secure state +// Interrupt 488 <0=> Secure state <1=> Non-Secure state +// Interrupt 489 <0=> Secure state <1=> Non-Secure state +// Interrupt 490 <0=> Secure state <1=> Non-Secure state +// Interrupt 491 <0=> Secure state <1=> Non-Secure state +// Interrupt 492 <0=> Secure state <1=> Non-Secure state +// Interrupt 493 <0=> Secure state <1=> Non-Secure state +// Interrupt 494 <0=> Secure state <1=> Non-Secure state +// Interrupt 495 <0=> Secure state <1=> Non-Secure state +// Interrupt 496 <0=> Secure state <1=> Non-Secure state +// Interrupt 497 <0=> Secure state <1=> Non-Secure state +// Interrupt 498 <0=> Secure state <1=> Non-Secure state +// Interrupt 499 <0=> Secure state <1=> Non-Secure state +// Interrupt 500 <0=> Secure state <1=> Non-Secure state +// Interrupt 501 <0=> Secure state <1=> Non-Secure state +// Interrupt 502 <0=> Secure state <1=> Non-Secure state +// Interrupt 503 <0=> Secure state <1=> Non-Secure state +// Interrupt 504 <0=> Secure state <1=> Non-Secure state +// Interrupt 505 <0=> Secure state <1=> Non-Secure state +// Interrupt 506 <0=> Secure state <1=> Non-Secure state +// Interrupt 507 <0=> Secure state <1=> Non-Secure state +// Interrupt 508 <0=> Secure state <1=> Non-Secure state +// Interrupt 509 <0=> Secure state <1=> Non-Secure state +// Interrupt 510 <0=> Secure state <1=> Non-Secure state +// Interrupt 511 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS15_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + + + +/* + max 128 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + + #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) + NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; + #endif + + #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) + NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; + #endif + + #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) + NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; + #endif + + #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) + NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; + #endif + + #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) + NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; + #endif + + #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) + NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; + #endif + + #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) + NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; + #endif + + #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) + NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; + #endif + + #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) + NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; + #endif + + #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) + NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; + #endif + + #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) + NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; + #endif + + /* repeat this for all possible ITNS elements */ + +} + +#endif /* PARTITION_ARMCM33_H */ diff --git a/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c new file mode 100644 index 00000000..5ee4322c --- /dev/null +++ b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/startup_ARMCM33.c @@ -0,0 +1,138 @@ +/****************************************************************************** + * @file startup_ARMCM33.c + * @brief CMSIS Core Device Startup File for Cortex-M33 Device + * @version V2.0.0 + * @date 20. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM33) + #include "ARMCM33.h" +#elif defined (ARMCM33_TZ) + #include "ARMCM33_TZ.h" +#elif defined (ARMCM33_DSP_FP) + #include "ARMCM33_DSP_FP.h" +#elif defined (ARMCM33_DSP_FP_TZ) + #include "ARMCM33_DSP_FP_TZ.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler Function Prototype + *----------------------------------------------------------------------------*/ +typedef void( *pFunc )( void ); + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern void __PROGRAM_START(void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Default_Handler(void) __NO_RETURN; +void Reset_Handler (void) __NO_RETURN; + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const pFunc __VECTOR_TABLE[496]; + const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} diff --git a/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c new file mode 100644 index 00000000..17679234 --- /dev/null +++ b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/system_ARMCM33.c @@ -0,0 +1,99 @@ +/**************************************************************************//** + * @file system_ARMCM33.c + * @brief CMSIS Device System Source File for + * ARMCM33 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM33) + #include "ARMCM33.h" +#elif defined (ARMCM33_TZ) + #include "ARMCM33_TZ.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM33.h" + #endif +#elif defined (ARMCM33_DSP_FP) + #include "ARMCM33_DSP_FP.h" +#elif defined (ARMCM33_DSP_FP_TZ) + #include "ARMCM33_DSP_FP_TZ.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM33.h" + #endif +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h new file mode 100644 index 00000000..78d1b429 --- /dev/null +++ b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'demo_threadx_non-secure_zone' + * Target: 'FVP Simulation Model' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h new file mode 100644 index 00000000..1eb74752 --- /dev/null +++ b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'ThreadX_Library' + * Target: 'ThreadX_Library_Project' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/ThreadX_Demo.uvopt b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/ThreadX_Demo.uvopt new file mode 100644 index 00000000..7ec4b36b --- /dev/null +++ b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/ThreadX_Demo.uvopt @@ -0,0 +1,305 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + ThreadX_Demo + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 1 + 0 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + -1 + + + + + + + + + + + + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0) + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(102=-1,-1,-1,-1,0)(103=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(163=-1,-1,-1,-1,0)(164=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)(152=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)(1013=-1,-1,-1,-1,0)(171=-1,-1,-1,-1,0)(172=-1,-1,-1,-1,0)(173=-1,-1,-1,-1,0)(1014=-1,-1,-1,-1,0)(1016=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T5F + + + 0 + UL2CM3 + -UV0289BJE -O14 -S0 -C0 -N00("ARM CoreSight JTAG-DP") -D00(3BA00477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_16 -FS00 -FL04000 + + + + + + 0 + 1 + thread_0_counter + + + 1 + 1 + thread_1_counter + + + 2 + 1 + thread_2_counter + + + 3 + 1 + thread_3_counter + + + 4 + 1 + thread_4_counter + + + 5 + 1 + thread_5_counter + + + 6 + 1 + _tx_thread_current_ptr + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Source Group + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + .\tx_initialize_low_level.s + tx_initialize_low_level.s + 0 + 0 + + + 1 + 2 + 1 + 1 + 0 + 0 + .\demo_threadx.c + demo_threadx.c + 0 + 0 + + 44 + 0 + 1 + + -1 + -1 + + + -1 + -1 + + + 56 + 12 + 1633 + 671 + + + + + + + Library_Group + 1 + 0 + 0 + 0 + + 2 + 3 + 4 + 0 + 0 + 0 + .\ThreadX_Library.lib + ThreadX_Library.lib + 0 + 0 + + + + diff --git a/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/ThreadX_Demo.uvproj b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/ThreadX_Demo.uvproj new file mode 100644 index 00000000..5f5dcbdb --- /dev/null +++ b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/ThreadX_Demo.uvproj @@ -0,0 +1,556 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + ThreadX_Demo + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + Cortex-M4 FPU + ARM + CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 + + + + 5237 + + + + + + + + + + + + 0 + 0 + + + + Luminary\ + Luminary\ + + 0 + 0 + 0 + 0 + 1 + + .\ + threadx_demo + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DCM.DLL + -pCM4F + SARMCM3.DLL + + TCM.DLL + -pCM4F + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + + 0 + -1 + + + + + + + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 4096 + + 0 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + --first __tx_vectors --entry=__main + + + + + + + + Source Group + + + 0 + 1 + 1 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 0 + + + + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + tx_initialize_low_level.s + 2 + .\tx_initialize_low_level.s + + + 2 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 2 + 2 + 1 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + demo_threadx.c + 1 + .\demo_threadx.c + + + + + Library_Group + + + ThreadX_Library.lib + 4 + .\ThreadX_Library.lib + + + + + + + + diff --git a/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx.c b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx.c new file mode 100644 index 00000000..7257ac6d --- /dev/null +++ b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx.c @@ -0,0 +1,401 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. Please refer to Chapter 6 of the ThreadX User Guide for a complete + description of this demonstration. */ + +#include "tx_api.h" +#include "..\demo_secure_zone\interface.h" /* Interface to sample secure functions. */ + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +static TX_THREAD thread_0; +static TX_THREAD thread_1; +static TX_THREAD thread_2; +static TX_THREAD thread_3; +static TX_THREAD thread_4; +static TX_THREAD thread_5; +static TX_THREAD thread_6; +static TX_THREAD thread_7; +static TX_QUEUE queue_0; +static TX_SEMAPHORE semaphore_0; +static TX_MUTEX mutex_0; +static TX_EVENT_FLAGS_GROUP event_flags_0; +static TX_BYTE_POOL byte_pool_0; +static TX_BLOCK_POOL block_pool_0; + +/* Define byte pool memory. */ + +static UCHAR byte_pool_memory[DEMO_BYTE_POOL_SIZE]; + + +/* Define event buffer. */ + +#ifdef TX_ENABLE_EVENT_TRACE +UCHAR trace_buffer[0x10000]; +#endif + + +/* Define the counters used in the demo application... */ + +static ULONG thread_0_counter; +static ULONG thread_1_counter; +static ULONG thread_1_messages_sent; +static ULONG thread_2_counter; +static ULONG thread_2_messages_received; +static ULONG thread_3_counter; +static ULONG thread_4_counter; +static ULONG thread_5_counter; +static ULONG thread_6_counter; +static ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + +/* Define main entry point. */ + +int main() +{ + + /* Please refer to Chapter 6 of the ThreadX User Guide for a complete + description of this demonstration. */ + + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer; + + (VOID)first_unused_memory; /* unused parameter. */ + +#ifdef TX_ENABLE_EVENT_TRACE + tx_trace_enable(trace_buffer, sizeof(trace_buffer), 32); +#endif + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", byte_pool_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); + + tx_thread_secure_stack_allocate(&thread_0,256); + tx_thread_secure_stack_allocate(&thread_1,256); + tx_thread_secure_stack_allocate(&thread_2,256); + tx_thread_secure_stack_allocate(&thread_3,256); + tx_thread_secure_stack_allocate(&thread_4,256); + tx_thread_secure_stack_allocate(&thread_5,256); + tx_thread_secure_stack_allocate(&thread_6,256); + tx_thread_secure_stack_allocate(&thread_7,256); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ +UINT status; + + (VOID)thread_input; /* unused parameter. */ + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + (VOID)thread_input; /* unused parameter. */ + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + (VOID)thread_input; /* unused parameter. */ + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + (VOID)thread_input; /* unused parameter. */ + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx_non-secure_zone.uvoptx b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx_non-secure_zone.uvoptx new file mode 100644 index 00000000..5d966f5b --- /dev/null +++ b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx_non-secure_zone.uvoptx @@ -0,0 +1,342 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + FVP Simulation Model + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 15 + + + + + + + + + + ..\Debug.ini + BIN\DbgFMv8M.DLL + + + + 0 + PWSTATINFO + 200,50,700 + + + 0 + DLGTARM + (6010=1243,118,1720,714,0)(6018=1284,352,1473,701,0)(6019=1328,34,1517,370,0)(6008=-1,-1,-1,-1,0)(6009=969,18,1263,203,0)(6014=1111,129,1369,860,0)(6015=872,146,1130,768,0)(6003=-1,-1,-1,-1,0)(6000=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0)(106=511,345,1277,660,0)(107=-1,-1,-1,-1,0) + + + 0 + DbgFMv8M + -I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMCM33_DSP_FP_TZ_config.txt" -PF -MA + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FC1000 -FD20000000 + + + + + + 0 + 1 + thread_0_counter + + + 1 + 1 + thread_1_counter + + + 2 + 1 + thread_2_counter + + + 3 + 1 + thread_3_counter + + + 4 + 1 + thread_4_counter + + + 5 + 1 + thread_5_counter + + + 6 + 1 + thread_6_counter + + + 7 + 1 + thread_7_counter + + + + + 1 + 2 + 0x20200a10 + 0 + + + + + 2 + 2 + 0xE000ED28 + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 1 + 10000000 + + + + + + Non-secure Code + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + .\demo_threadx.c + demo_threadx.c + 0 + 0 + + + 1 + 2 + 4 + 0 + 0 + 0 + ..\ThreadX_Library.lib + ThreadX_Library.lib + 0 + 0 + + + + + CMSE Library + 1 + 0 + 0 + 0 + + 2 + 3 + 5 + 0 + 0 + 0 + ..\demo_secure_zone\interface.h + interface.h + 0 + 0 + + + 2 + 4 + 3 + 0 + 0 + 0 + ..\demo_secure_zone\Objects\demo_secure_zone_CMSE_Lib.o + demo_secure_zone_CMSE_Lib.o + 0 + 0 + + + + + ::CMSIS + 1 + 0 + 0 + 1 + + + + ::Device + 1 + 0 + 0 + 1 + + + diff --git a/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx_non-secure_zone.uvprojx b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx_non-secure_zone.uvprojx new file mode 100644 index 00000000..159e9d25 --- /dev/null +++ b/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx_non-secure_zone.uvprojx @@ -0,0 +1,585 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + FVP Simulation Model + 0x4 + ARM-ADS + 6140000::V6.14::ARMCLANG + 1 + + + ARMCM33_DSP_FP_TZ + ARM + ARM.CMSIS.5.7.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ESEL ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM33_DSP_FP_TZ$Device\ARM\ARMCM33\Include\ARMCM33_DSP_FP_TZ.h + + + + + + + + + + $$Device:ARMCM33_DSP_FP_TZ$Device\ARM\SVD\ARMCM33.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + demo_threadx_non-secure_zone + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU + TCM.DLL + -pCM33 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 0 + -1 + + 1 + BIN\UL2V8M.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M33" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 1 + 1 + 16 + 1 + 1 + 0 + 0 + 4 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x200000 + + + 1 + 0x200000 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x20200000 + 0x20000 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 3 + 1 + 1 + 1 + 0 + 0 + 0 + + -Wno-unused-function -Wno-visibility + + + ..\..\..\..\..\common\inc, ..\..\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\RTE\Device\ARMCM33_DSP_FP_TZ\ARMCM33_AC6.sct + + + + + + + + + + + Non-secure Code + + + demo_threadx.c + 1 + .\demo_threadx.c + + + ThreadX_Library.lib + 4 + ..\ThreadX_Library.lib + + + + + CMSE Library + + + interface.h + 5 + ..\demo_secure_zone\interface.h + + + demo_secure_zone_CMSE_Lib.o + 3 + ..\demo_secure_zone\Objects\demo_secure_zone_CMSE_Lib.o + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + RTE\Device\ARMCM33_DSP_FP\startup_ARMCM33.s + + + + + + RTE\Device\ARMCM33_DSP_FP\system_ARMCM33.c + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\ARMCM33_ac6.sct + + + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\partition_ARMCM33.h + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.c + + + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.s + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\system_ARMCM33.c + + + + + + + + RTE\Device\ARMCM33_TZ\partition_ARMCM33.h + + + + + + RTE\Device\ARMCM33_TZ\startup_ARMCM33.s + + + + + + RTE\Device\ARMCM33_TZ\system_ARMCM33.c + + + + + + RTE\Device\ARMv8MBL\partition_ARMv8MBL.h + + + + + + RTE\Device\ARMv8MBL\startup_ARMv8MBL.s + + + + + + RTE\Device\ARMv8MBL\system_ARMv8MBL.c + + + + + + RTE\Device\CMSDK_ARMv8MBL\RTE_Device.h + + + + + + RTE\Device\CMSDK_ARMv8MBL\partition_CMSDK_ARMv8MBL.h + + + + + + RTE\Device\CMSDK_ARMv8MBL\startup_CMSDK_ARMv8MBL.s + + + + + + RTE\Device\CMSDK_ARMv8MBL\system_CMSDK_ARMv8MBL.c + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/ports/cortex_m33/ac6/example_build/tx_initialize_low_level.S b/ports/cortex_m33/ac6/example_build/tx_initialize_low_level.S new file mode 100644 index 00000000..bc2c31cf --- /dev/null +++ b/ports/cortex_m33/ac6/example_build/tx_initialize_low_level.S @@ -0,0 +1,268 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +SYSTEM_CLOCK = 6000000 +SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) + +/* Setup the stack and heap areas. */ + +STACK_SIZE = 0x00000400 +HEAP_SIZE = 0x00000000 + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-M33/AC6 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_initialize_low_level(VOID) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_initialize_low_level + .thumb_func +.type _tx_initialize_low_level, function +_tx_initialize_low_level: + + /* Disable interrupts during ThreadX initialization. */ + CPSID i + + /* Set base of available memory to end of non-initialised RAM area. */ + LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer + LDR r1, =Image$$ARM_LIB_STACK$$ZI$$Limit // Build first free address + ADD r1, r1, #4 // + STR r1, [r0] // Setup first unused memory pointer + + /* Setup Vector Table Offset Register. */ + MOV r0, #0xE000E000 // Build address of NVIC registers + LDR r1, =__Vectors // Pickup address of vector table + STR r1, [r0, #0xD08] // Set vector table address + + /* Enable the cycle count register. */ + LDR r0, =0xE0001000 // Build address of DWT register + LDR r1, [r0] // Pickup the current value + ORR r1, r1, #1 // Set the CYCCNTENA bit + STR r1, [r0] // Enable the cycle count register + + /* Set system stack pointer from vector value. */ + LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer + LDR r1, =__Vectors // Pickup address of vector table + LDR r1, [r1] // Pickup reset stack pointer + STR r1, [r0] // Save system stack pointer + + /* Configure SysTick. */ + MOV r0, #0xE000E000 // Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] // Setup SysTick Reload Value + MOV r1, #0x7 // Build SysTick Control Enable Value + STR r1, [r0, #0x10] // Setup SysTick Control + + /* Configure handler priorities. */ + LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] // Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] // Setup System Handlers 8-11 Priority Registers + // Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] // Setup System Handlers 12-15 Priority Registers + // Note: PnSV must be lowest priority, which is 0xFF + + /* Return to caller. */ + BX lr +// } + + +/* Define shells for each of the unused vectors. */ + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global __tx_BadHandler + .thumb_func +.type __tx_BadHandler, function +__tx_BadHandler: + B __tx_BadHandler + + + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global __tx_IntHandler + .thumb_func +.type __tx_IntHandler, function +__tx_IntHandler: +// VOID InterruptHandler (VOID) +// { + PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) + + /* Do interrupt handler work here */ + /* .... */ + + POP {r0,lr} + BX LR +// } + + + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global SysTick_Handler + .thumb_func +.type SysTick_Handler, function +SysTick_Handler: +// VOID TimerInterruptHandler (VOID) +// { + PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) + BL _tx_timer_interrupt + POP {r0,lr} + BX LR +// } + + + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global HardFault_Handler + .thumb_func +.type HardFault_Handler, function +HardFault_Handler: + B HardFault_Handler + + + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global UsageFault_Handler + .thumb_func +.type UsageFault_Handler, function +UsageFault_Handler: + CPSID i // Disable interrupts + // Check for stack limit fault + LDR r0, =0xE000ED28 // CFSR address + LDR r1,[r0] // Pick up CFSR + TST r1, #0x00100000 // Check for Stack Overflow +_unhandled_usage_loop: + BEQ _unhandled_usage_loop // If not stack overflow then loop + + // Handle stack overflow + STR r1, [r0] // Clear CFSR flag(s) + +#ifdef __ARM_PCS_VFP + LDR r0, =0xE000EF34 // Cleanup FPU context: Load FPCCR address + LDR r1, [r0] // Load FPCCR + BIC r1, r1, #1 // Clear the lazy preservation active bit + STR r1, [r0] // Store the value +#endif + + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r0,[r0] // Pick up current thread pointer + PUSH {r0,lr} // Save LR (and r0 to maintain stack alignment) + BL _tx_thread_stack_error_handler // Call ThreadX/user handler + POP {r0,lr} // Restore LR and dummy reg + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + // Call the thread exit function to indicate the thread is no longer executing. + PUSH {r0, lr} // Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit // Call the thread exit function + POP {r0, lr} // Recover LR +#endif + + MOV r1, #0 // Build NULL value + LDR r0, =_tx_thread_current_ptr // Pickup address of current thread pointer + STR r1, [r0] // Clear current thread pointer + + // Return from UsageFault_Handler exception + LDR r0, =0xE000ED04 // Load ICSR + LDR r1, =0x10000000 // Set PENDSVSET bit + STR r1, [r0] // Store ICSR + DSB // Wait for memory access to complete + CPSIE i // Enable interrupts + BX lr // Return from exception + + + + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global __tx_NMIHandler + .thumb_func +.type __tx_NMIHandler, function +__tx_NMIHandler: + B __tx_NMIHandler + + + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global __tx_DBGHandler + .thumb_func +.type __tx_DBGHandler, function +__tx_DBGHandler: + B __tx_DBGHandler + + .end diff --git a/ports/cortex_m33/ac6/inc/tx_port.h b/ports/cortex_m33/ac6/inc/tx_port.h new file mode 100644 index 00000000..bee06e96 --- /dev/null +++ b/ports/cortex_m33/ac6/inc/tx_port.h @@ -0,0 +1,551 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-M33/AC6 */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + +/* Determine if the optional ThreadX user define file should be used. */ +#ifdef TX_INCLUDE_USER_DEFINE_FILE + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + +/* Define compiler library include files. */ + +#include +#include +#include +#include "ARMCM33_DSP_FP_TZ.h" /* For intrinsic functions. */ + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef unsigned long long ULONG64; +typedef short SHORT; +typedef unsigned short USHORT; + +/* Function prototypes for this port. */ +struct TX_THREAD_STRUCT; +UINT _txe_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *thread_ptr, ULONG stack_size); +UINT _txe_thread_secure_stack_free(struct TX_THREAD_STRUCT *thread_ptr); +UINT _tx_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *tx_thread, ULONG stack_size); +UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); + +/* This hardware has stack checking that we take advantage of - do NOT define. */ +#ifdef TX_ENABLE_STACK_CHECKING + #error "Do not define TX_ENABLE_STACK_CHECKING" +#endif + +/* If user does not want to terminate thread on stack overflow, + #define the TX_THREAD_NO_TERMINATE_STACK_ERROR symbol. + The thread will be rescheduled and continue to cause the exception. + It is suggested user code handle this by registering a notification with the + tx_thread_stack_error_notify function. */ +/*#define TX_THREAD_NO_TERMINATE_STACK_ERROR */ + +/* Define the system API mappings based on the error checking + selected by the user. Note: this section is only applicable to + application source code, hence the conditional that turns off this + stuff when the include file is processed by the ThreadX source. */ + +#ifndef TX_SOURCE_CODE + + +/* Determine if error checking is desired. If so, map API functions + to the appropriate error checking front-ends. Otherwise, map API + functions to the core functions that actually perform the work. + Note: error checking is enabled by default. */ + +#ifdef TX_DISABLE_ERROR_CHECKING + +/* Services without error checking. */ + +#define tx_thread_secure_stack_allocate _tx_thread_secure_stack_allocate +#define tx_thread_secure_stack_free _tx_thread_secure_stack_free + +#else + +/* Services with error checking. */ + +#define tx_thread_secure_stack_allocate _txe_thread_secure_stack_allocate +#define tx_thread_secure_stack_free _txe_thread_secure_stack_free + +#endif +#endif + + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX Cortex-M33 port. */ + +#define TX_INT_DISABLE 1 /* Disable interrupts */ +#define TX_INT_ENABLE 0 /* Enable interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) +#endif +#else +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif + +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_secure_stack_context; +#else +#define TX_THREAD_EXTENSION_2 +#endif +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) if(thread_ptr -> tx_thread_secure_stack_context){_tx_thread_secure_stack_free(thread_ptr);} +#else +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +/* Define the size of the secure stack for the timer thread and use the extension to allocate the secure stack. */ +#define TX_TIMER_THREAD_SECURE_STACK_SIZE 256 +#define TX_TIMER_INITIALIZE_EXTENSION(status) _tx_thread_secure_stack_allocate(&_tx_timer_thread, TX_TIMER_THREAD_SECURE_STACK_SIZE); +#endif + + +#ifndef TX_MISRA_ENABLE + +//register unsigned int _ipsr __asm ("MRS %[result], ipsr" : [result] "=r" (_ipsr) : ); +inline static unsigned int _get_ipsr(void); +inline static unsigned int _get_ipsr(void) +{ + unsigned int _ipsr; + __asm("MRS %[result], ipsr" : [result] "=r" (_ipsr) : ); + return _ipsr; +} + +#endif + + +#ifdef __ARM_PCS_VFP + +#ifdef TX_MISRA_ENABLE + +ULONG _tx_misra_control_get(void); +void _tx_misra_control_set(ULONG value); +ULONG _tx_misra_fpccr_get(void); +void _tx_misra_vfp_touch(void); + +#else + +#ifdef TX_SOURCE_CODE + +static unsigned int _get_control(void); +static unsigned int _get_control(void) +{ + unsigned int _control; + __asm("MRS %[result], control" : [result] "=r" (_control) : ); + return _control; +} + +static void _set_control(unsigned int _control); +static void _set_control(unsigned int _control) +{ + __asm("MSR control, %[input]" : : [input] "r" (_control)); +} + +#endif +#endif + +/* A completed thread falls into _thread_shell_entry and we can simply deactivate the FPU via CONTROL.FPCA + in order to ensure no lazy stacking will occur. */ + +#ifndef TX_MISRA_ENABLE + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _get_control(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _set_control(_tx_vfp_state);; \ + } +#else + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } + +#endif + +/* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. + If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + the lazy FPU save, then restore the CONTROL.FPCA state. */ + +#ifndef TX_MISRA_ENABLE + +void _tx_vfp_access(void); + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _get_control(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _set_control(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = *((ULONG *) 0xE000EF34); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _get_control(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + _tx_vfp_access(); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = _get_control(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _set_control(_tx_vfp_state); \ + } \ + } \ + } \ + } +#else + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = _tx_misra_fpccr_get(); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + _tx_misra_vfp_touch(); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + } \ + } \ + } +#endif + +#else + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + +#endif + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define the get system state macro. */ + +#ifndef TX_THREAD_GET_SYSTEM_STATE +#ifndef TX_MISRA_ENABLE +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _get_ipsr()) +#else +ULONG _tx_misra_ipsr_get(VOID); +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get()) +#endif +#endif + + +/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value + indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h + for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always + zero after initialization for Cortex-M ports. */ + +#ifndef TX_THREAD_SYSTEM_RETURN_CHECK +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#endif + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +/* Initialize secure stacks for threads calling secure functions. */ +extern void _tx_thread_secure_stack_initialize(void); +#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION _tx_thread_secure_stack_initialize(); +#endif + +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to + prevent early scheduling on Cortex-M parts. */ + +#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT)__clz(__rbit((m))); + +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifdef TX_DISABLE_INLINE + +UINT _tx_thread_interrupt_disable(VOID); +VOID _tx_thread_interrupt_restore(UINT previous_posture); + +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); + +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA unsigned int was_masked; +#define TX_DISABLE was_masked = __disable_irq(); +#define TX_RESTORE if (was_masked == 0) __enable_irq(); + +#define _tx_thread_system_return _tx_thread_system_return_inline + + +static void _tx_thread_system_return_inline(void) +{ +unsigned int was_masked; + + + /* Set PendSV to invoke ThreadX scheduler. */ + *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + if (_get_ipsr() == 0) + { + was_masked = __disable_irq(); + __enable_irq(); + if (was_masked != 0) + __disable_irq(); + } +} +#endif + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33/AC6 Version 6.0.1 *"; +#else +#ifdef TX_MISRA_ENABLE +extern CHAR _tx_version_id[100]; +#else +extern CHAR _tx_version_id[]; +#endif +#endif + + +#endif + + + diff --git a/ports/cortex_m33/ac6/inc/tx_secure_interface.h b/ports/cortex_m33/ac6/inc/tx_secure_interface.h new file mode 100644 index 00000000..e2133c88 --- /dev/null +++ b/ports/cortex_m33/ac6/inc/tx_secure_interface.h @@ -0,0 +1,60 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* tx_secure_interface.h PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the ThreadX secure thread stack components, */ +/* including data types and external references. */ +/* It is assumed that tx_api.h and tx_port.h have already been */ +/* included. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_SECURE_INTERFACE_H +#define TX_SECURE_INTERFACE_H + +/* Define internal secure thread stack function prototypes. */ + +extern void _tx_thread_secure_stack_initialize(void); +extern UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size); +extern UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr); +extern void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr); +extern void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr); + +#endif diff --git a/ports/cortex_m33/ac6/readme_threadx.txt b/ports/cortex_m33/ac6/readme_threadx.txt new file mode 100644 index 00000000..767c22c6 --- /dev/null +++ b/ports/cortex_m33/ac6/readme_threadx.txt @@ -0,0 +1,214 @@ + Microsoft's Azure RTOS ThreadX for Cortex-M33 + + Using the AC6 Tools in Keil uVision + +1. Import the ThreadX Projects + +In order to build the ThreadX library and the ThreadX demonstration, first open +the AzureRTOS.uvmpw workspace (located in the "example_build" directory) +into Keil. + + +2. Building the ThreadX run-time Library + +Building the ThreadX library is easy; simply set the ThreadX_Library project +as active, then then build the library. You should now observe the compilation +and assembly of the ThreadX library. This project build produces the ThreadX +library file ThreadX_Library.lib. + + +3. Demonstration System + +The ThreadX demonstration is designed to execute under the Keil debugger on the +FVP_MPS2_Cortex-M33_MDK simulator. + +Building the demonstration is easy; simply select the "Batch Build" button. +You should now observe the compilation and assembly of the ThreadX demonstration of +both the demo_secure_zone and demo_threadx_non-secure_zone projects. +Then click the Start/Stop Debug Session button to start the simulator and begin debugging. +You are now ready to execute the ThreadX demonstration. + + +4. System Initialization + +The entry point in ThreadX for the Cortex-M33 using AC6 tools uses the standard AC6 +Cortex-M33 reset sequence. From the reset vector the C runtime will be initialized. + +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. + +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input +parameter to your application definition function, tx_application_define. + + +5. Register Usage and Stack Frames + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have the same stack frame in the Cortex-M33 version of +ThreadX. The top of the suspended thread's stack is pointed to by +tx_thread_stack_ptr in the associated thread control block TX_THREAD. + +Non-FPU Stack Frame: + + Stack Offset Stack Contents + + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 r4 + 0x08 r5 + 0x0C r6 + 0x10 r7 + 0x14 r8 + 0x18 r9 + 0x1C r10 + 0x20 r11 + 0x24 r0 (Hardware stack starts here!!) + 0x28 r1 + 0x2C r2 + 0x30 r3 + 0x34 r12 + 0x38 lr + 0x3C pc + 0x40 xPSR + +FPU Stack Frame (only interrupted thread with FPU enabled): + + Stack Offset Stack Contents + + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 s0 + 0x08 s1 + 0x0C s2 + 0x10 s3 + 0x14 s4 + 0x18 s5 + 0x1C s6 + 0x20 s7 + 0x24 s8 + 0x28 s9 + 0x2C s10 + 0x30 s11 + 0x34 s12 + 0x38 s13 + 0x3C s14 + 0x40 s15 + 0x44 s16 + 0x48 s17 + 0x4C s18 + 0x50 s19 + 0x54 s20 + 0x58 s21 + 0x5C s22 + 0x60 s23 + 0x64 s24 + 0x68 s25 + 0x6C s26 + 0x70 s27 + 0x74 s28 + 0x78 s29 + 0x7C s30 + 0x80 s31 + 0x84 fpscr + 0x88 r4 + 0x8C r5 + 0x90 r6 + 0x94 r7 + 0x98 r8 + 0x9C r9 + 0xA0 r10 + 0xA4 r11 + 0xA8 r0 (Hardware stack starts here!!) + 0xAC r1 + 0xB0 r2 + 0xB4 r3 + 0xB8 r12 + 0xBC lr + 0xC0 pc + 0xC4 xPSR + + +6. Improving Performance + +To make ThreadX and the application(s) run faster, you can enable +all compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-M33 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +7.1 Vector Area + +The Cortex-M33 vectors start at the label __Vectors or similar. The application may modify +the vector area according to its needs. There is code in tx_initialize_low_level() that will +configure the vector base register. + + +7.2 Managed Interrupts + +ISRs can be written completely in C (or assembly language) without any calls to +_tx_thread_context_save or _tx_thread_context_restore. These ISRs are allowed access to the +ThreadX API that is available to ISRs. + +ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table): + +void your_C_isr(void) +{ + + /* ISR processing goes here, including any needed function calls. */ +} + +ISRs written in assembly language will take the form: + + + .global your_assembly_isr + .thumb_func +your_assembly_isr: +; VOID your_assembly_isr(VOID) +; { + PUSH {r0, lr} +; +; /* Do interrupt handler work here */ +; /* BL */ + + POP {r0, lr} + BX lr +; } + +Note: the Cortex-M33 requires exception handlers to be thumb labels, this implies bit 0 set. +To accomplish this, the declaration of the label has to be preceded by the assembler directive +.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to +be inserted in the correct location in the interrupt vector table. This table is typically +located in either your runtime startup file or in the tx_initialize_low_level.s file. + + +8. FPU Support + +ThreadX for Cortex-M33 supports automatic ("lazy") VFP support, which means that applications threads +can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread +context. + + +9. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06-30-2020 Initial ThreadX 6.0.1 version for Cortex-M33 using AC6 tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_m33/ac6/src/tx_thread_context_restore.S b/ports/cortex_m33/ac6/src/tx_thread_context_restore.S new file mode 100644 index 00000000..c35e441e --- /dev/null +++ b/ports/cortex_m33/ac6/src/tx_thread_context_restore.S @@ -0,0 +1,85 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore Cortex-M33/AC6 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores the interrupt context if it is processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_context_restore(VOID) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_context_restore + .thumb_func +.type _tx_thread_context_restore, function +_tx_thread_context_restore: + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + /* Call the ISR exit function to indicate an ISR is complete. */ + PUSH {r0,lr} // Save ISR lr (and r0 for 8-byte stack alignment) + BL _tx_execution_isr_exit + POP {r0,lr} +#endif + + /* Just return! */ + BX lr +// } + .end diff --git a/ports/cortex_m33/ac6/src/tx_thread_context_save.S b/ports/cortex_m33/ac6/src/tx_thread_context_save.S new file mode 100644 index 00000000..3519e2ed --- /dev/null +++ b/ports/cortex_m33/ac6/src/tx_thread_context_save.S @@ -0,0 +1,84 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save Cortex-M33/AC6 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_context_save(VOID) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_context_save + .thumb_func +.type _tx_thread_context_save, function +_tx_thread_context_save: + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + /* Call the ISR enter function to indicate an ISR is executing. */ + PUSH {r0,lr} // Save ISR lr (and r0 for 8-byte stack alignment) + BL _tx_execution_isr_enter // Call the ISR enter function + POP {r0,lr} // Recover ISR lr (and r0) +#endif + + /* Return to interrupt processing. */ + BX lr +// } + .end diff --git a/ports/cortex_m33/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_m33/ac6/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..716c06a4 --- /dev/null +++ b/ports/cortex_m33/ac6/src/tx_thread_interrupt_control.S @@ -0,0 +1,78 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control Cortex-M33/AC6 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_interrupt_control(UINT new_posture) +// { + .section .text + .balign 4 + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_interrupt_control + .thumb_func +.type _tx_thread_interrupt_control, function +_tx_thread_interrupt_control: + + /* Pickup current interrupt lockout posture. */ + MRS r1, PRIMASK + MSR PRIMASK, r0 + MOV r0, r1 + BX lr +// } + .end diff --git a/ports/cortex_m33/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_m33/ac6/src/tx_thread_interrupt_disable.S new file mode 100644 index 00000000..f8f4eab2 --- /dev/null +++ b/ports/cortex_m33/ac6/src/tx_thread_interrupt_disable.S @@ -0,0 +1,77 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_disable Cortex-M33/AC6 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for disabling interrupts and returning */ +/* the previous interrupt lockout posture. */ +/* */ +/* INPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_interrupt_disable(UINT new_posture) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_interrupt_disable + .thumb_func +.type _tx_thread_interrupt_disable, function +_tx_thread_interrupt_disable: + /* Return current interrupt lockout posture. */ + MRS r0, PRIMASK + CPSID i + BX lr +// } + .end diff --git a/ports/cortex_m33/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_m33/ac6/src/tx_thread_interrupt_restore.S new file mode 100644 index 00000000..90f886f7 --- /dev/null +++ b/ports/cortex_m33/ac6/src/tx_thread_interrupt_restore.S @@ -0,0 +1,76 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_restore Cortex-M33/AC6 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for restoring the previous */ +/* interrupt lockout posture. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* previous_posture Previous interrupt posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_interrupt_restore(UINT new_posture) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_interrupt_restore + .thumb_func +.type _tx_thread_interrupt_restore, function +_tx_thread_interrupt_restore: + /* Restore previous interrupt lockout posture. */ + MSR PRIMASK, r0 + BX lr +// } + .end diff --git a/ports/cortex_m33/ac6/src/tx_thread_schedule.S b/ports/cortex_m33/ac6/src/tx_thread_schedule.S new file mode 100644 index 00000000..8e9f3a0f --- /dev/null +++ b/ports/cortex_m33/ac6/src/tx_thread_schedule.S @@ -0,0 +1,325 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule Cortex-M33/AC6 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_schedule(VOID) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_schedule + .thumb_func +.type _tx_thread_schedule, function +_tx_thread_schedule: + /* This function should only ever be called on Cortex-M + from the first schedule request. Subsequent scheduling occurs + from the PendSV handling routine below. */ + + /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ + MOV r0, #0 // Build value for TX_FALSE + LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag + STR r0, [r2, #0] // Clear preempt disable flag + + /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */ + +#ifdef __ARM_PCS_VFP + MRS r0, CONTROL // Pickup current CONTROL register + BIC r0, r0, #4 // Clear the FPCA bit + MSR CONTROL, r0 // Setup new CONTROL register +#endif + + /* Enable interrupts */ + CPSIE i + + /* Enter the scheduler for the first time. */ + + MOV r0, #0x10000000 // Load PENDSVSET bit + MOV r1, #0xE000E000 // Load NVIC base + STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + DSB // Complete all memory accesses + ISB // Flush pipeline + + /* Wait here for the PendSV to take place. */ + +__tx_wait_here: + B __tx_wait_here // Wait for the PendSV to happen +// } + + /* Generic context switching PendSV handler. */ + + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global PendSV_Handler + .thumb_func +.type PendSV_Handler, function + /* Get current thread value and new thread pointer. */ +PendSV_Handler: +__tx_ts_handler: + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread exit function to indicate the thread is no longer executing. */ + + CPSID i // Disable interrupts + PUSH {r0, lr} // Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit // Call the thread exit function + POP {r0, lr} // Recover LR + CPSIE i // Enable interrupts +#endif + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address + MOV r3, #0 // Build NULL value + LDR r1, [r0] // Pickup current thread pointer + + /* Determine if there is a current thread to finish preserving. */ + + CBZ r1, __tx_ts_new // If NULL, skip preservation + + /* Recover PSP and preserve current thread context. */ + + STR r3, [r0] // Set _tx_thread_current_ptr to NULL + MRS r12, PSP // Pickup PSP pointer (thread's stack pointer) + STMDB r12!, {r4-r11} // Save its remaining registers +#ifdef __ARM_PCS_VFP + TST LR, #0x10 // Determine if the VFP extended frame is present + BNE _skip_vfp_save + VSTMDB r12!,{s16-s31} // Yes, save additional VFP registers +_skip_vfp_save: +#endif + LDR r4, =_tx_timer_time_slice // Build address of time-slice variable + STMDB r12!, {LR} // Save LR on the stack + STR r12, [r1, #8] // Save the thread stack pointer + +#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) + // Save secure context + LDR r5, [r1,#0x90] // Load secure stack index + CBZ r5, _skip_secure_save // Skip save if there is no secure context + PUSH {r0,r1,r2,r3} // Save scratch registers + MOV r0, r1 // Move thread ptr to r0 + BL _tx_thread_secure_stack_context_save // Save secure stack + POP {r0,r1,r2,r3} // Restore secure registers +_skip_secure_save: +#endif + + /* Determine if time-slice is active. If it isn't, skip time handling processing. */ + + LDR r5, [r4] // Pickup current time-slice + CBZ r5, __tx_ts_new // If not active, skip processing + + /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ + + STR r5, [r1, #24] // Save current time-slice + + /* Clear the global time-slice. */ + + STR r3, [r4] // Clear time-slice + + /* Executing thread is now completely preserved!!! */ + +__tx_ts_new: + + /* Now we are looking for a new thread to execute! */ + + CPSID i // Disable interrupts + LDR r1, [r2] // Is there another thread ready to execute? + CBZ r1, __tx_ts_wait // No, skip to the wait processing + + /* Yes, another thread is ready for else, make the current thread the new thread. */ + + STR r1, [r0] // Setup the current thread pointer to the new thread + CPSIE i // Enable interrupts + + /* Increment the thread run count. */ + +__tx_ts_restore: + LDR r7, [r1, #4] // Pickup the current thread run count + LDR r4, =_tx_timer_time_slice // Build address of time-slice variable + LDR r5, [r1, #24] // Pickup thread's current time-slice + ADD r7, r7, #1 // Increment the thread run count + STR r7, [r1, #4] // Store the new run count + + /* Setup global time-slice with thread's current time-slice. */ + + STR r5, [r4] // Setup global time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + /* Call the thread entry function to indicate the thread is executing. */ + PUSH {r0, r1} // Save r0/r1 + BL _tx_execution_thread_enter // Call the thread execution enter function + POP {r0, r1} // Recover r0/r1 +#endif + +#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) + // Restore secure context + LDR r0, [r1,#0x90] // Load secure stack index + CBZ r0, _skip_secure_restore // Skip restore if there is no secure context + PUSH {r0,r1} // Save r1 (and dummy r0) + MOV r0, r1 // Move thread ptr to r0 + BL _tx_thread_secure_stack_context_restore // Restore secure stack + POP {r0,r1} // Restore r1 (and dummy r0) +_skip_secure_restore: +#endif + + /* Restore the thread context and PSP. */ + LDR r12, [r1, #12] // Get stack start + MSR PSPLIM, r12 // Set stack limit + LDR r12, [r1, #8] // Pickup thread's stack pointer + LDMIA r12!, {LR} // Pickup LR +#ifdef __ARM_PCS_VFP + TST LR, #0x10 // Determine if the VFP extended frame is present + BNE _skip_vfp_restore // If not, skip VFP restore + VLDMIA r12!, {s16-s31} // Yes, restore additional VFP registers +_skip_vfp_restore: +#endif + LDMIA r12!, {r4-r11} // Recover thread's registers + MSR PSP, r12 // Setup the thread's stack pointer + + /* Return to thread. */ + BX lr // Return to thread! + + /* The following is the idle wait processing... in this case, no threads are ready for execution and the + system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts + are disabled to allow use of WFI for waiting for a thread to arrive. */ + +__tx_ts_wait: + CPSID i // Disable interrupts + LDR r1, [r2] // Pickup the next thread to execute pointer + STR r1, [r0] // Store it in the current pointer + CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! +#ifdef TX_ENABLE_WFI + DSB // Ensure no outstanding memory transactions + WFI // Wait for interrupt + ISB // Ensure pipeline is flushed +#endif + CPSIE i // Enable interrupts + B __tx_ts_wait // Loop to continue waiting + + /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are + already in the handler! */ +__tx_ts_ready: + MOV r7, #0x08000000 // Build clear PendSV value + MOV r8, #0xE000E000 // Build base NVIC address + STR r7, [r8, #0xD04] // Clear any PendSV + + /* Re-enable interrupts and restore new thread. */ + CPSIE i // Enable interrupts + B __tx_ts_restore // Restore the thread + + +#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) + // SVC_Handler is not needed when ThreadX is running in single mode. + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global SVC_Handler + .thumb_func +.type SVC_Handler, function +SVC_Handler: + TST lr, #0x04 // Determine return stack from EXC_RETURN bit 2 + ITE EQ + MRSEQ r0, MSP // Get MSP if return stack is MSP + MRSNE r0, PSP // Get PSP if return stack is PSP + + LDR r1, [r0,#24] // Load saved PC from stack + LDRB r1, [r1,#-2] // Load SVC number + + CMP r1, #1 // Is it a secure stack allocate request? + BEQ _tx_svc_secure_alloc // Yes, go there + + CMP r1, #2 // Is it a secure stack free request? + BEQ _tx_svc_secure_free // Yes, go there + + // Unknown SVC argument - just return + BX lr + +_tx_svc_secure_alloc: + PUSH {r0,lr} // Save SP and EXC_RETURN + LDM r0, {r0-r3} // Load function parameters from stack + BL _tx_thread_secure_mode_stack_allocate + POP {r12,lr} // Restore SP and EXC_RETURN + STR r0,[r12] // Store function return value + BX lr +_tx_svc_secure_free: + PUSH {r0,lr} // Save SP and EXC_RETURN + LDM r0, {r0-r3} // Load function parameters from stack + BL _tx_thread_secure_mode_stack_free + POP {r12,lr} // Restore SP and EXC_RETURN + STR r0,[r12] // Store function return value + BX lr +#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE + + + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_vfp_access + .thumb_func +.type _tx_vfp_access, function +_tx_vfp_access: + VMOV.F32 s0, s0 // Simply access the VFP + BX lr // Return to caller +.end diff --git a/ports/cortex_m33/ac6/src/tx_thread_secure_stack.c b/ports/cortex_m33/ac6/src/tx_thread_secure_stack.c new file mode 100644 index 00000000..b563ba7c --- /dev/null +++ b/ports/cortex_m33/ac6/src/tx_thread_secure_stack.c @@ -0,0 +1,465 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +#include "tx_api.h" + +/* If TX_SINGLE_MODE_SECURE or TX_SINGLE_MODE_NON_SECURE is defined, + no secure stack functionality is needed. */ +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + +#define TX_SOURCE_CODE + +#include "ARMCM33_DSP_FP_TZ.h" /* For intrinsic functions. */ +#include "tx_secure_interface.h" /* Interface for NS code. */ + +/* Minimum size of secure stack. */ +#ifndef TX_THREAD_SECURE_STACK_MINIMUM +#define TX_THREAD_SECURE_STACK_MINIMUM 256 +#endif +/* Maximum size of secure stack. */ +#ifndef TX_THREAD_SECURE_STACK_MAXIMUM +#define TX_THREAD_SECURE_STACK_MAXIMUM 1024 +#endif + +/* Secure stack info struct to hold stack start, stack limit, + current stack pointer, and pointer to owning thread. + This will be allocated for each thread with a secure stack. */ +typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT +{ + VOID *tx_thread_secure_stack_ptr; /* Thread's secure stack current pointer */ + VOID *tx_thread_secure_stack_start; /* Thread's secure stack start address */ + VOID *tx_thread_secure_stack_limit; /* Thread's secure stack limit */ + TX_THREAD *tx_thread_ptr; /* Keep track of thread for error handling */ +} TX_THREAD_SECURE_STACK_INFO; + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_initialize Cortex-M33/AC6 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes secure mode to use PSP stack. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __get_CONTROL Intrinsic to get CONTROL */ +/* __set_CONTROL Intrinsic to set CONTROL */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +void _tx_thread_secure_stack_initialize(void) +{ + + /* Set secure mode to use PSP. */ + __set_CONTROL(__get_CONTROL() | 2); + + /* Set process stack pointer and stack limit to 0 to throw exception when a thread + without a secure stack calls a secure function that tries to use secure stack. */ + __set_PSPLIM(0); + __set_PSP(0); + + return; +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_mode_stack_allocate PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function allocates a thread's secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* stack_size Size of stack to allocates */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_SIZE_ERROR Invalid stack size */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* calloc Compiler's calloc function */ +/* malloc Compiler's malloc function */ +/* free Compiler's free() function */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* __TZ_get_PSPLIM_NS Intrinsic to get NS PSP */ +/* */ +/* CALLED BY */ +/* */ +/* SVC Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +{ +UINT status; +TX_THREAD_SECURE_STACK_INFO *info_ptr; +UCHAR *stack_mem; + + status = TX_SUCCESS; + + /* Make sure function is called from interrupt (threads should not call). */ + if (__get_IPSR() == 0) + { + status = TX_CALLER_ERROR; + } + else if (stack_size < TX_THREAD_SECURE_STACK_MINIMUM || stack_size > TX_THREAD_SECURE_STACK_MAXIMUM) + { + status = TX_SIZE_ERROR; + } + + /* Check if thread already has secure stack allocated. */ + else if (thread_ptr -> tx_thread_secure_stack_context != 0) + { + status = TX_THREAD_ERROR; + } + + else + { + + /* Allocate space for secure stack info. */ + info_ptr = calloc(1, sizeof(TX_THREAD_SECURE_STACK_INFO)); + + if(info_ptr != TX_NULL) + { + /* If stack info allocated, allocate a stack. */ + stack_mem = malloc(stack_size); + + if(stack_mem != TX_NULL) + { + /* Secure stack has been allocated, save in the stack info struct. */ + info_ptr -> tx_thread_secure_stack_limit = stack_mem; + info_ptr -> tx_thread_secure_stack_start = stack_mem + stack_size; + info_ptr -> tx_thread_secure_stack_ptr = info_ptr -> tx_thread_secure_stack_start; + info_ptr -> tx_thread_ptr = thread_ptr; + + /* Save info pointer in thread. */ + thread_ptr -> tx_thread_secure_stack_context = info_ptr; + + /* Check if this thread is running by looking at its stack start and PSPLIM_NS */ + if(((ULONG) thread_ptr -> tx_thread_stack_start & 0xFFFFFFF8) == __TZ_get_PSPLIM_NS()) + { + /* If this thread is running, set Secure PSP and PSPLIM. */ + __set_PSPLIM((ULONG)(info_ptr -> tx_thread_secure_stack_limit)); + __set_PSP((ULONG)(info_ptr -> tx_thread_secure_stack_ptr)); + } + } + + else + { + /* Stack not allocated, free the info struct. */ + free(info_ptr); + status = TX_NO_MEMORY; + } + } + + else + { + status = TX_NO_MEMORY; + } + } + + return(status); +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_mode_stack_free PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function frees a thread's secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* free Compiler's free() function */ +/* */ +/* CALLED BY */ +/* */ +/* SVC Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr) +{ +UINT status; +TX_THREAD_SECURE_STACK_INFO *info_ptr; + + status = TX_SUCCESS; + + /* Pickup stack info from thread. */ + info_ptr = thread_ptr -> tx_thread_secure_stack_context; + + /* Make sure function is called from interrupt (threads should not call). */ + if (__get_IPSR() == 0) + { + status = TX_CALLER_ERROR; + } + + /* Check that this secure context is for this thread. */ + else if (info_ptr -> tx_thread_ptr != thread_ptr) + { + status = TX_THREAD_ERROR; + } + + else + { + + /* Free secure stack. */ + free(info_ptr -> tx_thread_secure_stack_limit); + + /* Free info struct. */ + free(info_ptr); + + /* Clear secure context from thread. */ + thread_ptr -> tx_thread_secure_stack_context = 0; + } + + return(status); +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_context_save PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves context of the secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* __get_PSP Intrinsic to get PSP */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* */ +/* CALLED BY */ +/* */ +/* PendSV Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr) +{ +TX_THREAD_SECURE_STACK_INFO *info_ptr; +ULONG sp; + + /* This function should be called from scheduler only. */ + if (__get_IPSR() == 0) + { + return; + } + + /* Pickup the secure context pointer. */ + info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); + + /* Check that this secure context is for this thread. */ + if (info_ptr -> tx_thread_ptr != thread_ptr) + { + return; + } + + /* Check that stack pointer is in range */ + sp = __get_PSP(); + if ((sp < (ULONG)info_ptr -> tx_thread_secure_stack_limit) || + (sp > (ULONG)info_ptr -> tx_thread_secure_stack_start)) + { + return; + } + + /* Save stack pointer. */ + *(ULONG *) info_ptr -> tx_thread_secure_stack_ptr = sp; + + /* Set process stack pointer and stack limit to 0 to throw exception when a thread + without a secure stack calls a secure function that tries to use secure stack. */ + __set_PSPLIM(0); + __set_PSP(0); + + return; +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_context_restore PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores context of the secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* */ +/* CALLED BY */ +/* */ +/* PendSV Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr) +{ +TX_THREAD_SECURE_STACK_INFO *info_ptr; + + /* This function should be called from scheduler only. */ + if (__get_IPSR() == 0) + { + return; + } + + /* Pickup the secure context pointer. */ + info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); + + /* Check that this secure context is for this thread. */ + if (info_ptr -> tx_thread_ptr != thread_ptr) + { + return; + } + + /* Set stack pointer and limit. */ + __set_PSPLIM((ULONG)info_ptr -> tx_thread_secure_stack_limit); + __set_PSP ((ULONG)info_ptr -> tx_thread_secure_stack_ptr); + + return; +} + +#endif diff --git a/ports/cortex_m33/ac6/src/tx_thread_secure_stack_allocate.S b/ports/cortex_m33/ac6/src/tx_thread_secure_stack_allocate.S new file mode 100644 index 00000000..c6a1fa53 --- /dev/null +++ b/ports/cortex_m33/ac6/src/tx_thread_secure_stack_allocate.S @@ -0,0 +1,85 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_allocate Cortex-M33/AC6 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function enters the SVC handler to allocate a secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* stack_size Size of secure stack to */ +/* allocate */ +/* */ +/* OUTPUT */ +/* */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* SVC 1 */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_secure_stack_allocate + .thumb_func +.type _tx_thread_secure_stack_allocate, function +_tx_thread_secure_stack_allocate: +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + MRS r3, PRIMASK // Save interrupt mask + CPSIE i // Enable interrupts for SVC call + SVC 1 + CMP r3, #0 // If interrupts enabled, just return + BEQ _alloc_return_interrupt_enabled + CPSID i // Otherwise, disable interrupts +#else + MOV r0, #0xFF // Feature not enabled +#endif +_alloc_return_interrupt_enabled: + BX lr + .end diff --git a/ports/cortex_m33/ac6/src/tx_thread_secure_stack_free.S b/ports/cortex_m33/ac6/src/tx_thread_secure_stack_free.S new file mode 100644 index 00000000..24d830bd --- /dev/null +++ b/ports/cortex_m33/ac6/src/tx_thread_secure_stack_free.S @@ -0,0 +1,83 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_free Cortex-M33/AC6 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function enters the SVC handler to free a secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* SVC 2 */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_secure_stack_free + .thumb_func +.type _tx_thread_secure_stack_free, function +_tx_thread_secure_stack_free: +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + MRS r3, PRIMASK // Save interrupt mask + CPSIE i // Enable interrupts for SVC call + SVC 2 + CMP r3, #0 // If interrupts enabled, just return + BEQ _free_return_interrupt_enabled + CPSID i // Otherwise, disable interrupts +#else + MOV r0, #0xFF // Feature not enabled +#endif +_free_return_interrupt_enabled: + BX lr + .end diff --git a/ports/cortex_m33/ac6/src/tx_thread_stack_build.S b/ports/cortex_m33/ac6/src/tx_thread_stack_build.S new file mode 100644 index 00000000..c232f89e --- /dev/null +++ b/ports/cortex_m33/ac6/src/tx_thread_stack_build.S @@ -0,0 +1,140 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build Cortex-M33/AC6 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_stack_build + .thumb_func +.type _tx_thread_stack_build, function +_tx_thread_stack_build: + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-M33 should look like the following after it is built: + + Stack Top: + LR Interrupted LR (LR at time of PENDSV) + r4 Initial value for r4 + r5 Initial value for r5 + r6 Initial value for r6 + r7 Initial value for r7 + r8 Initial value for r8 + r9 Initial value for r9 + r10 Initial value for r10 + r11 Initial value for r11 + r0 Initial value for r0 (Hardware stack starts here!!) + r1 Initial value for r1 + r2 Initial value for r2 + r3 Initial value for r3 + r12 Initial value for r12 + lr Initial value for lr + pc Initial value for pc + xPSR Initial value for xPSR + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, #16] // Pickup end of stack area + BIC r2, r2, #0x7 // Align frame for 8-byte alignment + SUB r2, r2, #68 // Subtract frame size +#ifdef TX_SINGLE_MODE_SECURE + LDR r3, =0xFFFFFFFD // Build initial LR value for secure mode +#else + LDR r3, =0xFFFFFFBC // Build initial LR value to return to non-secure PSP +#endif + STR r3, [r2, #0] // Save on the stack + + /* Actually build the stack frame. */ + + MOV r3, #0 // Build initial register value + STR r3, [r2, #4] // Store initial r4 + STR r3, [r2, #8] // Store initial r5 + STR r3, [r2, #12] // Store initial r6 + STR r3, [r2, #16] // Store initial r7 + STR r3, [r2, #20] // Store initial r8 + STR r3, [r2, #24] // Store initial r9 + STR r3, [r2, #28] // Store initial r10 + STR r3, [r2, #32] // Store initial r11 + + /* Hardware stack follows. */ + + STR r3, [r2, #36] // Store initial r0 + STR r3, [r2, #40] // Store initial r1 + STR r3, [r2, #44] // Store initial r2 + STR r3, [r2, #48] // Store initial r3 + STR r3, [r2, #52] // Store initial r12 + MOV r3, #0xFFFFFFFF // Poison EXC_RETURN value + STR r3, [r2, #56] // Store initial lr + STR r1, [r2, #60] // Store initial pc + MOV r3, #0x01000000 // Only T-bit need be set + STR r3, [r2, #64] // Store initial xPSR + + /* Setup stack pointer. */ + // thread_ptr -> tx_thread_stack_ptr = r2; + + STR r2, [r0, #8] // Save stack pointer in thread's + // control block + BX lr // Return to caller +// } + .end diff --git a/ports/cortex_m33/ac6/src/tx_thread_stack_error_handler.c b/ports/cortex_m33/ac6/src/tx_thread_stack_error_handler.c new file mode 100644 index 00000000..133497b4 --- /dev/null +++ b/ports/cortex_m33/ac6/src/tx_thread_stack_error_handler.c @@ -0,0 +1,97 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + +/* Define the global function pointer for stack error handling. If a stack error is + detected and the application has registered a stack error handler, it will be + called via this function pointer. */ + +VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_error_handler Cortex-M33/AC6 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes stack errors detected during run-time. */ +/* */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_terminate */ +/* _tx_thread_application_stack_error_handler */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX internal code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) +{ + + #ifndef TX_THREAD_NO_TERMINATE_STACK_ERROR + /* Is there a thread? */ + if (thread_ptr) + { + /* Terminate the current thread. */ + _tx_thread_terminate(_tx_thread_current_ptr); + } + #endif + + /* Determine if the application has registered an error handler. */ + if (_tx_thread_application_stack_error_handler != TX_NULL) + { + + /* Yes, an error handler is present, simply call the application error handler. */ + (_tx_thread_application_stack_error_handler)(thread_ptr); + } + +} + diff --git a/ports/cortex_m33/ac6/src/tx_thread_stack_error_notify.c b/ports/cortex_m33/ac6/src/tx_thread_stack_error_notify.c new file mode 100644 index 00000000..c9e70eb6 --- /dev/null +++ b/ports/cortex_m33/ac6/src/tx_thread_stack_error_notify.c @@ -0,0 +1,98 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_trace.h" + +extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_error_notify Cortex-M33/AC6 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application stack error handler. If */ +/* ThreadX detects a stack error, this application handler is called. */ +/* */ +/* */ +/* INPUT */ +/* */ +/* stack_error_handler Pointer to stack error */ +/* handler, TX_NULL to disable */ +/* */ +/* OUTPUT */ +/* */ +/* status Service return status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr)) +{ + +TX_INTERRUPT_SAVE_AREA + + + /* Disable interrupts. */ + TX_DISABLE + + /* Make entry in event log. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_STACK_ERROR_NOTIFY, 0, 0, 0, 0, TX_TRACE_THREAD_EVENTS) + + /* Make entry in event log. */ + TX_EL_THREAD_STACK_ERROR_NOTIFY_INSERT + + /* Setup global thread stack error handler. */ + _tx_thread_application_stack_error_handler = stack_error_handler; + + /* Restore interrupts. */ + TX_RESTORE + + /* Return success to caller. */ + return(TX_SUCCESS); +} + diff --git a/ports/cortex_m33/ac6/src/tx_thread_system_return.S b/ports/cortex_m33/ac6/src/tx_thread_system_return.S new file mode 100644 index 00000000..eb3183c0 --- /dev/null +++ b/ports/cortex_m33/ac6/src/tx_thread_system_return.S @@ -0,0 +1,89 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return Cortex-M33/AC6 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the ThreadX system. Only a */ +/* minimal context is saved since the compiler assumes temp registers */ +/* are going to get slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_system_return(VOID) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_system_return + .thumb_func +.type _tx_thread_system_return, function +_tx_thread_system_return: + /* Return to real scheduler via PendSV. Note that this routine is often + replaced with in-line assembly in tx_port.h to improved performance. */ + + MOV r0, #0x10000000 // Load PENDSVSET bit + LDR r1, =0xE000E000 // Load NVIC base + STR r0, [r1, #0xD04] // Set PENDSVBIT in ICSR + MRS r0, IPSR // Pickup IPSR + CMP r0, #0 // Is it a thread returning? + BNE _isr_context // If ISR, skip interrupt enable + MRS r1, PRIMASK // Thread context returning, pickup PRIMASK + CPSIE i // Enable interrupts + MSR PRIMASK, r1 // Restore original interrupt posture +_isr_context: + BX lr // Return to caller +// } + .end diff --git a/ports/cortex_m33/ac6/src/tx_timer_interrupt.S b/ports/cortex_m33/ac6/src/tx_timer_interrupt.S new file mode 100644 index 00000000..9aedaad9 --- /dev/null +++ b/ports/cortex_m33/ac6/src/tx_timer_interrupt.S @@ -0,0 +1,245 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt Cortex-M33/AC6 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_timer_interrupt(VOID) +{ */ + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_timer_interrupt + .thumb_func +.type _tx_timer_interrupt, function +_tx_timer_interrupt: + + /* Upon entry to this routine, it is assumed that context save has already + been called, and therefore the compiler scratch registers are available + for use. */ + + /* Increment the system clock. */ + // _tx_timer_system_clock++; + + LDR r1, =_tx_timer_system_clock // Pickup address of system clock + LDR r0, [r1, #0] // Pickup system clock + ADD r0, r0, #1 // Increment system clock + STR r0, [r1, #0] // Store new system clock + + /* Test for time-slice expiration. */ + // if (_tx_timer_time_slice) + // { + + LDR r3, =_tx_timer_time_slice // Pickup address of time-slice + LDR r2, [r3, #0] // Pickup time-slice + CBZ r2, __tx_timer_no_time_slice // Is it non-active? + // Yes, skip time-slice processing + + /* Decrement the time_slice. */ + // _tx_timer_time_slice--; + + SUB r2, r2, #1 // Decrement the time-slice + STR r2, [r3, #0] // Store new time-slice value + + /* Check for expiration. */ + // if (__tx_timer_time_slice == 0) + + CBNZ r2, __tx_timer_no_time_slice // Has it expired? + + /* Set the time-slice expired flag. */ + // _tx_timer_expired_time_slice = TX_TRUE; + + LDR r3, =_tx_timer_expired_time_slice // Pickup address of expired flag + MOV r0, #1 // Build expired value + STR r0, [r3, #0] // Set time-slice expiration flag + + // } + +__tx_timer_no_time_slice: + + /* Test for timer expiration. */ + // if (*_tx_timer_current_ptr) + // { + + LDR r1, =_tx_timer_current_ptr // Pickup current timer pointer address + LDR r0, [r1, #0] // Pickup current timer + LDR r2, [r0, #0] // Pickup timer list entry + CBZ r2, __tx_timer_no_timer // Is there anything in the list? + // No, just increment the timer + + /* Set expiration flag. */ + // _tx_timer_expired = TX_TRUE; + + LDR r3, =_tx_timer_expired // Pickup expiration flag address + MOV r2, #1 // Build expired value + STR r2, [r3, #0] // Set expired flag + B __tx_timer_done // Finished timer processing + + // } + // else + // { +__tx_timer_no_timer: + + /* No timer expired, increment the timer pointer. */ + // _tx_timer_current_ptr++; + + ADD r0, r0, #4 // Move to next timer + + /* Check for wrap-around. */ + // if (_tx_timer_current_ptr == _tx_timer_list_end) + + LDR r3, =_tx_timer_list_end // Pickup addr of timer list end + LDR r2, [r3, #0] // Pickup list end + CMP r0, r2 // Are we at list end? + BNE __tx_timer_skip_wrap // No, skip wrap-around logic + + /* Wrap to beginning of list. */ + // _tx_timer_current_ptr = _tx_timer_list_start; + + LDR r3, =_tx_timer_list_start // Pickup addr of timer list start + LDR r0, [r3, #0] // Set current pointer to list start + +__tx_timer_skip_wrap: + + STR r0, [r1, #0] // Store new current timer pointer + // } + +__tx_timer_done: + + + /* See if anything has expired. */ + // if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) + // { + + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of expired flag + LDR r2, [r3, #0] // Pickup time-slice expired flag + CBNZ r2, __tx_something_expired // Did a time-slice expire? + // If non-zero, time-slice expired + LDR r1, =_tx_timer_expired // Pickup addr of other expired flag + LDR r0, [r1, #0] // Pickup timer expired flag + CBZ r0, __tx_timer_nothing_expired // Did a timer expire? + // No, nothing expired + +__tx_something_expired: + + STMDB sp!, {r0, lr} // Save the lr register on the stack + // and save r0 just to keep 8-byte alignment + + /* Did a timer expire? */ + // if (_tx_timer_expired) + // { + + LDR r1, =_tx_timer_expired // Pickup addr of expired flag + LDR r0, [r1, #0] // Pickup timer expired flag + CBZ r0, __tx_timer_dont_activate // Check for timer expiration + // If not set, skip timer activation + + /* Process timer expiration. */ + // _tx_timer_expiration_process(); + + BL _tx_timer_expiration_process // Call the timer expiration handling routine + + // } +__tx_timer_dont_activate: + + /* Did time slice expire? */ + // if (_tx_timer_expired_time_slice) + // { + + LDR r3, =_tx_timer_expired_time_slice // Pickup addr of time-slice expired + LDR r2, [r3, #0] // Pickup the actual flag + CBZ r2, __tx_timer_not_ts_expiration // See if the flag is set + // No, skip time-slice processing + + /* Time slice interrupted thread. */ + // _tx_thread_time_slice(); + + BL _tx_thread_time_slice // Call time-slice processing + LDR r0, =_tx_thread_preempt_disable // Build address of preempt disable flag + LDR r1, [r0] // Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice // Yes, skip the PendSV logic + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r0] // Pickup the current thread pointer + LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address + LDR r3, [r2] // Pickup the execute thread pointer + LDR r0, =0xE000ED04 // Build address of control register + MOV r2, 0x10000000 // Build value for PendSV bit + CMP r1, r3 // Are they the same? + BEQ __tx_timer_skip_time_slice // If the same, there was no time-slice performed + STR r2, [r0] // Not the same, issue the PendSV for preemption +__tx_timer_skip_time_slice: + + // } + +__tx_timer_not_ts_expiration: + + LDMIA sp!, {r0, lr} // Recover lr register (r0 is just there for + + // } + +__tx_timer_nothing_expired: + + BX lr // Return to caller + +// } + .end diff --git a/ports/cortex_m33/ac6/src/txe_thread_secure_stack_allocate.c b/ports/cortex_m33/ac6/src/txe_thread_secure_stack_allocate.c new file mode 100644 index 00000000..ded0507d --- /dev/null +++ b/ports/cortex_m33/ac6/src/txe_thread_secure_stack_allocate.c @@ -0,0 +1,123 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_allocate PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the secure stack allocate */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* stack_size Size of secure stack to */ +/* allocate */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_secure_stack_allocate Actual stack alloc function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +{ +#if defined(TX_SINGLE_MODE_SECURE) || defined(TX_SINGLE_MODE_NON_SECURE) + return(TX_FEATURE_NOT_ENABLED); +#else +UINT status; + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid thread pointer. */ + if (thread_ptr == TX_NULL) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Now check for invalid thread ID. */ + else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Check for interrupt call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + /* Is call from an interrupt and not initialization? */ + if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS) + { + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + + /* Call actual secure stack allocate function. */ + status = _tx_thread_secure_stack_allocate(thread_ptr, stack_size); + } + + /* Return completion status. */ + return(status); +#endif +} + diff --git a/ports/cortex_m33/ac6/src/txe_thread_secure_stack_free.c b/ports/cortex_m33/ac6/src/txe_thread_secure_stack_free.c new file mode 100644 index 00000000..af49c7df --- /dev/null +++ b/ports/cortex_m33/ac6/src/txe_thread_secure_stack_free.c @@ -0,0 +1,121 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_secure_stack_free PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the secure stack free */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_secure_stack_free Actual stack free function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) +{ +#if defined(TX_SINGLE_MODE_SECURE) || defined(TX_SINGLE_MODE_NON_SECURE) + return(TX_FEATURE_NOT_ENABLED); +#else +UINT status; + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid thread pointer. */ + if (thread_ptr == TX_NULL) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Now check for invalid thread ID. */ + else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Check for interrupt call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + /* Is call from an interrupt and not initialization? */ + if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS) + { + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + + /* Call actual secure stack allocate function. */ + status = _tx_thread_secure_stack_free(thread_ptr); + } + + /* Return completion status. */ + return(status); +#endif +} + diff --git a/ports/cortex_m33/iar/inc/tx_port.h b/ports/cortex_m33/iar/inc/tx_port.h new file mode 100644 index 00000000..fceae6ec --- /dev/null +++ b/ports/cortex_m33/iar/inc/tx_port.h @@ -0,0 +1,572 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-M33/IAR */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + +/* Determine if the optional ThreadX user define file should be used. */ +#ifdef TX_INCLUDE_USER_DEFINE_FILE + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + +/* Define compiler library include files. */ + +#include +#include +#include +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef unsigned long long ULONG64; +typedef short SHORT; +typedef unsigned short USHORT; + +/* Function prototypes for this port. */ +struct TX_THREAD_STRUCT; +UINT _txe_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *thread_ptr, ULONG stack_size); +UINT _txe_thread_secure_stack_free(struct TX_THREAD_STRUCT *thread_ptr); +UINT _tx_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *tx_thread, ULONG stack_size); +UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); + +/* This hardware has stack checking that we take advantage of - do NOT define. */ +#ifdef TX_ENABLE_STACK_CHECKING + #error "Do not define TX_ENABLE_STACK_CHECKING" +#endif + +/* If user does not want to terminate thread on stack overflow, + #define the TX_THREAD_NO_TERMINATE_STACK_ERROR symbol. + The thread will be rescheduled and continue to cause the exception. + It is suggested user code handle this by registering a notification with the + tx_thread_stack_error_notify function. */ +/*#define TX_THREAD_NO_TERMINATE_STACK_ERROR */ + +/* Define the system API mappings based on the error checking + selected by the user. Note: this section is only applicable to + application source code, hence the conditional that turns off this + stuff when the include file is processed by the ThreadX source. */ + +#ifndef TX_SOURCE_CODE + + +/* Determine if error checking is desired. If so, map API functions + to the appropriate error checking front-ends. Otherwise, map API + functions to the core functions that actually perform the work. + Note: error checking is enabled by default. */ + +#ifdef TX_DISABLE_ERROR_CHECKING + +/* Services without error checking. */ + +#define tx_thread_secure_stack_allocate _tx_thread_secure_stack_allocate +#define tx_thread_secure_stack_free _tx_thread_secure_stack_free + +#else + +/* Services with error checking. */ + +#define tx_thread_secure_stack_allocate _txe_thread_secure_stack_allocate +#define tx_thread_secure_stack_free _txe_thread_secure_stack_free + +#endif +#endif + + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX Cortex-M33 port. */ + +#define TX_INT_DISABLE 1 /* Disable interrupts */ +#define TX_INT_ENABLE 0 /* Enable interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) +#endif +#else +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif + +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +/* IAR library support */ +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +/* ThreadX in non-secure zone with calls to secure zone. */ +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_secure_stack_context; \ + VOID *tx_thread_iar_tls_pointer; +#else +/* ThreadX in only one zone. */ +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#endif + +#else +/* No IAR library support */ +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +/* ThreadX in non-secure zone with calls to secure zone. */ +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_secure_stack_context; +#else +/* ThreadX in only one zone. */ +#define TX_THREAD_EXTENSION_2 +#endif + +#endif + + +#ifndef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#define TX_THREAD_EXTENSION_3 +#else +#define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ + unsigned long long tx_thread_execution_time_last_start; +#endif + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +void *_tx_iar_create_per_thread_tls_area(void); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); +void __iar_Initlocks(void); +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); \ + if(thread_ptr -> tx_thread_secure_stack_context){_tx_thread_secure_stack_free(thread_ptr);} +#else +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); +#endif +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#else +/* No IAR library support. */ +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) if(thread_ptr -> tx_thread_secure_stack_context){_tx_thread_secure_stack_free(thread_ptr);} +#else +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif +#endif + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +/* Define the size of the secure stack for the timer thread and use the extension to allocate the secure stack. */ +#define TX_TIMER_THREAD_SECURE_STACK_SIZE 256 +#define TX_TIMER_INITIALIZE_EXTENSION(status) _tx_thread_secure_stack_allocate(&_tx_timer_thread, TX_TIMER_THREAD_SECURE_STACK_SIZE); +#endif + +#ifdef __ARMVFP__ + +#ifdef TX_MISRA_ENABLE + +ULONG _tx_misra_control_get(void); +void _tx_misra_control_set(ULONG value); +ULONG _tx_misra_fpccr_get(void); +void _tx_misra_vfp_touch(void); + +#endif + +/* A completed thread falls into _thread_shell_entry and we can simply deactivate the FPU via CONTROL.FPCA + in order to ensure no lazy stacking will occur. */ + +#ifndef TX_MISRA_ENABLE + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_CONTROL(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_CONTROL(_tx_vfp_state); \ + } +#else + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } + +#endif + +/* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. + If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + the lazy FPU save, then restore the CONTROL.FPCA state. */ + +#ifndef TX_MISRA_ENABLE + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_CONTROL(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_CONTROL(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = *((ULONG *) 0xE000EF34); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_CONTROL(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + __asm volatile ("vmov.f32 s0, s0"); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = __get_CONTROL(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_CONTROL(_tx_vfp_state); \ + } \ + } \ + } \ + } +#else + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = _tx_misra_fpccr_get(); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + _tx_misra_vfp_touch(); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + } \ + } \ + } +#endif + +#else + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + +#endif + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define the get system state macro. */ + +#ifndef TX_THREAD_GET_SYSTEM_STATE +#ifndef TX_MISRA_ENABLE +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | __get_IPSR()) +#else +ULONG _tx_misra_ipsr_get(VOID); +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get()) +#endif +#endif + + +/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value + indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h + for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always + zero after initialization for Cortex-M ports. */ + +#ifndef TX_THREAD_SYSTEM_RETURN_CHECK +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#endif + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +/* Initialize secure stacks for threads calling secure functions. */ +extern void _tx_thread_secure_stack_initialize(void); +#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION _tx_thread_secure_stack_initialize(); +#endif + +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to + prevent early scheduling on Cortex-M parts. */ + +#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT)__CLZ(__RBIT((m))); + +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +/* The embedded assembler blocks are design so as to be inlinable by the + armlink linker inlining. This requires them to consist of either a + single 32-bit instruction, or either one or two 16-bit instructions + followed by a "BX lr". Note that to reduce the critical region size, the + 16-bit "CPSID i" instruction is preceeded by a 16-bit NOP */ + +#ifdef TX_DISABLE_INLINE + +UINT _tx_thread_interrupt_disable(VOID); +VOID _tx_thread_interrupt_restore(UINT previous_posture); + +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); + +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA __istate_t interrupt_save; +#define TX_DISABLE {interrupt_save = __get_interrupt_state();__disable_interrupt();}; +#define TX_RESTORE {__set_interrupt_state(interrupt_save);}; + +#define _tx_thread_system_return _tx_thread_system_return_inline + +static void _tx_thread_system_return_inline(void) +{ +__istate_t interrupt_save; + + /* Set PendSV to invoke ThreadX scheduler. */ + *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + if (__get_IPSR() == 0) + { + interrupt_save = __get_interrupt_state(); + __enable_interrupt(); + __set_interrupt_state(interrupt_save); + } +} + +#endif + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33/IAR Version 6.0.1 *"; +#else +#ifdef TX_MISRA_ENABLE +extern CHAR _tx_version_id[100]; +#else +extern CHAR _tx_version_id[]; +#endif +#endif + + +#endif + + + diff --git a/ports/cortex_m33/iar/inc/tx_secure_interface.h b/ports/cortex_m33/iar/inc/tx_secure_interface.h new file mode 100644 index 00000000..e2133c88 --- /dev/null +++ b/ports/cortex_m33/iar/inc/tx_secure_interface.h @@ -0,0 +1,60 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* tx_secure_interface.h PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the ThreadX secure thread stack components, */ +/* including data types and external references. */ +/* It is assumed that tx_api.h and tx_port.h have already been */ +/* included. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_SECURE_INTERFACE_H +#define TX_SECURE_INTERFACE_H + +/* Define internal secure thread stack function prototypes. */ + +extern void _tx_thread_secure_stack_initialize(void); +extern UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size); +extern UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr); +extern void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr); +extern void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr); + +#endif diff --git a/ports/cortex_m33/iar/readme_threadx.txt b/ports/cortex_m33/iar/readme_threadx.txt new file mode 100644 index 00000000..888a0a71 --- /dev/null +++ b/ports/cortex_m33/iar/readme_threadx.txt @@ -0,0 +1,208 @@ + Microsoft's Azure RTOS ThreadX for Cortex-M33 + + Using the IAR Tools + + +1. Building the ThreadX run-time Library + +Import all ThreadX common and port-specific source files into an IAR project. +Configure the project to build a library rather than an executable. This +results in the ThreadX run-time library file tx.a, which is needed by +the application. + + +2. Demonstration System + +No demonstration is provided because the IAR EWARM 8.50 simulator does +not simulate the Cortex-M33 correctly. + + +3. System Initialization + +The entry point in ThreadX for the Cortex-M33 using IAR tools is at label +__iar_program_start. This is defined within the IAR compiler's startup code. +In addition, this is where all static and global preset C variable +initialization processing takes place. + +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, and a periodic timer interrupt source. + +The _tx_initialize_low_level function inside of tx_initialize_low_level.s +also determines the first available address for use by the application, which +is supplied as the sole input parameter to your application definition function, +tx_application_define. To accomplish this, a section is created in +tx_initialize_low_level.s called FREE_MEM, which must be located after all +other RAM sections in memory. + + +4. Register Usage and Stack Frames + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have the same stack frame in the Cortex-M33 version of +ThreadX. The top of the suspended thread's stack is pointed to by +tx_thread_stack_ptr in the associated thread control block TX_THREAD. + +Non-FPU Stack Frame: + + Stack Offset Stack Contents + + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 r4 + 0x08 r5 + 0x0C r6 + 0x10 r7 + 0x14 r8 + 0x18 r9 + 0x1C r10 + 0x20 r11 + 0x24 r0 (Hardware stack starts here!!) + 0x28 r1 + 0x2C r2 + 0x30 r3 + 0x34 r12 + 0x38 lr + 0x3C pc + 0x40 xPSR + +FPU Stack Frame (only interrupted thread with FPU enabled): + + Stack Offset Stack Contents + + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 s0 + 0x08 s1 + 0x0C s2 + 0x10 s3 + 0x14 s4 + 0x18 s5 + 0x1C s6 + 0x20 s7 + 0x24 s8 + 0x28 s9 + 0x2C s10 + 0x30 s11 + 0x34 s12 + 0x38 s13 + 0x3C s14 + 0x40 s15 + 0x44 s16 + 0x48 s17 + 0x4C s18 + 0x50 s19 + 0x54 s20 + 0x58 s21 + 0x5C s22 + 0x60 s23 + 0x64 s24 + 0x68 s25 + 0x6C s26 + 0x70 s27 + 0x74 s28 + 0x78 s29 + 0x7C s30 + 0x80 s31 + 0x84 fpscr + 0x88 r4 + 0x8C r5 + 0x90 r6 + 0x94 r7 + 0x98 r8 + 0x9C r9 + 0xA0 r10 + 0xA4 r11 + 0xA8 r0 (Hardware stack starts here!!) + 0xAC r1 + 0xB0 r2 + 0xB4 r3 + 0xB8 r12 + 0xBC lr + 0xC0 pc + 0xC4 xPSR + + +5. Improving Performance + +To make ThreadX and the application(s) run faster, you can enable +all compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +6. Interrupt Handling + +The Cortex-M33 vectors start at the label __vector_table and is typically defined in a +startup.s file (or similar). The application may modify the vector area according to its needs. + + +6.1 Managed Interrupts + +ISRs for Cortex-M using the IAR tools can be written completely in C (or assembly +language) without any calls to _tx_thread_context_save or _tx_thread_context_restore. +These ISRs are allowed access to the ThreadX API that is available to ISRs. + +ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table): + +void your_C_isr(void) +{ + + /* ISR processing goes here, including any needed function calls. */ +} + +ISRs written in assembly language will take the form: + + PUBLIC your_assembly_isr +your_assembly_isr: + + PUSH {r0, lr} + + ; ISR processing goes here, including any needed function calls. + + POP {r0, lr} + BX lr + + +7. IAR Thread-safe Library Support + +Thread-safe support for the IAR tools is easily enabled by building the ThreadX library +and the application with TX_ENABLE_IAR_LIBRARY_SUPPORT. Also, the linker control file +should have the following line added (if not already in place): + +initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application + + +7. IAR Thread-safe Library Support + +Thread-safe support for the IAR tools is easily enabled by building the ThreadX library +and the application with TX_ENABLE_IAR_LIBRARY_SUPPORT. Also, the linker control file +should have the following line added (if not already in place): + +initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application + +The project options "General Options -> Library Configuration" should also have the +"Enable thread support in library" box selected. + + +8. VFP Support + +ThreadX for Cortex-M33 supports automatic ("lazy") VFP support, which means that applications threads +can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread +context. + + +9. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06-30-2020 Initial ThreadX 6.0.1 version for Cortex-M33 using IAR's ARM tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_m33/iar/src/tx_iar.c b/ports/cortex_m33/iar/src/tx_iar.c new file mode 100644 index 00000000..dd719370 --- /dev/null +++ b/ports/cortex_m33/iar/src/tx_iar.c @@ -0,0 +1,804 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** IAR Multithreaded Library Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Define IAR library for tools prior to version 8. */ + +#if (__VER__ < 8000000) + + +/* IAR version 7 and below. */ + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_mutex.h" + + +/* This implementation requires that the following macros are defined in the + tx_port.h file and is included with the following code segments: + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. + + Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. +*/ + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT + +#include + + +#if _MULTI_THREAD + +TX_MUTEX __tx_iar_system_lock_mutexes[_MAX_LOCK]; +UINT __tx_iar_system_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_system_lock_no_mutexes; +UINT __tx_iar_system_lock_internal_errors; +UINT __tx_iar_system_lock_isr_caller; + + +/* Define the TLS access function for the IAR library. */ + +void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) +{ + +char _DLIB_TLS_MEMORY *p = 0; + + /* Is there a current thread? */ + if (_tx_thread_current_ptr) + p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; + else + p = (void _DLIB_TLS_MEMORY *) __segment_begin("__DLIB_PERTHREAD"); + p += __IAR_DLIB_PERTHREAD_SYMBOL_OFFSET(symbp); + return (void _DLIB_TLS_MEMORY *) p; +} + + +/* Define mutexes for IAR library. */ + +void __iar_system_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_LOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_system_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_system_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_system_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_system_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_system_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } +} + +void __iar_system_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } +} + + +#if _DLIB_FILE_DESCRIPTOR + +TX_MUTEX __tx_iar_file_lock_mutexes[_MAX_FLOCK]; +UINT __tx_iar_file_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_file_lock_no_mutexes; +UINT __tx_iar_file_lock_internal_errors; +UINT __tx_iar_file_lock_isr_caller; + + +void __iar_file_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_FLOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_file_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_file_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_file_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_file_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_file_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} + +void __iar_file_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} +#endif /* _DLIB_FILE_DESCRIPTOR */ + +#endif /* _MULTI_THREAD */ + +#endif /* TX_ENABLE_IAR_LIBRARY_SUPPORT */ + +#else /* IAR version 8 and above. */ + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_mutex.h" + +/* This implementation requires that the following macros are defined in the + tx_port.h file and is included with the following code segments: + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +void *_tx_iar_create_per_thread_tls_area(void); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); +void __iar_Initlocks(void); + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. + + Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. +*/ + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT + +#include + + +void * __aeabi_read_tp(); + +void* _tx_iar_create_per_thread_tls_area(); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); + +#pragma section="__iar_tls$$DATA" + +/* Define the TLS access function for the IAR library. */ +void * __aeabi_read_tp(void) +{ + void *p = 0; + TX_THREAD *thread_ptr = _tx_thread_current_ptr; + if (thread_ptr) + { + p = thread_ptr->tx_thread_iar_tls_pointer; + } + else + { + p = __section_begin("__iar_tls$$DATA"); + } + return p; +} + +/* Define the TLS creation and destruction to use malloc/free. */ + +void* _tx_iar_create_per_thread_tls_area() +{ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ + void *p = malloc(tls_size); + + /* Initialize TLS-area and run constructors for objects in TLS */ + __iar_tls_init(p); + return p; +} + +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) +{ + /* Destroy objects living in TLS */ + __call_thread_dtors(); + free(tls_ptr); +} + +#ifndef _MAX_LOCK +#define _MAX_LOCK 4 +#endif + +static TX_MUTEX __tx_iar_system_lock_mutexes[_MAX_LOCK]; +static UINT __tx_iar_system_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_system_lock_no_mutexes; +UINT __tx_iar_system_lock_internal_errors; +UINT __tx_iar_system_lock_isr_caller; + + +/* Define mutexes for IAR library. */ + +void __iar_system_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_LOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_system_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_system_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_system_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_system_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_system_Mtxlock(__iar_Rmtx *m) +{ + if (*m) + { + UINT status; + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } + } +} + +void __iar_system_Mtxunlock(__iar_Rmtx *m) +{ + if (*m) + { + UINT status; + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } + } +} + + +#if _DLIB_FILE_DESCRIPTOR + +#include /* Added to get access to FOPEN_MAX */ +#ifndef _MAX_FLOCK +#define _MAX_FLOCK FOPEN_MAX /* Define _MAX_FLOCK as the maximum number of open files */ +#endif + + +TX_MUTEX __tx_iar_file_lock_mutexes[_MAX_FLOCK]; +UINT __tx_iar_file_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_file_lock_no_mutexes; +UINT __tx_iar_file_lock_internal_errors; +UINT __tx_iar_file_lock_isr_caller; + + +void __iar_file_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_FLOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_file_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_file_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_file_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_file_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_file_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} + +void __iar_file_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} +#endif /* _DLIB_FILE_DESCRIPTOR */ + +#endif /* TX_ENABLE_IAR_LIBRARY_SUPPORT */ + +#endif /* IAR version 8 and above. */ diff --git a/ports/cortex_m33/iar/src/tx_initialize_low_level.s b/ports/cortex_m33/iar/src/tx_initialize_low_level.s new file mode 100644 index 00000000..e58c20a1 --- /dev/null +++ b/ports/cortex_m33/iar/src/tx_initialize_low_level.s @@ -0,0 +1,243 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_initialize_unused_memory + EXTERN _tx_timer_interrupt + EXTERN __main + EXTERN __vector_table + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_stack_error_handler +; +; +SYSTEM_CLOCK EQU 96000000 +SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1) +; +; + RSEG FREE_MEM:DATA + PUBLIC __tx_free_memory_start +__tx_free_memory_start + DS32 4 +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-M33/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + PUBLIC _tx_initialize_low_level +_tx_initialize_low_level: +; +; /* Disable interrupts during ThreadX initialization. */ +; + CPSID i +; +; /* Set base of available memory to end of non-initialised RAM area. */ +; + LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer + LDR r1, =__tx_free_memory_start ; Build first free address + STR r1, [r0] ; Setup first unused memory pointer +; +; /* Setup Vector Table Offset Register. */ +; + MOV r0, #0xE000E000 ; Build address of NVIC registers + LDR r1, =__vector_table ; Pickup address of vector table + STR r1, [r0, #0xD08] ; Set vector table address +; +; /* Enable the cycle count register. */ +; +; LDR r0, =0xE0001000 ; Build address of DWT register +; LDR r1, [r0] ; Pickup the current value +; ORR r1, r1, #1 ; Set the CYCCNTENA bit +; STR r1, [r0] ; Enable the cycle count register +; +; /* Set system stack pointer from vector value. */ +; + LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer + LDR r1, =__vector_table ; Pickup address of vector table + LDR r1, [r1] ; Pickup reset stack pointer + STR r1, [r0] ; Save system stack pointer +; +; /* Configure SysTick. */ +; + MOV r0, #0xE000E000 ; Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] ; Setup SysTick Reload Value + MOV r1, #0x7 ; Build SysTick Control Enable Value + STR r1, [r0, #0x10] ; Setup SysTick Control +; +; /* Configure handler priorities. */ +; + LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] ; Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] ; Setup System Handlers 8-11 Priority Registers + ; Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] ; Setup System Handlers 12-15 Priority Registers + ; Note: PnSV must be lowest priority, which is 0xFF +; +; /* Return to caller. */ +; + BX lr +;} +; +; +;/* Define shells for each of the unused vectors. */ +; + PUBLIC __tx_BadHandler +__tx_BadHandler: + B __tx_BadHandler + + + PUBLIC __tx_IntHandler +__tx_IntHandler: +; VOID InterruptHandler (VOID) +; { + PUSH {r0,lr} ; Save LR (and dummy r0 to maintain stack alignment) + +; /* Do interrupt handler work here */ +; /* .... */ + + POP {r0,lr} + BX LR +; } + + + PUBLIC __tx_SysTickHandler + PUBLIC SysTick_Handler +SysTick_Handler: +__tx_SysTickHandler: +; VOID TimerInterruptHandler (VOID) +; { +; + PUSH {r0,lr} ; Save LR (and dummy r0 to maintain stack alignment) + BL _tx_timer_interrupt + POP {r0,lr} + BX LR +; } + + PUBLIC HardFault_Handler +HardFault_Handler: + B HardFault_Handler + + + PUBLIC UsageFault_Handler +UsageFault_Handler: + CPSID i ; Disable interrupts + ; Check for stack limit fault + LDR r0, =0xE000ED28 ; CFSR address + LDR r1,[r0] ; Pick up CFSR + TST r1, #0x00100000 ; Check for Stack Overflow +_unhandled_usage_loop + BEQ _unhandled_usage_loop ; If not stack overflow then loop + + ; Handle stack overflow + STR r1, [r0] ; Clear CFSR flag(s) + +#ifdef __ARMVFP__ + LDR r0, =0xE000EF34 ; Cleanup FPU context: Load FPCCR address + LDR r1, [r0] ; Load FPCCR + BIC r1, r1, #1 ; Clear the lazy preservation active bit + STR r1, [r0] ; Store the value +#endif + + MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address + LDR r0,[r0] ; Pick up current thread pointer + PUSH {r0,lr} ; Save LR (and r0 to maintain stack alignment) + BL _tx_thread_stack_error_handler ; Call ThreadX/user handler + POP {r0,lr} ; Restore LR and dummy reg + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + ; Call the thread exit function to indicate the thread is no longer executing. + PUSH {r0, lr} ; Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit ; Call the thread exit function + POP {r0, lr} ; Recover LR +#endif + + MOV r1, #0 ; Build NULL value + LDR r0, =_tx_thread_current_ptr ; Pickup address of current thread pointer + STR r1, [r0] ; Clear current thread pointer + + ; Return from UsageFault_Handler exception + LDR r0, =0xE000ED04 ; Load ICSR + LDR r1, =0x10000000 ; Set PENDSVSET bit + STR r1, [r0] ; Store ICSR + DSB ; Wait for memory access to complete + CPSIE i ; Enable interrupts + BX lr ; Return from exception + + + PUBLIC __tx_NMIHandler +__tx_NMIHandler: + B __tx_NMIHandler + + + PUBLIC __tx_DBGHandler +__tx_DBGHandler: + B __tx_DBGHandler + + END diff --git a/ports/cortex_m33/iar/src/tx_misra.s b/ports/cortex_m33/iar/src/tx_misra.s new file mode 100644 index 00000000..0edc32a1 --- /dev/null +++ b/ports/cortex_m33/iar/src/tx_misra.s @@ -0,0 +1,1003 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** ThreadX MISRA Compliance */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + #define SHT_PROGBITS 0x1 + + EXTERN __aeabi_memset + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_interrupt_disable + EXTERN _tx_thread_interrupt_restore + EXTERN _tx_thread_stack_analyze + EXTERN _tx_thread_stack_error_handler + EXTERN _tx_thread_system_state +#ifdef TX_ENABLE_EVENT_TRACE + EXTERN _tx_trace_buffer_current_ptr + EXTERN _tx_trace_buffer_end_ptr + EXTERN _tx_trace_buffer_start_ptr + EXTERN _tx_trace_event_enable_bits + EXTERN _tx_trace_full_notify_function + EXTERN _tx_trace_header_ptr +#endif + + PUBLIC _tx_misra_always_true + PUBLIC _tx_misra_block_pool_to_uchar_pointer_convert + PUBLIC _tx_misra_byte_pool_to_uchar_pointer_convert + PUBLIC _tx_misra_char_to_uchar_pointer_convert + PUBLIC _tx_misra_const_char_to_char_pointer_convert +#ifdef TX_ENABLE_EVENT_TRACE + PUBLIC _tx_misra_entry_to_uchar_pointer_convert +#endif + PUBLIC _tx_misra_indirect_void_to_uchar_pointer_convert + PUBLIC _tx_misra_memset + PUBLIC _tx_misra_message_copy +#ifdef TX_ENABLE_EVENT_TRACE + PUBLIC _tx_misra_object_to_uchar_pointer_convert +#endif + PUBLIC _tx_misra_pointer_to_ulong_convert + PUBLIC _tx_misra_status_get + PUBLIC _tx_misra_thread_stack_check +#ifdef TX_ENABLE_EVENT_TRACE + PUBLIC _tx_misra_time_stamp_get +#endif + PUBLIC _tx_misra_timer_indirect_to_void_pointer_convert + PUBLIC _tx_misra_timer_pointer_add + PUBLIC _tx_misra_timer_pointer_dif +#ifdef TX_ENABLE_EVENT_TRACE + PUBLIC _tx_misra_trace_event_insert +#endif + PUBLIC _tx_misra_uchar_pointer_add + PUBLIC _tx_misra_uchar_pointer_dif + PUBLIC _tx_misra_uchar_pointer_sub + PUBLIC _tx_misra_uchar_to_align_type_pointer_convert + PUBLIC _tx_misra_uchar_to_block_pool_pointer_convert +#ifdef TX_ENABLE_EVENT_TRACE + PUBLIC _tx_misra_uchar_to_entry_pointer_convert + PUBLIC _tx_misra_uchar_to_header_pointer_convert +#endif + PUBLIC _tx_misra_uchar_to_indirect_byte_pool_pointer_convert + PUBLIC _tx_misra_uchar_to_indirect_uchar_pointer_convert +#ifdef TX_ENABLE_EVENT_TRACE + PUBLIC _tx_misra_uchar_to_object_pointer_convert +#endif + PUBLIC _tx_misra_uchar_to_void_pointer_convert + PUBLIC _tx_misra_ulong_pointer_add + PUBLIC _tx_misra_ulong_pointer_dif + PUBLIC _tx_misra_ulong_pointer_sub + PUBLIC _tx_misra_ulong_to_pointer_convert + PUBLIC _tx_misra_ulong_to_thread_pointer_convert + PUBLIC _tx_misra_user_timer_pointer_get + PUBLIC _tx_misra_void_to_block_pool_pointer_convert + PUBLIC _tx_misra_void_to_byte_pool_pointer_convert + PUBLIC _tx_misra_void_to_event_flags_pointer_convert + PUBLIC _tx_misra_void_to_indirect_uchar_pointer_convert + PUBLIC _tx_misra_void_to_mutex_pointer_convert + PUBLIC _tx_misra_void_to_queue_pointer_convert + PUBLIC _tx_misra_void_to_semaphore_pointer_convert + PUBLIC _tx_misra_void_to_thread_pointer_convert + PUBLIC _tx_misra_void_to_uchar_pointer_convert + PUBLIC _tx_misra_void_to_ulong_pointer_convert + PUBLIC _tx_misra_ipsr_get + PUBLIC _tx_version_id + + + SECTION `.data`:DATA:REORDER:NOROOT(2) + DATA +// 51 CHAR _tx_version_id[100] = "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX 6.0 MISRA C Compliant *"; +_tx_version_id: + DC8 43H, 6FH, 70H, 79H, 72H, 69H, 67H, 68H + DC8 74H, 20H, 28H, 63H, 29H, 20H, 31H, 39H + DC8 39H, 36H, 2DH, 32H, 30H, 31H, 38H, 20H + DC8 45H, 78H, 70H, 72H, 65H, 73H, 73H, 20H + DC8 4CH, 6FH, 67H, 69H, 63H, 20H, 49H, 6EH + DC8 63H, 2EH, 20H, 2AH, 20H, 54H, 68H, 72H + DC8 65H, 61H, 64H, 58H, 20H, 36H, 2EH, 30H + DC8 20H, 4DH, 49H, 53H, 52H, 41H, 20H, 43H + DC8 20H, 43H, 6FH, 6DH, 70H, 6CH, 69H, 61H + DC8 6EH, 74H, 20H, 2AH, 0 + DC8 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_memset(VOID *ptr, UINT value, UINT size); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_memset: + PUSH {R4,LR} + MOVS R4,R0 + MOVS R0,R2 + MOVS R2,R1 + MOVS R1,R0 + MOVS R0,R4 + BL __aeabi_memset + POP {R4,PC} ;; return + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UCHAR *_tx_misra_uchar_pointer_add(UCHAR *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_pointer_add: + ADD R0,R0,R1 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UCHAR *_tx_misra_uchar_pointer_sub(UCHAR *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_pointer_sub: + RSBS R1,R1,#+0 + ADD R0,R0,R1 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_uchar_pointer_dif(UCHAR *ptr1, UCHAR *ptr2); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_pointer_dif: + SUBS R0,R0,R1 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_pointer_to_ulong_convert: + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG *_tx_misra_ulong_pointer_add(ULONG *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_ulong_pointer_add: + ADD R0,R0,R1, LSL #+2 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG *_tx_misra_ulong_pointer_sub(ULONG *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_ulong_pointer_sub: + MVNS R2,#+3 + MULS R1,R2,R1 + ADD R0,R0,R1 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_ulong_pointer_dif(ULONG *ptr1, ULONG *ptr2); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_ulong_pointer_dif: + SUBS R0,R0,R1 + ASRS R0,R0,#+2 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_ulong_to_pointer_convert: + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_message_copy(ULONG **source, ULONG **destination, */ +/** UINT size); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_message_copy: + PUSH {R4,R5} + LDR R3,[R0, #+0] + LDR R4,[R1, #+0] + LDR R5,[R3, #+0] + STR R5,[R4, #+0] + ADDS R4,R4,#+4 + ADDS R3,R3,#+4 + CMP R2,#+2 + BCC.N ??_tx_misra_message_copy_0 + SUBS R2,R2,#+1 + B.N ??_tx_misra_message_copy_1 +??_tx_misra_message_copy_2: + LDR R5,[R3, #+0] + STR R5,[R4, #+0] + ADDS R4,R4,#+4 + ADDS R3,R3,#+4 + SUBS R2,R2,#+1 +??_tx_misra_message_copy_1: + CMP R2,#+0 + BNE.N ??_tx_misra_message_copy_2 +??_tx_misra_message_copy_0: + STR R3,[R0, #+0] + STR R4,[R1, #+0] + POP {R4,R5} + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_timer_pointer_dif(TX_TIMER_INTERNAL **ptr1, */ +/** TX_TIMER_INTERNAL **ptr2); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_timer_pointer_dif: + SUBS R0,R0,R1 + ASRS R0,R0,#+2 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** TX_TIMER_INTERNAL **_tx_misra_timer_pointer_add(TX_TIMER_INTERNAL */ +/** **ptr1, ULONG size); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_timer_pointer_add: + ADD R0,R0,R1, LSL #+2 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_user_timer_pointer_get(TX_TIMER_INTERNAL */ +/** *internal_timer, TX_TIMER **user_timer); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_user_timer_pointer_get: + ADDS R2,R0,#+8 + SUBS R2,R2,R0 + RSBS R2,R2,#+0 + ADD R0,R0,R2 + STR R0,[R1, #+0] + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_thread_stack_check(TX_THREAD *thread_ptr, */ +/** VOID **highest_stack); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_thread_stack_check: + PUSH {R3-R5,LR} + MOVS R4,R0 + MOVS R5,R1 + BL _tx_thread_interrupt_disable + CMP R4,#+0 + BEQ.N ??_tx_misra_thread_stack_check_0 + LDR R1,[R4, #+0] + LDR.N R2,??DataTable2 ;; 0x54485244 + CMP R1,R2 + BNE.N ??_tx_misra_thread_stack_check_0 + LDR R1,[R4, #+8] + LDR R2,[R5, #+0] + CMP R1,R2 + BCS.N ??_tx_misra_thread_stack_check_1 + LDR R1,[R4, #+8] + STR R1,[R5, #+0] +??_tx_misra_thread_stack_check_1: + LDR R1,[R4, #+12] + LDR R1,[R1, #+0] + CMP R1,#-269488145 + BNE.N ??_tx_misra_thread_stack_check_2 + LDR R1,[R4, #+16] + LDR R1,[R1, #+1] + CMP R1,#-269488145 + BNE.N ??_tx_misra_thread_stack_check_2 + LDR R1,[R5, #+0] + LDR R2,[R4, #+12] + CMP R1,R2 + BCS.N ??_tx_misra_thread_stack_check_3 +??_tx_misra_thread_stack_check_2: + BL _tx_thread_interrupt_restore + MOVS R0,R4 + BL _tx_thread_stack_error_handler + BL _tx_thread_interrupt_disable +??_tx_misra_thread_stack_check_3: + LDR R1,[R5, #+0] + LDR R1,[R1, #-4] + CMP R1,#-269488145 + BEQ.N ??_tx_misra_thread_stack_check_0 + BL _tx_thread_interrupt_restore + MOVS R0,R4 + BL _tx_thread_stack_analyze + BL _tx_thread_interrupt_disable +??_tx_misra_thread_stack_check_0: + BL _tx_thread_interrupt_restore + POP {R0,R4,R5,PC} ;; return + +#ifdef TX_ENABLE_EVENT_TRACE + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_trace_event_insert(ULONG event_id, */ +/** VOID *info_field_1, ULONG info_field_2, ULONG info_field_3, */ +/** ULONG info_field_4, ULONG filter, ULONG time_stamp); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_trace_event_insert: + PUSH {R3-R7,LR} + LDR.N R4,??DataTable2_1 + LDR R4,[R4, #+0] + CMP R4,#+0 + BEQ.N ??_tx_misra_trace_event_insert_0 + LDR.N R5,??DataTable2_2 + LDR R5,[R5, #+0] + LDR R6,[SP, #+28] + TST R5,R6 + BEQ.N ??_tx_misra_trace_event_insert_0 + LDR.N R5,??DataTable2_3 + LDR R5,[R5, #+0] + LDR.N R6,??DataTable2_4 + LDR R6,[R6, #+0] + CMP R5,#+0 + BNE.N ??_tx_misra_trace_event_insert_1 + LDR R5,[R6, #+44] + LDR R7,[R6, #+60] + LSLS R7,R7,#+16 + ORRS R7,R7,#0x80000000 + ORRS R5,R7,R5 + B.N ??_tx_misra_trace_event_insert_2 +??_tx_misra_trace_event_insert_1: + CMP R5,#-252645136 + BCS.N ??_tx_misra_trace_event_insert_3 + MOVS R5,R6 + MOVS R6,#-1 + B.N ??_tx_misra_trace_event_insert_2 +??_tx_misra_trace_event_insert_3: + MOVS R6,#-252645136 + MOVS R5,#+0 +??_tx_misra_trace_event_insert_2: + STR R6,[R4, #+0] + STR R5,[R4, #+4] + STR R0,[R4, #+8] + LDR R0,[SP, #+32] + STR R0,[R4, #+12] + STR R1,[R4, #+16] + STR R2,[R4, #+20] + STR R3,[R4, #+24] + LDR R0,[SP, #+24] + STR R0,[R4, #+28] + ADDS R4,R4,#+32 + LDR.N R0,??DataTable2_5 + LDR R0,[R0, #+0] + CMP R4,R0 + BCC.N ??_tx_misra_trace_event_insert_4 + LDR.N R0,??DataTable2_6 + LDR R4,[R0, #+0] + LDR.N R0,??DataTable2_1 + STR R4,[R0, #+0] + LDR.N R0,??DataTable2_7 + LDR R0,[R0, #+0] + STR R4,[R0, #+32] + LDR.N R0,??DataTable2_8 + LDR R0,[R0, #+0] + CMP R0,#+0 + BEQ.N ??_tx_misra_trace_event_insert_0 + LDR.N R0,??DataTable2_7 + LDR R0,[R0, #+0] + LDR.N R1,??DataTable2_8 + LDR R1,[R1, #+0] + BLX R1 + B.N ??_tx_misra_trace_event_insert_0 +??_tx_misra_trace_event_insert_4: + LDR.N R0,??DataTable2_1 + STR R4,[R0, #+0] + LDR.N R0,??DataTable2_7 + LDR R0,[R0, #+0] + STR R4,[R0, #+32] +??_tx_misra_trace_event_insert_0: + POP {R0,R4-R7,PC} ;; return + + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_1: + DC32 _tx_trace_buffer_current_ptr + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_2: + DC32 _tx_trace_event_enable_bits + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_5: + DC32 _tx_trace_buffer_end_ptr + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_6: + DC32 _tx_trace_buffer_start_ptr + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_7: + DC32 _tx_trace_header_ptr + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_8: + DC32 _tx_trace_full_notify_function + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_time_stamp_get(VOID); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_time_stamp_get: + MOVS R0,#+0 + BX LR ;; return + +#endif + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2: + DC32 0x54485244 + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_3: + DC32 _tx_thread_system_state + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_4: + DC32 _tx_thread_current_ptr + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UINT _tx_misra_always_true(void); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_always_true: + MOVS R0,#+1 + BX LR ;; return + + +/******************************************************************************************/ +/******************************************************************************************/ +/** */ +/** UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr); */ +/** */ +/******************************************************************************************/ +/******************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_indirect_void_to_uchar_pointer_convert: + BX LR ;; return + + +/***************************************************************************************/ +/***************************************************************************************/ +/** */ +/** UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); */ +/** */ +/***************************************************************************************/ +/***************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_indirect_uchar_pointer_convert: + BX LR ;; return + + +/***********************************************************************************/ +/***********************************************************************************/ +/** */ +/** UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); */ +/** */ +/***********************************************************************************/ +/***********************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_block_pool_to_uchar_pointer_convert: + BX LR ;; return + + +/******************************************************************************************/ +/******************************************************************************************/ +/** */ +/** TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); */ +/** */ +/******************************************************************************************/ +/******************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_block_pool_pointer_convert: + BX LR ;; return + + +/*****************************************************************************/ +/*****************************************************************************/ +/** */ +/** UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); */ +/** */ +/*****************************************************************************/ +/*****************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_uchar_pointer_convert: + BX LR ;; return + + +/************************************************************************************/ +/************************************************************************************/ +/** */ +/** TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); */ +/** */ +/************************************************************************************/ +/************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_block_pool_pointer_convert: + BX LR ;; return + + +/**************************************************************************************/ +/**************************************************************************************/ +/** */ +/** UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); */ +/** */ +/**************************************************************************************/ +/**************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_indirect_uchar_pointer_convert: + BX LR ;; return + + +/*****************************************************************************************/ +/*****************************************************************************************/ +/** */ +/** TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); */ +/** */ +/*****************************************************************************************/ +/*****************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_byte_pool_pointer_convert: + BX LR ;; return + + +/***************************************************************************************/ +/***************************************************************************************/ +/** */ +/** UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); */ +/** */ +/***************************************************************************************/ +/***************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_byte_pool_to_uchar_pointer_convert: + BX LR ;; return + + +/*****************************************************************************************/ +/*****************************************************************************************/ +/** */ +/** ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); */ +/** */ +/*****************************************************************************************/ +/*****************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_align_type_pointer_convert: + BX LR ;; return + + +/****************************************************************************************************/ +/****************************************************************************************************/ +/** */ +/** TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); */ +/** */ +/****************************************************************************************************/ +/****************************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_indirect_byte_pool_pointer_convert: + BX LR ;; return + + +/**************************************************************************************************/ +/**************************************************************************************************/ +/** */ +/** TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); */ +/** */ +/**************************************************************************************************/ +/**************************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_event_flags_pointer_convert: + BX LR ;; return + + +/*****************************************************************************/ +/*****************************************************************************/ +/** */ +/** ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); */ +/** */ +/*****************************************************************************/ +/*****************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_ulong_pointer_convert: + BX LR ;; return + + +/********************************************************************************/ +/********************************************************************************/ +/** */ +/** TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); */ +/** */ +/********************************************************************************/ +/********************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_mutex_pointer_convert: + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UINT _tx_misra_status_get(UINT status); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_status_get: + MOVS R0,#+0 + BX LR ;; return + + +/********************************************************************************/ +/********************************************************************************/ +/** */ +/** TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); */ +/** */ +/********************************************************************************/ +/********************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_queue_pointer_convert: + BX LR ;; return + + +/****************************************************************************************/ +/****************************************************************************************/ +/** */ +/** TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); */ +/** */ +/****************************************************************************************/ +/****************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_semaphore_pointer_convert: + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_void_pointer_convert: + BX LR ;; return + + +/*********************************************************************************/ +/*********************************************************************************/ +/** */ +/** TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); */ +/** */ +/*********************************************************************************/ +/*********************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_ulong_to_thread_pointer_convert: + BX LR ;; return + + +/***************************************************************************************************/ +/***************************************************************************************************/ +/** */ +/** VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); */ +/** */ +/***************************************************************************************************/ +/***************************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_timer_indirect_to_void_pointer_convert: + BX LR ;; return + + +/***************************************************************************************/ +/***************************************************************************************/ +/** */ +/** CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); */ +/** */ +/***************************************************************************************/ +/***************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_const_char_to_char_pointer_convert: + BX LR ;; return + + +/**********************************************************************************/ +/**********************************************************************************/ +/** */ +/** TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer); */ +/** */ +/**********************************************************************************/ +/**********************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_thread_pointer_convert: + BX LR ;; return + + +#ifdef TX_ENABLE_EVENT_TRACE + +/************************************************************************************************/ +/************************************************************************************************/ +/** */ +/** UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); */ +/** */ +/************************************************************************************************/ +/************************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_object_to_uchar_pointer_convert: + BX LR ;; return + + +/************************************************************************************************/ +/************************************************************************************************/ +/** */ +/** TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); */ +/** */ +/************************************************************************************************/ +/************************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_object_pointer_convert: + BX LR ;; return + + +/******************************************************************************************/ +/******************************************************************************************/ +/** */ +/** TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); */ +/** */ +/******************************************************************************************/ +/******************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_header_pointer_convert: + BX LR ;; return + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_entry_pointer_convert: + BX LR ;; return + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_entry_to_uchar_pointer_convert: + BX LR ;; return +#endif + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_char_to_uchar_pointer_convert: + BX LR ;; return + + +***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** ULONG _tx_misra_ipsr_get(void); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_ipsr_get: + MRS R0, IPSR + BX LR ;; return + + + SECTION `.iar_vfe_header`:DATA:NOALLOC:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA + DC32 0 + + END diff --git a/ports/cortex_m33/iar/src/tx_thread_context_restore.s b/ports/cortex_m33/iar/src/tx_thread_context_restore.s new file mode 100644 index 00000000..0fee5f51 --- /dev/null +++ b/ports/cortex_m33/iar/src/tx_thread_context_restore.s @@ -0,0 +1,88 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + EXTERN _tx_execution_isr_exit +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-M33/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + PUBLIC _tx_thread_context_restore +_tx_thread_context_restore: + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + PUSH {r0, lr} ; Save return address + BL _tx_execution_isr_exit ; Call the ISR exit function + POP {r0, lr} ; Recover Save return address +#endif +; +; /* Return to interrupt processing. */ +; + BX lr +;} + END + diff --git a/ports/cortex_m33/iar/src/tx_thread_context_save.s b/ports/cortex_m33/iar/src/tx_thread_context_save.s new file mode 100644 index 00000000..6774dd3d --- /dev/null +++ b/ports/cortex_m33/iar/src/tx_thread_context_save.s @@ -0,0 +1,86 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + EXTERN _tx_execution_isr_enter +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-M33/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + PUBLIC _tx_thread_context_save +_tx_thread_context_save: +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {r0, lr} ; Save return address + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {r0, lr} ; Recover return address +#endif +; +; /* Return to interrupt processing. */ +; + BX lr +;} + END + diff --git a/ports/cortex_m33/iar/src/tx_thread_interrupt_control.s b/ports/cortex_m33/iar/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..0fe770f4 --- /dev/null +++ b/ports/cortex_m33/iar/src/tx_thread_interrupt_control.s @@ -0,0 +1,77 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-M33/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + PUBLIC _tx_thread_interrupt_control +_tx_thread_interrupt_control: +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r1, PRIMASK + MSR PRIMASK, r0 + MOV r0, r1 + BX lr +; +;} + END diff --git a/ports/cortex_m33/iar/src/tx_thread_interrupt_disable.s b/ports/cortex_m33/iar/src/tx_thread_interrupt_disable.s new file mode 100644 index 00000000..82a8d239 --- /dev/null +++ b/ports/cortex_m33/iar/src/tx_thread_interrupt_disable.s @@ -0,0 +1,76 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-M33/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts and returning */ +;/* the previous interrupt lockout posture. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(UINT new_posture) +;{ + PUBLIC _tx_thread_interrupt_disable +_tx_thread_interrupt_disable: +; +; /* Return current interrupt lockout posture. */ +; + MRS r0, PRIMASK + CPSID i + BX lr +; +;} + END diff --git a/ports/cortex_m33/iar/src/tx_thread_interrupt_restore.s b/ports/cortex_m33/iar/src/tx_thread_interrupt_restore.s new file mode 100644 index 00000000..b90c86c0 --- /dev/null +++ b/ports/cortex_m33/iar/src/tx_thread_interrupt_restore.s @@ -0,0 +1,75 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-M33/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for restoring the previous */ +;/* interrupt lockout posture. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* previous_posture Previous interrupt posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_interrupt_restore(UINT new_posture) +;{ + PUBLIC _tx_thread_interrupt_restore +_tx_thread_interrupt_restore: +; +; /* Restore previous interrupt lockout posture. */ +; + MSR PRIMASK, r0 + BX lr +; +;} + END diff --git a/ports/cortex_m33/iar/src/tx_thread_schedule.s b/ports/cortex_m33/iar/src/tx_thread_schedule.s new file mode 100644 index 00000000..161766f2 --- /dev/null +++ b/ports/cortex_m33/iar/src/tx_thread_schedule.s @@ -0,0 +1,330 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_thread_preempt_disable + EXTERN _tx_execution_thread_enter + EXTERN _tx_execution_thread_exit + EXTERN _tx_thread_secure_stack_context_restore + EXTERN _tx_thread_secure_stack_context_save + EXTERN _tx_thread_secure_mode_stack_allocate + EXTERN _tx_thread_secure_mode_stack_free +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-M33/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + PUBLIC _tx_thread_schedule +_tx_thread_schedule: +; +; /* This function should only ever be called on Cortex-M +; from the first schedule request. Subsequent scheduling occurs +; from the PendSV handling routines below. */ +; +; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ +; + MOV r0, #0 ; Build value for TX_FALSE + LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag + STR r0, [r2, #0] ; Clear preempt disable flag +; +; /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */ +; +#ifdef __ARMVFP__ + MRS r0, CONTROL ; Pickup current CONTROL register + BIC r0, r0, #4 ; Clear the FPCA bit + MSR CONTROL, r0 ; Setup new CONTROL register +#endif +; +; /* Enable interrupts */ +; + CPSIE i +; +; /* Enter the scheduler for the first time. */ +; + MOV r0, #0x10000000 ; Load PENDSVSET bit + MOV r1, #0xE000E000 ; Load NVIC base + STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR + DSB ; Complete all memory accesses + ISB ; Flush pipeline +; +; /* Wait here for the PendSV to take place. */ +; +__tx_wait_here: + B __tx_wait_here ; Wait for the PendSV to happen +;} +; +; /* Generic context switching PendSV handler. */ +; + PUBLIC PendSV_Handler +PendSV_Handler: +; +; /* Get current thread value and new thread pointer. */ +; +__tx_ts_handler: + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + CPSID i ; Disable interrupts + PUSH {r0, lr} ; Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit ; Call the thread exit function + POP {r0, lr} ; Recover LR + CPSIE i ; Enable interrupts +#endif + MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address + MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address + MOV r3, #0 ; Build NULL value + LDR r1, [r0] ; Pickup current thread pointer +; +; /* Determine if there is a current thread to finish preserving. */ +; + CBZ r1, __tx_ts_new ; If NULL, skip preservation +; +; /* Recover PSP and preserve current thread context. */ +; + STR r3, [r0] ; Set _tx_thread_current_ptr to NULL + MRS r12, PSP ; Pickup PSP pointer (thread's stack pointer) + STMDB r12!, {r4-r11} ; Save its remaining registers +#ifdef __ARMVFP__ + TST LR, #0x10 ; Determine if the VFP extended frame is present + BNE _skip_vfp_save + VSTMDB r12!,{s16-s31} ; Yes, save additional VFP registers +_skip_vfp_save: +#endif + MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable + STMDB r12!, {LR} ; Save LR on the stack + STR r12, [r1, #8] ; Save the thread stack pointer + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + ; Save secure context + LDR r5, [r1,#0x90] ; Load secure stack index + CBZ r5, _skip_secure_save ; Skip save if there is no secure context + PUSH {r0,r1,r2,r3} ; Save scratch registers + MOV r0, r1 ; Move thread ptr to r0 + BL _tx_thread_secure_stack_context_save ; Save secure stack + POP {r0,r1,r2,r3} ; Restore secure registers +_skip_secure_save: +#endif +; +; /* Determine if time-slice is active. If it isn't, skip time handling processing. */ +; + LDR r5, [r4] ; Pickup current time-slice + CBZ r5, __tx_ts_new ; If not active, skip processing +; +; /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ +; + STR r5, [r1, #24] ; Save current time-slice +; +; /* Clear the global time-slice. */ +; + STR r3, [r4] ; Clear time-slice +; +; /* Executing thread is now completely preserved!!! */ +; +__tx_ts_new: +; +; /* Now we are looking for a new thread to execute! */ +; + CPSID i ; Disable interrupts + LDR r1, [r2] ; Is there another thread ready to execute? + CBZ r1, __tx_ts_wait ; No, skip to the wait processing +; +; /* Yes, another thread is ready for else, make the current thread the new thread. */ +; + STR r1, [r0] ; Setup the current thread pointer to the new thread + CPSIE i ; Enable interrupts +; +; /* Increment the thread run count. */ +; +__tx_ts_restore: + LDR r7, [r1, #4] ; Pickup the current thread run count + MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable + LDR r5, [r1, #24] ; Pickup thread's current time-slice + ADD r7, r7, #1 ; Increment the thread run count + STR r7, [r1, #4] ; Store the new run count +; +; /* Setup global time-slice with thread's current time-slice. */ +; + STR r5, [r4] ; Setup global time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + PUSH {r0, r1} ; Save r0/r1 + BL _tx_execution_thread_enter ; Call the thread execution enter function + POP {r0, r1} ; Recover r0/r1 +#endif + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + ; Restore secure context + LDR r0, [r1,#0x90] ; Load secure stack index + CBZ r0, _skip_secure_restore ; Skip restore if there is no secure context + PUSH {r0,r1} ; Save r1 (and dummy r0) + MOV r0, r1 ; Move thread ptr to r0 + BL _tx_thread_secure_stack_context_restore ; Restore secure stack + POP {r0,r1} ; Restore r1 (and dummy r0) +_skip_secure_restore: +#endif + +; +; /* Restore the thread context and PSP. */ +; + LDR r12, [r1, #12] ; Get stack start + MSR PSPLIM, r12 ; Set stack limit + LDR r12, [r1, #8] ; Pickup thread's stack pointer + LDMIA r12!, {LR} ; Pickup LR +#ifdef __ARMVFP__ + TST LR, #0x10 ; Determine if the VFP extended frame is present + BNE _skip_vfp_restore ; If not, skip VFP restore + VLDMIA r12!, {s16-s31} ; Yes, restore additional VFP registers +_skip_vfp_restore: +#endif + LDMIA r12!, {r4-r11} ; Recover thread's registers + MSR PSP, r12 ; Setup the thread's stack pointer +; +; /* Return to thread. */ +; + BX lr ; Return to thread! +; +; /* The following is the idle wait processing... in this case, no threads are ready for execution and the +; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +; are disabled to allow use of WFI for waiting for a thread to arrive. */ +; +__tx_ts_wait: + CPSID i ; Disable interrupts + LDR r1, [r2] ; Pickup the next thread to execute pointer + STR r1, [r0] ; Store it in the current pointer + CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready! +#ifdef TX_ENABLE_WFI + DSB ; Ensure no outstanding memory transactions + WFI ; Wait for interrupt + ISB ; Ensure pipeline is flushed +#endif + CPSIE i ; Enable interrupts + B __tx_ts_wait ; Loop to continue waiting +; +; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +; already in the handler! */ +; +__tx_ts_ready: + MOV r7, #0x08000000 ; Build clear PendSV value + MOV r8, #0xE000E000 ; Build base NVIC address + STR r7, [r8, #0xD04] ; Clear any PendSV +; +; /* Re-enable interrupts and restore new thread. */ +; + CPSIE i ; Enable interrupts + B __tx_ts_restore ; Restore the thread + + + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + ; SVC_Handler is not needed when ThreadX is running in single mode. + PUBLIC SVC_Handler +SVC_Handler: + TST lr, #0x04 ; Determine return stack from EXC_RETURN bit 2 + ITE EQ + MRSEQ r0, MSP ; Get MSP if return stack is MSP + MRSNE r0, PSP ; Get PSP if return stack is PSP + + LDR r1, [r0,#24] ; Load saved PC from stack + LDRB r1, [r1,#-2] ; Load SVC number + + CMP r1, #1 ; Is it a secure stack allocate request? + BEQ _tx_svc_secure_alloc ; Yes, go there + + CMP r1, #2 ; Is it a secure stack free request? + BEQ _tx_svc_secure_free ; Yes, go there + + ; Unknown SVC argument - just return + BX lr + +_tx_svc_secure_alloc: + PUSH {r0,lr} ; Save SP and EXC_RETURN + LDM r0, {r0-r3} ; Load function parameters from stack + BL _tx_thread_secure_mode_stack_allocate + POP {r12,lr} ; Restore SP and EXC_RETURN + STR r0,[r12] ; Store function return value + BX lr +_tx_svc_secure_free: + PUSH {r0,lr} ; Save SP and EXC_RETURN + LDM r0, {r0-r3} ; Load function parameters from stack + BL _tx_thread_secure_mode_stack_free + POP {r12,lr} ; Restore SP and EXC_RETURN + STR r0,[r12] ; Store function return value + BX lr +#endif ; End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE + + + PUBLIC _tx_vfp_access +_tx_vfp_access: + VMOV.F32 s0, s0 ; Simply access the VFP + BX lr ; Return to caller + + END diff --git a/ports/cortex_m33/iar/src/tx_thread_secure_stack.c b/ports/cortex_m33/iar/src/tx_thread_secure_stack.c new file mode 100644 index 00000000..7d4a4b2e --- /dev/null +++ b/ports/cortex_m33/iar/src/tx_thread_secure_stack.c @@ -0,0 +1,464 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#include "tx_api.h" + +/* If TX_SINGLE_MODE_SECURE or TX_SINGLE_MODE_NON_SECURE is defined, + no secure stack functionality is needed. */ +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + +#define TX_SOURCE_CODE + +#include /* For intrinsic functions. */ +#include "tx_secure_interface.h" /* Interface for NS code. */ + +/* Minimum size of secure stack. */ +#ifndef TX_THREAD_SECURE_STACK_MINIMUM +#define TX_THREAD_SECURE_STACK_MINIMUM 256 +#endif +/* Maximum size of secure stack. */ +#ifndef TX_THREAD_SECURE_STACK_MAXIMUM +#define TX_THREAD_SECURE_STACK_MAXIMUM 1024 +#endif + +/* Secure stack info struct to hold stack start, stack limit, + current stack pointer, and pointer to owning thread. + This will be allocated for each thread with a secure stack. */ +typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT +{ + VOID *tx_thread_secure_stack_ptr; /* Thread's secure stack current pointer */ + VOID *tx_thread_secure_stack_start; /* Thread's secure stack start address */ + VOID *tx_thread_secure_stack_limit; /* Thread's secure stack limit */ + TX_THREAD *tx_thread_ptr; /* Keep track of thread for error handling */ +} TX_THREAD_SECURE_STACK_INFO; + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_initialize Cortex-M33/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes secure mode to use PSP stack. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __get_CONTROL Intrinsic to get CONTROL */ +/* __set_CONTROL Intrinsic to set CONTROL */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +void _tx_thread_secure_stack_initialize(void) +{ + + /* Set secure mode to use PSP. */ + __set_CONTROL(__get_CONTROL() | 2); + + /* Set process stack pointer and stack limit to 0 to throw exception when a thread + without a secure stack calls a secure function that tries to use secure stack. */ + __set_PSPLIM(0); + __set_PSP(0); + + return; +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_mode_stack_allocate PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function allocates a thread's secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* stack_size Size of stack to allocates */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_SIZE_ERROR Invalid stack size */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* calloc Compiler's calloc function */ +/* malloc Compiler's malloc function */ +/* free Compiler's free() function */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* __TZ_get_PSPLIM_NS Intrinsic to get NS PSP */ +/* */ +/* CALLED BY */ +/* */ +/* SVC Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +{ +UINT status; +TX_THREAD_SECURE_STACK_INFO *info_ptr; +UCHAR *stack_mem; + + status = TX_SUCCESS; + + /* Make sure function is called from interrupt (threads should not call). */ + if (__get_IPSR() == 0) + { + status = TX_CALLER_ERROR; + } + else if (stack_size < TX_THREAD_SECURE_STACK_MINIMUM || stack_size > TX_THREAD_SECURE_STACK_MAXIMUM) + { + status = TX_SIZE_ERROR; + } + + /* Check if thread already has secure stack allocated. */ + else if (thread_ptr -> tx_thread_secure_stack_context != 0) + { + status = TX_THREAD_ERROR; + } + + else + { + + /* Allocate space for secure stack info. */ + info_ptr = calloc(1, sizeof(TX_THREAD_SECURE_STACK_INFO)); + + if(info_ptr != TX_NULL) + { + /* If stack info allocated, allocate a stack. */ + stack_mem = malloc(stack_size); + + if(stack_mem != TX_NULL) + { + /* Secure stack has been allocated, save in the stack info struct. */ + info_ptr -> tx_thread_secure_stack_limit = stack_mem; + info_ptr -> tx_thread_secure_stack_start = stack_mem + stack_size; + info_ptr -> tx_thread_secure_stack_ptr = info_ptr -> tx_thread_secure_stack_start; + info_ptr -> tx_thread_ptr = thread_ptr; + + /* Save info pointer in thread. */ + thread_ptr -> tx_thread_secure_stack_context = info_ptr; + + /* Check if this thread is running by looking at its stack start and PSPLIM_NS */ + if(((ULONG) thread_ptr -> tx_thread_stack_start & 0xFFFFFFF8) == __TZ_get_PSPLIM_NS()) + { + /* If this thread is running, set Secure PSP and PSPLIM. */ + __set_PSPLIM((ULONG)(info_ptr -> tx_thread_secure_stack_limit)); + __set_PSP((ULONG)(info_ptr -> tx_thread_secure_stack_ptr)); + } + } + + else + { + /* Stack not allocated, free the info struct. */ + free(info_ptr); + status = TX_NO_MEMORY; + } + } + + else + { + status = TX_NO_MEMORY; + } + } + + return(status); +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_mode_stack_free PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function frees a thread's secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* free Compiler's free() function */ +/* */ +/* CALLED BY */ +/* */ +/* SVC Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr) +{ +UINT status; +TX_THREAD_SECURE_STACK_INFO *info_ptr; + + status = TX_SUCCESS; + + /* Pickup stack info from thread. */ + info_ptr = thread_ptr -> tx_thread_secure_stack_context; + + /* Make sure function is called from interrupt (threads should not call). */ + if (__get_IPSR() == 0) + { + status = TX_CALLER_ERROR; + } + + /* Check that this secure context is for this thread. */ + else if (info_ptr -> tx_thread_ptr != thread_ptr) + { + status = TX_THREAD_ERROR; + } + + else + { + + /* Free secure stack. */ + free(info_ptr -> tx_thread_secure_stack_limit); + + /* Free info struct. */ + free(info_ptr); + + /* Clear secure context from thread. */ + thread_ptr -> tx_thread_secure_stack_context = 0; + } + + return(status); +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_context_save PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves context of the secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* __get_PSP Intrinsic to get PSP */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* */ +/* CALLED BY */ +/* */ +/* PendSV Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr) +{ +TX_THREAD_SECURE_STACK_INFO *info_ptr; +ULONG sp; + + /* This function should be called from scheduler only. */ + if (__get_IPSR() == 0) + { + return; + } + + /* Pickup the secure context pointer. */ + info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); + + /* Check that this secure context is for this thread. */ + if (info_ptr -> tx_thread_ptr != thread_ptr) + { + return; + } + + /* Check that stack pointer is in range */ + sp = __get_PSP(); + if ((sp < (ULONG)info_ptr -> tx_thread_secure_stack_limit) || + (sp > (ULONG)info_ptr -> tx_thread_secure_stack_start)) + { + return; + } + + /* Save stack pointer. */ + *(ULONG *) info_ptr -> tx_thread_secure_stack_ptr = sp; + + /* Set process stack pointer and stack limit to 0 to throw exception when a thread + without a secure stack calls a secure function that tries to use secure stack. */ + __set_PSPLIM(0); + __set_PSP(0); + + return; +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_context_restore PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores context of the secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* */ +/* CALLED BY */ +/* */ +/* PendSV Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr) +{ +TX_THREAD_SECURE_STACK_INFO *info_ptr; + + /* This function should be called from scheduler only. */ + if (__get_IPSR() == 0) + { + return; + } + + /* Pickup the secure context pointer. */ + info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); + + /* Check that this secure context is for this thread. */ + if (info_ptr -> tx_thread_ptr != thread_ptr) + { + return; + } + + /* Set stack pointer and limit. */ + __set_PSPLIM((ULONG)info_ptr -> tx_thread_secure_stack_limit); + __set_PSP ((ULONG)info_ptr -> tx_thread_secure_stack_ptr); + + return; +} + +#endif diff --git a/ports/cortex_m33/iar/src/tx_thread_secure_stack_allocate.s b/ports/cortex_m33/iar/src/tx_thread_secure_stack_allocate.s new file mode 100644 index 00000000..dc414183 --- /dev/null +++ b/ports/cortex_m33/iar/src/tx_thread_secure_stack_allocate.s @@ -0,0 +1,82 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_secure_stack_allocate Cortex-M33/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function enters the SVC handler to allocate a secure stack. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Thread control block pointer */ +;/* stack_size Size of secure stack to */ +;/* allocate */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* status Actual completion status */ +;/* */ +;/* CALLS */ +;/* */ +;/* SVC 1 */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +;{ + EXPORT _tx_thread_secure_stack_allocate +_tx_thread_secure_stack_allocate: +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + MRS r3, PRIMASK ; Save interrupt mask + CPSIE i ; Enable interrupts for SVC call + SVC 1 + CMP r3, #0 ; If interrupts enabled, just return + BEQ _alloc_return_interrupt_enabled + CPSID i ; Otherwise, disable interrupts +#else + MOV32 r0, #0xFF ; Feature not enabled +#endif +_alloc_return_interrupt_enabled + BX lr + + END diff --git a/ports/cortex_m33/iar/src/tx_thread_secure_stack_free.s b/ports/cortex_m33/iar/src/tx_thread_secure_stack_free.s new file mode 100644 index 00000000..3fb3c795 --- /dev/null +++ b/ports/cortex_m33/iar/src/tx_thread_secure_stack_free.s @@ -0,0 +1,80 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_secure_stack_free Cortex-M33/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function enters the SVC handler to free a secure stack. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Thread control block pointer */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* status Actual completion status */ +;/* */ +;/* CALLS */ +;/* */ +;/* SVC 2 */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) +;{ + EXPORT _tx_thread_secure_stack_free +_tx_thread_secure_stack_free: +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + MRS r3, PRIMASK ; Save interrupt mask + CPSIE i ; Enable interrupts for SVC call + SVC 2 + CMP r3, #0 ; If interrupts enabled, just return + BEQ _free_return_interrupt_enabled + CPSID i ; Otherwise, disable interrupts +#else + MOV32 r0, #0xFF ; Feature not enabled +#endif +_free_return_interrupt_enabled + BX lr + END + \ No newline at end of file diff --git a/ports/cortex_m33/iar/src/tx_thread_stack_build.s b/ports/cortex_m33/iar/src/tx_thread_stack_build.s new file mode 100644 index 00000000..8d63dbf0 --- /dev/null +++ b/ports/cortex_m33/iar/src/tx_thread_stack_build.s @@ -0,0 +1,138 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-M33/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + PUBLIC _tx_thread_stack_build +_tx_thread_stack_build: +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-M33 should look like the following after it is built: +; +; Stack Top: +; LR Interrupted LR (LR at time of PENDSV) +; r4 Initial value for r4 +; r5 Initial value for r5 +; r6 Initial value for r6 +; r7 Initial value for r7 +; r8 Initial value for r8 +; r9 Initial value for r9 +; r10 Initial value for r10 +; r11 Initial value for r11 +; r0 Initial value for r0 (Hardware stack starts here!!) +; r1 Initial value for r1 +; r2 Initial value for r2 +; r3 Initial value for r3 +; r12 Initial value for r12 +; lr Initial value for lr +; pc Initial value for pc +; xPSR Initial value for xPSR +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #0x7 ; Align frame for 8-byte alignment + SUB r2, r2, #68 ; Subtract frame size +#ifdef TX_SINGLE_MODE_SECURE + LDR r3, =0xFFFFFFFD ; Build initial LR value for secure mode +#else + LDR r3, =0xFFFFFFBC ; Build initial LR value to return to non-secure PSP +#endif + STR r3, [r2, #0] ; Save on the stack +; +; /* Actually build the stack frame. */ +; + MOV r3, #0 ; Build initial register value + STR r3, [r2, #4] ; Store initial r4 + STR r3, [r2, #8] ; Store initial r5 + STR r3, [r2, #12] ; Store initial r6 + STR r3, [r2, #16] ; Store initial r7 + STR r3, [r2, #20] ; Store initial r8 + STR r3, [r2, #24] ; Store initial r9 + STR r3, [r2, #28] ; Store initial r10 + STR r3, [r2, #32] ; Store initial r11 +; +; /* Hardware stack follows. */ +; + STR r3, [r2, #36] ; Store initial r0 + STR r3, [r2, #40] ; Store initial r1 + STR r3, [r2, #44] ; Store initial r2 + STR r3, [r2, #48] ; Store initial r3 + STR r3, [r2, #52] ; Store initial r12 + MOV r3, #0xFFFFFFFF ; Poison EXC_RETURN value + STR r3, [r2, #56] ; Store initial lr + STR r1, [r2, #60] ; Store initial pc + MOV r3, #0x01000000 ; Only T-bit need be set + STR r3, [r2, #64] ; Store initial xPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block + BX lr ; Return to caller +;} + END + diff --git a/ports/cortex_m33/iar/src/tx_thread_stack_error_handler.c b/ports/cortex_m33/iar/src/tx_thread_stack_error_handler.c new file mode 100644 index 00000000..03fe6fdb --- /dev/null +++ b/ports/cortex_m33/iar/src/tx_thread_stack_error_handler.c @@ -0,0 +1,97 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + +/* Define the global function pointer for stack error handling. If a stack error is + detected and the application has registered a stack error handler, it will be + called via this function pointer. */ + +VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_error_handler Cortex-M33/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes stack errors detected during run-time. */ +/* */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_terminate */ +/* _tx_thread_application_stack_error_handler */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX internal code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) +{ + + #ifndef TX_THREAD_NO_TERMINATE_STACK_ERROR + /* Is there a thread? */ + if (thread_ptr) + { + /* Terminate the current thread. */ + _tx_thread_terminate(_tx_thread_current_ptr); + } + #endif + + /* Determine if the application has registered an error handler. */ + if (_tx_thread_application_stack_error_handler != TX_NULL) + { + + /* Yes, an error handler is present, simply call the application error handler. */ + (_tx_thread_application_stack_error_handler)(thread_ptr); + } + +} + diff --git a/ports/cortex_m33/iar/src/tx_thread_stack_error_notify.c b/ports/cortex_m33/iar/src/tx_thread_stack_error_notify.c new file mode 100644 index 00000000..eb9b3928 --- /dev/null +++ b/ports/cortex_m33/iar/src/tx_thread_stack_error_notify.c @@ -0,0 +1,98 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_trace.h" + +extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_error_notify Cortex-M33/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application stack error handler. If */ +/* ThreadX detects a stack error, this application handler is called. */ +/* */ +/* */ +/* INPUT */ +/* */ +/* stack_error_handler Pointer to stack error */ +/* handler, TX_NULL to disable */ +/* */ +/* OUTPUT */ +/* */ +/* status Service return status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr)) +{ + +TX_INTERRUPT_SAVE_AREA + + + /* Disable interrupts. */ + TX_DISABLE + + /* Make entry in event log. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_STACK_ERROR_NOTIFY, 0, 0, 0, 0, TX_TRACE_THREAD_EVENTS) + + /* Make entry in event log. */ + TX_EL_THREAD_STACK_ERROR_NOTIFY_INSERT + + /* Setup global thread stack error handler. */ + _tx_thread_application_stack_error_handler = stack_error_handler; + + /* Restore interrupts. */ + TX_RESTORE + + /* Return success to caller. */ + return(TX_SUCCESS); +} + diff --git a/ports/cortex_m33/iar/src/tx_thread_system_return.s b/ports/cortex_m33/iar/src/tx_thread_system_return.s new file mode 100644 index 00000000..9d55121e --- /dev/null +++ b/ports/cortex_m33/iar/src/tx_thread_system_return.s @@ -0,0 +1,87 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-M33/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + PUBLIC _tx_thread_system_return +_tx_thread_system_return??rA: +_tx_thread_system_return: +; +; /* Return to real scheduler via PendSV. Note that this routine is often +; replaced with in-line assembly in tx_port.h to improved performance. */ +; + MOV r0, #0x10000000 ; Load PENDSVSET bit + MOV r1, #0xE000E000 ; Load NVIC base + STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR + MRS r0, IPSR ; Pickup IPSR + CMP r0, #0 ; Is it a thread returning? + BNE _isr_context ; If ISR, skip interrupt enable + MRS r1, PRIMASK ; Thread context returning, pickup PRIMASK + CPSIE i ; Enable interrupts + MSR PRIMASK, r1 ; Restore original interrupt posture +_isr_context: + BX lr ; Return to caller +;} + END diff --git a/ports/cortex_m33/iar/src/tx_timer_interrupt.s b/ports/cortex_m33/iar/src/tx_timer_interrupt.s new file mode 100644 index 00000000..cbda08bd --- /dev/null +++ b/ports/cortex_m33/iar/src/tx_timer_interrupt.s @@ -0,0 +1,257 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + EXTERN _tx_timer_time_slice + EXTERN _tx_timer_system_clock + EXTERN _tx_timer_current_ptr + EXTERN _tx_timer_list_start + EXTERN _tx_timer_list_end + EXTERN _tx_timer_expired_time_slice + EXTERN _tx_timer_expired + EXTERN _tx_thread_time_slice + EXTERN _tx_timer_expiration_process + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_thread_preempt_disable +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-M33/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* the expiration functions are called. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + PUBLIC _tx_timer_interrupt +_tx_timer_interrupt: +; +; /* Upon entry to this routine, it is assumed that the compiler scratch registers are available +; for use. */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + MOV32 r1, _tx_timer_system_clock ; Pickup address of system clock + LDR r0, [r1, #0] ; Pickup system clock + ADD r0, r0, #1 ; Increment system clock + STR r0, [r1, #0] ; Store new system clock +; +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice + LDR r2, [r3, #0] ; Pickup time-slice + CBZ r2, __tx_timer_no_time_slice ; Is it non-active? + ; Yes, skip time-slice processing +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; + SUB r2, r2, #1 ; Decrement the time-slice + STR r2, [r3, #0] ; Store new time-slice value +; +; /* Check for expiration. */ +; if (__tx_timer_time_slice == 0) +; + CBNZ r2, __tx_timer_no_time_slice ; Has it expired? +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup address of expired flag + MOV r0, #1 ; Build expired value + STR r0, [r3, #0] ; Set time-slice expiration flag +; +; } +; +__tx_timer_no_time_slice: +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + MOV32 r1, _tx_timer_current_ptr ; Pickup current timer pointer address + LDR r0, [r1, #0] ; Pickup current timer + LDR r2, [r0, #0] ; Pickup timer list entry + CBZ r2, __tx_timer_no_timer ; Is there anything in the list? + ; No, just increment the timer +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + MOV32 r3, _tx_timer_expired ; Pickup expiration flag address + MOV r2, #1 ; Build expired value + STR r2, [r3, #0] ; Set expired flag + B __tx_timer_done ; Finished timer processing +; +; } +; else +; { +__tx_timer_no_timer: +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ADD r0, r0, #4 ; Move to next timer +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + MOV32 r3, _tx_timer_list_end ; Pickup addr of timer list end + LDR r2, [r3, #0] ; Pickup list end + CMP r0, r2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, skip wrap-around logic +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + MOV32 r3, _tx_timer_list_start ; Pickup addr of timer list start + LDR r0, [r3, #0] ; Set current pointer to list start +; +__tx_timer_skip_wrap: +; + STR r0, [r1, #0] ; Store new current timer pointer +; } +; +__tx_timer_done: +; +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of expired flag + LDR r2, [r3, #0] ; Pickup time-slice expired flag + CBNZ r2, __tx_something_expired ; Did a time-slice expire? + ; If non-zero, time-slice expired + MOV32 r1, _tx_timer_expired ; Pickup addr of other expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CBZ r0, __tx_timer_nothing_expired ; Did a timer expire? + ; No, nothing expired +; +__tx_something_expired: +; +; + STMDB sp!, {r0, lr} ; Save the lr register on the stack + ; and save r0 just to keep 8-byte alignment +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + MOV32 r1, _tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CBZ r0, __tx_timer_dont_activate ; Check for timer expiration + ; If not set, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BL _tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate: +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r2, [r3, #0] ; Pickup the actual flag + CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set + ; No, skip time-slice processing +; +; /* Time slice interrupted thread. */ +; _tx_thread_time_slice(); + + BL _tx_thread_time_slice ; Call time-slice processing + MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag + LDR r1, [r0] ; Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice ; Yes, skip the PendSV logic + MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup the current thread pointer + MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address + LDR r3, [r2] ; Pickup the execute thread pointer + MOV32 r0, 0xE000ED04 ; Build address of control register + MOV32 r2, 0x10000000 ; Build value for PendSV bit + CMP r1, r3 ; Are they the same? + BEQ __tx_timer_skip_time_slice ; If the same, there was no time-slice performed + STR r2, [r0] ; Not the same, issue the PendSV for preemption +__tx_timer_skip_time_slice: +; +; } +; +__tx_timer_not_ts_expiration: +; + LDMIA sp!, {r0, lr} ; Recover lr register (r0 is just there for + ; the 8-byte stack alignment +; +; } +; +__tx_timer_nothing_expired: + + DSB ; Complete all memory access + BX lr ; Return to caller +; +;} + END + diff --git a/ports/cortex_m33/iar/src/txe_thread_secure_stack_allocate.c b/ports/cortex_m33/iar/src/txe_thread_secure_stack_allocate.c new file mode 100644 index 00000000..ded0507d --- /dev/null +++ b/ports/cortex_m33/iar/src/txe_thread_secure_stack_allocate.c @@ -0,0 +1,123 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_allocate PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the secure stack allocate */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* stack_size Size of secure stack to */ +/* allocate */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_secure_stack_allocate Actual stack alloc function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +{ +#if defined(TX_SINGLE_MODE_SECURE) || defined(TX_SINGLE_MODE_NON_SECURE) + return(TX_FEATURE_NOT_ENABLED); +#else +UINT status; + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid thread pointer. */ + if (thread_ptr == TX_NULL) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Now check for invalid thread ID. */ + else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Check for interrupt call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + /* Is call from an interrupt and not initialization? */ + if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS) + { + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + + /* Call actual secure stack allocate function. */ + status = _tx_thread_secure_stack_allocate(thread_ptr, stack_size); + } + + /* Return completion status. */ + return(status); +#endif +} + diff --git a/ports/cortex_m33/iar/src/txe_thread_secure_stack_free.c b/ports/cortex_m33/iar/src/txe_thread_secure_stack_free.c new file mode 100644 index 00000000..af49c7df --- /dev/null +++ b/ports/cortex_m33/iar/src/txe_thread_secure_stack_free.c @@ -0,0 +1,121 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_secure_stack_free PORTABLE C */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the secure stack free */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_secure_stack_free Actual stack free function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) +{ +#if defined(TX_SINGLE_MODE_SECURE) || defined(TX_SINGLE_MODE_NON_SECURE) + return(TX_FEATURE_NOT_ENABLED); +#else +UINT status; + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid thread pointer. */ + if (thread_ptr == TX_NULL) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Now check for invalid thread ID. */ + else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Check for interrupt call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + /* Is call from an interrupt and not initialization? */ + if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS) + { + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + + /* Call actual secure stack allocate function. */ + status = _tx_thread_secure_stack_free(thread_ptr); + } + + /* Return completion status. */ + return(status); +#endif +} + diff --git a/ports/cortex_m4/ac6/example_build/sample_threadx/.cproject b/ports/cortex_m4/ac6/example_build/sample_threadx/.cproject new file mode 100644 index 00000000..62738bd0 --- /dev/null +++ b/ports/cortex_m4/ac6/example_build/sample_threadx/.cproject @@ -0,0 +1,238 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_m4/ac6/example_build/sample_threadx/.project b/ports/cortex_m4/ac6/example_build/sample_threadx/.project new file mode 100644 index 00000000..725328bd --- /dev/null +++ b/ports/cortex_m4/ac6/example_build/sample_threadx/.project @@ -0,0 +1,27 @@ + + + sample_threadx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.arm.debug.ds.nature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/ports/cortex_m4/ac6/example_build/sample_threadx/.settings/language.settings.xml b/ports/cortex_m4/ac6/example_build/sample_threadx/.settings/language.settings.xml new file mode 100644 index 00000000..bfa6d9db --- /dev/null +++ b/ports/cortex_m4/ac6/example_build/sample_threadx/.settings/language.settings.xml @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_m4/ac6/example_build/sample_threadx/cortex-m4_tx.launch b/ports/cortex_m4/ac6/example_build/sample_threadx/cortex-m4_tx.launch new file mode 100644 index 00000000..49e82da0 --- /dev/null +++ b/ports/cortex_m4/ac6/example_build/sample_threadx/cortex-m4_tx.launch @@ -0,0 +1,166 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_m4/ac6/example_build/sample_threadx/exceptions.c b/ports/cortex_m4/ac6/example_build/sample_threadx/exceptions.c new file mode 100644 index 00000000..94c87d7a --- /dev/null +++ b/ports/cortex_m4/ac6/example_build/sample_threadx/exceptions.c @@ -0,0 +1,96 @@ +/* +** Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. +** Use, modification and redistribution of this file is subject to your possession of a +** valid End User License Agreement for the Arm Product of which these examples are part of +** and your compliance with all applicable terms and conditions of such licence agreement. +*/ + +/* This file contains the default exception handlers and vector table. +All exceptions are handled in Handler mode. Processor state is automatically +pushed onto the stack when an exception occurs, and popped from the stack at +the end of the handler */ + + +/* Exception Handlers */ +/* Marking as __attribute__((interrupt)) avoids them being accidentally called from elsewhere */ + +__attribute__((interrupt)) void NMIException(void) +{ while(1); } + +__attribute__((interrupt)) void HardFaultException(void) +{ while(1); } + +__attribute__((interrupt)) void MemManageException(void) +{ while(1); } + +__attribute__((interrupt)) void BusFaultException(void) +{ while(1); } + +__attribute__((interrupt)) void UsageFaultException(void) +{ while(1); } + +__attribute__((interrupt)) void DebugMonitor(void) +{ while(1); } + +void __tx_SVCallHandler(void); + +void __tx_PendSVHandler(void); + +void SysTick_Handler(void); + +__attribute__((interrupt)) void InterruptHandler(void) +{ while(1); } + + +/* typedef for the function pointers in the vector table */ +typedef void(* const ExecFuncPtr)(void) __attribute__((interrupt)); + +/* Linker-generated Stack Base address */ +#ifdef TWO_REGION +extern unsigned int Image$$ARM_LIB_STACK$$ZI$$Limit; /* for Two Region model */ +#else +extern unsigned int Image$$ARM_LIB_STACKHEAP$$ZI$$Limit; /* for (default) One Region model */ +#endif + +/* Entry point for C run-time initialization */ +extern int __main(void); + + +/* Vector table +Create a named ELF section for the vector table that can be placed in a scatter file. +The first two entries are: + Initial SP = |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit| for (default) One Region model + or |Image$$ARM_LIB_STACK$$ZI$$Limit| for Two Region model + Initial PC= &__main (with LSB set to indicate Thumb) +*/ + +ExecFuncPtr vector_table[] __attribute__((section("vectors"))) = { + /* Configure Initial Stack Pointer using linker-generated symbol */ +#ifdef TWO_REGION + #pragma import(__use_two_region_memory) + (ExecFuncPtr)&Image$$ARM_LIB_STACK$$ZI$$Limit, +#else /* (default) One Region model */ + (ExecFuncPtr)&Image$$ARM_LIB_STACKHEAP$$ZI$$Limit, +#endif + (ExecFuncPtr)__main, /* Initial PC, set to entry point */ + NMIException, + HardFaultException, + MemManageException, + BusFaultException, + UsageFaultException, + 0, 0, 0, 0, /* Reserved */ + __tx_SVCallHandler, + DebugMonitor, + 0, /* Reserved */ + __tx_PendSVHandler, + SysTick_Handler, + + /* Add up to 240 interrupt handlers, starting here... */ + InterruptHandler, + InterruptHandler, /* Some dummy interrupt handlers */ + InterruptHandler + /* + : + */ +}; + diff --git a/ports/cortex_m4/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_m4/ac6/example_build/sample_threadx/sample_threadx.c new file mode 100644 index 00000000..597f373c --- /dev/null +++ b/ports/cortex_m4/ac6/example_build/sample_threadx/sample_threadx.c @@ -0,0 +1,370 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; +UCHAR memory_area[DEMO_BYTE_POOL_SIZE]; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_m4/ac6/example_build/sample_threadx/sample_threadx.scat b/ports/cortex_m4/ac6/example_build/sample_threadx/sample_threadx.scat new file mode 100644 index 00000000..eb8e0c23 --- /dev/null +++ b/ports/cortex_m4/ac6/example_build/sample_threadx/sample_threadx.scat @@ -0,0 +1,44 @@ +;******************************************************* +; Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. +; Use, modification and redistribution of this file is subject to your possession of a +; valid End User License Agreement for the Arm Product of which these examples are part of +; and your compliance with all applicable terms and conditions of such licence agreement. +;******************************************************* + +; Scatter-file for Cortex-M4 bare-metal example + +; This scatter-file places the vector table, application code, data, stacks and heap at suitable addresses in the memory map. + +; The vector table is placed first at the start of the image. +; Code starts after the last entry in the vector table. +; Data is placed at an address that must correspond to RAM. +; Stack and Heap are placed using ARM_LIB_STACKHEAP, to eliminate the need to set stack-base or heap-base in the debugger. +; System Control Space registers appear at their architecturally-defined addresses, based at 0xE000E000. + + +LOAD_REGION 0x00000000 +{ + VECTORS +0 0xC0 ; 16 exceptions + up to 32 interrupts, 4 bytes each entry == 0xC0 + { + exceptions.o (vectors, +FIRST) ; from exceptions.c + } + + ; Code is placed immediately (+0) after the previous root region + ; (so code region will also be a root region) + CODE +0 + { + * (+RO) ; All program code, including library code + } + + DATA +0 + { + * (+RW, +ZI) ; All RW and ZI data + } + + ; Heap grows upwards from start of this region and + ; Stack grows downwards from end of this region + ; The Main Stack Pointer is initialized on reset to the top addresses of this region + ARM_LIB_STACKHEAP +0 EMPTY 0x1000 + { + } +} diff --git a/ports/cortex_m4/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_m4/ac6/example_build/sample_threadx/tx_initialize_low_level.S new file mode 100644 index 00000000..1c274e81 --- /dev/null +++ b/ports/cortex_m4/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -0,0 +1,240 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Initialize */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_initialize.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global _tx_timer_interrupt + .global __main + .global __tx_SVCallHandler + .global __tx_PendSVHandler + .global __tx_NMIHandler @ NMI + .global __tx_BadHandler @ HardFault + .global __tx_SVCallHandler @ SVCall + .global __tx_DBGHandler @ Monitor + .global __tx_PendSVHandler @ PendSV + .global __tx_SysTickHandler @ SysTick + .global __tx_IntHandler @ Int 0 +@ +@ +SYSTEM_CLOCK = 6000000 +SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) + + .text 32 + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_initialize_low_level Cortex-M4/AC6 */ +@/* 6.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for any low-level processor */ +@/* initialization, including setting up interrupt vectors, setting */ +@/* up a periodic timer interrupt source, saving the system stack */ +@/* pointer for use in ISR processing later, and finding the first */ +@/* available RAM memory address for tx_application_define. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* xx-xx-xxxx William E. Lamie Modified comments, */ +@/* resulting in version 6.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_initialize_low_level(VOID) +@{ + .global _tx_initialize_low_level + .thumb_func +_tx_initialize_low_level: +@ +@ /* Disable interrupts during ThreadX initialization. */ +@ + CPSID i +@ +@ /* Set base of available memory to end of non-initialised RAM area. */ +@ + LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer + LDR r1, =Image$$ARM_LIB_STACKHEAP$$ZI$$Limit @ Build first free address + ADD r1, r1, #4 @ + STR r1, [r0] @ Setup first unused memory pointer +@ +@ /* Setup Vector Table Offset Register. */ +@ + MOV r0, #0xE000E000 @ Build address of NVIC registers + LDR r1, =vector_table @ Pickup address of vector table + STR r1, [r0, #0xD08] @ Set vector table address +@ +@ /* Set system stack pointer from vector value. */ +@ + LDR r0, =_tx_thread_system_stack_ptr @ Build address of system stack pointer + LDR r1, =vector_table @ Pickup address of vector table + LDR r1, [r1] @ Pickup reset stack pointer + STR r1, [r0] @ Save system stack pointer +@ +@ /* Enable the cycle count register. */ +@ + LDR r0, =0xE0001000 @ Build address of DWT register + LDR r1, [r0] @ Pickup the current value + ORR r1, r1, #1 @ Set the CYCCNTENA bit + STR r1, [r0] @ Enable the cycle count register +@ +@ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ +@ + MOV r0, #0xE000E000 @ Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] @ Setup SysTick Reload Value + MOV r1, #0x7 @ Build SysTick Control Enable Value + STR r1, [r0, #0x10] @ Setup SysTick Control +@ +@ /* Configure handler priorities. */ +@ + LDR r1, =0x00000000 @ Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] @ Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 @ SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] @ Setup System Handlers 8-11 Priority Registers + @ Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] @ Setup System Handlers 12-15 Priority Registers + @ Note: PnSV must be lowest priority, which is 0xFF + +@ +@ /* Return to caller. */ +@ + BX lr +@} +@ + +@/* Define shells for each of the unused vectors. */ +@ + .global __tx_BadHandler + .thumb_func +__tx_BadHandler: + B __tx_BadHandler + +@ /* added to catch the hardfault */ + + .global __tx_HardfaultHandler + .thumb_func +__tx_HardfaultHandler: + B __tx_HardfaultHandler + + +@ /* added to catch the SVC */ + + .global __tx_SVCallHandler + .thumb_func +__tx_SVCallHandler: + B __tx_SVCallHandler + + +@ /* Generic interrupt handler template */ + .global __tx_IntHandler + .thumb_func +__tx_IntHandler: +@ VOID InterruptHandler (VOID) +@ { + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter @ Call the ISR enter function +#endif + +@ /* Do interrupt handler work here */ +@ /* BL .... */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif + POP {r0, lr} + BX LR +@ } + +@ /* System Tick timer interrupt handler */ + .global __tx_SysTickHandler + .global SysTick_Handler + .thumb_func +__tx_SysTickHandler: + .thumb_func +SysTick_Handler: +@ VOID TimerInterruptHandler (VOID) +@ { +@ + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter @ Call the ISR enter function +#endif + BL _tx_timer_interrupt +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif + POP {r0, lr} + BX LR +@ } + + +@ /* NMI, DBG handlers */ + .global __tx_NMIHandler + .thumb_func +__tx_NMIHandler: + B __tx_NMIHandler + + .global __tx_DBGHandler + .thumb_func +__tx_DBGHandler: + B __tx_DBGHandler + diff --git a/ports/cortex_m4/ac6/example_build/tx/.cproject b/ports/cortex_m4/ac6/example_build/tx/.cproject new file mode 100644 index 00000000..74e1ad88 --- /dev/null +++ b/ports/cortex_m4/ac6/example_build/tx/.cproject @@ -0,0 +1,212 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_m4/ac6/example_build/tx/.project b/ports/cortex_m4/ac6/example_build/tx/.project new file mode 100644 index 00000000..863ca5cb --- /dev/null +++ b/ports/cortex_m4/ac6/example_build/tx/.project @@ -0,0 +1,48 @@ + + + tx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + inc_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/inc + + + inc_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/inc + + + src_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/src + + + src_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/src + + + diff --git a/ports/cortex_m4/ac6/example_build/tx/.settings/language.settings.xml b/ports/cortex_m4/ac6/example_build/tx/.settings/language.settings.xml new file mode 100644 index 00000000..5340a8e5 --- /dev/null +++ b/ports/cortex_m4/ac6/example_build/tx/.settings/language.settings.xml @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_m4/ac6/inc/tx_port.h b/ports/cortex_m4/ac6/inc/tx_port.h new file mode 100644 index 00000000..98b2adea --- /dev/null +++ b/ports/cortex_m4/ac6/inc/tx_port.h @@ -0,0 +1,499 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-M4/AC6 */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX Cortex-M7 port. */ + +#define TX_INT_DISABLE 1 /* Disable interrupts */ +#define TX_INT_ENABLE 0 /* Enable interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0 + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) + + +#ifdef TX_ENABLE_FPU_SUPPORT + + +#ifdef TX_MISRA_ENABLE + +ULONG _tx_misra_control_get(void); +void _tx_misra_control_set(ULONG value); +ULONG _tx_misra_fpccr_get(void); +void _tx_misra_vfp_touch(void); + +#else + +__attribute__( ( always_inline ) ) static inline ULONG __get_control(void) +{ + +ULONG control_value; + + __asm__ volatile (" MRS %0,CONTROL ": "=r" (control_value) ); + return(control_value); +} + + +__attribute__( ( always_inline ) ) static inline void __set_control(ULONG control_value) +{ + + __asm__ volatile (" MSR CONTROL,%0": : "r" (control_value): "memory" ); +} + + +#endif + + +/* A completed thread falls into _thread_shell_entry and we can simply deactivate the FPU via CONTROL.FPCA + in order to ensure no lazy stacking will occur. */ + +#ifndef TX_MISRA_ENABLE + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_control(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_control(_tx_vfp_state); \ + } +#else + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } + +#endif + + +/* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. + If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + the lazy FPU save, then restore the CONTROL.FPCA state. */ + +#ifndef TX_MISRA_ENABLE + + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_control(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_control(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = *((ULONG *) 0xE000EF34); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_control(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + __asm__ volatile ("vmov.f32 s0, s0"); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = __get_control(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_control(_tx_vfp_state); \ + } \ + } \ + } \ + } +#else + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = _tx_misra_fpccr_get(); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + _tx_misra_vfp_touch(); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + } \ + } \ + } +#endif + +#else + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + +#endif + + + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define the get system state macro. */ + +#ifndef TX_THREAD_GET_SYSTEM_STATE +#ifndef TX_MISRA_ENABLE + +__attribute__( ( always_inline ) ) static inline unsigned int __get_ipsr_value(void) +{ + +unsigned int ipsr_value; + + __asm__ volatile (" MRS %0,IPSR ": "=r" (ipsr_value) ); + return(ipsr_value); +} + + +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | __get_ipsr_value()) +#else +ULONG _tx_misra_ipsr_get(VOID); +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get()) +#endif +#endif + + +/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value + indicates that _tx_thread_system_return should not be called. */ + +#ifndef TX_THREAD_SYSTEM_RETURN_CHECK +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#endif + +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to + prevent early scheduling on Cortex-M parts. */ + +#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; + + +/* This ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + +#endif + + +#ifndef TX_DISABLE_INLINE + +/* Define AC6 specific macros, with in-line assembly for performance. */ + +__attribute__( ( always_inline ) ) static inline unsigned int __disable_interrupts(void) +{ + +unsigned int primask_value; + + __asm__ volatile (" MRS %0,PRIMASK ": "=r" (primask_value) ); + __asm__ volatile (" CPSID i" : : : "memory" ); + return(primask_value); +} + +__attribute__( ( always_inline ) ) static inline void __restore_interrupts(unsigned int primask_value) +{ + + __asm__ volatile (" MSR PRIMASK,%0": : "r" (primask_value): "memory" ); +} + +__attribute__( ( always_inline ) ) static inline unsigned int __get_primask_value(void) +{ + +unsigned int primask_value; + + __asm__ volatile (" MRS %0,PRIMASK ": "=r" (primask_value) ); + return(primask_value); +} + +__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void) +{ + + __asm__ volatile (" CPSIE i": : : "memory" ); +} + + +__attribute__( ( always_inline ) ) static inline void _tx_thread_system_return_inline(void) +{ +unsigned int interrupt_save; + + *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + if (__get_ipsr_value() == 0) + { + interrupt_save = __get_primask_value(); + __enable_interrupts(); + __restore_interrupts(interrupt_save); + } +} + + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = __disable_interrupts(); +#define TX_RESTORE __restore_interrupts(interrupt_save); + + +/* Redefine _tx_thread_system_return for improved performance. */ + +#define _tx_thread_system_return _tx_thread_system_return_inline + + +#else + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); +#define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); +#endif + + +/* Define FPU extension for the Cortex-M4. Each is assumed to be called in the context of the executing + thread. This is for legacy only, and not needed anylonger. */ + +void tx_thread_fpu_enable(void); +void tx_thread_fpu_disable(void); + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/AC6 Version 6.0.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + + + + + diff --git a/ports/cortex_m4/ac6/readme_threadx.txt b/ports/cortex_m4/ac6/readme_threadx.txt new file mode 100644 index 00000000..4df37323 --- /dev/null +++ b/ports/cortex_m4/ac6/readme_threadx.txt @@ -0,0 +1,221 @@ + Microsoft's Azure RTOS ThreadX for Cortex-M4 + + Using the AC6 Tools + +1. Import the ThreadX Projects + +In order to build the ThreadX library and the ThreadX demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +into your DS workspace. + + +2. Building the ThreadX run-time Library + +Building the ThreadX library is easy; simply right-click the Eclipse project +"tx" and then select the "Build Project" button. You should now observe the compilation +and assembly of the ThreadX library. This project build produces the ThreadX +library file tx.a. + + +3. Demonstration System + +The ThreadX demonstration is designed to execute under the DS debugger on the +MPS2_Cortex_M4 Bare Metal simulator. + +Building the demonstration is easy; simply right-click the Eclipse project +"sample_threadx" and then select the "Build Project" button. You should now observe +the compilation and assembly of the ThreadX demonstration. This project build produces +the ThreadX library file sample_threadx.axf. Next, expand the demo ThreadX project folder +in the Project Explorer window, right-click on the 'cortex-m4_tx.launch' file, click +'Debug As', and then click 'cortex-m4_tx' from the submenu. This will cause the +debugger to load the sample_threadx.axf ELF file and run to main. You are now ready +to execute the ThreadX demonstration. + + +4. System Initialization + +The entry point in ThreadX for the Cortex-M4 using AC6 tools uses the standard AC6 +Cortex-M4 reset sequence. From the reset vector the C runtime will be initialized. + +The ThreadX tx_initialize_low_level.S file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. + +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input +parameter to your application definition function, tx_application_define. + + +5. Register Usage and Stack Frames + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have the same stack frame in the Cortex-M4 version of +ThreadX. The top of the suspended thread's stack is pointed to by +tx_thread_stack_ptr in the associated thread control block TX_THREAD. + +Non-FPU Stack Frame: + + Stack Offset Stack Contents + + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 r4 + 0x08 r5 + 0x0C r6 + 0x10 r7 + 0x14 r8 + 0x18 r9 + 0x1C r10 + 0x20 r11 + 0x24 r0 (Hardware stack starts here!!) + 0x28 r1 + 0x2C r2 + 0x30 r3 + 0x34 r12 + 0x38 lr + 0x3C pc + 0x40 xPSR + +FPU Stack Frame (only interrupted thread with FPU enabled): + + Stack Offset Stack Contents + + 0x00 LR Interrupted LR (LR at time of PENDSV) + 0x04 s0 + 0x08 s1 + 0x0C s2 + 0x10 s3 + 0x14 s4 + 0x18 s5 + 0x1C s6 + 0x20 s7 + 0x24 s8 + 0x28 s9 + 0x2C s10 + 0x30 s11 + 0x34 s12 + 0x38 s13 + 0x3C s14 + 0x40 s15 + 0x44 s16 + 0x48 s17 + 0x4C s18 + 0x50 s19 + 0x54 s20 + 0x58 s21 + 0x5C s22 + 0x60 s23 + 0x64 s24 + 0x68 s25 + 0x6C s26 + 0x70 s27 + 0x74 s28 + 0x78 s29 + 0x7C s30 + 0x80 s31 + 0x84 fpscr + 0x88 r4 + 0x8C r5 + 0x90 r6 + 0x94 r7 + 0x98 r8 + 0x9C r9 + 0xA0 r10 (sl) + 0xA4 r11 + 0xA8 r0 (Hardware stack starts here!!) + 0xAC r1 + 0xB0 r2 + 0xB4 r3 + 0xB8 r12 + 0xBC lr + 0xC0 pc + 0xC4 xPSR + + +6. Improving Performance + +The distribution version of ThreadX is built without any compiler optimizations. +This makes it easy to debug because you can trace or set breakpoints inside of +ThreadX itself. Of course, this costs some performance. To make it run faster, +you can change the build_threadx.bat file to remove the -g option and enable +all compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-M4 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +7.1 Vector Area + +The Cortex-M4 vectors start at the label __tx_vectors or similar. The application may modify +the vector area according to its needs. There is code in tx_initialize_low_level() that will +configure the vector base register. + + +7.2 Managed Interrupts + +ISRs can be written completely in C (or assembly language) without any calls to +_tx_thread_context_save or _tx_thread_context_restore. These ISRs are allowed access to the +ThreadX API that is available to ISRs. + +ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table): + +void your_C_isr(void) +{ + + /* ISR processing goes here, including any needed function calls. */ +} + +ISRs written in assembly language will take the form: + + + .global your_assembly_isr + .thumb_func +your_assembly_isr: +; VOID your_assembly_isr(VOID) +; { + PUSH {r0, lr} +; +; /* Do interrupt handler work here */ +; /* BL */ + + POP {r0, lr} + BX lr +; } + +Note: the Cortex-M4 requires exception handlers to be thumb labels, this implies bit 0 set. +To accomplish this, the declaration of the label has to be preceded by the assembler directive +.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to +be inserted in the correct location in the interrupt vector table. This table is typically +located in either your runtime startup file or in the tx_initialize_low_level.S file. + + +8. FPU Support + +ThreadX for Cortex-M4 supports automatic ("lazy") VFP support, which means that applications threads +can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread +context. If saving the context of the FPU registers is needed, the ThreadX library should be re-built +with TX_ENABLE_FPU_SUPPORT defined. + + +9. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M4 using AC6 tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_m4/ac6/src/tx_thread_context_restore.S b/ports/cortex_m4/ac6/src/tx_thread_context_restore.S new file mode 100644 index 00000000..abcda29c --- /dev/null +++ b/ports/cortex_m4/ac6/src/tx_thread_context_restore.S @@ -0,0 +1,95 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_system_stack_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable +@ +@ + .text + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_restore Cortex-M4/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function restores the interrupt context if it is processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs Interrupt Service Routines */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_restore(VOID) +@{ + .global _tx_thread_context_restore + .thumb_func +_tx_thread_context_restore: +@ +@ /* Not needed for this port - just return! */ + BX lr +@} + diff --git a/ports/cortex_m4/ac6/src/tx_thread_context_save.S b/ports/cortex_m4/ac6/src/tx_thread_context_save.S new file mode 100644 index 00000000..c198f6d3 --- /dev/null +++ b/ports/cortex_m4/ac6/src/tx_thread_context_save.S @@ -0,0 +1,88 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr +@ +@ + .text + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_save Cortex-M4/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_save(VOID) +@{ + .global _tx_thread_context_save + .thumb_func +_tx_thread_context_save: +@ +@ /* Not needed for this port - just return! */ + BX lr +@} diff --git a/ports/cortex_m4/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_m4/ac6/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..cc317cf3 --- /dev/null +++ b/ports/cortex_m4/ac6/src/tx_thread_interrupt_control.S @@ -0,0 +1,92 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ + + +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ + +@/* #define TX_SOURCE_CODE */ + + +@/* Include necessary system files. */ + +@/* #include "tx_api.h" + #include "tx_thread.h" */ + + + .text 32 + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_control Cortex-M4/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for changing the interrupt lockout */ +@/* posture of the system. */ +@/* */ +@/* INPUT */ +@/* */ +@/* new_posture New interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@/* UINT _tx_thread_interrupt_control(UINT new_posture) +{ */ + .global _tx_thread_interrupt_control + .thumb_func +_tx_thread_interrupt_control: + +@/* Pickup current interrupt lockout posture. */ + + MRS r1, PRIMASK @ Pickup current interrupt lockout + +@/* Apply the new interrupt posture. */ + + MSR PRIMASK, r0 @ Apply the new interrupt lockout + MOV r0, r1 @ Transfer old to return register + BX lr @ Return to caller + +@/* } */ + + + diff --git a/ports/cortex_m4/ac6/src/tx_thread_schedule.S b/ports/cortex_m4/ac6/src/tx_thread_schedule.S new file mode 100644 index 00000000..b3b78246 --- /dev/null +++ b/ports/cortex_m4/ac6/src/tx_thread_schedule.S @@ -0,0 +1,294 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ + .global _tx_thread_current_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_system_stack_ptr +@ +@ + .text + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_schedule Cortex-M4/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function waits for a thread control block pointer to appear in */ +@/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +@/* in the variable, the corresponding thread is resumed. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* _tx_thread_system_return Return to system from thread */ +@/* _tx_thread_context_restore Restore thread's context */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_schedule(VOID) +@{ + .global _tx_thread_schedule + .thumb_func +_tx_thread_schedule: +@ +@ /* This function should only ever be called on Cortex-M4 +@ from the first schedule request. Subsequent scheduling occurs +@ from the PendSV handling routines below. */ +@ +@ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ +@ + MOV r0, #0 @ Build value for TX_FALSE + LDR r2, =_tx_thread_preempt_disable @ Build address of preempt disable flag + STR r0, [r2, #0] @ Clear preempt disable flag +@ +@ /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */ +@ +#ifdef TX_ENABLE_FPU_SUPPORT + MRS r0, CONTROL @ Pickup current CONTROL register + BIC r0, r0, #4 @ Clear the FPCA bit + MSR CONTROL, r0 @ Setup new CONTROL register +#endif +@ +@ /* Enable interrupts */ +@ + CPSIE i +@ +@ /* Enter the scheduler for the first time. */ +@ + MOV r0, #0x10000000 @ Load PENDSVSET bit + MOV r1, #0xE000E000 @ Load NVIC base + STR r0, [r1, #0xD04] @ Set PENDSVBIT in ICSR + DSB @ Complete all memory accesses + ISB @ Flush pipeline +@ +@ /* Wait here for the PendSV to take place. */ +@ +__tx_wait_here: + B __tx_wait_here @ Wait for the PendSV to happen +@} +@ +@ /* Generic context switch-out switch-in handler... Note that this handler is +@ common for both PendSV and SVCall. */ +@ + .global PendSV_Handler + .global __tx_PendSVHandler + .thumb_func +PendSV_Handler: + .thumb_func +__tx_PendSVHandler: +@ +@ /* Get current thread value and new thread pointer. */ +@ +__tx_ts_handler: + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the thread exit function to indicate the thread is no longer executing. */ +@ + CPSID i @ Disable interrupts + PUSH {r0, lr} @ Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit @ Call the thread exit function + POP {r0, lr} @ Recover LR + CPSIE i @ Enable interrupts +#endif + LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address + LDR r2, =_tx_thread_execute_ptr @ Build execute thread pointer address + MOV r3, #0 @ Build NULL value + LDR r1, [r0] @ Pickup current thread pointer +@ +@ /* Determine if there is a current thread to finish preserving. */ +@ + CBZ r1, __tx_ts_new @ If NULL, skip preservation +@ +@ /* Recover PSP and preserve current thread context. */ +@ + STR r3, [r0] @ Set _tx_thread_current_ptr to NULL + MRS r12, PSP @ Pickup PSP pointer (thread's stack pointer) + STMDB r12!, {r4-r11} @ Save its remaining registers +#ifdef TX_ENABLE_FPU_SUPPORT + TST LR, #0x10 @ Determine if the VFP extended frame is present + BNE _skip_vfp_save + VSTMDB r12!,{s16-s31} @ Yes, save additional VFP registers +_skip_vfp_save: +#endif + LDR r4, =_tx_timer_time_slice @ Build address of time-slice variable + STMDB r12!, {LR} @ Save LR on the stack +@ +@ /* Determine if time-slice is active. If it isn't, skip time handling processing. */ +@ + LDR r5, [r4] @ Pickup current time-slice + STR r12, [r1, #8] @ Save the thread stack pointer + CBZ r5, __tx_ts_new @ If not active, skip processing +@ +@ /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ +@ + STR r5, [r1, #24] @ Save current time-slice +@ +@ /* Clear the global time-slice. */ +@ + STR r3, [r4] @ Clear time-slice +@ +@ +@ /* Executing thread is now completely preserved!!! */ +@ +__tx_ts_new: +@ +@ /* Now we are looking for a new thread to execute! */ +@ + CPSID i @ Disable interrupts + LDR r1, [r2] @ Is there another thread ready to execute? + CBZ r1, __tx_ts_wait @ No, skip to the wait processing +@ +@ /* Yes, another thread is ready for else, make the current thread the new thread. */ +@ + STR r1, [r0] @ Setup the current thread pointer to the new thread + CPSIE i @ Enable interrupts +@ +@ /* Increment the thread run count. */ +@ +__tx_ts_restore: + LDR r7, [r1, #4] @ Pickup the current thread run count + LDR r4, =_tx_timer_time_slice @ Build address of time-slice variable + LDR r5, [r1, #24] @ Pickup thread's current time-slice + ADD r7, r7, #1 @ Increment the thread run count + STR r7, [r1, #4] @ Store the new run count +@ +@ /* Setup global time-slice with thread's current time-slice. */ +@ + STR r5, [r4] @ Setup global time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the thread entry function to indicate the thread is executing. */ +@ + PUSH {r0, r1} @ Save r0/r1 + BL _tx_execution_thread_enter @ Call the thread execution enter function + POP {r0, r1} @ Recover r3 +#endif +@ +@ /* Restore the thread context and PSP. */ +@ + LDR r12, [r1, #8] @ Pickup thread's stack pointer + LDMIA r12!, {LR} @ Pickup LR +#ifdef TX_ENABLE_FPU_SUPPORT + TST LR, #0x10 @ Determine if the VFP extended frame is present + BNE _skip_vfp_restore @ If not, skip VFP restore + VLDMIA r12!, {s16-s31} @ Yes, restore additional VFP registers +_skip_vfp_restore: +#endif + LDMIA r12!, {r4-r11} @ Recover thread's registers + MSR PSP, r12 @ Setup the thread's stack pointer +@ +@ /* Return to thread. */ +@ + BX lr @ Return to thread! +@ +@ /* The following is the idle wait processing... in this case, no threads are ready for execution and the +@ system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +@ are disabled to allow use of WFI for waiting for a thread to arrive. */ +@ +__tx_ts_wait: + CPSID i @ Disable interrupts + LDR r1, [r2] @ Pickup the next thread to execute pointer + STR r1, [r0] @ Store it in the current pointer + CBNZ r1, __tx_ts_ready @ If non-NULL, a new thread is ready! +#ifdef TX_ENABLE_WFI + DSB @ Ensure no outstanding memory transactions + WFI @ Wait for interrupt + ISB @ Ensure pipeline is flushed +#endif + CPSIE i @ Enable interrupts + B __tx_ts_wait @ Loop to continue waiting +@ +@ /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +@ already in the handler! */ +@ +__tx_ts_ready: + MOV r7, #0x08000000 @ Build clear PendSV value + MOV r8, #0xE000E000 @ Build base NVIC address + STR r7, [r8, #0xD04] @ Clear any PendSV +@ +@ /* Re-enable interrupts and restore new thread. */ +@ + CPSIE i @ Enable interrupts + B __tx_ts_restore @ Restore the thread + + +#ifdef TX_ENABLE_FPU_SUPPORT + + .global tx_thread_fpu_enable + .thumb_func +tx_thread_fpu_enable: +@ +@ /* Automatic VPF logic is supported, this function is present only for +@ backward compatibility purposes and therefore simply returns. */ +@ + BX LR @ Return to caller + + .global tx_thread_fpu_disable + .thumb_func +tx_thread_fpu_disable: +@ +@ /* Automatic VPF logic is supported, this function is present only for +@ backward compatibility purposes and therefore simply returns. */ +@ + BX LR @ Return to caller + + +#endif + diff --git a/ports/cortex_m4/ac6/src/tx_thread_stack_build.S b/ports/cortex_m4/ac6/src/tx_thread_stack_build.S new file mode 100644 index 00000000..1f17511c --- /dev/null +++ b/ports/cortex_m4/ac6/src/tx_thread_stack_build.S @@ -0,0 +1,146 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ + .text + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_stack_build Cortex-M4/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function builds a stack frame on the supplied thread's stack. */ +@/* The stack frame results in a fake interrupt return to the supplied */ +@/* function pointer. */ +@/* */ +@/* INPUT */ +@/* */ +@/* thread_ptr Pointer to thread control blk */ +@/* function_ptr Pointer to return function */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_thread_create Create thread service */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +@{ + .global _tx_thread_stack_build + .thumb_func +_tx_thread_stack_build: +@ +@ +@ /* Build a fake interrupt frame. The form of the fake interrupt stack +@ on the Cortex-M4 should look like the following after it is built: +@ +@ Stack Top: +@ LR Interrupted LR (LR at time of PENDSV) +@ r4 Initial value for r4 +@ r5 Initial value for r5 +@ r6 Initial value for r6 +@ r7 Initial value for r7 +@ r8 Initial value for r8 +@ r9 Initial value for r9 +@ r10 Initial value for r10 +@ r11 Initial value for r11 +@ r0 Initial value for r0 (Hardware stack starts here!!) +@ r1 Initial value for r1 +@ r2 Initial value for r2 +@ r3 Initial value for r3 +@ r12 Initial value for r12 +@ lr Initial value for lr +@ pc Initial value for pc +@ xPSR Initial value for xPSR +@ +@ Stack Bottom: (higher memory address) */ +@ + LDR r2, [r0, #16] @ Pickup end of stack area + BIC r2, r2, #0x7 @ Align frame + SUB r2, r2, #68 @ Subtract frame size + LDR r3, =0xFFFFFFFD @ Build initial LR value + STR r3, [r2, #0] @ Save on the stack +@ +@ /* Actually build the stack frame. */ +@ + MOV r3, #0 @ Build initial register value + STR r3, [r2, #4] @ Store initial r4 + STR r3, [r2, #8] @ Store initial r5 + STR r3, [r2, #12] @ Store initial r6 + STR r3, [r2, #16] @ Store initial r7 + STR r3, [r2, #20] @ Store initial r8 + STR r3, [r2, #24] @ Store initial r9 + STR r3, [r2, #28] @ Store initial r10 + STR r3, [r2, #32] @ Store initial r11 +@ +@ /* Hardware stack follows. */ +@ + STR r3, [r2, #36] @ Store initial r0 + STR r3, [r2, #40] @ Store initial r1 + STR r3, [r2, #44] @ Store initial r2 + STR r3, [r2, #48] @ Store initial r3 + STR r3, [r2, #52] @ Store initial r12 + MOV r3, #0xFFFFFFFF @ Poison EXC_RETURN value + STR r3, [r2, #56] @ Store initial lr + STR r1, [r2, #60] @ Store initial pc + MOV r3, #0x01000000 @ Only T-bit need be set + STR r3, [r2, #64] @ Store initial xPSR +@ +@ /* Setup stack pointer. */ +@ thread_ptr -> tx_thread_stack_ptr = r2; +@ + STR r2, [r0, #8] @ Save stack pointer in thread's + @ control block + BX lr @ Return to caller +@} + + diff --git a/ports/cortex_m4/ac6/src/tx_thread_system_return.S b/ports/cortex_m4/ac6/src/tx_thread_system_return.S new file mode 100644 index 00000000..d7e24361 --- /dev/null +++ b/ports/cortex_m4/ac6/src/tx_thread_system_return.S @@ -0,0 +1,98 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@/* #define TX_SOURCE_CODE */ +@ +@ +@/* Include necessary system files. */ +@ +@/* #include "tx_api.h" +@ #include "tx_thread.h" +@ #include "tx_timer.h" */ + + + .text 32 + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_system_return Cortex-M4/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is target processor specific. It is used to transfer */ +@/* control from a thread back to the ThreadX system. Only a */ +@/* minimal context is saved since the compiler assumes temp registers */ +@/* are going to get slicked by a function call anyway. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling loop */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX components */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@/* VOID _tx_thread_system_return(VOID) +@{ */ + .thumb_func + .global _tx_thread_system_return +_tx_thread_system_return: +@ +@ /* Return to real scheduler via PendSV. Note that this routine is often +@ replaced with in-line assembly in tx_port.h to improved performance. */ +@ + MOV r0, #0x10000000 @ Load PENDSVSET bit + MOV r1, #0xE000E000 @ Load NVIC base + STR r0, [r1, #0xD04] @ Set PENDSVBIT in ICSR + MRS r0, IPSR @ Pickup IPSR + CMP r0, #0 @ Is it a thread returning? + BNE _isr_context @ If ISR, skip interrupt enable + MRS r1, PRIMASK @ Thread context returning, pickup PRIMASK + CPSIE i @ Enable interrupts + MSR PRIMASK, r1 @ Restore original interrupt posture +_isr_context: + BX lr @ Return to caller + +@/* } */ + diff --git a/ports/cortex_m4/ac6/src/tx_timer_interrupt.S b/ports/cortex_m4/ac6/src/tx_timer_interrupt.S new file mode 100644 index 00000000..2fbf230b --- /dev/null +++ b/ports/cortex_m4/ac6/src/tx_timer_interrupt.S @@ -0,0 +1,270 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Timer */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_timer.h" +@#include "tx_thread.h" +@ +@ +@Define Assembly language external references... +@ + .global _tx_timer_time_slice + .global _tx_timer_system_clock + .global _tx_timer_current_ptr + .global _tx_timer_list_start + .global _tx_timer_list_end + .global _tx_timer_expired_time_slice + .global _tx_timer_expired + .global _tx_thread_time_slice + .global _tx_timer_expiration_process +@ +@ + .text + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_timer_interrupt Cortex-M4/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function processes the hardware timer interrupt. This */ +@/* processing includes incrementing the system clock and checking for */ +@/* time slice and/or timer expiration. If either is found, the */ +@/* interrupt context save/restore functions are called along with the */ +@/* expiration functions. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_timer_expiration_process Timer expiration processing */ +@/* _tx_thread_time_slice Time slice interrupted thread */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* interrupt vector */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_timer_interrupt(VOID) +@{ + .global _tx_timer_interrupt + .thumb_func +_tx_timer_interrupt: +@ +@ /* Upon entry to this routine, it is assumed that context save has already +@ been called, and therefore the compiler scratch registers are available +@ for use. */ +@ +@ /* Increment the system clock. */ +@ _tx_timer_system_clock++; +@ + LDR r1, =_tx_timer_system_clock @ Pickup address of system clock + LDR r0, [r1, #0] @ Pickup system clock + ADD r0, r0, #1 @ Increment system clock + STR r0, [r1, #0] @ Store new system clock +@ +@ /* Test for time-slice expiration. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice + LDR r2, [r3, #0] @ Pickup time-slice + CMP r2, #0 @ Is it non-active? + BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing +@ +@ /* Decrement the time_slice. */ +@ _tx_timer_time_slice--; +@ + SUB r2, r2, #1 @ Decrement the time-slice + STR r2, [r3, #0] @ Store new time-slice value +@ +@ /* Check for expiration. */ +@ if (__tx_timer_time_slice == 0) +@ + CMP r2, #0 @ Has it expired? + BNE __tx_timer_no_time_slice @ No, skip expiration processing +@ +@ /* Set the time-slice expired flag. */ +@ _tx_timer_expired_time_slice = TX_TRUE; +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of expired flag + MOV r0, #1 @ Build expired value + STR r0, [r3, #0] @ Set time-slice expiration flag +@ +@ } +@ +__tx_timer_no_time_slice: +@ +@ /* Test for timer expiration. */ +@ if (*_tx_timer_current_ptr) +@ { +@ + LDR r1, =_tx_timer_current_ptr @ Pickup current timer pointer address + LDR r0, [r1, #0] @ Pickup current timer + LDR r2, [r0, #0] @ Pickup timer list entry + CMP r2, #0 @ Is there anything in the list? + BEQ __tx_timer_no_timer @ No, just increment the timer +@ +@ /* Set expiration flag. */ +@ _tx_timer_expired = TX_TRUE; +@ + LDR r3, =_tx_timer_expired @ Pickup expiration flag address + MOV r2, #1 @ Build expired value + STR r2, [r3, #0] @ Set expired flag + B __tx_timer_done @ Finished timer processing +@ +@ } +@ else +@ { +__tx_timer_no_timer: +@ +@ /* No timer expired, increment the timer pointer. */ +@ _tx_timer_current_ptr++; +@ + ADD r0, r0, #4 @ Move to next timer +@ +@ /* Check for wrap-around. */ +@ if (_tx_timer_current_ptr == _tx_timer_list_end) +@ + LDR r3, =_tx_timer_list_end @ Pickup addr of timer list end + LDR r2, [r3, #0] @ Pickup list end + CMP r0, r2 @ Are we at list end? + BNE __tx_timer_skip_wrap @ No, skip wrap-around logic +@ +@ /* Wrap to beginning of list. */ +@ _tx_timer_current_ptr = _tx_timer_list_start; +@ + LDR r3, =_tx_timer_list_start @ Pickup addr of timer list start + LDR r0, [r3, #0] @ Set current pointer to list start +@ +__tx_timer_skip_wrap: +@ + STR r0, [r1, #0] @ Store new current timer pointer +@ } +@ +__tx_timer_done: +@ +@ +@ /* See if anything has expired. */ +@ if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +@ { +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of expired flag + LDR r2, [r3, #0] @ Pickup time-slice expired flag + CMP r2, #0 @ Did a time-slice expire? + BNE __tx_something_expired @ If non-zero, time-slice expired + LDR r1, =_tx_timer_expired @ Pickup addr of other expired flag + LDR r0, [r1, #0] @ Pickup timer expired flag + CMP r0, #0 @ Did a timer expire? + BEQ __tx_timer_nothing_expired @ No, nothing expired +@ +__tx_something_expired: +@ +@ + STMDB sp!, {r0, lr} @ Save the lr register on the stack + @ and save r0 just to keep 8-byte alignment +@ +@ /* Did a timer expire? */ +@ if (_tx_timer_expired) +@ { +@ + LDR r1, =_tx_timer_expired @ Pickup addr of expired flag + LDR r0, [r1, #0] @ Pickup timer expired flag + CMP r0, #0 @ Check for timer expiration + BEQ __tx_timer_dont_activate @ If not set, skip timer activation +@ +@ /* Process timer expiration. */ +@ _tx_timer_expiration_process(); +@ + BL _tx_timer_expiration_process @ Call the timer expiration handling routine +@ +@ } +__tx_timer_dont_activate: +@ +@ /* Did time slice expire? */ +@ if (_tx_timer_expired_time_slice) +@ { +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired + LDR r2, [r3, #0] @ Pickup the actual flag + CMP r2, #0 @ See if the flag is set + BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing +@ +@ /* Time slice interrupted thread. */ +@ _tx_thread_time_slice(); +@ + BL _tx_thread_time_slice @ Call time-slice processing + LDR r0, =_tx_thread_preempt_disable @ Build address of preempt disable flag + LDR r1, [r0] @ Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice @ Yes, skip the PendSV logic + LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address + LDR r1, [r0] @ Pickup the current thread pointer + LDR r2, =_tx_thread_execute_ptr @ Build execute thread pointer address + LDR r3, [r2] @ Pickup the execute thread pointer + LDR r0, =0xE000ED04 @ Build address of control register + LDR r2, =0x10000000 @ Build value for PendSV bit + CMP r1, r3 @ Are they the same? + BEQ __tx_timer_skip_time_slice @ If the same, there was no time-slice performed + STR r2, [r0] @ Not the same, issue the PendSV for preemption +__tx_timer_skip_time_slice: +@ +@ } +@ +__tx_timer_not_ts_expiration: +@ + LDMIA sp!, {r0, lr} @ Recover lr register (r0 is just there for + @ the 8-byte stack alignment +@ +@ } +@ +__tx_timer_nothing_expired: + + DSB @ Complete all memory access + BX lr @ Return to caller +@ +@} + + diff --git a/ports/cortex_m7/ac6/example_build/sample_threadx/.cproject b/ports/cortex_m7/ac6/example_build/sample_threadx/.cproject new file mode 100644 index 00000000..62738bd0 --- /dev/null +++ b/ports/cortex_m7/ac6/example_build/sample_threadx/.cproject @@ -0,0 +1,238 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_m7/ac6/example_build/sample_threadx/.project b/ports/cortex_m7/ac6/example_build/sample_threadx/.project new file mode 100644 index 00000000..725328bd --- /dev/null +++ b/ports/cortex_m7/ac6/example_build/sample_threadx/.project @@ -0,0 +1,27 @@ + + + sample_threadx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.arm.debug.ds.nature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/ports/cortex_m7/ac6/example_build/sample_threadx/.settings/language.settings.xml b/ports/cortex_m7/ac6/example_build/sample_threadx/.settings/language.settings.xml new file mode 100644 index 00000000..3bf3f2cd --- /dev/null +++ b/ports/cortex_m7/ac6/example_build/sample_threadx/.settings/language.settings.xml @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_m7/ac6/example_build/sample_threadx/cortex-m7_tx.launch b/ports/cortex_m7/ac6/example_build/sample_threadx/cortex-m7_tx.launch new file mode 100644 index 00000000..d93daba1 --- /dev/null +++ b/ports/cortex_m7/ac6/example_build/sample_threadx/cortex-m7_tx.launch @@ -0,0 +1,164 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_m7/ac6/example_build/sample_threadx/exceptions.c b/ports/cortex_m7/ac6/example_build/sample_threadx/exceptions.c new file mode 100644 index 00000000..94c87d7a --- /dev/null +++ b/ports/cortex_m7/ac6/example_build/sample_threadx/exceptions.c @@ -0,0 +1,96 @@ +/* +** Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. +** Use, modification and redistribution of this file is subject to your possession of a +** valid End User License Agreement for the Arm Product of which these examples are part of +** and your compliance with all applicable terms and conditions of such licence agreement. +*/ + +/* This file contains the default exception handlers and vector table. +All exceptions are handled in Handler mode. Processor state is automatically +pushed onto the stack when an exception occurs, and popped from the stack at +the end of the handler */ + + +/* Exception Handlers */ +/* Marking as __attribute__((interrupt)) avoids them being accidentally called from elsewhere */ + +__attribute__((interrupt)) void NMIException(void) +{ while(1); } + +__attribute__((interrupt)) void HardFaultException(void) +{ while(1); } + +__attribute__((interrupt)) void MemManageException(void) +{ while(1); } + +__attribute__((interrupt)) void BusFaultException(void) +{ while(1); } + +__attribute__((interrupt)) void UsageFaultException(void) +{ while(1); } + +__attribute__((interrupt)) void DebugMonitor(void) +{ while(1); } + +void __tx_SVCallHandler(void); + +void __tx_PendSVHandler(void); + +void SysTick_Handler(void); + +__attribute__((interrupt)) void InterruptHandler(void) +{ while(1); } + + +/* typedef for the function pointers in the vector table */ +typedef void(* const ExecFuncPtr)(void) __attribute__((interrupt)); + +/* Linker-generated Stack Base address */ +#ifdef TWO_REGION +extern unsigned int Image$$ARM_LIB_STACK$$ZI$$Limit; /* for Two Region model */ +#else +extern unsigned int Image$$ARM_LIB_STACKHEAP$$ZI$$Limit; /* for (default) One Region model */ +#endif + +/* Entry point for C run-time initialization */ +extern int __main(void); + + +/* Vector table +Create a named ELF section for the vector table that can be placed in a scatter file. +The first two entries are: + Initial SP = |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit| for (default) One Region model + or |Image$$ARM_LIB_STACK$$ZI$$Limit| for Two Region model + Initial PC= &__main (with LSB set to indicate Thumb) +*/ + +ExecFuncPtr vector_table[] __attribute__((section("vectors"))) = { + /* Configure Initial Stack Pointer using linker-generated symbol */ +#ifdef TWO_REGION + #pragma import(__use_two_region_memory) + (ExecFuncPtr)&Image$$ARM_LIB_STACK$$ZI$$Limit, +#else /* (default) One Region model */ + (ExecFuncPtr)&Image$$ARM_LIB_STACKHEAP$$ZI$$Limit, +#endif + (ExecFuncPtr)__main, /* Initial PC, set to entry point */ + NMIException, + HardFaultException, + MemManageException, + BusFaultException, + UsageFaultException, + 0, 0, 0, 0, /* Reserved */ + __tx_SVCallHandler, + DebugMonitor, + 0, /* Reserved */ + __tx_PendSVHandler, + SysTick_Handler, + + /* Add up to 240 interrupt handlers, starting here... */ + InterruptHandler, + InterruptHandler, /* Some dummy interrupt handlers */ + InterruptHandler + /* + : + */ +}; + diff --git a/ports/cortex_m7/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_m7/ac6/example_build/sample_threadx/sample_threadx.c new file mode 100644 index 00000000..597f373c --- /dev/null +++ b/ports/cortex_m7/ac6/example_build/sample_threadx/sample_threadx.c @@ -0,0 +1,370 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; +UCHAR memory_area[DEMO_BYTE_POOL_SIZE]; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_m7/ac6/example_build/sample_threadx/sample_threadx.scat b/ports/cortex_m7/ac6/example_build/sample_threadx/sample_threadx.scat new file mode 100644 index 00000000..8b4bb5bd --- /dev/null +++ b/ports/cortex_m7/ac6/example_build/sample_threadx/sample_threadx.scat @@ -0,0 +1,44 @@ +;******************************************************* +; Copyright (c) 2006-2017 Arm Limited (or its affiliates). All rights reserved. +; Use, modification and redistribution of this file is subject to your possession of a +; valid End User License Agreement for the Arm Product of which these examples are part of +; and your compliance with all applicable terms and conditions of such licence agreement. +;******************************************************* + +; Scatter-file for Cortex-M7 bare-metal example + +; This scatter-file places the vector table, application code, data, stacks and heap at suitable addresses in the memory map. + +; The vector table is placed first at the start of the image. +; Code starts after the last entry in the vector table. +; Data is placed at an address that must correspond to RAM. +; Stack and Heap are placed using ARM_LIB_STACKHEAP, to eliminate the need to set stack-base or heap-base in the debugger. +; System Control Space registers appear at their architecturally-defined addresses, based at 0xE000E000. + + +LOAD_REGION 0x00000000 +{ + VECTORS +0 0xC0 ; 16 exceptions + up to 32 interrupts, 4 bytes each entry == 0xC0 + { + exceptions.o (vectors, +FIRST) ; from exceptions.c + } + + ; Code is placed immediately (+0) after the previous root region + ; (so code region will also be a root region) + CODE +0 + { + * (+RO) ; All program code, including library code + } + + DATA +0 + { + * (+RW, +ZI) ; All RW and ZI data + } + + ; Heap grows upwards from start of this region and + ; Stack grows downwards from end of this region + ; The Main Stack Pointer is initialized on reset to the top addresses of this region + ARM_LIB_STACKHEAP +0 EMPTY 0x1000 + { + } +} diff --git a/ports/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S new file mode 100644 index 00000000..12bed311 --- /dev/null +++ b/ports/cortex_m7/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -0,0 +1,237 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Initialize */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_initialize.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global _tx_timer_interrupt + .global __main + .global __tx_SVCallHandler + .global __tx_PendSVHandler + .global __tx_NMIHandler @ NMI + .global __tx_BadHandler @ HardFault + .global __tx_SVCallHandler @ SVCall + .global __tx_DBGHandler @ Monitor + .global __tx_PendSVHandler @ PendSV + .global __tx_SysTickHandler @ SysTick + .global __tx_IntHandler @ Int 0 +@ +@ +SYSTEM_CLOCK = 6000000 +SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) + + .text 32 + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_initialize_low_level Cortex-M7/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for any low-level processor */ +@/* initialization, including setting up interrupt vectors, setting */ +@/* up a periodic timer interrupt source, saving the system stack */ +@/* pointer for use in ISR processing later, and finding the first */ +@/* available RAM memory address for tx_application_define. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_initialize_low_level(VOID) +@{ + .global _tx_initialize_low_level + .thumb_func +_tx_initialize_low_level: +@ +@ /* Disable interrupts during ThreadX initialization. */ +@ + CPSID i +@ +@ /* Set base of available memory to end of non-initialised RAM area. */ +@ + LDR r0, =_tx_initialize_unused_memory @ Build address of unused memory pointer + LDR r1, =Image$$ARM_LIB_STACKHEAP$$ZI$$Limit @ Build first free address + ADD r1, r1, #4 @ + STR r1, [r0] @ Setup first unused memory pointer +@ +@ /* Setup Vector Table Offset Register. */ +@ + MOV r0, #0xE000E000 @ Build address of NVIC registers + LDR r1, =vector_table @ Pickup address of vector table + STR r1, [r0, #0xD08] @ Set vector table address +@ +@ /* Set system stack pointer from vector value. */ +@ + LDR r0, =_tx_thread_system_stack_ptr @ Build address of system stack pointer + LDR r1, =vector_table @ Pickup address of vector table + LDR r1, [r1] @ Pickup reset stack pointer + STR r1, [r0] @ Save system stack pointer +@ +@ /* Enable the cycle count register. */ +@ + LDR r0, =0xE0001000 @ Build address of DWT register + LDR r1, [r0] @ Pickup the current value + ORR r1, r1, #1 @ Set the CYCCNTENA bit + STR r1, [r0] @ Enable the cycle count register +@ +@ /* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */ +@ + MOV r0, #0xE000E000 @ Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] @ Setup SysTick Reload Value + MOV r1, #0x7 @ Build SysTick Control Enable Value + STR r1, [r0, #0x10] @ Setup SysTick Control +@ +@ /* Configure handler priorities. */ +@ + LDR r1, =0x00000000 @ Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] @ Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 @ SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] @ Setup System Handlers 8-11 Priority Registers + @ Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 @ SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] @ Setup System Handlers 12-15 Priority Registers + @ Note: PnSV must be lowest priority, which is 0xFF + +@ +@ /* Return to caller. */ +@ + BX lr +@} +@ + +@/* Define shells for each of the unused vectors. */ +@ + .global __tx_BadHandler + .thumb_func +__tx_BadHandler: + B __tx_BadHandler + +@ /* added to catch the hardfault */ + + .global __tx_HardfaultHandler + .thumb_func +__tx_HardfaultHandler: + B __tx_HardfaultHandler + + +@ /* added to catch the SVC */ + + .global __tx_SVCallHandler + .thumb_func +__tx_SVCallHandler: + B __tx_SVCallHandler + + +@ /* Generic interrupt handler template */ + .global __tx_IntHandler + .thumb_func +__tx_IntHandler: +@ VOID InterruptHandler (VOID) +@ { + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter @ Call the ISR enter function +#endif + +@ /* Do interrupt handler work here */ +@ /* BL .... */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif + POP {r0, lr} + BX LR +@ } + +@ /* System Tick timer interrupt handler */ + .global __tx_SysTickHandler + .global SysTick_Handler + .thumb_func +__tx_SysTickHandler: + .thumb_func +SysTick_Handler: +@ VOID TimerInterruptHandler (VOID) +@ { +@ + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter @ Call the ISR enter function +#endif + BL _tx_timer_interrupt +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif + POP {r0, lr} + BX LR +@ } + + +@ /* NMI, DBG handlers */ + .global __tx_NMIHandler + .thumb_func +__tx_NMIHandler: + B __tx_NMIHandler + + .global __tx_DBGHandler + .thumb_func +__tx_DBGHandler: + B __tx_DBGHandler diff --git a/ports/cortex_m7/ac6/example_build/tx/.cproject b/ports/cortex_m7/ac6/example_build/tx/.cproject new file mode 100644 index 00000000..f419b776 --- /dev/null +++ b/ports/cortex_m7/ac6/example_build/tx/.cproject @@ -0,0 +1,212 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_m7/ac6/example_build/tx/.project b/ports/cortex_m7/ac6/example_build/tx/.project new file mode 100644 index 00000000..863ca5cb --- /dev/null +++ b/ports/cortex_m7/ac6/example_build/tx/.project @@ -0,0 +1,48 @@ + + + tx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + inc_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/inc + + + inc_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/inc + + + src_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/src + + + src_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/src + + + diff --git a/ports/cortex_m7/ac6/example_build/tx/.settings/language.settings.xml b/ports/cortex_m7/ac6/example_build/tx/.settings/language.settings.xml new file mode 100644 index 00000000..455e31e2 --- /dev/null +++ b/ports/cortex_m7/ac6/example_build/tx/.settings/language.settings.xml @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_m7/ac6/inc/tx_port.h b/ports/cortex_m7/ac6/inc/tx_port.h new file mode 100644 index 00000000..129c26fe --- /dev/null +++ b/ports/cortex_m7/ac6/inc/tx_port.h @@ -0,0 +1,496 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-M7/AC6 */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX Cortex-M7 port. */ + +#define TX_INT_DISABLE 1 /* Disable interrupts */ +#define TX_INT_ENABLE 0 /* Enable interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0 + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) + +#ifdef TX_ENABLE_FPU_SUPPORT + + +#ifdef TX_MISRA_ENABLE + +ULONG _tx_misra_control_get(void); +void _tx_misra_control_set(ULONG value); +ULONG _tx_misra_fpccr_get(void); +void _tx_misra_vfp_touch(void); + +#else + +__attribute__( ( always_inline ) ) static inline ULONG __get_control(void) +{ + +ULONG control_value; + + __asm__ volatile (" MRS %0,CONTROL ": "=r" (control_value) ); + return(control_value); +} + + +__attribute__( ( always_inline ) ) static inline void __set_control(ULONG control_value) +{ + + __asm__ volatile (" MSR CONTROL,%0": : "r" (control_value): "memory" ); +} + + +#endif + + +/* A completed thread falls into _thread_shell_entry and we can simply deactivate the FPU via CONTROL.FPCA + in order to ensure no lazy stacking will occur. */ + +#ifndef TX_MISRA_ENABLE + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_control(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_control(_tx_vfp_state); \ + } +#else + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } + +#endif + + +/* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. + If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + the lazy FPU save, then restore the CONTROL.FPCA state. */ + +#ifndef TX_MISRA_ENABLE + + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_control(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_control(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = *((ULONG *) 0xE000EF34); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_control(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + __asm__ volatile ("vmov.f32 s0, s0"); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = __get_control(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_control(_tx_vfp_state); \ + } \ + } \ + } \ + } +#else + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = _tx_misra_fpccr_get(); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + _tx_misra_vfp_touch(); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + } \ + } \ + } +#endif + +#else + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + +#endif + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define the get system state macro. */ + +#ifndef TX_THREAD_GET_SYSTEM_STATE +#ifndef TX_MISRA_ENABLE + +__attribute__( ( always_inline ) ) static inline unsigned int __get_ipsr_value(void) +{ + +unsigned int ipsr_value; + + __asm__ volatile (" MRS %0,IPSR ": "=r" (ipsr_value) ); + return(ipsr_value); +} + + +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | __get_ipsr_value()) +#else +ULONG _tx_misra_ipsr_get(VOID); +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get()) +#endif +#endif + + +/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value + indicates that _tx_thread_system_return should not be called. */ + +#ifndef TX_THREAD_SYSTEM_RETURN_CHECK +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#endif + +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to + prevent early scheduling on Cortex-M parts. */ + +#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; + + +/* This ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); + +#endif + + +#ifndef TX_DISABLE_INLINE + +/* Define AC6 specific macros, with in-line assembly for performance. */ + +__attribute__( ( always_inline ) ) static inline unsigned int __disable_interrupts(void) +{ + +unsigned int primask_value; + + __asm__ volatile (" MRS %0,PRIMASK ": "=r" (primask_value) ); + __asm__ volatile (" CPSID i" : : : "memory" ); + return(primask_value); +} + +__attribute__( ( always_inline ) ) static inline void __restore_interrupts(unsigned int primask_value) +{ + + __asm__ volatile (" MSR PRIMASK,%0": : "r" (primask_value): "memory" ); +} + +__attribute__( ( always_inline ) ) static inline unsigned int __get_primask_value(void) +{ + +unsigned int primask_value; + + __asm__ volatile (" MRS %0,PRIMASK ": "=r" (primask_value) ); + return(primask_value); +} + +__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void) +{ + + __asm__ volatile (" CPSIE i": : : "memory" ); +} + + +__attribute__( ( always_inline ) ) static inline void _tx_thread_system_return_inline(void) +{ +unsigned int interrupt_save; + + *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + if (__get_ipsr_value() == 0) + { + interrupt_save = __get_primask_value(); + __enable_interrupts(); + __restore_interrupts(interrupt_save); + } +} + + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = __disable_interrupts(); +#define TX_RESTORE __restore_interrupts(interrupt_save); + + +/* Redefine _tx_thread_system_return for improved performance. */ + +#define _tx_thread_system_return _tx_thread_system_return_inline + + +#else + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); +#define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); +#endif + + +/* Define FPU extension for the Cortex-M7. Each is assumed to be called in the context of the executing + thread. This is for legacy only, and not needed any longer. */ + +void tx_thread_fpu_enable(void); +void tx_thread_fpu_disable(void); + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/AC6 Version 6.0.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + + + + + diff --git a/ports/cortex_m7/ac6/readme_threadx.txt b/ports/cortex_m7/ac6/readme_threadx.txt new file mode 100644 index 00000000..262b51e9 --- /dev/null +++ b/ports/cortex_m7/ac6/readme_threadx.txt @@ -0,0 +1,154 @@ + Microsoft's Azure RTOS ThreadX for Cortex-M7 + + Using the AC6 Tools + +1. Import the ThreadX Projects + +In order to build the ThreadX library and the ThreadX demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +into your DS workspace. + + +2. Building the ThreadX run-time Library + +Building the ThreadX library is easy; simply right-click the Eclipse project +"tx" and then select the "Build Project" button. You should now observe the compilation +and assembly of the ThreadX library. This project build produces the ThreadX +library file tx.a. + + +3. Demonstration System + +The ThreadX demonstration is designed to execute under the DS debugger on the +MPS2_Cortex_M7 Bare Metal simulator. + +Building the demonstration is easy; simply right-click the Eclipse project +"sample_threadx" and then select the "Build Project" button. You should now observe +the compilation and assembly of the ThreadX demonstration. This project build produces +the ThreadX library file sample_threadx.axf. Next, expand the demo ThreadX project folder +in the Project Explorer window, right-click on the 'cortex-m7_tx.launch' file, click +'Debug As', and then click 'cortex-m7_tx' from the submenu. This will cause the +debugger to load the sample_threadx.axf ELF file and run to main. You are now ready +to execute the ThreadX demonstration. + + +4. System Initialization + +The entry point in ThreadX for the Cortex-M7 using gnu tools uses the standard GNU +Cortex-M7 reset sequence. From the reset vector the C runtime will be initialized. + +The ThreadX tx_initialize_low_level.S file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. + +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input +parameter to your application definition function, tx_application_define. + + +5. Register Usage and Stack Frames + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have the same stack frame in the Cortex-M7 version of +ThreadX. The top of the suspended thread's stack is pointed to by +tx_thread_stack_ptr in the associated thread control block TX_THREAD. + + + Stack Offset Stack Contents + + 0x00 r4 + 0x04 r5 + 0x08 r6 + 0x0C r7 + 0x10 r8 + 0x14 r9 + 0x18 r10 + 0x1C r11 + 0x20 r0 (Hardware stack starts here!!) + 0x24 r1 + 0x28 r2 + 0x2C r3 + 0x30 r12 + 0x34 lr + 0x38 pc + 0x3C xPSR + + +6. Improving Performance + +The distribution version of ThreadX is built without any compiler optimizations. +This makes it easy to debug because you can trace or set breakpoints inside of +ThreadX itself. Of course, this costs some performance. To make it run faster, +you can change the build_threadx.bat file to remove the -g option and enable +all compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-M7 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +7.1 Vector Area + +The Cortex-M7 vectors start at the label __tx_vectors or similar. The application may modify +the vector area according to its needs. There is code in tx_initialize_low_level() that will +configure the vector base register. + + +7.2 Managed Interrupts + +A ThreadX managed interrupt is defined below. By following these conventions, the +application ISR is then allowed access to various ThreadX services from the ISR. +Here is the standard template for managed ISRs in ThreadX: + + + .global __tx_IntHandler + .thumb_func +__tx_IntHandler: +; VOID InterruptHandler (VOID) +; { + PUSH {r0, lr} + +; /* Do interrupt handler work here */ +; /* BL */ + + POP {r0, lr} + BX lr +; } + + +Note: the Cortex-M7 requires exception handlers to be thumb labels, this implies bit 0 set. +To accomplish this, the declaration of the label has to be preceded by the assembler directive +.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to +be inserted in the correct location in the interrupt vector table. This table is typically +located in either your runtime startup file or in the tx_initialize_low_level.S file. + + +8. FPU Support + +ThreadX for Cortex-M7 supports automatic ("lazy") VFP support, which means that applications threads +can simply use the VFP and ThreadX automatically maintains the VFP registers as part of the thread +context - no additional setup by the application. + + +9. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX 6.0.1 version for Cortex-M7 using AC6 tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_m7/ac6/src/tx_thread_context_restore.S b/ports/cortex_m7/ac6/src/tx_thread_context_restore.S new file mode 100644 index 00000000..e50e4d1e --- /dev/null +++ b/ports/cortex_m7/ac6/src/tx_thread_context_restore.S @@ -0,0 +1,95 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_system_stack_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable +@ +@ + .text + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_restore Cortex-M7/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function restores the interrupt context if it is processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs Interrupt Service Routines */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_restore(VOID) +@{ + .global _tx_thread_context_restore + .thumb_func +_tx_thread_context_restore: +@ +@ /* Not needed for this port - just return! */ + BX lr +@} + diff --git a/ports/cortex_m7/ac6/src/tx_thread_context_save.S b/ports/cortex_m7/ac6/src/tx_thread_context_save.S new file mode 100644 index 00000000..3f25a5eb --- /dev/null +++ b/ports/cortex_m7/ac6/src/tx_thread_context_save.S @@ -0,0 +1,88 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr +@ +@ + .text + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_save Cortex-M7/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_save(VOID) +@{ + .global _tx_thread_context_save + .thumb_func +_tx_thread_context_save: +@ +@ /* Not needed for this port - just return! */ + BX lr +@} diff --git a/ports/cortex_m7/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_m7/ac6/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..fc7d8741 --- /dev/null +++ b/ports/cortex_m7/ac6/src/tx_thread_interrupt_control.S @@ -0,0 +1,92 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ + + +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ + +@/* #define TX_SOURCE_CODE */ + + +@/* Include necessary system files. */ + +@/* #include "tx_api.h" + #include "tx_thread.h" */ + + + .text 32 + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_control Cortex-M7/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for changing the interrupt lockout */ +@/* posture of the system. */ +@/* */ +@/* INPUT */ +@/* */ +@/* new_posture New interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@/* UINT _tx_thread_interrupt_control(UINT new_posture) +{ */ + .global _tx_thread_interrupt_control + .thumb_func +_tx_thread_interrupt_control: + +@/* Pickup current interrupt lockout posture. */ + + MRS r1, PRIMASK @ Pickup current interrupt lockout + +@/* Apply the new interrupt posture. */ + + MSR PRIMASK, r0 @ Apply the new interrupt lockout + MOV r0, r1 @ Transfer old to return register + BX lr @ Return to caller + +@/* } */ + + + diff --git a/ports/cortex_m7/ac6/src/tx_thread_schedule.S b/ports/cortex_m7/ac6/src/tx_thread_schedule.S new file mode 100644 index 00000000..c905067b --- /dev/null +++ b/ports/cortex_m7/ac6/src/tx_thread_schedule.S @@ -0,0 +1,294 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ + .global _tx_thread_current_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_system_stack_ptr +@ +@ + .text + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_schedule Cortex-M7/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function waits for a thread control block pointer to appear in */ +@/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +@/* in the variable, the corresponding thread is resumed. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* _tx_thread_system_return Return to system from thread */ +@/* _tx_thread_context_restore Restore thread's context */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_schedule(VOID) +@{ + .global _tx_thread_schedule + .thumb_func +_tx_thread_schedule: +@ +@ /* This function should only ever be called on Cortex-M7 +@ from the first schedule request. Subsequent scheduling occurs +@ from the PendSV handling routines below. */ +@ +@ /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ +@ + MOV r0, #0 @ Build value for TX_FALSE + LDR r2, =_tx_thread_preempt_disable @ Build address of preempt disable flag + STR r0, [r2, #0] @ Clear preempt disable flag +@ +@ /* Clear CONTROL.FPCA bit so VFP registers aren't unnecessarily stacked. */ +@ +#ifdef TX_ENABLE_FPU_SUPPORT + MRS r0, CONTROL @ Pickup current CONTROL register + BIC r0, r0, #4 @ Clear the FPCA bit + MSR CONTROL, r0 @ Setup new CONTROL register +#endif +@ +@ /* Enable interrupts */ +@ + CPSIE i +@ +@ /* Enter the scheduler for the first time. */ +@ + MOV r0, #0x10000000 @ Load PENDSVSET bit + MOV r1, #0xE000E000 @ Load NVIC base + STR r0, [r1, #0xD04] @ Set PENDSVBIT in ICSR + DSB @ Complete all memory accesses + ISB @ Flush pipeline +@ +@ /* Wait here for the PendSV to take place. */ +@ +__tx_wait_here: + B __tx_wait_here @ Wait for the PendSV to happen +@} +@ +@ /* Generic context switch-out switch-in handler... Note that this handler is +@ common for both PendSV and SVCall. */ +@ + .global PendSV_Handler + .global __tx_PendSVHandler + .thumb_func +PendSV_Handler: + .thumb_func +__tx_PendSVHandler: +@ +@ /* Get current thread value and new thread pointer. */ +@ +__tx_ts_handler: + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the thread exit function to indicate the thread is no longer executing. */ +@ + CPSID i @ Disable interrupts + PUSH {r0, lr} @ Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit @ Call the thread exit function + POP {r0, lr} @ Recover LR + CPSIE i @ Enable interrupts +#endif + LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address + LDR r2, =_tx_thread_execute_ptr @ Build execute thread pointer address + MOV r3, #0 @ Build NULL value + LDR r1, [r0] @ Pickup current thread pointer +@ +@ /* Determine if there is a current thread to finish preserving. */ +@ + CBZ r1, __tx_ts_new @ If NULL, skip preservation +@ +@ /* Recover PSP and preserve current thread context. */ +@ + STR r3, [r0] @ Set _tx_thread_current_ptr to NULL + MRS r12, PSP @ Pickup PSP pointer (thread's stack pointer) + STMDB r12!, {r4-r11} @ Save its remaining registers +#ifdef TX_ENABLE_FPU_SUPPORT + TST LR, #0x10 @ Determine if the VFP extended frame is present + BNE _skip_vfp_save + VSTMDB r12!,{s16-s31} @ Yes, save additional VFP registers +_skip_vfp_save: +#endif + LDR r4, =_tx_timer_time_slice @ Build address of time-slice variable + STMDB r12!, {LR} @ Save LR on the stack +@ +@ /* Determine if time-slice is active. If it isn't, skip time handling processing. */ +@ + LDR r5, [r4] @ Pickup current time-slice + STR r12, [r1, #8] @ Save the thread stack pointer + CBZ r5, __tx_ts_new @ If not active, skip processing +@ +@ /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ +@ + STR r5, [r1, #24] @ Save current time-slice +@ +@ /* Clear the global time-slice. */ +@ + STR r3, [r4] @ Clear time-slice +@ +@ +@ /* Executing thread is now completely preserved!!! */ +@ +__tx_ts_new: +@ +@ /* Now we are looking for a new thread to execute! */ +@ + CPSID i @ Disable interrupts + LDR r1, [r2] @ Is there another thread ready to execute? + CBZ r1, __tx_ts_wait @ No, skip to the wait processing +@ +@ /* Yes, another thread is ready for else, make the current thread the new thread. */ +@ + STR r1, [r0] @ Setup the current thread pointer to the new thread + CPSIE i @ Enable interrupts +@ +@ /* Increment the thread run count. */ +@ +__tx_ts_restore: + LDR r7, [r1, #4] @ Pickup the current thread run count + LDR r4, =_tx_timer_time_slice @ Build address of time-slice variable + LDR r5, [r1, #24] @ Pickup thread's current time-slice + ADD r7, r7, #1 @ Increment the thread run count + STR r7, [r1, #4] @ Store the new run count +@ +@ /* Setup global time-slice with thread's current time-slice. */ +@ + STR r5, [r4] @ Setup global time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the thread entry function to indicate the thread is executing. */ +@ + PUSH {r0, r1} @ Save r0/r1 + BL _tx_execution_thread_enter @ Call the thread execution enter function + POP {r0, r1} @ Recover r3 +#endif +@ +@ /* Restore the thread context and PSP. */ +@ + LDR r12, [r1, #8] @ Pickup thread's stack pointer + LDMIA r12!, {LR} @ Pickup LR +#ifdef TX_ENABLE_FPU_SUPPORT + TST LR, #0x10 @ Determine if the VFP extended frame is present + BNE _skip_vfp_restore @ If not, skip VFP restore + VLDMIA r12!, {s16-s31} @ Yes, restore additional VFP registers +_skip_vfp_restore: +#endif + LDMIA r12!, {r4-r11} @ Recover thread's registers + MSR PSP, r12 @ Setup the thread's stack pointer +@ +@ /* Return to thread. */ +@ + BX lr @ Return to thread! +@ +@ /* The following is the idle wait processing... in this case, no threads are ready for execution and the +@ system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +@ are disabled to allow use of WFI for waiting for a thread to arrive. */ +@ +__tx_ts_wait: + CPSID i @ Disable interrupts + LDR r1, [r2] @ Pickup the next thread to execute pointer + STR r1, [r0] @ Store it in the current pointer + CBNZ r1, __tx_ts_ready @ If non-NULL, a new thread is ready! +#ifdef TX_ENABLE_WFI + DSB @ Ensure no outstanding memory transactions + WFI @ Wait for interrupt + ISB @ Ensure pipeline is flushed +#endif + CPSIE i @ Enable interrupts + B __tx_ts_wait @ Loop to continue waiting +@ +@ /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +@ already in the handler! */ +@ +__tx_ts_ready: + MOV r7, #0x08000000 @ Build clear PendSV value + MOV r8, #0xE000E000 @ Build base NVIC address + STR r7, [r8, #0xD04] @ Clear any PendSV +@ +@ /* Re-enable interrupts and restore new thread. */ +@ + CPSIE i @ Enable interrupts + B __tx_ts_restore @ Restore the thread + + +#ifdef TX_ENABLE_FPU_SUPPORT + + .global tx_thread_fpu_enable + .thumb_func +tx_thread_fpu_enable: +@ +@ /* Automatic VPF logic is supported, this function is present only for +@ backward compatibility purposes and therefore simply returns. */ +@ + BX LR @ Return to caller + + .global tx_thread_fpu_disable + .thumb_func +tx_thread_fpu_disable: +@ +@ /* Automatic VPF logic is supported, this function is present only for +@ backward compatibility purposes and therefore simply returns. */ +@ + BX LR @ Return to caller + + +#endif + diff --git a/ports/cortex_m7/ac6/src/tx_thread_stack_build.S b/ports/cortex_m7/ac6/src/tx_thread_stack_build.S new file mode 100644 index 00000000..f7a7ec21 --- /dev/null +++ b/ports/cortex_m7/ac6/src/tx_thread_stack_build.S @@ -0,0 +1,146 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ + .text + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_stack_build Cortex-M7/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function builds a stack frame on the supplied thread's stack. */ +@/* The stack frame results in a fake interrupt return to the supplied */ +@/* function pointer. */ +@/* */ +@/* INPUT */ +@/* */ +@/* thread_ptr Pointer to thread control blk */ +@/* function_ptr Pointer to return function */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_thread_create Create thread service */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +@{ + .global _tx_thread_stack_build + .thumb_func +_tx_thread_stack_build: +@ +@ +@ /* Build a fake interrupt frame. The form of the fake interrupt stack +@ on the Cortex-M7 should look like the following after it is built: +@ +@ Stack Top: +@ LR Interrupted LR (LR at time of PENDSV) +@ r4 Initial value for r4 +@ r5 Initial value for r5 +@ r6 Initial value for r6 +@ r7 Initial value for r7 +@ r8 Initial value for r8 +@ r9 Initial value for r9 +@ r10 Initial value for r10 +@ r11 Initial value for r11 +@ r0 Initial value for r0 (Hardware stack starts here!!) +@ r1 Initial value for r1 +@ r2 Initial value for r2 +@ r3 Initial value for r3 +@ r12 Initial value for r12 +@ lr Initial value for lr +@ pc Initial value for pc +@ xPSR Initial value for xPSR +@ +@ Stack Bottom: (higher memory address) */ +@ + LDR r2, [r0, #16] @ Pickup end of stack area + BIC r2, r2, #0x7 @ Align frame + SUB r2, r2, #68 @ Subtract frame size + LDR r3, =0xFFFFFFFD @ Build initial LR value + STR r3, [r2, #0] @ Save on the stack +@ +@ /* Actually build the stack frame. */ +@ + MOV r3, #0 @ Build initial register value + STR r3, [r2, #4] @ Store initial r4 + STR r3, [r2, #8] @ Store initial r5 + STR r3, [r2, #12] @ Store initial r6 + STR r3, [r2, #16] @ Store initial r7 + STR r3, [r2, #20] @ Store initial r8 + STR r3, [r2, #24] @ Store initial r9 + STR r3, [r2, #28] @ Store initial r10 + STR r3, [r2, #32] @ Store initial r11 +@ +@ /* Hardware stack follows. */ +@ + STR r3, [r2, #36] @ Store initial r0 + STR r3, [r2, #40] @ Store initial r1 + STR r3, [r2, #44] @ Store initial r2 + STR r3, [r2, #48] @ Store initial r3 + STR r3, [r2, #52] @ Store initial r12 + MOV r3, #0xFFFFFFFF @ Poison EXC_RETURN value + STR r3, [r2, #56] @ Store initial lr + STR r1, [r2, #60] @ Store initial pc + MOV r3, #0x01000000 @ Only T-bit need be set + STR r3, [r2, #64] @ Store initial xPSR +@ +@ /* Setup stack pointer. */ +@ thread_ptr -> tx_thread_stack_ptr = r2; +@ + STR r2, [r0, #8] @ Save stack pointer in thread's + @ control block + BX lr @ Return to caller +@} + + diff --git a/ports/cortex_m7/ac6/src/tx_thread_system_return.S b/ports/cortex_m7/ac6/src/tx_thread_system_return.S new file mode 100644 index 00000000..f9ba40fb --- /dev/null +++ b/ports/cortex_m7/ac6/src/tx_thread_system_return.S @@ -0,0 +1,98 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@/* #define TX_SOURCE_CODE */ +@ +@ +@/* Include necessary system files. */ +@ +@/* #include "tx_api.h" +@ #include "tx_thread.h" +@ #include "tx_timer.h" */ + + + .text 32 + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_system_return Cortex-M7/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is target processor specific. It is used to transfer */ +@/* control from a thread back to the ThreadX system. Only a */ +@/* minimal context is saved since the compiler assumes temp registers */ +@/* are going to get slicked by a function call anyway. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling loop */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX components */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@/* VOID _tx_thread_system_return(VOID) +@{ */ + .thumb_func + .global _tx_thread_system_return +_tx_thread_system_return: +@ +@ /* Return to real scheduler via PendSV. Note that this routine is often +@ replaced with in-line assembly in tx_port.h to improved performance. */ +@ + MOV r0, #0x10000000 @ Load PENDSVSET bit + MOV r1, #0xE000E000 @ Load NVIC base + STR r0, [r1, #0xD04] @ Set PENDSVBIT in ICSR + MRS r0, IPSR @ Pickup IPSR + CMP r0, #0 @ Is it a thread returning? + BNE _isr_context @ If ISR, skip interrupt enable + MRS r1, PRIMASK @ Thread context returning, pickup PRIMASK + CPSIE i @ Enable interrupts + MSR PRIMASK, r1 @ Restore original interrupt posture +_isr_context: + BX lr @ Return to caller + +@/* } */ + diff --git a/ports/cortex_m7/ac6/src/tx_timer_interrupt.S b/ports/cortex_m7/ac6/src/tx_timer_interrupt.S new file mode 100644 index 00000000..e58e27d2 --- /dev/null +++ b/ports/cortex_m7/ac6/src/tx_timer_interrupt.S @@ -0,0 +1,270 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Timer */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_timer.h" +@#include "tx_thread.h" +@ +@ +@Define Assembly language external references... +@ + .global _tx_timer_time_slice + .global _tx_timer_system_clock + .global _tx_timer_current_ptr + .global _tx_timer_list_start + .global _tx_timer_list_end + .global _tx_timer_expired_time_slice + .global _tx_timer_expired + .global _tx_thread_time_slice + .global _tx_timer_expiration_process +@ +@ + .text + .align 4 + .syntax unified +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_timer_interrupt Cortex-M7/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function processes the hardware timer interrupt. This */ +@/* processing includes incrementing the system clock and checking for */ +@/* time slice and/or timer expiration. If either is found, the */ +@/* interrupt context save/restore functions are called along with the */ +@/* expiration functions. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_timer_expiration_process Timer expiration processing */ +@/* _tx_thread_time_slice Time slice interrupted thread */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* interrupt vector */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_timer_interrupt(VOID) +@{ + .global _tx_timer_interrupt + .thumb_func +_tx_timer_interrupt: +@ +@ /* Upon entry to this routine, it is assumed that context save has already +@ been called, and therefore the compiler scratch registers are available +@ for use. */ +@ +@ /* Increment the system clock. */ +@ _tx_timer_system_clock++; +@ + LDR r1, =_tx_timer_system_clock @ Pickup address of system clock + LDR r0, [r1, #0] @ Pickup system clock + ADD r0, r0, #1 @ Increment system clock + STR r0, [r1, #0] @ Store new system clock +@ +@ /* Test for time-slice expiration. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice + LDR r2, [r3, #0] @ Pickup time-slice + CMP r2, #0 @ Is it non-active? + BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing +@ +@ /* Decrement the time_slice. */ +@ _tx_timer_time_slice--; +@ + SUB r2, r2, #1 @ Decrement the time-slice + STR r2, [r3, #0] @ Store new time-slice value +@ +@ /* Check for expiration. */ +@ if (__tx_timer_time_slice == 0) +@ + CMP r2, #0 @ Has it expired? + BNE __tx_timer_no_time_slice @ No, skip expiration processing +@ +@ /* Set the time-slice expired flag. */ +@ _tx_timer_expired_time_slice = TX_TRUE; +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of expired flag + MOV r0, #1 @ Build expired value + STR r0, [r3, #0] @ Set time-slice expiration flag +@ +@ } +@ +__tx_timer_no_time_slice: +@ +@ /* Test for timer expiration. */ +@ if (*_tx_timer_current_ptr) +@ { +@ + LDR r1, =_tx_timer_current_ptr @ Pickup current timer pointer address + LDR r0, [r1, #0] @ Pickup current timer + LDR r2, [r0, #0] @ Pickup timer list entry + CMP r2, #0 @ Is there anything in the list? + BEQ __tx_timer_no_timer @ No, just increment the timer +@ +@ /* Set expiration flag. */ +@ _tx_timer_expired = TX_TRUE; +@ + LDR r3, =_tx_timer_expired @ Pickup expiration flag address + MOV r2, #1 @ Build expired value + STR r2, [r3, #0] @ Set expired flag + B __tx_timer_done @ Finished timer processing +@ +@ } +@ else +@ { +__tx_timer_no_timer: +@ +@ /* No timer expired, increment the timer pointer. */ +@ _tx_timer_current_ptr++; +@ + ADD r0, r0, #4 @ Move to next timer +@ +@ /* Check for wrap-around. */ +@ if (_tx_timer_current_ptr == _tx_timer_list_end) +@ + LDR r3, =_tx_timer_list_end @ Pickup addr of timer list end + LDR r2, [r3, #0] @ Pickup list end + CMP r0, r2 @ Are we at list end? + BNE __tx_timer_skip_wrap @ No, skip wrap-around logic +@ +@ /* Wrap to beginning of list. */ +@ _tx_timer_current_ptr = _tx_timer_list_start; +@ + LDR r3, =_tx_timer_list_start @ Pickup addr of timer list start + LDR r0, [r3, #0] @ Set current pointer to list start +@ +__tx_timer_skip_wrap: +@ + STR r0, [r1, #0] @ Store new current timer pointer +@ } +@ +__tx_timer_done: +@ +@ +@ /* See if anything has expired. */ +@ if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +@ { +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of expired flag + LDR r2, [r3, #0] @ Pickup time-slice expired flag + CMP r2, #0 @ Did a time-slice expire? + BNE __tx_something_expired @ If non-zero, time-slice expired + LDR r1, =_tx_timer_expired @ Pickup addr of other expired flag + LDR r0, [r1, #0] @ Pickup timer expired flag + CMP r0, #0 @ Did a timer expire? + BEQ __tx_timer_nothing_expired @ No, nothing expired +@ +__tx_something_expired: +@ +@ + STMDB sp!, {r0, lr} @ Save the lr register on the stack + @ and save r0 just to keep 8-byte alignment +@ +@ /* Did a timer expire? */ +@ if (_tx_timer_expired) +@ { +@ + LDR r1, =_tx_timer_expired @ Pickup addr of expired flag + LDR r0, [r1, #0] @ Pickup timer expired flag + CMP r0, #0 @ Check for timer expiration + BEQ __tx_timer_dont_activate @ If not set, skip timer activation +@ +@ /* Process timer expiration. */ +@ _tx_timer_expiration_process(); +@ + BL _tx_timer_expiration_process @ Call the timer expiration handling routine +@ +@ } +__tx_timer_dont_activate: +@ +@ /* Did time slice expire? */ +@ if (_tx_timer_expired_time_slice) +@ { +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup addr of time-slice expired + LDR r2, [r3, #0] @ Pickup the actual flag + CMP r2, #0 @ See if the flag is set + BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing +@ +@ /* Time slice interrupted thread. */ +@ _tx_thread_time_slice(); +@ + BL _tx_thread_time_slice @ Call time-slice processing + LDR r0, =_tx_thread_preempt_disable @ Build address of preempt disable flag + LDR r1, [r0] @ Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice @ Yes, skip the PendSV logic + LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address + LDR r1, [r0] @ Pickup the current thread pointer + LDR r2, =_tx_thread_execute_ptr @ Build execute thread pointer address + LDR r3, [r2] @ Pickup the execute thread pointer + LDR r0, =0xE000ED04 @ Build address of control register + LDR r2, =0x10000000 @ Build value for PendSV bit + CMP r1, r3 @ Are they the same? + BEQ __tx_timer_skip_time_slice @ If the same, there was no time-slice performed + STR r2, [r0] @ Not the same, issue the PendSV for preemption +__tx_timer_skip_time_slice: +@ +@ } +@ +__tx_timer_not_ts_expiration: +@ + LDMIA sp!, {r0, lr} @ Recover lr register (r0 is just there for + @ the 8-byte stack alignment +@ +@ } +@ +__tx_timer_nothing_expired: + + DSB @ Complete all memory access + BX lr @ Return to caller +@ +@} + + diff --git a/ports/cortex_r5/ac6/example_build/sample_threadx/.cproject b/ports/cortex_r5/ac6/example_build/sample_threadx/.cproject new file mode 100644 index 00000000..9dca2462 --- /dev/null +++ b/ports/cortex_r5/ac6/example_build/sample_threadx/.cproject @@ -0,0 +1,238 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_r5/ac6/example_build/sample_threadx/.project b/ports/cortex_r5/ac6/example_build/sample_threadx/.project new file mode 100644 index 00000000..725328bd --- /dev/null +++ b/ports/cortex_r5/ac6/example_build/sample_threadx/.project @@ -0,0 +1,27 @@ + + + sample_threadx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.arm.debug.ds.nature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/ports/cortex_r5/ac6/example_build/sample_threadx/.settings/language.settings.xml b/ports/cortex_r5/ac6/example_build/sample_threadx/.settings/language.settings.xml new file mode 100644 index 00000000..394dd20f --- /dev/null +++ b/ports/cortex_r5/ac6/example_build/sample_threadx/.settings/language.settings.xml @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_r5/ac6/example_build/sample_threadx/cortex-r5_tx.launch b/ports/cortex_r5/ac6/example_build/sample_threadx/cortex-r5_tx.launch new file mode 100644 index 00000000..eccecf15 --- /dev/null +++ b/ports/cortex_r5/ac6/example_build/sample_threadx/cortex-r5_tx.launch @@ -0,0 +1,202 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_r5/ac6/example_build/sample_threadx/sample_threadx.c b/ports/cortex_r5/ac6/example_build/sample_threadx/sample_threadx.c new file mode 100644 index 00000000..418ec634 --- /dev/null +++ b/ports/cortex_r5/ac6/example_build/sample_threadx/sample_threadx.c @@ -0,0 +1,369 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports/cortex_r5/ac6/example_build/sample_threadx/sample_threadx.scat b/ports/cortex_r5/ac6/example_build/sample_threadx/sample_threadx.scat new file mode 100644 index 00000000..c13f39f8 --- /dev/null +++ b/ports/cortex_r5/ac6/example_build/sample_threadx/sample_threadx.scat @@ -0,0 +1,39 @@ +;******************************************************* +; Copyright (c) 2011-2017 Arm Limited (or its affiliates). All rights reserved. +; Use, modification and redistribution of this file is subject to your possession of a +; valid End User License Agreement for the Arm Product of which these examples are part of +; and your compliance with all applicable terms and conditions of such licence agreement. +;******************************************************* + +; Scatter-file for Cortex-R5 bare-metal example +; Addresses suitable for Cortex-R5 Logic Tile on Versatile Express with SRAM from 0x48000000 to 0x4C000000 +; Change these addresses to match the memory map your own target + +LOAD 0x48000000 +{ + CODE +0 + { + startup.o (VECTORS, +First) ; Startup code + * (InRoot$$Sections) ; All library sections that must be in a root region + * (+RO) ; Application code, including C library + } + + DATA 0x48010000 + { + * (+RW,+ZI) ; All RW and ZI Data + } + + ARM_LIB_STACKHEAP 0x48020000 EMPTY 0x4000 ; Stack and heap + { + } +} + +; The Cortex-R5 Logic Tile on Versatile Express has +; 64K ATCM from 0x40000000 to 0x4000FFFF +; 64K BTCM from 0xE0FE0000 to 0xE0FEFFFF +; +; Use these regions to place code and/or data in TCM: +; ATCM 0x40000000 0x10000 { ... } +; BTCM 0xE0FE0000 0x10000 { ... } +; +; Scatterloading can be used to copy code and/or data into the TCMs diff --git a/ports/cortex_r5/ac6/example_build/sample_threadx/startup.S b/ports/cortex_r5/ac6/example_build/sample_threadx/startup.S new file mode 100644 index 00000000..584f08a1 --- /dev/null +++ b/ports/cortex_r5/ac6/example_build/sample_threadx/startup.S @@ -0,0 +1,362 @@ +//---------------------------------------------------------------- +// Cortex-R5(F) Embedded example - Startup Code +// +// Copyright (c) 2006-2018 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +//---------------------------------------------------------------- + +// MPU region defines + +#define Region_32B 0b00100 +#define Region_64B 0b00101 +#define Region_128B 0b00110 +#define Region_256B 0b00111 +#define Region_512B 0b01000 +#define Region_1K 0b01001 +#define Region_2K 0b01010 +#define Region_4K 0b01011 +#define Region_8K 0b01100 +#define Region_16K 0b01101 +#define Region_32K 0b01110 +#define Region_64K 0b01111 +#define Region_128K 0b10000 +#define Region_256K 0b10001 +#define Region_512K 0b10010 +#define Region_1M 0b10011 +#define Region_2M 0b10100 +#define Region_4M 0b10101 +#define Region_8M 0b10110 +#define Region_16M 0b10111 +#define Region_32M 0b11000 +#define Region_64M 0b11001 +#define Region_128M 0b11010 +#define Region_256M 0b11011 +#define Region_512M 0b11100 +#define Region_1G 0b11101 +#define Region_2G 0b11110 +#define Region_4G 0b11111 + +#define Region_Enable 0b1 + +#define Execute_Never 0x1000 // Bit 12 + +#define Normal_nShared 0x03 // Outer and Inner write-back, no write-allocate +#define Device_nShared 0x10 + +#define Full_Access 0b011 +#define Read_Only 0b110 + +//---------------------------------------------------------------- + + .eabi_attribute Tag_ABI_align8_preserved,1 + + .section VECTORS,"ax" + .align 3 + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + + +//---------------------------------------------------------------- +// Entry point for the Reset handler +//---------------------------------------------------------------- + + .global Start + +Start: + +//---------------------------------------------------------------- +// Exception Vector Table +//---------------------------------------------------------------- +// Note: LDR PC instructions are used here, though branch (B) instructions +// could also be used, unless the exception handlers are >32MB away. + +Vectors: + LDR PC, Reset_Addr + LDR PC, Undefined_Addr + LDR PC, SVC_Addr + LDR PC, Prefetch_Addr + LDR PC, Abort_Addr + B . // Reserved vector + LDR PC, IRQ_Addr + LDR PC, FIQ_Addr + + + .balign 4 +Reset_Addr: .word Reset_Handler +Undefined_Addr: .word __tx_undefined +SVC_Addr: .word __tx_swi_interrupt +Prefetch_Addr: .word __tx_prefetch_handler +Abort_Addr: .word __tx_abort_handler +IRQ_Addr: .word __tx_irq_handler +FIQ_Addr: .word __tx_fiq_handler + + +//---------------------------------------------------------------- +// Exception Handlers +//---------------------------------------------------------------- + +Undefined_Handler: + B Undefined_Handler +SVC_Handler: + B SVC_Handler +Prefetch_Handler: + B Prefetch_Handler +Abort_Handler: + B Abort_Handler +IRQ_Handler: + B IRQ_Handler +FIQ_Handler: + B FIQ_Handler + + +//---------------------------------------------------------------- +// Reset Handler +//---------------------------------------------------------------- + + .global Reset_Handler + .type Reset_Handler, "function" +Reset_Handler: + +//---------------------------------------------------------------- +// Disable MPU and caches +//---------------------------------------------------------------- + +// Disable MPU and cache in case it was left enabled from an earlier run +// This does not need to be done from a cold reset + + MRC p15, 0, r0, c1, c0, 0 // Read System Control Register + BIC r0, r0, #0x05 // Disable MPU (M bit) and data cache (C bit) + BIC r0, r0, #0x1000 // Disable instruction cache (I bit) + DSB // Ensure all previous loads/stores have completed + MCR p15, 0, r0, c1, c0, 0 // Write System Control Register + ISB // Ensure subsequent insts execute wrt new MPU settings + +//---------------------------------------------------------------- +// Disable Branch prediction +//---------------------------------------------------------------- + +// In the Cortex-R5, the Z-bit of the SCTLR does not control the program flow prediction. +// Some control bits in the ACTLR control the program flow and prefetch features instead. +// These are enabled by default, but are shown here for completeness. + + MRC p15, 0, r0, c1, c0, 1 // Read ACTLR + ORR r0, r0, #(0x1 << 17) // Enable RSDIS bit 17 to disable the return stack + ORR r0, r0, #(0x1 << 16) // Clear BP bit 15 and set BP bit 16: + BIC r0, r0, #(0x1 << 15) // Branch always not taken and history table updates disabled + MCR p15, 0, r0, c1, c0, 1 // Write ACTLR + ISB + +//---------------------------------------------------------------- +// Initialize Supervisor Mode Stack using Linker symbol from scatter file. +// Stacks must be 8 byte aligned. +//---------------------------------------------------------------- + + .global Image$$ARM_LIB_STACKHEAP$$ZI$$Limit + LDR SP, =Image$$ARM_LIB_STACKHEAP$$ZI$$Limit + + +//---------------------------------------------------------------- +// Cache invalidation +//---------------------------------------------------------------- + + DSB // Complete all outstanding explicit memory operations + + MOV r0, #0 + + MCR p15, 0, r0, c7, c5, 0 // Invalidate entire instruction cache + MCR p15, 0, r0, c15, c5, 0 // Invalidate entire data cache + + +//---------------------------------------------------------------- +// TCM Configuration +//---------------------------------------------------------------- + +// Cortex-R5 optionally provides two Tightly-Coupled Memory (TCM) blocks (ATCM and BTCM) for fast access to code or data. +// ATCM typically holds interrupt or exception code that must be accessed at high speed, +// without any potential delay resulting from a cache miss. +// BTCM typically holds a block of data for intensive processing, such as audio or video data. +// In the Cortex-R5 processor, both ATCM and BTCM support both instruction and data accesses. + +// The following illustrates basic TCM configuration, as the basis for exploration by the user + +#ifdef TCM + .global Image$$ATCM$$Base + .global Image$$BTCM$$Base + + MRC p15, 0, r0, c0, c0, 2 // Read TCM Type Register + // r0 now contains ATCM & BTCM availability + + MRC p15, 0, r0, c9, c1, 1 // Read ATCM Region Register + // r0 now contains ATCM size in bits [6:2] + + MRC p15, 0, r0, c9, c1, 0 // Read BTCM Region Register + // r0 now contains BTCM size in bits [6:2] + +// The Cortex-R5 Logic Tile on Versatile Express has +// 64K ATCM from 0x40000000 to 0x4000FFFF +// 64K BTCM from 0xE0FE0000 to 0xE0FEFFFF + + LDR r0, =Image$$ATCM$$Base // Set ATCM base address + ORR r0, r0, #1 // Enable it + MCR p15, 0, r0, c9, c1, 1 // Write ATCM Region Register + + LDR r0, =Image$$BTCM$$Base // Set BTCM base address + ORR r0, r0, #1 // Enable it + MCR p15, 0, r0, c9, c1, 0 // Write BTCM Region Register + +#endif + + +//---------------------------------------------------------------- +// MPU Configuration +//---------------------------------------------------------------- + +// Notes: +// * Regions apply to both instruction and data accesses. +// * Each region base address must be a multiple of its size +// * Any address range not covered by an enabled region will abort +// * The region at 0x0 over the Vector table is needed to support semihosting + +// Region 0: Code Base = 0x48000000 Size = 32KB Normal Non-shared Read-only Executable +// Region 1: Data Base = 0x48008000 Size = 16KB Normal Non-shared Full access Not Executable +// Region 2: Stack/Heap Base = 0x4800C000 Size = 16KB Normal Non-shared Full access Not Executable +// Region 3: Vectors Base = 0x00000000 Size = 1KB Normal Non-shared Full access Executable + + // Import linker symbols to get region base addresses + .global Image$$CODE$$Base + .global Image$$DATA$$Base + .global Image$$ARM_LIB_STACKHEAP$$Base + + // Region 0 - Code + MOV r1, #0 + MCR p15, 0, r1, c6, c2, 0 // Set memory region number register + ISB // Ensure subsequent insts execute wrt this region + LDR r2, =Image$$CODE$$Base + MCR p15, 0, r2, c6, c1, 0 // Set region base address register + LDR r2, =0x0 | (Region_64K << 1) | Region_Enable + MCR p15, 0, r2, c6, c1, 2 // Set region size & enable register + LDR r2, =0x0 | (Read_Only << 8) | Normal_nShared + MCR p15, 0, r2, c6, c1, 4 // Set region access control register + + // Region 1 - Data + ADD r1, r1, #1 + MCR p15, 0, r1, c6, c2, 0 // Set memory region number register + ISB // Ensure subsequent insts execute wrt this region + LDR r2, =Image$$DATA$$Base + MCR p15, 0, r2, c6, c1, 0 // Set region base address register + LDR r2, =0x0 | (Region_16K << 1) | Region_Enable + MCR p15, 0, r2, c6, c1, 2 // Set region size & enable register + LDR r2, =0x0 | (Full_Access << 8) | Normal_nShared | Execute_Never + MCR p15, 0, r2, c6, c1, 4 // Set region access control register + + // Region 2 - Stack/Heap + ADD r1, r1, #1 + MCR p15, 0, r1, c6, c2, 0 // Set memory region number register + ISB // Ensure subsequent insts execute wrt this region + LDR r2, =Image$$ARM_LIB_STACKHEAP$$Base + MCR p15, 0, r2, c6, c1, 0 // Set region base address register + LDR r2, =0x0 | (Region_32K << 1) | Region_Enable + MCR p15, 0, r2, c6, c1, 2 // Set region size & enable register + LDR r2, =0x0 | (Full_Access << 8) | Normal_nShared | Execute_Never + MCR p15, 0, r2, c6, c1, 4 // Set region access control register + + // Region 3 - Vectors + ADD r1, r1, #1 + MCR p15, 0, r1, c6, c2, 0 // Set memory region number register + ISB // Ensure subsequent insts execute wrt this region + LDR r2, =0 + MCR p15, 0, r2, c6, c1, 0 // Set region base address register + LDR r2, =0x0 | (Region_1K << 1) | Region_Enable + MCR p15, 0, r2, c6, c1, 2 // Set region size & enable register + LDR r2, =0x0 | (Full_Access << 8) | Normal_nShared + MCR p15, 0, r2, c6, c1, 4 // Set region access control register + + // Disable all higher priority regions (assumes unified regions, which is always true for Cortex-R5) + MRC p15, 0, r0, c0, c0, 4 // Read MPU Type register (MPUIR) + LSR r0, r0, #8 + AND r0, r0, #0xff // r0 = Number of MPU regions (0, 12, or 16 for Cortex-R5) + MOV r2, #0 // Value to write to disable region +region_loop: + ADD r1, r1, #1 + CMP r0, r1 + BLS regions_done + MCR p15, 0, r1, c6, c2, 0 // Set memory region number register (RGNR) + MCR p15, 0, r2, c6, c1, 2 // Set region size & enable register (DRSR) + B region_loop +regions_done: + + +#ifdef __ARM_FP +//---------------------------------------------------------------- +// Enable access to VFP by enabling access to Coprocessors 10 and 11. +// Enables Full Access i.e. in both privileged and non privileged modes +//---------------------------------------------------------------- + + MRC p15, 0, r0, c1, c0, 2 // Read Coprocessor Access Control Register (CPACR) + ORR r0, r0, #(0xF << 20) // Enable access to CP 10 & 11 + MCR p15, 0, r0, c1, c0, 2 // Write Coprocessor Access Control Register (CPACR) + ISB + +//---------------------------------------------------------------- +// Switch on the VFP hardware +//---------------------------------------------------------------- + + MOV r0, #0x40000000 + VMSR FPEXC, r0 // Write FPEXC register, EN bit set +#endif + +//---------------------------------------------------------------- +// Enable Branch prediction +//---------------------------------------------------------------- + +// In the Cortex-R5, the Z-bit of the SCTLR does not control the program flow prediction. +// Some control bits in the ACTLR control the program flow and prefetch features instead. +// These are enabled by default, but are shown here for completeness. + + MRC p15, 0, r0, c1, c0, 1 // Read ACTLR + BIC r0, r0, #(0x1 << 17) // Clear RSDIS bit 17 to enable return stack + BIC r0, r0, #(0x1 << 16) // Clear BP bit 15 and BP bit 16: + BIC r0, r0, #(0x1 << 15) // Normal operation, BP is taken from the global history table. + MCR p15, 0, r0, c1, c0, 1 // Write ACTLR + ISB + +#if 1 +//---------------------------------------------------------------- +// Enable MPU and branch to C library init +// Leaving the caches disabled until after scatter loading. +//---------------------------------------------------------------- + + MRC p15, 0, r0, c1, c0, 0 // Read System Control Register + ORR r0, r0, #0x01 // Set M bit to enable MPU + DSB // Ensure all previous loads/stores have completed + MCR p15, 0, r0, c1, c0, 0 // Write System Control Register + ISB // Ensure subsequent insts execute wrt new MPU settings +#endif + + .global __main + B __main + + .size Reset_Handler, . - Reset_Handler + + +//---------------------------------------------------------------- +// Global Enable for Instruction and Data Caching +//---------------------------------------------------------------- + + .global enable_caches + + .type enable_caches, "function" + .cfi_startproc +enable_caches: + + MRC p15, 0, r0, c1, c0, 0 // Read System Control Register + ORR r0, r0, #(0x1 << 12) // enable I Cache + ORR r0, r0, #(0x1 << 2) // enable D Cache + MCR p15, 0, r0, c1, c0, 0 // Write System Control Register + ISB + + BX lr + .cfi_endproc + + .size enable_caches, . - enable_caches diff --git a/ports/cortex_r5/ac6/example_build/sample_threadx/tx_initialize_low_level.S b/ports/cortex_r5/ac6/example_build/sample_threadx/tx_initialize_low_level.S new file mode 100644 index 00000000..e744c843 --- /dev/null +++ b/ports/cortex_r5/ac6/example_build/sample_threadx/tx_initialize_low_level.S @@ -0,0 +1,345 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Initialize */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_initialize.h" +@#include "tx_thread.h" +@#include "tx_timer.h" + + .arm + +SVC_MODE = 0xD3 @ Disable IRQ/FIQ SVC mode +IRQ_MODE = 0xD2 @ Disable IRQ/FIQ IRQ mode +FIQ_MODE = 0xD1 @ Disable IRQ/FIQ FIQ mode +SYS_MODE = 0xDF @ Disable IRQ/FIQ SYS mode +FIQ_STACK_SIZE = 512 @ FIQ stack size +IRQ_STACK_SIZE = 1024 @ IRQ stack size +SYS_STACK_SIZE = 1024 @ System stack size +@ +@ + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global _tx_thread_context_save + .global _tx_thread_context_restore + .global _tx_timer_interrupt + +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_initialize_low_level for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .thumb + .global $_tx_initialize_low_level + .type $_tx_initialize_low_level,function +$_tx_initialize_low_level: + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_initialize_low_level @ Call _tx_initialize_low_level function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_initialize_low_level Cortex-R5/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for any low-level processor */ +@/* initialization, including setting up interrupt vectors, setting */ +@/* up a periodic timer interrupt source, saving the system stack */ +@/* pointer for use in ISR processing later, and finding the first */ +@/* available RAM memory address for tx_application_define. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_initialize_low_level(VOID) +@{ + .global _tx_initialize_low_level + .type _tx_initialize_low_level,function +_tx_initialize_low_level: +@ +@ /* We must be in SVC mode at this point! */ +@ +@ /* Setup various stack pointers. */ +@ + LDR r1, =Image$$ARM_LIB_STACKHEAP$$ZI$$Limit @ Get pointer to stack area + +#ifdef TX_ENABLE_IRQ_NESTING +@ +@ /* Setup the system mode stack for nested interrupt support */ +@ + LDR r2, =SYS_STACK_SIZE @ Pickup stack size + MOV r3, #SYS_MODE @ Build SYS mode CPSR + MSR CPSR_c, r3 @ Enter SYS mode + SUB r1, r1, #1 @ Backup 1 byte + BIC r1, r1, #7 @ Ensure 8-byte alignment + MOV sp, r1 @ Setup SYS stack pointer + SUB r1, r1, r2 @ Calculate start of next stack +#endif + + LDR r2, =FIQ_STACK_SIZE @ Pickup stack size + MOV r0, #FIQ_MODE @ Build FIQ mode CPSR + MSR CPSR, r0 @ Enter FIQ mode + SUB r1, r1, #1 @ Backup 1 byte + BIC r1, r1, #7 @ Ensure 8-byte alignment + MOV sp, r1 @ Setup FIQ stack pointer + SUB r1, r1, r2 @ Calculate start of next stack + LDR r2, =IRQ_STACK_SIZE @ Pickup IRQ stack size + MOV r0, #IRQ_MODE @ Build IRQ mode CPSR + MSR CPSR, r0 @ Enter IRQ mode + SUB r1, r1, #1 @ Backup 1 byte + BIC r1, r1, #7 @ Ensure 8-byte alignment + MOV sp, r1 @ Setup IRQ stack pointer + SUB r3, r1, r2 @ Calculate end of IRQ stack + MOV r0, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR, r0 @ Enter SVC mode + LDR r2, =Image$$ARM_LIB_STACKHEAP$$Base @ Pickup stack bottom + CMP r3, r2 @ Compare the current stack end with the bottom +_stack_error_loop: + BLT _stack_error_loop @ If the IRQ stack exceeds the stack bottom, just sit here! +@ +@ /* Save the system stack pointer. */ +@ _tx_thread_system_stack_ptr = (VOID_PTR) (sp); +@ + LDR r2, =_tx_thread_system_stack_ptr @ Pickup stack pointer + STR r1, [r2] @ Save the system stack +@ +@ /* Save the first available memory address. */ +@ _tx_initialize_unused_memory = (VOID_PTR) _end; +@ + LDR r1, =Image$$DATA$$ZI$$Limit @ Get end of non-initialized RAM area + LDR r2, =_tx_initialize_unused_memory @ Pickup unused memory ptr address + ADD r1, r1, #8 @ Increment to next free word + STR r1, [r2] @ Save first free memory address +@ +@ /* Setup Timer for periodic interrupts. */ +@ +@ /* Done, return to caller. */ +@ +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} +@ +@ +@/* Define shells for each of the interrupt vectors. */ +@ + .global __tx_undefined +__tx_undefined: + B __tx_undefined @ Undefined handler +@ + .global __tx_swi_interrupt +__tx_swi_interrupt: + B __tx_swi_interrupt @ Software interrupt handler +@ + .global __tx_prefetch_handler +__tx_prefetch_handler: + B __tx_prefetch_handler @ Prefetch exception handler +@ + .global __tx_abort_handler +__tx_abort_handler: + B __tx_abort_handler @ Abort exception handler +@ + .global __tx_reserved_handler +__tx_reserved_handler: + B __tx_reserved_handler @ Reserved exception handler +@ + .global __tx_irq_processing_return + .type __tx_irq_processing_return,function + .global __tx_irq_handler +__tx_irq_handler: +@ +@ /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return: +@ +@ /* At this point execution is still in the IRQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. In +@ addition, IRQ interrupts may be re-enabled - with certain restrictions - +@ if nested IRQ interrupts are desired. Interrupts may be re-enabled over +@ small code sequences where lr is saved before enabling interrupts and +@ restored after interrupts are again disabled. */ +@ +@ /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +@ from IRQ mode with interrupts disabled. This routine switches to the +@ system mode and returns with IRQ interrupts enabled. +@ +@ NOTE: It is very important to ensure all IRQ interrupts are cleared +@ prior to enabling nested IRQ interrupts. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_start +#endif +@ +@ /* For debug purpose, execute the timer interrupt processing here. In +@ a real system, some kind of status indication would have to be checked +@ before the timer interrupt handler could be called. */ +@ + BL _tx_timer_interrupt @ Timer interrupt handler +@ +@ +@ /* If interrupt nesting was started earlier, the end of interrupt nesting +@ service must be called before returning to _tx_thread_context_restore. +@ This routine returns in processing in IRQ mode with interrupts disabled. */ +#ifdef TX_ENABLE_IRQ_NESTING + BL _tx_thread_irq_nesting_end +#endif +@ +@ /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore +@ +@ +@ /* This is an example of a vectored IRQ handler. */ +@ +@ .global __tx_example_vectored_irq_handler +@__tx_example_vectored_irq_handler: +@ +@ +@ /* Save initial context and call context save to prepare for +@ vectored ISR execution. */ +@ +@ STMDB sp!, {r0-r3} @ Save some scratch registers +@ MRS r0, SPSR @ Pickup saved SPSR +@ SUB lr, lr, #4 @ Adjust point of interrupt +@ STMDB sp!, {r0, r10, r12, lr} @ Store other scratch registers +@ BL _tx_thread_vectored_context_save @ Vectored context save +@ +@ /* At this point execution is still in the IRQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. In +@ addition, IRQ interrupts may be re-enabled - with certain restrictions - +@ if nested IRQ interrupts are desired. Interrupts may be re-enabled over +@ small code sequences where lr is saved before enabling interrupts and +@ restored after interrupts are again disabled. */ +@ +@ +@ /* Interrupt nesting is allowed after calling _tx_thread_irq_nesting_start +@ from IRQ mode with interrupts disabled. This routine switches to the +@ system mode and returns with IRQ interrupts enabled. +@ +@ NOTE: It is very important to ensure all IRQ interrupts are cleared +@ prior to enabling nested IRQ interrupts. */ +@#ifdef TX_ENABLE_IRQ_NESTING +@ BL _tx_thread_irq_nesting_start +@#endif +@ +@ /* Application IRQ handlers can be called here! */ +@ +@ /* If interrupt nesting was started earlier, the end of interrupt nesting +@ service must be called before returning to _tx_thread_context_restore. +@ This routine returns in processing in IRQ mode with interrupts disabled. */ +@#ifdef TX_ENABLE_IRQ_NESTING +@ BL _tx_thread_irq_nesting_end +@#endif +@ +@ /* Jump to context restore to restore system context. */ +@ B _tx_thread_context_restore +@ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + .global __tx_fiq_handler + .global __tx_fiq_processing_return +__tx_fiq_handler: +@ +@ /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +@ +@ /* At this point execution is still in the FIQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. */ +@ +@ /* Interrupt nesting is allowed after calling _tx_thread_fiq_nesting_start +@ from FIQ mode with interrupts disabled. This routine switches to the +@ system mode and returns with FIQ interrupts enabled. +@ +@ NOTE: It is very important to ensure all FIQ interrupts are cleared +@ prior to enabling nested FIQ interrupts. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_start +#endif +@ +@ /* Application FIQ handlers can be called here! */ +@ +@ /* If interrupt nesting was started earlier, the end of interrupt nesting +@ service must be called before returning to _tx_thread_fiq_context_restore. */ +#ifdef TX_ENABLE_FIQ_NESTING + BL _tx_thread_fiq_nesting_end +#endif +@ +@ /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore +@ +@ +#else + .global __tx_fiq_handler +__tx_fiq_handler: + B __tx_fiq_handler @ FIQ interrupt handler +#endif +@ +@ +BUILD_OPTIONS: + .word _tx_build_options @ Reference to bring in +VERSION_ID: + .word _tx_version_id @ Reference to bring in + + + diff --git a/ports/cortex_r5/ac6/example_build/tx/.cproject b/ports/cortex_r5/ac6/example_build/tx/.cproject new file mode 100644 index 00000000..c59050b6 --- /dev/null +++ b/ports/cortex_r5/ac6/example_build/tx/.cproject @@ -0,0 +1,216 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_r5/ac6/example_build/tx/.project b/ports/cortex_r5/ac6/example_build/tx/.project new file mode 100644 index 00000000..863ca5cb --- /dev/null +++ b/ports/cortex_r5/ac6/example_build/tx/.project @@ -0,0 +1,48 @@ + + + tx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + inc_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/inc + + + inc_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/inc + + + src_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common/src + + + src_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/src + + + diff --git a/ports/cortex_r5/ac6/example_build/tx/.settings/language.settings.xml b/ports/cortex_r5/ac6/example_build/tx/.settings/language.settings.xml new file mode 100644 index 00000000..c7e44f62 --- /dev/null +++ b/ports/cortex_r5/ac6/example_build/tx/.settings/language.settings.xml @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports/cortex_r5/ac6/inc/tx_port.h b/ports/cortex_r5/ac6/inc/tx_port.h new file mode 100644 index 00000000..dc2eee31 --- /dev/null +++ b/ports/cortex_r5/ac6/inc/tx_port.h @@ -0,0 +1,316 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-R5/AC6 */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#if __TARGET_ARCH_ARM > 4 + +#ifndef __thumb__ + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + asm volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); \ + b = 31 - b; +#endif +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifdef __thumb__ + +unsigned int _tx_thread_interrupt_disable(void); +unsigned int _tx_thread_interrupt_restore(UINT old_posture); + + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save, tx_temp; + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); +#else +#define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID i ": "=r" (interrupt_save) ); +#endif + +#define TX_RESTORE asm volatile (" MSR CPSR_c,%0 "::"r" (interrupt_save) ); + +#endif + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R5/AC6 Version 6.0.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + diff --git a/ports/cortex_r5/ac6/readme_threadx.txt b/ports/cortex_r5/ac6/readme_threadx.txt new file mode 100644 index 00000000..410f78bf --- /dev/null +++ b/ports/cortex_r5/ac6/readme_threadx.txt @@ -0,0 +1,325 @@ + Microsoft's Azure RTOS ThreadX for Cortex-R5 + + Using ARM Compiler 6 & DS + +1. Import the ThreadX Projects + +In order to build the ThreadX library and the ThreadX demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +into your DS workspace. + + +2. Building the ThreadX run-time Library + +Building the ThreadX library is easy; simply right-click the Eclipse project +"tx" and then select the "Build Project" button. You should now observe the compilation +and assembly of the ThreadX library. This project build produces the ThreadX +library file tx.a. + + +3. Demonstration System + +The ThreadX demonstration is designed to execute under the DS debugger on the +VE_Cortex-R5 Bare Metal simulator. + +Building the demonstration is easy; simply right-click the Eclipse project +"sample_threadx" and then select the "Build Project" button. You should now observe +the compilation and assembly of the ThreadX demonstration. This project build produces +the ThreadX library file sample_threadx.axf. Next, expand the demo ThreadX project folder +in the Project Explorer window, right-click on the 'cortex-r5_tx.launch' file, click +'Debug As', and then click 'cortex-r5_tx' from the submenu. This will cause the +debugger to load the sample_threadx.axf ELF file and run to main. You are now ready +to execute the ThreadX demonstration. + + +4. System Initialization + +The entry point in ThreadX for the Cortex-R5 using ARM tools is at label +"Vectors". This is defined within startup.S in the sample_threadx project. In addition, +this is where all static and global pre-set C variable initialization processing +takes place. + +This is also where initialization of a periodic timer interrupt source should take +place. + +In addition, _tx_initialize_low_level defines the first available address +for use by the application, which is supplied as the sole input parameter +to your application definition function, tx_application_define. + + +5. Register Usage and Stack Frames + +The AC6 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread +is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 CPSR CPSR + 0x08 r0 (a1) r4 (v1) + 0x0C r1 (a2) r5 (v2) + 0x10 r2 (a3) r6 (v3) + 0x14 r3 (a4) r7 (v4) + 0x18 r4 (v1) r8 (v5) + 0x1C r5 (v2) r9 (v6) + 0x20 r6 (v3) r10 (v7) + 0x24 r7 (v4) r11 (fp) + 0x28 r8 (v5) r14 (lr) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) + 0x3C r14 (lr) + 0x40 PC + + +6. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-R5 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +7.1 Vector Area + +The Cortex-R5 vectors start at address zero. The demonstration system startup +reset.S file contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. + + +7.2 IRQ ISRs + +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports +nested IRQ interrupts. The following sub-sections define the IRQ capabilities. + + +7.2.1 Standard IRQ ISRs + +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +is the default IRQ handler defined in tx_initialize_low_level.S: + + .global __tx_irq_handler + .global __tx_irq_processing_return +__tx_irq_handler: +@ +@ /* Jump to context save to save system context. */ + B _tx_thread_context_save @ Jump to the context save +__tx_irq_processing_return: +@ +@ /* At this point execution is still in the IRQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. Note +@ that IRQ interrupts are still disabled upon return from the context +@ save function. */ +@ +@ /* Application ISR call(s) go here! */ +@ +@ /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.2 Vectored IRQ ISRs + +The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified +by the particular implementation. The following is an example IRQ handler defined in +tx_initialize_low_level.S: + + .global __tx_irq_example_handler +__tx_irq_example_handler: +@ +@ /* Call context save to save system context. */ + + STMDB sp!, {r0-r3} @ Save some scratch registers + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} @ Store other scratch registers + BL _tx_thread_vectored_context_save @ Call the vectored IRQ context save +@ +@ /* At this point execution is still in the IRQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. Note +@ that IRQ interrupts are still disabled upon return from the context +@ save function. */ +@ +@ /* Application ISR call goes here! */ +@ +@ /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.3 Nested IRQ Support + +By default, nested IRQ interrupt support is not enabled. To enable nested +IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING +defined. With this defined, two new IRQ interrupt management services are +available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. +These function should be called between the IRQ context save and restore +calls. + +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +by switching from IRQ mode to SYS mode and enabling IRQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.S. When nested IRQ interrupts are no +longer required, calling the _tx_thread_irq_nesting_end service disables +nesting by disabling IRQ interrupts and switching back to IRQ mode in +preparation for the IRQ context restore service. + +The following is an example of enabling IRQ nested interrupts in a standard +IRQ handler: + + .global __tx_irq_handler + .global __tx_irq_processing_return +__tx_irq_handler: +@ +@ /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return: +@ +@ /* Enable nested IRQ interrupts. NOTE: Since this service returns +@ with IRQ interrupts enabled, all IRQ interrupt sources must be +@ cleared prior to calling this service. */ + BL _tx_thread_irq_nesting_start +@ +@ /* Application ISR call(s) go here! */ +@ +@ /* Disable nested IRQ interrupts. The mode is switched back to +@ IRQ mode and IRQ interrupts are disable upon return. */ + BL _tx_thread_irq_nesting_end +@ +@ /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.3 FIQ Interrupts + +By default, FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made +from default FIQ ISRs, which is located in tx_initialize_low_level.S. + + +7.3.1 Managed FIQ Interrupts + +Full ThreadX management of FIQ interrupts is provided if the ThreadX sources +are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built +this way, the FIQ interrupt handlers are very similar to the IRQ interrupt +handlers defined previously. The following is default FIQ handler +defined in tx_initialize_low_level.S: + + + .global __tx_fiq_handler + .global __tx_fiq_processing_return +__tx_fiq_handler: +@ +@ /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +@ +@ /* At this point execution is still in the FIQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. */ +@ +@ /* Application FIQ handlers can be called here! */ +@ +@ /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +7.3.1.1 Nested FIQ Support + +By default, nested FIQ interrupt support is not enabled. To enable nested +FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING +defined. With this defined, two new FIQ interrupt management services are +available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. +These function should be called between the FIQ context save and restore +calls. + +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +by switching from FIQ mode to SYS mode and enabling FIQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.S. When nested FIQ interrupts are no longer required, +calling the _tx_thread_fiq_nesting_end service disables nesting by disabling +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +context restore service. + +The following is an example of enabling FIQ nested interrupts in the +typical FIQ handler: + + + .global __tx_fiq_handler + .global __tx_fiq_processing_return +__tx_fiq_handler: +@ +@ /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +@ +@ /* At this point execution is still in the FIQ mode. The CPSR, point of +@ interrupt, and all C scratch registers are available for use. */ +@ +@ /* Enable nested FIQ interrupts. NOTE: Since this service returns +@ with FIQ interrupts enabled, all FIQ interrupt sources must be +@ cleared prior to calling this service. */ + BL _tx_thread_fiq_nesting_start +@ +@ /* Application FIQ handlers can be called here! */ +@ +@ /* Disable nested FIQ interrupts. The mode is switched back to +@ FIQ mode and FIQ interrupts are disable upon return. */ + BL _tx_thread_fiq_nesting_end +@ +@ /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +8. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional but the remainder of +ThreadX will still run. + +To add the timer interrupt processing, simply make a call to +_tx_timer_interrupt in the IRQ processing. An example of this can be +found in the file tx_initialize_low_level.S for the demonstration system. + + +9. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX 6.0.1 version for Cortex-R5 using AC6 tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports/cortex_r5/ac6/src/tx_thread_context_restore.S b/ports/cortex_r5/ac6/src/tx_thread_context_restore.S new file mode 100644 index 00000000..91ea27dc --- /dev/null +++ b/ports/cortex_r5/ac6/src/tx_thread_context_restore.S @@ -0,0 +1,255 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ + .arm + +#ifdef TX_ENABLE_FIQ_SUPPORT +SVC_MODE = 0xD3 @ Disable IRQ/FIQ, SVC mode +IRQ_MODE = 0xD2 @ Disable IRQ/FIQ, IRQ mode +#else +SVC_MODE = 0x93 @ Disable IRQ, SVC mode +IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode +#endif +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_restore Cortex-R5/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function restores the interrupt context if it is processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs Interrupt Service Routines */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_restore(VOID) +@{ + .global _tx_thread_context_restore + .type _tx_thread_context_restore,function +_tx_thread_context_restore: +@ +@ /* Lockout interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR exit function to indicate an ISR is complete. */ +@ + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif +@ +@ /* Determine if interrupts are nested. */ +@ if (--_tx_thread_system_state) +@ { +@ + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + SUB r2, r2, #1 @ Decrement the counter + STR r2, [r3] @ Store the counter + CMP r2, #0 @ Was this the first interrupt? + BEQ __tx_thread_not_nested_restore @ If so, not a nested restore +@ +@ /* Interrupts are nested. */ +@ +@ /* Just recover the saved registers and return to the point of +@ interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +__tx_thread_not_nested_restore: +@ +@ /* Determine if a thread was interrupted and no preemption is required. */ +@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +@ || (_tx_thread_preempt_disable)) +@ { +@ + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup actual current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_restore @ Yes, idle system was interrupted +@ + LDR r3, =_tx_thread_preempt_disable @ Pickup preempt disable address + LDR r2, [r3] @ Pickup actual preempt disable flag + CMP r2, #0 @ Is it set? + BNE __tx_thread_no_preempt_restore @ Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr @ Pickup address of execute thread ptr + LDR r2, [r3] @ Pickup actual execute thread pointer + CMP r0, r2 @ Is the same thread highest priority? + BNE __tx_thread_preempt_restore @ No, preemption needs to happen +@ +@ +__tx_thread_no_preempt_restore: +@ +@ /* Restore interrupted thread or ISR. */ +@ +@ /* Pickup the saved stack pointer. */ +@ tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +@ +@ /* Recover the saved context and return to the point of interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +@ else +@ { +__tx_thread_preempt_restore: +@ + LDMIA sp!, {r3, r10, r12, lr} @ Recover temporarily saved registers + MOV r1, lr @ Save lr (point of interrupt) + MOV r2, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r2 @ Enter SVC mode + STR r1, [sp, #-4]! @ Save point of interrupt + STMDB sp!, {r4-r12, lr} @ Save upper half of registers + MOV r4, r3 @ Save SPSR in r4 + MOV r2, #IRQ_MODE @ Build IRQ mode CPSR + MSR CPSR_c, r2 @ Enter IRQ mode + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOV r5, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r5 @ Enter SVC mode + STMDB sp!, {r0-r3} @ Save r0-r3 on thread's stack +@ + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer +@ +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r2, [r0, #144] @ Pickup the VFP enabled flag + CMP r2, #0 @ Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save @ No, skip VFP IRQ save + VMRS r2, FPSCR @ Pickup the FPSCR + STR r2, [sp, #-4]! @ Save FPSCR + VSTMDB sp!, {D0-D15} @ Save D0-D15 +_tx_skip_irq_vfp_save: +#endif +@ + MOV r3, #1 @ Build interrupt stack type + STMDB sp!, {r3, r4} @ Save interrupt stack type and SPSR + STR sp, [r0, #8] @ Save stack pointer in thread control + @ block +@ +@ /* Save the remaining time-slice and disable it. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup time-slice variable address + LDR r2, [r3] @ Pickup time-slice + CMP r2, #0 @ Is it active? + BEQ __tx_thread_dont_save_ts @ No, don't save it +@ +@ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +@ _tx_timer_time_slice = 0; +@ + STR r2, [r0, #24] @ Save thread's time-slice + MOV r2, #0 @ Clear value + STR r2, [r3] @ Disable global time-slice flag +@ +@ } +__tx_thread_dont_save_ts: +@ +@ +@ /* Clear the current task pointer. */ +@ _tx_thread_current_ptr = TX_NULL; +@ + MOV r0, #0 @ NULL value + STR r0, [r1] @ Clear current thread pointer +@ +@ /* Return to the scheduler. */ +@ _tx_thread_schedule(); +@ + B _tx_thread_schedule @ Return to scheduler +@ } +@ +__tx_thread_idle_system_restore: +@ +@ /* Just return back to the scheduler! */ +@ + MOV r0, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r0 @ Enter SVC mode + B _tx_thread_schedule @ Return to scheduler +@} + + + diff --git a/ports/cortex_r5/ac6/src/tx_thread_context_save.S b/ports/cortex_r5/ac6/src/tx_thread_context_save.S new file mode 100644 index 00000000..25368660 --- /dev/null +++ b/ports/cortex_r5/ac6/src/tx_thread_context_save.S @@ -0,0 +1,202 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global __tx_irq_processing_return +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_save Cortex-R5/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_save(VOID) +@{ + .global _tx_thread_context_save + .type _tx_thread_context_save,function +_tx_thread_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state++) +@ { +@ + STMDB sp!, {r0-r3} @ Save some working registers +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable FIQ interrupts +#endif + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable +@ +@ /* Save the rest of the scratch registers on the stack and return to the +@ calling ISR. */ +@ + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} @ Store other registers +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_irq_processing_return @ Continue IRQ processing +@ +__tx_thread_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + @ scheduling loop - nothing needs saving! +@ +@ /* Save minimal context of interrupted thread. */ +@ + MRS r2, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r2, r10, r12, lr} @ Store other registers +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr@ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_irq_processing_return @ Continue IRQ processing +@ +@ } +@ else +@ { +@ +__tx_thread_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ processing. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + ADD sp, sp, #16 @ Recover saved registers + B __tx_irq_processing_return @ Continue IRQ processing +@ +@ } +@} + + + diff --git a/ports/cortex_r5/ac6/src/tx_thread_fiq_context_restore.S b/ports/cortex_r5/ac6/src/tx_thread_fiq_context_restore.S new file mode 100644 index 00000000..bcd9072c --- /dev/null +++ b/ports/cortex_r5/ac6/src/tx_thread_fiq_context_restore.S @@ -0,0 +1,246 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ +SVC_MODE = 0xD3 @ SVC mode +FIQ_MODE = 0xD1 @ FIQ mode +MODE_MASK = 0x1F @ Mode mask +THUMB_MASK = 0x20 @ Thumb bit mask +IRQ_MODE_BITS = 0x12 @ IRQ mode bits +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_system_stack_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_context_restore +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_context_restore Cortex-R5/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function restores the fiq interrupt context when processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* FIQ ISR Interrupt Service Routines */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_fiq_context_restore(VOID) +@{ + .global _tx_thread_fiq_context_restore + .type _tx_thread_fiq_context_restore,function +_tx_thread_fiq_context_restore: +@ +@ /* Lockout interrupts. */ +@ + CPSID if @ Disable IRQ and FIQ interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR exit function to indicate an ISR is complete. */ +@ + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif +@ +@ /* Determine if interrupts are nested. */ +@ if (--_tx_thread_system_state) +@ { +@ + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + SUB r2, r2, #1 @ Decrement the counter + STR r2, [r3] @ Store the counter + CMP r2, #0 @ Was this the first interrupt? + BEQ __tx_thread_fiq_not_nested_restore @ If so, not a nested restore +@ +@ /* Interrupts are nested. */ +@ +@ /* Just recover the saved registers and return to the point of +@ interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +__tx_thread_fiq_not_nested_restore: +@ +@ /* Determine if a thread was interrupted and no preemption is required. */ +@ else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +@ || (_tx_thread_preempt_disable)) +@ { +@ + LDR r1, [sp] @ Pickup the saved SPSR + MOV r2, #MODE_MASK @ Build mask to isolate the interrupted mode + AND r1, r1, r2 @ Isolate mode bits + CMP r1, #IRQ_MODE_BITS @ Was an interrupt taken in IRQ mode before we + @ got to context save? */ + BEQ __tx_thread_fiq_no_preempt_restore @ Yes, just go back to point of interrupt + + + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup actual current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_fiq_idle_system_restore @ Yes, idle system was interrupted + + LDR r3, =_tx_thread_preempt_disable @ Pickup preempt disable address + LDR r2, [r3] @ Pickup actual preempt disable flag + CMP r2, #0 @ Is it set? + BNE __tx_thread_fiq_no_preempt_restore @ Yes, don't preempt this thread + LDR r3, =_tx_thread_execute_ptr @ Pickup address of execute thread ptr + LDR r2, [r3] @ Pickup actual execute thread pointer + CMP r0, r2 @ Is the same thread highest priority? + BNE __tx_thread_fiq_preempt_restore @ No, preemption needs to happen + + +__tx_thread_fiq_no_preempt_restore: +@ +@ /* Restore interrupted thread or ISR. */ +@ +@ /* Pickup the saved stack pointer. */ +@ tmp_ptr = _tx_thread_current_ptr -> tx_thread_stack_ptr; +@ +@ /* Recover the saved context and return to the point of interrupt. */ +@ + LDMIA sp!, {r0, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +@ else +@ { +__tx_thread_fiq_preempt_restore: +@ + LDMIA sp!, {r3, lr} @ Recover temporarily saved registers + MOV r1, lr @ Save lr (point of interrupt) + MOV r2, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r2 @ Enter SVC mode + STR r1, [sp, #-4]! @ Save point of interrupt + STMDB sp!, {r4-r12, lr} @ Save upper half of registers + MOV r4, r3 @ Save SPSR in r4 + MOV r2, #FIQ_MODE @ Build FIQ mode CPSR + MSR CPSR_c, r2 @ Reenter FIQ mode + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOV r5, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r5 @ Enter SVC mode + STMDB sp!, {r0-r3} @ Save r0-r3 on thread's stack + MOV r3, #1 @ Build interrupt stack type + STMDB sp!, {r3, r4} @ Save interrupt stack type and SPSR + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + STR sp, [r0, #8] @ Save stack pointer in thread control + @ block */ +@ +@ /* Save the remaining time-slice and disable it. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup time-slice variable address + LDR r2, [r3] @ Pickup time-slice + CMP r2, #0 @ Is it active? + BEQ __tx_thread_fiq_dont_save_ts @ No, don't save it +@ +@ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +@ _tx_timer_time_slice = 0; +@ + STR r2, [r0, #24] @ Save thread's time-slice + MOV r2, #0 @ Clear value + STR r2, [r3] @ Disable global time-slice flag +@ +@ } +__tx_thread_fiq_dont_save_ts: +@ +@ +@ /* Clear the current task pointer. */ +@ _tx_thread_current_ptr = TX_NULL; +@ + MOV r0, #0 @ NULL value + STR r0, [r1] @ Clear current thread pointer +@ +@ /* Return to the scheduler. */ +@ _tx_thread_schedule(); +@ + B _tx_thread_schedule @ Return to scheduler +@ } +@ +__tx_thread_fiq_idle_system_restore: +@ +@ /* Just return back to the scheduler! */ +@ + ADD sp, sp, #24 @ Recover FIQ stack space + MOV r3, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r3 @ Lockout interrupts + B _tx_thread_schedule @ Return to scheduler +@ +@} + diff --git a/ports/cortex_r5/ac6/src/tx_thread_fiq_context_save.S b/ports/cortex_r5/ac6/src/tx_thread_fiq_context_save.S new file mode 100644 index 00000000..0ae85699 --- /dev/null +++ b/ports/cortex_r5/ac6/src/tx_thread_fiq_context_save.S @@ -0,0 +1,203 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global __tx_fiq_processing_return +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_context_save +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_context_save Cortex-R5/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@ VOID _tx_thread_fiq_context_save(VOID) +@{ + .global _tx_thread_fiq_context_save + .type _tx_thread_fiq_context_save,function +_tx_thread_fiq_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state++) +@ { +@ + STMDB sp!, {r0-r3} @ Save some working registers + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_fiq_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable +@ +@ /* Save the rest of the scratch registers on the stack and return to the +@ calling ISR. */ +@ + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} @ Store other registers +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_fiq_processing_return @ Continue FIQ processing +@ +__tx_thread_fiq_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_fiq_idle_system_save @ If so, interrupt occurred in +@ @ scheduling loop - nothing needs saving! +@ +@ /* Save minimal context of interrupted thread. */ +@ + MRS r2, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r2, lr} @ Store other registers, Note that we don't +@ @ need to save sl and ip since FIQ has +@ @ copies of these registers. Nested +@ @ interrupt processing does need to save +@ @ these registers. +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr; +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + B __tx_fiq_processing_return @ Continue FIQ processing +@ +@ } +@ else +@ { +@ +__tx_thread_fiq_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif +@ +@ /* Not much to do here, save the current SPSR and LR for possible +@ use in IRQ interrupted in idle system conditions, and return to +@ FIQ interrupt processing. */ +@ + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, lr} @ Store other registers that will get used +@ @ or stripped off the stack in context +@ @ restore + B __tx_fiq_processing_return @ Continue FIQ processing +@ +@ } +@} + diff --git a/ports/cortex_r5/ac6/src/tx_thread_fiq_nesting_end.S b/ports/cortex_r5/ac6/src/tx_thread_fiq_nesting_end.S new file mode 100644 index 00000000..b7c7edbf --- /dev/null +++ b/ports/cortex_r5/ac6/src/tx_thread_fiq_nesting_end.S @@ -0,0 +1,116 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts +#else +DISABLE_INTS = 0x80 @ Disable IRQ interrupts +#endif +MODE_MASK = 0x1F @ Mode mask +FIQ_MODE_BITS = 0x11 @ FIQ mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_end +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_nesting_end Cortex-R5/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from FIQ mode after */ +@/* _tx_thread_fiq_nesting_start has been called and switches the FIQ */ +@/* processing from system mode back to FIQ mode prior to the ISR */ +@/* calling _tx_thread_fiq_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with FIQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_fiq_nesting_end(VOID) +@{ + .global _tx_thread_fiq_nesting_end + .type _tx_thread_fiq_nesting_end,function +_tx_thread_fiq_nesting_end: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value + MSR CPSR_c, r0 @ Disable interrupts + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + @ 8-byte alignment logic) + BIC r0, r0, #MODE_MASK @ Clear mode bits + ORR r0, r0, #FIQ_MODE_BITS @ Build IRQ mode CPSR + MSR CPSR_c, r0 @ Reenter IRQ mode + +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_r5/ac6/src/tx_thread_fiq_nesting_start.S b/ports/cortex_r5/ac6/src/tx_thread_fiq_nesting_start.S new file mode 100644 index 00000000..8ad04e55 --- /dev/null +++ b/ports/cortex_r5/ac6/src/tx_thread_fiq_nesting_start.S @@ -0,0 +1,108 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +FIQ_DISABLE = 0x40 @ FIQ disable bit +MODE_MASK = 0x1F @ Mode mask +SYS_MODE_BITS = 0x1F @ System mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_fiq_nesting_start +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_fiq_nesting_start Cortex-R5/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from FIQ mode after */ +@/* _tx_thread_fiq_context_save has been called and switches the FIQ */ +@/* processing to the system mode so nested FIQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with FIQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_fiq_nesting_start(VOID) +@{ + .global _tx_thread_fiq_nesting_start + .type _tx_thread_fiq_nesting_start,function +_tx_thread_fiq_nesting_start: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + BIC r0, r0, #MODE_MASK @ Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS @ Build system mode CPSR + MSR CPSR_c, r0 @ Enter system mode + STMDB sp!, {r1, lr} @ Push the system mode lr on the system mode stack + @ and push r1 just to keep 8-byte alignment + BIC r0, r0, #FIQ_DISABLE @ Build enable FIQ CPSR + MSR CPSR_c, r0 @ Enter system mode +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_r5/ac6/src/tx_thread_interrupt_control.S b/ports/cortex_r5/ac6/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..6cbb502d --- /dev/null +++ b/ports/cortex_r5/ac6/src/tx_thread_interrupt_control.S @@ -0,0 +1,115 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" */ +@ + +INT_MASK = 0x03F + +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_control for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_interrupt_control +$_tx_thread_interrupt_control: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_interrupt_control @ Call _tx_thread_interrupt_control function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_control Cortex-R5/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for changing the interrupt lockout */ +@/* posture of the system. */ +@/* */ +@/* INPUT */ +@/* */ +@/* new_posture New interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_control(UINT new_posture) +@{ + .global _tx_thread_interrupt_control + .type _tx_thread_interrupt_control,function +_tx_thread_interrupt_control: +@ +@ /* Pickup current interrupt lockout posture. */ +@ + MRS r3, CPSR @ Pickup current CPSR + MOV r2, #INT_MASK @ Build interrupt mask + AND r1, r3, r2 @ Clear interrupt lockout bits + ORR r1, r1, r0 @ Or-in new interrupt lockout bits +@ +@ /* Apply the new interrupt posture. */ +@ + MSR CPSR_c, r1 @ Setup new CPSR + BIC r0, r3, r2 @ Return previous interrupt mask +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + diff --git a/ports/cortex_r5/ac6/src/tx_thread_interrupt_disable.S b/ports/cortex_r5/ac6/src/tx_thread_interrupt_disable.S new file mode 100644 index 00000000..0a50e7b0 --- /dev/null +++ b/ports/cortex_r5/ac6/src/tx_thread_interrupt_disable.S @@ -0,0 +1,113 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_interrupt_disable +$_tx_thread_interrupt_disable: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_interrupt_disable @ Call _tx_thread_interrupt_disable function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_disable Cortex-R5/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for disabling interrupts */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_disable(void) +@{ + .global _tx_thread_interrupt_disable + .type _tx_thread_interrupt_disable,function +_tx_thread_interrupt_disable: +@ +@ /* Pickup current interrupt lockout posture. */ +@ + MRS r0, CPSR @ Pickup current CPSR +@ +@ /* Mask interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ +#else + CPSID i @ Disable IRQ +#endif + +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + + diff --git a/ports/cortex_r5/ac6/src/tx_thread_interrupt_restore.S b/ports/cortex_r5/ac6/src/tx_thread_interrupt_restore.S new file mode 100644 index 00000000..b5af0546 --- /dev/null +++ b/ports/cortex_r5/ac6/src/tx_thread_interrupt_restore.S @@ -0,0 +1,104 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_interrupt_restore +$_tx_thread_interrupt_restore: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_interrupt_restore @ Call _tx_thread_interrupt_restore function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_restore Cortex-R5/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for restoring interrupts to the state */ +@/* returned by a previous _tx_thread_interrupt_disable call. */ +@/* */ +@/* INPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_restore(UINT old_posture) +@{ + .global _tx_thread_interrupt_restore + .type _tx_thread_interrupt_restore,function +_tx_thread_interrupt_restore: +@ +@ /* Apply the new interrupt posture. */ +@ + MSR CPSR_c, r0 @ Setup new CPSR +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + diff --git a/ports/cortex_r5/ac6/src/tx_thread_irq_nesting_end.S b/ports/cortex_r5/ac6/src/tx_thread_irq_nesting_end.S new file mode 100644 index 00000000..829e20b8 --- /dev/null +++ b/ports/cortex_r5/ac6/src/tx_thread_irq_nesting_end.S @@ -0,0 +1,115 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts +#else +DISABLE_INTS = 0x80 @ Disable IRQ interrupts +#endif +MODE_MASK = 0x1F @ Mode mask +IRQ_MODE_BITS = 0x12 @ IRQ mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_end +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_end Cortex-R5/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +@/* processing from system mode back to IRQ mode prior to the ISR */ +@/* calling _tx_thread_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_irq_nesting_end(VOID) +@{ + .global _tx_thread_irq_nesting_end + .type _tx_thread_irq_nesting_end,function +_tx_thread_irq_nesting_end: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value + MSR CPSR_c, r0 @ Disable interrupts + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + @ 8-byte alignment logic) + BIC r0, r0, #MODE_MASK @ Clear mode bits + ORR r0, r0, #IRQ_MODE_BITS @ Build IRQ mode CPSR + MSR CPSR_c, r0 @ Reenter IRQ mode +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_r5/ac6/src/tx_thread_irq_nesting_start.S b/ports/cortex_r5/ac6/src/tx_thread_irq_nesting_start.S new file mode 100644 index 00000000..10e834fd --- /dev/null +++ b/ports/cortex_r5/ac6/src/tx_thread_irq_nesting_start.S @@ -0,0 +1,108 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +IRQ_DISABLE = 0x80 @ IRQ disable bit +MODE_MASK = 0x1F @ Mode mask +SYS_MODE_BITS = 0x1F @ System mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_start +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_start Cortex-R5/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_context_save has been called and switches the IRQ */ +@/* processing to the system mode so nested IRQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_irq_nesting_start(VOID) +@{ + .global _tx_thread_irq_nesting_start + .type _tx_thread_irq_nesting_start,function +_tx_thread_irq_nesting_start: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + BIC r0, r0, #MODE_MASK @ Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS @ Build system mode CPSR + MSR CPSR_c, r0 @ Enter system mode + STMDB sp!, {r1, lr} @ Push the system mode lr on the system mode stack + @ and push r1 just to keep 8-byte alignment + BIC r0, r0, #IRQ_DISABLE @ Build enable IRQ CPSR + MSR CPSR_c, r0 @ Enter system mode +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + diff --git a/ports/cortex_r5/ac6/src/tx_thread_schedule.S b/ports/cortex_r5/ac6/src/tx_thread_schedule.S new file mode 100644 index 00000000..537a6b90 --- /dev/null +++ b/ports/cortex_r5/ac6/src/tx_thread_schedule.S @@ -0,0 +1,249 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_execute_ptr + .global _tx_thread_current_ptr + .global _tx_timer_time_slice +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_schedule for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_schedule + .type $_tx_thread_schedule,function +$_tx_thread_schedule: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_schedule @ Call _tx_thread_schedule function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_schedule Cortex-R5/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function waits for a thread control block pointer to appear in */ +@/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +@/* in the variable, the corresponding thread is resumed. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* _tx_thread_system_return Return to system from thread */ +@/* _tx_thread_context_restore Restore thread's context */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_schedule(VOID) +@{ + .global _tx_thread_schedule + .type _tx_thread_schedule,function +_tx_thread_schedule: +@ +@ /* Enable interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSIE if @ Enable IRQ and FIQ interrupts +#else + CPSIE i @ Enable IRQ interrupts +#endif +@ +@ /* Wait for a thread to execute. */ +@ do +@ { + LDR r1, =_tx_thread_execute_ptr @ Address of thread execute ptr +@ +__tx_thread_schedule_loop: +@ + LDR r0, [r1] @ Pickup next thread to execute + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_schedule_loop @ If so, keep looking for a thread +@ +@ } +@ while(_tx_thread_execute_ptr == TX_NULL); +@ +@ /* Yes! We have a thread to execute. Lockout interrupts and +@ transfer control to it. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif +@ +@ /* Setup the current thread pointer. */ +@ _tx_thread_current_ptr = _tx_thread_execute_ptr; +@ + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread + STR r0, [r1] @ Setup current thread pointer +@ +@ /* Increment the run count for this thread. */ +@ _tx_thread_current_ptr -> tx_thread_run_count++; +@ + LDR r2, [r0, #4] @ Pickup run counter + LDR r3, [r0, #24] @ Pickup time-slice for this thread + ADD r2, r2, #1 @ Increment thread run-counter + STR r2, [r0, #4] @ Store the new run counter +@ +@ /* Setup time-slice, if present. */ +@ _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; +@ + LDR r2, =_tx_timer_time_slice @ Pickup address of time-slice + @ variable + LDR sp, [r0, #8] @ Switch stack pointers + STR r3, [r2] @ Setup time-slice +@ +@ /* Switch to the thread's stack. */ +@ sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; +@ +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the thread entry function to indicate the thread is executing. */ +@ + BL _tx_execution_thread_enter @ Call the thread execution enter function +#endif +@ +@ /* Determine if an interrupt frame or a synchronous task suspension frame +@ is present. */ +@ + LDMIA sp!, {r4, r5} @ Pickup the stack type and saved CPSR + CMP r4, #0 @ Check for synchronous context switch + BEQ _tx_solicited_return + MSR SPSR_cxsf, r5 @ Setup SPSR for return +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r1, [r0, #144] @ Pickup the VFP enabled flag + CMP r1, #0 @ Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore @ No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} @ Recover D0-D15 + LDR r4, [sp], #4 @ Pickup FPSCR + VMSR FPSCR, r4 @ Restore FPSCR +_tx_skip_interrupt_vfp_restore: +#endif + LDMIA sp!, {r0-r12, lr, pc}^ @ Return to point of thread interrupt +@ +_tx_solicited_return: +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r1, [r0, #144] @ Pickup the VFP enabled flag + CMP r1, #0 @ Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore @ No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} @ Recover D8-D15 + LDR r4, [sp], #4 @ Pickup FPSCR + VMSR FPSCR, r4 @ Restore FPSCR +_tx_skip_solicited_vfp_restore: +#endif + MOV r0, r5 @ Move CPSR to scratch register + LDMIA sp!, {r4-r11, lr} @ Return to thread synchronously + MSR CPSR_cxsf, r0 @ Recover CPSR +@ +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@ +@} +@ +@ +#ifdef TX_ENABLE_VFP_SUPPORT + .global tx_thread_vfp_enable + .type tx_thread_vfp_enable,function +tx_thread_vfp_enable: + MRS r2, CPSR @ Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address + LDR r1, [r0] @ Pickup current thread pointer + CMP r1, #0 @ Check for NULL thread pointer + BEQ __tx_no_thread_to_enable @ If NULL, skip VFP enable + MOV r0, #1 @ Build enable value + STR r0, [r1, #144] @ Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable: + MSR CPSR_cxsf, r2 @ Recover CPSR + BX LR @ Return to caller +@ + .global tx_thread_vfp_disable + .type tx_thread_vfp_disable,function +tx_thread_vfp_disable: + MRS r2, CPSR @ Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif + LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address + LDR r1, [r0] @ Pickup current thread pointer + CMP r1, #0 @ Check for NULL thread pointer + BEQ __tx_no_thread_to_disable @ If NULL, skip VFP disable + MOV r0, #0 @ Build disable value + STR r0, [r1, #144] @ Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable: + MSR CPSR_cxsf, r2 @ Recover CPSR + BX LR @ Return to caller +#endif + diff --git a/ports/cortex_r5/ac6/src/tx_thread_stack_build.S b/ports/cortex_r5/ac6/src/tx_thread_stack_build.S new file mode 100644 index 00000000..21fa32e9 --- /dev/null +++ b/ports/cortex_r5/ac6/src/tx_thread_stack_build.S @@ -0,0 +1,178 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ + .arm + +SVC_MODE = 0x13 @ SVC mode +#ifdef TX_ENABLE_FIQ_SUPPORT +CPSR_MASK = 0xDF @ Mask initial CPSR, IRQ & FIQ interrupts enabled +#else +CPSR_MASK = 0x9F @ Mask initial CPSR, IRQ interrupts enabled +#endif +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_stack_build for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .thumb + .global $_tx_thread_stack_build + .type $_tx_thread_stack_build,function +$_tx_thread_stack_build: + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_stack_build @ Call _tx_thread_stack_build function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_stack_build Cortex-R5/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function builds a stack frame on the supplied thread's stack. */ +@/* The stack frame results in a fake interrupt return to the supplied */ +@/* function pointer. */ +@/* */ +@/* INPUT */ +@/* */ +@/* thread_ptr Pointer to thread control blk */ +@/* function_ptr Pointer to return function */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_thread_create Create thread service */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +@{ + .global _tx_thread_stack_build + .type _tx_thread_stack_build,function +_tx_thread_stack_build: +@ +@ +@ /* Build a fake interrupt frame. The form of the fake interrupt stack +@ on the ARM9 should look like the following after it is built: +@ +@ Stack Top: 1 Interrupt stack frame type +@ CPSR Initial value for CPSR +@ a1 (r0) Initial value for a1 +@ a2 (r1) Initial value for a2 +@ a3 (r2) Initial value for a3 +@ a4 (r3) Initial value for a4 +@ v1 (r4) Initial value for v1 +@ v2 (r5) Initial value for v2 +@ v3 (r6) Initial value for v3 +@ v4 (r7) Initial value for v4 +@ v5 (r8) Initial value for v5 +@ sb (r9) Initial value for sb +@ sl (r10) Initial value for sl +@ fp (r11) Initial value for fp +@ ip (r12) Initial value for ip +@ lr (r14) Initial value for lr +@ pc (r15) Initial value for pc +@ 0 For stack backtracing +@ +@ Stack Bottom: (higher memory address) */ +@ + LDR r2, [r0, #16] @ Pickup end of stack area + BIC r2, r2, #7 @ Ensure 8-byte alignment + SUB r2, r2, #76 @ Allocate space for the stack frame +@ +@ /* Actually build the stack frame. */ +@ + MOV r3, #1 @ Build interrupt stack type + STR r3, [r2, #0] @ Store stack type + MOV r3, #0 @ Build initial register value + STR r3, [r2, #8] @ Store initial r0 + STR r3, [r2, #12] @ Store initial r1 + STR r3, [r2, #16] @ Store initial r2 + STR r3, [r2, #20] @ Store initial r3 + STR r3, [r2, #24] @ Store initial r4 + STR r3, [r2, #28] @ Store initial r5 + STR r3, [r2, #32] @ Store initial r6 + STR r3, [r2, #36] @ Store initial r7 + STR r3, [r2, #40] @ Store initial r8 + STR r3, [r2, #44] @ Store initial r9 + LDR r3, [r0, #12] @ Pickup stack starting address + STR r3, [r2, #48] @ Store initial r10 (sl) + LDR r3,=_tx_thread_schedule @ Pickup address of _tx_thread_schedule for GDB backtrace + STR r3, [r2, #60] @ Store initial r14 (lr) + MOV r3, #0 @ Build initial register value + STR r3, [r2, #52] @ Store initial r11 + STR r3, [r2, #56] @ Store initial r12 + STR r1, [r2, #64] @ Store initial pc + STR r3, [r2, #68] @ 0 for back-trace + MRS r1, CPSR @ Pickup CPSR + BIC r1, r1, #CPSR_MASK @ Mask mode bits of CPSR + ORR r3, r1, #SVC_MODE @ Build CPSR, SVC mode, interrupts enabled + STR r3, [r2, #4] @ Store initial CPSR +@ +@ /* Setup stack pointer. */ +@ thread_ptr -> tx_thread_stack_ptr = r2; +@ + STR r2, [r0, #8] @ Save stack pointer in thread's + @ control block +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + + diff --git a/ports/cortex_r5/ac6/src/tx_thread_system_return.S b/ports/cortex_r5/ac6/src/tx_thread_system_return.S new file mode 100644 index 00000000..55721890 --- /dev/null +++ b/ports/cortex_r5/ac6/src/tx_thread_system_return.S @@ -0,0 +1,176 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ + .arm +@ +@ + .global _tx_thread_current_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule +@ +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_system_return for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_system_return + .type $_tx_thread_system_return,function +$_tx_thread_system_return: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_system_return @ Call _tx_thread_system_return function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_system_return Cortex-R5/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is target processor specific. It is used to transfer */ +@/* control from a thread back to the ThreadX system. Only a */ +@/* minimal context is saved since the compiler assumes temp registers */ +@/* are going to get slicked by a function call anyway. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling loop */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX components */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_system_return(VOID) +@{ + .global _tx_thread_system_return + .type _tx_thread_system_return,function +_tx_thread_system_return: +@ +@ /* Lockout interrupts. */ +@ + MRS r1, CPSR @ Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif +@ /* Save minimal context on the stack. */ +@ + STMDB sp!, {r4-r11, lr} @ Save minimal context + LDR r5, =_tx_thread_current_ptr @ Pickup address of current ptr + LDR r6, [r5, #0] @ Pickup current thread pointer +@ +#ifdef TX_ENABLE_VFP_SUPPORT + LDR r0, [r6, #144] @ Pickup the VFP enabled flag + CMP r0, #0 @ Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save @ No, skip VFP solicited save + VMRS r4, FPSCR @ Pickup the FPSCR + STR r4, [sp, #-4]! @ Save FPSCR + VSTMDB sp!, {D8-D15} @ Save D8-D15 +_tx_skip_solicited_vfp_save: +#endif +@ + MOV r0, #0 @ Build a solicited stack type + STMDB sp!, {r0-r1} @ Save type and CPSR +@ +@ +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the thread exit function to indicate the thread is no longer executing. */ +@ + BL _tx_execution_thread_exit @ Call the thread exit function +#endif +@ + LDR r2, =_tx_timer_time_slice @ Pickup address of time slice + LDR r1, [r2, #0] @ Pickup current time slice +@ +@ /* Save current stack and switch to system stack. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ sp = _tx_thread_system_stack_ptr; +@ + STR sp, [r6, #8] @ Save thread stack pointer +@ +@ /* Determine if the time-slice is active. */ +@ if (_tx_timer_time_slice) +@ { +@ + MOV r4, #0 @ Build clear value + CMP r1, #0 @ Is a time-slice active? + BEQ __tx_thread_dont_save_ts @ No, don't save the time-slice +@ +@ /* Save time-slice for the thread and clear the current time-slice. */ +@ _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; +@ _tx_timer_time_slice = 0; +@ + STR r4, [r2, #0] @ Clear time-slice + STR r1, [r6, #24] @ Save current time-slice +@ +@ } +__tx_thread_dont_save_ts: +@ +@ /* Clear the current thread pointer. */ +@ _tx_thread_current_ptr = TX_NULL; +@ + STR r4, [r5, #0] @ Clear current thread pointer + B _tx_thread_schedule @ Jump to scheduler! +@ +@} + diff --git a/ports/cortex_r5/ac6/src/tx_thread_vectored_context_save.S b/ports/cortex_r5/ac6/src/tx_thread_vectored_context_save.S new file mode 100644 index 00000000..00ed6fbf --- /dev/null +++ b/ports/cortex_r5/ac6/src/tx_thread_vectored_context_save.S @@ -0,0 +1,189 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr +@ +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_vectored_context_save +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_vectored_context_save Cortex-R5/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_vectored_context_save(VOID) +@{ + .global _tx_thread_vectored_context_save + .type _tx_thread_vectored_context_save,function +_tx_thread_vectored_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state++) +@ { +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#endif + LDR r3, =_tx_thread_system_state @ Pickup address of system state variable + LDR r2, [r3, #0] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3, #0] @ Store it back in the variable +@ +@ /* Note: Minimal context of interrupted thread is already saved. */ +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + MOV pc, lr @ Return to caller +@ +__tx_thread_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3, #0] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + LDR r0, [r1, #0] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + @ scheduling loop - nothing needs saving! +@ +@ /* Note: Minimal context of interrupted thread is already saved. */ +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr; +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + MOV pc, lr @ Return to caller +@ +@ } +@ else +@ { +@ +__tx_thread_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ processing. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {lr} @ Save ISR lr + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {lr} @ Recover ISR lr +#endif + + ADD sp, sp, #32 @ Recover saved registers + MOV pc, lr @ Return to caller +@ +@ } +@} + diff --git a/ports/cortex_r5/ac6/src/tx_timer_interrupt.S b/ports/cortex_r5/ac6/src/tx_timer_interrupt.S new file mode 100644 index 00000000..899853e7 --- /dev/null +++ b/ports/cortex_r5/ac6/src/tx_timer_interrupt.S @@ -0,0 +1,279 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Timer */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_timer.h" +@#include "tx_thread.h" +@ +@ + .arm + +@ +@/* Define Assembly language external references... */ +@ + .global _tx_timer_time_slice + .global _tx_timer_system_clock + .global _tx_timer_current_ptr + .global _tx_timer_list_start + .global _tx_timer_list_end + .global _tx_timer_expired_time_slice + .global _tx_timer_expired + .global _tx_thread_time_slice +@ +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_timer_interrupt for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .thumb + .global $_tx_timer_interrupt + .type $_tx_timer_interrupt,function +$_tx_timer_interrupt: + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_timer_interrupt @ Call _tx_timer_interrupt function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_timer_interrupt Cortex-R5/AC6 */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function processes the hardware timer interrupt. This */ +@/* processing includes incrementing the system clock and checking for */ +@/* time slice and/or timer expiration. If either is found, the */ +@/* interrupt context save/restore functions are called along with the */ +@/* expiration functions. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_time_slice Time slice interrupted thread */ +@/* _tx_timer_expiration_process Timer expiration processing */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* interrupt vector */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_timer_interrupt(VOID) +@{ + .global _tx_timer_interrupt + .type _tx_timer_interrupt,function +_tx_timer_interrupt: +@ +@ /* Upon entry to this routine, it is assumed that context save has already +@ been called, and therefore the compiler scratch registers are available +@ for use. */ +@ +@ /* Increment the system clock. */ +@ _tx_timer_system_clock++; +@ + LDR r1, =_tx_timer_system_clock @ Pickup address of system clock + LDR r0, [r1] @ Pickup system clock + ADD r0, r0, #1 @ Increment system clock + STR r0, [r1] @ Store new system clock +@ +@ /* Test for time-slice expiration. */ +@ if (_tx_timer_time_slice) +@ { +@ + LDR r3, =_tx_timer_time_slice @ Pickup address of time-slice + LDR r2, [r3] @ Pickup time-slice + CMP r2, #0 @ Is it non-active? + BEQ __tx_timer_no_time_slice @ Yes, skip time-slice processing +@ +@ /* Decrement the time_slice. */ +@ _tx_timer_time_slice--; +@ + SUB r2, r2, #1 @ Decrement the time-slice + STR r2, [r3] @ Store new time-slice value +@ +@ /* Check for expiration. */ +@ if (__tx_timer_time_slice == 0) +@ + CMP r2, #0 @ Has it expired? + BNE __tx_timer_no_time_slice @ No, skip expiration processing +@ +@ /* Set the time-slice expired flag. */ +@ _tx_timer_expired_time_slice = TX_TRUE; +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of expired flag + MOV r0, #1 @ Build expired value + STR r0, [r3] @ Set time-slice expiration flag +@ +@ } +@ +__tx_timer_no_time_slice: +@ +@ /* Test for timer expiration. */ +@ if (*_tx_timer_current_ptr) +@ { +@ + LDR r1, =_tx_timer_current_ptr @ Pickup current timer pointer address + LDR r0, [r1] @ Pickup current timer + LDR r2, [r0] @ Pickup timer list entry + CMP r2, #0 @ Is there anything in the list? + BEQ __tx_timer_no_timer @ No, just increment the timer +@ +@ /* Set expiration flag. */ +@ _tx_timer_expired = TX_TRUE; +@ + LDR r3, =_tx_timer_expired @ Pickup expiration flag address + MOV r2, #1 @ Build expired value + STR r2, [r3] @ Set expired flag + B __tx_timer_done @ Finished timer processing +@ +@ } +@ else +@ { +__tx_timer_no_timer: +@ +@ /* No timer expired, increment the timer pointer. */ +@ _tx_timer_current_ptr++; +@ + ADD r0, r0, #4 @ Move to next timer +@ +@ /* Check for wraparound. */ +@ if (_tx_timer_current_ptr == _tx_timer_list_end) +@ + LDR r3, =_tx_timer_list_end @ Pickup address of timer list end + LDR r2, [r3] @ Pickup list end + CMP r0, r2 @ Are we at list end? + BNE __tx_timer_skip_wrap @ No, skip wraparound logic +@ +@ /* Wrap to beginning of list. */ +@ _tx_timer_current_ptr = _tx_timer_list_start; +@ + LDR r3, =_tx_timer_list_start @ Pickup address of timer list start + LDR r0, [r3] @ Set current pointer to list start +@ +__tx_timer_skip_wrap: +@ + STR r0, [r1] @ Store new current timer pointer +@ } +@ +__tx_timer_done: +@ +@ +@ /* See if anything has expired. */ +@ if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +@ { +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of expired flag + LDR r2, [r3] @ Pickup time-slice expired flag + CMP r2, #0 @ Did a time-slice expire? + BNE __tx_something_expired @ If non-zero, time-slice expired + LDR r1, =_tx_timer_expired @ Pickup address of other expired flag + LDR r0, [r1] @ Pickup timer expired flag + CMP r0, #0 @ Did a timer expire? + BEQ __tx_timer_nothing_expired @ No, nothing expired +@ +__tx_something_expired: +@ +@ + STMDB sp!, {r0, lr} @ Save the lr register on the stack + @ and save r0 just to keep 8-byte alignment +@ +@ /* Did a timer expire? */ +@ if (_tx_timer_expired) +@ { +@ + LDR r1, =_tx_timer_expired @ Pickup address of expired flag + LDR r0, [r1] @ Pickup timer expired flag + CMP r0, #0 @ Check for timer expiration + BEQ __tx_timer_dont_activate @ If not set, skip timer activation +@ +@ /* Process timer expiration. */ +@ _tx_timer_expiration_process(); +@ + BL _tx_timer_expiration_process @ Call the timer expiration handling routine +@ +@ } +__tx_timer_dont_activate: +@ +@ /* Did time slice expire? */ +@ if (_tx_timer_expired_time_slice) +@ { +@ + LDR r3, =_tx_timer_expired_time_slice @ Pickup address of time-slice expired + LDR r2, [r3] @ Pickup the actual flag + CMP r2, #0 @ See if the flag is set + BEQ __tx_timer_not_ts_expiration @ No, skip time-slice processing +@ +@ /* Time slice interrupted thread. */ +@ _tx_thread_time_slice(); +@ + BL _tx_thread_time_slice @ Call time-slice processing +@ +@ } +@ +__tx_timer_not_ts_expiration: +@ + LDMIA sp!, {r0, lr} @ Recover lr register (r0 is just there for + @ the 8-byte stack alignment +@ +@ } +@ +__tx_timer_nothing_expired: +@ +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@ +@} + diff --git a/ports_module/cortex-m3/iar/example_build/ThreadX_Modules_Cortex-M3_IAR.pdf b/ports_module/cortex-m3/iar/example_build/ThreadX_Modules_Cortex-M3_IAR.pdf new file mode 100644 index 00000000..676b3645 Binary files /dev/null and b/ports_module/cortex-m3/iar/example_build/ThreadX_Modules_Cortex-M3_IAR.pdf differ diff --git a/ports_module/cortex-m3/iar/example_build/azure_rtos.eww b/ports_module/cortex-m3/iar/example_build/azure_rtos.eww new file mode 100644 index 00000000..e490c85a --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/azure_rtos.eww @@ -0,0 +1,19 @@ + + + + $WS_DIR$\sample_threadx_module_manager.ewp + + + $WS_DIR$\sample_threadx_module.ewp + + + $WS_DIR$\sample_threadx.ewp + + + $WS_DIR$\tx.ewp + + + $WS_DIR$\txm.ewp + + + diff --git a/ports_module/cortex-m3/iar/example_build/cstartup_M.s b/ports_module/cortex-m3/iar/example_build/cstartup_M.s new file mode 100644 index 00000000..75d9369b --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/cstartup_M.s @@ -0,0 +1,73 @@ + EXTERN __iar_program_start + PUBLIC __vector_table + + SECTION .text:CODE:REORDER(1) + + ;; Keep vector table even if it's not referenced + REQUIRE __vector_table + + THUMB + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec:CODE:NOROOT(2) + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD __Reset_Vector + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + + PUBWEAK NMI_Handler + PUBWEAK HardFault_Handler + PUBWEAK MemManage_Handler + PUBWEAK BusFault_Handler + PUBWEAK UsageFault_Handler + PUBWEAK SVC_Handler + PUBWEAK DebugMon_Handler + PUBWEAK PendSV_Handler + PUBWEAK SysTick_Handler + + SECTION .text:CODE:REORDER:NOROOT(1) + THUMB +__Reset_Vector: + CPSID i ; Disable interrupts + B __iar_program_start + + +NMI_Handler +HardFault_Handler +MemManage_Handler +BusFault_Handler +UsageFault_Handler +SVC_Handler +DebugMon_Handler +PendSV_Handler +SysTick_Handler +Default_Handler +__default_handler + CALL_GRAPH_ROOT __default_handler, "interrupt" + NOCALL __default_handler + B __default_handler + + END diff --git a/ports_module/cortex-m3/iar/example_build/sample_threadx.c b/ports_module/cortex-m3/iar/example_build/sample_threadx.c new file mode 100644 index 00000000..c67d75d0 --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/sample_threadx.c @@ -0,0 +1,385 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define byte pool memory. */ + +UCHAR byte_pool_memory[DEMO_BYTE_POOL_SIZE]; + + +/* Define event buffer. */ + +#ifdef TX_ENABLE_EVENT_TRACE +UCHAR trace_buffer[0x10000]; +#endif + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + +#ifdef TX_ENABLE_EVENT_TRACE + tx_trace_enable(trace_buffer, sizeof(trace_buffer), 32); +#endif + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", byte_pool_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports_module/cortex-m3/iar/example_build/sample_threadx.ewd b/ports_module/cortex-m3/iar/example_build/sample_threadx.ewd new file mode 100644 index 00000000..9df387fc --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/sample_threadx.ewd @@ -0,0 +1,2974 @@ + + + 3 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 32 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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@@ +define symbol __ICFEDIT_intvec_start__ = 0x0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x80; +define symbol __ICFEDIT_region_ROM_end__ = 0x1FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x100000; +define symbol __ICFEDIT_region_RAM_end__ = 0x1FFFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x2000; +define symbol __ICFEDIT_size_heap__ = 0x8000; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __ICFEDIT_size_freemem__ = 0x100000; + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region RAM_freemem = mem:[from 0x200000 to 0x300000]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + + +initialize by copy { readwrite }; +initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP}; + +place in RAM_region { last section FREE_MEM}; diff --git a/ports_module/cortex-m3/iar/example_build/sample_threadx_module.c b/ports_module/cortex-m3/iar/example_build/sample_threadx_module.c new file mode 100644 index 00000000..0570a7cd --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/sample_threadx_module.c @@ -0,0 +1,428 @@ +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, + event flags group, byte pool, and block pool. */ + +/* Specify that this is a module! */ + +#define TXM_MODULE + + +/* Include the ThreadX module definitions. */ + +#include "txm_module.h" + + +/* Define constants. */ + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the pool space in the bss section of the module. ULONG is used to + get the word alignment. */ + +ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD *thread_0; +TX_THREAD *thread_1; +TX_THREAD *thread_2; +TX_THREAD *thread_3; +TX_THREAD *thread_4; +TX_THREAD *thread_5; +TX_THREAD *thread_6; +TX_THREAD *thread_7; +TX_QUEUE *queue_0; +TX_SEMAPHORE *semaphore_0; +TX_MUTEX *mutex_0; +TX_EVENT_FLAGS_GROUP *event_flags_0; +TX_BYTE_POOL *byte_pool_0; +TX_BLOCK_POOL *block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; +ULONG semaphore_0_puts; +ULONG event_0_sets; +ULONG queue_0_sends; + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + +void semaphore_0_notify(TX_SEMAPHORE *semaphore_ptr) +{ + + if (semaphore_ptr == semaphore_0) + semaphore_0_puts++; +} + + +void event_0_notify(TX_EVENT_FLAGS_GROUP *event_flag_group_ptr) +{ + + if (event_flag_group_ptr == event_flags_0) + event_0_sets++; +} + + +void queue_0_notify(TX_QUEUE *queue_ptr) +{ + + if (queue_ptr == queue_0) + queue_0_sends++; +} + + +/* Define the module start function. */ + +void demo_module_start(ULONG id) +{ + +CHAR *pointer; + + /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + the control block(s). */ + txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_2, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_3, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_4, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_5, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_6, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_7, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&queue_0, sizeof(TX_QUEUE)); + txm_module_object_allocate((void*)&semaphore_0, sizeof(TX_SEMAPHORE)); + txm_module_object_allocate((void*)&mutex_0, sizeof(TX_MUTEX)); + txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); + txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); + txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(queue_0, "module queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + tx_queue_send_notify(queue_0, queue_0_notify); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(semaphore_0, "module semaphore 0", 1); + + tx_semaphore_put_notify(semaphore_0, semaphore_0_notify); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(event_flags_0, "module event flags 0"); + + tx_event_flags_set_notify(event_flags_0, event_0_notify); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(mutex_0, "module mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(block_pool_0, "module block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + /* Test memory handler. */ + *(ULONG *)0x64005000 = 0xCDCDCDCD; + + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + diff --git a/ports_module/cortex-m3/iar/example_build/sample_threadx_module.ewd b/ports_module/cortex-m3/iar/example_build/sample_threadx_module.ewd new file mode 100644 index 00000000..21bf663c --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/sample_threadx_module.ewd @@ -0,0 +1,2974 @@ + + + 3 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 32 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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@@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x080f0000; +define symbol __ICFEDIT_region_ROM_end__ = 0x080fffff; +define symbol __ICFEDIT_region_RAM_start__ = 0x64002800; +define symbol __ICFEDIT_region_RAM_end__ = 0x64100000; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0; +define symbol __ICFEDIT_size_svcstack__ = 0; +define symbol __ICFEDIT_size_irqstack__ = 0; +define symbol __ICFEDIT_size_fiqstack__ = 0; +define symbol __ICFEDIT_size_undstack__ = 0; +define symbol __ICFEDIT_size_abtstack__ = 0; +define symbol __ICFEDIT_size_heap__ = 0x1000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +//define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +//define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +//define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +//define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; +//define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; +//define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +//place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +define movable block ROPI with alignment = 4, fixed order +{ + ro object txm_module_preamble.o, + ro, + ro data +}; + +define movable block RWPI with alignment = 8, fixed order, static base +{ + rw, + block HEAP +}; + +place in ROM_region { block ROPI }; +place in RAM_region { block RWPI }; + diff --git a/ports_module/cortex-m3/iar/example_build/sample_threadx_module_manager.c b/ports_module/cortex-m3/iar/example_build/sample_threadx_module_manager.c new file mode 100644 index 00000000..f9656fce --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/sample_threadx_module_manager.c @@ -0,0 +1,109 @@ +/* Small demonstration of the ThreadX module manager. */ + +#include "tx_api.h" +#include "txm_module.h" + + +#define DEMO_STACK_SIZE 1024 + +/* Define the ThreadX object control blocks... */ + +TX_THREAD module_manager; +TXM_MODULE_INSTANCE my_module; + + +/* Define the object pool area. */ + +UCHAR object_memory[8192]; + + +/* Define the count of memory faults. */ + +ULONG memory_faults; + + +/* Define thread prototypes. */ + +void module_manager_entry(ULONG thread_input); + + +/* Define fault handler. */ + +VOID module_fault_handler(TX_THREAD *thread, TXM_MODULE_INSTANCE *module) +{ + + /* Just increment the fault counter. */ + memory_faults++; +} + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = (CHAR*)first_unused_memory; + + + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + pointer = pointer + DEMO_STACK_SIZE; +} + + + + +/* Define the test threads. */ + +void module_manager_entry(ULONG thread_input) +{ + + /* Initialize the module manager. */ + txm_module_manager_initialize((VOID *) 0x64000000, 0x1000000); + + txm_module_manager_object_pool_create(object_memory, sizeof(object_memory)); + + /* Register a fault handler. */ + txm_module_manager_memory_fault_notify(module_fault_handler); + + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ + txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0x080F0000); + + /* Enable 128 byte read/write shared memory region at 0x64005000. */ + txm_module_manager_external_memory_enable(&my_module, (void *) 0x64005000, 128, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); + + /* Start the module. */ + txm_module_manager_start(&my_module); + + /* Sleep for a while.... */ + tx_thread_sleep(1000); + + /* Stop the module. */ + txm_module_manager_stop(&my_module); + + /* Unload the module. */ + txm_module_manager_unload(&my_module); + + /* Load the module that is already there. */ + txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0x080F0000); + + /* Start the module again. */ + txm_module_manager_start(&my_module); + + /* Now just spin... */ + while(1) + { + + tx_thread_sleep(100); + } +} diff --git a/ports_module/cortex-m3/iar/example_build/sample_threadx_module_manager.ewd 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IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x64000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x640FFFFF; +define symbol __ICFEDIT_region_IRAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_IRAM_end__ = 0x2001FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in IRAM_region { block HEAP }; +place in IRAM_region { readwrite, block CSTACK }; + +place in IRAM_region { last section FREE_MEM}; diff --git a/ports_module/cortex-m3/iar/example_build/settings/azure_rtos.wsdt b/ports_module/cortex-m3/iar/example_build/settings/azure_rtos.wsdt new file mode 100644 index 00000000..60671001 --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/settings/azure_rtos.wsdt @@ -0,0 +1,561 @@ + + + + + sample_threadx_module_manager/Debug + sample_threadx_module/Debug + sample_threadx/Debug + tx/Debug + txm/Debug + + sample_threadx_module_manager + 1 + + + + + 21 + 2518 + 2 + + 0 + -1 + + + + 34001 + 0 + + + + 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+ + + 34050 + 0A0000000A0000006E0000006E000000 + 0000000000000000FE0200001A000000 + 8192 + 0 + 0 + 744 + 0 + + + 1 + + + + 34048 + 34049 + 34050 + 34051 + 34052 + 34053 + 34054 + 34055 + 34056 + 34057 + 34058 + 34059 + 34060 + 34061 + 34062 + 34063 + 34064 + 34065 + + + + 010000000300000001000000000000000000000001000000010000000200000000000000010000000100000000000000280000002800000000000000 + + + + diff --git a/ports_module/cortex-m3/iar/example_build/settings/sample_threadx.Debug.cspy.bat b/ports_module/cortex-m3/iar/example_build/settings/sample_threadx.Debug.cspy.bat new file mode 100644 index 00000000..2f3ad708 --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/settings/sample_threadx.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%~1" == "" goto debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\tasks\st_work\threadx_07242020_rc2\ports_module\cortex-m3\iar\example_build\settings\sample_threadx.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\tasks\st_work\threadx_07242020_rc2\ports_module\cortex-m3\iar\example_build\settings\sample_threadx.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\tasks\st_work\threadx_07242020_rc2\ports_module\cortex-m3\iar\example_build\settings\sample_threadx.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\Users\nisohack\Documents\work\tasks\st_work\threadx_07242020_rc2\ports_module\cortex-m3\iar\example_build\settings\sample_threadx.Debug.driver.xcl" + +@echo off +:end \ No newline at end of file diff --git a/ports_module/cortex-m3/iar/example_build/settings/sample_threadx.Debug.cspy.ps1 b/ports_module/cortex-m3/iar/example_build/settings/sample_threadx.Debug.cspy.ps1 new file mode 100644 index 00000000..aecd02d9 --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/settings/sample_threadx.Debug.cspy.ps1 @@ -0,0 +1,31 @@ +param([String]$debugfile = ""); + +# This powershell file has been generated by the IAR Embedded Workbench +# C - SPY Debugger, as an aid to preparing a command line for running +# the cspybat command line utility using the appropriate settings. +# +# Note that this file is generated every time a new debug session +# is initialized, so you may want to move or rename the file before +# making changes. +# +# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed +# by the name of the debug file (usually an ELF / DWARF or UBROF file). +# +# Read about available command line parameters in the C - SPY Debugging +# Guide. Hints about additional command line parameters that may be +# useful in specific cases : +# --download_only Downloads a code image without starting a debug +# session afterwards. +# --silent Omits the sign - on message. +# --timeout Limits the maximum allowed execution time. +# + + +if ($debugfile -eq "") +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\tasks\st_work\threadx_07242020_rc2\ports_module\cortex-m3\iar\example_build\settings\sample_threadx.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\tasks\st_work\threadx_07242020_rc2\ports_module\cortex-m3\iar\example_build\settings\sample_threadx.Debug.driver.xcl" +} +else +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\tasks\st_work\threadx_07242020_rc2\ports_module\cortex-m3\iar\example_build\settings\sample_threadx.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\Users\nisohack\Documents\work\tasks\st_work\threadx_07242020_rc2\ports_module\cortex-m3\iar\example_build\settings\sample_threadx.Debug.driver.xcl" +} diff --git a/ports_module/cortex-m3/iar/example_build/settings/sample_threadx.Debug.driver.xcl b/ports_module/cortex-m3/iar/example_build/settings/sample_threadx.Debug.driver.xcl new file mode 100644 index 00000000..11a77ea1 --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/settings/sample_threadx.Debug.driver.xcl @@ -0,0 +1,13 @@ +"--endian=little" + +"--cpu=Cortex-M3" + +"--fpu=None" + +"--semihosting" + +"--multicore_nr_of_cores=1" + + + + diff --git a/ports_module/cortex-m3/iar/example_build/settings/sample_threadx.Debug.general.xcl b/ports_module/cortex-m3/iar/example_build/settings/sample_threadx.Debug.general.xcl new file mode 100644 index 00000000..8a77c31c --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/settings/sample_threadx.Debug.general.xcl @@ -0,0 +1,11 @@ +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armproc.dll" + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armsim2.dll" + +"C:\Users\nisohack\Documents\work\tasks\st_work\threadx_07242020_rc2\ports_module\cortex-m3\iar\example_build\Debug\Exe\sample_threadx.out" + +--plugin="C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armbat.dll" + + + + diff --git a/ports_module/cortex-m3/iar/example_build/settings/sample_threadx.crun b/ports_module/cortex-m3/iar/example_build/settings/sample_threadx.crun new file mode 100644 index 00000000..d71ea555 --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/settings/sample_threadx.crun @@ -0,0 +1,13 @@ + + + 1 + + + * + * + * + 0 + 1 + + + diff --git a/ports_module/cortex-m3/iar/example_build/settings/sample_threadx.dbgdt b/ports_module/cortex-m3/iar/example_build/settings/sample_threadx.dbgdt new file mode 100644 index 00000000..aebcbbc8 --- /dev/null +++ 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+ + + 34123 + 0A0000000A0000006E0000006E000000 + 0000000000000000150300001A000000 + 8192 + 0 + 0 + 32767 + 0 + + + 1 + + + + diff --git a/ports_module/cortex-m3/iar/example_build/settings/sample_threadx.dnx b/ports_module/cortex-m3/iar/example_build/settings/sample_threadx.dnx new file mode 100644 index 00000000..0fa79328 --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/settings/sample_threadx.dnx @@ -0,0 +1,99 @@ + + + + 0 + 1 + 90 + 1 + 1 + 1 + main + 0 + 50 + + + 0 + 1 + + + 1618778298 + + + 0 + 0 + 0 + + + 0 + + + _ 0 + _ 0 + + + 0 + + + 0 + 1 + 0 + 0 + + + 0 + + + 1 + + + _ 0 + _ "" + + + _ 0 + _ "" + _ 0 + + + 0 + 0 + 1 + 0 + 1 + 0 + + + 0 + 0 + 1 + 0 + 1 + + + 0 + + + 0 + + + 1 + _ 0 9999 0 9999 1 0 0 100 0 1 "SysTick 1 0x3C" + 1 + + + 1 + 0 + 1 + 0 + 1 + + + 0 + 0 + + + 10000000 + 0 + 1 + + diff --git a/ports_module/cortex-m3/iar/example_build/settings/sample_threadx_module.Debug.cspy.bat b/ports_module/cortex-m3/iar/example_build/settings/sample_threadx_module.Debug.cspy.bat new file mode 100644 index 00000000..6a76a8e3 --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/settings/sample_threadx_module.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%~1" == "" goto debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m3\iar\example_build\settings\sample_threadx_module.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m3\iar\example_build\settings\sample_threadx_module.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m3\iar\example_build\settings\sample_threadx_module.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m3\iar\example_build\settings\sample_threadx_module.Debug.driver.xcl" + +@echo off +:end diff --git a/ports_module/cortex-m3/iar/example_build/settings/sample_threadx_module.Debug.cspy.ps1 b/ports_module/cortex-m3/iar/example_build/settings/sample_threadx_module.Debug.cspy.ps1 new file mode 100644 index 00000000..fb7f5494 --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/settings/sample_threadx_module.Debug.cspy.ps1 @@ -0,0 +1,31 @@ +param([String]$debugfile = ""); + +# This powershell file has been generated by the IAR Embedded Workbench +# C - SPY Debugger, as an aid to preparing a command line for running +# the cspybat command line utility using the appropriate settings. +# +# Note that this file is generated every time a new debug session +# is initialized, so you may want to move or rename the file before +# making changes. +# +# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed +# by the name of the debug file (usually an ELF / DWARF or UBROF file). +# +# Read about available command line parameters in the C - SPY Debugging +# Guide. Hints about additional command line parameters that may be +# useful in specific cases : +# --download_only Downloads a code image without starting a debug +# session afterwards. +# --silent Omits the sign - on message. +# --timeout Limits the maximum allowed execution time. +# + + +if ($debugfile -eq "") +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m3\iar\example_build\settings\sample_threadx_module.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m3\iar\example_build\settings\sample_threadx_module.Debug.driver.xcl" +} +else +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m3\iar\example_build\settings\sample_threadx_module.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m3\iar\example_build\settings\sample_threadx_module.Debug.driver.xcl" +} diff --git a/ports_module/cortex-m3/iar/example_build/settings/sample_threadx_module.Debug.driver.xcl b/ports_module/cortex-m3/iar/example_build/settings/sample_threadx_module.Debug.driver.xcl new file mode 100644 index 00000000..11a77ea1 --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/settings/sample_threadx_module.Debug.driver.xcl @@ -0,0 +1,13 @@ +"--endian=little" + +"--cpu=Cortex-M3" + +"--fpu=None" + +"--semihosting" + +"--multicore_nr_of_cores=1" + + + + diff --git a/ports_module/cortex-m3/iar/example_build/settings/sample_threadx_module.Debug.general.xcl b/ports_module/cortex-m3/iar/example_build/settings/sample_threadx_module.Debug.general.xcl new file mode 100644 index 00000000..8179c7fe --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/settings/sample_threadx_module.Debug.general.xcl @@ -0,0 +1,11 @@ +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armproc.dll" + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armsim2.dll" + +"C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m3\iar\example_build\Debug\Exe\sample_threadx_module_stm32f4xx.out" + +--plugin="C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armbat.dll" + + + + diff --git a/ports_module/cortex-m3/iar/example_build/settings/sample_threadx_module.crun b/ports_module/cortex-m3/iar/example_build/settings/sample_threadx_module.crun new file mode 100644 index 00000000..d71ea555 --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/settings/sample_threadx_module.crun @@ -0,0 +1,13 @@ + + + 1 + + + * + * + * + 0 + 1 + + + diff --git a/ports_module/cortex-m3/iar/example_build/settings/sample_threadx_module.dbgdt b/ports_module/cortex-m3/iar/example_build/settings/sample_threadx_module.dbgdt new file mode 100644 index 00000000..73e71f6e --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/settings/sample_threadx_module.dbgdt @@ -0,0 +1,4 @@ + + + + diff --git a/ports_module/cortex-m3/iar/example_build/settings/sample_threadx_module.dnx b/ports_module/cortex-m3/iar/example_build/settings/sample_threadx_module.dnx new file mode 100644 index 00000000..1872e83f --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/settings/sample_threadx_module.dnx @@ -0,0 +1,58 @@ + + + + 0 + 0 + 1 + 0 + 1 + 0 + + + 0 + 0 + 1 + 0 + 1 + + + 0 + 1 + 90 + 1 + 1 + 1 + main + 0 + 50 + + + 0 + + + 0 + + + 1 + + + 1 + 0 + 1 + 0 + 1 + + + 0 + 1 + + + 0 + 0 + + + 10000000 + 0 + 1 + + diff --git a/ports_module/cortex-m3/iar/example_build/settings/sample_threadx_module_manager.Debug.cspy.bat b/ports_module/cortex-m3/iar/example_build/settings/sample_threadx_module_manager.Debug.cspy.bat new file mode 100644 index 00000000..820020f4 --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/settings/sample_threadx_module_manager.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%~1" == "" goto debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m3\iar\example_build\settings\sample_threadx_module_manager.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m3\iar\example_build\settings\sample_threadx_module_manager.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m3\iar\example_build\settings\sample_threadx_module_manager.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m3\iar\example_build\settings\sample_threadx_module_manager.Debug.driver.xcl" + +@echo off +:end \ No newline at end of file diff --git a/ports_module/cortex-m3/iar/example_build/settings/sample_threadx_module_manager.Debug.cspy.ps1 b/ports_module/cortex-m3/iar/example_build/settings/sample_threadx_module_manager.Debug.cspy.ps1 new file mode 100644 index 00000000..34a9f4f9 --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/settings/sample_threadx_module_manager.Debug.cspy.ps1 @@ -0,0 +1,31 @@ +param([String]$debugfile = ""); + +# This powershell file has been generated by the IAR Embedded Workbench +# C - SPY Debugger, as an aid to preparing a command line for running +# the cspybat command line utility using the appropriate settings. +# +# Note that this file is generated every time a new debug session +# is initialized, so you may want to move or rename the file before +# making changes. +# +# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed +# by the name of the debug file (usually an ELF / DWARF or UBROF file). +# +# Read about available command line parameters in the C - SPY Debugging +# Guide. Hints about additional command line parameters that may be +# useful in specific cases : +# --download_only Downloads a code image without starting a debug +# session afterwards. +# --silent Omits the sign - on message. +# --timeout Limits the maximum allowed execution time. +# + + +if ($debugfile -eq "") +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m3\iar\example_build\settings\sample_threadx_module_manager.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m3\iar\example_build\settings\sample_threadx_module_manager.Debug.driver.xcl" +} +else +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m3\iar\example_build\settings\sample_threadx_module_manager.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m3\iar\example_build\settings\sample_threadx_module_manager.Debug.driver.xcl" +} diff --git a/ports_module/cortex-m3/iar/example_build/settings/sample_threadx_module_manager.Debug.driver.xcl b/ports_module/cortex-m3/iar/example_build/settings/sample_threadx_module_manager.Debug.driver.xcl new file mode 100644 index 00000000..23c72b54 --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/settings/sample_threadx_module_manager.Debug.driver.xcl @@ -0,0 +1,19 @@ +"--endian=little" + +"--cpu=Cortex-M3" + +"--fpu=None" + +"-p" + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\CONFIG\debugger\ST\STM32F217IG.ddf" + +"--semihosting" + +"--device=STM32F217IG" + +"--multicore_nr_of_cores=1" + + + + diff --git a/ports_module/cortex-m3/iar/example_build/settings/sample_threadx_module_manager.Debug.general.xcl b/ports_module/cortex-m3/iar/example_build/settings/sample_threadx_module_manager.Debug.general.xcl new file mode 100644 index 00000000..d510d7eb --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/settings/sample_threadx_module_manager.Debug.general.xcl @@ -0,0 +1,13 @@ +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armproc.dll" + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armsim2.dll" + +"C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m3\iar\example_build\Debug\Exe\sample_threadx_module_manager_stm32f4xx.out" + +--plugin="C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armbat.dll" + +--device_macro="C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\config\debugger\ST\STM32F2xx.dmac" + + + + diff --git a/ports_module/cortex-m3/iar/example_build/settings/sample_threadx_module_manager.crun b/ports_module/cortex-m3/iar/example_build/settings/sample_threadx_module_manager.crun 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+ + + 34050 + 0A0000000A0000006E0000006E000000 + 0000000000000000150300001A000000 + 8192 + 0 + 0 + 767 + 0 + + + 1 + + + + diff --git a/ports_module/cortex-m3/iar/example_build/settings/sample_threadx_module_manager.dnx b/ports_module/cortex-m3/iar/example_build/settings/sample_threadx_module_manager.dnx new file mode 100644 index 00000000..77e49cb9 --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/settings/sample_threadx_module_manager.dnx @@ -0,0 +1,105 @@ + + + + 0 + 1 + 90 + 1 + 1 + 1 + main + 0 + 50 + + + _ 0 + _ 0 + + + 3269948375 + + + 0 + 1 + + + 0 + 0 + 0 + + + 0 + 1 + + + _ 0 + _ 0 + + + 0 + + + 0 + 1 + 0 + 0 + + + 0 + + + 1 + + + _ 0 + _ "" + + + _ 0 + _ "" + _ 0 + + + 0 + 0 + 1 + 0 + 1 + 0 + + + 0 + 0 + 1 + 0 + 1 + + + 0 + + + 0 + + + 1 + _ 0 10000 0 10000 1 0 0 100 0 1 "SysTick 1 0x3C" + 1 + + + 1 + 0 + 1 + 0 + 1 + + + _ "C:\Users\nisohack\Documents\work\tasks\st_work\threadx_07242020_rc2\ports_module\cortex-m3\iar\example_build\sample_threadx_module_stm32f2xx.c" "" + 1 + 0 + + + 10000000 + 0 + 1 + + diff --git a/ports_module/cortex-m3/iar/example_build/settings/tx.Debug.cspy.bat b/ports_module/cortex-m3/iar/example_build/settings/tx.Debug.cspy.bat new file mode 100644 index 00000000..c4707b78 --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/settings/tx.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%~1" == "" goto debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" + +@echo off +:end diff --git a/ports_module/cortex-m3/iar/example_build/settings/tx.Debug.cspy.ps1 b/ports_module/cortex-m3/iar/example_build/settings/tx.Debug.cspy.ps1 new file mode 100644 index 00000000..1c1ba13b --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/settings/tx.Debug.cspy.ps1 @@ -0,0 +1,31 @@ +param([String]$debugfile = ""); + +# This powershell file has been generated by the IAR Embedded Workbench +# C - SPY Debugger, as an aid to preparing a command line for running +# the cspybat command line utility using the appropriate settings. +# +# Note that this file is generated every time a new debug session +# is initialized, so you may want to move or rename the file before +# making changes. +# +# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed +# by the name of the debug file (usually an ELF / DWARF or UBROF file). +# +# Read about available command line parameters in the C - SPY Debugging +# Guide. Hints about additional command line parameters that may be +# useful in specific cases : +# --download_only Downloads a code image without starting a debug +# session afterwards. +# --silent Omits the sign - on message. +# --timeout Limits the maximum allowed execution time. +# + + +if ($debugfile -eq "") +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" +} +else +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" +} diff --git a/ports_module/cortex-m3/iar/example_build/settings/tx.Debug.driver.xcl b/ports_module/cortex-m3/iar/example_build/settings/tx.Debug.driver.xcl new file mode 100644 index 00000000..11a77ea1 --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/settings/tx.Debug.driver.xcl @@ -0,0 +1,13 @@ +"--endian=little" + +"--cpu=Cortex-M3" + +"--fpu=None" + +"--semihosting" + +"--multicore_nr_of_cores=1" + + + + diff --git a/ports_module/cortex-m3/iar/example_build/settings/tx.Debug.general.xcl b/ports_module/cortex-m3/iar/example_build/settings/tx.Debug.general.xcl new file mode 100644 index 00000000..ef6d6dd5 --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/settings/tx.Debug.general.xcl @@ -0,0 +1,11 @@ +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\bin\armproc.dll" + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\bin\armsim2.dll" + +"C:\release\threadx\Debug\Exe\tx.out" + +--plugin "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\bin\armbat.dll" + + + + diff --git a/ports_module/cortex-m3/iar/example_build/settings/tx.crun b/ports_module/cortex-m3/iar/example_build/settings/tx.crun new file mode 100644 index 00000000..d71ea555 --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/settings/tx.crun @@ -0,0 +1,13 @@ + + + 1 + + + * + * + * + 0 + 1 + + + diff --git a/ports_module/cortex-m3/iar/example_build/settings/tx.dbgdt b/ports_module/cortex-m3/iar/example_build/settings/tx.dbgdt new file mode 100644 index 00000000..9e08d965 --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/settings/tx.dbgdt @@ -0,0 +1,4 @@ + + + + diff --git a/ports_module/cortex-m3/iar/example_build/settings/tx.dnx b/ports_module/cortex-m3/iar/example_build/settings/tx.dnx new file mode 100644 index 00000000..25e4c4ba --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/settings/tx.dnx @@ -0,0 +1,58 @@ + + + + 0 + 1 + 90 + 1 + 1 + 1 + main + 0 + 50 + + + 0 + 1 + + + 0 + 0 + 1 + 0 + 1 + 0 + + + 0 + 0 + 1 + 0 + 1 + + + 0 + + + 0 + + + 1 + + + 1 + 0 + 1 + 0 + 1 + + + 0 + 0 + + + 10000000 + 0 + 1 + + diff --git a/ports_module/cortex-m3/iar/example_build/settings/txm.Debug.cspy.bat b/ports_module/cortex-m3/iar/example_build/settings/txm.Debug.cspy.bat new file mode 100644 index 00000000..1ab003ac --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/settings/txm.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%~1" == "" goto debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m3\iar\example_build\settings\txm.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m3\iar\example_build\settings\txm.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m3\iar\example_build\settings\txm.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m3\iar\example_build\settings\txm.Debug.driver.xcl" + +@echo off +:end diff --git a/ports_module/cortex-m3/iar/example_build/settings/txm.Debug.cspy.ps1 b/ports_module/cortex-m3/iar/example_build/settings/txm.Debug.cspy.ps1 new file mode 100644 index 00000000..9ab546ed --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/settings/txm.Debug.cspy.ps1 @@ -0,0 +1,31 @@ +param([String]$debugfile = ""); + +# This powershell file has been generated by the IAR Embedded Workbench +# C - SPY Debugger, as an aid to preparing a command line for running +# the cspybat command line utility using the appropriate settings. +# +# Note that this file is generated every time a new debug session +# is initialized, so you may want to move or rename the file before +# making changes. +# +# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed +# by the name of the debug file (usually an ELF / DWARF or UBROF file). +# +# Read about available command line parameters in the C - SPY Debugging +# Guide. Hints about additional command line parameters that may be +# useful in specific cases : +# --download_only Downloads a code image without starting a debug +# session afterwards. +# --silent Omits the sign - on message. +# --timeout Limits the maximum allowed execution time. +# + + +if ($debugfile -eq "") +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m3\iar\example_build\settings\txm.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m3\iar\example_build\settings\txm.Debug.driver.xcl" +} +else +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m3\iar\example_build\settings\txm.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m3\iar\example_build\settings\txm.Debug.driver.xcl" +} diff --git a/ports_module/cortex-m3/iar/example_build/settings/txm.Debug.driver.xcl b/ports_module/cortex-m3/iar/example_build/settings/txm.Debug.driver.xcl new file mode 100644 index 00000000..11a77ea1 --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/settings/txm.Debug.driver.xcl @@ -0,0 +1,13 @@ +"--endian=little" + +"--cpu=Cortex-M3" + +"--fpu=None" + +"--semihosting" + +"--multicore_nr_of_cores=1" + + + + diff --git a/ports_module/cortex-m3/iar/example_build/settings/txm.Debug.general.xcl b/ports_module/cortex-m3/iar/example_build/settings/txm.Debug.general.xcl new file mode 100644 index 00000000..0d0166c6 --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/settings/txm.Debug.general.xcl @@ -0,0 +1,11 @@ +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armproc.dll" + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armsim2.dll" + +"C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m3\iar\example_build\Debug\Exe\txm.out" + +--plugin="C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armbat.dll" + + + + diff --git a/ports_module/cortex-m3/iar/example_build/settings/txm.crun b/ports_module/cortex-m3/iar/example_build/settings/txm.crun new file mode 100644 index 00000000..d71ea555 --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/settings/txm.crun @@ -0,0 +1,13 @@ + + + 1 + + + * + * + * + 0 + 1 + + + diff --git a/ports_module/cortex-m3/iar/example_build/settings/txm.dbgdt b/ports_module/cortex-m3/iar/example_build/settings/txm.dbgdt new file mode 100644 index 00000000..73e71f6e --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/settings/txm.dbgdt @@ -0,0 +1,4 @@ + + + + diff --git a/ports_module/cortex-m3/iar/example_build/settings/txm.dnx b/ports_module/cortex-m3/iar/example_build/settings/txm.dnx new file mode 100644 index 00000000..1872e83f --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/settings/txm.dnx @@ -0,0 +1,58 @@ + + + + 0 + 0 + 1 + 0 + 1 + 0 + + + 0 + 0 + 1 + 0 + 1 + + + 0 + 1 + 90 + 1 + 1 + 1 + main + 0 + 50 + + + 0 + + + 0 + + + 1 + + + 1 + 0 + 1 + 0 + 1 + + + 0 + 1 + + + 0 + 0 + + + 10000000 + 0 + 1 + + diff --git a/ports_module/cortex-m3/iar/example_build/startup.s b/ports_module/cortex-m3/iar/example_build/startup.s new file mode 100644 index 00000000..bbe8142b --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/startup.s @@ -0,0 +1,622 @@ +;/******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup.s +;* Author : MCD Application Team +;* Version : V1.0.0 +;* Date : 18-April-2011 +;* Description : STM32F2xx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Configure he external SRAM mounted on STM322xG-EVAL board +;* to be used as data memory (optional, to be enabled by user) +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;*******************************************************************************/ +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + +__initial_spTop EQU 0x20000400 ; stack used for SystemInit & SystemInit_ExtMemCtl + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD __initial_spTop ; Use internal RAM for stack for calling SystemInit + DCD Reset_Handler ; Reset Handler + + DC32 NMI_Handler ; NMI + DC32 HardFault_Handler ; HardFault + DC32 MemManage_Handler ; MemManage + DC32 0 ; BusFault + DC32 0 ; UsageFault + DC32 0 ; 7 + DC32 0 ; 8 + DC32 0 ; 9 + DC32 0 ; 10 + DC32 SVC_Handler ; SVCall + DC32 DebugMon_Handler ; Monitor + DC32 0 ; 13 + DC32 PendSV_Handler ; PendSV + DC32 SysTick_Handler ; SysTick + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYP crypto + DCD HASH_RNG_IRQHandler ; Hash and Rng + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT(2) +Reset_Handler + CPSID i ; Disable interrupts + LDR R0, =sfe(CSTACK) ; restore original stack pointer + MSR MSP, R0 + LDR R0, =__iar_program_start ; Jump to ThreadX start, which will call IAR startup code + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT(2) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT(2) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT(2) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT(2) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT(2) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT(2) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT(2) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT(2) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT(2) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT(2) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:NOROOT(2) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT(2) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT(2) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT(2) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT(2) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT(2) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT(2) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT(2) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT(2) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT(2) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:NOROOT(2) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT(2) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT(2) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT(2) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT(2) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT(2) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:NOROOT(2) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT(2) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT(2) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK FSMC_IRQHandler + SECTION .text:CODE:NOROOT(2) +FSMC_IRQHandler + B FSMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:NOROOT(2) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT(2) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT(2) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT(2) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK ETH_IRQHandler + SECTION .text:CODE:NOROOT(2) +ETH_IRQHandler + B ETH_IRQHandler + + PUBWEAK ETH_WKUP_IRQHandler + SECTION .text:CODE:NOROOT(2) +ETH_WKUP_IRQHandler + B ETH_WKUP_IRQHandler + + PUBWEAK CAN2_TX_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN2_TX_IRQHandler + B CAN2_TX_IRQHandler + + PUBWEAK CAN2_RX0_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN2_RX0_IRQHandler + B CAN2_RX0_IRQHandler + + PUBWEAK CAN2_RX1_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN2_RX1_IRQHandler + B CAN2_RX1_IRQHandler + + PUBWEAK CAN2_SCE_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN2_SCE_IRQHandler + B CAN2_SCE_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:NOROOT(2) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_HS_EP1_OUT_IRQHandler + B OTG_HS_EP1_OUT_IRQHandler + + PUBWEAK OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_HS_EP1_IN_IRQHandler + B OTG_HS_EP1_IN_IRQHandler + + PUBWEAK OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_HS_WKUP_IRQHandler + B OTG_HS_WKUP_IRQHandler + + PUBWEAK OTG_HS_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_HS_IRQHandler + B OTG_HS_IRQHandler + + PUBWEAK DCMI_IRQHandler + SECTION .text:CODE:NOROOT(2) +DCMI_IRQHandler + B DCMI_IRQHandler + + PUBWEAK CRYP_IRQHandler + SECTION .text:CODE:NOROOT(2) +CRYP_IRQHandler + B CRYP_IRQHandler + + PUBWEAK HASH_RNG_IRQHandler + SECTION .text:CODE:NOROOT(2) +HASH_RNG_IRQHandler + B HASH_RNG_IRQHandler + + END +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/ports_module/cortex-m3/iar/example_build/stm32f2xx_library.a b/ports_module/cortex-m3/iar/example_build/stm32f2xx_library.a new file mode 100644 index 00000000..be049c34 Binary files /dev/null and b/ports_module/cortex-m3/iar/example_build/stm32f2xx_library.a differ diff --git a/ports_module/cortex-m3/iar/example_build/tx.ewd b/ports_module/cortex-m3/iar/example_build/tx.ewd new file mode 100644 index 00000000..b2b3f2fe --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/tx.ewd @@ -0,0 +1,2974 @@ + + + 3 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 32 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\RemedyRtosViewer\RemedyRtosViewer.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8b.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8bBE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 32 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 0 + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8b.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8bBE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/ports_module/cortex-m3/iar/example_build/tx.ewp b/ports_module/cortex-m3/iar/example_build/tx.ewp new file mode 100644 index 00000000..8b287181 --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/tx.ewp @@ -0,0 +1,2867 @@ + + + 3 + + Debug + + ARM + + 1 + + General + 3 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 36 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 23 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + Coder + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\common\inc\tx_mutex.h + + + $PROJ_DIR$\..\module_common\inc\tx_port.h + + + $PROJ_DIR$\..\..\..\..\common\inc\tx_queue.h + + + $PROJ_DIR$\..\..\..\..\common\inc\tx_semaphore.h + + + $PROJ_DIR$\..\..\..\..\common\inc\tx_thread.h + + + $PROJ_DIR$\..\..\..\..\common\inc\tx_timer.h + + + $PROJ_DIR$\..\..\..\..\common\inc\tx_trace.h + + + $PROJ_DIR$\..\..\..\..\common\inc\tx_user_sample.h + + + $PROJ_DIR$\..\..\..\..\common_modules\module_common\inc\txm_module.h + + + $PROJ_DIR$\..\..\..\..\common_modules\module_manager\inc\txm_module_manager_dispatch.h + + + $PROJ_DIR$\..\..\..\..\common_modules\module_manager\inc\txm_module_manager_util.h + + + $PROJ_DIR$\..\module_common\inc\txm_module_port.h + + + $PROJ_DIR$\..\..\..\..\common_modules\module_common\inc\txm_module_user.h + + + + src + + $PROJ_DIR$\..\..\..\..\common\src\tx_block_allocate.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_cleanup.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_initialize.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_performance_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_performance_system_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_prioritize.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_block_release.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_allocate.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_cleanup.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_initialize.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_performance_info_get.c + + + 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a/ports_module/cortex-m3/iar/example_build/tx_initialize_low_level.s b/ports_module/cortex-m3/iar/example_build/tx_initialize_low_level.s new file mode 100644 index 00000000..ab6a346c --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/tx_initialize_low_level.s @@ -0,0 +1,181 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_initialize.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_initialize_unused_memory + EXTERN _tx_timer_interrupt + EXTERN __vector_table + EXTERN _tx_execution_isr_enter + EXTERN _tx_execution_isr_exit +; +; +SYSTEM_CLOCK EQU 7200000 +SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1) + + RSEG FREE_MEM:DATA + PUBLIC __tx_free_memory_start +__tx_free_memory_start + DS32 4 +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-M3/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + PUBLIC _tx_initialize_low_level +_tx_initialize_low_level: +; +; /* Ensure that interrupts are disabled. */ +; + CPSID i ; Disable interrupts +; +; +; /* Set base of available memory to end of non-initialised RAM area. */ +; + LDR r0, =__tx_free_memory_start ; Get end of non-initialized RAM area + LDR r2, =_tx_initialize_unused_memory ; Build address of unused memory pointer + STR r0, [r2, #0] ; Save first free memory address +; +; /* Enable the cycle count register. */ +; + LDR r0, =0xE0001000 ; Build address of DWT register + LDR r1, [r0] ; Pickup the current value + ORR r1, r1, #1 ; Set the CYCCNTENA bit + STR r1, [r0] ; Enable the cycle count register +; +; /* Setup Vector Table Offset Register. */ +; + MOV r0, #0xE000E000 ; Build address of NVIC registers + LDR r1, =__vector_table ; Pickup address of vector table + STR r1, [r0, #0xD08] ; Set vector table address +; +; /* Set system stack pointer from vector value. */ +; + LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer + LDR r1, =__vector_table ; Pickup address of vector table + LDR r1, [r1] ; Pickup reset stack pointer + STR r1, [r0] ; Save system stack pointer +; +; /* Configure SysTick. */ +; + MOV r0, #0xE000E000 ; Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] ; Setup SysTick Reload Value + MOV r1, #0x7 ; Build SysTick Control Enable Value + STR r1, [r0, #0x10] ; Setup SysTick Control +; +; /* Configure handler priorities. */ +; + LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] ; Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] ; Setup System Handlers 8-11 Priority Registers + ; Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] ; Setup System Handlers 12-15 Priority Registers + ; Note: PnSV must be lowest priority, which is 0xFF +; +; /* Return to caller. */ +; + BX lr +;} +; +; +;/* Define SystTick Handler. */ +; + + PUBLIC SysTick_Handler + PUBLIC __tx_SysTickHandler +SysTick_Handler: +__tx_SysTickHandler: +; VOID SysTickHandler (VOID) +; { +; + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter ; Call the ISR enter function +#endif + BL _tx_timer_interrupt +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit ; Call the ISR exit function +#endif + POP {r0, lr} + BX LR +; } + + END + + diff --git a/ports_module/cortex-m3/iar/example_build/txm.ewd b/ports_module/cortex-m3/iar/example_build/txm.ewd new file mode 100644 index 00000000..21bf663c --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/txm.ewd @@ -0,0 +1,2974 @@ + + + 3 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 32 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_trace_event_unfilter.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_trace_interrupt_control.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_trace_isr_enter_insert.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_trace_isr_exit_insert.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_trace_user_event_insert.c + + + diff --git a/ports_module/cortex-m3/iar/example_build/txm_module_preamble.s b/ports_module/cortex-m3/iar/example_build/txm_module_preamble.s new file mode 100644 index 00000000..3dd55a1f --- /dev/null +++ b/ports_module/cortex-m3/iar/example_build/txm_module_preamble.s @@ -0,0 +1,73 @@ + SECTION .text:CODE + + AAPCS INTERWORK, ROPI, RWPI_COMPATIBLE, VFP_COMPATIBLE + PRESERVE8 + + /* Define public symbols. */ + + PUBLIC __txm_module_preamble + + + /* Define application-specific start/stop entry points for the module. */ + + EXTERN demo_module_start + + + /* Define common external refrences. */ + + EXTERN _txm_module_thread_shell_entry + EXTERN _txm_module_callback_request_thread_entry + EXTERN ROPI$$Length + EXTERN RWPI$$Length + + DATA +__txm_module_preamble: + DC32 0x4D4F4455 ; Module ID + DC32 0x5 ; Module Major Version + DC32 0x6 ; Module Minor Version + DC32 32 ; Module Preamble Size in 32-bit words + DC32 0x12345678 ; Module ID (application defined) + DC32 0x00000007 ; Module Properties where: + ; Bits 31-24: Compiler ID + ; 0 -> IAR + ; 1 -> RVDS + ; 2 -> GNU + ; Bits 23-3: Reserved + ; Bit 2: 0 -> Disable shared/external memory access + ; 1 -> Enable shared/external memory access + ; Bit 1: 0 -> No MPU protection + ; 1 -> MPU protection (must have user mode selected - bit 0 set) + ; Bit 0: 0 -> Privileged mode execution + ; 1 -> User mode execution + + + DC32 _txm_module_thread_shell_entry - . - 0 ; Module Shell Entry Point + DC32 demo_module_start - . - 0 ; Module Start Thread Entry Point + DC32 0 ; Module Stop Thread Entry Point + DC32 1 ; Module Start/Stop Thread Priority + DC32 1022 ; Module Start/Stop Thread Stack Size + DC32 _txm_module_callback_request_thread_entry - . - 0 ; Module Callback Thread Entry + DC32 1 ; Module Callback Thread Priority + DC32 1022 ; Module Callback Thread Stack Size + DC32 ROPI$$Length ; Module Code Size + DC32 RWPI$$Length ; Module Data Size + DC32 0 ; Reserved 0 + DC32 0 ; Reserved 1 + DC32 0 ; Reserved 2 + DC32 0 ; Reserved 3 + DC32 0 ; Reserved 4 + DC32 0 ; Reserved 5 + DC32 0 ; Reserved 6 + DC32 0 ; Reserved 7 + DC32 0 ; Reserved 8 + DC32 0 ; Reserved 9 + DC32 0 ; Reserved 10 + DC32 0 ; Reserved 11 + DC32 0 ; Reserved 12 + DC32 0 ; Reserved 13 + DC32 0 ; Reserved 14 + DC32 0 ; Reserved 15 + + END + + diff --git a/ports_module/cortex-m3/iar/inc/tx_port.h b/ports_module/cortex-m3/iar/inc/tx_port.h new file mode 100644 index 00000000..c4fa27a5 --- /dev/null +++ b/ports_module/cortex-m3/iar/inc/tx_port.h @@ -0,0 +1,404 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-M3/IAR */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include +#include +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef signed int INT; +typedef unsigned int UINT; +typedef signed long LONG; +typedef unsigned long ULONG; +typedef signed short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX Cortex-M3 port. */ + +#define TX_INT_DISABLE 1 /* Disable interrupts */ +#define TX_INT_ENABLE 0 /* Enable interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024UL) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) +#endif +#else +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif + +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; \ + VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; +#endif +#ifndef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#define TX_THREAD_EXTENSION_3 +#else +#define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ + unsigned long long tx_thread_execution_time_last_start; +#endif + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#if (__VER__ < 8000000) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); +#else +void *_tx_iar_create_per_thread_tls_area(void); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); +void __iar_Initlocks(void); + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#endif +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define the get system state macro. */ + +#ifndef TX_THREAD_GET_SYSTEM_STATE +#ifndef TX_MISRA_ENABLE +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | __get_IPSR()) +#else +ULONG _tx_misra_ipsr_get(VOID); +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get()) +#endif +#endif + + +/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value + indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h + for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always + zero after initialization for Cortex-M ports. */ + +#ifndef TX_THREAD_SYSTEM_RETURN_CHECK +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#endif + + +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to + prevent early scheduling on Cortex-M parts. */ + +#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT)__CLZ(__RBIT((m))); + +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifdef TX_DISABLE_INLINE + +UINT _tx_thread_interrupt_disable(VOID); +VOID _tx_thread_interrupt_restore(UINT previous_posture); + +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); + +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA __istate_t interrupt_save; +#define TX_DISABLE {interrupt_save = __get_interrupt_state();__disable_interrupt();}; +#define TX_RESTORE {__set_interrupt_state(interrupt_save);}; + +#define _tx_thread_system_return _tx_thread_system_return_inline + +static void _tx_thread_system_return_inline(void) +{ +__istate_t interrupt_save; + + /* Set PendSV to invoke ThreadX scheduler. */ + *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + if (__get_IPSR() == 0) + { + interrupt_save = __get_interrupt_state(); + __enable_interrupt(); + __set_interrupt_state(interrupt_save); + } +} + +#endif + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/IAR Version 6.0.1 *"; +#else +#ifdef TX_MISRA_ENABLE +extern CHAR _tx_version_id[100]; +#else +extern CHAR _tx_version_id[]; +#endif +#endif + + +#endif + + + + + diff --git a/ports_module/cortex-m3/iar/inc/txm_module_port.h b/ports_module/cortex-m3/iar/inc/txm_module_port.h new file mode 100644 index 00000000..87ea62fb --- /dev/null +++ b/ports_module/cortex-m3/iar/inc/txm_module_port.h @@ -0,0 +1,346 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* txm_module_port.h Cortex-M3/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the basic module constants, interface structures, */ +/* and function prototypes. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TXM_MODULE_PORT_H +#define TXM_MODULE_PORT_H + +/* It is assumed that the base ThreadX tx_port.h file has been modified to add the + following extensions to the ThreadX thread control block (this code should replace + the corresponding macro define in tx_port.h): + +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; \ + VOID *tx_thread_iar_tls_pointer; + +The following extensions must also be defined in tx_port.h: + +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); + +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); +*/ + +#define TXM_MODULE_THREAD_ENTRY_INFO_USER_EXTENSION + +/**************************************************************************/ +/* User-adjustable constants */ +/**************************************************************************/ + +/* Define the kernel stack size for a module thread. */ +#ifndef TXM_MODULE_KERNEL_STACK_SIZE +#define TXM_MODULE_KERNEL_STACK_SIZE 512 +#endif + +/**************************************************************************/ +/* End of user-adjustable constants */ +/**************************************************************************/ + + + +/* Define constants specific to the tools the module can be built with for this particular modules port. */ + +#define TXM_MODULE_IAR_COMPILER 0x00000000 +#define TXM_MODULE_RVDS_COMPILER 0x01000000 +#define TXM_MODULE_GNU_COMPILER 0x02000000 +#define TXM_MODULE_COMPILER_MASK 0xFF000000 +#define TXM_MODULE_OPTIONS_MASK 0x000000FF + + +/* Define the properties for this particular module port. */ + +#define TXM_MODULE_MEMORY_PROTECTION_ENABLED + +#ifdef TXM_MODULE_MEMORY_PROTECTION_ENABLED +#define TXM_MODULE_REQUIRE_ALLOCATED_OBJECT_MEMORY +#else +#define TXM_MODULE_REQUIRE_LOCAL_OBJECT_MEMORY +#endif + +#define TXM_MODULE_USER_MODE 0x00000001 +#define TXM_MODULE_MEMORY_PROTECTION 0x00000002 +#define TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS 0x00000004 + + +/* Define the supported options for this module. */ + +#define TXM_MODULE_MANAGER_SUPPORTED_OPTIONS (TXM_MODULE_USER_MODE | TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS) +#define TXM_MODULE_MANAGER_REQUIRED_OPTIONS 0 + + +/* Define offset adjustments according to the compiler used to build the module. */ + +#define TXM_MODULE_IAR_SHELL_ADJUST 24 +#define TXM_MODULE_IAR_START_ADJUST 28 +#define TXM_MODULE_IAR_STOP_ADJUST 32 +#define TXM_MODULE_IAR_CALLBACK_ADJUST 44 + +#define TXM_MODULE_RVDS_SHELL_ADJUST 0 +#define TXM_MODULE_RVDS_START_ADJUST 0 +#define TXM_MODULE_RVDS_STOP_ADJUST 0 +#define TXM_MODULE_RVDS_CALLBACK_ADJUST 0 + +#define TXM_MODULE_GNU_SHELL_ADJUST 24 +#define TXM_MODULE_GNU_START_ADJUST 28 +#define TXM_MODULE_GNU_STOP_ADJUST 32 +#define TXM_MODULE_GNU_CALLBACK_ADJUST 44 + + +/* Define other module port-specific constants. */ + +/* Define INLINE_DECLARE to inline for IAR compiler. */ + +#define INLINE_DECLARE inline + +/* Define the number of MPU entries assigned to the code and data sections. On Cortex-M parts, there can only be 7 total + entries, since ThreadX uses one for access to the kernel dispatch function. */ + +#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 +#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 +#define TXM_MODULE_MANAGER_SHARED_MPU_INDEX 8 +#define TXM_MODULE_MANAGER_SHARED_MPU_REGION 4 + +/* Shared memory region attributes. */ +#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 +#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 + +/* Define the port-extensions to the module manager instance structure. */ + +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + ULONG txm_module_instance_mpu_registers[16]; \ + ULONG txm_module_instance_shared_memory_address; \ + ULONG txm_module_instance_shared_memory_length; + + +/* Define the memory fault information structure that is populated when a memory fault occurs. */ + + +typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT +{ + TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr; + VOID *txm_module_manager_memory_fault_info_code_location; + ULONG txm_module_manager_memory_fault_info_shcsr; + ULONG txm_module_manager_memory_fault_info_mmfsr; + ULONG txm_module_manager_memory_fault_info_mmfar; + ULONG txm_module_manager_memory_fault_info_control; + ULONG txm_module_manager_memory_fault_info_sp; + ULONG txm_module_manager_memory_fault_info_r0; + ULONG txm_module_manager_memory_fault_info_r1; + ULONG txm_module_manager_memory_fault_info_r2; + ULONG txm_module_manager_memory_fault_info_r3; + ULONG txm_module_manager_memory_fault_info_r4; + ULONG txm_module_manager_memory_fault_info_r5; + ULONG txm_module_manager_memory_fault_info_r6; + ULONG txm_module_manager_memory_fault_info_r7; + ULONG txm_module_manager_memory_fault_info_r8; + ULONG txm_module_manager_memory_fault_info_r9; + ULONG txm_module_manager_memory_fault_info_r10; + ULONG txm_module_manager_memory_fault_info_r11; + ULONG txm_module_manager_memory_fault_info_r12; + ULONG txm_module_manager_memory_fault_info_lr; + ULONG txm_module_manager_memory_fault_info_xpsr; +} TXM_MODULE_MANAGER_MEMORY_FAULT_INFO; + + +#define TXM_MODULE_MANAGER_FAULT_INFO \ + TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; + +/* Define the macro to check the stack available in dispatch. */ +#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE + + +/* Define the macro to check the code alignment. */ + +#define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment) \ + { \ + ULONG temp; \ + temp = (ULONG) module_location; \ + temp = temp & (code_alignment - 1); \ + if (temp) \ + { \ + _tx_mutex_put(&_txm_module_manager_mutex); \ + return(TXM_MODULE_ALIGNMENT_ERROR); \ + } \ + } + + +/* Define the macro to adjust the alignment and size for code/data areas. */ + +#define TXM_MODULE_MANAGER_ALIGNMENT_ADJUST(module_preamble, code_size, code_alignment, data_size, data_alignment) _txm_module_manager_alignment_adjust(module_preamble, &code_size, &code_alignment, &data_size, &data_alignment); + + +/* Define the macro to adjust the symbols in the module preamble. */ + +#define TXM_MODULE_MANAGER_CALCULATE_ADJUSTMENTS(properties, shell_function_adjust, start_function_adjust, stop_function_adjust, callback_function_adjust) \ + if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_IAR_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_IAR_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_IAR_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_IAR_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_IAR_CALLBACK_ADJUST; \ + } \ + else if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_RVDS_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_RVDS_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_RVDS_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_RVDS_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_RVDS_CALLBACK_ADJUST; \ + } \ + else \ + { \ + shell_function_adjust = TXM_MODULE_GNU_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_GNU_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_GNU_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_GNU_CALLBACK_ADJUST; \ + } + + +/* Define the macro to populate the thread control block with module port-specific information. + Check if the module is in user mode and set up txm_module_thread_entry_info_kernel_call_dispatcher accordingly. +*/ + +#define TXM_MODULE_MANAGER_THREAD_SETUP(thread_ptr, module_instance) \ + thread_ptr -> tx_thread_module_current_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \ + thread_ptr -> tx_thread_module_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \ + if (thread_ptr -> tx_thread_module_user_mode) \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_user_mode_entry; \ + } \ + else \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_kernel_dispatch; \ + } + + +/* Define the macro to populate the module control block with module port-specific information. + If memory protection is enabled, set up the MPU registers. +*/ +#define TXM_MODULE_MANAGER_MODULE_SETUP(module_instance) \ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE) \ + { \ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) \ + { \ + _txm_module_manager_mm_register_setup(module_instance); \ + } \ + } \ + else \ + { \ + /* Do nothing. */ \ + } + +/* Define the macro to perform port-specific functions when unloading the module. */ +/* Nothing needs to be done for this port. */ +#define TXM_MODULE_MANAGER_MODULE_UNLOAD(module_instance) + + +/* Define the macro to perform port-specific functions when passing pointer to kernel. */ +/* Determine if the pointer is within the module's data or shared memory. */ +#define TXM_MODULE_MANAGER_CHECK_DATA_POINTER(module_instance, pointer) \ + if ((pointer < (ULONG) module_instance -> txm_module_instance_data_start) || \ + ((pointer+sizeof(pointer)) > (ULONG) module_instance -> txm_module_instance_data_end)) \ + { \ + if((pointer < module_instance -> txm_module_instance_shared_memory_address) || \ + ((pointer+sizeof(pointer)) > module_instance -> txm_module_instance_shared_memory_address \ + + module_instance -> txm_module_instance_shared_memory_length)) \ + { \ + return(TXM_MODULE_INVALID_MEMORY); \ + } \ + } + +/* Define the macro to perform port-specific functions when passing function pointer to kernel. */ +/* Determine if the pointer is within the module's code memory. */ +#define TXM_MODULE_MANAGER_CHECK_FUNCTION_POINTER(module_instance, pointer) \ + if (((pointer < sizeof(TXM_MODULE_PREAMBLE) + (ULONG) module_instance -> txm_module_instance_code_start) || \ + ((pointer+sizeof(pointer)) > (ULONG) module_instance -> txm_module_instance_code_end)) \ + && (pointer != (ULONG) TX_NULL)) \ + { \ + return(TX_PTR_ERROR); \ + } + + + +/* Define some internal prototypes to this module port. */ + +#ifndef TX_SOURCE_CODE +#define txm_module_manager_memory_fault_notify _txm_module_manager_memory_fault_notify +#endif + + +#define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES \ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment); \ +VOID _txm_module_manager_memory_fault_handler(VOID); \ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)); \ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \ +ULONG _txm_power_of_two_block_size(ULONG size); \ +ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); \ +ULONG _txm_module_manager_region_size_get(ULONG block_size); \ +UCHAR _txm_module_manager_shared_memory_check_outside(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size); \ +UCHAR _txm_module_manager_shared_memory_check_inside(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size); \ +UCHAR _txm_module_manager_shared_memory_check_inside_byte(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr); + +#define TXM_MODULE_MANAGER_VERSION_ID \ +CHAR _txm_module_manager_version_id[] = \ + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M3/MPU/IAR Version 6.0.1 *"; + +#endif + diff --git a/ports_module/cortex-m3/iar/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex-m3/iar/module_lib/src/txm_module_thread_shell_entry.c new file mode 100644 index 00000000..3db7757a --- /dev/null +++ b/ports_module/cortex-m3/iar/module_lib/src/txm_module_thread_shell_entry.c @@ -0,0 +1,176 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#ifndef TXM_MODULE +#define TXM_MODULE +#endif + +#ifndef TX_SOURCE_CODE +#define TX_SOURCE_CODE +#endif + + +/* Include necessary system files. */ + +#include "txm_module.h" +#include "tx_thread.h" + +/* Define the global module entry pointer from the start thread of the module. */ + +TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; + + +/* Define the dispatch function pointer used in the module implementation. */ + +ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3); + + +/* Define the IAR startup code that clears the uninitialized global data and sets up the + preset global variables. */ + +extern VOID __iar_data_init3(VOID); + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_thread_shell_entry Cortex-M3/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calls the specified entry function of the thread. It */ +/* also provides a place for the thread's entry function to return. */ +/* If the thread returns, this function places the thread in a */ +/* "COMPLETED" state. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to current thread */ +/* thread_info Pointer to thread entry info */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __iar_data_init3 IAR global initialization function*/ +/* thread_entry Thread's entry function */ +/* tx_thread_resume Resume the module callback thread */ +/* _txm_module_thread_system_suspend Module thread suspension routine */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) +{ + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + VOID (*entry_exit_notify)(TX_THREAD *, UINT); +#endif + + + /* Determine if this is the start thread. If so, we must prepare the module for + execution. If not, simply skip the C startup code. */ + if (thread_info -> txm_module_thread_entry_info_start_thread) + { + + /* Initialize the IAR C environment. */ + __iar_data_init3(); + + /* Save the entry info pointer, for later use. */ + _txm_module_entry_info = thread_info; + + /* Save the kernel function dispatch address. This is used to make all resident calls from + the module. */ + _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; + + /* Ensure that we have a valid pointer. */ + while (!_txm_module_kernel_call_dispatcher) + { + + /* Loop here, if an error is present getting the dispatch function pointer! + An error here typically indicates the resident portion of _tx_thread_schedule + is not supporting the trap to obtain the function pointer. */ + } + + /* Resume the module's callback thread, already created in the manager. */ + _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); + } + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has been entered! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_ENTRY); + } +#endif + + /* Call current thread's entry function. */ + (thread_info -> txm_module_thread_entry_info_entry) (thread_info -> txm_module_thread_entry_info_parameter); + + /* Suspend thread with a "completed" state. */ + + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine again. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has exited! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_EXIT); + } +#endif + + /* Call actual thread suspension routine. */ + _txm_module_thread_system_suspend(thread_ptr); + +#ifdef TX_SAFETY_CRITICAL + + /* If we ever get here, raise safety critical exception. */ + TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0); +#endif +} + diff --git a/ports_module/cortex-m3/iar/module_manager/src/tx_iar.c b/ports_module/cortex-m3/iar/module_manager/src/tx_iar.c new file mode 100644 index 00000000..dd719370 --- /dev/null +++ b/ports_module/cortex-m3/iar/module_manager/src/tx_iar.c @@ -0,0 +1,804 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** IAR Multithreaded Library Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Define IAR library for tools prior to version 8. */ + +#if (__VER__ < 8000000) + + +/* IAR version 7 and below. */ + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_mutex.h" + + +/* This implementation requires that the following macros are defined in the + tx_port.h file and is included with the following code segments: + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. + + Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. +*/ + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT + +#include + + +#if _MULTI_THREAD + +TX_MUTEX __tx_iar_system_lock_mutexes[_MAX_LOCK]; +UINT __tx_iar_system_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_system_lock_no_mutexes; +UINT __tx_iar_system_lock_internal_errors; +UINT __tx_iar_system_lock_isr_caller; + + +/* Define the TLS access function for the IAR library. */ + +void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) +{ + +char _DLIB_TLS_MEMORY *p = 0; + + /* Is there a current thread? */ + if (_tx_thread_current_ptr) + p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; + else + p = (void _DLIB_TLS_MEMORY *) __segment_begin("__DLIB_PERTHREAD"); + p += __IAR_DLIB_PERTHREAD_SYMBOL_OFFSET(symbp); + return (void _DLIB_TLS_MEMORY *) p; +} + + +/* Define mutexes for IAR library. */ + +void __iar_system_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_LOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_system_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_system_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_system_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_system_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_system_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } +} + +void __iar_system_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } +} + + +#if _DLIB_FILE_DESCRIPTOR + +TX_MUTEX __tx_iar_file_lock_mutexes[_MAX_FLOCK]; +UINT __tx_iar_file_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_file_lock_no_mutexes; +UINT __tx_iar_file_lock_internal_errors; +UINT __tx_iar_file_lock_isr_caller; + + +void __iar_file_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_FLOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_file_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_file_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_file_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_file_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_file_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} + +void __iar_file_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} +#endif /* _DLIB_FILE_DESCRIPTOR */ + +#endif /* _MULTI_THREAD */ + +#endif /* TX_ENABLE_IAR_LIBRARY_SUPPORT */ + +#else /* IAR version 8 and above. */ + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_mutex.h" + +/* This implementation requires that the following macros are defined in the + tx_port.h file and is included with the following code segments: + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +void *_tx_iar_create_per_thread_tls_area(void); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); +void __iar_Initlocks(void); + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. + + Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. +*/ + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT + +#include + + +void * __aeabi_read_tp(); + +void* _tx_iar_create_per_thread_tls_area(); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); + +#pragma section="__iar_tls$$DATA" + +/* Define the TLS access function for the IAR library. */ +void * __aeabi_read_tp(void) +{ + void *p = 0; + TX_THREAD *thread_ptr = _tx_thread_current_ptr; + if (thread_ptr) + { + p = thread_ptr->tx_thread_iar_tls_pointer; + } + else + { + p = __section_begin("__iar_tls$$DATA"); + } + return p; +} + +/* Define the TLS creation and destruction to use malloc/free. */ + +void* _tx_iar_create_per_thread_tls_area() +{ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ + void *p = malloc(tls_size); + + /* Initialize TLS-area and run constructors for objects in TLS */ + __iar_tls_init(p); + return p; +} + +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) +{ + /* Destroy objects living in TLS */ + __call_thread_dtors(); + free(tls_ptr); +} + +#ifndef _MAX_LOCK +#define _MAX_LOCK 4 +#endif + +static TX_MUTEX __tx_iar_system_lock_mutexes[_MAX_LOCK]; +static UINT __tx_iar_system_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_system_lock_no_mutexes; +UINT __tx_iar_system_lock_internal_errors; +UINT __tx_iar_system_lock_isr_caller; + + +/* Define mutexes for IAR library. */ + +void __iar_system_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_LOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_system_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_system_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_system_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_system_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_system_Mtxlock(__iar_Rmtx *m) +{ + if (*m) + { + UINT status; + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } + } +} + +void __iar_system_Mtxunlock(__iar_Rmtx *m) +{ + if (*m) + { + UINT status; + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } + } +} + + +#if _DLIB_FILE_DESCRIPTOR + +#include /* Added to get access to FOPEN_MAX */ +#ifndef _MAX_FLOCK +#define _MAX_FLOCK FOPEN_MAX /* Define _MAX_FLOCK as the maximum number of open files */ +#endif + + +TX_MUTEX __tx_iar_file_lock_mutexes[_MAX_FLOCK]; +UINT __tx_iar_file_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_file_lock_no_mutexes; +UINT __tx_iar_file_lock_internal_errors; +UINT __tx_iar_file_lock_isr_caller; + + +void __iar_file_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_FLOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_file_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_file_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_file_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_file_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_file_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} + +void __iar_file_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} +#endif /* _DLIB_FILE_DESCRIPTOR */ + +#endif /* TX_ENABLE_IAR_LIBRARY_SUPPORT */ + +#endif /* IAR version 8 and above. */ diff --git a/ports_module/cortex-m3/iar/module_manager/src/tx_misra.s b/ports_module/cortex-m3/iar/module_manager/src/tx_misra.s new file mode 100644 index 00000000..f6a6c3a5 --- /dev/null +++ b/ports_module/cortex-m3/iar/module_manager/src/tx_misra.s @@ -0,0 +1,1003 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** ThreadX MISRA Compliance */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + #define SHT_PROGBITS 0x1 + + EXTERN __aeabi_memset + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_interrupt_disable + EXTERN _tx_thread_interrupt_restore + EXTERN _tx_thread_stack_analyze + EXTERN _tx_thread_stack_error_handler + EXTERN _tx_thread_system_state +#ifdef TX_ENABLE_EVENT_TRACE + EXTERN _tx_trace_buffer_current_ptr + EXTERN _tx_trace_buffer_end_ptr + EXTERN _tx_trace_buffer_start_ptr + EXTERN _tx_trace_event_enable_bits + EXTERN _tx_trace_full_notify_function + EXTERN _tx_trace_header_ptr +#endif + + PUBLIC _tx_misra_always_true + PUBLIC _tx_misra_block_pool_to_uchar_pointer_convert + PUBLIC _tx_misra_byte_pool_to_uchar_pointer_convert + PUBLIC _tx_misra_char_to_uchar_pointer_convert + PUBLIC _tx_misra_const_char_to_char_pointer_convert +#ifdef TX_ENABLE_EVENT_TRACE + PUBLIC _tx_misra_entry_to_uchar_pointer_convert +#endif + PUBLIC _tx_misra_indirect_void_to_uchar_pointer_convert + PUBLIC _tx_misra_memset + PUBLIC _tx_misra_message_copy +#ifdef TX_ENABLE_EVENT_TRACE + PUBLIC _tx_misra_object_to_uchar_pointer_convert +#endif + PUBLIC _tx_misra_pointer_to_ulong_convert + PUBLIC _tx_misra_status_get + PUBLIC _tx_misra_thread_stack_check +#ifdef TX_ENABLE_EVENT_TRACE + PUBLIC _tx_misra_time_stamp_get +#endif + PUBLIC _tx_misra_timer_indirect_to_void_pointer_convert + PUBLIC _tx_misra_timer_pointer_add + PUBLIC _tx_misra_timer_pointer_dif +#ifdef TX_ENABLE_EVENT_TRACE + PUBLIC _tx_misra_trace_event_insert +#endif + PUBLIC _tx_misra_uchar_pointer_add + PUBLIC _tx_misra_uchar_pointer_dif + PUBLIC _tx_misra_uchar_pointer_sub + PUBLIC _tx_misra_uchar_to_align_type_pointer_convert + PUBLIC _tx_misra_uchar_to_block_pool_pointer_convert +#ifdef TX_ENABLE_EVENT_TRACE + PUBLIC _tx_misra_uchar_to_entry_pointer_convert + PUBLIC _tx_misra_uchar_to_header_pointer_convert +#endif + PUBLIC _tx_misra_uchar_to_indirect_byte_pool_pointer_convert + PUBLIC _tx_misra_uchar_to_indirect_uchar_pointer_convert +#ifdef TX_ENABLE_EVENT_TRACE + PUBLIC _tx_misra_uchar_to_object_pointer_convert +#endif + PUBLIC _tx_misra_uchar_to_void_pointer_convert + PUBLIC _tx_misra_ulong_pointer_add + PUBLIC _tx_misra_ulong_pointer_dif + PUBLIC _tx_misra_ulong_pointer_sub + PUBLIC _tx_misra_ulong_to_pointer_convert + PUBLIC _tx_misra_ulong_to_thread_pointer_convert + PUBLIC _tx_misra_user_timer_pointer_get + PUBLIC _tx_misra_void_to_block_pool_pointer_convert + PUBLIC _tx_misra_void_to_byte_pool_pointer_convert + PUBLIC _tx_misra_void_to_event_flags_pointer_convert + PUBLIC _tx_misra_void_to_indirect_uchar_pointer_convert + PUBLIC _tx_misra_void_to_mutex_pointer_convert + PUBLIC _tx_misra_void_to_queue_pointer_convert + PUBLIC _tx_misra_void_to_semaphore_pointer_convert + PUBLIC _tx_misra_void_to_thread_pointer_convert + PUBLIC _tx_misra_void_to_uchar_pointer_convert + PUBLIC _tx_misra_void_to_ulong_pointer_convert + PUBLIC _tx_misra_ipsr_get + PUBLIC _tx_version_id + + + SECTION `.data`:DATA:REORDER:NOROOT(2) + DATA +// 51 CHAR _tx_version_id[100] = "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX 6.0.1 MISRA C Compliant *"; +_tx_version_id: + DC8 43H, 6FH, 70H, 79H, 72H, 69H, 67H, 68H + DC8 74H, 20H, 28H, 63H, 29H, 20H, 31H, 39H + DC8 39H, 36H, 2DH, 32H, 30H, 31H, 38H, 20H + DC8 45H, 78H, 70H, 72H, 65H, 73H, 73H, 20H + DC8 4CH, 6FH, 67H, 69H, 63H, 20H, 49H, 6EH + DC8 63H, 2EH, 20H, 2AH, 20H, 54H, 68H, 72H + DC8 65H, 61H, 64H, 58H, 20H, 35H, 2EH, 38H + DC8 20H, 4DH, 49H, 53H, 52H, 41H, 20H, 43H + DC8 20H, 43H, 6FH, 6DH, 70H, 6CH, 69H, 61H + DC8 6EH, 74H, 20H, 2AH, 0 + DC8 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_memset(VOID *ptr, UINT value, UINT size); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_memset: + PUSH {R4,LR} + MOVS R4,R0 + MOVS R0,R2 + MOVS R2,R1 + MOVS R1,R0 + MOVS R0,R4 + BL __aeabi_memset + POP {R4,PC} ;; return + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UCHAR *_tx_misra_uchar_pointer_add(UCHAR *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_pointer_add: + ADD R0,R0,R1 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UCHAR *_tx_misra_uchar_pointer_sub(UCHAR *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_pointer_sub: + RSBS R1,R1,#+0 + ADD R0,R0,R1 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_uchar_pointer_dif(UCHAR *ptr1, UCHAR *ptr2); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_pointer_dif: + SUBS R0,R0,R1 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_pointer_to_ulong_convert: + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG *_tx_misra_ulong_pointer_add(ULONG *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_ulong_pointer_add: + ADD R0,R0,R1, LSL #+2 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG *_tx_misra_ulong_pointer_sub(ULONG *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_ulong_pointer_sub: + MVNS R2,#+3 + MULS R1,R2,R1 + ADD R0,R0,R1 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_ulong_pointer_dif(ULONG *ptr1, ULONG *ptr2); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_ulong_pointer_dif: + SUBS R0,R0,R1 + ASRS R0,R0,#+2 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_ulong_to_pointer_convert: + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_message_copy(ULONG **source, ULONG **destination, */ +/** UINT size); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_message_copy: + PUSH {R4,R5} + LDR R3,[R0, #+0] + LDR R4,[R1, #+0] + LDR R5,[R3, #+0] + STR R5,[R4, #+0] + ADDS R4,R4,#+4 + ADDS R3,R3,#+4 + CMP R2,#+2 + BCC.N ??_tx_misra_message_copy_0 + SUBS R2,R2,#+1 + B.N ??_tx_misra_message_copy_1 +??_tx_misra_message_copy_2: + LDR R5,[R3, #+0] + STR R5,[R4, #+0] + ADDS R4,R4,#+4 + ADDS R3,R3,#+4 + SUBS R2,R2,#+1 +??_tx_misra_message_copy_1: + CMP R2,#+0 + BNE.N ??_tx_misra_message_copy_2 +??_tx_misra_message_copy_0: + STR R3,[R0, #+0] + STR R4,[R1, #+0] + POP {R4,R5} + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_timer_pointer_dif(TX_TIMER_INTERNAL **ptr1, */ +/** TX_TIMER_INTERNAL **ptr2); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_timer_pointer_dif: + SUBS R0,R0,R1 + ASRS R0,R0,#+2 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** TX_TIMER_INTERNAL **_tx_misra_timer_pointer_add(TX_TIMER_INTERNAL */ +/** **ptr1, ULONG size); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_timer_pointer_add: + ADD R0,R0,R1, LSL #+2 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_user_timer_pointer_get(TX_TIMER_INTERNAL */ +/** *internal_timer, TX_TIMER **user_timer); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_user_timer_pointer_get: + ADDS R2,R0,#+8 + SUBS R2,R2,R0 + RSBS R2,R2,#+0 + ADD R0,R0,R2 + STR R0,[R1, #+0] + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_thread_stack_check(TX_THREAD *thread_ptr, */ +/** VOID **highest_stack); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_thread_stack_check: + PUSH {R3-R5,LR} + MOVS R4,R0 + MOVS R5,R1 + BL _tx_thread_interrupt_disable + CMP R4,#+0 + BEQ.N ??_tx_misra_thread_stack_check_0 + LDR R1,[R4, #+0] + LDR.N R2,??DataTable2 ;; 0x54485244 + CMP R1,R2 + BNE.N ??_tx_misra_thread_stack_check_0 + LDR R1,[R4, #+8] + LDR R2,[R5, #+0] + CMP R1,R2 + BCS.N ??_tx_misra_thread_stack_check_1 + LDR R1,[R4, #+8] + STR R1,[R5, #+0] +??_tx_misra_thread_stack_check_1: + LDR R1,[R4, #+12] + LDR R1,[R1, #+0] + CMP R1,#-269488145 + BNE.N ??_tx_misra_thread_stack_check_2 + LDR R1,[R4, #+16] + LDR R1,[R1, #+1] + CMP R1,#-269488145 + BNE.N ??_tx_misra_thread_stack_check_2 + LDR R1,[R5, #+0] + LDR R2,[R4, #+12] + CMP R1,R2 + BCS.N ??_tx_misra_thread_stack_check_3 +??_tx_misra_thread_stack_check_2: + BL _tx_thread_interrupt_restore + MOVS R0,R4 + BL _tx_thread_stack_error_handler + BL _tx_thread_interrupt_disable +??_tx_misra_thread_stack_check_3: + LDR R1,[R5, #+0] + LDR R1,[R1, #-4] + CMP R1,#-269488145 + BEQ.N ??_tx_misra_thread_stack_check_0 + BL _tx_thread_interrupt_restore + MOVS R0,R4 + BL _tx_thread_stack_analyze + BL _tx_thread_interrupt_disable +??_tx_misra_thread_stack_check_0: + BL _tx_thread_interrupt_restore + POP {R0,R4,R5,PC} ;; return + +#ifdef TX_ENABLE_EVENT_TRACE + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_trace_event_insert(ULONG event_id, */ +/** VOID *info_field_1, ULONG info_field_2, ULONG info_field_3, */ +/** ULONG info_field_4, ULONG filter, ULONG time_stamp); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_trace_event_insert: + PUSH {R3-R7,LR} + LDR.N R4,??DataTable2_1 + LDR R4,[R4, #+0] + CMP R4,#+0 + BEQ.N ??_tx_misra_trace_event_insert_0 + LDR.N R5,??DataTable2_2 + LDR R5,[R5, #+0] + LDR R6,[SP, #+28] + TST R5,R6 + BEQ.N ??_tx_misra_trace_event_insert_0 + LDR.N R5,??DataTable2_3 + LDR R5,[R5, #+0] + LDR.N R6,??DataTable2_4 + LDR R6,[R6, #+0] + CMP R5,#+0 + BNE.N ??_tx_misra_trace_event_insert_1 + LDR R5,[R6, #+44] + LDR R7,[R6, #+60] + LSLS R7,R7,#+16 + ORRS R7,R7,#0x80000000 + ORRS R5,R7,R5 + B.N ??_tx_misra_trace_event_insert_2 +??_tx_misra_trace_event_insert_1: + CMP R5,#-252645136 + BCS.N ??_tx_misra_trace_event_insert_3 + MOVS R5,R6 + MOVS R6,#-1 + B.N ??_tx_misra_trace_event_insert_2 +??_tx_misra_trace_event_insert_3: + MOVS R6,#-252645136 + MOVS R5,#+0 +??_tx_misra_trace_event_insert_2: + STR R6,[R4, #+0] + STR R5,[R4, #+4] + STR R0,[R4, #+8] + LDR R0,[SP, #+32] + STR R0,[R4, #+12] + STR R1,[R4, #+16] + STR R2,[R4, #+20] + STR R3,[R4, #+24] + LDR R0,[SP, #+24] + STR R0,[R4, #+28] + ADDS R4,R4,#+32 + LDR.N R0,??DataTable2_5 + LDR R0,[R0, #+0] + CMP R4,R0 + BCC.N ??_tx_misra_trace_event_insert_4 + LDR.N R0,??DataTable2_6 + LDR R4,[R0, #+0] + LDR.N R0,??DataTable2_1 + STR R4,[R0, #+0] + LDR.N R0,??DataTable2_7 + LDR R0,[R0, #+0] + STR R4,[R0, #+32] + LDR.N R0,??DataTable2_8 + LDR R0,[R0, #+0] + CMP R0,#+0 + BEQ.N ??_tx_misra_trace_event_insert_0 + LDR.N R0,??DataTable2_7 + LDR R0,[R0, #+0] + LDR.N R1,??DataTable2_8 + LDR R1,[R1, #+0] + BLX R1 + B.N ??_tx_misra_trace_event_insert_0 +??_tx_misra_trace_event_insert_4: + LDR.N R0,??DataTable2_1 + STR R4,[R0, #+0] + LDR.N R0,??DataTable2_7 + LDR R0,[R0, #+0] + STR R4,[R0, #+32] +??_tx_misra_trace_event_insert_0: + POP {R0,R4-R7,PC} ;; return + + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_1: + DC32 _tx_trace_buffer_current_ptr + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_2: + DC32 _tx_trace_event_enable_bits + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_5: + DC32 _tx_trace_buffer_end_ptr + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_6: + DC32 _tx_trace_buffer_start_ptr + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_7: + DC32 _tx_trace_header_ptr + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_8: + DC32 _tx_trace_full_notify_function + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_time_stamp_get(VOID); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_time_stamp_get: + MOVS R0,#+0 + BX LR ;; return + +#endif + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2: + DC32 0x54485244 + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_3: + DC32 _tx_thread_system_state + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_4: + DC32 _tx_thread_current_ptr + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UINT _tx_misra_always_true(void); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_always_true: + MOVS R0,#+1 + BX LR ;; return + + +/******************************************************************************************/ +/******************************************************************************************/ +/** */ +/** UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr); */ +/** */ +/******************************************************************************************/ +/******************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_indirect_void_to_uchar_pointer_convert: + BX LR ;; return + + +/***************************************************************************************/ +/***************************************************************************************/ +/** */ +/** UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); */ +/** */ +/***************************************************************************************/ +/***************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_indirect_uchar_pointer_convert: + BX LR ;; return + + +/***********************************************************************************/ +/***********************************************************************************/ +/** */ +/** UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); */ +/** */ +/***********************************************************************************/ +/***********************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_block_pool_to_uchar_pointer_convert: + BX LR ;; return + + +/******************************************************************************************/ +/******************************************************************************************/ +/** */ +/** TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); */ +/** */ +/******************************************************************************************/ +/******************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_block_pool_pointer_convert: + BX LR ;; return + + +/*****************************************************************************/ +/*****************************************************************************/ +/** */ +/** UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); */ +/** */ +/*****************************************************************************/ +/*****************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_uchar_pointer_convert: + BX LR ;; return + + +/************************************************************************************/ +/************************************************************************************/ +/** */ +/** TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); */ +/** */ +/************************************************************************************/ +/************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_block_pool_pointer_convert: + BX LR ;; return + + +/**************************************************************************************/ +/**************************************************************************************/ +/** */ +/** UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); */ +/** */ +/**************************************************************************************/ +/**************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_indirect_uchar_pointer_convert: + BX LR ;; return + + +/*****************************************************************************************/ +/*****************************************************************************************/ +/** */ +/** TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); */ +/** */ +/*****************************************************************************************/ +/*****************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_byte_pool_pointer_convert: + BX LR ;; return + + +/***************************************************************************************/ +/***************************************************************************************/ +/** */ +/** UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); */ +/** */ +/***************************************************************************************/ +/***************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_byte_pool_to_uchar_pointer_convert: + BX LR ;; return + + +/*****************************************************************************************/ +/*****************************************************************************************/ +/** */ +/** ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); */ +/** */ +/*****************************************************************************************/ +/*****************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_align_type_pointer_convert: + BX LR ;; return + + +/****************************************************************************************************/ +/****************************************************************************************************/ +/** */ +/** TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); */ +/** */ +/****************************************************************************************************/ +/****************************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_indirect_byte_pool_pointer_convert: + BX LR ;; return + + +/**************************************************************************************************/ +/**************************************************************************************************/ +/** */ +/** TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); */ +/** */ +/**************************************************************************************************/ +/**************************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_event_flags_pointer_convert: + BX LR ;; return + + +/*****************************************************************************/ +/*****************************************************************************/ +/** */ +/** ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); */ +/** */ +/*****************************************************************************/ +/*****************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_ulong_pointer_convert: + BX LR ;; return + + +/********************************************************************************/ +/********************************************************************************/ +/** */ +/** TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); */ +/** */ +/********************************************************************************/ +/********************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_mutex_pointer_convert: + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UINT _tx_misra_status_get(UINT status); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_status_get: + MOVS R0,#+0 + BX LR ;; return + + +/********************************************************************************/ +/********************************************************************************/ +/** */ +/** TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); */ +/** */ +/********************************************************************************/ +/********************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_queue_pointer_convert: + BX LR ;; return + + +/****************************************************************************************/ +/****************************************************************************************/ +/** */ +/** TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); */ +/** */ +/****************************************************************************************/ +/****************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_semaphore_pointer_convert: + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_void_pointer_convert: + BX LR ;; return + + +/*********************************************************************************/ +/*********************************************************************************/ +/** */ +/** TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); */ +/** */ +/*********************************************************************************/ +/*********************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_ulong_to_thread_pointer_convert: + BX LR ;; return + + +/***************************************************************************************************/ +/***************************************************************************************************/ +/** */ +/** VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); */ +/** */ +/***************************************************************************************************/ +/***************************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_timer_indirect_to_void_pointer_convert: + BX LR ;; return + + +/***************************************************************************************/ +/***************************************************************************************/ +/** */ +/** CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); */ +/** */ +/***************************************************************************************/ +/***************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_const_char_to_char_pointer_convert: + BX LR ;; return + + +/**********************************************************************************/ +/**********************************************************************************/ +/** */ +/** TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer); */ +/** */ +/**********************************************************************************/ +/**********************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_thread_pointer_convert: + BX LR ;; return + + +#ifdef TX_ENABLE_EVENT_TRACE + +/************************************************************************************************/ +/************************************************************************************************/ +/** */ +/** UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); */ +/** */ +/************************************************************************************************/ +/************************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_object_to_uchar_pointer_convert: + BX LR ;; return + + +/************************************************************************************************/ +/************************************************************************************************/ +/** */ +/** TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); */ +/** */ +/************************************************************************************************/ +/************************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_object_pointer_convert: + BX LR ;; return + + +/******************************************************************************************/ +/******************************************************************************************/ +/** */ +/** TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); */ +/** */ +/******************************************************************************************/ +/******************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_header_pointer_convert: + BX LR ;; return + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_entry_pointer_convert: + BX LR ;; return + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_entry_to_uchar_pointer_convert: + BX LR ;; return +#endif + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_char_to_uchar_pointer_convert: + BX LR ;; return + + +***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** ULONG _tx_misra_ipsr_get(void); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_ipsr_get: + MRS R0, IPSR + BX LR ;; return + + + SECTION `.iar_vfe_header`:DATA:NOALLOC:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA + DC32 0 + + END diff --git a/ports_module/cortex-m3/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex-m3/iar/module_manager/src/tx_thread_context_restore.s new file mode 100644 index 00000000..e3e42286 --- /dev/null +++ b/ports_module/cortex-m3/iar/module_manager/src/tx_thread_context_restore.s @@ -0,0 +1,97 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + EXTERN _tx_execution_isr_exit +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-M3/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* [_tx_execution_isr_exit] Execution profiling ISR exit */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + PUBLIC _tx_thread_context_restore +_tx_thread_context_restore: + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + PUSH {r0,lr} ; Save ISR lr + BL _tx_execution_isr_exit ; Call the ISR exit function + POP {r0,lr} ; Restore ISR lr +#endif +; + POP {lr} + BX lr +; +;} + END diff --git a/ports_module/cortex-m3/iar/module_manager/src/tx_thread_context_save.s b/ports_module/cortex-m3/iar/module_manager/src/tx_thread_context_save.s new file mode 100644 index 00000000..49e11d68 --- /dev/null +++ b/ports_module/cortex-m3/iar/module_manager/src/tx_thread_context_save.s @@ -0,0 +1,96 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + EXTERN _tx_execution_isr_enter +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-M3/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* [_tx_execution_isr_enter] Execution profiling ISR enter */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + PUBLIC _tx_thread_context_save +_tx_thread_context_save: +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is starting. */ +; + PUSH {r0, lr} ; Save return address + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {r0, lr} ; Recover return address +#endif +; +; /* Context is already saved - just return! */ +; + BX lr +;} + END + diff --git a/ports_module/cortex-m3/iar/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex-m3/iar/module_manager/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..d956fd6d --- /dev/null +++ b/ports_module/cortex-m3/iar/module_manager/src/tx_thread_interrupt_control.s @@ -0,0 +1,86 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-M3/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + PUBLIC _tx_thread_interrupt_control +_tx_thread_interrupt_control: +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r1, PRIMASK + MSR PRIMASK, r0 + MOV r0, r1 + BX lr +; +;} + END + diff --git a/ports_module/cortex-m3/iar/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex-m3/iar/module_manager/src/tx_thread_interrupt_disable.s new file mode 100644 index 00000000..38a2083d --- /dev/null +++ b/ports_module/cortex-m3/iar/module_manager/src/tx_thread_interrupt_disable.s @@ -0,0 +1,84 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-M3/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts and returning */ +;/* the previous interrupt lockout posture. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(UINT new_posture) +;{ + PUBLIC _tx_thread_interrupt_disable +_tx_thread_interrupt_disable: +; +; /* Return current interrupt lockout posture. */ +; + MRS r0, PRIMASK + CPSID i + BX lr +; +;} + END diff --git a/ports_module/cortex-m3/iar/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex-m3/iar/module_manager/src/tx_thread_interrupt_restore.s new file mode 100644 index 00000000..356c8aac --- /dev/null +++ b/ports_module/cortex-m3/iar/module_manager/src/tx_thread_interrupt_restore.s @@ -0,0 +1,83 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-M3/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for restoring the previous */ +;/* interrupt lockout posture. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* previous_posture Previous interrupt posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_interrupt_restore(UINT new_posture) +;{ + PUBLIC _tx_thread_interrupt_restore +_tx_thread_interrupt_restore: +; +; /* Restore previous interrupt lockout posture. */ +; + MSR PRIMASK, r0 + BX lr +; +;} + END diff --git a/ports_module/cortex-m3/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex-m3/iar/module_manager/src/tx_thread_schedule.s new file mode 100644 index 00000000..20ce37cc --- /dev/null +++ b/ports_module/cortex-m3/iar/module_manager/src/tx_thread_schedule.s @@ -0,0 +1,526 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_execution_thread_enter + EXTERN _tx_execution_thread_exit + EXTERN _tx_thread_preempt_disable + EXTERN _txm_module_manager_memory_fault_handler + EXTERN _txm_module_manager_memory_fault_info +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-M3/MPU/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + PUBLIC _tx_thread_schedule +_tx_thread_schedule: +; +; /* This function should only ever be called on Cortex-M +; from the first schedule request. Subsequent scheduling occurs +; from the PendSV handling routines below. */ +; +; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ +; + MOV r0, #0 ; Build value for TX_FALSE + LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag + STR r0, [r2, #0] ; Clear preempt disable flag +; +; /* Enable memory fault registers. */ +; + LDR r0, =0xE000ED24 ; Build SHCSR address + LDR r1, =0x70000 ; Enable Usage, Bus, and MemManage faults + STR r1, [r0] ; +; +; /* Enable interrupts */ +; + CPSIE i +; +; /* Enter the scheduler for the first time. */ +; + MOV r0, #0x10000000 ; Load PENDSVSET bit + MOV r1, #0xE000E000 ; Load NVIC base + STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR + NOP ; + NOP ; + NOP ; + NOP ; +; +; /* We should never get here - ever! */ +; + BKPT 0xEF ; Setup error conditions + BX lr ; +;} +; + +; +; /* Memory Exception Handler. */ +; + PUBLIC MemManage_Handler +MemManage_Handler: +;{ + CPSID i ; Disable interrupts +; +; /* Now pickup and store all the fault related information. */ +; + LDR r12,=_txm_module_manager_memory_fault_info ; Pickup fault info struct + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup the current thread pointer + STR r1, [r12, #0] ; Save current thread pointer in fault info structure + LDR r0, =0xE000ED24 ; Build SHCSR address + LDR r1, [r0] ; Pickup SHCSR + STR r1, [r12, #8] ; Save SHCSR + LDR r0, =0xE000ED28 ; Build MMFSR address + LDR r1, [r0] ; Pickup MMFSR (and other fault status too!) + STR r1, [r12, #12] ; Save MMFSR + LDR r0, =0xE000ED34 ; Build MMFAR address + LDR r1, [r0] ; Pickup MMFAR + STR r1, [r12, #16] ; Save MMFAR + MRS r0, CONTROL ; Pickup current CONTROL register + STR r0, [r12, #20] ; Save CONTROL + MRS r1, PSP ; Pickup thread stack pointer + STR r1, [r12, #24] ; Save thread stack pointer + LDR r0, [r1] ; Pickup saved r0 + STR r0, [r12, #28] ; Save r0 + LDR r0, [r1, #4] ; Pickup saved r1 + STR r0, [r12, #32] ; Save r1 + STR r2, [r12, #36] ; Save r2 + STR r3, [r12, #40] ; Save r3 + STR r4, [r12, #44] ; Save r4 + STR r5, [r12, #48] ; Save r5 + STR r6, [r12, #52] ; Save r6 + STR r7, [r12, #56] ; Save r7 + STR r8, [r12, #60] ; Save r8 + STR r9, [r12, #64] ; Save r9 + STR r10,[r12, #68] ; Save r10 + STR r11,[r12, #72] ; Save r11 + LDR r0, [r1, #16] ; Pickup saved r12 + STR r0, [r12, #76] ; Save r12 + LDR r0, [r1, #20] ; Pickup saved lr + STR r0, [r12, #80] ; Save lr + LDR r0, [r1, #24] ; Pickup instruction address at point of fault + STR r0, [r12, #4] ; Save point of fault + LDR r0, [r1, #28] ; Pickup xPSR + STR r0, [r12, #84] ; Save xPSR + + MRS r0, CONTROL ; Pickup current CONTROL register + BIC r0, r0, #1 ; Clear the UNPRIV bit + MSR CONTROL, r0 ; Setup new CONTROL register + + LDR r0, =0xE000ED28 ; Build the Memory Management Fault Status Register (MMFSR) + LDRB r1, [r0] ; Pickup the MMFSR, with the following bit definitions: + ; Bit 0 = 1 -> Instruction address violation + ; Bit 1 = 1 -> Load/store address violation + ; Bit 7 = 1 -> MMFAR is valid + STRB r1, [r0] ; Clear the MMFSR + + BL _txm_module_manager_memory_fault_handler ; Call memory manager fault handler + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + CPSID i ; Disable interrupts + BL _tx_execution_thread_exit ; Call the thread exit function + CPSIE i ; Enable interrupts +#endif + + MOV r1, #0 ; Build NULL value + LDR r0, =_tx_thread_current_ptr ; Pickup address of current thread pointer + STR r1, [r0] ; Clear current thread pointer + + ; Return from MemManage_Handler exception + LDR r0, =0xE000ED04 ; Load ICSR + LDR r1, =0x10000000 ; Set PENDSVSET bit + STR r1, [r0] ; Store ICSR + DSB ; Wait for memory access to complete + CPSIE i ; Enable interrupts + MOV lr, #0xFFFFFFFD ; Load exception return code + BX lr ; Return from exception +;} + +; +; /* Generic context PendSV handler. */ +; + PUBLIC PendSV_Handler + PUBLIC __tx_PendSVHandler +PendSV_Handler: +__tx_PendSVHandler: +; +; /* Get current thread value and new thread pointer. */ +; +__tx_ts_handler: + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + CPSID i ; Disable interrupts + PUSH {r0, lr} ; Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit ; Call the thread exit function + POP {r0, lr} ; Recover LR + CPSIE i ; Enable interrupts +#endif + MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address + MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address + MOV r3, #0 ; Build NULL value + LDR r1, [r0] ; Pickup current thread pointer +; +; /* Determine if there is a current thread to finish preserving. */ +; + CBZ r1, __tx_ts_new ; If NULL, skip preservation +; +; /* Recover PSP and preserve current thread context. */ +; + STR r3, [r0] ; Set _tx_thread_current_ptr to NULL + MRS r12, PSP ; Pickup PSP pointer (thread's stack pointer) + STMDB r12!, {r4-r11} ; Save its remaining registers + MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable + STMDB r12!, {LR} ; Save LR on the stack +; +; /* Determine if time-slice is active. If it isn't, skip time handling processing. */ +; + LDR r5, [r4] ; Pickup current time-slice + STR r12, [r1, #8] ; Save the thread stack pointer + CBZ r5, __tx_ts_new ; If not active, skip processing +; +; /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ +; + STR r5, [r1, #24] ; Save current time-slice +; +; /* Clear the global time-slice. */ +; + STR r3, [r4] ; Clear time-slice +; +; +; /* Executing thread is now completely preserved!!! */ +; +__tx_ts_new: +; +; /* Now we are looking for a new thread to execute! */ +; + CPSID i ; Disable interrupts + LDR r1, [r2] ; Is there another thread ready to execute? + CBZ r1, __tx_ts_wait ; No, skip to the wait processing +; +; /* Yes, another thread is ready for else, make the current thread the new thread. */ +; + STR r1, [r0] ; Setup the current thread pointer to the new thread + CPSIE i ; Enable interrupts +; +; /* Increment the thread run count. */ +; +__tx_ts_restore: + LDR r7, [r1, #4] ; Pickup the current thread run count + MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable + LDR r5, [r1, #24] ; Pickup thread's current time-slice + ADD r7, r7, #1 ; Increment the thread run count + STR r7, [r1, #4] ; Store the new run count +; +; /* Setup global time-slice with thread's current time-slice. */ +; + STR r5, [r4] ; Setup global time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + PUSH {r0, r1} ; Save r0 and r1 + BL _tx_execution_thread_enter ; Call the thread execution enter function + POP {r0, r1} ; Recover r0 and r1 +#endif +; +; /* Restore the thread context and PSP. */ +; + LDR r12, [r1, #8] ; Pickup thread's stack pointer + + MRS r5, CONTROL ; Pickup current CONTROL register + LDR r4, [r1, #0x98] ; Pickup current user mode flag + BIC r5, r5, #1 ; Clear the UNPRIV bit + ORR r4, r4, r5 ; Build new CONTROL register + MSR CONTROL, r4 ; Setup new CONTROL register + + LDR r0, =0xE000ED94 ; Build MPU control reg address + MOV r3, #0 ; Build disable value + STR r3, [r0] ; Disable MPU + LDR r0, [r1, #0x90] ; Pickup the module instance pointer + CBZ r0, skip_mpu_setup ; Is this thread owned by a module? No, skip MPU setup + LDR r1, [r0, #0x64] ; Pickup MPU register[0] + CBZ r1, skip_mpu_setup ; Is protection required for this module? No, skip MPU setup + LDR r1, =0xE000ED9C ; Build address of MPU base register + + ; Use alias registers to quickly load MPU + ADD r0, r0, #100 ; Build address of MPU register start in thread control block + LDM r0!,{r2-r9} ; Load first four MPU regions + STM r1,{r2-r9} ; Store first four MPU regions + LDM r0,{r2-r9} ; Load second four MPU regions + STM r1,{r2-r9} ; Store second four MPU regions + LDR r0, =0xE000ED94 ; Build MPU control reg address + MOV r1, #5 ; Build enable value + STR r1, [r0] ; Enable MPU +skip_mpu_setup: + LDMIA r12!, {LR} ; Pickup LR + LDMIA r12!, {r4-r11} ; Recover thread's registers + MSR PSP, r12 ; Setup the thread's stack pointer +; +; /* Return to thread. */ +; + BX lr ; Return to thread! +; +; /* The following is the idle wait processing... in this case, no threads are ready for execution and the +; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +; are disabled to allow use of WFI for waiting for a thread to arrive. */ +; +__tx_ts_wait: + CPSID i ; Disable interrupts + LDR r1, [r2] ; Pickup the next thread to execute pointer + STR r1, [r0] ; Store it in the current pointer + CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready! +#ifdef TX_ENABLE_WFI + DSB ; Ensure no outstanding memory transactions + WFI ; Wait for interrupt + ISB ; Ensure pipeline is flushed +#endif + CPSIE i ; Enable interrupts + B __tx_ts_wait ; Loop to continue waiting +; +; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +; already in the handler! */ +; +__tx_ts_ready: + MOV r7, #0x08000000 ; Build clear PendSV value + MOV r8, #0xE000E000 ; Build base NVIC address + STR r7, [r8, #0xD04] ; Clear any PendSV +; +; /* Re-enable interrupts and restore new thread. */ +; + CPSIE i ; Enable interrupts + B __tx_ts_restore ; Restore the thread +;} + +; +; /* SVC Handler. */ +; + PUBLIC SVC_Handler + PUBLIC __tx_SVCallHandler +SVC_Handler: +__tx_SVCallHandler: +;{ + MRS r0, PSP ; Pickup the PSP stack + LDR r1, [r0, #24] ; Pickup the point of interrupt + LDRB r2, [r1, #-2] ; Pickup the SVC parameter + ; + ; Determine which SVC trap we are processing + ; + CMP r2, #1 ; Is it the entry into ThreadX? + BNE _tx_thread_user_return ; No, return to user mode + ; + ; At this point we have an SVC 1, which means we are entering the kernel from a module thread with user mode selected + ; + LDR r2, =_txm_module_priv-1 ; Subtract 1 because of THUMB mode. + CMP r1, r2 ; Did we come from user_mode_entry? + IT NE ; If no (not equal), then... + BXNE lr ; return from where we came. + + LDR r3, [r0, #20] ; This is the saved LR + LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r2, [r1] ; Pickup current thread pointer + MOV r1, #0 ; Build clear value + STR r1, [r2, #0x98] ; Clear the current user mode selection for thread + STR r3, [r2, #0xA0] ; Save the original LR in thread control block + + ; If there is memory protection, use kernel stack + LDR r0, [r2, #0x90] ; Load the module instance ptr + LDR r0, [r0, #0x0C] ; Load the module property flags + TST r0, #2 ; Check if memory protected + BEQ _tx_skip_kernel_stack_enter + + ; Switch to the module thread's kernel stack + LDR r0, [r2, #0xA8] ; Load the module kernel stack end +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r1, [r2, #0xA4] ; Load the module kernel stack start + LDR r3, [r2, #0xAC] ; Load the module kernel stack size + STR r1, [r2, #12] ; Set stack start + STR r0, [r2, #16] ; Set stack end + STR r3, [r2, #20] ; Set stack size +#endif + + MRS r3, PSP ; Pickup thread stack pointer + STR r3, [r2, #0xB0] ; Save thread stack pointer + + ; Build kernel stack by copying thread stack two registers at a time + ADD r3, r3, #32 ; start at bottom of hardware stack + LDMDB r3!,{r1-r2} ; + STMDB r0!,{r1-r2} ; + LDMDB r3!,{r1-r2} ; + STMDB r0!,{r1-r2} ; + LDMDB r3!,{r1-r2} ; + STMDB r0!,{r1-r2} ; + LDMDB r3!,{r1-r2} ; + STMDB r0!,{r1-r2} ; + + MSR PSP, r0 ; Set kernel stack pointer + +_tx_skip_kernel_stack_enter: + MRS r0, CONTROL ; Pickup current CONTROL register + BIC r0, r0, #1 ; Clear the UNPRIV bit + MSR CONTROL, r0 ; Setup new CONTROL register + BX lr ; Return to thread + +_tx_thread_user_return: + + LDR r2, =_txm_module_user_mode_exit-1 ; Subtract 1 because of THUMB mode. + CMP r1, r2 ; Did we come from user_mode_exit? + IT NE ; If no (not equal), then... + BXNE lr ; return from where we came + + LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r2, [r1] ; Pickup current thread pointer + LDR r1, [r2, #0x9C] ; Pick up user mode + STR r1, [r2, #0x98] ; Set the current user mode selection for thread + + ; If there is memory protection, use kernel stack + LDR r0, [r2, #0x90] ; Load the module instance ptr + LDR r0, [r0, #0x0C] ; Load the module property flags + TST r0, #2 ; Check if memory protected + BEQ _tx_skip_kernel_stack_exit + +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r0, [r2, #0xB4] ; Load the module thread stack start + LDR r1, [r2, #0xB8] ; Load the module thread stack end + LDR r3, [r2, #0xBC] ; Load the module thread stack size + STR r0, [r2, #12] ; Set stack start + STR r1, [r2, #16] ; Set stack end + STR r3, [r2, #20] ; Set stack size +#endif + LDR r0, [r2, #0xB0] ; Load the module thread stack pointer + MRS r3, PSP ; Pickup kernel stack pointer + + ; Copy kernel hardware stack to module thread stack. + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + SUB r0, r0, #32 ; Subtract 32 to get back to top of stack + MSR PSP, r0 ; Set thread stack pointer + + LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r2, [r1] ; Pickup current thread pointer + LDR r1, [r2, #0x9C] ; Pick up user mode + +_tx_skip_kernel_stack_exit: + MRS r0, CONTROL ; Pickup current CONTROL register + ORR r0, r0, r1 ; OR in the user mode bit + MSR CONTROL, r0 ; Setup new CONTROL register + BX lr ; Return to thread +;} + +; +; /* Kernel entry function from user mode. */ +; + EXTERN _txm_module_manager_kernel_dispatch +; + SECTION `.text`:CODE:NOROOT(5) + THUMB + ALIGNROM 5 +;VOID _txm_module_manager_user_mode_entry(VOID) +;{ + PUBLIC _txm_module_manager_user_mode_entry +_txm_module_manager_user_mode_entry: + SVC 1 ; Enter kernel +_txm_module_priv: + ; At this point, we are out of user mode. The original LR has been saved in the + ; thread control block. Simply call the kernel dispatch function. + BL _txm_module_manager_kernel_dispatch + + ; Pickup the original LR value while still in privileged mode + LDR r2, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r3, [r2] ; Pickup current thread pointer + LDR lr, [r3, #0xA0] ; Pickup saved LR from original call + + SVC 2 ; Exit kernel and return to user mode +_txm_module_user_mode_exit: + BX lr ; Return to the caller + NOP + NOP + NOP + NOP +;} + END diff --git a/ports_module/cortex-m3/iar/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex-m3/iar/module_manager/src/tx_thread_stack_build.s new file mode 100644 index 00000000..86734467 --- /dev/null +++ b/ports_module/cortex-m3/iar/module_manager/src/tx_thread_stack_build.s @@ -0,0 +1,135 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-M3/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + PUBLIC _tx_thread_stack_build +_tx_thread_stack_build: +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-M should look like the following after it is built: +; +; Stack Top: +; LR Interrupted LR (LR at time of PENDSV) +; r4 Initial value for r4 +; r5 Initial value for r5 +; r6 Initial value for r6 +; r7 Initial value for r7 +; r8 Initial value for r8 +; r9 Initial value for r9 +; r10 Initial value for r10 +; r11 Initial value for r11 +; r0 Initial value for r0 (Hardware stack starts here!!) +; r1 Initial value for r1 +; r2 Initial value for r2 +; r3 Initial value for r3 +; r12 Initial value for r12 +; lr Initial value for lr +; pc Initial value for pc +; xPSR Initial value for xPSR +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #0x7 ; Align frame for 8-byte alignment + SUB r2, r2, #68 ; Subtract frame size + LDR r3, =0xFFFFFFFD ; Build initial LR value + STR r3, [r2, #0] ; Save on the stack +; +; /* Actually build the stack frame. */ +; + MOV r3, #0 ; Build initial register value + STR r3, [r2, #4] ; Store initial r4 + STR r3, [r2, #8] ; Store initial r5 + STR r3, [r2, #12] ; Store initial r6 + STR r3, [r2, #16] ; Store initial r7 + STR r3, [r2, #20] ; Store initial r8 + STR r3, [r2, #24] ; Store initial r9 + STR r3, [r2, #28] ; Store initial r10 + STR r3, [r2, #32] ; Store initial r11 +; +; /* Hardware stack follows. */ +; + STR r3, [r2, #36] ; Store initial r0 + STR r3, [r2, #40] ; Store initial r1 + STR r3, [r2, #44] ; Store initial r2 + STR r3, [r2, #48] ; Store initial r3 + STR r3, [r2, #52] ; Store initial r12 + MOV r3, #0xFFFFFFFF ; Poison EXC_RETURN value + STR r3, [r2, #56] ; Store initial lr + STR r1, [r2, #60] ; Store initial pc + MOV r3, #0x01000000 ; Only T-bit need be set + STR r3, [r2, #64] ; Store initial xPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block + BX lr ; Return to caller +;} + END + diff --git a/ports_module/cortex-m3/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex-m3/iar/module_manager/src/tx_thread_system_return.s new file mode 100644 index 00000000..fa0ef7a3 --- /dev/null +++ b/ports_module/cortex-m3/iar/module_manager/src/tx_thread_system_return.s @@ -0,0 +1,98 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-M3/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + PUBLIC _tx_thread_system_return +_tx_thread_system_return??rA: +_tx_thread_system_return: +; +; /* Return to real scheduler via PendSV. Note that this routine is often +; replaced with in-line assembly in tx_port.h to improved performance. */ +; + MOV r0, #0x10000000 ; Load PENDSVSET bit + MOV r1, #0xE000E000 ; Load NVIC base + STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR + MRS r0, IPSR ; Pickup IPSR + CMP r0, #0 ; Is it a thread returning? + BNE _isr_context ; If ISR, skip interrupt enable + MRS r1, PRIMASK ; Thread context returning, pickup PRIMASK + CPSIE i ; Enable interrupts + MSR PRIMASK, r1 ; Restore original interrupt posture +_isr_context: + BX lr ; Return to caller +;} + END + diff --git a/ports_module/cortex-m3/iar/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex-m3/iar/module_manager/src/tx_timer_interrupt.s new file mode 100644 index 00000000..94af5d87 --- /dev/null +++ b/ports_module/cortex-m3/iar/module_manager/src/tx_timer_interrupt.s @@ -0,0 +1,268 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_timer.h" +;#include "tx_thread.h" +; +; +;Define Assembly language external references... +; + EXTERN _tx_timer_time_slice + EXTERN _tx_timer_system_clock + EXTERN _tx_timer_current_ptr + EXTERN _tx_timer_list_start + EXTERN _tx_timer_list_end + EXTERN _tx_timer_expired_time_slice + EXTERN _tx_timer_expired + EXTERN _tx_thread_time_slice + EXTERN _tx_timer_expiration_process + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_thread_preempt_disable +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-M3/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* expiration functions are called. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + PUBLIC _tx_timer_interrupt +_tx_timer_interrupt: +; +; /* Upon entry to this routine, it is assumed that the compiler scratch registers are available +; for use. */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + MOV32 r1, _tx_timer_system_clock ; Pickup address of system clock + LDR r0, [r1, #0] ; Pickup system clock + ADD r0, r0, #1 ; Increment system clock + STR r0, [r1, #0] ; Store new system clock +; +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice + LDR r2, [r3, #0] ; Pickup time-slice + CBZ r2, __tx_timer_no_time_slice ; Is it non-active? + ; Yes, skip time-slice processing +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; + SUB r2, r2, #1 ; Decrement the time-slice + STR r2, [r3, #0] ; Store new time-slice value +; +; /* Check for expiration. */ +; if (__tx_timer_time_slice == 0) +; + CBNZ r2, __tx_timer_no_time_slice ; Has it expired? +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup address of expired flag + MOV r0, #1 ; Build expired value + STR r0, [r3, #0] ; Set time-slice expiration flag +; +; } +; +__tx_timer_no_time_slice: +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + MOV32 r1, _tx_timer_current_ptr ; Pickup current timer pointer address + LDR r0, [r1, #0] ; Pickup current timer + LDR r2, [r0, #0] ; Pickup timer list entry + CBZ r2, __tx_timer_no_timer ; Is there anything in the list? + ; No, just increment the timer +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + MOV32 r3, _tx_timer_expired ; Pickup expiration flag address + MOV r2, #1 ; Build expired value + STR r2, [r3, #0] ; Set expired flag + B __tx_timer_done ; Finished timer processing +; +; } +; else +; { +__tx_timer_no_timer: +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ADD r0, r0, #4 ; Move to next timer +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + MOV32 r3, _tx_timer_list_end ; Pickup addr of timer list end + LDR r2, [r3, #0] ; Pickup list end + CMP r0, r2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, skip wrap-around logic +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + MOV32 r3, _tx_timer_list_start ; Pickup addr of timer list start + LDR r0, [r3, #0] ; Set current pointer to list start +; +__tx_timer_skip_wrap: +; + STR r0, [r1, #0] ; Store new current timer pointer +; } +; +__tx_timer_done: +; +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of expired flag + LDR r2, [r3, #0] ; Pickup time-slice expired flag + CBNZ r2, __tx_something_expired ; Did a time-slice expire? + ; If non-zero, time-slice expired + MOV32 r1, _tx_timer_expired ; Pickup addr of other expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CBZ r0, __tx_timer_nothing_expired ; Did a timer expire? + ; No, nothing expired +; +__tx_something_expired: +; +; + STMDB sp!, {r0, lr} ; Save the lr register on the stack + ; and save r0 just to keep 8-byte alignment +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + MOV32 r1, _tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CBZ r0, __tx_timer_dont_activate ; Check for timer expiration + ; If not set, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BL _tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate: +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r2, [r3, #0] ; Pickup the actual flag + CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set + ; No, skip time-slice processing +; +; /* Time slice interrupted thread. */ +; _tx_thread_time_slice(); + + BL _tx_thread_time_slice ; Call time-slice processing + MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag + LDR r1, [r0] ; Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice ; Yes, skip the PendSV logic + MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup the current thread pointer + MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address + LDR r3, [r2] ; Pickup the execute thread pointer + MOV32 r0, 0xE000ED04 ; Build address of control register + MOV32 r2, 0x10000000 ; Build value for PendSV bit + CMP r1, r3 ; Are they the same? + BEQ __tx_timer_skip_time_slice ; If the same, there was no time-slice performed + STR r2, [r0] ; Not the same, issue the PendSV for preemption +__tx_timer_skip_time_slice: +; +; } +; +__tx_timer_not_ts_expiration: +; + LDMIA sp!, {r0, lr} ; Recover lr register (r0 is just there for + ; the 8-byte stack alignment +; +; } +; +__tx_timer_nothing_expired: + + DSB ; Complete all memory access + BX lr ; Return to caller +; +;} + END + diff --git a/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_alignment_adjust.c new file mode 100644 index 00000000..553949ee --- /dev/null +++ b/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -0,0 +1,400 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_power_of_two_block_size Cortex-M3/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calculates a power of two size at or immediately above*/ +/* the input size and returns it to the caller. */ +/* */ +/* INPUT */ +/* */ +/* size Block size */ +/* */ +/* OUTPUT */ +/* */ +/* calculated size Rounded up to power of two */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_power_of_two_block_size(ULONG size) +{ + /* Check for 0 size. */ + if(size == 0) + return 0; + + /* Minimum MPU block size is 32. */ + if(size <= 32) + return 32; + + /* Bit twiddling trick to round to next high power of 2 + (if original size is power of 2, it will return original size. Perfect!) */ + size--; + size |= size >> 1; + size |= size >> 2; + size |= size >> 4; + size |= size >> 8; + size |= size >> 16; + size++; + + /* Return a power of 2 size at or above the input size. */ + return(size); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_alignment_adjust Cortex-M3/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function adjusts the alignment and size of the code and data */ +/* section for a given module implementation. */ +/* */ +/* INPUT */ +/* */ +/* module_preamble Pointer to module preamble */ +/* code_size Size of the code area (updated) */ +/* code_alignment Code area alignment (updated) */ +/* data_size Size of data area (updated) */ +/* data_alignment Data area alignment (updated) */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_power_of_two_block_size Calculate power of two size */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, + ULONG *code_size, + ULONG *code_alignment, + ULONG *data_size, + ULONG *data_alignment) +{ + +ULONG local_code_size; +ULONG local_code_alignment; +ULONG local_data_size; +ULONG local_data_alignment; +ULONG code_block_size; +ULONG data_block_size; +ULONG code_size_accum; +ULONG data_size_accum; + + /* Copy the input parameters into local variables for ease of use. */ + local_code_size = *code_size; + local_code_alignment = *code_alignment; + local_data_size = *data_size; + local_data_alignment = *data_alignment; + + + /* Test for external memory enabled in preamble. */ + if(module_preamble -> txm_module_preamble_property_flags & TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS) + { + /* External/shared memory enabled. TXM_MODULE_MANAGER_CODE_MPU_ENTRIES-1 code entries will be used. */ + if (local_code_size <= (32*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 32 is best. */ + code_block_size = 32; + } + else if (local_code_size <= (64*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 64 is best. */ + code_block_size = 64; + } + else if (local_code_size <= (128*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 128 is best. */ + code_block_size = 128; + } + else if (local_code_size <= (256*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 256 is best. */ + code_block_size = 256; + } + else if (local_code_size <= (512*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 512 is best. */ + code_block_size = 512; + } + else if (local_code_size <= (1024*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 1024 is best. */ + code_block_size = 1024; + } + else if (local_code_size <= (2048*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 2048 is best. */ + code_block_size = 2048; + } + else if (local_code_size <= (4096*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 4096 is best. */ + code_block_size = 4096; + } + else if (local_code_size <= (8192*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 8192 is best. */ + code_block_size = 8192; + } + else if (local_code_size <= (16384*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 16384 is best. */ + code_block_size = 16384; + } + else if (local_code_size <= (32768*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 32768 is best. */ + code_block_size = 32768; + } + else if (local_code_size <= (65536*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 65536 is best. */ + code_block_size = 65536; + } + else if (local_code_size <= (131072*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 131072 is best. */ + code_block_size = 131072; + } + else if (local_code_size <= (262144*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 262144 is best. */ + code_block_size = 262144; + } + else if (local_code_size <= (524288*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 524288 is best. */ + code_block_size = 524288; + } + else if (local_code_size <= (1048576*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 1048576 is best. */ + code_block_size = 1048576; + } + else if (local_code_size <= (2097152*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 2097152 is best. */ + code_block_size = 2097152; + } + else if (local_code_size <= (4194304*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 4194304 is best. */ + code_block_size = 4194304; + } + else + { + /* Just set block size to 32MB just to create an allocation error! */ + code_block_size = 33554432; + } + + /* Calculate the new code size. */ + local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); + + /* Determine if the code block size is greater than the current alignment. If so, use block size + as the alignment. */ + if (code_block_size > local_code_alignment) + local_code_alignment = code_block_size; + + } + else + { + + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + local_code_alignment = _txm_power_of_two_block_size(local_code_size) >> 2; + code_size_accum = local_code_alignment + local_code_alignment; + code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); + code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); + local_code_size = code_size_accum; + } + + /* Determine the best data block size, which in our case is the minimal alignment. */ + if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + + /* Block size of 32 is best. */ + data_block_size = 32; + } + else if (local_data_size <= (64*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 64 is best. */ + data_block_size = 64; + } + else if (local_data_size <= (128*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 128 is best. */ + data_block_size = 128; + } + else if (local_data_size <= (256*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 256 is best. */ + data_block_size = 256; + } + else if (local_data_size <= (512*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 512 is best. */ + data_block_size = 512; + } + else if (local_data_size <= (1024*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 1024 is best. */ + data_block_size = 1024; + } + else if (local_data_size <= (2048*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 2048 is best. */ + data_block_size = 2048; + } + else if (local_data_size <= (4096*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 4096 is best. */ + data_block_size = 4096; + } + else if (local_data_size <= (8192*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 8192 is best. */ + data_block_size = 8192; + } + else if (local_data_size <= (16384*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 16384 is best. */ + data_block_size = 16384; + } + else if (local_data_size <= (32768*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 32768 is best. */ + data_block_size = 32768; + } + else if (local_data_size <= (65536*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 65536 is best. */ + data_block_size = 65536; + } + else if (local_data_size <= (131072*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 131072 is best. */ + data_block_size = 131072; + } + else if (local_data_size <= (262144*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 262144 is best. */ + data_block_size = 262144; + } + else if (local_data_size <= (524288*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 524288 is best. */ + data_block_size = 524288; + } + else if (local_data_size <= (1048576*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 1048576 is best. */ + data_block_size = 1048576; + } + else if (local_data_size <= (2097152*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 2097152 is best. */ + data_block_size = 2097152; + } + else if (local_data_size <= (4194304*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 4194304 is best. */ + data_block_size = 4194304; + } + else + { + + /* Just set data block size to 32MB just to create an allocation error! */ + data_block_size = 33554432; + } + + /* Calculate the new data size. */ + data_size_accum = data_block_size; + while(data_size_accum < local_data_size) + { + data_size_accum += data_block_size; + } + local_data_size = data_size_accum; + + /* Determine if the data block size is greater than the current alignment. If so, use block size + as the alignment. */ + if (data_block_size > local_data_alignment) + local_data_alignment = data_block_size; + + /* Return all the information to the caller. */ + *code_size = local_code_size; + *code_alignment = local_code_alignment; + *data_size = local_data_size; + *data_alignment = local_data_alignment; +} diff --git a/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_external_memory_enable.c new file mode 100644 index 00000000..8da1ae7b --- /dev/null +++ b/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -0,0 +1,186 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_mutex.h" +#include "tx_queue.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_external_memory_enable Cortex-M3/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates an entry in the MPU table for a shared */ +/* memory space. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* start_address Start address of memory */ +/* length Length of external memory */ +/* attributes Memory attributes (r/w) */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_mutex_get Get protection mutex */ +/* _tx_mutex_put Release protection mutex */ +/* _txm_power_of_two_block_size Round length to power of two */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, + VOID *start_address, + ULONG length, + UINT attributes) +{ + +ULONG block_size; +ULONG region_size; +ULONG subregion_bits; +ULONG address; +UINT attributes_check = 0; +TXM_MODULE_PREAMBLE *module_preamble; + + /* Determine if the module manager has not been initialized yet. */ + if (_txm_module_manager_ready != TX_TRUE) + { + + /* Module manager has not been initialized. */ + return(TX_NOT_AVAILABLE); + } + + /* Determine if the module is valid. */ + if (module_instance == TX_NULL) + { + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Get module manager protection mutex. */ + _tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER); + + /* Determine if the module instance is valid. */ + if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) + { + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Determine if the module instance is in the loaded state. */ + if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) + { + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not ready. */ + return(TX_START_ERROR); + } + + /* Check if preamble shared mem and mem protection property bits are set. */ + module_preamble = module_instance -> txm_module_instance_preamble_ptr; + if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) + != (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if bit not set. */ + return(TXM_MODULE_INVALID_PROPERTIES); + } + + /* Start address and length must adhere to Cortex-M MPU. + The address must align with the block size. */ + + block_size = _txm_power_of_two_block_size(length); + address = (ULONG) start_address; + if(address != (address & ~(block_size - 1))) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return alignment error. */ + return(TXM_MODULE_ALIGNMENT_ERROR); + } + + /* At this point, we have a valid address and block size. + Set up MPU registers. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | 0x10; + + /* Calculate the region size. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + /* Calculate the subregion bits. */ + subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); + + /* Check for valid attributes. */ + if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) + { + attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; + } + + /* Build register with attributes. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX+1] = region_size | subregion_bits | attributes_check | 0x12070001; + + /* Keep track of shared memory address and length in module instance. */ + module_instance -> txm_module_instance_shared_memory_address = address; + module_instance -> txm_module_instance_shared_memory_length = length; + + /* Recalculate MPU settings. */ + _txm_module_manager_mm_register_setup(module_instance); + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return success. */ + return(TX_SUCCESS); +} + diff --git a/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_memory_fault_handler.c new file mode 100644 index 00000000..96045103 --- /dev/null +++ b/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -0,0 +1,114 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + +/* Define a macro that can be used to allocate global variables useful to + store information about the last fault. This macro is defined in + txm_module_port.h and is usually populated in the assembly language + fault handling prior to the code calling _txm_module_manager_memory_fault_handler. */ + +TXM_MODULE_MANAGER_FAULT_INFO + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_handler Cortex-M3/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles a fault associated with a memory protected */ +/* module. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_terminate Terminate thread */ +/* */ +/* CALLED BY */ +/* */ +/* Fault handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_memory_fault_handler(VOID) +{ + +TXM_MODULE_INSTANCE *module_instance_ptr; +TX_THREAD *thread_ptr; + + + /* Pickup the current thread. */ + thread_ptr = _tx_thread_current_ptr; + + /* Initialize the module instance pointer to NULL. */ + module_instance_ptr = TX_NULL; + + /* Is there a thread? */ + if (thread_ptr) + { + + /* Pickup the module instance. */ + module_instance_ptr = thread_ptr -> tx_thread_module_instance_ptr; + + /* Terminate the current thread. */ + _tx_thread_terminate(_tx_thread_current_ptr); + } + + /* Determine if there is a user memory fault notification callback. */ + if (_txm_module_manager_fault_notify) + { + + /* Yes, call the user's notification memory fault callback. */ + (_txm_module_manager_fault_notify)(thread_ptr, module_instance_ptr); + } +} + diff --git a/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_memory_fault_notify.c new file mode 100644 index 00000000..afc2be47 --- /dev/null +++ b/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -0,0 +1,86 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the external user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_notify Cortex-M3/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application callback when/if a memory */ +/* fault occurs. The supplied thread is automatically terminated, but */ +/* any other threads in the same module may still execute. */ +/* */ +/* INPUT */ +/* */ +/* notify_function Memory fault notification */ +/* function, NULL disables. */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +{ + + /* Setup notification function. */ + _txm_module_manager_fault_notify = notify_function; + + /* Return success. */ + return(TX_SUCCESS); +} + diff --git a/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_mm_register_setup.c new file mode 100644 index 00000000..c3118c14 --- /dev/null +++ b/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -0,0 +1,683 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" +#include "txm_module_manager_util.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_region_size_get Cortex-M3/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function converts the region size in bytes to the block size */ +/* for the Cortex-M3 MPU specification. */ +/* */ +/* INPUT */ +/* */ +/* block_size Size of the block in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* MPU size specification */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_module_manager_region_size_get(ULONG block_size) +{ + +ULONG return_value; + + + /* Process relative to the input block size. */ + if (block_size == 32) + { + return_value = 0x04; + } + else if (block_size == 64) + { + return_value = 0x05; + } + else if (block_size == 128) + { + return_value = 0x06; + } + else if (block_size == 256) + { + return_value = 0x07; + } + else if (block_size == 512) + { + return_value = 0x08; + } + else if (block_size == 1024) + { + return_value = 0x09; + } + else if (block_size == 2048) + { + return_value = 0x0A; + } + else if (block_size == 4096) + { + return_value = 0x0B; + } + else if (block_size == 8192) + { + return_value = 0x0C; + } + else if (block_size == 16384) + { + return_value = 0x0D; + } + else if (block_size == 32768) + { + return_value = 0x0E; + } + else if (block_size == 65536) + { + return_value = 0x0F; + } + else if (block_size == 131072) + { + return_value = 0x10; + } + else if (block_size == 262144) + { + return_value = 0x11; + } + else if (block_size == 524288) + { + return_value = 0x12; + } + else if (block_size == 1048576) + { + return_value = 0x13; + } + else if (block_size == 2097152) + { + return_value = 0x14; + } + else + { + /* Max 4MB MPU pages for modules. */ + return_value = 0x15; + } + + return(return_value); +} + + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_calculate_srd_bits Cortex-M3/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calculates the SRD bits that need to be set to */ +/* protect "length" bytes in a block. */ +/* */ +/* INPUT */ +/* */ +/* block_size Size of the block in bytes */ +/* length Actual length in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* SRD bits to be OR'ed with region attribute register. */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) +{ + +ULONG srd_bits = 0; +UINT srd_bit_index; + + /* length is smaller than block_size, set SRD bits if block_size is 256 or more. */ + if((block_size >= 256) && (length < block_size)) + { + /* Divide block_size by 8 by shifting right 3. Result is size of subregion. */ + block_size = block_size >> 3; + + /* Set SRD index into attribute register. */ + srd_bit_index = 8; + + /* If subregion overlaps length, move to the next subregion. */ + while(length > block_size) + { + length = length - block_size; + srd_bit_index++; + } + /* Check for a portion of code remaining. */ + if(length) + { + srd_bit_index++; + } + + /* Set unused subregion bits. */ + while(srd_bit_index < 16) + { + srd_bits = srd_bits | (0x1 << srd_bit_index); + srd_bit_index++; + } + } + + return(srd_bits); +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_mm_register_setup Cortex-M3/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets up the Cortex-M3 MPU register definitions based */ +/* on the module's memory characteristics. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* */ +/* OUTPUT */ +/* */ +/* MPU specifications for module in module_instance */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_manager_region_size_get */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_thread_create */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) +{ + +ULONG code_address; +ULONG code_size; +ULONG data_address; +ULONG data_size; +ULONG start_stop_stack_size; +ULONG callback_stack_size; +ULONG block_size; +ULONG base_address_register; +ULONG base_attribute_register; +ULONG region_size; +ULONG srd_bits = 0; +UINT mpu_register = 0; +UINT mpu_table_index; +UINT i; + + + /* Setup the first region for the ThreadX trampoline code. */ + /* Set base register to user mode entry, which is guaranteed to be at least 32-byte aligned. */ + base_address_register = (ULONG) _txm_module_manager_user_mode_entry; + /* Mask address to proper range, region 0, set Valid bit. */ + base_address_register = (base_address_register & 0xFFFFFFE0) | mpu_register | 0x10; + module_instance -> txm_module_instance_mpu_registers[0] = base_address_register; + /* Attributes: read only, write-back, shareable, size 32 bytes, region enabled. */ + module_instance -> txm_module_instance_mpu_registers[1] = 0x06070009; + + /* Initialize the MPU register. */ + mpu_register = 1; + + /* Initialize the MPU table index. */ + mpu_table_index = 2; + + /* Setup values for code area. */ + code_address = (ULONG) module_instance -> txm_module_instance_code_start; + code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; + + + /* Check if shared memory was set up. If so, only 3 entries are available for + code protection. If not set up, 4 code entries are available. */ + if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] == 0) + { + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + + /* Now loop through to setup MPU protection for the code area. */ + for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES; i++) + { + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + if (i < 2) + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + } + + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ + else if (i == 2) + { + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size) >> 1; + } + + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + else + { + /* Calculate remaining space. */ + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + + /* Build the base address register. */ + base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Build the base attribute register. */ + base_attribute_register = region_size | srd_bits | 0x06070001; + + /* Setup the MPU Base Address Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; + + /* Setup the MPU Base Attribute Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; + + /* Adjust the code address. */ + code_address = code_address + block_size; + + /* Move MPU table index. */ + mpu_table_index = mpu_table_index + 2; + + /* Increment the MPU register index. */ + mpu_register++; + } + } + + /* Only 3 code entries available. */ + else + { + /* Calculate block size, one code entry taken up by shared memory. */ + block_size = _txm_power_of_two_block_size(code_size / (TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)); + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Now loop through to setup MPU protection for the code area. */ + for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) + { + + /* Build the base address register. */ + base_address_register = code_address & ~(block_size - 1) | mpu_register | 0x10; + + /* Check if SRD bits need to be set. */ + if (code_size < block_size) + { + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + + /* Build the base attribute register. */ + base_attribute_register = region_size | srd_bits | 0x06070000; + + /* Is there still some code? If so set the region enable bit. */ + if (code_size) + { + /* Set the region enable bit. */ + base_attribute_register = base_attribute_register | 0x1; + } + /* Setup the MPU Base Address Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; + + /* Setup the MPU Base Attribute Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; + + /* Adjust the code address. */ + code_address = code_address + block_size; + + /* Decrement the code size. */ + if (code_size > block_size) + code_size = code_size - block_size; + else + code_size = 0; + + /* Move MPU table index. */ + mpu_table_index = mpu_table_index + 2; + + /* Increment the MPU register index. */ + mpu_register++; + } + + /* Adjust indeces to pass over the shared memory entry. */ + /* Move MPU table index. */ + mpu_table_index = mpu_table_index + 2; + + /* Increment the MPU register index. */ + mpu_register++; + } + + /* Setup values for data area. */ + data_address = (ULONG) module_instance -> txm_module_instance_data_start; + + /* Adjust the size of the module elements to be aligned to the default alignment. We do this + so that when we partition the allocated memory, we can simply place these regions right beside + each other without having to align their pointers. Note this only works when they all have + the same alignment. */ + + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; + start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; + callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; + + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + /* Update the data size to include thread stacks. */ + data_size = data_size + start_stop_stack_size + callback_stack_size; + + + block_size = _txm_power_of_two_block_size(data_size / TXM_MODULE_MANAGER_DATA_MPU_ENTRIES); + + /* Reset SRD bitfield. */ + srd_bits = 0; + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Now loop through to setup MPU protection for the data area. */ + for (i = 0; i < TXM_MODULE_MANAGER_DATA_MPU_ENTRIES; i++) + { + + /* Build the base address register. */ + base_address_register = (data_address & ~(block_size - 1)) | mpu_register | 0x10; + + /* Check if SRD bits need to be set. */ + if (data_size < block_size) + { + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + } + + /* Build the base attribute register. */ + base_attribute_register = region_size | srd_bits | 0x13070000; + + /* Is there still some data? If so set the region enable bit. */ + if (data_size) + { + /* Set the region enable bit. */ + base_attribute_register = base_attribute_register | 0x1; + } + + /* Setup the MPU Base Address Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; + + /* Setup the MPU Base Attribute Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; + + /* Adjust the data address. */ + data_address = data_address + block_size; + + /* Decrement the data size. */ + if (data_size > block_size) + data_size = data_size - block_size; + else + data_size = 0; + + /* Move MPU table index. */ + mpu_table_index = mpu_table_index + 2; + + /* Increment the MPU register index. */ + mpu_register++; + } + +} + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_shared_memory_check_outside */ +/* Cortex-M3/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks if the specified object is outside shared */ +/* memory. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* obj_ptr Pointer to the object */ +/* obj_size Size of the object */ +/* */ +/* OUTPUT */ +/* */ +/* Whether the object is outside the shared memory region. */ +/* */ +/* CALLS */ +/* */ +/* N/A */ +/* */ +/* CALLED BY */ +/* */ +/* Module dispatch check functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UCHAR _txm_module_manager_shared_memory_check_outside(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) +{ + +ALIGN_TYPE shared_memory_start; +ALIGN_TYPE shared_memory_end; + + shared_memory_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address; + shared_memory_end = shared_memory_start + module_instance -> txm_module_instance_shared_memory_length; + + if (TXM_MODULE_MANAGER_CHECK_OUTSIDE_RANGE_EXCLUSIVE(shared_memory_start, shared_memory_end, + obj_ptr, obj_size)) + { + return(TX_TRUE); + } + return(TX_FALSE); +} + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_shared_memory_check_inside Cortex-M3/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks if the specified object is inside shared */ +/* memory. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* obj_ptr Pointer to the object */ +/* obj_size Size of the object */ +/* */ +/* OUTPUT */ +/* */ +/* Whether the object is inside the shared memory region. */ +/* */ +/* CALLS */ +/* */ +/* N/A */ +/* */ +/* CALLED BY */ +/* */ +/* Module dispatch check functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UCHAR _txm_module_manager_shared_memory_check_inside(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) +{ + +ALIGN_TYPE shared_memory_start; +ALIGN_TYPE shared_memory_end; + + shared_memory_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address; + shared_memory_end = shared_memory_start + module_instance -> txm_module_instance_shared_memory_length; + + if (TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_EXCLUSIVE(shared_memory_start, shared_memory_end, + obj_ptr, obj_size)) + { + return(TX_TRUE); + } + return(TX_FALSE); +} + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_shared_memory_check_inside_byte */ +/* Cortex-M3/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks if the specified byte is inside shared memory. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* byte_ptr Pointer to the byte */ +/* */ +/* OUTPUT */ +/* */ +/* Whether the byte is inside the shared memory region. */ +/* */ +/* CALLS */ +/* */ +/* N/A */ +/* */ +/* CALLED BY */ +/* */ +/* Module dispatch check functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UCHAR _txm_module_manager_shared_memory_check_inside_byte(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE byte_ptr) +{ + +ALIGN_TYPE shared_memory_start; +ALIGN_TYPE shared_memory_end; + + shared_memory_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address; + shared_memory_end = shared_memory_start + module_instance -> txm_module_instance_shared_memory_length; + + if (TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_EXCLUSIVE_BYTE(shared_memory_start, shared_memory_end, + byte_ptr)) + { + return(TX_TRUE); + } + return(TX_FALSE); +} diff --git a/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_thread_stack_build.s new file mode 100644 index 00000000..f3fbd758 --- /dev/null +++ b/ports_module/cortex-m3/iar/module_manager/src/txm_module_manager_thread_stack_build.s @@ -0,0 +1,153 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Module Manager */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _txm_module_manager_thread_stack_build Cortex-M3/MPU/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread */ +;/* function_ptr Pointer to shell function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +;{ + PUBLIC _txm_module_manager_thread_stack_build +_txm_module_manager_thread_stack_build: +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-M should look like the following after it is built: +; +; Stack Top: +; LR Interrupted LR (LR at time of PENDSV) +; r4 Initial value for r4 +; r5 Initial value for r5 +; r6 Initial value for r6 +; r7 Initial value for r7 +; r8 Initial value for r8 +; r9 Initial value for r9 +; r10 (sl) Initial value for r10 (sl) +; r11 Initial value for r11 +; r0 Initial value for r0 (Hardware stack starts here!!) +; r1 Initial value for r1 +; r2 Initial value for r2 +; r3 Initial value for r3 +; r12 Initial value for r12 +; lr Initial value for lr +; pc Initial value for pc +; xPSR Initial value for xPSR +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #0x7 ; Align frame + SUB r2, r2, #68 ; Subtract frame size + LDR r3, =0xFFFFFFFD ; Build initial LR value + STR r3, [r2, #0] ; Save on the stack +; +; /* Actually build the stack frame. */ +; + MOV r3, #0 ; Build initial register value + STR r3, [r2, #4] ; Store initial r4 + STR r3, [r2, #8] ; Store initial r5 + STR r3, [r2, #12] ; Store initial r6 + STR r3, [r2, #16] ; Store initial r7 + STR r3, [r2, #20] ; Store initial r8 + LDR r3, [r0, #12] ; Pickup stack starting address + STR r3, [r2, #28] ; Store initial r10 (sl) + MOV r3, #0 ; Build initial register value + STR r3, [r2, #32] ; Store initial r11 +; +; /* Hardware stack follows. / +; + STR r0, [r2, #36] ; Store initial r0, which is the thread control block + + LDR r3, [r0, #8] ; Pickup thread entry info pointer,which is in the stack pointer position of the thread control block. + ; It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this + ; function with the actual, initial stack pointer. + STR r3, [r2, #40] ; Store initial r1, which is the module entry information. + LDR r3, [r3, #8] ; Pickup data base register from the module information + STR r3, [r2, #24] ; Store initial r9 (data base register) + MOV r3, #0 ; Clear r3 again + + STR r3, [r2, #44] ; Store initial r2 + STR r3, [r2, #48] ; Store initial r3 + STR r3, [r2, #52] ; Store initial r12 + MOV r3, #0xFFFFFFFF ; Poison EXC_RETURN value + STR r3, [r2, #56] ; Store initial lr + STR r1, [r2, #60] ; Store initial pc + MOV r3, #0x01000000 ; Only T-bit need be set + STR r3, [r2, #64] ; Store initial xPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block + BX lr ; Return to caller +;} + END + diff --git a/ports_module/cortex-m4/iar/example_build/ThreadX_Modules_Cortex-M4_IAR.pdf b/ports_module/cortex-m4/iar/example_build/ThreadX_Modules_Cortex-M4_IAR.pdf new file mode 100644 index 00000000..87f96571 Binary files /dev/null and b/ports_module/cortex-m4/iar/example_build/ThreadX_Modules_Cortex-M4_IAR.pdf differ diff --git a/ports_module/cortex-m4/iar/example_build/azure_rtos.eww b/ports_module/cortex-m4/iar/example_build/azure_rtos.eww new file mode 100644 index 00000000..75799733 --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/azure_rtos.eww @@ -0,0 +1,19 @@ + + + + $WS_DIR$\sample_threadx.ewp + + + $WS_DIR$\sample_threadx_module_manager.ewp + + + $WS_DIR$\sample_threadx_module.ewp + + + $WS_DIR$\tx.ewp + + + $WS_DIR$\txm.ewp + + + diff --git a/ports_module/cortex-m4/iar/example_build/cstartup_M.s b/ports_module/cortex-m4/iar/example_build/cstartup_M.s new file mode 100644 index 00000000..75d9369b --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/cstartup_M.s @@ -0,0 +1,73 @@ + EXTERN __iar_program_start + PUBLIC __vector_table + + SECTION .text:CODE:REORDER(1) + + ;; Keep vector table even if it's not referenced + REQUIRE __vector_table + + THUMB + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec:CODE:NOROOT(2) + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD __Reset_Vector + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + + PUBWEAK NMI_Handler + PUBWEAK HardFault_Handler + PUBWEAK MemManage_Handler + PUBWEAK BusFault_Handler + PUBWEAK UsageFault_Handler + PUBWEAK SVC_Handler + PUBWEAK DebugMon_Handler + PUBWEAK PendSV_Handler + PUBWEAK SysTick_Handler + + SECTION .text:CODE:REORDER:NOROOT(1) + THUMB +__Reset_Vector: + CPSID i ; Disable interrupts + B __iar_program_start + + +NMI_Handler +HardFault_Handler +MemManage_Handler +BusFault_Handler +UsageFault_Handler +SVC_Handler +DebugMon_Handler +PendSV_Handler +SysTick_Handler +Default_Handler +__default_handler + CALL_GRAPH_ROOT __default_handler, "interrupt" + NOCALL __default_handler + B __default_handler + + END diff --git a/ports_module/cortex-m4/iar/example_build/sample_threadx.c b/ports_module/cortex-m4/iar/example_build/sample_threadx.c new file mode 100644 index 00000000..60f5a3d3 --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/sample_threadx.c @@ -0,0 +1,389 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. Please refer to Chapter 6 of the ThreadX User Guide for a complete + description of this demonstration. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define byte pool memory. */ + +UCHAR byte_pool_memory[DEMO_BYTE_POOL_SIZE]; + + +/* Define event buffer. */ + +#ifdef TX_ENABLE_EVENT_TRACE +UCHAR trace_buffer[0x10000]; +#endif + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Please refer to Chapter 6 of the ThreadX User Guide for a complete + description of this demonstration. */ + + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + +#ifdef TX_ENABLE_EVENT_TRACE + tx_trace_enable(trace_buffer, sizeof(trace_buffer), 32); +#endif + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", byte_pool_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports_module/cortex-m4/iar/example_build/sample_threadx.ewd b/ports_module/cortex-m4/iar/example_build/sample_threadx.ewd new file mode 100644 index 00000000..22c813a3 --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/sample_threadx.ewd @@ -0,0 +1,2974 @@ + + + 3 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 32 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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@@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x200; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + +define symbol FlashConfig_start__= 0x00000400; +define symbol FlashConfig_end__ = 0x0000040f; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to (FlashConfig_start__ - 1)] | [from (FlashConfig_end__+1) to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +define region FlashConfig_region = mem:[from FlashConfig_start__ to FlashConfig_end__]; + +initialize by copy { readwrite }; +initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; + +place in FlashConfig_region + {section FlashConfig}; + +place in RAM_region { last section FREE_MEM}; + diff --git a/ports_module/cortex-m4/iar/example_build/sample_threadx_module.c b/ports_module/cortex-m4/iar/example_build/sample_threadx_module.c new file mode 100644 index 00000000..939433cd --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/sample_threadx_module.c @@ -0,0 +1,428 @@ +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, + event flags group, byte pool, and block pool. */ + +/* Specify that this is a module! */ + +#define TXM_MODULE + + +/* Include the ThreadX module definitions. */ + +#include "txm_module.h" + + +/* Define constants. */ + +#define DEMO_STACK_SIZE 512 +#define DEMO_BYTE_POOL_SIZE 6000 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the pool space in the bss section of the module. ULONG is used to + get the word alignment. */ + +ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD *thread_0; +TX_THREAD *thread_1; +TX_THREAD *thread_2; +TX_THREAD *thread_3; +TX_THREAD *thread_4; +TX_THREAD *thread_5; +TX_THREAD *thread_6; +TX_THREAD *thread_7; +TX_QUEUE *queue_0; +TX_SEMAPHORE *semaphore_0; +TX_MUTEX *mutex_0; +TX_EVENT_FLAGS_GROUP *event_flags_0; +TX_BYTE_POOL *byte_pool_0; +TX_BLOCK_POOL *block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; +ULONG semaphore_0_puts; +ULONG event_0_sets; +ULONG queue_0_sends; + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + +void semaphore_0_notify(TX_SEMAPHORE *semaphore_ptr) +{ + + if (semaphore_ptr == semaphore_0) + semaphore_0_puts++; +} + + +void event_0_notify(TX_EVENT_FLAGS_GROUP *event_flag_group_ptr) +{ + + if (event_flag_group_ptr == event_flags_0) + event_0_sets++; +} + + +void queue_0_notify(TX_QUEUE *queue_ptr) +{ + + if (queue_ptr == queue_0) + queue_0_sends++; +} + + +/* Define the module start function. */ + +void demo_module_start(ULONG id) +{ + +CHAR *pointer; + + /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + the control block(s). */ + txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_2, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_3, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_4, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_5, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_6, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_7, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&queue_0, sizeof(TX_QUEUE)); + txm_module_object_allocate((void*)&semaphore_0, sizeof(TX_SEMAPHORE)); + txm_module_object_allocate((void*)&mutex_0, sizeof(TX_MUTEX)); + txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); + txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); + txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(byte_pool_0, "module byte pool 0", (UCHAR*)demo_module_pool_space, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(queue_0, "module queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + tx_queue_send_notify(queue_0, queue_0_notify); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(semaphore_0, "module semaphore 0", 1); + + tx_semaphore_put_notify(semaphore_0, semaphore_0_notify); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(event_flags_0, "module event flags 0"); + + tx_event_flags_set_notify(event_flags_0, event_0_notify); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(mutex_0, "module mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(block_pool_0, "module block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + /* Test memory handler. */ + *(ULONG *)0x64005000 = 0xCDCDCDCD; + + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + diff --git a/ports_module/cortex-m4/iar/example_build/sample_threadx_module.ewd b/ports_module/cortex-m4/iar/example_build/sample_threadx_module.ewd new file mode 100644 index 00000000..21bf663c --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/sample_threadx_module.ewd @@ -0,0 +1,2974 @@ + + + 3 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 32 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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@@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x080f0000; +define symbol __ICFEDIT_region_ROM_end__ = 0x080fffff; +define symbol __ICFEDIT_region_RAM_start__ = 0x64002800; +define symbol __ICFEDIT_region_RAM_end__ = 0x64100000; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0; +define symbol __ICFEDIT_size_svcstack__ = 0; +define symbol __ICFEDIT_size_irqstack__ = 0; +define symbol __ICFEDIT_size_fiqstack__ = 0; +define symbol __ICFEDIT_size_undstack__ = 0; +define symbol __ICFEDIT_size_abtstack__ = 0; +define symbol __ICFEDIT_size_heap__ = 0x1000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +//define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +//define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +//define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +//define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; +//define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; +//define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +//place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +define movable block ROPI with alignment = 4, fixed order +{ + ro object txm_module_preamble.o, + ro, + ro data +}; + +define movable block RWPI with alignment = 8, fixed order, static base +{ + rw, + block HEAP +}; + +place in ROM_region { block ROPI }; +place in RAM_region { block RWPI }; + diff --git a/ports_module/cortex-m4/iar/example_build/sample_threadx_module_manager.c b/ports_module/cortex-m4/iar/example_build/sample_threadx_module_manager.c new file mode 100644 index 00000000..ca18eea6 --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/sample_threadx_module_manager.c @@ -0,0 +1,109 @@ +/* Small demonstration of the ThreadX module manager. */ + +#include "tx_api.h" +#include "txm_module.h" + + +#define DEMO_STACK_SIZE 1024 + +/* Define the ThreadX object control blocks... */ + +TX_THREAD module_manager; +TXM_MODULE_INSTANCE my_module; + + +/* Define the object pool area. */ + +UCHAR object_memory[16384]; + + +/* Define the count of memory faults. */ + +ULONG memory_faults; + + +/* Define thread prototypes. */ + +void module_manager_entry(ULONG thread_input); + + +/* Define fault handler. */ + +VOID module_fault_handler(TX_THREAD *thread, TXM_MODULE_INSTANCE *module) +{ + + /* Just increment the fault counter. */ + memory_faults++; +} + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = (CHAR*)first_unused_memory; + + + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + pointer = pointer + DEMO_STACK_SIZE; +} + + + + +/* Define the test threads. */ + +void module_manager_entry(ULONG thread_input) +{ + + /* Initialize the module manager. */ + txm_module_manager_initialize((VOID *) 0x64000000, 0x1000000); + + txm_module_manager_object_pool_create(object_memory, sizeof(object_memory)); + + /* Register a fault handler. */ + txm_module_manager_memory_fault_notify(module_fault_handler); + + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ + txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0x080F0000); + + /* Enable 128 byte read/write shared memory region at 0x64005000. */ + txm_module_manager_external_memory_enable(&my_module, (void *) 0x64005000, 128, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); + + /* Start the module. */ + txm_module_manager_start(&my_module); + + /* Sleep for a while.... */ + tx_thread_sleep(1000); + + /* Stop the module. */ + txm_module_manager_stop(&my_module); + + /* Unload the module. */ + txm_module_manager_unload(&my_module); + + /* Load the module that is already there. */ + txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0x080F0000); + + /* Start the module again. */ + txm_module_manager_start(&my_module); + + /* Now just spin... */ + while(1) + { + + tx_thread_sleep(100); + } +} diff --git a/ports_module/cortex-m4/iar/example_build/sample_threadx_module_manager.ewd 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IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20020000; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define symbol __EXTRAM_start__ = 0x64000000; +define symbol __EXTRAM_end__ = 0x641FFFFF; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region EXTRAM_region = mem:[from __EXTRAM_start__ to __EXTRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; +place in EXTRAM_region { section EXT_RAM }; + +place in RAM_region { last section FREE_MEM}; diff --git a/ports_module/cortex-m4/iar/example_build/settings/azure_rtos.wsdt b/ports_module/cortex-m4/iar/example_build/settings/azure_rtos.wsdt new file mode 100644 index 00000000..cc813a03 --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/settings/azure_rtos.wsdt @@ -0,0 +1,561 @@ + + + + + sample_threadx/Debug + sample_threadx_module_manager/Debug + sample_threadx_module/Debug + tx/Debug + txm/Debug + + sample_threadx_module_manager + 1 + + + + + 21 + 2518 + 2 + + 0 + -1 + + + + 34001 + 0 + + + + + 57600 + 57601 + 57603 + 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every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%~1" == "" goto debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m4\iar\example_build\settings\sample_threadx.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m4\iar\example_build\settings\sample_threadx.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m4\iar\example_build\settings\sample_threadx.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m4\iar\example_build\settings\sample_threadx.Debug.driver.xcl" + +@echo off +:end diff --git a/ports_module/cortex-m4/iar/example_build/settings/sample_threadx.Debug.cspy.ps1 b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx.Debug.cspy.ps1 new file mode 100644 index 00000000..6549d1ee --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx.Debug.cspy.ps1 @@ -0,0 +1,31 @@ +param([String]$debugfile = ""); + +# This powershell file has been generated by the IAR Embedded Workbench +# C - SPY Debugger, as an aid to preparing a command line for running +# the cspybat command line utility using the appropriate settings. +# +# Note that this file is generated every time a new debug session +# is initialized, so you may want to move or rename the file before +# making changes. +# +# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed +# by the name of the debug file (usually an ELF / DWARF or UBROF file). +# +# Read about available command line parameters in the C - SPY Debugging +# Guide. Hints about additional command line parameters that may be +# useful in specific cases : +# --download_only Downloads a code image without starting a debug +# session afterwards. +# --silent Omits the sign - on message. +# --timeout Limits the maximum allowed execution time. +# + + +if ($debugfile -eq "") +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m4\iar\example_build\settings\sample_threadx.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m4\iar\example_build\settings\sample_threadx.Debug.driver.xcl" +} +else +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m4\iar\example_build\settings\sample_threadx.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m4\iar\example_build\settings\sample_threadx.Debug.driver.xcl" +} diff --git a/ports_module/cortex-m4/iar/example_build/settings/sample_threadx.Debug.driver.xcl b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx.Debug.driver.xcl new file mode 100644 index 00000000..22bc90ef --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx.Debug.driver.xcl @@ -0,0 +1,13 @@ +"--endian=little" + +"--cpu=Cortex-M4" + +"--fpu=None" + +"--semihosting" + +"--multicore_nr_of_cores=1" + + + + diff --git a/ports_module/cortex-m4/iar/example_build/settings/sample_threadx.Debug.general.xcl b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx.Debug.general.xcl new file mode 100644 index 00000000..c55c1832 --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx.Debug.general.xcl @@ -0,0 +1,11 @@ +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armproc.dll" + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armsim2.dll" + +"C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m4\iar\example_build\Debug\Exe\sample_threadx.out" + +--plugin="C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armbat.dll" + + + + diff --git a/ports_module/cortex-m4/iar/example_build/settings/sample_threadx.crun b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx.crun new file mode 100644 index 00000000..d71ea555 --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx.crun @@ -0,0 +1,13 @@ + + + 1 + + + * + * + * + 0 + 1 + + + diff --git a/ports_module/cortex-m4/iar/example_build/settings/sample_threadx.dbgdt b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx.dbgdt new file mode 100644 index 00000000..fd4db9fe --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx.dbgdt @@ -0,0 +1,1701 @@ + + + + + + 20 + 1350 + + + 20 + 1012 + 270 + 67 + + + + 124 + 27 + 27 + 27 + + + + 1 + 1 + 1 + + + + + + + 171 + 100 + 100 + 100 + + + + + + + TabID-19457-10101 + Debug Log + Debug-Log + + + + TabID-18934-10111 + Build + Build + + + + 0 + + + + + TabID-30205-10105 + Workspace + Workspace + + + sample_threadx + + + + + 0 + + + + + TabID-8186-10108 + Disassembly + Disassembly + + + + 0 + + + + + TabID-23179-10441 + Thread List + TX-THREAD + + + TabID-22657-10451 + Message Queues + TX-MESSAGEQUEUE + + + TabID-22134-10461 + Semaphores + TX-SEMAPHORE + + + TabID-32359-10474 + Mutexes + TX-MUTEX + + + TabID-9817-10487 + Byte Pools + TX-BYTEPOOL + + + TabID-9294-10497 + Block Pools + TX-BLOCKPOOL + + + TabID-19520-10510 + Timers + TX-TIMER + + + TabID-29745-10523 + Event Flag Groups + TX-EVENTFLAG + + + 0 + + + + + TabID-17429-10549 + Watch + Watch + + + + thread_0_counter + + + thread_1_counter + + + thread_2_counter + + + thread_3_counter + + + thread_4_counter + + + thread_5_counter + + + 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+ + + 34122 + 0A0000000A0000006E0000006E000000 + 0000000000000000150300001A000000 + 8192 + 0 + 0 + 32767 + 0 + + + 1 + + + + diff --git a/ports_module/cortex-m4/iar/example_build/settings/sample_threadx.dnx b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx.dnx new file mode 100644 index 00000000..cf1f427a --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx.dnx @@ -0,0 +1,100 @@ + + + + 0 + 1 + 90 + 1 + 1 + 1 + main + 0 + 50 + + + 0 + 1 + + + 4132951230 + + + 1 + 0 + + + _ 0 + _ 0 + + + 0 + + + 0 + 0 + 0 + + + 0 + 1 + 0 + 0 + + + 0 + + + 1 + + + _ 0 + _ "" + + + _ 0 + _ "" + _ 0 + + + 0 + 0 + 1 + 0 + 1 + 0 + + + 0 + 0 + 1 + 0 + 1 + + + 0 + + + 0 + + + 1 + _ 0 9999 0 9999 1 0 0 100 0 1 "SysTick 1 0x3C" + 1 + + + 1 + 0 + 1 + 0 + 1 + + + 0 + 0 + + + 10000000 + 0 + 1 + + diff --git a/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module.Debug.cspy.bat b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module.Debug.cspy.bat new file mode 100644 index 00000000..78bc494a --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%~1" == "" goto debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m4\iar\example_build\settings\sample_threadx_module.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m4\iar\example_build\settings\sample_threadx_module.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m4\iar\example_build\settings\sample_threadx_module.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m4\iar\example_build\settings\sample_threadx_module.Debug.driver.xcl" + +@echo off +:end diff --git a/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module.Debug.cspy.ps1 b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module.Debug.cspy.ps1 new file mode 100644 index 00000000..344d9767 --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module.Debug.cspy.ps1 @@ -0,0 +1,31 @@ +param([String]$debugfile = ""); + +# This powershell file has been generated by the IAR Embedded Workbench +# C - SPY Debugger, as an aid to preparing a command line for running +# the cspybat command line utility using the appropriate settings. +# +# Note that this file is generated every time a new debug session +# is initialized, so you may want to move or rename the file before +# making changes. +# +# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed +# by the name of the debug file (usually an ELF / DWARF or UBROF file). +# +# Read about available command line parameters in the C - SPY Debugging +# Guide. Hints about additional command line parameters that may be +# useful in specific cases : +# --download_only Downloads a code image without starting a debug +# session afterwards. +# --silent Omits the sign - on message. +# --timeout Limits the maximum allowed execution time. +# + + +if ($debugfile -eq "") +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m4\iar\example_build\settings\sample_threadx_module.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m4\iar\example_build\settings\sample_threadx_module.Debug.driver.xcl" +} +else +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m4\iar\example_build\settings\sample_threadx_module.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m4\iar\example_build\settings\sample_threadx_module.Debug.driver.xcl" +} diff --git a/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module.Debug.driver.xcl b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module.Debug.driver.xcl new file mode 100644 index 00000000..9450929f --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module.Debug.driver.xcl @@ -0,0 +1,13 @@ +"--endian=little" + +"--cpu=Cortex-M4" + +"--fpu=VFPv4_SP" + +"--semihosting" + +"--multicore_nr_of_cores=1" + + + + diff --git a/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module.Debug.general.xcl b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module.Debug.general.xcl new file mode 100644 index 00000000..c91baa58 --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module.Debug.general.xcl @@ -0,0 +1,11 @@ +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armproc.dll" + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armsim2.dll" + +"C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m4\iar\example_build\Debug\Exe\sample_threadx_module.out" + +--plugin="C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armbat.dll" + + + + diff --git a/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module.crun b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module.crun new file mode 100644 index 00000000..d71ea555 --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module.crun @@ -0,0 +1,13 @@ + + + 1 + + + * + * + * + 0 + 1 + + + diff --git a/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module.dbgdt b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module.dbgdt new file mode 100644 index 00000000..73e71f6e --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module.dbgdt @@ -0,0 +1,4 @@ + + + + diff --git a/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module.dnx b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module.dnx new file mode 100644 index 00000000..1872e83f --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module.dnx @@ -0,0 +1,58 @@ + + + + 0 + 0 + 1 + 0 + 1 + 0 + + + 0 + 0 + 1 + 0 + 1 + + + 0 + 1 + 90 + 1 + 1 + 1 + main + 0 + 50 + + + 0 + + + 0 + + + 1 + + + 1 + 0 + 1 + 0 + 1 + + + 0 + 1 + + + 0 + 0 + + + 10000000 + 0 + 1 + + diff --git a/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module_manager.Debug.cspy.bat b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module_manager.Debug.cspy.bat new file mode 100644 index 00000000..dfedb9ac --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module_manager.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%~1" == "" goto debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m4\iar\example_build\settings\sample_threadx_module_manager.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m4\iar\example_build\settings\sample_threadx_module_manager.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m4\iar\example_build\settings\sample_threadx_module_manager.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m4\iar\example_build\settings\sample_threadx_module_manager.Debug.driver.xcl" + +@echo off +:end \ No newline at end of file diff --git a/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module_manager.Debug.cspy.ps1 b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module_manager.Debug.cspy.ps1 new file mode 100644 index 00000000..2d0cf4f8 --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module_manager.Debug.cspy.ps1 @@ -0,0 +1,31 @@ +param([String]$debugfile = ""); + +# This powershell file has been generated by the IAR Embedded Workbench +# C - SPY Debugger, as an aid to preparing a command line for running +# the cspybat command line utility using the appropriate settings. +# +# Note that this file is generated every time a new debug session +# is initialized, so you may want to move or rename the file before +# making changes. +# +# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed +# by the name of the debug file (usually an ELF / DWARF or UBROF file). +# +# Read about available command line parameters in the C - SPY Debugging +# Guide. Hints about additional command line parameters that may be +# useful in specific cases : +# --download_only Downloads a code image without starting a debug +# session afterwards. +# --silent Omits the sign - on message. +# --timeout Limits the maximum allowed execution time. +# + + +if ($debugfile -eq "") +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m4\iar\example_build\settings\sample_threadx_module_manager.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m4\iar\example_build\settings\sample_threadx_module_manager.Debug.driver.xcl" +} +else +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m4\iar\example_build\settings\sample_threadx_module_manager.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m4\iar\example_build\settings\sample_threadx_module_manager.Debug.driver.xcl" +} diff --git a/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module_manager.Debug.driver.xcl b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module_manager.Debug.driver.xcl new file mode 100644 index 00000000..ac99f3bc --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module_manager.Debug.driver.xcl @@ -0,0 +1,19 @@ +"--endian=little" + +"--cpu=Cortex-M4" + +"--fpu=VFPv4_SP" + +"-p" + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\CONFIG\debugger\ST\STM32F417IG.ddf" + +"--semihosting" + +"--device=STM32F417IG" + +"--multicore_nr_of_cores=1" + + + + diff --git a/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module_manager.Debug.general.xcl b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module_manager.Debug.general.xcl new file mode 100644 index 00000000..9d9498f9 --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module_manager.Debug.general.xcl @@ -0,0 +1,13 @@ +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armproc.dll" + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armsim2.dll" + +"C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m4\iar\example_build\Debug\Exe\sample_threadx_module_manager.out" + +--plugin="C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armbat.dll" + +--device_macro="C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\config\debugger\ST\STM32F4xx.dmac" + + + + diff --git a/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module_manager.crun b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module_manager.crun new file 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+ + + 34050 + 0A0000000A0000006E0000006E000000 + 0000000000000000150300001A000000 + 8192 + 0 + 0 + 767 + 0 + + + 1 + + + + diff --git a/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module_manager.dnx b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module_manager.dnx new file mode 100644 index 00000000..22b42d0a --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module_manager.dnx @@ -0,0 +1,104 @@ + + + + 0 + 1 + 90 + 1 + 1 + 1 + main + 0 + 50 + + + _ 0 + _ 0 + + + 2687327604 + + + 0 + 1 + + + 0 + 0 + 0 + + + 0 + 1 + + + _ 0 + _ 0 + + + 0 + + + 0 + 1 + 0 + 0 + + + 0 + + + 1 + + + _ 0 + _ "" + + + _ 0 + _ "" + _ 0 + + + 0 + 0 + 1 + 0 + 1 + 0 + + + 0 + 0 + 1 + 0 + 1 + + + 0 + + + 0 + + + 1 + _ 0 10000 0 10000 1 0 0 100 0 1 "SysTick 1 0x3C" + 1 + + + 1 + 0 + 1 + 0 + 1 + + + 0 + 0 + + + 10000000 + 0 + 1 + + diff --git a/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module_manager.reggroups b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module_manager.reggroups new file mode 100644 index 00000000..5f282702 --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/settings/sample_threadx_module_manager.reggroups @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/ports_module/cortex-m4/iar/example_build/settings/tx.Debug.cspy.bat b/ports_module/cortex-m4/iar/example_build/settings/tx.Debug.cspy.bat new file mode 100644 index 00000000..c4707b78 --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/settings/tx.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%~1" == "" goto debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" + +@echo off +:end diff --git a/ports_module/cortex-m4/iar/example_build/settings/tx.Debug.cspy.ps1 b/ports_module/cortex-m4/iar/example_build/settings/tx.Debug.cspy.ps1 new file mode 100644 index 00000000..1c1ba13b --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/settings/tx.Debug.cspy.ps1 @@ -0,0 +1,31 @@ +param([String]$debugfile = ""); + +# This powershell file has been generated by the IAR Embedded Workbench +# C - SPY Debugger, as an aid to preparing a command line for running +# the cspybat command line utility using the appropriate settings. +# +# Note that this file is generated every time a new debug session +# is initialized, so you may want to move or rename the file before +# making changes. +# +# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed +# by the name of the debug file (usually an ELF / DWARF or UBROF file). +# +# Read about available command line parameters in the C - SPY Debugging +# Guide. Hints about additional command line parameters that may be +# useful in specific cases : +# --download_only Downloads a code image without starting a debug +# session afterwards. +# --silent Omits the sign - on message. +# --timeout Limits the maximum allowed execution time. +# + + +if ($debugfile -eq "") +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" +} +else +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" +} diff --git a/ports_module/cortex-m4/iar/example_build/settings/tx.Debug.driver.xcl b/ports_module/cortex-m4/iar/example_build/settings/tx.Debug.driver.xcl new file mode 100644 index 00000000..22bc90ef --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/settings/tx.Debug.driver.xcl @@ -0,0 +1,13 @@ +"--endian=little" + +"--cpu=Cortex-M4" + +"--fpu=None" + +"--semihosting" + +"--multicore_nr_of_cores=1" + + + + diff --git a/ports_module/cortex-m4/iar/example_build/settings/tx.Debug.general.xcl b/ports_module/cortex-m4/iar/example_build/settings/tx.Debug.general.xcl new file mode 100644 index 00000000..ef6d6dd5 --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/settings/tx.Debug.general.xcl @@ -0,0 +1,11 @@ +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\bin\armproc.dll" + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\bin\armsim2.dll" + +"C:\release\threadx\Debug\Exe\tx.out" + +--plugin "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\bin\armbat.dll" + + + + diff --git a/ports_module/cortex-m4/iar/example_build/settings/tx.crun b/ports_module/cortex-m4/iar/example_build/settings/tx.crun new file mode 100644 index 00000000..d71ea555 --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/settings/tx.crun @@ -0,0 +1,13 @@ + + + 1 + + + * + * + * + 0 + 1 + + + diff --git a/ports_module/cortex-m4/iar/example_build/settings/tx.dbgdt b/ports_module/cortex-m4/iar/example_build/settings/tx.dbgdt new file mode 100644 index 00000000..9e08d965 --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/settings/tx.dbgdt @@ -0,0 +1,4 @@ + + + + diff --git a/ports_module/cortex-m4/iar/example_build/settings/tx.dnx b/ports_module/cortex-m4/iar/example_build/settings/tx.dnx new file mode 100644 index 00000000..25e4c4ba --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/settings/tx.dnx @@ -0,0 +1,58 @@ + + + + 0 + 1 + 90 + 1 + 1 + 1 + main + 0 + 50 + + + 0 + 1 + + + 0 + 0 + 1 + 0 + 1 + 0 + + + 0 + 0 + 1 + 0 + 1 + + + 0 + + + 0 + + + 1 + + + 1 + 0 + 1 + 0 + 1 + + + 0 + 0 + + + 10000000 + 0 + 1 + + diff --git a/ports_module/cortex-m4/iar/example_build/settings/txm.Debug.cspy.bat b/ports_module/cortex-m4/iar/example_build/settings/txm.Debug.cspy.bat new file mode 100644 index 00000000..b592aec6 --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/settings/txm.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%~1" == "" goto debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m4\iar\example_build\settings\txm.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m4\iar\example_build\settings\txm.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m4\iar\example_build\settings\txm.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m4\iar\example_build\settings\txm.Debug.driver.xcl" + +@echo off +:end diff --git a/ports_module/cortex-m4/iar/example_build/settings/txm.Debug.cspy.ps1 b/ports_module/cortex-m4/iar/example_build/settings/txm.Debug.cspy.ps1 new file mode 100644 index 00000000..d1ce3359 --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/settings/txm.Debug.cspy.ps1 @@ -0,0 +1,31 @@ +param([String]$debugfile = ""); + +# This powershell file has been generated by the IAR Embedded Workbench +# C - SPY Debugger, as an aid to preparing a command line for running +# the cspybat command line utility using the appropriate settings. +# +# Note that this file is generated every time a new debug session +# is initialized, so you may want to move or rename the file before +# making changes. +# +# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed +# by the name of the debug file (usually an ELF / DWARF or UBROF file). +# +# Read about available command line parameters in the C - SPY Debugging +# Guide. Hints about additional command line parameters that may be +# useful in specific cases : +# --download_only Downloads a code image without starting a debug +# session afterwards. +# --silent Omits the sign - on message. +# --timeout Limits the maximum allowed execution time. +# + + +if ($debugfile -eq "") +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m4\iar\example_build\settings\txm.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m4\iar\example_build\settings\txm.Debug.driver.xcl" +} +else +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m4\iar\example_build\settings\txm.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m4\iar\example_build\settings\txm.Debug.driver.xcl" +} diff --git a/ports_module/cortex-m4/iar/example_build/settings/txm.Debug.driver.xcl b/ports_module/cortex-m4/iar/example_build/settings/txm.Debug.driver.xcl new file mode 100644 index 00000000..9450929f --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/settings/txm.Debug.driver.xcl @@ -0,0 +1,13 @@ +"--endian=little" + +"--cpu=Cortex-M4" + +"--fpu=VFPv4_SP" + +"--semihosting" + +"--multicore_nr_of_cores=1" + + + + diff --git a/ports_module/cortex-m4/iar/example_build/settings/txm.Debug.general.xcl b/ports_module/cortex-m4/iar/example_build/settings/txm.Debug.general.xcl new file mode 100644 index 00000000..065a3239 --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/settings/txm.Debug.general.xcl @@ -0,0 +1,11 @@ +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armproc.dll" + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armsim2.dll" + +"C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m4\iar\example_build\Debug\Exe\txm.out" + +--plugin="C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armbat.dll" + + + + diff --git a/ports_module/cortex-m4/iar/example_build/settings/txm.crun b/ports_module/cortex-m4/iar/example_build/settings/txm.crun new file mode 100644 index 00000000..d71ea555 --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/settings/txm.crun @@ -0,0 +1,13 @@ + + + 1 + + + * + * + * + 0 + 1 + + + diff --git a/ports_module/cortex-m4/iar/example_build/settings/txm.dbgdt b/ports_module/cortex-m4/iar/example_build/settings/txm.dbgdt new file mode 100644 index 00000000..73e71f6e --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/settings/txm.dbgdt @@ -0,0 +1,4 @@ + + + + diff --git a/ports_module/cortex-m4/iar/example_build/settings/txm.dnx b/ports_module/cortex-m4/iar/example_build/settings/txm.dnx new file mode 100644 index 00000000..25e4c4ba --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/settings/txm.dnx @@ -0,0 +1,58 @@ + + + + 0 + 1 + 90 + 1 + 1 + 1 + main + 0 + 50 + + + 0 + 1 + + + 0 + 0 + 1 + 0 + 1 + 0 + + + 0 + 0 + 1 + 0 + 1 + + + 0 + + + 0 + + + 1 + + + 1 + 0 + 1 + 0 + 1 + + + 0 + 0 + + + 10000000 + 0 + 1 + + diff --git a/ports_module/cortex-m4/iar/example_build/startup.s b/ports_module/cortex-m4/iar/example_build/startup.s new file mode 100644 index 00000000..ba46e572 --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/startup.s @@ -0,0 +1,630 @@ +;/******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f40x.s +;* Author : MCD Application Team +;* Version : V0.0.2 +;* Date : 25-July-2011 +;* Description : STM32F40x devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;*******************************************************************************/ +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + + PUBLIC __vector_table + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYP crypto + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT(2) +Reset_Handler + + CPSID i ; Disable interrupts + + ;FPU settings + LDR R0, =0xE000ED88 ; Enable CP10,CP11 + LDR R1,[R0] + ORR R1,R1,#(0xF << 20) + STR R1,[R0] + + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT(2) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT(2) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT(2) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT(2) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT(2) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT(2) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT(2) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT(2) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT(2) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT(2) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:NOROOT(2) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT(2) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT(2) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT(2) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT(2) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT(2) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT(2) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT(2) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT(2) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT(2) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:NOROOT(2) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT(2) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT(2) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT(2) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT(2) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT(2) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:NOROOT(2) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT(2) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT(2) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK FSMC_IRQHandler + SECTION .text:CODE:NOROOT(2) +FSMC_IRQHandler + B FSMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:NOROOT(2) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT(2) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT(2) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT(2) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:NOROOT(2) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK ETH_IRQHandler + SECTION .text:CODE:NOROOT(2) +ETH_IRQHandler + B ETH_IRQHandler + + PUBWEAK ETH_WKUP_IRQHandler + SECTION .text:CODE:NOROOT(2) +ETH_WKUP_IRQHandler + B ETH_WKUP_IRQHandler + + PUBWEAK CAN2_TX_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN2_TX_IRQHandler + B CAN2_TX_IRQHandler + + PUBWEAK CAN2_RX0_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN2_RX0_IRQHandler + B CAN2_RX0_IRQHandler + + PUBWEAK CAN2_RX1_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN2_RX1_IRQHandler + B CAN2_RX1_IRQHandler + + PUBWEAK CAN2_SCE_IRQHandler + SECTION .text:CODE:NOROOT(2) +CAN2_SCE_IRQHandler + B CAN2_SCE_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:NOROOT(2) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:NOROOT(2) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT(2) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_HS_EP1_OUT_IRQHandler + B OTG_HS_EP1_OUT_IRQHandler + + PUBWEAK OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_HS_EP1_IN_IRQHandler + B OTG_HS_EP1_IN_IRQHandler + + PUBWEAK OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_HS_WKUP_IRQHandler + B OTG_HS_WKUP_IRQHandler + + PUBWEAK OTG_HS_IRQHandler + SECTION .text:CODE:NOROOT(2) +OTG_HS_IRQHandler + B OTG_HS_IRQHandler + + PUBWEAK DCMI_IRQHandler + SECTION .text:CODE:NOROOT(2) +DCMI_IRQHandler + B DCMI_IRQHandler + + PUBWEAK CRYP_IRQHandler + SECTION .text:CODE:NOROOT(2) +CRYP_IRQHandler + B CRYP_IRQHandler + + PUBWEAK HASH_RNG_IRQHandler + SECTION .text:CODE:NOROOT(2) +HASH_RNG_IRQHandler + B HASH_RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:NOROOT(2) +FPU_IRQHandler + B FPU_IRQHandler + + END +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/ports_module/cortex-m4/iar/example_build/tx.ewd b/ports_module/cortex-m4/iar/example_build/tx.ewd new file mode 100644 index 00000000..df7edfb3 --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/tx.ewd @@ -0,0 +1,2974 @@ + + + 3 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 32 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 2 + 1 + 1 + + + + + + + + + + NULINK_ID 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$PROJ_DIR$\..\..\..\..\common\inc\tx_user_sample.h + + + $PROJ_DIR$\..\..\..\..\common_modules\module_common\inc\txm_module.h + + + $PROJ_DIR$\..\..\..\..\common_modules\module_manager\inc\txm_module_manager_dispatch.h + + + $PROJ_DIR$\..\..\..\..\common_modules\module_manager\inc\txm_module_manager_util.h + + + $PROJ_DIR$\..\module_common\inc\txm_module_port.h + + + $PROJ_DIR$\..\..\..\..\common_modules\module_common\inc\txm_module_user.h + + + + src + + $PROJ_DIR$\..\..\..\..\common\src\tx_block_allocate.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_cleanup.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_initialize.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_performance_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_performance_system_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_block_pool_prioritize.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_block_release.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_allocate.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_cleanup.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_create.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_delete.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_initialize.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_performance_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_performance_system_info_get.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_prioritize.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_pool_search.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_byte_release.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_cleanup.c + + + $PROJ_DIR$\..\..\..\..\common\src\tx_event_flags_create.c + + + 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/dev/null +++ b/ports_module/cortex-m4/iar/example_build/tx_initialize_low_level.s @@ -0,0 +1,176 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_initialize.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_initialize_unused_memory + EXTERN _tx_timer_interrupt + EXTERN __vector_table + EXTERN _tx_execution_isr_enter + EXTERN _tx_execution_isr_exit +; +; +SYSTEM_CLOCK EQU 25000000 +SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1) + + RSEG FREE_MEM:DATA + PUBLIC __tx_free_memory_start +__tx_free_memory_start + DS32 4 +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-M4/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + PUBLIC _tx_initialize_low_level +_tx_initialize_low_level: +; +; /* Ensure that interrupts are disabled. */ +; + CPSID i ; Disable interrupts +; +; +; /* Set base of available memory to end of non-initialised RAM area. */ +; + LDR r0, =__tx_free_memory_start ; Get end of non-initialized RAM area + LDR r2, =_tx_initialize_unused_memory ; Build address of unused memory pointer + STR r0, [r2, #0] ; Save first free memory address +; +; /* Enable the cycle count register. */ +; + LDR r0, =0xE0001000 ; Build address of DWT register + LDR r1, [r0] ; Pickup the current value + ORR r1, r1, #1 ; Set the CYCCNTENA bit + STR r1, [r0] ; Enable the cycle count register +; +; /* Setup Vector Table Offset Register. */ +; + MOV r0, #0xE000E000 ; Build address of NVIC registers + LDR r1, =__vector_table ; Pickup address of vector table + STR r1, [r0, #0xD08] ; Set vector table address +; +; /* Set system stack pointer from vector value. */ +; + LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer + LDR r1, =__vector_table ; Pickup address of vector table + LDR r1, [r1] ; Pickup reset stack pointer + STR r1, [r0] ; Save system stack pointer +; +; /* Configure SysTick. */ +; + MOV r0, #0xE000E000 ; Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] ; Setup SysTick Reload Value + MOV r1, #0x7 ; Build SysTick Control Enable Value + STR r1, [r0, #0x10] ; Setup SysTick Control +; +; /* Configure handler priorities. */ +; + LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] ; Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] ; Setup System Handlers 8-11 Priority Registers + ; Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] ; Setup System Handlers 12-15 Priority Registers + ; Note: PnSV must be lowest priority, which is 0xFF +; +; /* Return to caller. */ +; + BX lr +;} +; + PUBLIC SysTick_Handler + PUBLIC __tx_SysTickHandler +__tx_SysTickHandler: +SysTick_Handler: +; +; VOID SysTick_Handler(VOID) +; { +; + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter ; Call the ISR enter function +#endif + BL _tx_timer_interrupt +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit ; Call the ISR exit function +#endif + POP {r0, lr} + BX LR +; } + END + diff --git a/ports_module/cortex-m4/iar/example_build/txm.ewd b/ports_module/cortex-m4/iar/example_build/txm.ewd new file mode 100644 index 00000000..21bf663c --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/txm.ewd @@ -0,0 +1,2974 @@ + + + 3 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 32 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_trace_event_unfilter.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_trace_interrupt_control.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_trace_isr_enter_insert.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_trace_isr_exit_insert.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_trace_user_event_insert.c + + + diff --git a/ports_module/cortex-m4/iar/example_build/txm_module_preamble.s b/ports_module/cortex-m4/iar/example_build/txm_module_preamble.s new file mode 100644 index 00000000..81f6b250 --- /dev/null +++ b/ports_module/cortex-m4/iar/example_build/txm_module_preamble.s @@ -0,0 +1,70 @@ + SECTION .text:CODE + + AAPCS INTERWORK, ROPI, RWPI_COMPATIBLE, VFP_COMPATIBLE + PRESERVE8 + + /* Define public symbols. */ + + PUBLIC __txm_module_preamble + + + /* Define application-specific start/stop entry points for the module. */ + + EXTERN demo_module_start + + + /* Define common external refrences. */ + + EXTERN _txm_module_thread_shell_entry + EXTERN _txm_module_callback_request_thread_entry + EXTERN ROPI$$Length + EXTERN RWPI$$Length + + DATA +__txm_module_preamble: + DC32 0x4D4F4455 ; Module ID + DC32 0x5 ; Module Major Version + DC32 0x6 ; Module Minor Version + DC32 32 ; Module Preamble Size in 32-bit words + DC32 0x12345678 ; Module ID (application defined) + DC32 0x00000007 ; Module Properties where: + ; Bits 31-24: Compiler ID + ; 0 -> IAR + ; 1 -> RVDS + ; 2 -> GNU + ; Bit 0: 0 -> Privileged mode execution + ; 1 -> User mode execution + ; Bit 1: 0 -> No MPU protection + ; 1 -> MPU protection (must have user mode selected) + ; Bit 2: 0 -> Disable shared/external memory access + ; 1 -> Enable shared/external memory access + DC32 _txm_module_thread_shell_entry - . - 0 ; Module Shell Entry Point + DC32 demo_module_start - . - 0 ; Module Start Thread Entry Point + DC32 0 ; Module Stop Thread Entry Point + DC32 1 ; Module Start/Stop Thread Priority + DC32 1022 ; Module Start/Stop Thread Stack Size + DC32 _txm_module_callback_request_thread_entry - . - 0 ; Module Callback Thread Entry + DC32 1 ; Module Callback Thread Priority + DC32 1022 ; Module Callback Thread Stack Size + DC32 ROPI$$Length ; Module Code Size + DC32 RWPI$$Length ; Module Data Size + DC32 0 ; Reserved 0 + DC32 0 ; Reserved 1 + DC32 0 ; Reserved 2 + DC32 0 ; Reserved 3 + DC32 0 ; Reserved 4 + DC32 0 ; Reserved 5 + DC32 0 ; Reserved 6 + DC32 0 ; Reserved 7 + DC32 0 ; Reserved 8 + DC32 0 ; Reserved 9 + DC32 0 ; Reserved 10 + DC32 0 ; Reserved 11 + DC32 0 ; Reserved 12 + DC32 0 ; Reserved 13 + DC32 0 ; Reserved 14 + DC32 0 ; Reserved 15 + + END + + diff --git a/ports_module/cortex-m4/iar/inc/tx_port.h b/ports_module/cortex-m4/iar/inc/tx_port.h new file mode 100644 index 00000000..b5f4e221 --- /dev/null +++ b/ports_module/cortex-m4/iar/inc/tx_port.h @@ -0,0 +1,522 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-M4/IAR */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include +#include +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX Cortex-M3 port. */ + +#define TX_INT_DISABLE 1 /* Disable interrupts */ +#define TX_INT_ENABLE 0 /* Enable interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) +#endif +#else +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif + +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; \ + VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; +#endif +#ifndef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#define TX_THREAD_EXTENSION_3 +#else +#define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ + unsigned long long tx_thread_execution_time_last_start; +#endif + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#if (__VER__ < 8000000) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); +#else +void *_tx_iar_create_per_thread_tls_area(void); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); +void __iar_Initlocks(void); + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#endif +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + + +#ifdef __ARMVFP__ + +#ifdef TX_MISRA_ENABLE + +ULONG _tx_misra_control_get(void); +void _tx_misra_control_set(ULONG value); +ULONG _tx_misra_fpccr_get(void); +void _tx_misra_vfp_touch(void); + +#endif + +/* A completed thread falls into _thread_shell_entry and we can simply deactivate the FPU via CONTROL.FPCA + in order to ensure no lazy stacking will occur. */ + +#ifndef TX_MISRA_ENABLE + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_CONTROL(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_CONTROL(_tx_vfp_state); \ + } +#else + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } + +#endif + +/* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. + If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + the lazy FPU save, then restore the CONTROL.FPCA state. */ + +#ifndef TX_MISRA_ENABLE + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_CONTROL(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_CONTROL(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = *((ULONG *) 0xE000EF34); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_CONTROL(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + __asm volatile ("vmov.f32 s0, s0"); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = __get_CONTROL(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_CONTROL(_tx_vfp_state); \ + } \ + } \ + } \ + } +#else + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = _tx_misra_fpccr_get(); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + _tx_misra_vfp_touch(); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + } \ + } \ + } +#endif + +#else + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + +#endif + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define the get system state macro. */ + +#ifndef TX_THREAD_GET_SYSTEM_STATE +#ifndef TX_MISRA_ENABLE +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | __get_IPSR()) +#else +ULONG _tx_misra_ipsr_get(VOID); +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get()) +#endif +#endif + + +/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value + indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h + for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always + zero after initialization for Cortex-M ports. */ + +#ifndef TX_THREAD_SYSTEM_RETURN_CHECK +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#endif + + +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to + prevent early scheduling on Cortex-M parts. */ + +#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT)__CLZ(__RBIT((m))); + +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifdef TX_DISABLE_INLINE + +UINT _tx_thread_interrupt_disable(VOID); +VOID _tx_thread_interrupt_restore(UINT previous_posture); + +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); + +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA __istate_t interrupt_save; +#define TX_DISABLE {interrupt_save = __get_interrupt_state();__disable_interrupt();}; +#define TX_RESTORE {__set_interrupt_state(interrupt_save);}; + +#define _tx_thread_system_return _tx_thread_system_return_inline + +static void _tx_thread_system_return_inline(void) +{ +__istate_t interrupt_save; + + /* Set PendSV to invoke ThreadX scheduler. */ + *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + if (__get_IPSR() == 0) + { + interrupt_save = __get_interrupt_state(); + __enable_interrupt(); + __set_interrupt_state(interrupt_save); + } +} + +#endif + + +/* Define FPU extension for the Cortex-M4. Each is assumed to be called in the context of the executing + thread. These are no longer needed, but are preserved for backward compatibility only. */ + +void tx_thread_fpu_enable(void); +void tx_thread_fpu_disable(void); + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/IAR Version 6.0.1 *"; +#else +#ifdef TX_MISRA_ENABLE +extern CHAR _tx_version_id[100]; +#else +extern CHAR _tx_version_id[]; +#endif +#endif + + +#endif + + + diff --git a/ports_module/cortex-m4/iar/inc/txm_module_port.h b/ports_module/cortex-m4/iar/inc/txm_module_port.h new file mode 100644 index 00000000..5220e5b9 --- /dev/null +++ b/ports_module/cortex-m4/iar/inc/txm_module_port.h @@ -0,0 +1,331 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* txm_module_port.h Cortex-M4/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the basic module constants, interface structures, */ +/* and function prototypes. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TXM_MODULE_PORT_H +#define TXM_MODULE_PORT_H + +/* Determine if the optional Modules user define file should be used. */ + +#ifdef TXM_MODULE_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in txm_module_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "txm_module_user.h" +#endif + +/* It is assumed that the base ThreadX tx_port.h file has been modified to add the + following extensions to the ThreadX thread control block (this code should replace + the corresponding macro define in tx_port.h): + +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; \ + VOID *tx_thread_iar_tls_pointer; + +The following extensions must also be defined in tx_port.h: + +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); + +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); +*/ + +/* Define the kernel stack size for a module thread. */ +#ifndef TXM_MODULE_KERNEL_STACK_SIZE +#define TXM_MODULE_KERNEL_STACK_SIZE 512 +#endif + +/* Define constants specific to the tools the module can be built with for this particular modules port. */ + +#define TXM_MODULE_IAR_COMPILER 0x00000000 +#define TXM_MODULE_RVDS_COMPILER 0x01000000 +#define TXM_MODULE_GNU_COMPILER 0x02000000 +#define TXM_MODULE_COMPILER_MASK 0xFF000000 +#define TXM_MODULE_OPTIONS_MASK 0x000000FF + + +/* Define the properties for this particular module port. */ + +#define TXM_MODULE_MEMORY_PROTECTION_ENABLED + +#ifdef TXM_MODULE_MEMORY_PROTECTION_ENABLED +#define TXM_MODULE_REQUIRE_ALLOCATED_OBJECT_MEMORY +#else +#define TXM_MODULE_REQUIRE_LOCAL_OBJECT_MEMORY +#endif + +#define TXM_MODULE_USER_MODE 0x00000001 +#define TXM_MODULE_MEMORY_PROTECTION 0x00000002 +#define TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS 0x00000004 + + +/* Define the supported options for this module. */ + +#define TXM_MODULE_MANAGER_SUPPORTED_OPTIONS (TXM_MODULE_USER_MODE | TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS) +#define TXM_MODULE_MANAGER_REQUIRED_OPTIONS 0 + + +/* Define offset adjustments according to the compiler used to build the module. */ + +#define TXM_MODULE_IAR_SHELL_ADJUST 24 +#define TXM_MODULE_IAR_START_ADJUST 28 +#define TXM_MODULE_IAR_STOP_ADJUST 32 +#define TXM_MODULE_IAR_CALLBACK_ADJUST 44 + +#define TXM_MODULE_RVDS_SHELL_ADJUST 0 +#define TXM_MODULE_RVDS_START_ADJUST 0 +#define TXM_MODULE_RVDS_STOP_ADJUST 0 +#define TXM_MODULE_RVDS_CALLBACK_ADJUST 0 + +#define TXM_MODULE_GNU_SHELL_ADJUST 24 +#define TXM_MODULE_GNU_START_ADJUST 28 +#define TXM_MODULE_GNU_STOP_ADJUST 32 +#define TXM_MODULE_GNU_CALLBACK_ADJUST 44 + + +/* Define other module port-specific constants. */ + +/* Define INLINE_DECLARE to inline for IAR compiler. */ + +#define INLINE_DECLARE inline + +/* Define the number of MPU entries assigned to the code and data sections. On Cortex-M parts, there can only be 7 total + entries, since ThreadX uses one for access to the kernel dispatch function. */ + +#define TXM_MODULE_MANAGER_CODE_MPU_ENTRIES 4 +#define TXM_MODULE_MANAGER_DATA_MPU_ENTRIES 3 +#define TXM_MODULE_MANAGER_SHARED_MPU_INDEX 8 +#define TXM_MODULE_MANAGER_SHARED_MPU_REGION 4 + +/* Shared memory region attributes. */ +#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 +#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 + +/* Define the port-extensions to the module manager instance structure. */ + +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + ULONG txm_module_instance_mpu_registers[16]; \ + ULONG txm_module_instance_shared_memory_address; \ + ULONG txm_module_instance_shared_memory_length; + + +/* Define the memory fault information structure that is populated when a memory fault occurs. */ + + +typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT +{ + TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr; + VOID *txm_module_manager_memory_fault_info_code_location; + ULONG txm_module_manager_memory_fault_info_shcsr; + ULONG txm_module_manager_memory_fault_info_cfsr; + ULONG txm_module_manager_memory_fault_info_mmfar; + ULONG txm_module_manager_memory_fault_info_bfar; + ULONG txm_module_manager_memory_fault_info_control; + ULONG txm_module_manager_memory_fault_info_sp; + ULONG txm_module_manager_memory_fault_info_r0; + ULONG txm_module_manager_memory_fault_info_r1; + ULONG txm_module_manager_memory_fault_info_r2; + ULONG txm_module_manager_memory_fault_info_r3; + ULONG txm_module_manager_memory_fault_info_r4; + ULONG txm_module_manager_memory_fault_info_r5; + ULONG txm_module_manager_memory_fault_info_r6; + ULONG txm_module_manager_memory_fault_info_r7; + ULONG txm_module_manager_memory_fault_info_r8; + ULONG txm_module_manager_memory_fault_info_r9; + ULONG txm_module_manager_memory_fault_info_r10; + ULONG txm_module_manager_memory_fault_info_r11; + ULONG txm_module_manager_memory_fault_info_r12; + ULONG txm_module_manager_memory_fault_info_lr; + ULONG txm_module_manager_memory_fault_info_xpsr; +} TXM_MODULE_MANAGER_MEMORY_FAULT_INFO; + + +#define TXM_MODULE_MANAGER_FAULT_INFO \ + TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; + +/* Define the macro to check the stack available in dispatch. */ +#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE + +/* Define the macro to check the code alignment. */ + +#define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment) \ + { \ + ULONG temp; \ + temp = (ULONG) module_location; \ + temp = temp & (code_alignment - 1); \ + if (temp) \ + { \ + _tx_mutex_put(&_txm_module_manager_mutex); \ + return(TXM_MODULE_ALIGNMENT_ERROR); \ + } \ + } + + +/* Define the macro to adjust the alignment and size for code/data areas. */ + +#define TXM_MODULE_MANAGER_ALIGNMENT_ADJUST(module_preamble, code_size, code_alignment, data_size, data_alignment) _txm_module_manager_alignment_adjust(module_preamble, &code_size, &code_alignment, &data_size, &data_alignment); + + +/* Define the macro to adjust the symbols in the module preamble. */ + +#define TXM_MODULE_MANAGER_CALCULATE_ADJUSTMENTS(properties, shell_function_adjust, start_function_adjust, stop_function_adjust, callback_function_adjust) \ + if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_IAR_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_IAR_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_IAR_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_IAR_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_IAR_CALLBACK_ADJUST; \ + } \ + else if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_RVDS_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_RVDS_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_RVDS_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_RVDS_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_RVDS_CALLBACK_ADJUST; \ + } \ + else \ + { \ + shell_function_adjust = TXM_MODULE_GNU_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_GNU_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_GNU_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_GNU_CALLBACK_ADJUST; \ + } + + +/* Define the macro to populate the thread control block with module port-specific information. + Check if the module is in user mode and set up txm_module_thread_entry_info_kernel_call_dispatcher accordingly. +*/ + +#define TXM_MODULE_MANAGER_THREAD_SETUP(thread_ptr, module_instance) \ + thread_ptr -> tx_thread_module_current_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \ + thread_ptr -> tx_thread_module_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \ + if (thread_ptr -> tx_thread_module_user_mode) \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_user_mode_entry; \ + } \ + else \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_kernel_dispatch; \ + } + + +/* Define the macro to populate the module control block with module port-specific information. + If memory protection is enabled, set up the MPU registers. +*/ +#define TXM_MODULE_MANAGER_MODULE_SETUP(module_instance) \ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE) \ + { \ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) \ + { \ + _txm_module_manager_mm_register_setup(module_instance); \ + } \ + } \ + else \ + { \ + /* Do nothing. */ \ + } + +/* Define the macro to perform port-specific functions when unloading the module. */ +/* Nothing needs to be done for this port. */ +#define TXM_MODULE_MANAGER_MODULE_UNLOAD(module_instance) + + +/* Define the macro to perform port-specific functions when passing function pointer to kernel. */ +/* Determine if the pointer is within the module's code memory. */ +#define TXM_MODULE_MANAGER_CHECK_FUNCTION_POINTER(module_instance, pointer) \ + if (((pointer < sizeof(TXM_MODULE_PREAMBLE) + (ULONG) module_instance -> txm_module_instance_code_start) || \ + ((pointer+sizeof(pointer)) > (ULONG) module_instance -> txm_module_instance_code_end)) \ + && (pointer != (ULONG) TX_NULL)) \ + { \ + return(TX_PTR_ERROR); \ + } + + + +/* Define some internal prototypes to this module port. */ + +#ifndef TX_SOURCE_CODE +#define txm_module_manager_memory_fault_notify _txm_module_manager_memory_fault_notify +#endif + + +#define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES \ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment); \ +VOID _txm_module_manager_memory_fault_handler(VOID); \ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)); \ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \ +ULONG _txm_power_of_two_block_size(ULONG size); \ +ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); \ +ULONG _txm_module_manager_region_size_get(ULONG block_size); \ +UCHAR _txm_module_manager_shared_memory_check_outside(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size); \ +UCHAR _txm_module_manager_shared_memory_check_inside(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size); \ +UCHAR _txm_module_manager_shared_memory_check_inside_byte(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr); + +#define TXM_MODULE_MANAGER_VERSION_ID \ +CHAR _txm_module_manager_version_id[] = \ + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M4/MPU/IAR Version 6.0.1 *"; + +#endif + diff --git a/ports_module/cortex-m4/iar/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex-m4/iar/module_lib/src/txm_module_thread_shell_entry.c new file mode 100644 index 00000000..91fd4706 --- /dev/null +++ b/ports_module/cortex-m4/iar/module_lib/src/txm_module_thread_shell_entry.c @@ -0,0 +1,176 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#ifndef TXM_MODULE +#define TXM_MODULE +#endif + +#ifndef TX_SOURCE_CODE +#define TX_SOURCE_CODE +#endif + + +/* Include necessary system files. */ + +#include "txm_module.h" +#include "tx_thread.h" + +/* Define the global module entry pointer from the start thread of the module. */ + +TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; + + +/* Define the dispatch function pointer used in the module implementation. */ + +ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3); + + +/* Define the IAR startup code that clears the uninitialized global data and sets up the + preset global variables. */ + +extern VOID __iar_data_init3(VOID); + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_thread_shell_entry Cortex-M4/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calls the specified entry function of the thread. It */ +/* also provides a place for the thread's entry function to return. */ +/* If the thread returns, this function places the thread in a */ +/* "COMPLETED" state. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to current thread */ +/* thread_info Pointer to thread entry info */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __iar_data_init3 IAR global initialization function*/ +/* thread_entry Thread's entry function */ +/* tx_thread_resume Resume the module callback thread */ +/* _txm_module_thread_system_suspend Module thread suspension routine */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) +{ + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + VOID (*entry_exit_notify)(TX_THREAD *, UINT); +#endif + + + /* Determine if this is the start thread. If so, we must prepare the module for + execution. If not, simply skip the C startup code. */ + if (thread_info -> txm_module_thread_entry_info_start_thread) + { + + /* Initialize the IAR C environment. */ + __iar_data_init3(); + + /* Save the entry info pointer, for later use. */ + _txm_module_entry_info = thread_info; + + /* Save the kernel function dispatch address. This is used to make all resident calls from + the module. */ + _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; + + /* Ensure that we have a valid pointer. */ + while (!_txm_module_kernel_call_dispatcher) + { + + /* Loop here, if an error is present getting the dispatch function pointer! + An error here typically indicates the resident portion of _tx_thread_schedule + is not supporting the trap to obtain the function pointer. */ + } + + /* Resume the module's callback thread, already created in the manager. */ + _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); + } + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has been entered! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_ENTRY); + } +#endif + + /* Call current thread's entry function. */ + (thread_info -> txm_module_thread_entry_info_entry) (thread_info -> txm_module_thread_entry_info_parameter); + + /* Suspend thread with a "completed" state. */ + + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine again. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has exited! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_EXIT); + } +#endif + + /* Call actual thread suspension routine. */ + _txm_module_thread_system_suspend(thread_ptr); + +#ifdef TX_SAFETY_CRITICAL + + /* If we ever get here, raise safety critical exception. */ + TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0); +#endif +} + diff --git a/ports_module/cortex-m4/iar/module_manager/src/tx_iar.c b/ports_module/cortex-m4/iar/module_manager/src/tx_iar.c new file mode 100644 index 00000000..dd719370 --- /dev/null +++ b/ports_module/cortex-m4/iar/module_manager/src/tx_iar.c @@ -0,0 +1,804 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** IAR Multithreaded Library Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Define IAR library for tools prior to version 8. */ + +#if (__VER__ < 8000000) + + +/* IAR version 7 and below. */ + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_mutex.h" + + +/* This implementation requires that the following macros are defined in the + tx_port.h file and is included with the following code segments: + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. + + Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. +*/ + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT + +#include + + +#if _MULTI_THREAD + +TX_MUTEX __tx_iar_system_lock_mutexes[_MAX_LOCK]; +UINT __tx_iar_system_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_system_lock_no_mutexes; +UINT __tx_iar_system_lock_internal_errors; +UINT __tx_iar_system_lock_isr_caller; + + +/* Define the TLS access function for the IAR library. */ + +void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) +{ + +char _DLIB_TLS_MEMORY *p = 0; + + /* Is there a current thread? */ + if (_tx_thread_current_ptr) + p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; + else + p = (void _DLIB_TLS_MEMORY *) __segment_begin("__DLIB_PERTHREAD"); + p += __IAR_DLIB_PERTHREAD_SYMBOL_OFFSET(symbp); + return (void _DLIB_TLS_MEMORY *) p; +} + + +/* Define mutexes for IAR library. */ + +void __iar_system_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_LOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_system_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_system_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_system_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_system_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_system_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } +} + +void __iar_system_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } +} + + +#if _DLIB_FILE_DESCRIPTOR + +TX_MUTEX __tx_iar_file_lock_mutexes[_MAX_FLOCK]; +UINT __tx_iar_file_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_file_lock_no_mutexes; +UINT __tx_iar_file_lock_internal_errors; +UINT __tx_iar_file_lock_isr_caller; + + +void __iar_file_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_FLOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_file_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_file_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_file_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_file_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_file_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} + +void __iar_file_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} +#endif /* _DLIB_FILE_DESCRIPTOR */ + +#endif /* _MULTI_THREAD */ + +#endif /* TX_ENABLE_IAR_LIBRARY_SUPPORT */ + +#else /* IAR version 8 and above. */ + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_mutex.h" + +/* This implementation requires that the following macros are defined in the + tx_port.h file and is included with the following code segments: + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +void *_tx_iar_create_per_thread_tls_area(void); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); +void __iar_Initlocks(void); + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. + + Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. +*/ + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT + +#include + + +void * __aeabi_read_tp(); + +void* _tx_iar_create_per_thread_tls_area(); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); + +#pragma section="__iar_tls$$DATA" + +/* Define the TLS access function for the IAR library. */ +void * __aeabi_read_tp(void) +{ + void *p = 0; + TX_THREAD *thread_ptr = _tx_thread_current_ptr; + if (thread_ptr) + { + p = thread_ptr->tx_thread_iar_tls_pointer; + } + else + { + p = __section_begin("__iar_tls$$DATA"); + } + return p; +} + +/* Define the TLS creation and destruction to use malloc/free. */ + +void* _tx_iar_create_per_thread_tls_area() +{ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ + void *p = malloc(tls_size); + + /* Initialize TLS-area and run constructors for objects in TLS */ + __iar_tls_init(p); + return p; +} + +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) +{ + /* Destroy objects living in TLS */ + __call_thread_dtors(); + free(tls_ptr); +} + +#ifndef _MAX_LOCK +#define _MAX_LOCK 4 +#endif + +static TX_MUTEX __tx_iar_system_lock_mutexes[_MAX_LOCK]; +static UINT __tx_iar_system_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_system_lock_no_mutexes; +UINT __tx_iar_system_lock_internal_errors; +UINT __tx_iar_system_lock_isr_caller; + + +/* Define mutexes for IAR library. */ + +void __iar_system_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_LOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_system_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_system_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_system_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_system_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_system_Mtxlock(__iar_Rmtx *m) +{ + if (*m) + { + UINT status; + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } + } +} + +void __iar_system_Mtxunlock(__iar_Rmtx *m) +{ + if (*m) + { + UINT status; + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } + } +} + + +#if _DLIB_FILE_DESCRIPTOR + +#include /* Added to get access to FOPEN_MAX */ +#ifndef _MAX_FLOCK +#define _MAX_FLOCK FOPEN_MAX /* Define _MAX_FLOCK as the maximum number of open files */ +#endif + + +TX_MUTEX __tx_iar_file_lock_mutexes[_MAX_FLOCK]; +UINT __tx_iar_file_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_file_lock_no_mutexes; +UINT __tx_iar_file_lock_internal_errors; +UINT __tx_iar_file_lock_isr_caller; + + +void __iar_file_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_FLOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_file_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_file_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_file_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_file_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_file_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} + +void __iar_file_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} +#endif /* _DLIB_FILE_DESCRIPTOR */ + +#endif /* TX_ENABLE_IAR_LIBRARY_SUPPORT */ + +#endif /* IAR version 8 and above. */ diff --git a/ports_module/cortex-m4/iar/module_manager/src/tx_misra.s b/ports_module/cortex-m4/iar/module_manager/src/tx_misra.s new file mode 100644 index 00000000..8a13551e --- /dev/null +++ b/ports_module/cortex-m4/iar/module_manager/src/tx_misra.s @@ -0,0 +1,1074 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** ThreadX MISRA Compliance */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + #define SHT_PROGBITS 0x1 + + EXTERN __aeabi_memset + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_interrupt_disable + EXTERN _tx_thread_interrupt_restore + EXTERN _tx_thread_stack_analyze + EXTERN _tx_thread_stack_error_handler + EXTERN _tx_thread_system_state +#ifdef TX_ENABLE_EVENT_TRACE + EXTERN _tx_trace_buffer_current_ptr + EXTERN _tx_trace_buffer_end_ptr + EXTERN _tx_trace_buffer_start_ptr + EXTERN _tx_trace_event_enable_bits + EXTERN _tx_trace_full_notify_function + EXTERN _tx_trace_header_ptr +#endif + + PUBLIC _tx_misra_always_true + PUBLIC _tx_misra_block_pool_to_uchar_pointer_convert + PUBLIC _tx_misra_byte_pool_to_uchar_pointer_convert + PUBLIC _tx_misra_char_to_uchar_pointer_convert + PUBLIC _tx_misra_const_char_to_char_pointer_convert +#ifdef TX_ENABLE_EVENT_TRACE + PUBLIC _tx_misra_entry_to_uchar_pointer_convert +#endif + PUBLIC _tx_misra_indirect_void_to_uchar_pointer_convert + PUBLIC _tx_misra_memset + PUBLIC _tx_misra_message_copy +#ifdef TX_ENABLE_EVENT_TRACE + PUBLIC _tx_misra_object_to_uchar_pointer_convert +#endif + PUBLIC _tx_misra_pointer_to_ulong_convert + PUBLIC _tx_misra_status_get + PUBLIC _tx_misra_thread_stack_check +#ifdef TX_ENABLE_EVENT_TRACE + PUBLIC _tx_misra_time_stamp_get +#endif + PUBLIC _tx_misra_timer_indirect_to_void_pointer_convert + PUBLIC _tx_misra_timer_pointer_add + PUBLIC _tx_misra_timer_pointer_dif +#ifdef TX_ENABLE_EVENT_TRACE + PUBLIC _tx_misra_trace_event_insert +#endif + PUBLIC _tx_misra_uchar_pointer_add + PUBLIC _tx_misra_uchar_pointer_dif + PUBLIC _tx_misra_uchar_pointer_sub + PUBLIC _tx_misra_uchar_to_align_type_pointer_convert + PUBLIC _tx_misra_uchar_to_block_pool_pointer_convert +#ifdef TX_ENABLE_EVENT_TRACE + PUBLIC _tx_misra_uchar_to_entry_pointer_convert + PUBLIC _tx_misra_uchar_to_header_pointer_convert +#endif + PUBLIC _tx_misra_uchar_to_indirect_byte_pool_pointer_convert + PUBLIC _tx_misra_uchar_to_indirect_uchar_pointer_convert +#ifdef TX_ENABLE_EVENT_TRACE + PUBLIC _tx_misra_uchar_to_object_pointer_convert +#endif + PUBLIC _tx_misra_uchar_to_void_pointer_convert + PUBLIC _tx_misra_ulong_pointer_add + PUBLIC _tx_misra_ulong_pointer_dif + PUBLIC _tx_misra_ulong_pointer_sub + PUBLIC _tx_misra_ulong_to_pointer_convert + PUBLIC _tx_misra_ulong_to_thread_pointer_convert + PUBLIC _tx_misra_user_timer_pointer_get + PUBLIC _tx_misra_void_to_block_pool_pointer_convert + PUBLIC _tx_misra_void_to_byte_pool_pointer_convert + PUBLIC _tx_misra_void_to_event_flags_pointer_convert + PUBLIC _tx_misra_void_to_indirect_uchar_pointer_convert + PUBLIC _tx_misra_void_to_mutex_pointer_convert + PUBLIC _tx_misra_void_to_queue_pointer_convert + PUBLIC _tx_misra_void_to_semaphore_pointer_convert + PUBLIC _tx_misra_void_to_thread_pointer_convert + PUBLIC _tx_misra_void_to_uchar_pointer_convert + PUBLIC _tx_misra_void_to_ulong_pointer_convert + PUBLIC _tx_misra_ipsr_get + PUBLIC _tx_misra_control_get + PUBLIC _tx_misra_control_set +#ifdef __ARMVFP__ + PUBLIC _tx_misra_fpccr_get + PUBLIC _tx_misra_vfp_touch +#endif + PUBLIC _tx_version_id + + + SECTION `.data`:DATA:REORDER:NOROOT(2) + DATA +// 51 CHAR _tx_version_id[100] = "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX 6.0.1 MISRA C Compliant *"; +_tx_version_id: + DC8 43H, 6FH, 70H, 79H, 72H, 69H, 67H, 68H + DC8 74H, 20H, 28H, 63H, 29H, 20H, 31H, 39H + DC8 39H, 36H, 2DH, 32H, 30H, 31H, 38H, 20H + DC8 45H, 78H, 70H, 72H, 65H, 73H, 73H, 20H + DC8 4CH, 6FH, 67H, 69H, 63H, 20H, 49H, 6EH + DC8 63H, 2EH, 20H, 2AH, 20H, 54H, 68H, 72H + DC8 65H, 61H, 64H, 58H, 20H, 35H, 2EH, 38H + DC8 20H, 4DH, 49H, 53H, 52H, 41H, 20H, 43H + DC8 20H, 43H, 6FH, 6DH, 70H, 6CH, 69H, 61H + DC8 6EH, 74H, 20H, 2AH, 0 + DC8 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_memset(VOID *ptr, UINT value, UINT size); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_memset: + PUSH {R4,LR} + MOVS R4,R0 + MOVS R0,R2 + MOVS R2,R1 + MOVS R1,R0 + MOVS R0,R4 + BL __aeabi_memset + POP {R4,PC} ;; return + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UCHAR *_tx_misra_uchar_pointer_add(UCHAR *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_pointer_add: + ADD R0,R0,R1 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UCHAR *_tx_misra_uchar_pointer_sub(UCHAR *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_pointer_sub: + RSBS R1,R1,#+0 + ADD R0,R0,R1 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_uchar_pointer_dif(UCHAR *ptr1, UCHAR *ptr2); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_pointer_dif: + SUBS R0,R0,R1 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_pointer_to_ulong_convert: + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG *_tx_misra_ulong_pointer_add(ULONG *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_ulong_pointer_add: + ADD R0,R0,R1, LSL #+2 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG *_tx_misra_ulong_pointer_sub(ULONG *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_ulong_pointer_sub: + MVNS R2,#+3 + MULS R1,R2,R1 + ADD R0,R0,R1 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_ulong_pointer_dif(ULONG *ptr1, ULONG *ptr2); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_ulong_pointer_dif: + SUBS R0,R0,R1 + ASRS R0,R0,#+2 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_ulong_to_pointer_convert: + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_message_copy(ULONG **source, ULONG **destination, */ +/** UINT size); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_message_copy: + PUSH {R4,R5} + LDR R3,[R0, #+0] + LDR R4,[R1, #+0] + LDR R5,[R3, #+0] + STR R5,[R4, #+0] + ADDS R4,R4,#+4 + ADDS R3,R3,#+4 + CMP R2,#+2 + BCC.N ??_tx_misra_message_copy_0 + SUBS R2,R2,#+1 + B.N ??_tx_misra_message_copy_1 +??_tx_misra_message_copy_2: + LDR R5,[R3, #+0] + STR R5,[R4, #+0] + ADDS R4,R4,#+4 + ADDS R3,R3,#+4 + SUBS R2,R2,#+1 +??_tx_misra_message_copy_1: + CMP R2,#+0 + BNE.N ??_tx_misra_message_copy_2 +??_tx_misra_message_copy_0: + STR R3,[R0, #+0] + STR R4,[R1, #+0] + POP {R4,R5} + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_timer_pointer_dif(TX_TIMER_INTERNAL **ptr1, */ +/** TX_TIMER_INTERNAL **ptr2); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_timer_pointer_dif: + SUBS R0,R0,R1 + ASRS R0,R0,#+2 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** TX_TIMER_INTERNAL **_tx_misra_timer_pointer_add(TX_TIMER_INTERNAL */ +/** **ptr1, ULONG size); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_timer_pointer_add: + ADD R0,R0,R1, LSL #+2 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_user_timer_pointer_get(TX_TIMER_INTERNAL */ +/** *internal_timer, TX_TIMER **user_timer); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_user_timer_pointer_get: + ADDS R2,R0,#+8 + SUBS R2,R2,R0 + RSBS R2,R2,#+0 + ADD R0,R0,R2 + STR R0,[R1, #+0] + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_thread_stack_check(TX_THREAD *thread_ptr, */ +/** VOID **highest_stack); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_thread_stack_check: + PUSH {R3-R5,LR} + MOVS R4,R0 + MOVS R5,R1 + BL _tx_thread_interrupt_disable + CMP R4,#+0 + BEQ.N ??_tx_misra_thread_stack_check_0 + LDR R1,[R4, #+0] + LDR.N R2,??DataTable2 ;; 0x54485244 + CMP R1,R2 + BNE.N ??_tx_misra_thread_stack_check_0 + LDR R1,[R4, #+8] + LDR R2,[R5, #+0] + CMP R1,R2 + BCS.N ??_tx_misra_thread_stack_check_1 + LDR R1,[R4, #+8] + STR R1,[R5, #+0] +??_tx_misra_thread_stack_check_1: + LDR R1,[R4, #+12] + LDR R1,[R1, #+0] + CMP R1,#-269488145 + BNE.N ??_tx_misra_thread_stack_check_2 + LDR R1,[R4, #+16] + LDR R1,[R1, #+1] + CMP R1,#-269488145 + BNE.N ??_tx_misra_thread_stack_check_2 + LDR R1,[R5, #+0] + LDR R2,[R4, #+12] + CMP R1,R2 + BCS.N ??_tx_misra_thread_stack_check_3 +??_tx_misra_thread_stack_check_2: + BL _tx_thread_interrupt_restore + MOVS R0,R4 + BL _tx_thread_stack_error_handler + BL _tx_thread_interrupt_disable +??_tx_misra_thread_stack_check_3: + LDR R1,[R5, #+0] + LDR R1,[R1, #-4] + CMP R1,#-269488145 + BEQ.N ??_tx_misra_thread_stack_check_0 + BL _tx_thread_interrupt_restore + MOVS R0,R4 + BL _tx_thread_stack_analyze + BL _tx_thread_interrupt_disable +??_tx_misra_thread_stack_check_0: + BL _tx_thread_interrupt_restore + POP {R0,R4,R5,PC} ;; return + +#ifdef TX_ENABLE_EVENT_TRACE + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_trace_event_insert(ULONG event_id, */ +/** VOID *info_field_1, ULONG info_field_2, ULONG info_field_3, */ +/** ULONG info_field_4, ULONG filter, ULONG time_stamp); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_trace_event_insert: + PUSH {R3-R7,LR} + LDR.N R4,??DataTable2_1 + LDR R4,[R4, #+0] + CMP R4,#+0 + BEQ.N ??_tx_misra_trace_event_insert_0 + LDR.N R5,??DataTable2_2 + LDR R5,[R5, #+0] + LDR R6,[SP, #+28] + TST R5,R6 + BEQ.N ??_tx_misra_trace_event_insert_0 + LDR.N R5,??DataTable2_3 + LDR R5,[R5, #+0] + LDR.N R6,??DataTable2_4 + LDR R6,[R6, #+0] + CMP R5,#+0 + BNE.N ??_tx_misra_trace_event_insert_1 + LDR R5,[R6, #+44] + LDR R7,[R6, #+60] + LSLS R7,R7,#+16 + ORRS R7,R7,#0x80000000 + ORRS R5,R7,R5 + B.N ??_tx_misra_trace_event_insert_2 +??_tx_misra_trace_event_insert_1: + CMP R5,#-252645136 + BCS.N ??_tx_misra_trace_event_insert_3 + MOVS R5,R6 + MOVS R6,#-1 + B.N ??_tx_misra_trace_event_insert_2 +??_tx_misra_trace_event_insert_3: + MOVS R6,#-252645136 + MOVS R5,#+0 +??_tx_misra_trace_event_insert_2: + STR R6,[R4, #+0] + STR R5,[R4, #+4] + STR R0,[R4, #+8] + LDR R0,[SP, #+32] + STR R0,[R4, #+12] + STR R1,[R4, #+16] + STR R2,[R4, #+20] + STR R3,[R4, #+24] + LDR R0,[SP, #+24] + STR R0,[R4, #+28] + ADDS R4,R4,#+32 + LDR.N R0,??DataTable2_5 + LDR R0,[R0, #+0] + CMP R4,R0 + BCC.N ??_tx_misra_trace_event_insert_4 + LDR.N R0,??DataTable2_6 + LDR R4,[R0, #+0] + LDR.N R0,??DataTable2_1 + STR R4,[R0, #+0] + LDR.N R0,??DataTable2_7 + LDR R0,[R0, #+0] + STR R4,[R0, #+32] + LDR.N R0,??DataTable2_8 + LDR R0,[R0, #+0] + CMP R0,#+0 + BEQ.N ??_tx_misra_trace_event_insert_0 + LDR.N R0,??DataTable2_7 + LDR R0,[R0, #+0] + LDR.N R1,??DataTable2_8 + LDR R1,[R1, #+0] + BLX R1 + B.N ??_tx_misra_trace_event_insert_0 +??_tx_misra_trace_event_insert_4: + LDR.N R0,??DataTable2_1 + STR R4,[R0, #+0] + LDR.N R0,??DataTable2_7 + LDR R0,[R0, #+0] + STR R4,[R0, #+32] +??_tx_misra_trace_event_insert_0: + POP {R0,R4-R7,PC} ;; return + + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_1: + DC32 _tx_trace_buffer_current_ptr + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_2: + DC32 _tx_trace_event_enable_bits + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_5: + DC32 _tx_trace_buffer_end_ptr + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_6: + DC32 _tx_trace_buffer_start_ptr + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_7: + DC32 _tx_trace_header_ptr + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_8: + DC32 _tx_trace_full_notify_function + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_time_stamp_get(VOID); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_time_stamp_get: + MOVS R0,#+0 + BX LR ;; return + +#endif + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2: + DC32 0x54485244 + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_3: + DC32 _tx_thread_system_state + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_4: + DC32 _tx_thread_current_ptr + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UINT _tx_misra_always_true(void); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_always_true: + MOVS R0,#+1 + BX LR ;; return + + +/******************************************************************************************/ +/******************************************************************************************/ +/** */ +/** UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr); */ +/** */ +/******************************************************************************************/ +/******************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_indirect_void_to_uchar_pointer_convert: + BX LR ;; return + + +/***************************************************************************************/ +/***************************************************************************************/ +/** */ +/** UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); */ +/** */ +/***************************************************************************************/ +/***************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_indirect_uchar_pointer_convert: + BX LR ;; return + + +/***********************************************************************************/ +/***********************************************************************************/ +/** */ +/** UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); */ +/** */ +/***********************************************************************************/ +/***********************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_block_pool_to_uchar_pointer_convert: + BX LR ;; return + + +/******************************************************************************************/ +/******************************************************************************************/ +/** */ +/** TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); */ +/** */ +/******************************************************************************************/ +/******************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_block_pool_pointer_convert: + BX LR ;; return + + +/*****************************************************************************/ +/*****************************************************************************/ +/** */ +/** UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); */ +/** */ +/*****************************************************************************/ +/*****************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_uchar_pointer_convert: + BX LR ;; return + + +/************************************************************************************/ +/************************************************************************************/ +/** */ +/** TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); */ +/** */ +/************************************************************************************/ +/************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_block_pool_pointer_convert: + BX LR ;; return + + +/**************************************************************************************/ +/**************************************************************************************/ +/** */ +/** UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); */ +/** */ +/**************************************************************************************/ +/**************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_indirect_uchar_pointer_convert: + BX LR ;; return + + +/*****************************************************************************************/ +/*****************************************************************************************/ +/** */ +/** TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); */ +/** */ +/*****************************************************************************************/ +/*****************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_byte_pool_pointer_convert: + BX LR ;; return + + +/***************************************************************************************/ +/***************************************************************************************/ +/** */ +/** UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); */ +/** */ +/***************************************************************************************/ +/***************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_byte_pool_to_uchar_pointer_convert: + BX LR ;; return + + +/*****************************************************************************************/ +/*****************************************************************************************/ +/** */ +/** ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); */ +/** */ +/*****************************************************************************************/ +/*****************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_align_type_pointer_convert: + BX LR ;; return + + +/****************************************************************************************************/ +/****************************************************************************************************/ +/** */ +/** TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); */ +/** */ +/****************************************************************************************************/ +/****************************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_indirect_byte_pool_pointer_convert: + BX LR ;; return + + +/**************************************************************************************************/ +/**************************************************************************************************/ +/** */ +/** TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); */ +/** */ +/**************************************************************************************************/ +/**************************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_event_flags_pointer_convert: + BX LR ;; return + + +/*****************************************************************************/ +/*****************************************************************************/ +/** */ +/** ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); */ +/** */ +/*****************************************************************************/ +/*****************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_ulong_pointer_convert: + BX LR ;; return + + +/********************************************************************************/ +/********************************************************************************/ +/** */ +/** TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); */ +/** */ +/********************************************************************************/ +/********************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_mutex_pointer_convert: + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UINT _tx_misra_status_get(UINT status); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_status_get: + MOVS R0,#+0 + BX LR ;; return + + +/********************************************************************************/ +/********************************************************************************/ +/** */ +/** TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); */ +/** */ +/********************************************************************************/ +/********************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_queue_pointer_convert: + BX LR ;; return + + +/****************************************************************************************/ +/****************************************************************************************/ +/** */ +/** TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); */ +/** */ +/****************************************************************************************/ +/****************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_semaphore_pointer_convert: + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_void_pointer_convert: + BX LR ;; return + + +/*********************************************************************************/ +/*********************************************************************************/ +/** */ +/** TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); */ +/** */ +/*********************************************************************************/ +/*********************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_ulong_to_thread_pointer_convert: + BX LR ;; return + + +/***************************************************************************************************/ +/***************************************************************************************************/ +/** */ +/** VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); */ +/** */ +/***************************************************************************************************/ +/***************************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_timer_indirect_to_void_pointer_convert: + BX LR ;; return + + +/***************************************************************************************/ +/***************************************************************************************/ +/** */ +/** CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); */ +/** */ +/***************************************************************************************/ +/***************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_const_char_to_char_pointer_convert: + BX LR ;; return + + +/**********************************************************************************/ +/**********************************************************************************/ +/** */ +/** TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer); */ +/** */ +/**********************************************************************************/ +/**********************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_thread_pointer_convert: + BX LR ;; return + + +#ifdef TX_ENABLE_EVENT_TRACE + +/************************************************************************************************/ +/************************************************************************************************/ +/** */ +/** UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); */ +/** */ +/************************************************************************************************/ +/************************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_object_to_uchar_pointer_convert: + BX LR ;; return + + +/************************************************************************************************/ +/************************************************************************************************/ +/** */ +/** TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); */ +/** */ +/************************************************************************************************/ +/************************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_object_pointer_convert: + BX LR ;; return + + +/******************************************************************************************/ +/******************************************************************************************/ +/** */ +/** TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); */ +/** */ +/******************************************************************************************/ +/******************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_header_pointer_convert: + BX LR ;; return + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_entry_pointer_convert: + BX LR ;; return + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_entry_to_uchar_pointer_convert: + BX LR ;; return +#endif + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_char_to_uchar_pointer_convert: + BX LR ;; return + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** ULONG _tx_misra_ipsr_get(void); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_ipsr_get: + MRS R0, IPSR + BX LR ;; return + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** ULONG _tx_misra_control_get(void); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_control_get: + MRS R0, CONTROL + BX LR ;; return + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** void _tx_misra_control_set(ULONG value); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_control_set: + MSR CONTROL, R0 + BX LR ;; return + + +#ifdef __ARMVFP__ + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** ULONG _tx_misra_fpccr_get(void); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(2) + THUMB +_tx_misra_fpccr_get: + LDR r0, =0xE000EF34 ; Build FPCCR address + LDR r0, [r0] ; Load FPCCR value + BX LR ;; return + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** void _tx_misra_vfp_touch(void); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_vfp_touch: + vmov.f32 s0, s0 + BX LR ;; return + +#endif + + + SECTION `.iar_vfe_header`:DATA:NOALLOC:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA + DC32 0 + + END diff --git a/ports_module/cortex-m4/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex-m4/iar/module_manager/src/tx_thread_context_restore.s new file mode 100644 index 00000000..1930c870 --- /dev/null +++ b/ports_module/cortex-m4/iar/module_manager/src/tx_thread_context_restore.s @@ -0,0 +1,98 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + EXTERN _tx_execution_isr_exit +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-M4/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* [_tx_execution_isr_exit] Execution profiling ISR exit */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + PUBLIC _tx_thread_context_restore +_tx_thread_context_restore: + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + PUSH {r0, lr} ; Save return address + BL _tx_execution_isr_exit ; Call the ISR exit function + POP {r0, lr} ; Save return address +#endif +; + POP {lr} + BX lr +; +;} + END + diff --git a/ports_module/cortex-m4/iar/module_manager/src/tx_thread_context_save.s b/ports_module/cortex-m4/iar/module_manager/src/tx_thread_context_save.s new file mode 100644 index 00000000..ab563506 --- /dev/null +++ b/ports_module/cortex-m4/iar/module_manager/src/tx_thread_context_save.s @@ -0,0 +1,95 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + EXTERN _tx_execution_isr_enter +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-M4/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + PUBLIC _tx_thread_context_save +_tx_thread_context_save: +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is starting. */ +; + PUSH {r0, lr} ; Save return address + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {r0, lr} ; Recover return address +#endif +; +; /* Context is already saved - just return! */ +; + BX lr +;} + END diff --git a/ports_module/cortex-m4/iar/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex-m4/iar/module_manager/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..e04f8ceb --- /dev/null +++ b/ports_module/cortex-m4/iar/module_manager/src/tx_thread_interrupt_control.s @@ -0,0 +1,86 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-M4/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + PUBLIC _tx_thread_interrupt_control +_tx_thread_interrupt_control: +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r1, PRIMASK + MSR PRIMASK, r0 + MOV r0, r1 + BX lr +; +;} + END + diff --git a/ports_module/cortex-m4/iar/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex-m4/iar/module_manager/src/tx_thread_interrupt_disable.s new file mode 100644 index 00000000..7807d5c8 --- /dev/null +++ b/ports_module/cortex-m4/iar/module_manager/src/tx_thread_interrupt_disable.s @@ -0,0 +1,84 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-M4/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts and returning */ +;/* the previous interrupt lockout posture. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(UINT new_posture) +;{ + PUBLIC _tx_thread_interrupt_disable +_tx_thread_interrupt_disable: +; +; /* Return current interrupt lockout posture. */ +; + MRS r0, PRIMASK + CPSID i + BX lr +; +;} + END diff --git a/ports_module/cortex-m4/iar/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex-m4/iar/module_manager/src/tx_thread_interrupt_restore.s new file mode 100644 index 00000000..2159ae40 --- /dev/null +++ b/ports_module/cortex-m4/iar/module_manager/src/tx_thread_interrupt_restore.s @@ -0,0 +1,83 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-M4/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for restoring the previous */ +;/* interrupt lockout posture. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* previous_posture Previous interrupt posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_interrupt_restore(UINT new_posture) +;{ + PUBLIC _tx_thread_interrupt_restore +_tx_thread_interrupt_restore: +; +; /* Restore previous interrupt lockout posture. */ +; + MSR PRIMASK, r0 + BX lr +; +;} + END diff --git a/ports_module/cortex-m4/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex-m4/iar/module_manager/src/tx_thread_schedule.s new file mode 100644 index 00000000..dfbeed5e --- /dev/null +++ b/ports_module/cortex-m4/iar/module_manager/src/tx_thread_schedule.s @@ -0,0 +1,583 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +#define TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_execution_thread_enter + EXTERN _tx_execution_thread_exit + EXTERN _tx_thread_preempt_disable + EXTERN _txm_module_manager_memory_fault_handler + EXTERN _txm_module_manager_memory_fault_info +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-M4/MPU/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + PUBLIC _tx_thread_schedule +_tx_thread_schedule: +; +; /* This function should only ever be called on Cortex-M +; from the first schedule request. Subsequent scheduling occurs +; from the PendSV handling routines below. */ +; +; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ +; + MOV r0, #0 ; Build value for TX_FALSE + LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag + STR r0, [r2, #0] ; Clear preempt disable flag +; +; /* Clear CONTROL.FPCA bit so FPU registers aren't unnecessarily stacked. */ +; +#ifdef __ARMVFP__ + MRS r0, CONTROL ; Pickup current CONTROL register + BIC r0, r0, #4 ; Clear the FPCA bit + MSR CONTROL, r0 ; Setup new CONTROL register +#endif +; +; /* Enable memory fault registers. */ +; + LDR r0, =0xE000ED24 ; Build SHCSR address + LDR r1, =0x70000 ; Enable Usage, Bus, and MemManage faults + STR r1, [r0] ; +; +; /* Enable interrupts */ +; + CPSIE i +; +; /* Enter the scheduler for the first time. */ +; + MOV r0, #0x10000000 ; Load PENDSVSET bit + MOV r1, #0xE000E000 ; Load NVIC base + STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR + NOP ; + NOP ; + NOP ; + NOP ; +; +; /* We should never get here - ever! */ +; + BKPT 0xEF ; Setup error conditions + BX lr ; +;} +; + +; +; /* Memory Exception Handler. */ +; + PUBLIC MemManage_Handler + PUBLIC BusFault_Handler + PUBLIC UsageFault_Handler +MemManage_Handler: +BusFault_Handler: +UsageFault_Handler: +;{ + CPSID i ; Disable interrupts +; +; /* Now pickup and store all the fault related information. */ +; + LDR r12,=_txm_module_manager_memory_fault_info ; Pickup fault info struct + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup the current thread pointer + STR r1, [r12, #0] ; Save current thread pointer in fault info structure + LDR r0, =0xE000ED24 ; Build SHCSR address + LDR r1, [r0] ; Pickup SHCSR + STR r1, [r12, #8] ; Save SHCSR + LDR r0, =0xE000ED28 ; Build CFSR address + LDR r1, [r0] ; Pickup CFSR + STR r1, [r12, #12] ; Save CFSR + LDR r0, =0xE000ED34 ; Build MMFAR address + LDR r1, [r0] ; Pickup MMFAR + STR r1, [r12, #16] ; Save MMFAR + LDR r0, =0xE000ED38 ; Build BFAR address + LDR r1, [r0] ; Pickup BFAR + STR r1, [r12, #20] ; Save BFAR + MRS r0, CONTROL ; Pickup current CONTROL register + STR r0, [r12, #24] ; Save CONTROL + MRS r1, PSP ; Pickup thread stack pointer + STR r1, [r12, #28] ; Save thread stack pointer + LDR r0, [r1] ; Pickup saved r0 + STR r0, [r12, #32] ; Save r0 + LDR r0, [r1, #4] ; Pickup saved r1 + STR r0, [r12, #36] ; Save r1 + STR r2, [r12, #40] ; Save r2 + STR r3, [r12, #44] ; Save r3 + STR r4, [r12, #48] ; Save r4 + STR r5, [r12, #52] ; Save r5 + STR r6, [r12, #56] ; Save r6 + STR r7, [r12, #60] ; Save r7 + STR r8, [r12, #64] ; Save r8 + STR r9, [r12, #68] ; Save r9 + STR r10,[r12, #72] ; Save r10 + STR r11,[r12, #76] ; Save r11 + LDR r0, [r1, #16] ; Pickup saved r12 + STR r0, [r12, #80] ; Save r12 + LDR r0, [r1, #20] ; Pickup saved lr + STR r0, [r12, #84] ; Save lr + LDR r0, [r1, #24] ; Pickup instruction address at point of fault + STR r0, [r12, #4] ; Save point of fault + LDR r0, [r1, #28] ; Pickup xPSR + STR r0, [r12, #88] ; Save xPSR + + MRS r0, CONTROL ; Pickup current CONTROL register + BIC r0, r0, #1 ; Clear the UNPRIV bit + MSR CONTROL, r0 ; Setup new CONTROL register + + LDR r0, =0xE000ED28 ; Build the Memory Management Fault Status Register (MMFSR) + LDRB r1, [r0] ; Pickup the MMFSR, with the following bit definitions: + ; Bit 0 = 1 -> Instruction address violation + ; Bit 1 = 1 -> Load/store address violation + ; Bit 7 = 1 -> MMFAR is valid + STRB r1, [r0] ; Clear the MMFSR + +#ifdef __ARMVFP__ + LDR r0, =0xE000EF34 ; Cleanup FPU context: Load FPCCR address + LDR r1, [r0] ; Load FPCCR + BIC r1, r1, #1 ; Clear the lazy preservation active bit + STR r1, [r0] ; Store the value +#endif + + BL _txm_module_manager_memory_fault_handler ; Call memory manager fault handler + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + CPSID i ; Disable interrupts + BL _tx_execution_thread_exit ; Call the thread exit function + CPSIE i ; Enable interrupts +#endif + + MOV r1, #0 ; Build NULL value + LDR r0, =_tx_thread_current_ptr ; Pickup address of current thread pointer + STR r1, [r0] ; Clear current thread pointer + + ; Return from MemManage_Handler exception + LDR r0, =0xE000ED04 ; Load ICSR + LDR r1, =0x10000000 ; Set PENDSVSET bit + STR r1, [r0] ; Store ICSR + DSB ; Wait for memory access to complete + CPSIE i ; Enable interrupts + MOV lr, #0xFFFFFFFD ; Load exception return code + BX lr ; Return from exception +;} + +; +; /* Generic context PendSV handler. */ +; + PUBLIC PendSV_Handler + PUBLIC __tx_PendSVHandler +PendSV_Handler: +__tx_PendSVHandler: +; +; /* Get current thread value and new thread pointer. */ +; +__tx_ts_handler: + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + CPSID i ; Disable interrupts + PUSH {r0, lr} ; Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit ; Call the thread exit function + POP {r0, lr} ; Recover LR + CPSIE i ; Enable interrupts +#endif + MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address + MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address + MOV r3, #0 ; Build NULL value + LDR r1, [r0] ; Pickup current thread pointer +; +; /* Determine if there is a current thread to finish preserving. */ +; + CBZ r1, __tx_ts_new ; If NULL, skip preservation +; +; /* Recover PSP and preserve current thread context. */ +; + STR r3, [r0] ; Set _tx_thread_current_ptr to NULL + MRS r12, PSP ; Pickup PSP pointer (thread's stack pointer) + STMDB r12!, {r4-r11} ; Save its remaining registers +#ifdef __ARMVFP__ + TST LR, #0x10 ; Determine if the VFP extended frame is present + BNE _skip_vfp_save + VSTMDB r12!,{s16-s31} ; Yes, save additional VFP registers +_skip_vfp_save: +#endif + MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable + STMDB r12!, {LR} ; Save LR on the stack +; +; /* Determine if time-slice is active. If it isn't, skip time handling processing. */ +; + LDR r5, [r4] ; Pickup current time-slice + STR r12, [r1, #8] ; Save the thread stack pointer + CBZ r5, __tx_ts_new ; If not active, skip processing +; +; /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ +; + STR r5, [r1, #24] ; Save current time-slice +; +; /* Clear the global time-slice. */ +; + STR r3, [r4] ; Clear time-slice +; +; +; /* Executing thread is now completely preserved!!! */ +; +__tx_ts_new: +; +; /* Now we are looking for a new thread to execute! */ +; + CPSID i ; Disable interrupts + LDR r1, [r2] ; Is there another thread ready to execute? + CBZ r1, __tx_ts_wait ; No, skip to the wait processing +; +; /* Yes, another thread is ready for else, make the current thread the new thread. */ +; + STR r1, [r0] ; Setup the current thread pointer to the new thread + CPSIE i ; Enable interrupts +; +; /* Increment the thread run count. */ +; +__tx_ts_restore: + LDR r7, [r1, #4] ; Pickup the current thread run count + MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable + LDR r5, [r1, #24] ; Pickup thread's current time-slice + ADD r7, r7, #1 ; Increment the thread run count + STR r7, [r1, #4] ; Store the new run count +; +; /* Setup global time-slice with thread's current time-slice. */ +; + STR r5, [r4] ; Setup global time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + PUSH {r0, r1} ; Save r0 and r1 + BL _tx_execution_thread_enter ; Call the thread execution enter function + POP {r0, r1} ; Recover r0 and r1 +#endif +; +; /* Restore the thread context and PSP. */ +; + LDR r12, [r1, #8] ; Pickup thread's stack pointer + + MRS r5, CONTROL ; Pickup current CONTROL register + LDR r4, [r1, #0x98] ; Pickup current user mode flag + BIC r5, r5, #1 ; Clear the UNPRIV bit + ORR r4, r4, r5 ; Build new CONTROL register + MSR CONTROL, r4 ; Setup new CONTROL register + + LDR r0, =0xE000ED94 ; Build MPU control reg address + MOV r3, #0 ; Build disable value + STR r3, [r0] ; Disable MPU + LDR r0, [r1, #0x90] ; Pickup the module instance pointer + CBZ r0, skip_mpu_setup ; Is this thread owned by a module? No, skip MPU setup + LDR r1, [r0, #0x64] ; Pickup MPU register[0] + CBZ r1, skip_mpu_setup ; Is protection required for this module? No, skip MPU setup + LDR r1, =0xE000ED9C ; Build address of MPU base register + + ; Use alias registers to quickly load MPU + ADD r0, r0, #100 ; Build address of MPU register start in thread control block + LDM r0!,{r2-r9} ; Load first four MPU regions + STM r1,{r2-r9} ; Store first four MPU regions + LDM r0,{r2-r9} ; Load second four MPU regions + STM r1,{r2-r9} ; Store second four MPU regions + LDR r0, =0xE000ED94 ; Build MPU control reg address + MOV r1, #5 ; Build enable value + STR r1, [r0] ; Enable MPU +skip_mpu_setup: + LDMIA r12!, {LR} ; Pickup LR +#ifdef __ARMVFP__ + TST LR, #0x10 ; Determine if the VFP extended frame is present + BNE _skip_vfp_restore ; If not, skip VFP restore + VLDMIA r12!, {s16-s31} ; Yes, restore additional VFP registers +_skip_vfp_restore: +#endif + LDMIA r12!, {r4-r11} ; Recover thread's registers + MSR PSP, r12 ; Setup the thread's stack pointer +; +; /* Return to thread. */ +; + BX lr ; Return to thread! +; +; /* The following is the idle wait processing... in this case, no threads are ready for execution and the +; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +; are disabled to allow use of WFI for waiting for a thread to arrive. */ +; +__tx_ts_wait: + CPSID i ; Disable interrupts + LDR r1, [r2] ; Pickup the next thread to execute pointer + STR r1, [r0] ; Store it in the current pointer + CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready! +#ifdef TX_ENABLE_WFI + DSB ; Ensure no outstanding memory transactions + WFI ; Wait for interrupt + ISB ; Ensure pipeline is flushed +#endif + CPSIE i ; Enable interrupts + B __tx_ts_wait ; Loop to continue waiting +; +; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +; already in the handler! */ +; +__tx_ts_ready: + MOV r7, #0x08000000 ; Build clear PendSV value + MOV r8, #0xE000E000 ; Build base NVIC address + STR r7, [r8, #0xD04] ; Clear any PendSV +; +; /* Re-enable interrupts and restore new thread. */ +; + CPSIE i ; Enable interrupts + B __tx_ts_restore ; Restore the thread +;} + +; +; /* SVC Handler. */ +; + PUBLIC SVC_Handler + PUBLIC __tx_SVCallHandler +SVC_Handler: +__tx_SVCallHandler: +;{ + MRS r0, PSP ; Pickup the PSP stack + LDR r1, [r0, #24] ; Pickup the point of interrupt + LDRB r2, [r1, #-2] ; Pickup the SVC parameter + ; + ; Determine which SVC trap we are processing + ; + CMP r2, #1 ; Is it the entry into ThreadX? + BNE _tx_thread_user_return ; No, return to user mode + ; + ; At this point we have an SVC 1, which means we are entering the kernel from a module thread with user mode selected + ; + LDR r2, =_txm_module_priv-1 ; Subtract 1 because of THUMB mode. + CMP r1, r2 ; Did we come from user_mode_entry? + IT NE ; If no (not equal), then... + BXNE lr ; return from where we came. + + LDR r3, [r0, #20] ; This is the saved LR + LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r2, [r1] ; Pickup current thread pointer + MOV r1, #0 ; Build clear value + STR r1, [r2, #0x98] ; Clear the current user mode selection for thread + STR r3, [r2, #0xA0] ; Save the original LR in thread control block + + ; If there is memory protection, use kernel stack + LDR r0, [r2, #0x90] ; Load the module instance ptr + LDR r0, [r0, #0x0C] ; Load the module property flags + TST r0, #2 ; Check if memory protected + BEQ _tx_skip_kernel_stack_enter + + ; Switch to the module thread's kernel stack + LDR r0, [r2, #0xA8] ; Load the module kernel stack end +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r1, [r2, #0xA4] ; Load the module kernel stack start + LDR r3, [r2, #0xAC] ; Load the module kernel stack size + STR r1, [r2, #12] ; Set stack start + STR r0, [r2, #16] ; Set stack end + STR r3, [r2, #20] ; Set stack size +#endif + + MRS r3, PSP ; Pickup thread stack pointer + STR r3, [r2, #0xB0] ; Save thread stack pointer + + ; Build kernel stack by copying thread stack two registers at a time + ADD r3, r3, #32 ; start at bottom of hardware stack + LDMDB r3!,{r1-r2} ; + STMDB r0!,{r1-r2} ; + LDMDB r3!,{r1-r2} ; + STMDB r0!,{r1-r2} ; + LDMDB r3!,{r1-r2} ; + STMDB r0!,{r1-r2} ; + LDMDB r3!,{r1-r2} ; + STMDB r0!,{r1-r2} ; + + MSR PSP, r0 ; Set kernel stack pointer + +_tx_skip_kernel_stack_enter: + MRS r0, CONTROL ; Pickup current CONTROL register + BIC r0, r0, #1 ; Clear the UNPRIV bit + MSR CONTROL, r0 ; Setup new CONTROL register + BX lr ; Return to thread + +_tx_thread_user_return: + + LDR r2, =_txm_module_user_mode_exit-1 ; Subtract 1 because of THUMB mode. + CMP r1, r2 ; Did we come from user_mode_exit? + IT NE ; If no (not equal), then... + BXNE lr ; return from where we came + + LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r2, [r1] ; Pickup current thread pointer + LDR r1, [r2, #0x9C] ; Pick up user mode + STR r1, [r2, #0x98] ; Set the current user mode selection for thread + + ; If there is memory protection, use kernel stack + LDR r0, [r2, #0x90] ; Load the module instance ptr + LDR r0, [r0, #0x0C] ; Load the module property flags + TST r0, #2 ; Check if memory protected + BEQ _tx_skip_kernel_stack_exit + +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r0, [r2, #0xB4] ; Load the module thread stack start + LDR r1, [r2, #0xB8] ; Load the module thread stack end + LDR r3, [r2, #0xBC] ; Load the module thread stack size + STR r0, [r2, #12] ; Set stack start + STR r1, [r2, #16] ; Set stack end + STR r3, [r2, #20] ; Set stack size +#endif + LDR r0, [r2, #0xB0] ; Load the module thread stack pointer + MRS r3, PSP ; Pickup kernel stack pointer + + ; Copy kernel hardware stack to module thread stack. + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + SUB r0, r0, #32 ; Subtract 32 to get back to top of stack + MSR PSP, r0 ; Set thread stack pointer + + LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r2, [r1] ; Pickup current thread pointer + LDR r1, [r2, #0x9C] ; Pick up user mode + +_tx_skip_kernel_stack_exit: + MRS r0, CONTROL ; Pickup current CONTROL register + ORR r0, r0, r1 ; OR in the user mode bit + MSR CONTROL, r0 ; Setup new CONTROL register + BX lr ; Return to thread +;} + +; +; /* Kernel entry function from user mode. */ +; + EXTERN _txm_module_manager_kernel_dispatch +; + SECTION `.text`:CODE:NOROOT(5) + THUMB + ALIGNROM 5 +;VOID _txm_module_manager_user_mode_entry(VOID) +;{ + PUBLIC _txm_module_manager_user_mode_entry +_txm_module_manager_user_mode_entry: + SVC 1 ; Enter kernel +_txm_module_priv: + ; At this point, we are out of user mode. The original LR has been saved in the + ; thread control block. Simply call the kernel dispatch function. + BL _txm_module_manager_kernel_dispatch + + ; Pickup the original LR value while still in privileged mode + LDR r2, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r3, [r2] ; Pickup current thread pointer + LDR lr, [r3, #0xA0] ; Pickup saved LR from original call + + SVC 2 ; Exit kernel and return to user mode +_txm_module_user_mode_exit: + BX lr ; Return to the caller + NOP + NOP + NOP + NOP +;} + +; +#ifdef __ARMVFP__ + + PUBLIC tx_thread_fpu_enable +tx_thread_fpu_enable: +; +; /* Automatic VPF logic is supported, this function is present only for +; backward compatibility purposes and therefore simply returns. */ +; + BX LR ; Return to caller + + PUBLIC tx_thread_fpu_disable +tx_thread_fpu_disable: +; +; /* Automatic VPF logic is supported, this function is present only for +; backward compatibility purposes and therefore simply returns. */ +; + BX LR ; Return to caller + +#endif + + END diff --git a/ports_module/cortex-m4/iar/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex-m4/iar/module_manager/src/tx_thread_stack_build.s new file mode 100644 index 00000000..55a8bc5e --- /dev/null +++ b/ports_module/cortex-m4/iar/module_manager/src/tx_thread_stack_build.s @@ -0,0 +1,135 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-M4/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + PUBLIC _tx_thread_stack_build +_tx_thread_stack_build: +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-M should look like the following after it is built: +; +; Stack Top: +; LR Interrupted LR (LR at time of PENDSV) +; r4 Initial value for r4 +; r5 Initial value for r5 +; r6 Initial value for r6 +; r7 Initial value for r7 +; r8 Initial value for r8 +; r9 Initial value for r9 +; r10 Initial value for r10 +; r11 Initial value for r11 +; r0 Initial value for r0 (Hardware stack starts here!!) +; r1 Initial value for r1 +; r2 Initial value for r2 +; r3 Initial value for r3 +; r12 Initial value for r12 +; lr Initial value for lr +; pc Initial value for pc +; xPSR Initial value for xPSR +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #0x7 ; Align frame for 8-byte alignment + SUB r2, r2, #68 ; Subtract frame size + LDR r3, =0xFFFFFFFD ; Build initial LR value + STR r3, [r2, #0] ; Save on the stack +; +; /* Actually build the stack frame. */ +; + MOV r3, #0 ; Build initial register value + STR r3, [r2, #4] ; Store initial r4 + STR r3, [r2, #8] ; Store initial r5 + STR r3, [r2, #12] ; Store initial r6 + STR r3, [r2, #16] ; Store initial r7 + STR r3, [r2, #20] ; Store initial r8 + STR r3, [r2, #24] ; Store initial r9 + STR r3, [r2, #28] ; Store initial r10 + STR r3, [r2, #32] ; Store initial r11 +; +; /* Hardware stack follows. */ +; + STR r3, [r2, #36] ; Store initial r0 + STR r3, [r2, #40] ; Store initial r1 + STR r3, [r2, #44] ; Store initial r2 + STR r3, [r2, #48] ; Store initial r3 + STR r3, [r2, #52] ; Store initial r12 + MOV r3, #0xFFFFFFFF ; Poison EXC_RETURN value + STR r3, [r2, #56] ; Store initial lr + STR r1, [r2, #60] ; Store initial pc + MOV r3, #0x01000000 ; Only T-bit need be set + STR r3, [r2, #64] ; Store initial xPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block + BX lr ; Return to caller +;} + END + diff --git a/ports_module/cortex-m4/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex-m4/iar/module_manager/src/tx_thread_system_return.s new file mode 100644 index 00000000..9820752e --- /dev/null +++ b/ports_module/cortex-m4/iar/module_manager/src/tx_thread_system_return.s @@ -0,0 +1,98 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-M4/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + PUBLIC _tx_thread_system_return +_tx_thread_system_return??rA: +_tx_thread_system_return: +; +; /* Return to real scheduler via PendSV. Note that this routine is often +; replaced with in-line assembly in tx_port.h to improved performance. */ +; + MOV r0, #0x10000000 ; Load PENDSVSET bit + MOV r1, #0xE000E000 ; Load NVIC base + STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR + MRS r0, IPSR ; Pickup IPSR + CMP r0, #0 ; Is it a thread returning? + BNE _isr_context ; If ISR, skip interrupt enable + MRS r1, PRIMASK ; Thread context returning, pickup PRIMASK + CPSIE i ; Enable interrupts + MSR PRIMASK, r1 ; Restore original interrupt posture +_isr_context: + BX lr ; Return to caller +;} + END + diff --git a/ports_module/cortex-m4/iar/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex-m4/iar/module_manager/src/tx_timer_interrupt.s new file mode 100644 index 00000000..0a3c3e52 --- /dev/null +++ b/ports_module/cortex-m4/iar/module_manager/src/tx_timer_interrupt.s @@ -0,0 +1,268 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_timer.h" +;#include "tx_thread.h" +; +; +;Define Assembly language external references... +; + EXTERN _tx_timer_time_slice + EXTERN _tx_timer_system_clock + EXTERN _tx_timer_current_ptr + EXTERN _tx_timer_list_start + EXTERN _tx_timer_list_end + EXTERN _tx_timer_expired_time_slice + EXTERN _tx_timer_expired + EXTERN _tx_thread_time_slice + EXTERN _tx_timer_expiration_process + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_thread_preempt_disable +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-M4/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* expiration functions are called. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + PUBLIC _tx_timer_interrupt +_tx_timer_interrupt: +; +; /* Upon entry to this routine, it is assumed that the compiler scratch registers are available +; for use. */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + MOV32 r1, _tx_timer_system_clock ; Pickup address of system clock + LDR r0, [r1, #0] ; Pickup system clock + ADD r0, r0, #1 ; Increment system clock + STR r0, [r1, #0] ; Store new system clock +; +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice + LDR r2, [r3, #0] ; Pickup time-slice + CBZ r2, __tx_timer_no_time_slice ; Is it non-active? + ; Yes, skip time-slice processing +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; + SUB r2, r2, #1 ; Decrement the time-slice + STR r2, [r3, #0] ; Store new time-slice value +; +; /* Check for expiration. */ +; if (__tx_timer_time_slice == 0) +; + CBNZ r2, __tx_timer_no_time_slice ; Has it expired? +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup address of expired flag + MOV r0, #1 ; Build expired value + STR r0, [r3, #0] ; Set time-slice expiration flag +; +; } +; +__tx_timer_no_time_slice: +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + MOV32 r1, _tx_timer_current_ptr ; Pickup current timer pointer address + LDR r0, [r1, #0] ; Pickup current timer + LDR r2, [r0, #0] ; Pickup timer list entry + CBZ r2, __tx_timer_no_timer ; Is there anything in the list? + ; No, just increment the timer +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + MOV32 r3, _tx_timer_expired ; Pickup expiration flag address + MOV r2, #1 ; Build expired value + STR r2, [r3, #0] ; Set expired flag + B __tx_timer_done ; Finished timer processing +; +; } +; else +; { +__tx_timer_no_timer: +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ADD r0, r0, #4 ; Move to next timer +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + MOV32 r3, _tx_timer_list_end ; Pickup addr of timer list end + LDR r2, [r3, #0] ; Pickup list end + CMP r0, r2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, skip wrap-around logic +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + MOV32 r3, _tx_timer_list_start ; Pickup addr of timer list start + LDR r0, [r3, #0] ; Set current pointer to list start +; +__tx_timer_skip_wrap: +; + STR r0, [r1, #0] ; Store new current timer pointer +; } +; +__tx_timer_done: +; +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of expired flag + LDR r2, [r3, #0] ; Pickup time-slice expired flag + CBNZ r2, __tx_something_expired ; Did a time-slice expire? + ; If non-zero, time-slice expired + MOV32 r1, _tx_timer_expired ; Pickup addr of other expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CBZ r0, __tx_timer_nothing_expired ; Did a timer expire? + ; No, nothing expired +; +__tx_something_expired: +; +; + STMDB sp!, {r0, lr} ; Save the lr register on the stack + ; and save r0 just to keep 8-byte alignment +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + MOV32 r1, _tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CBZ r0, __tx_timer_dont_activate ; Check for timer expiration + ; If not set, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BL _tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate: +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r2, [r3, #0] ; Pickup the actual flag + CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set + ; No, skip time-slice processing +; +; /* Time slice interrupted thread. */ +; _tx_thread_time_slice(); + + BL _tx_thread_time_slice ; Call time-slice processing + MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag + LDR r1, [r0] ; Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice ; Yes, skip the PendSV logic + MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup the current thread pointer + MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address + LDR r3, [r2] ; Pickup the execute thread pointer + MOV32 r0, 0xE000ED04 ; Build address of control register + MOV32 r2, 0x10000000 ; Build value for PendSV bit + CMP r1, r3 ; Are they the same? + BEQ __tx_timer_skip_time_slice ; If the same, there was no time-slice performed + STR r2, [r0] ; Not the same, issue the PendSV for preemption +__tx_timer_skip_time_slice: +; +; } +; +__tx_timer_not_ts_expiration: +; + LDMIA sp!, {r0, lr} ; Recover lr register (r0 is just there for + ; the 8-byte stack alignment +; +; } +; +__tx_timer_nothing_expired: + + DSB ; Complete all memory access + BX lr ; Return to caller +; +;} + END + diff --git a/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_alignment_adjust.c new file mode 100644 index 00000000..7425245b --- /dev/null +++ b/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -0,0 +1,400 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_power_of_two_block_size Cortex-M4/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calculates a power of two size at or immediately above*/ +/* the input size and returns it to the caller. */ +/* */ +/* INPUT */ +/* */ +/* size Block size */ +/* */ +/* OUTPUT */ +/* */ +/* calculated size Rounded up to power of two */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_power_of_two_block_size(ULONG size) +{ + /* Check for 0 size. */ + if(size == 0) + return 0; + + /* Minimum MPU block size is 32. */ + if(size <= 32) + return 32; + + /* Bit twiddling trick to round to next high power of 2 + (if original size is power of 2, it will return original size. Perfect!) */ + size--; + size |= size >> 1; + size |= size >> 2; + size |= size >> 4; + size |= size >> 8; + size |= size >> 16; + size++; + + /* Return a power of 2 size at or above the input size. */ + return(size); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_alignment_adjust Cortex-M4/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function adjusts the alignment and size of the code and data */ +/* section for a given module implementation. */ +/* */ +/* INPUT */ +/* */ +/* module_preamble Pointer to module preamble */ +/* code_size Size of the code area (updated) */ +/* code_alignment Code area alignment (updated) */ +/* data_size Size of data area (updated) */ +/* data_alignment Data area alignment (updated) */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_power_of_two_block_size Calculate power of two size */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, + ULONG *code_size, + ULONG *code_alignment, + ULONG *data_size, + ULONG *data_alignment) +{ + +ULONG local_code_size; +ULONG local_code_alignment; +ULONG local_data_size; +ULONG local_data_alignment; +ULONG code_block_size; +ULONG data_block_size; +ULONG code_size_accum; +ULONG data_size_accum; + + /* Copy the input parameters into local variables for ease of use. */ + local_code_size = *code_size; + local_code_alignment = *code_alignment; + local_data_size = *data_size; + local_data_alignment = *data_alignment; + + + /* Test for external memory enabled in preamble. */ + if(module_preamble -> txm_module_preamble_property_flags & TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS) + { + /* External/shared memory enabled. TXM_MODULE_MANAGER_CODE_MPU_ENTRIES-1 code entries will be used. */ + if (local_code_size <= (32*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 32 is best. */ + code_block_size = 32; + } + else if (local_code_size <= (64*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 64 is best. */ + code_block_size = 64; + } + else if (local_code_size <= (128*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 128 is best. */ + code_block_size = 128; + } + else if (local_code_size <= (256*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 256 is best. */ + code_block_size = 256; + } + else if (local_code_size <= (512*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 512 is best. */ + code_block_size = 512; + } + else if (local_code_size <= (1024*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 1024 is best. */ + code_block_size = 1024; + } + else if (local_code_size <= (2048*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 2048 is best. */ + code_block_size = 2048; + } + else if (local_code_size <= (4096*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 4096 is best. */ + code_block_size = 4096; + } + else if (local_code_size <= (8192*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 8192 is best. */ + code_block_size = 8192; + } + else if (local_code_size <= (16384*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 16384 is best. */ + code_block_size = 16384; + } + else if (local_code_size <= (32768*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 32768 is best. */ + code_block_size = 32768; + } + else if (local_code_size <= (65536*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 65536 is best. */ + code_block_size = 65536; + } + else if (local_code_size <= (131072*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 131072 is best. */ + code_block_size = 131072; + } + else if (local_code_size <= (262144*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 262144 is best. */ + code_block_size = 262144; + } + else if (local_code_size <= (524288*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 524288 is best. */ + code_block_size = 524288; + } + else if (local_code_size <= (1048576*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 1048576 is best. */ + code_block_size = 1048576; + } + else if (local_code_size <= (2097152*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 2097152 is best. */ + code_block_size = 2097152; + } + else if (local_code_size <= (4194304*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1))) + { + /* Block size of 4194304 is best. */ + code_block_size = 4194304; + } + else + { + /* Just set block size to 32MB just to create an allocation error! */ + code_block_size = 33554432; + } + + /* Calculate the new code size. */ + local_code_size = code_block_size*(TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1); + + /* Determine if the code block size is greater than the current alignment. If so, use block size + as the alignment. */ + if (code_block_size > local_code_alignment) + local_code_alignment = code_block_size; + + } + else + { + + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + local_code_alignment = _txm_power_of_two_block_size(local_code_size) >> 2; + code_size_accum = local_code_alignment + local_code_alignment; + code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); + code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); + local_code_size = code_size_accum; + } + + /* Determine the best data block size, which in our case is the minimal alignment. */ + if (local_data_size <= (32*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + + /* Block size of 32 is best. */ + data_block_size = 32; + } + else if (local_data_size <= (64*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 64 is best. */ + data_block_size = 64; + } + else if (local_data_size <= (128*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 128 is best. */ + data_block_size = 128; + } + else if (local_data_size <= (256*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 256 is best. */ + data_block_size = 256; + } + else if (local_data_size <= (512*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 512 is best. */ + data_block_size = 512; + } + else if (local_data_size <= (1024*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 1024 is best. */ + data_block_size = 1024; + } + else if (local_data_size <= (2048*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 2048 is best. */ + data_block_size = 2048; + } + else if (local_data_size <= (4096*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 4096 is best. */ + data_block_size = 4096; + } + else if (local_data_size <= (8192*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 8192 is best. */ + data_block_size = 8192; + } + else if (local_data_size <= (16384*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 16384 is best. */ + data_block_size = 16384; + } + else if (local_data_size <= (32768*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 32768 is best. */ + data_block_size = 32768; + } + else if (local_data_size <= (65536*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 65536 is best. */ + data_block_size = 65536; + } + else if (local_data_size <= (131072*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 131072 is best. */ + data_block_size = 131072; + } + else if (local_data_size <= (262144*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 262144 is best. */ + data_block_size = 262144; + } + else if (local_data_size <= (524288*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 524288 is best. */ + data_block_size = 524288; + } + else if (local_data_size <= (1048576*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 1048576 is best. */ + data_block_size = 1048576; + } + else if (local_data_size <= (2097152*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 2097152 is best. */ + data_block_size = 2097152; + } + else if (local_data_size <= (4194304*TXM_MODULE_MANAGER_DATA_MPU_ENTRIES)) + { + /* Block size of 4194304 is best. */ + data_block_size = 4194304; + } + else + { + + /* Just set data block size to 32MB just to create an allocation error! */ + data_block_size = 33554432; + } + + /* Calculate the new data size. */ + data_size_accum = data_block_size; + while(data_size_accum < local_data_size) + { + data_size_accum += data_block_size; + } + local_data_size = data_size_accum; + + /* Determine if the data block size is greater than the current alignment. If so, use block size + as the alignment. */ + if (data_block_size > local_data_alignment) + local_data_alignment = data_block_size; + + /* Return all the information to the caller. */ + *code_size = local_code_size; + *code_alignment = local_code_alignment; + *data_size = local_data_size; + *data_alignment = local_data_alignment; +} diff --git a/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_external_memory_enable.c new file mode 100644 index 00000000..4df714a7 --- /dev/null +++ b/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -0,0 +1,186 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_mutex.h" +#include "tx_queue.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_external_memory_enable Cortex-M4/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates an entry in the MPU table for a shared */ +/* memory space. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* start_address Start address of memory */ +/* length Length of external memory */ +/* attributes Memory attributes (r/w) */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_mutex_get Get protection mutex */ +/* _tx_mutex_put Release protection mutex */ +/* _txm_power_of_two_block_size Round length to power of two */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, + VOID *start_address, + ULONG length, + UINT attributes) +{ + +ULONG block_size; +ULONG region_size; +ULONG subregion_bits; +ULONG address; +UINT attributes_check = 0; +TXM_MODULE_PREAMBLE *module_preamble; + + /* Determine if the module manager has not been initialized yet. */ + if (_txm_module_manager_ready != TX_TRUE) + { + + /* Module manager has not been initialized. */ + return(TX_NOT_AVAILABLE); + } + + /* Determine if the module is valid. */ + if (module_instance == TX_NULL) + { + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Get module manager protection mutex. */ + _tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER); + + /* Determine if the module instance is valid. */ + if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) + { + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Determine if the module instance is in the loaded state. */ + if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) + { + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not ready. */ + return(TX_START_ERROR); + } + + /* Check if preamble shared mem and mem protection property bits are set. */ + module_preamble = module_instance -> txm_module_instance_preamble_ptr; + if((module_preamble -> txm_module_preamble_property_flags & (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) + != (TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS)) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if bit not set. */ + return(TXM_MODULE_INVALID_PROPERTIES); + } + + /* Start address and length must adhere to Cortex-M MPU. + The address must align with the block size. */ + + block_size = _txm_power_of_two_block_size(length); + address = (ULONG) start_address; + if(address != (address & ~(block_size - 1))) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return alignment error. */ + return(TXM_MODULE_ALIGNMENT_ERROR); + } + + /* At this point, we have a valid address and block size. + Set up MPU registers. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] = address | TXM_MODULE_MANAGER_SHARED_MPU_REGION | 0x10; + + /* Calculate the region size. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + /* Calculate the subregion bits. */ + subregion_bits = _txm_module_manager_calculate_srd_bits(block_size, length); + + /* Check for valid attributes. */ + if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) + { + attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; + } + + /* Build register with attributes. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX+1] = region_size | subregion_bits | attributes_check | 0x12070001; + + /* Keep track of shared memory address and length in module instance. */ + module_instance -> txm_module_instance_shared_memory_address = address; + module_instance -> txm_module_instance_shared_memory_length = length; + + /* Recalculate MPU settings. */ + _txm_module_manager_mm_register_setup(module_instance); + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return success. */ + return(TX_SUCCESS); +} + diff --git a/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c new file mode 100644 index 00000000..a6d64282 --- /dev/null +++ b/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -0,0 +1,114 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + +/* Define a macro that can be used to allocate global variables useful to + store information about the last fault. This macro is defined in + txm_module_port.h and is usually populated in the assembly language + fault handling prior to the code calling _txm_module_manager_memory_fault_handler. */ + +TXM_MODULE_MANAGER_FAULT_INFO + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_handler Cortex-M4/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles a fault associated with a memory protected */ +/* module. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_terminate Terminate thread */ +/* */ +/* CALLED BY */ +/* */ +/* Fault handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_memory_fault_handler(VOID) +{ + +TXM_MODULE_INSTANCE *module_instance_ptr; +TX_THREAD *thread_ptr; + + + /* Pickup the current thread. */ + thread_ptr = _tx_thread_current_ptr; + + /* Initialize the module instance pointer to NULL. */ + module_instance_ptr = TX_NULL; + + /* Is there a thread? */ + if (thread_ptr) + { + + /* Pickup the module instance. */ + module_instance_ptr = thread_ptr -> tx_thread_module_instance_ptr; + + /* Terminate the current thread. */ + _tx_thread_terminate(_tx_thread_current_ptr); + } + + /* Determine if there is a user memory fault notification callback. */ + if (_txm_module_manager_fault_notify) + { + + /* Yes, call the user's notification memory fault callback. */ + (_txm_module_manager_fault_notify)(thread_ptr, module_instance_ptr); + } +} + diff --git a/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c new file mode 100644 index 00000000..833d98bf --- /dev/null +++ b/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -0,0 +1,86 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the external user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_notify Cortex-M4/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application callback when/if a memory */ +/* fault occurs. The supplied thread is automatically terminated, but */ +/* any other threads in the same module may still execute. */ +/* */ +/* INPUT */ +/* */ +/* notify_function Memory fault notification */ +/* function, NULL disables. */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +{ + + /* Setup notification function. */ + _txm_module_manager_fault_notify = notify_function; + + /* Return success. */ + return(TX_SUCCESS); +} + diff --git a/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_mm_register_setup.c new file mode 100644 index 00000000..e567b33d --- /dev/null +++ b/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -0,0 +1,683 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" +#include "txm_module_manager_util.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_region_size_get Cortex-M4/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function converts the region size in bytes to the block size */ +/* for the Cortex-M4 MPU specification. */ +/* */ +/* INPUT */ +/* */ +/* block_size Size of the block in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* MPU size specification */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_module_manager_region_size_get(ULONG block_size) +{ + +ULONG return_value; + + + /* Process relative to the input block size. */ + if (block_size == 32) + { + return_value = 0x04; + } + else if (block_size == 64) + { + return_value = 0x05; + } + else if (block_size == 128) + { + return_value = 0x06; + } + else if (block_size == 256) + { + return_value = 0x07; + } + else if (block_size == 512) + { + return_value = 0x08; + } + else if (block_size == 1024) + { + return_value = 0x09; + } + else if (block_size == 2048) + { + return_value = 0x0A; + } + else if (block_size == 4096) + { + return_value = 0x0B; + } + else if (block_size == 8192) + { + return_value = 0x0C; + } + else if (block_size == 16384) + { + return_value = 0x0D; + } + else if (block_size == 32768) + { + return_value = 0x0E; + } + else if (block_size == 65536) + { + return_value = 0x0F; + } + else if (block_size == 131072) + { + return_value = 0x10; + } + else if (block_size == 262144) + { + return_value = 0x11; + } + else if (block_size == 524288) + { + return_value = 0x12; + } + else if (block_size == 1048576) + { + return_value = 0x13; + } + else if (block_size == 2097152) + { + return_value = 0x14; + } + else + { + /* Max 4MB MPU pages for modules. */ + return_value = 0x15; + } + + return(return_value); +} + + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_calculate_srd_bits Cortex-M4/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calculates the SRD bits that need to be set to */ +/* protect "length" bytes in a block. */ +/* */ +/* INPUT */ +/* */ +/* block_size Size of the block in bytes */ +/* length Actual length in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* SRD bits to be OR'ed with region attribute register. */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) +{ + +ULONG srd_bits = 0; +UINT srd_bit_index; + + /* length is smaller than block_size, set SRD bits if block_size is 256 or more. */ + if((block_size >= 256) && (length < block_size)) + { + /* Divide block_size by 8 by shifting right 3. Result is size of subregion. */ + block_size = block_size >> 3; + + /* Set SRD index into attribute register. */ + srd_bit_index = 8; + + /* If subregion overlaps length, move to the next subregion. */ + while(length > block_size) + { + length = length - block_size; + srd_bit_index++; + } + /* Check for a portion of code remaining. */ + if(length) + { + srd_bit_index++; + } + + /* Set unused subregion bits. */ + while(srd_bit_index < 16) + { + srd_bits = srd_bits | (0x1 << srd_bit_index); + srd_bit_index++; + } + } + + return(srd_bits); +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_mm_register_setup Cortex-M4/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets up the Cortex-M4 MPU register definitions based */ +/* on the module's memory characteristics. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* */ +/* OUTPUT */ +/* */ +/* MPU specifications for module in module_instance */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_manager_region_size_get */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_thread_create */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) +{ + +ULONG code_address; +ULONG code_size; +ULONG data_address; +ULONG data_size; +ULONG start_stop_stack_size; +ULONG callback_stack_size; +ULONG block_size; +ULONG base_address_register; +ULONG base_attribute_register; +ULONG region_size; +ULONG srd_bits = 0; +UINT mpu_register = 0; +UINT mpu_table_index; +UINT i; + + + /* Setup the first region for the ThreadX trampoline code. */ + /* Set base register to user mode entry, which is guaranteed to be at least 32-byte aligned. */ + base_address_register = (ULONG) _txm_module_manager_user_mode_entry; + /* Mask address to proper range, region 0, set Valid bit. */ + base_address_register = (base_address_register & 0xFFFFFFE0) | mpu_register | 0x10; + module_instance -> txm_module_instance_mpu_registers[0] = base_address_register; + /* Attributes: read only, write-back, shareable, size 32 bytes, region enabled. */ + module_instance -> txm_module_instance_mpu_registers[1] = 0x06070009; + + /* Initialize the MPU register. */ + mpu_register = 1; + + /* Initialize the MPU table index. */ + mpu_table_index = 2; + + /* Setup values for code area. */ + code_address = (ULONG) module_instance -> txm_module_instance_code_start; + code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; + + + /* Check if shared memory was set up. If so, only 3 entries are available for + code protection. If not set up, 4 code entries are available. */ + if(module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MANAGER_SHARED_MPU_INDEX] == 0) + { + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + + /* Now loop through to setup MPU protection for the code area. */ + for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES; i++) + { + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + if (i < 2) + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + } + + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ + else if (i == 2) + { + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size) >> 1; + } + + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + else + { + /* Calculate remaining space. */ + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + + /* Build the base address register. */ + base_address_register = (code_address & ~(block_size - 1)) | mpu_register | 0x10; + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Build the base attribute register. */ + base_attribute_register = region_size | srd_bits | 0x06070001; + + /* Setup the MPU Base Address Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; + + /* Setup the MPU Base Attribute Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; + + /* Adjust the code address. */ + code_address = code_address + block_size; + + /* Move MPU table index. */ + mpu_table_index = mpu_table_index + 2; + + /* Increment the MPU register index. */ + mpu_register++; + } + } + + /* Only 3 code entries available. */ + else + { + /* Calculate block size, one code entry taken up by shared memory. */ + block_size = _txm_power_of_two_block_size(code_size / (TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1)); + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Now loop through to setup MPU protection for the code area. */ + for (i = 0; i < TXM_MODULE_MANAGER_CODE_MPU_ENTRIES - 1; i++) + { + + /* Build the base address register. */ + base_address_register = code_address & ~(block_size - 1) | mpu_register | 0x10; + + /* Check if SRD bits need to be set. */ + if (code_size < block_size) + { + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + + /* Build the base attribute register. */ + base_attribute_register = region_size | srd_bits | 0x06070000; + + /* Is there still some code? If so set the region enable bit. */ + if (code_size) + { + /* Set the region enable bit. */ + base_attribute_register = base_attribute_register | 0x1; + } + /* Setup the MPU Base Address Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; + + /* Setup the MPU Base Attribute Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; + + /* Adjust the code address. */ + code_address = code_address + block_size; + + /* Decrement the code size. */ + if (code_size > block_size) + code_size = code_size - block_size; + else + code_size = 0; + + /* Move MPU table index. */ + mpu_table_index = mpu_table_index + 2; + + /* Increment the MPU register index. */ + mpu_register++; + } + + /* Adjust indeces to pass over the shared memory entry. */ + /* Move MPU table index. */ + mpu_table_index = mpu_table_index + 2; + + /* Increment the MPU register index. */ + mpu_register++; + } + + /* Setup values for data area. */ + data_address = (ULONG) module_instance -> txm_module_instance_data_start; + + /* Adjust the size of the module elements to be aligned to the default alignment. We do this + so that when we partition the allocated memory, we can simply place these regions right beside + each other without having to align their pointers. Note this only works when they all have + the same alignment. */ + + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; + start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; + callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; + + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + /* Update the data size to include thread stacks. */ + data_size = data_size + start_stop_stack_size + callback_stack_size; + + + block_size = _txm_power_of_two_block_size(data_size / TXM_MODULE_MANAGER_DATA_MPU_ENTRIES); + + /* Reset SRD bitfield. */ + srd_bits = 0; + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Now loop through to setup MPU protection for the data area. */ + for (i = 0; i < TXM_MODULE_MANAGER_DATA_MPU_ENTRIES; i++) + { + + /* Build the base address register. */ + base_address_register = (data_address & ~(block_size - 1)) | mpu_register | 0x10; + + /* Check if SRD bits need to be set. */ + if (data_size < block_size) + { + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + } + + /* Build the base attribute register. */ + base_attribute_register = region_size | srd_bits | 0x13070000; + + /* Is there still some data? If so set the region enable bit. */ + if (data_size) + { + /* Set the region enable bit. */ + base_attribute_register = base_attribute_register | 0x1; + } + + /* Setup the MPU Base Address Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index] = base_address_register; + + /* Setup the MPU Base Attribute Register. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index+1] = base_attribute_register; + + /* Adjust the data address. */ + data_address = data_address + block_size; + + /* Decrement the data size. */ + if (data_size > block_size) + data_size = data_size - block_size; + else + data_size = 0; + + /* Move MPU table index. */ + mpu_table_index = mpu_table_index + 2; + + /* Increment the MPU register index. */ + mpu_register++; + } + +} + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_shared_memory_check_outside */ +/* Cortex-M4/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks if the specified object is outside shared */ +/* memory. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* obj_ptr Pointer to the object */ +/* obj_size Size of the object */ +/* */ +/* OUTPUT */ +/* */ +/* Whether the object is outside the shared memory region. */ +/* */ +/* CALLS */ +/* */ +/* N/A */ +/* */ +/* CALLED BY */ +/* */ +/* Module dispatch check functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UCHAR _txm_module_manager_shared_memory_check_outside(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) +{ + +ALIGN_TYPE shared_memory_start; +ALIGN_TYPE shared_memory_end; + + shared_memory_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address; + shared_memory_end = shared_memory_start + module_instance -> txm_module_instance_shared_memory_length; + + if (TXM_MODULE_MANAGER_CHECK_OUTSIDE_RANGE_EXCLUSIVE(shared_memory_start, shared_memory_end, + obj_ptr, obj_size)) + { + return(TX_TRUE); + } + return(TX_FALSE); +} + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_shared_memory_check_inside Cortex-M4/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks if the specified object is inside shared */ +/* memory. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* obj_ptr Pointer to the object */ +/* obj_size Size of the object */ +/* */ +/* OUTPUT */ +/* */ +/* Whether the object is inside the shared memory region. */ +/* */ +/* CALLS */ +/* */ +/* N/A */ +/* */ +/* CALLED BY */ +/* */ +/* Module dispatch check functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UCHAR _txm_module_manager_shared_memory_check_inside(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) +{ + +ALIGN_TYPE shared_memory_start; +ALIGN_TYPE shared_memory_end; + + shared_memory_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address; + shared_memory_end = shared_memory_start + module_instance -> txm_module_instance_shared_memory_length; + + if (TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_EXCLUSIVE(shared_memory_start, shared_memory_end, + obj_ptr, obj_size)) + { + return(TX_TRUE); + } + return(TX_FALSE); +} + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_shared_memory_check_inside_byte */ +/* Cortex-M4/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks if the specified byte is inside shared memory. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* byte_ptr Pointer to the byte */ +/* */ +/* OUTPUT */ +/* */ +/* Whether the byte is inside the shared memory region. */ +/* */ +/* CALLS */ +/* */ +/* N/A */ +/* */ +/* CALLED BY */ +/* */ +/* Module dispatch check functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UCHAR _txm_module_manager_shared_memory_check_inside_byte(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE byte_ptr) +{ + +ALIGN_TYPE shared_memory_start; +ALIGN_TYPE shared_memory_end; + + shared_memory_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address; + shared_memory_end = shared_memory_start + module_instance -> txm_module_instance_shared_memory_length; + + if (TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_EXCLUSIVE_BYTE(shared_memory_start, shared_memory_end, + byte_ptr)) + { + return(TX_TRUE); + } + return(TX_FALSE); +} diff --git a/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_thread_stack_build.s new file mode 100644 index 00000000..f7dc7b68 --- /dev/null +++ b/ports_module/cortex-m4/iar/module_manager/src/txm_module_manager_thread_stack_build.s @@ -0,0 +1,153 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Module Manager */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _txm_module_manager_thread_stack_build Cortex-M4/MPU/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread */ +;/* function_ptr Pointer to shell function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +;{ + PUBLIC _txm_module_manager_thread_stack_build +_txm_module_manager_thread_stack_build: +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-M should look like the following after it is built: +; +; Stack Top: +; LR Interrupted LR (LR at time of PENDSV) +; r4 Initial value for r4 +; r5 Initial value for r5 +; r6 Initial value for r6 +; r7 Initial value for r7 +; r8 Initial value for r8 +; r9 Initial value for r9 +; r10 (sl) Initial value for r10 (sl) +; r11 Initial value for r11 +; r0 Initial value for r0 (Hardware stack starts here!!) +; r1 Initial value for r1 +; r2 Initial value for r2 +; r3 Initial value for r3 +; r12 Initial value for r12 +; lr Initial value for lr +; pc Initial value for pc +; xPSR Initial value for xPSR +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #0x7 ; Align frame + SUB r2, r2, #68 ; Subtract frame size + LDR r3, =0xFFFFFFFD ; Build initial LR value + STR r3, [r2, #0] ; Save on the stack +; +; /* Actually build the stack frame. */ +; + MOV r3, #0 ; Build initial register value + STR r3, [r2, #4] ; Store initial r4 + STR r3, [r2, #8] ; Store initial r5 + STR r3, [r2, #12] ; Store initial r6 + STR r3, [r2, #16] ; Store initial r7 + STR r3, [r2, #20] ; Store initial r8 + LDR r3, [r0, #12] ; Pickup stack starting address + STR r3, [r2, #28] ; Store initial r10 (sl) + MOV r3, #0 ; Build initial register value + STR r3, [r2, #32] ; Store initial r11 +; +; /* Hardware stack follows. / +; + STR r0, [r2, #36] ; Store initial r0, which is the thread control block + + LDR r3, [r0, #8] ; Pickup thread entry info pointer,which is in the stack pointer position of the thread control block. + ; It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this + ; function with the actual, initial stack pointer. + STR r3, [r2, #40] ; Store initial r1, which is the module entry information. + LDR r3, [r3, #8] ; Pickup data base register from the module information + STR r3, [r2, #24] ; Store initial r9 (data base register) + MOV r3, #0 ; Clear r3 again + + STR r3, [r2, #44] ; Store initial r2 + STR r3, [r2, #48] ; Store initial r3 + STR r3, [r2, #52] ; Store initial r12 + MOV r3, #0xFFFFFFFF ; Poison EXC_RETURN value + STR r3, [r2, #56] ; Store initial lr + STR r1, [r2, #60] ; Store initial pc + MOV r3, #0x01000000 ; Only T-bit need be set + STR r3, [r2, #64] ; Store initial xPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block + BX lr ; Return to caller +;} + END + diff --git a/ports_module/cortex-m7/ac5/inc/tx_port.h b/ports_module/cortex-m7/ac5/inc/tx_port.h new file mode 100644 index 00000000..c4153b1d --- /dev/null +++ b/ports_module/cortex-m7/ac5/inc/tx_port.h @@ -0,0 +1,487 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-M7/AC5 */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX Cortex-M3 port. */ + +#define TX_INT_DISABLE 1 /* Disable interrupts */ +#define TX_INT_ENABLE 0 /* Enable interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) +#endif +#else +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif + +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) + + +#ifndef TX_MISRA_ENABLE + +register unsigned int _ipsr __asm("ipsr"); + +#endif + + +#ifdef __TARGET_FPU_VFP + +#ifdef TX_MISRA_ENABLE + +ULONG _tx_misra_control_get(void); +void _tx_misra_control_set(ULONG value); +ULONG _tx_misra_fpccr_get(void); +void _tx_misra_vfp_touch(void); + +#else + +#ifdef TX_SOURCE_CODE + +register ULONG _control __asm("control"); + +#endif +#endif + +/* A completed thread falls into _thread_shell_entry and we can simply deactivate the FPU via CONTROL.FPCA + in order to ensure no lazy stacking will occur. */ + +#ifndef TX_MISRA_ENABLE + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _control; \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _control = _tx_vfp_state; \ + } +#else + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } + +#endif + +/* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. + If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + the lazy FPU save, then restore the CONTROL.FPCA state. */ + +#ifndef TX_MISRA_ENABLE + +void _tx_vfp_access(void); + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _control; \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _control = _tx_vfp_state; \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = *((ULONG *) 0xE000EF34); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _control; \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + _tx_vfp_access(); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = _control; \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _control = _tx_vfp_state; \ + } \ + } \ + } \ + } +#else + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = _tx_misra_fpccr_get(); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + _tx_misra_vfp_touch(); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + } \ + } \ + } +#endif + +#else + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + +#endif + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define the get system state macro. */ + +#ifndef TX_THREAD_GET_SYSTEM_STATE +#ifndef TX_MISRA_ENABLE +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _ipsr) +#else +ULONG _tx_misra_ipsr_get(VOID); +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get()) +#endif +#endif + + +/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value + indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h + for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always + zero after initialization for Cortex-M ports. */ + +#ifndef TX_THREAD_SYSTEM_RETURN_CHECK +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#endif + + +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to + prevent early scheduling on Cortex-M parts. */ + +#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __clz(__rbit((m))); + +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifdef TX_DISABLE_INLINE + +UINT _tx_thread_interrupt_disable(VOID); +VOID _tx_thread_interrupt_restore(UINT previous_posture); + +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); + +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA unsigned int was_masked; +#define TX_DISABLE was_masked = __disable_irq(); +#define TX_RESTORE if (was_masked == 0) __enable_irq(); + +#define _tx_thread_system_return _tx_thread_system_return_inline + + +static void _tx_thread_system_return_inline(void) +{ +unsigned int was_masked; + + + /* Set PendSV to invoke ThreadX scheduler. */ + *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + if (_ipsr == 0) + { + was_masked = __disable_irq(); + __enable_irq(); + if (was_masked != 0) + __disable_irq(); + } +} +#endif + + +/* Define FPU extension for the Cortex-M7. Each is assumed to be called in the context of the executing + thread. These are no longer needed, but are preserved for backward compatibility only. */ + +void tx_thread_fpu_enable(void); +void tx_thread_fpu_disable(void); + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/AC5 Version 6.0.1 *"; +#else +#ifdef TX_MISRA_ENABLE +extern CHAR _tx_version_id[100]; +#else +extern CHAR _tx_version_id[]; +#endif +#endif + + +#endif + + + + diff --git a/ports_module/cortex-m7/ac5/inc/txm_module_port.h b/ports_module/cortex-m7/ac5/inc/txm_module_port.h new file mode 100644 index 00000000..caf00eae --- /dev/null +++ b/ports_module/cortex-m7/ac5/inc/txm_module_port.h @@ -0,0 +1,371 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* txm_module_port.h Cortex-M7/MPU/AC5 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the basic module constants, interface structures, */ +/* and function prototypes. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TXM_MODULE_PORT_H +#define TXM_MODULE_PORT_H + +/* It is assumed that the base ThreadX tx_port.h file has been modified to add the + following extensions to the ThreadX thread control block (this code should replace + the corresponding macro define in tx_port.h): + +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; + +The following extensions must also be defined in tx_port.h: + +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); + +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); +*/ + +#define TXM_MODULE_THREAD_ENTRY_INFO_USER_EXTENSION + +/**************************************************************************/ +/* User-adjustable constants */ +/**************************************************************************/ + +/* Size of module heap. */ +#define TXM_MODULE_HEAP_SIZE 512 + + +#ifndef TXM_ASSEMBLY + +/* Define the kernel stack size for a module thread. */ +#ifndef TXM_MODULE_KERNEL_STACK_SIZE +#define TXM_MODULE_KERNEL_STACK_SIZE 512 +#endif + +/* For the following 3 access control settings, change TEX and C, B, S (bits 21 through 16 of MPU_RASR) + * to reflect your system memory attributes (cache, shareable, memory type). */ +/* Code region access control: privileged read-only, outer & inner write-back, normal memory, shareable. */ +#define TXM_MODULE_MPU_CODE_ACCESS_CONTROL 0x06070000 +/* Data region access control: execute never, read/write, outer & inner write-back, normal memory, shareable. */ +#define TXM_MODULE_MPU_DATA_ACCESS_CONTROL 0x13070000 +/* Shared region access control: execute never, read-only, outer & inner write-back, normal memory, shareable. */ +#define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 + +/**************************************************************************/ +/* End of user-adjustable constants */ +/**************************************************************************/ + + + +/* Define constants specific to the tools the module can be built with for this particular modules port. */ + +#define TXM_MODULE_IAR_COMPILER 0x00000000 +#define TXM_MODULE_RVDS_COMPILER 0x01000000 +#define TXM_MODULE_GNU_COMPILER 0x02000000 +#define TXM_MODULE_COMPILER_MASK 0xFF000000 +#define TXM_MODULE_OPTIONS_MASK 0x000000FF + + +/* Define the properties for this particular module port. */ + +#define TXM_MODULE_MEMORY_PROTECTION_ENABLED + +#ifdef TXM_MODULE_MEMORY_PROTECTION_ENABLED +#define TXM_MODULE_REQUIRE_ALLOCATED_OBJECT_MEMORY +#else +#define TXM_MODULE_REQUIRE_LOCAL_OBJECT_MEMORY +#endif + +#define TXM_MODULE_USER_MODE 0x00000001 +#define TXM_MODULE_MEMORY_PROTECTION 0x00000002 +#define TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS 0x00000004 + + +/* Define the supported options for this module. */ + +#define TXM_MODULE_MANAGER_SUPPORTED_OPTIONS (TXM_MODULE_USER_MODE | TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS) +#define TXM_MODULE_MANAGER_REQUIRED_OPTIONS 0 + + +/* Define offset adjustments according to the compiler used to build the module. */ + +#define TXM_MODULE_IAR_SHELL_ADJUST 24 +#define TXM_MODULE_IAR_START_ADJUST 28 +#define TXM_MODULE_IAR_STOP_ADJUST 32 +#define TXM_MODULE_IAR_CALLBACK_ADJUST 44 + +#define TXM_MODULE_RVDS_SHELL_ADJUST 0 +#define TXM_MODULE_RVDS_START_ADJUST 0 +#define TXM_MODULE_RVDS_STOP_ADJUST 0 +#define TXM_MODULE_RVDS_CALLBACK_ADJUST 0 + +#define TXM_MODULE_GNU_SHELL_ADJUST 24 +#define TXM_MODULE_GNU_START_ADJUST 28 +#define TXM_MODULE_GNU_STOP_ADJUST 32 +#define TXM_MODULE_GNU_CALLBACK_ADJUST 44 + + +/* Define other module port-specific constants. */ + +/* Define INLINE_DECLARE to whitespace for ARM compiler. */ + +#define INLINE_DECLARE + +/* Define the number of MPU entries assigned to the code and data sections. + On Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access + to the kernel entry function, thus 15 remain for code and data protection. */ +#define TXM_MODULE_MPU_TOTAL_ENTRIES 16 +#define TXM_MODULE_MPU_CODE_ENTRIES 4 +#define TXM_MODULE_MPU_DATA_ENTRIES 4 +#define TXM_MODULE_MPU_SHARED_ENTRIES 3 + +#define TXM_MODULE_MPU_KERNEL_ENTRY_INDEX 0 +#define TXM_MODULE_MPU_SHARED_INDEX 9 + +#define TXM_ENABLE_REGION 0x01 + +/* There are 2 registers to set up each MPU region: MPU_RBAR, MPU_RASR. */ +typedef struct TXM_MODULE_MPU_INFO_STRUCT +{ + ULONG txm_module_mpu_region_address; + ULONG txm_module_mpu_region_attribute_size; +} TXM_MODULE_MPU_INFO; +/* Shared memory region attributes. */ +#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 +#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 + +/* Define the port-extensions to the module manager instance structure. */ + +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_count; \ + ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES]; + + +/* Define the memory fault information structure that is populated when a memory fault occurs. */ + + +typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT +{ + TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr; + VOID *txm_module_manager_memory_fault_info_code_location; + ULONG txm_module_manager_memory_fault_info_shcsr; + ULONG txm_module_manager_memory_fault_info_mmfsr; + ULONG txm_module_manager_memory_fault_info_mmfar; + ULONG txm_module_manager_memory_fault_info_control; + ULONG txm_module_manager_memory_fault_info_sp; + ULONG txm_module_manager_memory_fault_info_r0; + ULONG txm_module_manager_memory_fault_info_r1; + ULONG txm_module_manager_memory_fault_info_r2; + ULONG txm_module_manager_memory_fault_info_r3; + ULONG txm_module_manager_memory_fault_info_r4; + ULONG txm_module_manager_memory_fault_info_r5; + ULONG txm_module_manager_memory_fault_info_r6; + ULONG txm_module_manager_memory_fault_info_r7; + ULONG txm_module_manager_memory_fault_info_r8; + ULONG txm_module_manager_memory_fault_info_r9; + ULONG txm_module_manager_memory_fault_info_r10; + ULONG txm_module_manager_memory_fault_info_r11; + ULONG txm_module_manager_memory_fault_info_r12; + ULONG txm_module_manager_memory_fault_info_lr; + ULONG txm_module_manager_memory_fault_info_xpsr; +} TXM_MODULE_MANAGER_MEMORY_FAULT_INFO; + + +#define TXM_MODULE_MANAGER_FAULT_INFO \ + TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; + +/* Define the macro to check the stack available in dispatch. */ +#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE \ + ULONG stack_available; \ + __asm("MOV %0, SP" : "=r"(stack_available)); \ + stack_available -= (ULONG)_tx_thread_current_ptr->tx_thread_stack_start; \ + if((stack_available < TXM_MODULE_MINIMUM_STACK_AVAILABLE) || \ + (stack_available > _tx_thread_current_ptr->tx_thread_stack_size)) \ + { \ + return(TX_SIZE_ERROR); \ + } + + +/* Define the macro to check the code alignment. */ + +#define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment) \ + { \ + ULONG temp; \ + temp = (ULONG) module_location; \ + temp = temp & (code_alignment - 1); \ + if (temp) \ + { \ + _tx_mutex_put(&_txm_module_manager_mutex); \ + return(TXM_MODULE_ALIGNMENT_ERROR); \ + } \ + } + + +/* Define the macro to adjust the alignment and size for code/data areas. */ + +#define TXM_MODULE_MANAGER_ALIGNMENT_ADJUST(module_preamble, code_size, code_alignment, data_size, data_alignment) _txm_module_manager_alignment_adjust(module_preamble, &code_size, &code_alignment, &data_size, &data_alignment); + + +/* Define the macro to adjust the symbols in the module preamble. */ + +#define TXM_MODULE_MANAGER_CALCULATE_ADJUSTMENTS(properties, shell_function_adjust, start_function_adjust, stop_function_adjust, callback_function_adjust) \ + if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_IAR_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_IAR_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_IAR_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_IAR_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_IAR_CALLBACK_ADJUST; \ + } \ + else if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_RVDS_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_RVDS_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_RVDS_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_RVDS_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_RVDS_CALLBACK_ADJUST; \ + } \ + else \ + { \ + shell_function_adjust = TXM_MODULE_GNU_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_GNU_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_GNU_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_GNU_CALLBACK_ADJUST; \ + } + + +/* Define the macro to populate the thread control block with module port-specific information. + Check if the module is in user mode and set up txm_module_thread_entry_info_kernel_call_dispatcher accordingly. +*/ + +#define TXM_MODULE_MANAGER_THREAD_SETUP(thread_ptr, module_instance) \ + thread_ptr -> tx_thread_module_current_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \ + thread_ptr -> tx_thread_module_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \ + if (thread_ptr -> tx_thread_module_user_mode) \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_user_mode_entry; \ + } \ + else \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_kernel_dispatch; \ + } + + +/* Define the macro to populate the module control block with module port-specific information. + If memory protection is enabled, set up the MPU registers. +*/ +#define TXM_MODULE_MANAGER_MODULE_SETUP(module_instance) \ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE) \ + { \ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) \ + { \ + _txm_module_manager_mm_register_setup(module_instance); \ + } \ + } \ + else \ + { \ + /* Do nothing. */ \ + } + +/* Define the macro to perform port-specific functions when unloading the module. */ +/* Nothing needs to be done for this port. */ +#define TXM_MODULE_MANAGER_MODULE_UNLOAD(module_instance) + + +/* Define the macro to perform port-specific functions when passing pointer to kernel. */ +#define TXM_MODULE_MANAGER_CHECK_DATA_POINTER(module_instance, pointer) \ + if(_txm_module_manager_data_pointer_check(module_instance, pointer)) \ + { return(TXM_MODULE_INVALID_MEMORY); } + +/* Define the macro to perform port-specific functions when passing function pointer to kernel. */ +/* Determine if the pointer is within the module's code memory. */ +#define TXM_MODULE_MANAGER_CHECK_FUNCTION_POINTER(module_instance, pointer) \ + if (((pointer < sizeof(TXM_MODULE_PREAMBLE) + (ULONG) module_instance -> txm_module_instance_code_start) || \ + ((pointer+sizeof(pointer)) > (ULONG) module_instance -> txm_module_instance_code_end)) \ + && (pointer != (ULONG) TX_NULL)) \ + { \ + return(TX_PTR_ERROR); \ + } + +/* Define some internal prototypes to this module port. */ + +#ifndef TX_SOURCE_CODE +#define txm_module_manager_memory_fault_notify _txm_module_manager_memory_fault_notify +#endif + + +#define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES \ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment); \ +ULONG _txm_module_manager_data_pointer_check(TXM_MODULE_INSTANCE *module_instance, ULONG pointer); \ +VOID _txm_module_manager_memory_fault_handler(VOID); \ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)); \ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \ +ULONG _txm_power_of_two_block_size(ULONG size); \ +ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); \ +ULONG _txm_module_manager_region_size_get(ULONG block_size); \ +ULONG _txm_module_manager_pointer_check(TXM_MODULE_INSTANCE *module_instance, ULONG pointer); \ +UCHAR _txm_module_manager_shared_memory_check_outside(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size); \ +UCHAR _txm_module_manager_shared_memory_check_inside(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size); \ +UCHAR _txm_module_manager_shared_memory_check_inside_byte(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr); + +#define TXM_MODULE_MANAGER_VERSION_ID \ +CHAR _txm_module_manager_version_id[] = \ + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M7/MPU/AC5 Version 6.0.1 *"; + +#endif /* ifndef TXM_ASSEMBLY */ +#endif diff --git a/ports_module/cortex-m7/ac5/module_lib/src/txm_module_initialize.s b/ports_module/cortex-m7/ac5/module_lib/src/txm_module_initialize.s new file mode 100644 index 00000000..8563b535 --- /dev/null +++ b/ports_module/cortex-m7/ac5/module_lib/src/txm_module_initialize.s @@ -0,0 +1,126 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Module */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" + +#include "txm_module_port.h" + +; +; + IMPORT __use_two_region_memory + IMPORT __scatterload + IMPORT txm_heap + + + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _txm_module_initialize Cortex-M7/MPU/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function initializes the module c runtime. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* __scatterload Initialize C runtime */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _txm_module_thread_shell_entry Start module thread */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _txm_module_initialize(VOID) + + EXPORT _txm_module_initialize +_txm_module_initialize + PUSH {r4-r12,lr} ; Save dregs and LR + + B __scatterload ; Call ARM func to initialize variables + +; +;/* Override __rt_exit function. */ +; + EXPORT __rt_exit +__rt_exit + + POP {r4-r12,lr} ; Restore dregs and LR + BX lr ; Return to caller +; +; +; + EXPORT __user_setup_stackheap + ; returns heap start address in R0 + ; returns heap end address in R2 + ; does not touch SP, it is already set up before the module runs + +__user_setup_stackheap + LDR r1, _tx_heap_offset ; load heap offset + ADD r0, r9, r1 ; calculate heap base address + MOV r2, #TXM_MODULE_HEAP_SIZE ; load heap size + ADD r2, r2, r0 ; calculate heap end address + BX lr + + ALIGN 4 +_tx_heap_offset + DCDO txm_heap + AREA ||.arm_vfe_header||, DATA, READONLY, NOALLOC, ALIGN=2 + + IMPORT txm_heap [DATA] + +; +; Dummy main function +; + AREA section_main, CODE, READONLY, ALIGN=2 + EXPORT main +main + BX lr + + END + diff --git a/ports_module/cortex-m7/ac5/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex-m7/ac5/module_lib/src/txm_module_thread_shell_entry.c new file mode 100644 index 00000000..b6567baf --- /dev/null +++ b/ports_module/cortex-m7/ac5/module_lib/src/txm_module_thread_shell_entry.c @@ -0,0 +1,175 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#ifndef TXM_MODULE +#define TXM_MODULE +#endif + +#ifndef TX_SOURCE_CODE +#define TX_SOURCE_CODE +#endif + + +/* Include necessary system files. */ + +#include "txm_module.h" +#include "tx_thread.h" + +/* Define the global module entry pointer from the start thread of the module. */ + +TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; + + +/* Define the dispatch function pointer used in the module implementation. */ + +ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3); + + +/* Define the ARM cstartup code. */ +extern VOID _txm_module_initialize(VOID); + +__align(8) UCHAR txm_heap[TXM_MODULE_HEAP_SIZE]; + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_thread_shell_entry Cortex-M7/MPU/AC5 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calls the specified entry function of the thread. It */ +/* also provides a place for the thread's entry function to return. */ +/* If the thread returns, this function places the thread in a */ +/* "COMPLETED" state. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to current thread */ +/* thread_info Pointer to thread entry info */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_initialize cstartup initialization */ +/* thread_entry Thread's entry function */ +/* tx_thread_resume Resume the module callback thread */ +/* _txm_module_thread_system_suspend Module thread suspension routine */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) +{ + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + VOID (*entry_exit_notify)(TX_THREAD *, UINT); +#endif + + + /* Determine if this is the start thread. If so, we must prepare the module for + execution. If not, simply skip the C startup code. */ + if (thread_info -> txm_module_thread_entry_info_start_thread) + { + + /* Initialize the ARM C environment. */ + _txm_module_initialize(); + + /* Save the entry info pointer, for later use. */ + _txm_module_entry_info = thread_info; + + /* Save the kernel function dispatch address. This is used to make all resident calls from + the module. */ + _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; + + /* Ensure that we have a valid pointer. */ + while (!_txm_module_kernel_call_dispatcher) + { + + /* Loop here, if an error is present getting the dispatch function pointer! + An error here typically indicates the resident portion of _tx_thread_schedule + is not supporting the trap to obtain the function pointer. */ + } + + /* Resume the module's callback thread, already created in the manager. */ + _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); + } + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has been entered! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_ENTRY); + } +#endif + + /* Call current thread's entry function. */ + (thread_info -> txm_module_thread_entry_info_entry) (thread_info -> txm_module_thread_entry_info_parameter); + + /* Suspend thread with a "completed" state. */ + + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine again. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has exited! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_EXIT); + } +#endif + + /* Call actual thread suspension routine. */ + _txm_module_thread_system_suspend(thread_ptr); + +#ifdef TX_SAFETY_CRITICAL + + /* If we ever get here, raise safety critical exception. */ + TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0); +#endif +} + diff --git a/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_context_restore.s new file mode 100644 index 00000000..6d310a17 --- /dev/null +++ b/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_context_restore.s @@ -0,0 +1,94 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_exit + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-M4/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + EXPORT _tx_thread_context_restore +_tx_thread_context_restore + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + PUSH {r0,lr} ; Save ISR lr + BL _tx_execution_isr_exit ; Call the ISR exit function + POP {r0,lr} ; Restore ISR lr + ENDIF +; + POP {lr} + BX lr +;} + ALIGN + LTORG + END diff --git a/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_context_save.s b/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_context_save.s new file mode 100644 index 00000000..052c3e5a --- /dev/null +++ b/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_context_save.s @@ -0,0 +1,94 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-M4/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + EXPORT _tx_thread_context_save +_tx_thread_context_save + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {r0, lr} ; Save ISR lr + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {lr0, r} ; Recover ISR lr + ENDIF +; +; /* Return to interrupt processing. */ +; + BX lr ; Return to interrupt processing caller +;} + ALIGN + LTORG + END diff --git a/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..e97c7a47 --- /dev/null +++ b/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_interrupt_control.s @@ -0,0 +1,80 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-M4/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + EXPORT _tx_thread_interrupt_control +_tx_thread_interrupt_control +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r1, PRIMASK + MSR PRIMASK, r0 + MOV r0, r1 + BX lr +; +;} + END + diff --git a/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_interrupt_disable.s new file mode 100644 index 00000000..e366e44b --- /dev/null +++ b/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_interrupt_disable.s @@ -0,0 +1,78 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-M4/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation. */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts and returning */ +;/* the previous interrupt lockout posture. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(UINT new_posture) +;{ + EXPORT _tx_thread_interrupt_disable +_tx_thread_interrupt_disable +; +; /* Return current interrupt lockout posture. */ +; + MRS r0, PRIMASK + CPSID i + BX lr +; +;} + END diff --git a/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_interrupt_restore.s new file mode 100644 index 00000000..1d0bffb6 --- /dev/null +++ b/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_interrupt_restore.s @@ -0,0 +1,77 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-M4/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation. */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for restoring the previous */ +;/* interrupt lockout posture. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* previous_posture Previous interrupt posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_interrupt_restore(UINT new_posture) +;{ + EXPORT _tx_thread_interrupt_restore +_tx_thread_interrupt_restore +; +; /* Restore previous interrupt lockout posture. */ +; + MSR PRIMASK, r0 + BX lr +; +;} + END diff --git a/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_schedule.s b/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_schedule.s new file mode 100644 index 00000000..f096baa2 --- /dev/null +++ b/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_schedule.s @@ -0,0 +1,583 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_execute_ptr + IMPORT _tx_timer_time_slice + IMPORT _tx_thread_system_stack_ptr + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_thread_enter + IMPORT _tx_execution_thread_exit + ENDIF + IMPORT _tx_thread_preempt_disable + IMPORT _txm_module_manager_memory_fault_handler + IMPORT _txm_module_manager_memory_fault_info +; +; + AREA ||.text||, CODE, READONLY + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-M7/MPU/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + EXPORT _tx_thread_schedule +_tx_thread_schedule +; +; /* This function should only ever be called on Cortex-M +; from the first schedule request. Subsequent scheduling occurs +; from the PendSV handling routines below. */ +; +; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ +; + MOV r0, #0 ; Build value for TX_FALSE + LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag + STR r0, [r2, #0] ; Clear preempt disable flag +; +; /* Clear CONTROL.FPCA bit so FPU registers aren't unnecessarily stacked. */ +; + IF :DEF:__ARMVFP__ + MRS r0, CONTROL ; Pickup current CONTROL register + BIC r0, r0, #4 ; Clear the FPCA bit + MSR CONTROL, r0 ; Setup new CONTROL register + ENDIF +; +; /* Enable memory fault registers. */ +; + LDR r0, =0xE000ED24 ; Build SHCSR address + LDR r1, =0x70000 ; Enable Usage, Bus, and MemManage faults + STR r1, [r0] ; +; +; /* Enable interrupts */ +; + CPSIE i +; +; /* Enter the scheduler for the first time. */ +; + MOV r0, #0x10000000 ; Load PENDSVSET bit + MOV r1, #0xE000E000 ; Load NVIC base + STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR + NOP ; + NOP ; + NOP ; + NOP ; +__wait_loop + B __wait_loop +; +; /* We should never get here - ever! */ +; + BKPT 0xEF ; Setup error conditions + BX lr ; +;} +; + +; +; /* Memory Exception Handler. */ +; + EXPORT MemManage_Handler +MemManage_Handler +;{ + CPSID i ; Disable interrupts +; +; /* Now pickup and store all the fault related information. */ +; + LDR r12,=_txm_module_manager_memory_fault_info ; Pickup fault info struct + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup the current thread pointer + STR r1, [r12, #0] ; Save current thread pointer in fault info structure + LDR r0, =0xE000ED24 ; Build SHCSR address + LDR r1, [r0] ; Pickup SHCSR + STR r1, [r12, #8] ; Save SHCSR + LDR r0, =0xE000ED28 ; Build MMFSR address + LDR r1, [r0] ; Pickup MMFSR (and other fault status too!) + STR r1, [r12, #12] ; Save MMFSR + LDR r0, =0xE000ED34 ; Build MMFAR address + LDR r1, [r0] ; Pickup MMFAR + STR r1, [r12, #16] ; Save MMFAR + MRS r0, CONTROL ; Pickup current CONTROL register + STR r0, [r12, #20] ; Save CONTROL + MRS r1, PSP ; Pickup thread stack pointer + STR r1, [r12, #24] ; Save thread stack pointer + LDR r0, [r1] ; Pickup saved r0 + STR r0, [r12, #28] ; Save r0 + LDR r0, [r1, #4] ; Pickup saved r1 + STR r0, [r12, #32] ; Save r1 + STR r2, [r12, #36] ; Save r2 + STR r3, [r12, #40] ; Save r3 + STR r4, [r12, #44] ; Save r4 + STR r5, [r12, #48] ; Save r5 + STR r6, [r12, #52] ; Save r6 + STR r7, [r12, #56] ; Save r7 + STR r8, [r12, #60] ; Save r8 + STR r9, [r12, #64] ; Save r9 + STR r10,[r12, #68] ; Save r10 + STR r11,[r12, #72] ; Save r11 + LDR r0, [r1, #16] ; Pickup saved r12 + STR r0, [r12, #76] ; Save r12 + LDR r0, [r1, #20] ; Pickup saved lr + STR r0, [r12, #80] ; Save lr + LDR r0, [r1, #24] ; Pickup instruction address at point of fault + STR r0, [r12, #4] ; Save point of fault + LDR r0, [r1, #28] ; Pickup xPSR + STR r0, [r12, #84] ; Save xPSR + + MRS r0, CONTROL ; Pickup current CONTROL register + BIC r0, r0, #1 ; Clear the UNPRIV bit + MSR CONTROL, r0 ; Setup new CONTROL register + + LDR r0, =0xE000ED28 ; Build the Memory Management Fault Status Register (MMFSR) + LDRB r1, [r0] ; Pickup the MMFSR, with the following bit definitions: + ; Bit 0 = 1 -> Instruction address violation + ; Bit 1 = 1 -> Load/store address violation + ; Bit 7 = 1 -> MMFAR is valid + STRB r1, [r0] ; Clear the MMFSR + + IF :DEF:__ARMVFP__ + LDR r0, =0xE000EF34 ; Cleanup FPU context: Load FPCCR address + LDR r1, [r0] ; Load FPCCR + BIC r1, r1, #1 ; Clear the lazy preservation active bit + STR r1, [r0] ; Store the value + ENDIF + + BL _txm_module_manager_memory_fault_handler ; Call memory manager fault handler + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + CPSID i ; Disable interrupts + BL _tx_execution_thread_exit ; Call the thread exit function + CPSIE i ; Enable interrupts + ENDIF + + MOV r1, #0 ; Build NULL value + LDR r0, =_tx_thread_current_ptr ; Pickup address of current thread pointer + STR r1, [r0] ; Clear current thread pointer + + ; Return from MemManage_Handler exception + LDR r0, =0xE000ED04 ; Load ICSR + LDR r1, =0x10000000 ; Set PENDSVSET bit + STR r1, [r0] ; Store ICSR + DSB ; Wait for memory access to complete + CPSIE i ; Enable interrupts + MOV lr, #0xFFFFFFFD ; Load exception return code + BX lr ; Return from exception +;} + +; +; /* Generic context PendSV handler. */ +; + EXPORT PendSV_Handler + EXPORT __tx_PendSVHandler +PendSV_Handler +__tx_PendSVHandler +; +; /* Get current thread value and new thread pointer. */ +; +__tx_ts_handler + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + CPSID i ; Disable interrupts + PUSH {r0, lr} ; Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit ; Call the thread exit function + POP {r0, lr} ; Recover LR + CPSIE i ; Enable interrupts + ENDIF + MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address + MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address + MOV r3, #0 ; Build NULL value + LDR r1, [r0] ; Pickup current thread pointer +; +; /* Determine if there is a current thread to finish preserving. */ +; + CBZ r1, __tx_ts_new ; If NULL, skip preservation +; +; /* Recover PSP and preserve current thread context. */ +; + STR r3, [r0] ; Set _tx_thread_current_ptr to NULL + MRS r12, PSP ; Pickup PSP pointer (thread's stack pointer) + STMDB r12!, {r4-r11} ; Save its remaining registers + IF :DEF:__ARMVFP__ + TST LR, #0x10 ; Determine if the VFP extended frame is present + BNE _skip_vfp_save + VSTMDB r12!,{s16-s31} ; Yes, save additional VFP registers +_skip_vfp_save + ENDIF + MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable + STMDB r12!, {LR} ; Save LR on the stack +; +; /* Determine if time-slice is active. If it isn't, skip time handling processing. */ +; + LDR r5, [r4] ; Pickup current time-slice + STR r12, [r1, #8] ; Save the thread stack pointer + CBZ r5, __tx_ts_new ; If not active, skip processing +; +; /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ +; + STR r5, [r1, #24] ; Save current time-slice +; +; /* Clear the global time-slice. */ +; + STR r3, [r4] ; Clear time-slice +; +; +; /* Executing thread is now completely preserved!!! */ +; +__tx_ts_new +; +; /* Now we are looking for a new thread to execute! */ +; + CPSID i ; Disable interrupts + LDR r1, [r2] ; Is there another thread ready to execute? + CBZ r1, __tx_ts_wait ; No, skip to the wait processing +; +; /* Yes, another thread is ready for else, make the current thread the new thread. */ +; + STR r1, [r0] ; Setup the current thread pointer to the new thread + CPSIE i ; Enable interrupts +; +; /* Increment the thread run count. */ +; +__tx_ts_restore + LDR r7, [r1, #4] ; Pickup the current thread run count + MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable + LDR r5, [r1, #24] ; Pickup thread's current time-slice + ADD r7, r7, #1 ; Increment the thread run count + STR r7, [r1, #4] ; Store the new run count +; +; /* Setup global time-slice with thread's current time-slice. */ +; + STR r5, [r4] ; Setup global time-slice + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + PUSH {r0, r1} ; Save r0 and r1 + BL _tx_execution_thread_enter ; Call the thread execution enter function + POP {r0, r1} ; Recover r0 and r1 + ENDIF +; +; /* Restore the thread context and PSP. */ +; + LDR r12, [r1, #8] ; Pickup thread's stack pointer + + MRS r5, CONTROL ; Pickup current CONTROL register + LDR r4, [r1, #0x98] ; Pickup current user mode flag + BIC r5, r5, #1 ; Clear the UNPRIV bit + ORR r4, r4, r5 ; Build new CONTROL register + MSR CONTROL, r4 ; Setup new CONTROL register + + LDR r0, =0xE000ED94 ; Build MPU control reg address + MOV r3, #0 ; Build disable value + STR r3, [r0] ; Disable MPU + LDR r0, [r1, #0x90] ; Pickup the module instance pointer + CBZ r0, skip_mpu_setup ; Is this thread owned by a module? No, skip MPU setup + LDR r1, [r0, #0x64] ; Pickup MPU register[0] + CBZ r1, skip_mpu_setup ; Is protection required for this module? No, skip MPU setup + LDR r1, =0xE000ED9C ; Build address of MPU base register + + ; Use alias registers to quickly load MPU + ADD r0, r0, #100 ; Build address of MPU register start in thread control block + LDM r0!,{r2-r9} ; Load MPU regions 0-3 + STM r1,{r2-r9} ; Store MPU regions 0-3 + LDM r0!,{r2-r9} ; Load MPU regions 4-7 + STM r1,{r2-r9} ; Store MPU regions 4-7 + LDM r0!,{r2-r9} ; Load MPU regions 8-11 + STM r1,{r2-r9} ; Store MPU regions 8-11 + LDM r0!,{r2-r9} ; Load MPU regions 12-15 + STM r1,{r2-r9} ; Store MPU regions 12-15 + LDR r0, =0xE000ED94 ; Build MPU control reg address + MOV r1, #5 ; Build enable value with background region enabled + STR r1, [r0] ; Enable MPU +skip_mpu_setup + LDMIA r12!, {LR} ; Pickup LR + IF :DEF:__ARMVFP__ + TST LR, #0x10 ; Determine if the VFP extended frame is present + BNE _skip_vfp_restore ; If not, skip VFP restore + VLDMIA r12!, {s16-s31} ; Yes, restore additional VFP registers +_skip_vfp_restore + ENDIF + LDMIA r12!, {r4-r11} ; Recover thread's registers + MSR PSP, r12 ; Setup the thread's stack pointer +; +; /* Return to thread. */ +; + BX lr ; Return to thread! +; +; /* The following is the idle wait processing... in this case, no threads are ready for execution and the +; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +; are disabled to allow use of WFI for waiting for a thread to arrive. */ +; +__tx_ts_wait + CPSID i ; Disable interrupts + LDR r1, [r2] ; Pickup the next thread to execute pointer + STR r1, [r0] ; Store it in the current pointer + CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready! + IF :DEF:TX_ENABLE_WFI + DSB ; Ensure no outstanding memory transactions + WFI ; Wait for interrupt + ISB ; Ensure pipeline is flushed + ENDIF + CPSIE i ; Enable interrupts + B __tx_ts_wait ; Loop to continue waiting +; +; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +; already in the handler! */ +; +__tx_ts_ready + MOV r7, #0x08000000 ; Build clear PendSV value + MOV r8, #0xE000E000 ; Build base NVIC address + STR r7, [r8, #0xD04] ; Clear any PendSV +; +; /* Re-enable interrupts and restore new thread. */ +; + CPSIE i ; Enable interrupts + B __tx_ts_restore ; Restore the thread +;} + +; +; /* SVC Handler. */ +; + EXPORT SVC_Handler + EXPORT __tx_SVCallHandler +SVC_Handler +__tx_SVCallHandler +;{ + MRS r0, PSP ; Pickup the PSP stack + LDR r1, [r0, #24] ; Pickup the point of interrupt + LDRB r2, [r1, #-2] ; Pickup the SVC parameter + ; + ; Determine which SVC trap we are processing + ; + CMP r2, #1 ; Is it the entry into ThreadX? + BNE _tx_thread_user_return ; No, return to user mode + ; + ; At this point we have an SVC 1, which means we are entering the kernel from a module thread with user mode selected + ; + LDR r2, =_txm_module_priv ; Subtract 1 because of THUMB mode. + SUB r2, r2, #1 ; Temporary fix until ARM describes how to load label above correctly. + CMP r1, r2 ; Did we come from user_mode_entry? + IT NE ; If no (not equal), then... + BXNE lr ; return from where we came. + + LDR r3, [r0, #20] ; This is the saved LR + LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r2, [r1] ; Pickup current thread pointer + MOV r1, #0 ; Build clear value + STR r1, [r2, #0x98] ; Clear the current user mode selection for thread + STR r3, [r2, #0xA0] ; Save the original LR in thread control block + + ; If there is memory protection, use kernel stack + LDR r0, [r2, #0x90] ; Load the module instance ptr + LDR r0, [r0, #0x0C] ; Load the module property flags + TST r0, #2 ; Check if memory protected + BEQ _tx_skip_kernel_stack_enter + + ; Switch to the module thread's kernel stack + LDR r0, [r2, #0xA8] ; Load the module kernel stack end + IF :LNOT: :DEF:TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r1, [r2, #0xA4] ; Load the module kernel stack start + LDR r3, [r2, #0xAC] ; Load the module kernel stack size + STR r1, [r2, #12] ; Set stack start + STR r0, [r2, #16] ; Set stack end + STR r3, [r2, #20] ; Set stack size + ENDIF + + MRS r3, PSP ; Pickup thread stack pointer + STR r3, [r2, #0xB0] ; Save thread stack pointer + + ; Build kernel stack by copying thread stack two registers at a time + ADD r3, r3, #32 ; start at bottom of hardware stack + LDMDB r3!,{r1-r2} ; + STMDB r0!,{r1-r2} ; + LDMDB r3!,{r1-r2} ; + STMDB r0!,{r1-r2} ; + LDMDB r3!,{r1-r2} ; + STMDB r0!,{r1-r2} ; + LDMDB r3!,{r1-r2} ; + STMDB r0!,{r1-r2} ; + + MSR PSP, r0 ; Set kernel stack pointer + +_tx_skip_kernel_stack_enter + MRS r0, CONTROL ; Pickup current CONTROL register + BIC r0, r0, #1 ; Clear the UNPRIV bit + MSR CONTROL, r0 ; Setup new CONTROL register + BX lr ; Return to thread + +_tx_thread_user_return + + LDR r2, =_txm_module_user_mode_exit ; Subtract 1 because of THUMB mode. + SUB r2, r2, #1 ; Temporary fix until ARM describes how to load label above correctly. + CMP r1, r2 ; Did we come from user_mode_exit? + IT NE ; If no (not equal), then... + BXNE lr ; return from where we came + + LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r2, [r1] ; Pickup current thread pointer + LDR r1, [r2, #0x9C] ; Pick up user mode + STR r1, [r2, #0x98] ; Set the current user mode selection for thread + + ; If there is memory protection, use kernel stack + LDR r0, [r2, #0x90] ; Load the module instance ptr + LDR r0, [r0, #0x0C] ; Load the module property flags + TST r0, #2 ; Check if memory protected + BEQ _tx_skip_kernel_stack_exit + + IF :LNOT: :DEF:TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r0, [r2, #0xB4] ; Load the module thread stack start + LDR r1, [r2, #0xB8] ; Load the module thread stack end + LDR r3, [r2, #0xBC] ; Load the module thread stack size + STR r0, [r2, #12] ; Set stack start + STR r1, [r2, #16] ; Set stack end + STR r3, [r2, #20] ; Set stack size + ENDIF + LDR r0, [r2, #0xB0] ; Load the module thread stack pointer + MRS r3, PSP ; Pickup kernel stack pointer + + ; Copy kernel hardware stack to module thread stack. + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + SUB r0, r0, #32 ; Subtract 32 to get back to top of stack + MSR PSP, r0 ; Set thread stack pointer + + LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r2, [r1] ; Pickup current thread pointer + LDR r1, [r2, #0x9C] ; Pick up user mode + +_tx_skip_kernel_stack_exit + MRS r0, CONTROL ; Pickup current CONTROL register + ORR r0, r0, r1 ; OR in the user mode bit + MSR CONTROL, r0 ; Setup new CONTROL register + BX lr ; Return to thread +;} + + IF :DEF:__ARMVFP__ + AREA ||.text||, CODE, READONLY + EXPORT tx_thread_fpu_enable +tx_thread_fpu_enable +; +; /* Automatic VPF logic is supported, this function is present only for +; backward compatibility purposes and therefore simply returns. */ +; + BX LR ; Return to caller + + EXPORT tx_thread_fpu_disable +tx_thread_fpu_disable +; +; /* Automatic VPF logic is supported, this function is present only for +; backward compatibility purposes and therefore simply returns. */ +; + BX LR ; Return to caller + ENDIF + + +; +; /* Kernel entry function from user mode. */ +; + IMPORT _txm_module_manager_kernel_dispatch +; + AREA ||.text||, CODE, READONLY, ALIGN=5 + THUMB +;VOID _txm_module_manager_user_mode_entry(VOID) +;{ + EXPORT _txm_module_manager_user_mode_entry +_txm_module_manager_user_mode_entry + SVC 1 ; Enter kernel +_txm_module_priv + ; At this point, we are out of user mode. The original LR has been saved in the + ; thread control block. Simply call the kernel dispatch function. + BL _txm_module_manager_kernel_dispatch + + ; Pickup the original LR value while still in privileged mode + LDR r2, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r3, [r2] ; Pickup current thread pointer + LDR lr, [r3, #0xA0] ; Pickup saved LR from original call + + SVC 2 ; Exit kernel and return to user mode +_txm_module_user_mode_exit + BX lr ; Return to the caller + NOP + NOP + NOP + NOP +;} + + END diff --git a/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_stack_build.s new file mode 100644 index 00000000..d24adb08 --- /dev/null +++ b/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_stack_build.s @@ -0,0 +1,129 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-M4/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + EXPORT _tx_thread_stack_build +_tx_thread_stack_build +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-M4 should look like the following after it is built: +; +; Stack Top: +; LR Interrupted LR (LR at time of PENDSV) +; r4 Initial value for r4 +; r5 Initial value for r5 +; r6 Initial value for r6 +; r7 Initial value for r7 +; r8 Initial value for r8 +; r9 Initial value for r9 +; r10 Initial value for r10 +; r11 Initial value for r11 +; r0 Initial value for r0 (Hardware stack starts here!!) +; r1 Initial value for r1 +; r2 Initial value for r2 +; r3 Initial value for r3 +; r12 Initial value for r12 +; lr Initial value for lr +; pc Initial value for pc +; xPSR Initial value for xPSR +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #0x7 ; Align frame for 8-byte alignment + SUB r2, r2, #68 ; Subtract frame size + LDR r3, =0xFFFFFFFD ; Build initial LR value + STR r3, [r2, #0] ; Save on the stack +; +; /* Actually build the stack frame. */ +; + MOV r3, #0 ; Build initial register value + STR r3, [r2, #4] ; Store initial r4 + STR r3, [r2, #8] ; Store initial r5 + STR r3, [r2, #12] ; Store initial r6 + STR r3, [r2, #16] ; Store initial r7 + STR r3, [r2, #20] ; Store initial r8 + STR r3, [r2, #24] ; Store initial r9 + STR r3, [r2, #28] ; Store initial r10 + STR r3, [r2, #32] ; Store initial r11 +; +; /* Hardware stack follows. */ +; + STR r3, [r2, #36] ; Store initial r0 + STR r3, [r2, #40] ; Store initial r1 + STR r3, [r2, #44] ; Store initial r2 + STR r3, [r2, #48] ; Store initial r3 + STR r3, [r2, #52] ; Store initial r12 + MOV r3, #0xFFFFFFFF ; Poison EXC_RETURN value + STR r3, [r2, #56] ; Store initial lr + STR r1, [r2, #60] ; Store initial pc + MOV r3, #0x01000000 ; Only T-bit need be set + STR r3, [r2, #64] ; Store initial xPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block + BX lr ; Return to caller +;} + END + diff --git a/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_system_return.s b/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_system_return.s new file mode 100644 index 00000000..c61d0e53 --- /dev/null +++ b/ports_module/cortex-m7/ac5/module_manager/src/tx_thread_system_return.s @@ -0,0 +1,91 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-M4/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + EXPORT _tx_thread_system_return +_tx_thread_system_return +; +; /* Return to real scheduler via PendSV. Note that this routine is often +; replaced with in-line assembly in tx_port.h to improved performance. */ +; + MOV r0, #0x10000000 ; Load PENDSVSET bit + MOV r1, #0xE000E000 ; Load NVIC base + STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR + MRS r0, IPSR ; Pickup IPSR + CMP r0, #0 ; Is it a thread returning? + BNE _isr_context ; If ISR, skip interrupt enable + MRS r1, PRIMASK ; Thread context returning, pickup PRIMASK + CPSIE i ; Enable interrupts + MSR PRIMASK, r1 ; Restore original interrupt posture +_isr_context + BX lr ; Return to caller +;} + END + diff --git a/ports_module/cortex-m7/ac5/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex-m7/ac5/module_manager/src/tx_timer_interrupt.s new file mode 100644 index 00000000..af94c70c --- /dev/null +++ b/ports_module/cortex-m7/ac5/module_manager/src/tx_timer_interrupt.s @@ -0,0 +1,266 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_timer.h" +;#include "tx_thread.h" +; +; +;Define Assembly language external references... +; + IMPORT _tx_timer_time_slice + IMPORT _tx_timer_system_clock + IMPORT _tx_timer_current_ptr + IMPORT _tx_timer_list_start + IMPORT _tx_timer_list_end + IMPORT _tx_timer_expired_time_slice + IMPORT _tx_timer_expired + IMPORT _tx_thread_time_slice + IMPORT _tx_timer_expiration_process + IMPORT _tx_thread_preempt_disable + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_execute_ptr +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-M4/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + EXPORT _tx_timer_interrupt +_tx_timer_interrupt +; +; /* Upon entry to this routine, it is assumed that context save has already +; been called, and therefore the compiler scratch registers are available +; for use. */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + MOV32 r1, _tx_timer_system_clock ; Pickup address of system clock + LDR r0, [r1, #0] ; Pickup system clock + ADD r0, r0, #1 ; Increment system clock + STR r0, [r1, #0] ; Store new system clock +; +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice + LDR r2, [r3, #0] ; Pickup time-slice + CBZ r2, __tx_timer_no_time_slice ; Is it non-active? + ; Yes, skip time-slice processing +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; + SUB r2, r2, #1 ; Decrement the time-slice + STR r2, [r3, #0] ; Store new time-slice value +; +; /* Check for expiration. */ +; if (__tx_timer_time_slice == 0) +; + CBNZ r2, __tx_timer_no_time_slice ; Has it expired? +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup address of expired flag + MOV r0, #1 ; Build expired value + STR r0, [r3, #0] ; Set time-slice expiration flag +; +; } +; +__tx_timer_no_time_slice +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + MOV32 r1, _tx_timer_current_ptr ; Pickup current timer pointer address + LDR r0, [r1, #0] ; Pickup current timer + LDR r2, [r0, #0] ; Pickup timer list entry + CBZ r2, __tx_timer_no_timer ; Is there anything in the list? + ; No, just increment the timer +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + MOV32 r3, _tx_timer_expired ; Pickup expiration flag address + MOV r2, #1 ; Build expired value + STR r2, [r3, #0] ; Set expired flag + B __tx_timer_done ; Finished timer processing +; +; } +; else +; { +__tx_timer_no_timer +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ADD r0, r0, #4 ; Move to next timer +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + MOV32 r3, _tx_timer_list_end ; Pickup addr of timer list end + LDR r2, [r3, #0] ; Pickup list end + CMP r0, r2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, skip wrap-around logic +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + MOV32 r3, _tx_timer_list_start ; Pickup addr of timer list start + LDR r0, [r3, #0] ; Set current pointer to list start +; +__tx_timer_skip_wrap +; + STR r0, [r1, #0] ; Store new current timer pointer +; } +; +__tx_timer_done +; +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of expired flag + LDR r2, [r3, #0] ; Pickup time-slice expired flag + CBNZ r2, __tx_something_expired ; Did a time-slice expire? + ; If non-zero, time-slice expired + MOV32 r1, _tx_timer_expired ; Pickup addr of other expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CBZ r0, __tx_timer_nothing_expired ; Did a timer expire? + ; No, nothing expired +; +__tx_something_expired +; +; + STMDB sp!, {r0, lr} ; Save the lr register on the stack + ; and save r0 just to keep 8-byte alignment +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + MOV32 r1, _tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CBZ r0, __tx_timer_dont_activate ; Check for timer expiration + ; If not set, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BL _tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r2, [r3, #0] ; Pickup the actual flag + CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set + ; No, skip time-slice processing +; +; /* Time slice interrupted thread. */ +; _tx_thread_time_slice(); + + BL _tx_thread_time_slice ; Call time-slice processing + MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag + LDR r1, [r0] ; Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice ; Yes, skip the PendSV logic + MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup the current thread pointer + MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address + LDR r3, [r2] ; Pickup the execute thread pointer + MOV32 r0, 0xE000ED04 ; Build address of control register + MOV32 r2, 0x10000000 ; Build value for PendSV bit + CMP r1, r3 ; Are they the same? + BEQ __tx_timer_skip_time_slice ; If the same, there was no time-slice performed + STR r2, [r0] ; Not the same, issue the PendSV for preemption +__tx_timer_skip_time_slice +; +; } +; +__tx_timer_not_ts_expiration +; + LDMIA sp!, {r0, lr} ; Recover lr register (r0 is just there for +; +; } +; +__tx_timer_nothing_expired + + DSB ; Complete all memory access + BX lr ; Return to caller +; +;} + ALIGN + LTORG + END + diff --git a/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c new file mode 100644 index 00000000..9d1b0a17 --- /dev/null +++ b/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_alignment_adjust.c @@ -0,0 +1,188 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_power_of_two_block_size Cortex-M7/MPU/AC5 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calculates a power of two size at or immediately above*/ +/* the input size and returns it to the caller. */ +/* */ +/* INPUT */ +/* */ +/* size Block size */ +/* */ +/* OUTPUT */ +/* */ +/* calculated size Rounded up to power of two */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_power_of_two_block_size(ULONG size) +{ + /* Check for 0 size. */ + if(size == 0) + return 0; + + /* Minimum MPU block size is 32. */ + if(size <= 32) + return 32; + + /* Bit twiddling trick to round to next high power of 2 + (if original size is power of 2, it will return original size. Perfect!) */ + size--; + size |= size >> 1; + size |= size >> 2; + size |= size >> 4; + size |= size >> 8; + size |= size >> 16; + size++; + + /* Return a power of 2 size at or above the input size. */ + return(size); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_alignment_adjust Cortex-M7/MPU/AC5 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function adjusts the alignment and size of the code and data */ +/* section for a given module implementation. */ +/* */ +/* INPUT */ +/* */ +/* module_preamble Pointer to module preamble */ +/* code_size Size of the code area (updated) */ +/* code_alignment Code area alignment (updated) */ +/* data_size Size of data area (updated) */ +/* data_alignment Data area alignment (updated) */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_power_of_two_block_size Calculate power of two size */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, + ULONG *code_size, + ULONG *code_alignment, + ULONG *data_size, + ULONG *data_alignment) +{ + +ULONG local_code_size; +ULONG local_code_alignment; +ULONG local_data_size; +ULONG local_data_alignment; +ULONG code_size_accum; +ULONG data_size_accum; + + /* Copy the input parameters into local variables for ease of use. */ + local_code_size = *code_size; + local_code_alignment = *code_alignment; + local_data_size = *data_size; + local_data_alignment = *data_alignment; + + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + local_code_alignment = _txm_power_of_two_block_size(local_code_size) >> 2; + code_size_accum = local_code_alignment + local_code_alignment; + code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); + code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); + local_code_size = code_size_accum; + + /* Determine data block sizes. Minimize the alignment requirement. + There are 4 MPU data entries available. The following is how the data size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to data size. + 2. 1/4 of the largest power of two that is greater than or equal to data size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + local_data_alignment = _txm_power_of_two_block_size(local_data_size) >> 2; + data_size_accum = local_data_alignment + local_data_alignment; + data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); + data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); + local_data_size = data_size_accum; + + /* Return all the information to the caller. */ + *code_size = local_code_size; + *code_alignment = local_code_alignment; + *data_size = local_data_size; + *data_alignment = local_data_alignment; +} + + + diff --git a/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c new file mode 100644 index 00000000..27e2cc34 --- /dev/null +++ b/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_external_memory_enable.c @@ -0,0 +1,195 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_mutex.h" +#include "tx_queue.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_external_memory_enable Cortex-M7/MPU/AC5 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates an entry in the MPU table for a shared */ +/* memory space. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* start_address Start address of memory */ +/* length Length of external memory */ +/* attributes Memory attributes (r/w) */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_mutex_get Get protection mutex */ +/* _tx_mutex_put Release protection mutex */ +/* _txm_power_of_two_block_size Round length to power of two */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, + VOID *start_address, + ULONG length, + UINT attributes) +{ + +ULONG block_size; +ULONG region_size; +ULONG srd_bits; +ULONG size_register; +ULONG address; +ULONG shared_index; +ULONG attributes_check = 0; + + /* Determine if the module manager has been initialized. */ + if (_txm_module_manager_ready != TX_TRUE) + { + + /* Module manager has not been initialized. */ + return(TX_NOT_AVAILABLE); + } + + /* Determine if the module is valid. */ + if (module_instance == TX_NULL) + { + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Get module manager protection mutex. */ + _tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER); + + /* Determine if the module instance is valid. */ + if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) + { + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Determine if the module instance is in the loaded state. */ + if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) + { + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not ready. */ + return(TX_START_ERROR); + } + + /* Determine if there are shared memory entries available. */ + if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) + { + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* No more entries available. */ + return(TX_NO_MEMORY); + } + + /* Start address and length must adhere to Cortex-M7 MPU. + The address must align with the block size. */ + + block_size = _txm_power_of_two_block_size(length); + address = (ULONG) start_address; + if(address != (address & ~(block_size - 1))) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return alignment error. */ + return(TXM_MODULE_ALIGNMENT_ERROR); + } + + /* At this point, we have a valid address and block size. + Set up MPU registers. */ + + /* Pick up index into shared memory entries. */ + shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; + + /* Save address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | 0x10; + + /* Calculate the region size. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Calculate the subregion bits. */ + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); + + /* Generate SRD, size, and enable attributes. */ + size_register = srd_bits | region_size | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; + + /* Check for optional write attribute. */ + if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) + { + attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; + } + + /* Save attribute-size register. */ + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; + + /* Keep track of shared memory address and length in module instance. */ + module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; + module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; + + /* Increment counter. */ + module_instance -> txm_module_instance_shared_memory_count++; + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return success. */ + return(TX_SUCCESS); +} + diff --git a/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c new file mode 100644 index 00000000..35f06b2a --- /dev/null +++ b/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -0,0 +1,114 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + +/* Define a macro that can be used to allocate global variables useful to + store information about the last fault. This macro is defined in + txm_module_port.h and is usually populated in the assembly language + fault handling prior to the code calling _txm_module_manager_memory_fault_handler. */ + +TXM_MODULE_MANAGER_FAULT_INFO + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_handler Cortex-M7/MPU/AC5 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles a fault associated with a memory protected */ +/* module. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_terminate Terminate thread */ +/* */ +/* CALLED BY */ +/* */ +/* Fault handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_memory_fault_handler(VOID) +{ + +TXM_MODULE_INSTANCE *module_instance_ptr; +TX_THREAD *thread_ptr; + + + /* Pickup the current thread. */ + thread_ptr = _tx_thread_current_ptr; + + /* Initialize the module instance pointer to NULL. */ + module_instance_ptr = TX_NULL; + + /* Is there a thread? */ + if (thread_ptr) + { + + /* Pickup the module instance. */ + module_instance_ptr = thread_ptr -> tx_thread_module_instance_ptr; + + /* Terminate the current thread. */ + _tx_thread_terminate(_tx_thread_current_ptr); + } + + /* Determine if there is a user memory fault notification callback. */ + if (_txm_module_manager_fault_notify) + { + + /* Yes, call the user's notification memory fault callback. */ + (_txm_module_manager_fault_notify)(thread_ptr, module_instance_ptr); + } +} + diff --git a/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c new file mode 100644 index 00000000..b9558f19 --- /dev/null +++ b/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -0,0 +1,86 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the external user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_notify Cortex-M7/MPU/AC5 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application callback when/if a memory */ +/* fault occurs. The supplied thread is automatically terminated, but */ +/* any other threads in the same module may still execute. */ +/* */ +/* INPUT */ +/* */ +/* notify_function Memory fault notification */ +/* function, NULL disables. */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +{ + + /* Setup notification function. */ + _txm_module_manager_fault_notify = notify_function; + + /* Return success. */ + return(TX_SUCCESS); +} + diff --git a/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c new file mode 100644 index 00000000..a3847297 --- /dev/null +++ b/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c @@ -0,0 +1,656 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" +#include "txm_module_manager_util.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_region_size_get Cortex-M7/MPU/AC5 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function converts the region size in bytes to the block size */ +/* for the Cortex-M7 MPU specification. */ +/* */ +/* INPUT */ +/* */ +/* block_size Size of the block in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* MPU size specification */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_module_manager_region_size_get(ULONG block_size) +{ + +ULONG return_value; + + + /* Process relative to the input block size. */ + if (block_size == 32) + { + return_value = 0x04; + } + else if (block_size == 64) + { + return_value = 0x05; + } + else if (block_size == 128) + { + return_value = 0x06; + } + else if (block_size == 256) + { + return_value = 0x07; + } + else if (block_size == 512) + { + return_value = 0x08; + } + else if (block_size == 1024) + { + return_value = 0x09; + } + else if (block_size == 2048) + { + return_value = 0x0A; + } + else if (block_size == 4096) + { + return_value = 0x0B; + } + else if (block_size == 8192) + { + return_value = 0x0C; + } + else if (block_size == 16384) + { + return_value = 0x0D; + } + else if (block_size == 32768) + { + return_value = 0x0E; + } + else if (block_size == 65536) + { + return_value = 0x0F; + } + else if (block_size == 131072) + { + return_value = 0x10; + } + else if (block_size == 262144) + { + return_value = 0x11; + } + else if (block_size == 524288) + { + return_value = 0x12; + } + else if (block_size == 1048576) + { + return_value = 0x13; + } + else if (block_size == 2097152) + { + return_value = 0x14; + } + else + { + /* Max 4MB MPU pages for modules. */ + return_value = 0x15; + } + + return(return_value); +} + + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_calculate_srd_bits Cortex-M7/MPU/AC5 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calculates the SRD bits that need to be set to */ +/* protect "length" bytes in a block. */ +/* */ +/* INPUT */ +/* */ +/* block_size Size of the block in bytes */ +/* length Actual length in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* SRD bits to be OR'ed with region attribute register. */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) +{ + +ULONG srd_bits = 0; +UINT srd_bit_index; + + /* length is smaller than block_size, set SRD bits if block_size is 256 or more. */ + if((block_size >= 256) && (length < block_size)) + { + /* Divide block_size by 8 by shifting right 3. Result is size of subregion. */ + block_size = block_size >> 3; + + /* Set SRD index into attribute register. */ + srd_bit_index = 8; + + /* If subregion overlaps length, move to the next subregion. */ + while(length > block_size) + { + length = length - block_size; + srd_bit_index++; + } + /* Check for a portion of code remaining. */ + if(length) + { + srd_bit_index++; + } + + /* Set unused subregion bits. */ + while(srd_bit_index < 16) + { + srd_bits = srd_bits | (0x1 << srd_bit_index); + srd_bit_index++; + } + } + + return(srd_bits); +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_mm_register_setup Cortex-M7/MPU/AC5 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets up the MPU register definitions based on the */ +/* module's memory characteristics. */ +/* MPU layout for the Cortex-M7: */ +/* Entry Description */ +/* 0 Kernel mode entry */ +/* 1 Module code region */ +/* 2 Module code region */ +/* 3 Module code region */ +/* 4 Module code region */ +/* 5 Module data region */ +/* 6 Module data region */ +/* 7 Module data region */ +/* 8 Module data region */ +/* 9 Module shared memory region */ +/* 10 Module shared memory region */ +/* 11 Module shared memory region */ +/* 12 Unused region */ +/* 13 Unused region */ +/* 14 Unused region */ +/* 15 Unused region */ +/* */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* */ +/* OUTPUT */ +/* */ +/* MPU specifications for module in module_instance */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_manager_region_size_get */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_thread_create */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) +{ + +ULONG code_address; +ULONG code_size; +ULONG data_address; +ULONG data_size; +ULONG start_stop_stack_size; +ULONG callback_stack_size; +ULONG block_size; +ULONG region_size; +ULONG srd_bits = 0; +UINT mpu_table_index; +UINT i; + + + /* Setup the first MPU region for kernel mode entry. */ + /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. + Mask address to proper range, region 0, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | 0x10; + /* Set the attributes, size (32 bytes) and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | (_txm_module_manager_region_size_get(32) << 1) | TXM_ENABLE_REGION; + /* End of kernel mode entry setup. */ + + /* Setup code protection. */ + + /* Initialize the MPU table index. */ + mpu_table_index = 1; + + /* Pickup code starting address and actual size. */ + code_address = (ULONG) module_instance -> txm_module_instance_code_start; + code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; + + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + + /* Now loop through to setup MPU protection for the code area. */ + for (i = 0; i < TXM_MODULE_MPU_CODE_ENTRIES; i++) + { + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + if (i < 2) + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + } + + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ + else if (i == 2) + { + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size) >> 1; + } + + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + else + { + /* Calculate remaining space. */ + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | 0x10; + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; + + /* Adjust the code address. */ + code_address = code_address + block_size; + + /* Increment MPU table index. */ + mpu_table_index++; + } + /* End of code protection. */ + + /* Setup data protection. */ + + /* Reset SRD bitfield. */ + srd_bits = 0; + + /* Pickup data starting address and actual size. */ + data_address = (ULONG) module_instance -> txm_module_instance_data_start; + + /* Adjust the size of the module elements to be aligned to the default alignment. We do this + so that when we partition the allocated memory, we can simply place these regions right beside + each other without having to align their pointers. Note this only works when they all have + the same alignment. */ + + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; + start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; + callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; + + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + /* Update the data size to include thread stacks. */ + data_size = data_size + start_stop_stack_size + callback_stack_size; + + /* Determine data block sizes. Minimize the alignment requirement. + There are 4 MPU data entries available. The following is how the data size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to data size. + 2. 1/4 of the largest power of two that is greater than or equal to data size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + + /* Now loop through to setup MPU protection for the data area. */ + for (i = 0; i < TXM_MODULE_MPU_DATA_ENTRIES; i++) + { + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to data size. */ + if (i < 2) + { + block_size = _txm_power_of_two_block_size(data_size) >> 2; + } + + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ + else if (i == 2) + { + /* Subtract (block_size*2) from data_size to calculate remaining space. */ + data_size = data_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(data_size) >> 1; + } + + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + else + { + /* Calculate remaining space. */ + data_size = data_size - block_size; + block_size = _txm_power_of_two_block_size(data_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + } + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | 0x10; + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; + + /* Adjust the data address. */ + data_address = data_address + block_size; + + /* Increment MPU table index. */ + mpu_table_index++; + } + + /* Setup MPU for the remaining regions. */ + while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES) + { + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10; + + /* Increment MPU table index. */ + mpu_table_index++; + } + +} + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_shared_memory_check_outside */ +/* Cortex-M7/MPU/AC5 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks if the specified object is outside shared */ +/* memory. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* obj_ptr Pointer to the object */ +/* obj_size Size of the object */ +/* */ +/* OUTPUT */ +/* */ +/* Whether the object is outside the shared memory region. */ +/* */ +/* CALLS */ +/* */ +/* N/A */ +/* */ +/* CALLED BY */ +/* */ +/* Module dispatch check functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UCHAR _txm_module_manager_shared_memory_check_outside(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) +{ + +UINT shared_memory_index; +UINT num_shared_memory_mpu_entries; +ALIGN_TYPE shared_memory_address_start; +ALIGN_TYPE shared_memory_address_end; + + num_shared_memory_mpu_entries = module_instance -> txm_module_instance_shared_memory_count; + for (shared_memory_index = 0; shared_memory_index < num_shared_memory_mpu_entries; shared_memory_index++) + { + + shared_memory_address_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address[shared_memory_index]; + shared_memory_address_end = shared_memory_address_start + module_instance -> txm_module_instance_shared_memory_length[shared_memory_index]; + + if (TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_EXCLUSIVE(shared_memory_address_start, shared_memory_address_end, + obj_ptr, obj_size)) + { + return(TX_FALSE); + } + } + + return(TX_TRUE); +} + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_shared_memory_check_inside Cortex-M7/MPU/AC5 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks if the specified object is inside shared */ +/* memory. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* obj_ptr Pointer to the object */ +/* obj_size Size of the object */ +/* */ +/* OUTPUT */ +/* */ +/* Whether the object is inside the shared memory region. */ +/* */ +/* CALLS */ +/* */ +/* N/A */ +/* */ +/* CALLED BY */ +/* */ +/* Module dispatch check functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UCHAR _txm_module_manager_shared_memory_check_inside(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) +{ + +UINT shared_memory_index; +UINT num_shared_memory_mpu_entries; +ALIGN_TYPE shared_memory_address_start; +ALIGN_TYPE shared_memory_address_end; + + num_shared_memory_mpu_entries = module_instance -> txm_module_instance_shared_memory_count; + for (shared_memory_index = 0; shared_memory_index < num_shared_memory_mpu_entries; shared_memory_index++) + { + + shared_memory_address_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address[shared_memory_index]; + shared_memory_address_end = shared_memory_address_start + module_instance -> txm_module_instance_shared_memory_length[shared_memory_index]; + + if (TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_EXCLUSIVE(shared_memory_address_start, shared_memory_address_end, + obj_ptr, obj_size)) + { + return(TX_TRUE); + } + } + + return(TX_FALSE); +} + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_shared_memory_check_inside_byte */ +/* Cortex-M7/MPU/AC5 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks if the specified byte is inside shared memory. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* byte_ptr Pointer to the byte */ +/* */ +/* OUTPUT */ +/* */ +/* Whether the byte is inside the shared memory region. */ +/* */ +/* CALLS */ +/* */ +/* N/A */ +/* */ +/* CALLED BY */ +/* */ +/* Module dispatch check functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UCHAR _txm_module_manager_shared_memory_check_inside_byte(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE byte_ptr) +{ + +UINT shared_memory_index; +UINT num_shared_memory_mpu_entries; +ALIGN_TYPE shared_memory_address_start; +ALIGN_TYPE shared_memory_address_end; + + num_shared_memory_mpu_entries = module_instance -> txm_module_instance_shared_memory_count; + for (shared_memory_index = 0; shared_memory_index < num_shared_memory_mpu_entries; shared_memory_index++) + { + + shared_memory_address_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address[shared_memory_index]; + shared_memory_address_end = shared_memory_address_start + module_instance -> txm_module_instance_shared_memory_length[shared_memory_index]; + + if (TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_EXCLUSIVE_BYTE(shared_memory_address_start, shared_memory_address_end, + byte_ptr)) + { + return(TX_TRUE); + } + } + + return(TX_FALSE); +} diff --git a/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_thread_stack_build.s new file mode 100644 index 00000000..995eeb56 --- /dev/null +++ b/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_thread_stack_build.s @@ -0,0 +1,153 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Module Manager */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + AREA ||.text||, CODE, READONLY + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _txm_module_manager_thread_stack_build Cortex-M7/MPU/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread */ +;/* function_ptr Pointer to shell function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +;{ + EXPORT _txm_module_manager_thread_stack_build +_txm_module_manager_thread_stack_build +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-M should look like the following after it is built: +; +; Stack Top: +; LR Interrupted LR (LR at time of PENDSV) +; r4 Initial value for r4 +; r5 Initial value for r5 +; r6 Initial value for r6 +; r7 Initial value for r7 +; r8 Initial value for r8 +; r9 Initial value for r9 +; r10 (sl) Initial value for r10 (sl) +; r11 Initial value for r11 +; r0 Initial value for r0 (Hardware stack starts here!!) +; r1 Initial value for r1 +; r2 Initial value for r2 +; r3 Initial value for r3 +; r12 Initial value for r12 +; lr Initial value for lr +; pc Initial value for pc +; xPSR Initial value for xPSR +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #0x7 ; Align frame + SUB r2, r2, #68 ; Subtract frame size + LDR r3, =0xFFFFFFFD ; Build initial LR value + STR r3, [r2, #0] ; Save on the stack +; +; /* Actually build the stack frame. */ +; + MOV r3, #0 ; Build initial register value + STR r3, [r2, #4] ; Store initial r4 + STR r3, [r2, #8] ; Store initial r5 + STR r3, [r2, #12] ; Store initial r6 + STR r3, [r2, #16] ; Store initial r7 + STR r3, [r2, #20] ; Store initial r8 + LDR r3, [r0, #12] ; Pickup stack starting address + STR r3, [r2, #28] ; Store initial r10 (sl) + MOV r3, #0 ; Build initial register value + STR r3, [r2, #32] ; Store initial r11 +; +; /* Hardware stack follows. / +; + STR r0, [r2, #36] ; Store initial r0, which is the thread control block + + LDR r3, [r0, #8] ; Pickup thread entry info pointer,which is in the stack pointer position of the thread control block. + ; It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this + ; function with the actual, initial stack pointer. + STR r3, [r2, #40] ; Store initial r1, which is the module entry information. + LDR r3, [r3, #8] ; Pickup data base register from the module information + STR r3, [r2, #24] ; Store initial r9 (data base register) + MOV r3, #0 ; Clear r3 again + + STR r3, [r2, #44] ; Store initial r2 + STR r3, [r2, #48] ; Store initial r3 + STR r3, [r2, #52] ; Store initial r12 + MOV r3, #0xFFFFFFFF ; Poison EXC_RETURN value + STR r3, [r2, #56] ; Store initial lr + STR r1, [r2, #60] ; Store initial pc + MOV r3, #0x01000000 ; Only T-bit need be set + STR r3, [r2, #64] ; Store initial xPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block + BX lr ; Return to caller +;} + END + diff --git a/ports_module/cortex-m7/iar/example_build/ThreadX_Modules_Cortex-M7_IAR.pdf b/ports_module/cortex-m7/iar/example_build/ThreadX_Modules_Cortex-M7_IAR.pdf new file mode 100644 index 00000000..315db450 Binary files /dev/null and b/ports_module/cortex-m7/iar/example_build/ThreadX_Modules_Cortex-M7_IAR.pdf differ diff --git a/ports_module/cortex-m7/iar/example_build/azure_rtos.eww b/ports_module/cortex-m7/iar/example_build/azure_rtos.eww new file mode 100644 index 00000000..a979e930 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/azure_rtos.eww @@ -0,0 +1,19 @@ + + + + $WS_DIR$\sample_threadx_module.ewp + + + $WS_DIR$\sample_threadx_module_manager.ewp + + + $WS_DIR$\sample_threadx.ewp + + + $WS_DIR$\tx.ewp + + + $WS_DIR$\txm.ewp + + + diff --git a/ports_module/cortex-m7/iar/example_build/cstartup_M.s b/ports_module/cortex-m7/iar/example_build/cstartup_M.s new file mode 100644 index 00000000..75d9369b --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/cstartup_M.s @@ -0,0 +1,73 @@ + EXTERN __iar_program_start + PUBLIC __vector_table + + SECTION .text:CODE:REORDER(1) + + ;; Keep vector table even if it's not referenced + REQUIRE __vector_table + + THUMB + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec:CODE:NOROOT(2) + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD __Reset_Vector + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + + PUBWEAK NMI_Handler + PUBWEAK HardFault_Handler + PUBWEAK MemManage_Handler + PUBWEAK BusFault_Handler + PUBWEAK UsageFault_Handler + PUBWEAK SVC_Handler + PUBWEAK DebugMon_Handler + PUBWEAK PendSV_Handler + PUBWEAK SysTick_Handler + + SECTION .text:CODE:REORDER:NOROOT(1) + THUMB +__Reset_Vector: + CPSID i ; Disable interrupts + B __iar_program_start + + +NMI_Handler +HardFault_Handler +MemManage_Handler +BusFault_Handler +UsageFault_Handler +SVC_Handler +DebugMon_Handler +PendSV_Handler +SysTick_Handler +Default_Handler +__default_handler + CALL_GRAPH_ROOT __default_handler, "interrupt" + NOCALL __default_handler + B __default_handler + + END diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/board.h b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/board.h new file mode 100644 index 00000000..e30a775d --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/board.h @@ -0,0 +1,763 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \page samv7_Xplained_ultra_board_desc SAM V71 Xplained Ultra - Board + * Description + * + * \section Purpose + * + * This file is dedicated to describe the SAM V71 Xplained Ultra board. + * + * \section Contents + * + * - For SAM V71 Xplained Ultra board information, see + * \subpage samv7_Xplained_ultra_board_info. + * - For operating frequency information, see \subpage samv7_Xplained_ultra_opfreq. + * - For using portable PIO definitions, see \subpage samv7_Xplained_ultra_piodef. + * - For using GMAC PIO definitions, see \subpage samv7_Xplained_ultra_gmac. + * - For using ISI definitions, see \subpage samv7_Xplained_ultra_isi. + * - For on-board memories, see \subpage samv7_Xplained_ultra_mem. + * - Several USB definitions are included here, + * see \subpage samv7_Xplained_ultra_usb. + * - For External components, see \subpage samv7_Xplained_ultra_extcomp. + * - For Individual chip definition, see \subpage samv7_Xplained_ultra_chipdef. + * + * To get more software details and the full list of parameters related to the + * SAM V71 Xplained Ultra board configuration, please have a look at the source + * file: + * \ref board.h\n + * + * \section Usage + * + * - The code for booting the board is provided by board_cstartup_xxx.c and + * board_lowlevel.c. + * - For using board PIOs, board characteristics (clock, etc.) and external + * components, see board.h. + * - For manipulating memories, see board_memories.h. + * + * This file can be used as a template and modified to fit a custom board, with + * specific PIOs usage or memory connections. + */ + +/** + * \file board.h + * + * Definition of SAM V71 Xplained Ultra board characteristics, PIOs and + * external components interface. + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include "include/board_lowlevel.h" +#include "include/board_memories.h" +#include "include/led.h" +#include "include/gmii.h" +#include "include/gmacb_phy.h" +#include "include/dbg_console.h" +#include "include/bmp.h" +#include "include/lcdd.h" +#include "include/ili9488.h" +#include "include/ili9488_reg.h" +#include "include/ili9488_spi.h" +#include "include/ili9488_ebi.h" +#include "include/ili9488_dma.h" +#include "include/ili9488_spi_dma.h" +#include "include/ili9488_ebi_dma.h" +#include "include/frame_buffer.h" +#include "include/lcd_color.h" +#include "include/lcd_draw.h" +#include "include/lcd_font10x14.h" +#include "include/lcd_font.h" +#include "include/lcd_gimp_image.h" +#include "include/rtc_calib.h" +#include "include/wm8904.h" +#include "include/cs2100.h" +#include "include/s25fl1.h" +#include "include/image_sensor_inf.h" +#include "include/iso7816_4.h" + +#if defined ( __GNUC__ ) +#include "include/syscalls.h" +#endif +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------*/ +/** + * \page samv7_Xplained_ultra_board_info "SAM V71 Xplained Ultra - Board informations" + * This page lists several definition related to the board description. + * + * \section Definitions + * - \ref BOARD_NAME + */ + +/** Name of the board */ +#define BOARD_NAME "SAM V71 Xplained Ultra" +#define NO_PUSHBUTTON +/*----------------------------------------------------------------------------*/ +/** + * \page samv7_Xplained_ultra_opfreq "SAM V71 Xplained Ultra - Operating frequencies" + * This page lists several definition related to the board operating frequency + * (when using the initialization done by board_lowlevel.c). + * + * \section Definitions + * - \ref BOARD_MAINOSC + * - \ref BOARD_MCK + */ + +/** Frequency of the board main oscillator */ +#define BOARD_MAINOSC 12000000 + +/** Master clock frequency (when using board_lowlevel.c) */ + +#ifdef MCK_123MHZ +#define BOARD_MCK 123000000 +#else +#define BOARD_MCK 150000000 +#endif + +#if (BOARD_MCK==132000000 ) + +#define PLL_MUL 0x16 +#define PLL_DIV 0x01 + +#else // 300MHz(PCK) and 150MHz(MCK) by default + +#define PLL_MUL 0x19 +#define PLL_DIV 0x01 + +#endif + +/*----------------------------------------------------------------------------*/ +/** + * \page samv7_Xplained_ultra_piodef "SAM V71 Xplained Ultra - PIO definitions" + * This pages lists all the PIOs definitions contained in board.h. The constants + * are named using the following convention: PIN_* for a constant which defines + * a single Pin instance (but may include several PIOs sharing the same + * controller), and PINS_* for a list of Pin instances. + * + * UART0 + * - \ref PINS_UART0 + * + * UART4 + * - \ref PINS_UART4 + * + * LEDs + * - \ref PIN_LED_0 + * - \ref PIN_LED_1 + * - \ref PINS_LEDS + * + * Push buttons + * - \ref PIN_PUSHBUTTON_0 + * - \ref PIN_PUSHBUTTON_1 + * - \ref PINS_PUSHBUTTONS + * - \ref PUSHBUTTON_BP0 + * - \ref PUSHBUTTON_BP1 + * + * PWMC + * - \ref PIN_PWMC_PWMH0 + * - \ref PIN_PWMC_PWMH1 + * - \ref PIN_PWM_LED0 + * - \ref PIN_PWM_LED1 + * - \ref CHANNEL_PWM_LED0 + * - \ref CHANNEL_PWM_LED1 + * + * SPI + * - \ref PIN_SPI_MISO + * - \ref PIN_SPI_MOSI + * - \ref PIN_SPI_SPCK + * - \ref PINS_SPI + * + * PCK0 + * - \ref PIN_PCK0 + * - \ref PIN_PCK1 + * - \ref PIN_PCK2 + * + * PIO PARALLEL CAPTURE + * - \ref PIN_PIODCEN1 + * - \ref PIN_PIODCEN2 + * + * TWI + * - \ref TWI_V3XX + * - \ref PIN_TWI_TWD0 + * - \ref PIN_TWI_TWCK0 + * - \ref PINS_TWI0 + * - \ref PIN_TWI_TWD1 + * - \ref PIN_TWI_TWCK1 + * - \ref PINS_TWI1 + * + * USART0 + * - \ref PIN_USART0_RXD + * - \ref PIN_USART0_TXD + * - \ref PIN_USART0_CTS + * - \ref PIN_USART0_RTS + * - \ref PIN_USART0_SCK + * + * USART1 + * - \ref PIN_USART1_RXD + * - \ref PIN_USART1_TXD + * - \ref PIN_USART1_CTS + * - \ref PIN_USART1_RTS + * - \ref PIN_USART1_SCK + * + * USART2 + * - \ref PIN_USART2_RXD + * - \ref PIN_USART2_TXD + * - \ref PIN_USART2_CTS + * - \ref PIN_USART2_RTS + * - \ref PIN_USART2_SCK + * + * SSC + * - \ref PIN_SSC_TD + * - \ref PIN_SSC_TK + * - \ref PIN_SSC_TF + * - \ref PIN_SSC_RD + * - \ref PIN_SSC_RK + * - \ref PIN_SSC_RF + * - \ref PIN_SSC_TD + * - \ref PINS_SSC_CODEC + * + * MCAN + * - \ref PIN_MCAN0_TXD + * - \ref PIN_MCAN0_RXD + * - \ref PIN_MCAN1_TXD + * - \ref PIN_MCAN1_RXD + */ + +/** SSC pin Transmitter Data (TD) */ +#define PIN_SSC_TD {PIO_PD26B_TD, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +/** SSC pin Transmitter Clock (TK) */ +#define PIN_SSC_TK {PIO_PB1D_TK, PIOB, ID_PIOB, PIO_PERIPH_D, PIO_DEFAULT} +/** SSC pin Transmitter FrameSync (TF) */ +#define PIN_SSC_TF {PIO_PB0D_TF, PIOB, ID_PIOB, PIO_PERIPH_D, PIO_DEFAULT} +/** SSC pin RD */ +#define PIN_SSC_RD {PIO_PA10C_RD, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_DEFAULT} +/** SSC pin RK */ +#define PIN_SSC_RK {PIO_PA22A_RK, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/** SSC pin RF */ +#define PIN_SSC_RF {PIO_PD24B_RF, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} + +/** SSC pins definition for codec. */ +#define PINS_SSC_CODEC \ + {PIN_SSC_TD, PIN_SSC_TK, PIN_SSC_TF, PIN_SSC_RD, PIN_SSC_RK, PIN_SSC_RF} + +/** UART pins (UTXD0 and URXD0) definitions, PA9,10. */ +#define PINS_UART0 \ + {PIO_PA9A_URXD0 | PIO_PA10A_UTXD0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/** UART pins (UTXD4 and URXD4) definitions, PD19,18. */ +#define PINS_UART4 \ + {PIO_PD18C_URXD4 | PIO_PD19C_UTXD4, PIOD, ID_PIOD, PIO_PERIPH_C, PIO_DEFAULT} + +/* LED pins definitions */ +#define LED_YELLOW0 0 +#define LED_YELLOW1 1 + +/** LED #0 pin definition (YELLOW). */ +#define PIN_LED_0 {PIO_PA23, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT} +/** LED #0 pin definition (YELLOW). */ +#define PIN_LED_1 {PIO_PC9, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} + +/** List of all LEDs definitions. */ +#define PINS_LEDS {PIN_LED_0, PIN_LED_1} + +/** + * Push button #0 definition. + * Attributes = pull-up + debounce + interrupt on rising edge. + */ +#define PIN_PUSHBUTTON_0 \ + {PIO_PA9, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE} +/** + * Push button #1 definition. + * Attributes = pull-up + debounce + interrupt on rising edge. + */ +#define PIN_PUSHBUTTON_1 \ + {PIO_PB12, PIOB, ID_PIOB, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE} + +/** List of all push button definitions. */ +#define PINS_PUSHBUTTONS {PIN_PUSHBUTTON_0, PIN_PUSHBUTTON_1} + +/** Push button #0 index. */ +#define PUSHBUTTON_BP0 0 +/** Push button #1 index. */ +#define PUSHBUTTON_BP1 1 + +/** PWMC PWM0 pin definition: Output High. */ +#define PIN_PWMC_PWMH0 {PIO_PD20A_PWMH0, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT} +/** PWMC PWM1 pin definition: Output High. */ +#define PIN_PWMC_PWMH1 {PIO_PD21A_PWMH1, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT} +/** PWM pins definition for LED0 */ +#define PIN_PWM_LED0 PIN_PWMC_PWMH0 +/** PWM pins definition for LED1 */ +#define PIN_PWM_LED1 PIN_PWMC_PWMH1 +/** PWM channel for LED0 */ +#define CHANNEL_PWM_LED0 0 +/** PWM channel for LED1 */ +#define CHANNEL_PWM_LED1 1 + +/** SPI MISO pin definition. */ +#define PIN_SPI_MISO {PIO_PD20B_SPI0_MISO, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +/** SPI MOSI pin definition. */ +#define PIN_SPI_MOSI {PIO_PD21B_SPI0_MOSI, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +/** SPI SPCK pin definition. */ +#define PIN_SPI_SPCK {PIO_PD22B_SPI0_SPCK, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +/** SPI chip select pin definition. */ +#define PIN_SPI_NPCS0 {PIO_PB2D_SPI0_NPCS0, PIOB, ID_PIOB, PIO_PERIPH_D, PIO_DEFAULT} +#define PIN_SPI_NPCS1 {PIO_PD25B_SPI0_NPCS1, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +#define PIN_SPI_NPCS3 {PIO_PD27B_SPI0_NPCS3, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} + +/** List of SPI pin definitions (MISO, MOSI & SPCK). */ +#define PINS_SPI PIN_SPI_MISO, PIN_SPI_MOSI, PIN_SPI_SPCK + +/** PCK0 */ +#define PIN_PCK0 {PIO_PB13B_PCK0, PIOB, ID_PIOB, PIO_PERIPH_B, PIO_DEFAULT} +/** PCK1 */ +#define PIN_PCK1 {PIO_PA17B_PCK1, PIOB, ID_PIOB, PIO_PERIPH_B, PIO_DEFAULT} +/** PCK2 */ +#define PIN_PCK2 {PIO_PA18B_PCK2, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT} + + +/** PIO PARALLEL CAPTURE */ +/** Parallel Capture Mode Data Enable1 */ +#define PIN_PIODCEN1 PIO_PA15 +/** Parallel Capture Mode Data Enable2 */ +#define PIN_PIODCEN2 PIO_PA16 + +/** TWI version 3.xx */ +#define TWI_V3XX +/** TWI0 data pin */ +#define PIN_TWI_TWD0 {PIO_PA3A_TWD0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/** TWI0 clock pin */ +#define PIN_TWI_TWCK0 {PIO_PA4A_TWCK0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/** TWI0 pins */ +#define PINS_TWI0 {PIN_TWI_TWD0, PIN_TWI_TWCK0} + +/** TWI1 data pin */ +#define PIN_TWI_TWD1 {PIO_PB4A_TWD1, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT} +/** TWI1 clock pin */ +#define PIN_TWI_TWCK1 {PIO_PB5A_TWCK1, PIOB, ID_PIOB, PIO_PERIPH_A,PIO_DEFAULT} +/** TWI1 pins */ +#define PINS_TWI1 {PIN_TWI_TWD1, PIN_TWI_TWCK1} + +/** USART0 pin RX */ +#define PIN_USART0_RXD {PIO_PB0C_RXD0, PIOB, ID_PIOB, PIO_PERIPH_C, PIO_DEFAULT} +/** USART0 pin TX */ +#define PIN_USART0_TXD {PIO_PB1C_TXD0, PIOB, ID_PIOB, PIO_PERIPH_C, PIO_DEFAULT} +/** USART0 pin CTS */ +#define PIN_USART0_CTS {PIO_PB2C_CTS0, PIOB, ID_PIOB, PIO_PERIPH_C, PIO_DEFAULT} +/** USART0 pin RTS */ +#define PIN_USART0_RTS {PIO_PB3C_RTS0, PIOB, ID_PIOB, PIO_PERIPH_C, PIO_DEFAULT} +/** USART0 pin SCK */ +#define PIN_USART0_SCK {PIO_PB13C_SCK0, PIOB, ID_PIOB, PIO_PERIPH_C,PIO_DEFAULT} + +/** USART1 pin RX */ +#define PIN_USART1_RXD {PIO_PA21A_RXD1, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/** USART1 pin TX */ +#define PIN_USART1_TXD {PIO_PB4D_TXD1, PIOB, ID_PIOB, PIO_PERIPH_D, PIO_DEFAULT} +/** USART1 pin CTS */ +#define PIN_USART1_CTS {PIO_PA25A_CTS1, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/** USART1 pin RTS */ +#define PIN_USART1_RTS {PIO_PA24A_RTS1, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/** USART1 pin ENABLE */ +#define PIN_USART1_EN {PIO_PA23A_SCK1, PIOA, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT} +/** USART1 pin SCK */ +#define PIN_USART1_SCK {PIO_PA23A_SCK1, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} + +/** USART2 pin RX */ +#define PIN_USART2_RXD {PIO_PD15B_RXD2, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +/** USART2 pin TX */ +#define PIN_USART2_TXD {PIO_PD16B_TXD2, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +/** USART2 pin CTS */ +#define PIN_USART2_CTS {PIO_PD19B_CTS2, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +/** USART2 pin RTS */ +#define PIN_USART2_RTS {PIO_PD18B_RTS2, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +/** USART2 pin SCK */ +#define PIN_USART2_SCK {PIO_PD17B_SCK2, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} + +/*Pins for USART0 as 7816 mode*/ +/** PIN used for reset the smartcard */ +#define PIN_ISO7816_RSTMC {PIO_PB2C_CTS0, PIOB, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT} +/** Pins used for connect the smartcard */ +#define PINS_ISO7816 PIN_USART0_TXD, PIN_USART0_SCK,PIN_ISO7816_RSTMC + +/** MCAN0 pin Transmit Data (TXD) */ +#define PIN_MCAN0_TXD {PIO_PB2A_CANTX0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/** MCAN0 pin Receive Data (RXD) */ +#define PIN_MCAN0_RXD {PIO_PB3A_CANRX0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} + +/** MCAN1 pin Transmit Data (TXD) */ +#define PIN_MCAN1_TXD {PIO_PC14C_CANTX1, PIOC, ID_PIOC, PIO_PERIPH_C, PIO_DEFAULT} +/** MCAN1 pin Receive Data (RXD) */ +#define PIN_MCAN1_RXD {PIO_PC12C_CANRX1, PIOC, ID_PIOC, PIO_PERIPH_C, PIO_DEFAULT} + +/*----------------------------------------------------------------------------*/ +/** + * \page samv7_Xplained_ultra_gmac "SAM V71 Xplained Ultra - GMAC" + * \section GMAC + * - \ref BOARD_GMAC_PHY_ADDR + * - \ref BOARD_GMAC_PHY_COMP_KSZ8061RNB + * - \ref BOARD_GMAC_MODE_RMII + * - \ref BOARD_GMAC_PINS + * - \ref BOARD_GMAC_RESET_PIN + * + */ +/** PHY address */ +#define BOARD_GMAC_PHY_ADDR 1 +/** PHY Component */ +#define BOARD_GMAC_PHY_COMP_KSZ8061RNB 1 +/** Board GMAC power control - ALWAYS ON */ +#define BOARD_GMAC_POWER_ALWAYS_ON +/** Board GMAC work mode - RMII/MII ( 1 / 0 ) */ +#define BOARD_GMAC_MODE_RMII 1 + +/** The PIN list of PIO for GMAC */ +#define BOARD_GMAC_PINS \ + { (PIO_PD0A_GTXCK | PIO_PD1A_GTXEN | PIO_PD2A_GTX0 | PIO_PD3A_GTX1 \ + | PIO_PD4A_GRXDV | PIO_PD5A_GRX0 | PIO_PD6A_GRX1 | PIO_PD7A_GRXER \ + | PIO_PD8A_GMDC | PIO_PD9A_GMDIO ),PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT}, \ + {PIO_PC30, PIOC, ID_PIOC, PIO_INPUT, PIO_PULLUP},\ + {PIO_PA29, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT} + +/** The PIN list of PIO for GMAC */ +#define BOARD_GMAC_RESET_PIN {PIO_PC10, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_PULLUP} + +/** The runtime pin configure list for GMAC */ +#define BOARD_GMAC_RUN_PINS BOARD_GMAC_PINS + + +/*----------------------------------------------------------------------------*/ +/** + * \page samv7_Xplained_ultra_isi "SAM V71 Xplained Ultra - ISI" + * This page lists all the IO definitions connected to ISI module. + * ISI + * - \ref PIN_ISI_D0 + * - \ref PIN_ISI_D1 + * - \ref PIN_ISI_D2 + * - \ref PIN_ISI_D3 + * - \ref PIN_ISI_D4 + * - \ref PIN_ISI_D5 + * - \ref PIN_ISI_D6 + * - \ref PIN_ISI_D7 + * - \ref PIN_ISI_D8 + * - \ref PIN_ISI_D9 + * - \ref BOARD_ISI_VSYNC + * - \ref BOARD_ISI_HSYNC + * - \ref BOARD_ISI_PCK + * - \ref BOARD_ISI_PINS + * + */ +#define PIN_ISI_D0 {PIO_PD22D_ISI_D0, PIOD, ID_PIOD, PIO_PERIPH_D, PIO_PULLUP} +#define PIN_ISI_D1 {PIO_PD21D_ISI_D1, PIOD, ID_PIOD, PIO_PERIPH_D, PIO_PULLUP} +#define PIN_ISI_D2 {PIO_PB3D_ISI_D2, PIOB, ID_PIOB, PIO_PERIPH_D, PIO_PULLUP} +#define PIN_ISI_D3 {PIO_PA9B_ISI_D3, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_PULLUP} +#define PIN_ISI_D4 {PIO_PA5B_ISI_D4, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_PULLUP} +#define PIN_ISI_D5 {PIO_PD11D_ISI_D5, PIOD, ID_PIOD, PIO_PERIPH_D, PIO_PULLUP} +#define PIN_ISI_D6 {PIO_PD12D_ISI_D6, PIOD, ID_PIOD, PIO_PERIPH_D, PIO_PULLUP} +#define PIN_ISI_D7 {PIO_PA27D_ISI_D7, PIOA, ID_PIOA, PIO_PERIPH_D, PIO_PULLUP} +#define PIN_ISI_D8 {PIO_PD27D_ISI_D8, PIOD, ID_PIOD, PIO_PERIPH_D, PIO_PULLUP} +#define PIN_ISI_D9 {PIO_PD28D_ISI_D9, PIOD, ID_PIOD, PIO_PERIPH_D, PIO_PULLUP} + +#define BOARD_ISI_VSYNC {PIO_PD25D_ISI_VSYNC, PIOD, ID_PIOD, PIO_PERIPH_D, PIO_DEFAULT} +#define BOARD_ISI_HSYNC {PIO_PD24D_ISI_HSYNC, PIOD, ID_PIOD, PIO_PERIPH_D, PIO_DEFAULT} +#define BOARD_ISI_PCK {PIO_PA24D_ISI_PCK, PIOA, ID_PIOA, PIO_PERIPH_D, PIO_DEFAULT} + +#define BOARD_ISI_PCK0 { PIO_PA6B_PCK0, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT } +#define BOARD_ISI_RST { 1 << 13, PIOB, ID_PIOB, PIO_OUTPUT_1, PIO_DEFAULT } +#define BOARD_ISI_PWD { 1 << 19, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT } + +#define BOARD_ISI_PINS \ + PIN_ISI_D0, PIN_ISI_D1, PIN_ISI_D2,PIN_ISI_D3,PIN_ISI_D4, PIN_ISI_D5,\ + PIN_ISI_D6,PIN_ISI_D7,PIN_ISI_D8, PIN_ISI_D9,BOARD_ISI_VSYNC ,\ + BOARD_ISI_HSYNC ,BOARD_ISI_PCK, BOARD_ISI_RST, BOARD_ISI_PWD,BOARD_ISI_PCK0 + +/*----------------------------------------------------------------------------*/ +/** + * \page samv7_Xplained_ultra_usb "SAM V71 Xplained Ultra - USB device" + * + * \section Definitions + * - \ref BOARD_USB_BMATTRIBUTES + * + * \section vBus + * - \ref PIN_USB_VBUS + * + */ + +/** + * USB attributes configuration descriptor (bus or self powered, + * remote wakeup) + */ +#define BOARD_USB_BMATTRIBUTES USBConfigurationDescriptor_SELFPOWERED_NORWAKEUP + +/** USB VBus monitoring pin definition. */ +#define PIN_USB_VBUS {PIO_PC16, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} + + +/*----------------------------------------------------------------------------*/ +/** + * \page samv7_Xplained_ultra_extcomp "SAM V71 Xplained Ultra - External components" + * This page lists the definitions related to external on-board components + * located in the board.h file for the SAM V71 Xplained Ultra board. + * + * LCD + */ +/** Indicates board has an ILI9325 external component to manage LCD. */ +#define BOARD_LCD_ILI9488 +//#define BOARD_LCD_SPI_EXT1 +#define BOARD_LCD_SPI_EXT2 + +/** SPI pin definition for LCD */ +#if defined (BOARD_LCD_SPI_EXT1) +/** SPI MISO pin definition. */ +#define LCD_SPI_MISO {PIO_PD20B_SPI0_MISO, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +/** SPI MOSI pin definition. */ +#define LCD_SPI_MOSI {PIO_PD21B_SPI0_MOSI, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +/** SPI SPCK pin definition. */ +#define LCD_SPI_SPCK {PIO_PD22B_SPI0_SPCK, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +/** SPI chip select pin definition. */ +#define LCD_SPI_NPCS {PIO_PD27B_SPI0_NPCS3, PIOD, ID_PIOD, PIO_PERIPH_B,PIO_DEFAULT} + +/** SPI chip select pin definition. */ +#define LCD_SPI_NPCS {PIO_PD25B_SPI0_NPCS1, PIOD, ID_PIOD, PIO_PERIPH_B,PIO_DEFAULT} + +/** LCD pins definition. */ +#define BOARD_SPI_LCD_PINS {LCD_SPI_MISO, LCD_SPI_MOSI, LCD_SPI_SPCK, LCD_SPI_NPCS} + +/** Back-light pin definition. */ + +#define BOARD_SPI_LCD_BACKLIGHT_PIN \ + {PIO_PA0A_PWMC0_PWMH0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} + +/** PWMC PWM0 pin definition: Output Low. */ +#define LCD_SPI_PIN_RESET {PIO_PD28, PIOD, ID_PIOD, PIO_OUTPUT_1, PIO_DEFAULT} + +/** PWM channel for LED0 */ +#define CHANNEL_PWM_LCD 0 + +#endif +/*ENDIF BOARD_LCD_SPI_EXT1 */ + +#if defined (BOARD_LCD_SPI_EXT2) + /** SPI MISO pin definition. */ +#define LCD_SPI_MISO {PIO_PD20B_SPI0_MISO, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +/** SPI MOSI pin definition. */ +#define LCD_SPI_MOSI {PIO_PD21B_SPI0_MOSI, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +/** SPI SPCK pin definition. */ +#define LCD_SPI_SPCK {PIO_PD22B_SPI0_SPCK, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +/** SPI chip select pin definition. */ +#define LCD_SPI_NPCS {PIO_PD27B_SPI0_NPCS3, PIOD, ID_PIOD, PIO_PERIPH_B,PIO_DEFAULT} + +/** LCD pins definition. */ +#define BOARD_SPI_LCD_PINS {LCD_SPI_MISO, LCD_SPI_MOSI, LCD_SPI_SPCK, LCD_SPI_NPCS} + +/** Back-light pin definition. */ + +#define BOARD_SPI_LCD_PIN_BACKLIGHT \ + {PIO_PC19B_PWMC0_PWMH2, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} + +/** PWMC PWM0 pin definition: Output Low. */ +#define LCD_SPI_PIN_RESET {PIO_PA24, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT} + +/** LCD command/data select pin */ +#define BOARD_SPI_LCD_PIN_CDS {PIO_PA6, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT} + +/** PWM channel for LED0 */ +#define CHANNEL_PWM_LCD 2 + +#endif +/*ENDIF BOARD_LCD_SPI_EXT2 */ + +/** SMC pin definition for LCD */ +/** LCD data pin */ +#define PIN_EBI_LCD_DATAL {0xFF, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} +#define PIN_EBI_LCD_DATAH_0 {0x3F, PIOE, ID_PIOE, PIO_PERIPH_A, PIO_PULLUP} +#define PIN_EBI_LCD_DATAH_1 {PIO_PA15A_D14|PIO_PA16A_D15, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_PULLUP} +/** LCD WE pin */ +#define PIN_EBI_LCD_NWE {PIO_PC8A_NWE, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} +/** LCD RD pin */ +#define PIN_EBI_LCD_NRD {PIO_PC11A_NRD, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} +/* LCD CS pin (NCS3) */ +#define PIN_EBI_LCD_CS {PIO_PD19A_NCS3, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_PULLUP} +/** LCD command/data select pin */ +#define BOARD_EBI_LCD_PIN_CDS {PIO_PC30, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} +/** Back-light pin definition. */ +#define BOARD_EBI_LCD_PIN_BACKLIGHT {PIO_PC9B_TIOB7, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} +/** LCD reset pin */ +#define LCD_EBI_PIN_RESET {PIO_PC13, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} + +/** LCD pins definition. */ +#define BOARD_EBI_LCD_PINS \ + {PIN_EBI_LCD_DATAL, PIN_EBI_LCD_DATAH_0, PIN_EBI_LCD_DATAH_1, \ + PIN_EBI_LCD_NWE,PIN_EBI_LCD_NRD,PIN_EBI_LCD_CS} + + +/** Display width in pixels. */ +#define BOARD_LCD_WIDTH 320 +/** Display height in pixels. */ +#define BOARD_LCD_HEIGHT 480 + + +/*----------------------------------------------------------------------------*/ +/** + * \page samv7_Xplained_ultra_mem "SAM V71 Xplained Ultra - Memories" + * This page lists definitions related to internal & external on-board memories. + * \section SDRAM + * - \ref PIN_SDRAM_D0_7 + * - \ref PIN_SDRAM_D8_13 + * - \ref PIN_SDRAM_D14_15 + * - \ref PIN_SDRAM_A0_9 + * - \ref PIN_SDRAM_SDA10 + * - \ref PIN_SDRAM_CAS + * - \ref PIN_SDRAM_RAS + * - \ref PIN_SDRAM_SDCKE + * - \ref PIN_SDRAM_SDCK + * - \ref PIN_SDRAM_SDSC + * - \ref PIN_SDRAM_NBS0 + * - \ref PIN_SDRAM_NBS1 + * - \ref PIN_SDRAM_SDWE + * - \ref PIN_SDRAM_BA0 + * + * \section SDMMC + * - \ref BOARD_MCI_PIN_CD + * - \ref BOARD_MCI_PIN_CK + * - \ref BOARD_MCI_PINS_SLOTA + * - \ref BOARD_SD_PINS + * + * \section QSPI + * - \ref PINS_QSPI_IO + * - \ref PINS_QSPI_IO3 + * - \ref PINS_QSPI + */ + +/** List of all SDRAM pin definitions. */ +#define BOARD_SDRAM_SIZE (2*1024*1024) +#define PIN_SDRAM_D0_7 {0x000000FF, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_SDRAM_D8_13 {0x0000003F, PIOE, ID_PIOE, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_SDRAM_D14_15 {0x00018000, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_SDRAM_A0_9 {0x3FF00000, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_SDRAM_SDA10 {0x00002000, PIOD, ID_PIOD, PIO_PERIPH_C, PIO_DEFAULT} + +#define PIN_SDRAM_CAS {0x00020000, PIOD, ID_PIOD, PIO_PERIPH_C, PIO_DEFAULT} +#define PIN_SDRAM_RAS {0x00010000, PIOD, ID_PIOD, PIO_PERIPH_C, PIO_DEFAULT} +#define PIN_SDRAM_SDCKE {0x00004000, PIOD, ID_PIOD, PIO_PERIPH_C, PIO_DEFAULT} +#define PIN_SDRAM_SDCK {0x00800000, PIOD, ID_PIOD, PIO_PERIPH_C, PIO_DEFAULT} +#define PIN_SDRAM_SDSC {0x00008000, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_SDRAM_NBS0 {0x00040000, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_SDRAM_NBS1 {0x00008000, PIOD, ID_PIOD, PIO_PERIPH_C, PIO_DEFAULT} +#define PIN_SDRAM_SDWE {0x20000000, PIOD, ID_PIOD, PIO_PERIPH_C, PIO_DEFAULT} +#define PIN_SDRAM_BA0 {0x00100000, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_DEFAULT} + +#define BOARD_SDRAM_PINS PIN_SDRAM_D0_7, PIN_SDRAM_D8_13 , PIN_SDRAM_D14_15,\ + PIN_SDRAM_A0_9, PIN_SDRAM_SDA10, PIN_SDRAM_BA0, \ + PIN_SDRAM_CAS, PIN_SDRAM_RAS, PIN_SDRAM_SDCKE,PIN_SDRAM_SDCK,\ + PIN_SDRAM_SDSC,PIN_SDRAM_NBS0 ,PIN_SDRAM_NBS1,PIN_SDRAM_SDWE + + +/** List of all MCI pin definitions. */ + +/** MCI0 Card detect pin definition. (PE5) */ +#define BOARD_MCI_PIN_CD {PIO_PD18, PIOD, ID_PIOD, PIO_INPUT, PIO_PULLUP} +/** MCI0 Clock . */ +#define BOARD_MCI_PIN_CK {PIO_PA25D_MCCK, PIOA, ID_PIOA, PIO_PERIPH_D, PIO_DEFAULT} + +/** MCI0 Solt A IO pins definition. (PC4-PC13) */ +#define BOARD_MCI_PINS_SLOTA \ + {(PIO_PA30C_MCDA0 | PIO_PA31C_MCDA1 | PIO_PA26C_MCDA2 | PIO_PA27C_MCDA3 | PIO_PA28C_MCCDA),\ + PIOA, ID_PIOA, PIO_PERIPH_C, PIO_DEFAULT} + +/** MCI pins that shall be configured to access the SD card. */ +#define BOARD_SD_PINS {BOARD_MCI_PINS_SLOTA, BOARD_MCI_PIN_CK} +/** MCI Card Detect pin. */ +#define BOARD_SD_PIN_CD BOARD_MCI_PIN_CD + /** Total number of MCI interface */ +#define BOARD_NUM_MCI 1 + +/** List of all SQPI pin definitions. */ +#define PINS_QSPI_IO \ + {(PIO_PA11A_QCS | PIO_PA13A_QIO0 | PIO_PA12A_QIO1 | PIO_PA17A_QIO2 | PIO_PA14A_QSCK),\ + PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PINS_QSPI_IO3 {PIO_PD31A_QIO3, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT} +#define PINS_QSPI {PINS_QSPI_IO, PINS_QSPI_IO3} + +/*----------------------------------------------------------------------------*/ +/** + * \page samv7_Xplained_ultra_chipdef "SAM V71 Xplained Ultra - Individual chip definition" + * This page lists the definitions related to different chip's definition + * + * \section USART + * - \ref BOARD_PIN_USART_RXD + * - \ref BOARD_PIN_USART_TXD + * - \ref BOARD_PIN_USART_CTS + * - \ref BOARD_PIN_USART_RTS + * - \ref BOARD_PIN_USART_EN + * - \ref BOARD_USART_BASE + * - \ref BOARD_ID_USART + */ + +/** Rtc */ +#define BOARD_RTC_ID ID_RTC + +/** TWI ID for QTouch application to use */ +#define BOARD_ID_TWI_AT42 ID_TWI0 +/** TWI Base for QTouch application to use */ +#define BOARD_BASE_TWI_AT42 TWI0 +/** TWI pins for QTouch application to use */ +#define BOARD_PINS_TWI_AT42 PINS_TWI0 + +/** USART RX pin for application */ +#define BOARD_PIN_USART_RXD PIN_USART1_RXD +/** USART TX pin for application */ +#define BOARD_PIN_USART_TXD PIN_USART1_TXD +/** USART CTS pin for application */ +#define BOARD_PIN_USART_CTS PIN_USART1_CTS +/** USART RTS pin for application */ +#define BOARD_PIN_USART_RTS PIN_USART1_RTS +/** USART ENABLE pin for application */ +#define BOARD_PIN_USART_EN PIN_USART1_EN +/** USART Base for application */ +#define BOARD_USART_BASE USART1 +/** USART ID for application */ +#define BOARD_ID_USART ID_USART1 + + + +/*----------------------------------------------------------------------------*/ + /* + * USB pins + */ +#define PINS_VBUS_EN {PIO_PC16, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} +#endif /* #ifndef _BOARD_H_ */ + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/bmp.h b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/bmp.h new file mode 100644 index 00000000..19659115 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/bmp.h @@ -0,0 +1,119 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * \section Purpose + * + * Utility for BMP + * + */ + +#ifndef BMP_H +#define BMP_H + +/** BMP magic number ('BM'). */ +#define BMP_TYPE 0x4D42 + +/** headerSize must be set to 40 */ +#define BITMAPINFOHEADER 40 + +/*------------------------------------------------------------------------------ + * Exported types + *------------------------------------------------------------------------------*/ + +#pragma pack( 1 ) + +/** BMP (Windows) Header Format */ +typedef struct _BMPHeader{ + /* signature, must be 4D42 hex */ + uint16_t type; + /* size of BMP file in bytes (unreliable) */ + uint32_t fileSize; + /* reserved, must be zero */ + uint16_t reserved1; + /* reserved, must be zero */ + uint16_t reserved2; + /* offset to start of image data in bytes */ + uint32_t offset; + /* size of BITMAPINFOHEADER structure, must be 40 */ + uint32_t headerSize; + /* image width in pixels */ + uint32_t width; + /* image height in pixels */ + uint32_t height; + /* number of planes in the image, must be 1 */ + uint16_t planes; + /* number of bits per pixel (1, 4, 8, 16, 24, 32) */ + uint16_t bits; + /* compression type (0=none, 1=RLE-8, 2=RLE-4) */ + uint32_t compression; + /* size of image data in bytes (including padding) */ + uint32_t imageSize; + /* horizontal resolution in pixels per meter (unreliable) */ + uint32_t xresolution; + /* vertical resolution in pixels per meter (unreliable) */ + uint32_t yresolution; + /* number of colors in image, or zero */ + uint32_t ncolours; + /* number of important colors, or zero */ + uint32_t importantcolours; + } BMPHeader; + +#pragma pack() + +/*------------------------------------------------------------------------------ + * Exported functions + *------------------------------------------------------------------------------*/ +extern uint8_t BMP_IsValid(void *file); +extern uint32_t BMP_GetFileSize(void *file); + +extern uint8_t BMP_Decode( + void *file, + uint8_t *buffer, + uint32_t width, + uint32_t height, + uint8_t bpp ); + +extern void WriteBMPheader( + uint32_t *pAddressHeader, + uint32_t bmpHSize, + uint32_t bmpVSize, + uint8_t nbByte_Pixels ); + +extern void BMP_displayHeader(uint32_t* pAddressHeader); +extern void RGB565toBGR555( + uint8_t *fileSource, + uint8_t *fileDestination, + uint32_t width, + uint32_t height, + uint8_t bpp ); + +#endif //#ifndef BMP_H + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/board_lowlevel.h b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/board_lowlevel.h new file mode 100644 index 00000000..836b3696 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/board_lowlevel.h @@ -0,0 +1,47 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface for the low-level initialization function. + * + */ + +#ifndef BOARD_LOWLEVEL_H +#define BOARD_LOWLEVEL_H + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +extern void LowLevelInit( void ); +extern void _SetupMemoryRegion( void ); + +#endif /* BOARD_LOWLEVEL_H */ + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/board_memories.h b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/board_memories.h new file mode 100644 index 00000000..04260ab4 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/board_memories.h @@ -0,0 +1,48 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface for memories configuration on board. + * + */ + +#ifndef BOARD_MEMORIES_H +#define BOARD_MEMORIES_H + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void BOARD_ConfigureSdram( void ); +extern uint32_t BOARD_SdramValidation(uint32_t baseAddr, uint32_t size); + +#endif /* #ifndef BOARD_MEMORIES_H */ + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/cs2100.h b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/cs2100.h new file mode 100644 index 00000000..6baf57ae --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/cs2100.h @@ -0,0 +1,93 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Implementation WM8904 driver. + * + */ + +#ifndef CS2100_H +#define CS2100_H + +#include "board.h" + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +#define CS2100_SLAVE_ADDRESS 0x4E + +/** ID and Rev register*/ +#define CS2100_REG_ID 0x01 + +/** VMID control 0 register*/ +#define CS2100_REG_CTRL 0x02 + +/** MIC Bias control 0 register*/ +#define CS2100_REG_DEV_CFG1 0x03 + +/** Bias control 1 register*/ +#define CS2100_REG_CFG 0x05 + +/** Power management control 0 register*/ +#define CS2100_REG_32_BIT_RATIO_1 0x06 +/** Power management control 0 register*/ +#define CS2100_REG_32_BIT_RATIO_2 0x07 +/** Power management control 0 register*/ +#define CS2100_REG_32_BIT_RATIO_3 0x08 +/** Power management control 0 register*/ +#define CS2100_REG_32_BIT_RATIO_4 0x09 +/** Power management control 2 register*/ +#define CS2100_REG_FUNC_CFG1 0x16 +/** Power management control 3 register*/ +#define CS2100_REG_FUNC_CFG2 0x17 +/** Power management control 3 register*/ +#define CS2100_REG_FUNC_CFG3 0x1E + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern uint16_t CS2100_Read( + Twid *pTwid, + uint32_t device, + uint32_t regAddr); + +extern void CS2100_Write( + Twid *pTwid, + uint32_t device, + uint32_t regAddr, + uint16_t data); + +extern uint8_t CS2100_Init(Twid *pTwid, uint32_t device, uint32_t PCK); +#endif // CS2100_H + + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/dbg_console.h b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/dbg_console.h new file mode 100644 index 00000000..af6e651b --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/dbg_console.h @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Include function prototype for the UART console. + */ + +#ifndef _DBG_CONSOLE_ +#define _DBG_CONSOLE_ + +#include + +extern void DBG_Configure( uint32_t dwBaudrate, uint32_t dwMasterClock ) ; +extern void DBG_PutChar( uint8_t uc ) ; +extern uint32_t DBG_GetChar( void ) ; +extern uint32_t DBG_IsRxReady( void ) ; + + +extern void DBG_DumpFrame( uint8_t* pucFrame, uint32_t dwSize ) ; +extern void DBG_DumpMemory( uint8_t* pucBuffer, uint32_t dwSize, uint32_t dwAddress ) ; +extern uint32_t DBG_GetInteger( int32_t* pdwValue ) ; +extern uint32_t DBG_GetIntegerMinMax( int32_t* pdwValue, int32_t dwMin, int32_t dwMax ) ; +extern uint32_t DBG_GetHexa32( uint32_t* pdwValue ) ; + +#endif /* _DBG_CONSOLE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/frame_buffer.h b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/frame_buffer.h new file mode 100644 index 00000000..7afe0488 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/frame_buffer.h @@ -0,0 +1,83 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface of frame buffer driver. + * + */ + +#ifndef _FRAME_BUFFER_ +#define _FRAME_BUFFER_ + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void FB_SetFrameBuffer( + LcdColor_t *pBuffer, + uint8_t ucWidth, + uint8_t ucHeight); + +extern void FB_SetColor(uint32_t color); + +extern uint32_t FB_DrawLine ( + uint32_t dwX1, + uint32_t dwY1, + uint32_t dwX2, + uint32_t dwY2 ); + +extern uint32_t FB_DrawPixel( uint32_t x, uint32_t y ); +extern uint32_t FB_DrawCircle( uint32_t x, uint32_t y, uint32_t r ); +extern uint32_t FB_DrawFilledCircle( + uint32_t dwX, + uint32_t dwY, + uint32_t dwRadius); + +extern uint32_t FB_DrawRectangle( + uint32_t dwX1, + uint32_t dwY1, + uint32_t dwX2, + uint32_t dwY2 ); + +extern uint32_t FB_DrawFilledRectangle( + uint32_t dwX1, + uint32_t dwY1, + uint32_t dwX2, + uint32_t dwY2 ); + +extern uint32_t FB_DrawPicture( + uint32_t dwX1, + uint32_t dwY1, + uint32_t dwX2, + uint32_t dwY2, + const void *pBuffer ); + +#endif /* #ifndef _FRAME_BUFFER_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/gmacb_phy.h b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/gmacb_phy.h new file mode 100644 index 00000000..568cc55a --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/gmacb_phy.h @@ -0,0 +1,114 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/** \addtogroup gmacb_module Ethernet GMACB Driver + *@{ + * Implement GEMAC PHY driver, that initialize the PHY to prepare for + * Ethernet transfer. + * + * \section Usage + * -# EMAC related pins and Driver should be initialized at first. + * -# Initialize GMACB Driver instance by invoking GMACB_Init(). + * -# Initialize PHY connected via GMACB_InitPhy(), PHY address is + * automatically adjusted by attempt to read. + * -# Perform PHY auto negotiate through GMACB_AutoNegotiate(), so + * connection established. + * + * + * Related files:\n + * \ref gmacb.h\n + * \ref gmacb.c\n + * \ref gmii.h.\n + * + */ +/**@}*/ + +#ifndef _GMACB_PHY_H +#define _GMACB_PHY_H + + +/*--------------------------------------------------------------------------- + * Headers + *---------------------------------------------------------------------------*/ + +#include "board.h" + +/*--------------------------------------------------------------------------- + * Definitions + *---------------------------------------------------------------------------*/ + +/** The reset length setting for external reset configuration */ +#define GMACB_RESET_LENGTH 0xD + +/*--------------------------------------------------------------------------- + * Types + *---------------------------------------------------------------------------*/ + + +/** The DM9161 instance */ +typedef struct _GMacb { + /**< Driver */ + sGmacd *pGmacd; + /** The retry & timeout settings */ + uint32_t retryMax; + /** PHY address ( pre-defined by pins on reset ) */ + uint8_t phyAddress; + } GMacb; + +/*--------------------------------------------------------------------------- + * Exported functions + *---------------------------------------------------------------------------*/ +extern void GMACB_SetupTimeout(GMacb *pMacb, uint32_t toMax); + +extern void GMACB_Init(GMacb *pMacb, sGmacd *pGmacd, uint8_t phyAddress); + +extern uint8_t GMACB_InitPhy( + GMacb *pMacb, + uint32_t mck, + const Pin *pResetPins, + uint32_t nbResetPins, + const Pin *pEmacPins, + uint32_t nbEmacPins); + +extern uint8_t GMACB_AutoNegotiate(GMacb *pMacb); + +extern uint8_t GMACB_GetLinkSpeed(GMacb *pMacb, uint8_t applySettings); + +extern uint8_t GMACB_Send(GMacb *pMacb, void *pBuffer, uint32_t size); + +extern uint32_t GMACB_Poll(GMacb *pMacb, uint8_t *pBuffer, uint32_t size); + +extern void GMACB_DumpRegisters(GMacb *pMacb); + +extern uint8_t GMACB_ResetPhy(GMacb *pMacb); + +#endif // #ifndef _GMACB_H + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/gmii.h b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/gmii.h new file mode 100644 index 00000000..bb1a667d --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/gmii.h @@ -0,0 +1,116 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _GMII_DEFINE_H +#define _GMII_DEFINE_H + + +/*--------------------------------------------------------------------------- + * Definitions + *---------------------------------------------------------------------------*/ + +//IEEE defined Registers +#define GMII_BMCR 0x0 // Basic Mode Control Register +#define GMII_BMSR 0x1 // Basic Mode Status Register +#define GMII_PHYID1R 0x2 // PHY Identifier Register 1 +#define GMII_PHYID2R 0x3 // PHY Identifier Register 2 +#define GMII_ANAR 0x4 // Auto_Negotiation Advertisement Register +#define GMII_ANLPAR 0x5 // Auto_negotiation Link Partner Ability Register +#define GMII_ANER 0x6 // Auto-negotiation Expansion Register +#define GMII_ANNPR 0x7 // Auto-negotiation Next Page Register +#define GMII_ANLPNPAR 0x8 // Auto_negotiation Link Partner Next Page Ability Register +#define GMII_AFEC0R 0x11 // AFE Control 0 Register +#define GMII_AFEC3R 0x14 // AFE Control 3 Register +#define GMII_RXERCR 0x15 // RXER Counter Register +#define GMII_OMSSR 0x17 // Operation Mode Strap Status Register +#define GMII_ECR 0x18 // Expanded Control Register +#define GMII_ICSR 0x1B // Interrupt Control/Status Register +#define GMII_FC 0x1C // Function Control +#define GMII_LCSR 0x1D // LinkMD® Control/Status Register +#define GMII_PC1R 0x1E // PHY Control 1 Register +#define GMII_PC2R 0x1F // PHY Control 2 Register + +// PHY ID Identifier Register +#define GMII_LSB_MASK 0x0U +// definitions: MII_PHYID1 +#define GMII_OUI_MSB 0x0022 +// definitions: MII_PHYID2 +#define GMII_OUI_LSB 0x1572 // KSZ8061 PHY Id2 + +// Basic Mode Control Register (BMCR) +// Bit definitions: MII_BMCR +#define GMII_RESET (1 << 15) // 1= Software Reset; 0=Normal Operation +#define GMII_LOOPBACK (1 << 14) // 1=loopback Enabled; 0=Normal Operation +#define GMII_SPEED_SELECT_LSB (1 << 13) // 1,0=1000Mbps 0,1=100Mbps; 0,0=10Mbps +#define GMII_AUTONEG (1 << 12) // Auto-negotiation Enable +#define GMII_POWER_DOWN (1 << 11) // 1=Power down 0=Normal operation +#define GMII_ISOLATE (1 << 10) // 1 = Isolates 0 = Normal operation +#define GMII_RESTART_AUTONEG (1 << 9) // 1 = Restart auto-negotiation 0 = Normal operation +#define GMII_DUPLEX_MODE (1 << 8) // 1 = Full duplex operation 0 = Normal operation +// Reserved 7 // Read as 0, ignore on write +#define GMII_SPEED_SELECT_MSB (1 << 6) // +// Reserved 5 to 0 // Read as 0, ignore on write + + +// Basic Mode Status Register (BMSR) +// Bit definitions: MII_BMSR +#define GMII_100BASE_T4 (1 << 15) // 100BASE-T4 Capable +#define GMII_100BASE_TX_FD (1 << 14) // 100BASE-TX Full Duplex Capable +#define GMII_100BASE_T4_HD (1 << 13) // 100BASE-TX Half Duplex Capable +#define GMII_10BASE_T_FD (1 << 12) // 10BASE-T Full Duplex Capable +#define GMII_10BASE_T_HD (1 << 11) // 10BASE-T Half Duplex Capable +// Reserved 10 to 9 // Read as 0, ignore on write +#define GMII_EXTEND_STATUS (1 << 8) // 1 = Extend Status Information In Reg 15 +// Reserved 7 +#define GMII_MF_PREAMB_SUPPR (1 << 6) // MII Frame Preamble Suppression +#define GMII_AUTONEG_COMP (1 << 5) // Auto-negotiation Complete +#define GMII_REMOTE_FAULT (1 << 4) // Remote Fault +#define GMII_AUTONEG_ABILITY (1 << 3) // Auto Configuration Ability +#define GMII_LINK_STATUS (1 << 2) // Link Status +#define GMII_JABBER_DETECT (1 << 1) // Jabber Detect +#define GMII_EXTEND_CAPAB (1 << 0) // Extended Capability + +// Auto-negotiation Advertisement Register (ANAR) +// Auto-negotiation Link Partner Ability Register (ANLPAR) +// Bit definitions: MII_ANAR, MII_ANLPAR +#define GMII_NP (1 << 15) // Next page Indication +// Reserved 7 +#define GMII_RF (1 << 13) // Remote Fault +// Reserved 12 // Write as 0, ignore on read +#define GMII_PAUSE_MASK (3 << 11) // 0,0 = No Pause 1,0 = Asymmetric Pause(link partner) + // 0,1 = Symmetric Pause 1,1 = Symmetric&Asymmetric Pause(local device) +#define GMII_T4 (1 << 9) // 100BASE-T4 Support +#define GMII_TX_FDX (1 << 8) // 100BASE-TX Full Duplex Support +#define GMII_TX_HDX (1 << 7) // 100BASE-TX Support +#define GMII_10_FDX (1 << 6) // 10BASE-T Full Duplex Support +#define GMII_10_HDX (1 << 5) // 10BASE-T Support +// Selector 4 to 0 // Protocol Selection Bits +#define GMII_AN_IEEE_802_3 0x00001 + +#endif // #ifndef _MII_DEFINE_H diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/ili9488.h b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/ili9488.h new file mode 100644 index 00000000..581c5129 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/ili9488.h @@ -0,0 +1,107 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface of ILI9488 driver. + * + */ + +#ifndef _ILI9488_H_ +#define _ILI9488_H_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +#include + + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +#define ILI9488_SPIMODE 0 +#define ILI9488_EBIMODE 1 + +/* ILI9325 ID code */ +#define ILI9488_DEVICE_CODE 0x9488 + +#define ILI9488_LCD_WIDTH 320 +#define ILI9488_LCD_HEIGHT 480 +#define ILI9488_SELF_TEST_OK 0xC0 + +/* EBI chip select for LCD */ +#define SMC_EBI_LCD_CS 3 + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ +typedef enum{ + AccessInst = 0, + AccessRead, + AccessWrite +}AccessIli_t; + +typedef union _union_type +{ + uint32_t value; + struct{ + uint8_t byte_8; + uint8_t byte_l6; + uint8_t byte_24; + uint8_t byte_32; + }byte; + struct{ + uint16_t half_word_l; + uint16_t half_word_h; + }half_word; + }union_type; +typedef volatile uint8_t REG8; + +typedef uint32_t LcdColor_t; + +/*---------------------------------------------------------------------------- + * Marcos + *----------------------------------------------------------------------------*/ +/* Pixel cache used to speed up communication */ +#define LCD_DATA_CACHE_SIZE BOARD_LCD_WIDTH + +/*---------------------------------------------------------------------------- + * Function Marcos + *----------------------------------------------------------------------------*/ +#define get_0b_to_8b(x) (((union_type*)&(x))->byte.byte_8) +#define get_8b_to_16b(x) (((union_type*)&(x))->byte.byte_l6) +#define get_16b_to_24b(x) (((union_type*)&(x))->byte.byte_24) +#define get_24b_to_32b(x) (((union_type*)&(x))->byte.byte_32) + +#endif /* #ifndef ILI9488 */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/ili9488_dma.h b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/ili9488_dma.h new file mode 100644 index 00000000..5c91539a --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/ili9488_dma.h @@ -0,0 +1,94 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface of ILI9488 driver. + * + */ + +#ifndef _ILI9488_DMA_H_ +#define _ILI9488_DMA_H_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" +#include + +/*------------------------------------------------------------------------------ + * Definitions + *----------------------------------------------------------------------------*/ +/** An unspecified error has occurred.*/ +#define ILI9488_ERROR_DMA_ALLOCATE_CHANNEL 1 +#define ILI9488_ERROR_DMA_CONFIGURE 2 +#define ILI9488_ERROR_DMA_TRANSFER 3 +#define ILI9488_ERROR_DMA_SIZE 4 + +#define ILI9488_SPI SPI0 +#define ILI9488_SPI_ID ID_SPI0 + +/* EBI BASE ADDRESS for SMC LCD */ +#define ILI9488_BASE_ADDRESS 0x63000000 + +/*------------------------------------------------------------------------------ + * Types + *----------------------------------------------------------------------------*/ + +typedef struct _ILI9488_dma +{ + /** Pointer to DMA driver */ + sXdmad *xdmaD; + /** ili9488 Tx channel */ + uint32_t ili9488DmaTxChannel; + /** ili9488 Rx channel */ + uint32_t ili9488DmaRxChannel; + /** ili9488 Tx/Rx configure descriptor */ + sXdmadCfg xdmadRxCfg,xdmadTxCfg; + /** ili9488 dma interrupt */ + uint32_t xdmaInt; + /** Pointer to SPI Hardware registers */ + Spi* pSpiHw ; + /** SPI Id as defined in the product datasheet */ + uint8_t spiId ; +}sIli9488Dma; + +typedef struct _ILI9488_ctl +{ + /** ili9488 Command/Data mode */ + volatile uint32_t cmdOrDataFlag; + /** ili9488 Rx done */ + volatile uint32_t rxDoneFlag; + /** ili9488 Tx done */ + volatile uint32_t txDoneFlag; +}sIli9488DmaCtl; + +#endif /* #ifndef ILI9488_DMA */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/ili9488_ebi.h b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/ili9488_ebi.h new file mode 100644 index 00000000..6539751e --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/ili9488_ebi.h @@ -0,0 +1,62 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface of ILI9488 driver. + * + */ + +#ifndef _ILI9488_EBI_H_ +#define _ILI9488_EBI_H_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +#include + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +extern uint32_t ILI9488_EbiReadChipId (void); +extern uint32_t ILI9488_EbiInitialize( sXdmad * dmad ); +extern void ILI9488_EbiSetPixelFormat(uint16_t format); +extern void ILI9488_EbiSetCursor(uint16_t x, uint16_t y); +extern void ILI9488_EbiSetWindow( + uint16_t dwX, uint16_t dwY, uint16_t dwWidth, uint16_t dwHeight ); +extern void ILI9488_EbiSetFullWindow(void); +extern void ILI9488_EbiOn(void ); +extern void ILI9488_EbiOff(void ); +extern void ILI9488_EbiSetDisplayLandscape( uint8_t dwRGB, uint8_t LandscaprMode ); + +#endif /* #ifndef ILI9488_EBI */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/ili9488_ebi_dma.h b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/ili9488_ebi_dma.h new file mode 100644 index 00000000..efe45e8c --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/ili9488_ebi_dma.h @@ -0,0 +1,55 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface of ILI9488 driver. + * + */ + +#ifndef _ILI9488_EBI_DMA_H_ +#define _ILI9488_EBI_DMA_H_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" +#include + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +extern uint8_t ILI9488_EbiInitializeWithDma(sXdmad * dmad); +extern uint8_t ILI9488_EbiDmaTxTransfer( uint16_t *pTxBuffer, uint32_t wTxSize); +extern uint8_t ILI9488_EbiDmaRxTransfer( uint32_t *pRxBuffer,uint32_t wRxSize); +extern uint8_t ILI9488_EbiSendCommand(uint16_t Instr, uint16_t *pTxData, + uint32_t *pRxData, AccessIli_t ReadWrite, uint32_t size); +#endif /* #ifndef ILI9488_EBI_DMA */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/ili9488_reg.h b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/ili9488_reg.h new file mode 100644 index 00000000..523ed4b0 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/ili9488_reg.h @@ -0,0 +1,131 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef ILI9488_REG_H_INCLUDED +#define ILI9488_REG_H_INCLUDED + +/* Level 1 Commands (from the display Datasheet) */ +#define ILI9488_CMD_NOP 0x00 +#define ILI9488_CMD_SOFTWARE_RESET 0x01 +#define ILI9488_CMD_READ_DISP_ID 0x04 +#define ILI9488_CMD_READ_ERROR_DSI 0x05 +#define ILI9488_CMD_READ_DISP_STATUS 0x09 +#define ILI9488_CMD_READ_DISP_POWER_MODE 0x0A +#define ILI9488_CMD_READ_DISP_MADCTRL 0x0B +#define ILI9488_CMD_READ_DISP_PIXEL_FORMAT 0x0C +#define ILI9488_CMD_READ_DISP_IMAGE_MODE 0x0D +#define ILI9488_CMD_READ_DISP_SIGNAL_MODE 0x0E +#define ILI9488_CMD_READ_DISP_SELF_DIAGNOSTIC 0x0F +#define ILI9488_CMD_ENTER_SLEEP_MODE 0x10 +#define ILI9488_CMD_SLEEP_OUT 0x11 +#define ILI9488_CMD_PARTIAL_MODE_ON 0x12 +#define ILI9488_CMD_NORMAL_DISP_MODE_ON 0x13 +#define ILI9488_CMD_DISP_INVERSION_OFF 0x20 +#define ILI9488_CMD_DISP_INVERSION_ON 0x21 +#define ILI9488_CMD_PIXEL_OFF 0x22 +#define ILI9488_CMD_PIXEL_ON 0x23 +#define ILI9488_CMD_DISPLAY_OFF 0x28 +#define ILI9488_CMD_DISPLAY_ON 0x29 +#define ILI9488_CMD_COLUMN_ADDRESS_SET 0x2A +#define ILI9488_CMD_PAGE_ADDRESS_SET 0x2B +#define ILI9488_CMD_MEMORY_WRITE 0x2C +#define ILI9488_CMD_MEMORY_READ 0x2E +#define ILI9488_CMD_PARTIAL_AREA 0x30 +#define ILI9488_CMD_VERT_SCROLL_DEFINITION 0x33 +#define ILI9488_CMD_TEARING_EFFECT_LINE_OFF 0x34 +#define ILI9488_CMD_TEARING_EFFECT_LINE_ON 0x35 +#define ILI9488_CMD_MEMORY_ACCESS_CONTROL 0x36 +#define ILI9488_CMD_VERT_SCROLL_START_ADDRESS 0x37 +#define ILI9488_CMD_IDLE_MODE_OFF 0x38 +#define ILI9488_CMD_IDLE_MODE_ON 0x39 +#define ILI9488_CMD_COLMOD_PIXEL_FORMAT_SET 0x3A +#define ILI9488_CMD_WRITE_MEMORY_CONTINUE 0x3C +#define ILI9488_CMD_READ_MEMORY_CONTINUE 0x3E +#define ILI9488_CMD_SET_TEAR_SCANLINE 0x44 +#define ILI9488_CMD_GET_SCANLINE 0x45 +#define ILI9488_CMD_WRITE_DISPLAY_BRIGHTNESS 0x51 +#define ILI9488_CMD_READ_DISPLAY_BRIGHTNESS 0x52 +#define ILI9488_CMD_WRITE_CTRL_DISPLAY 0x53 +#define ILI9488_CMD_READ_CTRL_DISPLAY 0x54 +#define ILI9488_CMD_WRITE_CONTENT_ADAPT_BRIGHTNESS 0x55 +#define ILI9488_CMD_READ_CONTENT_ADAPT_BRIGHTNESS 0x56 +#define ILI9488_CMD_WRITE_MIN_CAB_LEVEL 0x5E +#define ILI9488_CMD_READ_MIN_CAB_LEVEL 0x5F +#define ILI9488_CMD_READ_ABC_SELF_DIAG_RES 0x68 +#define ILI9488_CMD_READ_ID1 0xDA +#define ILI9488_CMD_READ_ID2 0xDB +#define ILI9488_CMD_READ_ID3 0xDC + +/* Level 2 Commands (from the display Datasheet) */ +#define ILI9488_CMD_INTERFACE_MODE_CONTROL 0xB0 +#define ILI9488_CMD_FRAME_RATE_CONTROL_NORMAL 0xB1 +#define ILI9488_CMD_FRAME_RATE_CONTROL_IDLE_8COLOR 0xB2 +#define ILI9488_CMD_FRAME_RATE_CONTROL_PARTIAL 0xB3 +#define ILI9488_CMD_DISPLAY_INVERSION_CONTROL 0xB4 +#define ILI9488_CMD_BLANKING_PORCH_CONTROL 0xB5 +#define ILI9488_CMD_DISPLAY_FUNCTION_CONTROL 0xB6 +#define ILI9488_CMD_ENTRY_MODE_SET 0xB7 +#define ILI9488_CMD_BACKLIGHT_CONTROL_1 0xB9 +#define ILI9488_CMD_BACKLIGHT_CONTROL_2 0xBA +#define ILI9488_CMD_HS_LANES_CONTROL 0xBE +#define ILI9488_CMD_POWER_CONTROL_1 0xC0 +#define ILI9488_CMD_POWER_CONTROL_2 0xC1 +#define ILI9488_CMD_POWER_CONTROL_NORMAL_3 0xC2 +#define ILI9488_CMD_POWER_CONTROL_IDEL_4 0xC3 +#define ILI9488_CMD_POWER_CONTROL_PARTIAL_5 0xC4 +#define ILI9488_CMD_VCOM_CONTROL_1 0xC5 +#define ILI9488_CMD_CABC_CONTROL_1 0xC6 +#define ILI9488_CMD_CABC_CONTROL_2 0xC8 +#define ILI9488_CMD_CABC_CONTROL_3 0xC9 +#define ILI9488_CMD_CABC_CONTROL_4 0xCA +#define ILI9488_CMD_CABC_CONTROL_5 0xCB +#define ILI9488_CMD_CABC_CONTROL_6 0xCC +#define ILI9488_CMD_CABC_CONTROL_7 0xCD +#define ILI9488_CMD_CABC_CONTROL_8 0xCE +#define ILI9488_CMD_CABC_CONTROL_9 0xCF +#define ILI9488_CMD_NVMEM_WRITE 0xD0 +#define ILI9488_CMD_NVMEM_PROTECTION_KEY 0xD1 +#define ILI9488_CMD_NVMEM_STATUS_READ 0xD2 +#define ILI9488_CMD_READ_ID4 0xD3 +#define ILI9488_CMD_ADJUST_CONTROL_1 0xD7 +#define ILI9488_CMD_READ_ID_VERSION 0xD8 +#define ILI9488_CMD_POSITIVE_GAMMA_CORRECTION 0xE0 +#define ILI9488_CMD_NEGATIVE_GAMMA_CORRECTION 0xE1 +#define ILI9488_CMD_DIGITAL_GAMMA_CONTROL_1 0xE2 +#define ILI9488_CMD_DIGITAL_GAMMA_CONTROL_2 0xE3 +#define ILI9488_CMD_SET_IMAGE_FUNCTION 0xE9 +#define ILI9488_CMD_ADJUST_CONTROL_2 0xF2 +#define ILI9488_CMD_ADJUST_CONTROL_3 0xF7 +#define ILI9488_CMD_ADJUST_CONTROL_4 0xF8 +#define ILI9488_CMD_ADJUST_CONTROL_5 0xF9 +#define ILI9488_CMD_SPI_READ_SETTINGS 0xFB +#define ILI9488_CMD_ADJUST_CONTROL_6 0xFC +#define ILI9488_CMD_ADJUST_CONTROL_7 0xFF + +#endif /* ILI9488_REGS_H_INCLUDED */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/ili9488_spi.h b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/ili9488_spi.h new file mode 100644 index 00000000..3f9ed815 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/ili9488_spi.h @@ -0,0 +1,69 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface of ILI9488 driver. + * + */ + +#ifndef _ILI9488_SPI_H_ +#define _ILI9488_SPI_H_ + +/*------------------------------------------------------------------------------ + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +/*------------------------------------------------------------------------------ + * Exported functions + *----------------------------------------------------------------------------*/ +extern uint32_t ILI9488_SpiReadChipId (void); +extern uint32_t ILI9488_SpiInitialize( sXdmad * dmad ); +extern void ILI9488_SpiSetPixelFormat(uint8_t format); +extern void ILI9488_SpiNop(void); +extern void ILI9488_SpiWriteMemory(const uint8_t *pBuf, uint32_t size); +extern void ILI9488_SpiReadMemory( const uint8_t *pBuf, uint32_t size); +extern void ILI9488_SpiSetCursor(uint16_t x, uint16_t y); +extern void ILI9488_SpiSetWindow( + uint16_t dwX, + uint16_t dwY, + uint16_t dwWidth, + uint16_t dwHeight ); + +extern void ILI9488_SpiSetFullWindow(void); +extern void ILI9488_SpiOn(void ); +extern void ILI9488_SpiOff(void ); +extern void ILI9488_SpiSetDisplayLandscape( + uint8_t dwRGB, uint8_t LandscaprMode ); +extern void ILI9488_SetPixelColor(uint32_t x, uint32_t y, uint32_t color); + +#endif /* #ifndef ILI9488_SPI */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/ili9488_spi_dma.h b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/ili9488_spi_dma.h new file mode 100644 index 00000000..9d37f78c --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/ili9488_spi_dma.h @@ -0,0 +1,56 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface of ILI9488 DMA driver. + * + */ + +#ifndef _ILI9488_SPI_DMA_H_ +#define _ILI9488_SPI_DMA_H_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" +#include + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +extern uint8_t ILI9488_SpiInitializeWithDma(sXdmad * dmad); +extern uint8_t ILI9488_SpiDmaTxTransfer( uint8_t *pTxBuffer, uint32_t wTxSize); +extern uint8_t ILI9488_SpiDmaRxTransfer( uint32_t *pRxBuffer,uint32_t wRxSize); +extern uint8_t ILI9488_SpiSendCommand(uint8_t Instr, uint8_t* pTxData, + uint32_t* pRxData, AccessIli_t ReadWrite, uint32_t size); + +#endif /* #ifndef ILI9488_SPI_DMA */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/image_sensor_inf.h b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/image_sensor_inf.h new file mode 100644 index 00000000..c84b5b93 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/image_sensor_inf.h @@ -0,0 +1,135 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "board.h" + + +/*--------------------------------------------------------------------------- + * Definition + *---------------------------------------------------------------------------*/ +#define SENDOR_SUPPORTED_OUTPUTS 7 + +/** terminating list entry for register in configuration file */ +#define SENSOR_REG_TERM 0xFF +/** terminating list entry for value in configuration file */ +#define SENSOR_VAL_TERM 0xFF + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** Sensor type */ +typedef enum _sensorType { + SENSOR_COMS = 0, + SENSOR_CCD +}sensorType_t; + +/** Sensor status or return code */ +typedef enum _sensorStatus { + SENSOR_OK = 0, /**< Operation is successful */ + SENSOR_TWI_ERROR, + SENSOR_ID_ERROR, + SENSOR_RESOLUTION_NOT_SUPPORTED +} sendorStatus_t; + +/** Sensor TWI mode */ +typedef enum _sensorTwiMode { + SENSOR_TWI_REG_BYTE_DATA_BYTE = 0, + SENSOR_TWI_REG_2BYTE_DATA_BYTE, + SENSOR_TWI_REG_BYTE_DATA_2BYTE +} sensorTwiMode_t; + +/** Sensor resolution */ +typedef enum _sensorResolution { + QVGA = 0, + VGA, + SVGA, + XGA, + WXGA, + UVGA +} sensorOutputResolution_t; + +/** Sensor output format */ +typedef enum _sensorOutputFormat { + RAW_BAYER_12_BIT = 0, + RAW_BAYER_10_BIT, + YUV_422_8_BIT, + YUV_422_10_BIT, + MONO_12_BIT +} sensorOutputFormat_t; + +/** define a structure for sensor register initialization values */ +typedef struct _sensor_reg { + uint16_t reg; /* Register to be written */ + uint16_t val; /* value to be written */ +}sensorReg_t; + +typedef struct _sensor_output { + uint8_t type ; /** Index 0: normal, 1: AF setting*/ + sensorOutputResolution_t output_resolution; /** sensor output resolution */ + sensorOutputFormat_t output_format; /** sensor output format */ + uint8_t supported; /** supported for current output_resolution*/ + uint32_t output_width; /** output width */ + uint32_t output_height; /** output height */ + const sensorReg_t *output_setting; /** sensor registers setting */ +}sensorOutput_t; + +/** define a structure for sensor profile */ +typedef struct _sensor_profile { + sensorType_t cmos_ccd; /** Sensor type for CMOS sensor or CCD */ + sensorTwiMode_t twi_inf_mode; /** TWI interface mode */ + uint32_t twi_slave_addr; /** TWI slave address */ + uint16_t pid_high_reg; /** Register address for product ID high byte */ + uint16_t pid_low_reg; /** Register address for product ID low byte*/ + uint16_t pid_high; /** product ID high byte */ + uint16_t pid_low; /** product ID low byte */ + uint16_t version_mask; /** version mask */ + const sensorOutput_t *outputConf[SENDOR_SUPPORTED_OUTPUTS]; /** sensor settings */ +}sensorProfile_t; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +extern sendorStatus_t sensor_twi_write_regs(Twid * pTwid, + const sensorReg_t * pReglist); + +extern sendorStatus_t sensor_twi_read_regs(Twid * pTwid, + const sensorReg_t * pReglist); + +extern sendorStatus_t sensor_setup(Twid * pTwid, + const sensorProfile_t *sensor_profile, + sensorOutputResolution_t resolution); + +extern sendorStatus_t sensor_get_output(sensorOutputFormat_t *format, + uint32_t *width, + uint32_t* height, + sensorOutputResolution_t resolution); diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/lcd_color.h b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/lcd_color.h new file mode 100644 index 00000000..5fc21d13 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/lcd_color.h @@ -0,0 +1,109 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef COLOR_H +#define COLOR_H + +/** + * \file + * + * RGB 24-bits color table definition. + * + */ + +/* + * RGB 24 Bpp + * RGB 888 + * R7R6R5R4 R3R2R1R0 G7G6G5G4 G3G2G1G0 B7B6B5B4 B3B2B1B0 + */ + +#define COLOR_BLACK 0x000000 +#define COLOR_WHITE 0xFFFFFF + +#define COLOR_BLUE 0x0000FF +#define COLOR_GREEN 0x00FF00 +#define COLOR_RED 0xFF0000 + +#define COLOR_NAVY 0x000080 +#define COLOR_DARKBLUE 0x00008B +#define COLOR_DARKGREEN 0x006400 +#define COLOR_DARKCYAN 0x008B8B +#define COLOR_CYAN 0x00FFFF +#define COLOR_TURQUOISE 0x40E0D0 +#define COLOR_INDIGO 0x4B0082 +#define COLOR_DARKRED 0x800000 +#define COLOR_OLIVE 0x808000 +#define COLOR_GRAY 0x808080 +#define COLOR_SKYBLUE 0x87CEEB +#define COLOR_BLUEVIOLET 0x8A2BE2 +#define COLOR_LIGHTGREEN 0x90EE90 +#define COLOR_DARKVIOLET 0x9400D3 +#define COLOR_YELLOWGREEN 0x9ACD32 +#define COLOR_BROWN 0xA52A2A +#define COLOR_DARKGRAY 0xA9A9A9 +#define COLOR_SIENNA 0xA0522D +#define COLOR_LIGHTBLUE 0xADD8E6 +#define COLOR_GREENYELLOW 0xADFF2F +#define COLOR_SILVER 0xC0C0C0 +#define COLOR_LIGHTGREY 0xD3D3D3 +#define COLOR_LIGHTCYAN 0xE0FFFF +#define COLOR_VIOLET 0xEE82EE +#define COLOR_AZUR 0xF0FFFF +#define COLOR_BEIGE 0xF5F5DC +#define COLOR_MAGENTA 0xFF00FF +#define COLOR_TOMATO 0xFF6347 +#define COLOR_GOLD 0xFFD700 +#define COLOR_ORANGE 0xFFA500 +#define COLOR_SNOW 0xFFFAFA +#define COLOR_YELLOW 0xFFFF00 + +#define BLACK 0x0000 +#define BLUE 0x001F +#define RED 0xF800 +#define GREEN 0x07E0 +#define WHITE 0xFFFF + +/* level is in [0; 31]*/ +#define BLUE_LEV( level) ( (level)&BLUE ) +#define GREEN_LEV(level) ( (((level)*2)<<5)&GREEN ) +#define RED_LEV( level) ( ((level)<<(5+6))&RED ) +#define GRAY_LEV( level) ( BLUE_LEV(level) | GREEN_LEV(level) | RED_LEV(level)) + +#define RGB_24_TO_RGB565(RGB) \ + (((RGB >>19)<<11) | (((RGB & 0x00FC00) >>5)) | (RGB & 0x00001F)) +#define RGB_24_TO_18BIT(RGB) \ + (((RGB >>16)&0xFC) | (((RGB & 0x00FF00) >>10) << 10) | (RGB & 0x0000FC)<<16) +#define RGB_16_TO_18BIT(RGB) \ + (((((RGB >>11)*63)/31)<<18) | (RGB & 0x00FC00) | (((RGB & 0x00001F)*63)/31)) +#define BGR_TO_RGB_18BIT(RGB) \ + (RGB & 0xFF0000) | ((RGB & 0x00FF00) >> 8 ) | ( (RGB & 0x0000FC) >> 16 )) +#define BGR_16_TO_18BITRGB(RGB) BGR_TO_RGB_18BIT(RGB_16_TO_18BIT(RGB)) + + +#endif /* #define COLOR_H */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/lcd_draw.h b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/lcd_draw.h new file mode 100644 index 00000000..21f7fa91 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/lcd_draw.h @@ -0,0 +1,186 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + /** + * \file + * + * Interface for draw function on LCD. + * + */ + +#ifndef DRAW_H +#define DRAW_H + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "board.h" +#include +#include "lcd_gimp_image.h" + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +/** Horizontal direction line definition */ +#define DIRECTION_HLINE 0 +/** Vertical direction line definition */ +#define DIRECTION_VLINE 1 + +typedef struct _rect{ + uint32_t x; + uint32_t y; + uint32_t width; + uint32_t height; +}rect; + +COMPILER_PACK_SET(1) +typedef struct _rgb{ + uint8_t b; + uint8_t g; + uint8_t r; +}sBGR; +COMPILER_PACK_RESET() + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +extern void LCDD_SetUpdateWindowSize(rect rc); + +extern void LCDD_UpdateWindow(void); + +extern void LCDD_UpdatePartialWindow( uint8_t* pbuf, uint32_t size); + +extern void LCDD_DrawRectangleWithFill( + uint16_t* pbuf, + uint32_t dwX, + uint32_t dwY, + uint32_t dwWidth, + uint32_t dwHeight, + uint32_t dwColor); + +extern uint32_t LCDD_DrawCircle( + uint16_t* pbuf, + uint32_t x, + uint32_t y, + uint32_t r, + uint32_t color); + +extern uint32_t LCD_DrawFilledCircle( + uint16_t* pbuf, + uint32_t dwX, + uint32_t dwY, + uint32_t dwRadius, + uint32_t color); + +extern void LCDD_DrawString( + uint16_t* pbuf, + uint32_t x, + uint32_t y, + const uint8_t *pString, + uint32_t color ); + +extern void LCDD_GetStringSize( + const uint8_t *pString, + uint32_t *pWidth, + uint32_t *pHeight ); + +extern void LCDD_BitBlt( + uint16_t* pbuf, + uint32_t dst_x, + uint32_t dst_y, + uint32_t dst_w, + uint32_t dst_h, + const LcdColor_t *src, + uint32_t src_x, + uint32_t src_y, + uint32_t src_w, + uint32_t src_h); + +extern void LCDD_BitBltAlphaBlend(uint16_t* pbuf, + uint32_t dst_x, + uint32_t dst_y, + uint32_t dst_w, + uint32_t dst_h, + const LcdColor_t *src, + uint32_t src_x, + uint32_t src_y, + uint32_t src_w, + uint32_t src_h, + uint32_t alpha); +extern void LCDD_DrawImage( + uint16_t* pbuf, + uint32_t dwX, + uint32_t dwY, + const LcdColor_t *pImage, + uint32_t dwWidth, + uint32_t dwHeight ); + +extern void LCDD_DrawPixel( + uint16_t* pbuf, + uint32_t x, + uint32_t y, + uint32_t color ); + +extern void LCDD_DrawLine( + uint16_t* pbuf, + uint32_t dwX1, + uint32_t dwY1, + uint32_t dwX2, + uint32_t dwY2, + uint32_t color); + +extern uint32_t LCDD_DrawLineBresenham( + uint16_t* pbuf, + uint32_t dwX1, + uint32_t dwY1, + uint32_t dwX2, + uint32_t dwY2, + uint32_t color); + +extern void LCDD_DrawRectangle( + uint16_t* pbuf, + uint32_t x, + uint32_t y, + uint32_t width, + uint32_t height, + uint32_t color); + +extern void LCDD_SetCavasBuffer( + void* pBuffer, + uint32_t wBufferSize); + +extern void LCDD_DrawStraightLine( + uint16_t* pbuf, + uint32_t dwX1, + uint32_t dwY1, + uint32_t dwX2, + uint32_t dwY2 , + uint32_t color ); +#endif /* #ifndef DRAW_H */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/lcd_font.h b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/lcd_font.h new file mode 100644 index 00000000..4d2c4796 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/lcd_font.h @@ -0,0 +1,108 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface for draw font on LCD. + * + */ + +/** + * + * \section Purpose + * + * The font.h files declares a font structure and a LCDD_DrawChar function + * that must be implemented by a font definition file to be used with the + * LCDD_DrawString method of draw.h. + * + * The font10x14.c implements the necessary variable and function for a 10x14 + * font. + * + * \section Usage + * + * -# Declare a gFont global variable with the necessary Font information. + * -# Implement an LCDD_DrawChar function which displays the specified + * character on the LCD. + * -# Use the LCDD_DrawString method defined in draw.h to display a complete + * string. + */ + +#ifndef _LCD_FONT_ +#define _LCD_FONT_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + + +/** \brief Describes the font (width, height, supported characters, etc.) used by + * the LCD driver draw API. + */ +typedef struct _Font { + /* Font width in pixels. */ + uint8_t width; + /* Font height in pixels. */ + uint8_t height; +} Font; + +/*---------------------------------------------------------------------------- + * Variables + *----------------------------------------------------------------------------*/ + +/** Global variable describing the font being instanced. */ +extern const Font gFont; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void LCDD_DrawChar( + uint16_t* pCanvasBuffer, + uint32_t x, + uint32_t y, + uint8_t c, + uint32_t color ); + +extern void LCD_DrawString( + uint16_t* pCanvasBuffer, + uint32_t dwX, + uint32_t dwY, + const uint8_t *pString, + uint32_t color ); + + +#endif /* #ifndef LCD_FONT_ */ + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/lcd_font10x14.h b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/lcd_font10x14.h new file mode 100644 index 00000000..050da6f2 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/lcd_font10x14.h @@ -0,0 +1,45 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + /** + * \file + * + * Font 10x14 table definition. + * + */ + +#ifndef _LCD_FONT_10x14_ +#define _LCD_FONT_10x14_ + +#include + +/** Char set of font 10x14 */ +extern const uint8_t pCharset10x14[]; + +#endif /* #ifdef _LCD_FONT_10x14_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/lcd_gimp_image.h b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/lcd_gimp_image.h new file mode 100644 index 00000000..2a975159 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/lcd_gimp_image.h @@ -0,0 +1,42 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _GIMP_IMAGE_ +#define _GIMP_IMAGE_ + +#include + +typedef struct _SGIMPImage{ + uint32_t dwWidth; + uint32_t dwHeight; + uint32_t dwBytes_per_pixel; /* 3:RGB, 4:RGBA */ + uint8_t* pucPixel_data ; +} SGIMPImage ; + +#endif // _GIMP_IMAGE_ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/lcdd.h b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/lcdd.h new file mode 100644 index 00000000..59d5e6f0 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/lcdd.h @@ -0,0 +1,52 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface for LCD driver. + * + */ + +#ifndef LCDD_H +#define LCDD_H + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void LCDD_Initialize(uint8_t lcdMode, sXdmad * dmad, uint8_t cRotate); + +extern void LCDD_On(void); + +extern void LCDD_Off(void); + +extern void LCDD_SetBacklight (uint32_t step); + +#endif /* #ifndef LCDD_H */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/led.h b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/led.h new file mode 100644 index 00000000..9f0b6abf --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/led.h @@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \section Purpose + * + * Small set of functions for simple and portable LED usage. + * + * \section Usage + * + * -# Configure one or more LEDs using LED_Configure and + * LED_ConfigureAll. + * -# Set, clear and toggle LEDs using LED_Set, LED_Clear and + * LED_Toggle. + * + * LEDs are numbered starting from 0; the number of LEDs depend on the + * board being used. All the functions defined here will compile properly + * regardless of whether the LED is defined or not; they will simply + * return 0 when a LED which does not exist is given as an argument. + * Also, these functions take into account how each LED is connected on to + * board; thus, \ref LED_Set might change the level on the corresponding pin + * to 0 or 1, but it will always light the LED on; same thing for the other + * methods. + */ + +#ifndef _LED_ +#define _LED_ + +#include + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern uint32_t LED_Configure( uint32_t dwLed ); + +extern uint32_t LED_Set( uint32_t dwLed ); + +extern uint32_t LED_Clear( uint32_t dwLed ); + +extern uint32_t LED_Toggle( uint32_t dwLed ); + +#endif /* #ifndef LED_H */ + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/math.h b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/math.h new file mode 100644 index 00000000..0bb602d7 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/math.h @@ -0,0 +1,42 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _MATH_ +#define _MATH_ + +/*------------------------------------------------------------------------------ + * Exported functions + *------------------------------------------------------------------------------*/ + +extern uint32_t min( uint32_t dwA, uint32_t dwB ); +extern uint32_t absv( int32_t lValue ); +extern uint32_t power( uint32_t dwX, uint32_t dwY ); + +#endif /* #ifndef _MATH_ */ + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/mcan_config.h b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/mcan_config.h new file mode 100644 index 00000000..a40cea49 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/mcan_config.h @@ -0,0 +1,126 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \section Purpose + * + * Interface for configuring and using Timer Counter (TC) peripherals. + * + * \section Usage + * -# Optionally, use TC_FindMckDivisor() to let the program find the best + * TCCLKS field value automatically. + * -# Configure a Timer Counter in the desired mode using TC_Configure(). + * -# Start or stop the timer clock using TC_Start() and TC_Stop(). + */ + +#ifndef _MCAN_CONFIG_ +#define _MCAN_CONFIG_ + +/*------------------------------------------------------------------------------ + * Headers + *------------------------------------------------------------------------------*/ + + +/*------------------------------------------------------------------------------ + * Global functions + *------------------------------------------------------------------------------*/ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Programmable Clock Source for Baud Rate is Common To Both MCAN Controllers */ +#define MCAN_PROG_CLK_PRESCALER 1 /* /1 to /256 */ +// select one of the following for the programmable clock source +//#define MCAN_PROG_CLK_SELECT PMC_PCK_CSS_SLOW_CLK +//#define MCAN_PROG_CLK_SELECT PMC_PCK_CSS_MAIN_CLK +//#define MCAN_PROG_CLK_SELECT PMC_PCK_CSS_PLLA_CLK +//#define MCAN_PROG_CLK_SELECT PMC_PCK_CSS_UPLL_CLK +#define MCAN_PROG_CLK_SELECT PMC_PCK_CSS_MCK +#define MCAN_PROG_CLK_FREQ_HZ \ + ( (float) 150000000 / (float) MCAN_PROG_CLK_PRESCALER ) + +#define MCAN0_BIT_RATE_BPS 500000 +#define MCAN0_PROP_SEG 2 +#define MCAN0_PHASE_SEG1 11 +#define MCAN0_PHASE_SEG2 11 +#define MCAN0_SYNC_JUMP 4 + +#define MCAN0_FAST_BIT_RATE_BPS 2000000 +#define MCAN0_FAST_PROP_SEG 2 +#define MCAN0_FAST_PHASE_SEG1 4 +#define MCAN0_FAST_PHASE_SEG2 4 +#define MCAN0_FAST_SYNC_JUMP 2 + +#define MCAN0_NMBR_STD_FLTS 8 /* 128 max filters */ +#define MCAN0_NMBR_EXT_FLTS 8 /* 64 max filters */ +#define MCAN0_NMBR_RX_FIFO0_ELMTS 0 /* # of elements, 64 elements max */ +#define MCAN0_NMBR_RX_FIFO1_ELMTS 0 /* # of elements, 64 elements max */ +#define MCAN0_NMBR_RX_DED_BUF_ELMTS 16 /* # of elements, 64 elements max */ +#define MCAN0_NMBR_TX_EVT_FIFO_ELMTS 0 /* # of elements, 32 elements max */ +#define MCAN0_NMBR_TX_DED_BUF_ELMTS 4 /* # of elements, 32 elements max */ +#define MCAN0_NMBR_TX_FIFO_Q_ELMTS 0 /* # of elements, 32 elements max */ +#define MCAN0_RX_FIFO0_ELMT_SZ 8 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ +#define MCAN0_RX_FIFO1_ELMT_SZ 8 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ +#define MCAN0_RX_BUF_ELMT_SZ 8 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ +#define MCAN0_TX_BUF_ELMT_SZ 8 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ + +#define MCAN1_BIT_RATE_BPS 500000 +#define MCAN1_PROP_SEG 2 +#define MCAN1_PHASE_SEG1 11 +#define MCAN1_PHASE_SEG2 11 +#define MCAN1_SYNC_JUMP 4 + +#define MCAN1_FAST_BIT_RATE_BPS 2000000 +#define MCAN1_FAST_PROP_SEG 2 +#define MCAN1_FAST_PHASE_SEG1 4 +#define MCAN1_FAST_PHASE_SEG2 4 +#define MCAN1_FAST_SYNC_JUMP 2 + +#define MCAN1_NMBR_STD_FLTS 8 /* 128 max filters */ +#define MCAN1_NMBR_EXT_FLTS 8 /* 64 max filters */ +#define MCAN1_NMBR_RX_FIFO0_ELMTS 12 /* # of elements, 64 elements max */ +#define MCAN1_NMBR_RX_FIFO1_ELMTS 0 /* # of elements, 64 elements max */ +#define MCAN1_NMBR_RX_DED_BUF_ELMTS 4 /* # of elements, 64 elements max */ +#define MCAN1_NMBR_TX_EVT_FIFO_ELMTS 0 /* # of elements, 32 elements max */ +#define MCAN1_NMBR_TX_DED_BUF_ELMTS 4 /* # of elements, 32 elements max */ +#define MCAN1_NMBR_TX_FIFO_Q_ELMTS 4 /* # of elements, 32 elements max */ +#define MCAN1_RX_FIFO0_ELMT_SZ 8 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ +#define MCAN1_RX_FIFO1_ELMT_SZ 8 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ +#define MCAN1_RX_BUF_ELMT_SZ 64 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ +#define MCAN1_TX_BUF_ELMT_SZ 32 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _MCAN_CONFIG_ */ + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/rtc_calib.h b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/rtc_calib.h new file mode 100644 index 00000000..7d4e1253 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/rtc_calib.h @@ -0,0 +1,49 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface for Real Time Clock calibration (RTC) . + * + */ + +/** RTC crystal **/ + + +typedef struct{ + int8_t Tempr; + int16_t PPM; + uint8_t NEGPPM; + uint8_t HIGHPPM; + uint16_t CORRECTION; + }RTC_PPMLookup; + + +extern void RTC_ClockCalibration( Rtc* pRtc, int32_t CurrentTempr); diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/s25fl1.h b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/s25fl1.h new file mode 100644 index 00000000..36b0590b --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/s25fl1.h @@ -0,0 +1,255 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface for the S25fl1 Serial Flash driver. + * + */ + +#ifndef S25FL1_H +#define S25FL1_H +#define USE_QSPI_DMA +/*---------------------------------------------------------------------------- + * Macros + *----------------------------------------------------------------------------*/ + +#define Size(pAt25) ((pAt25)->pDesc->size) +#define PageSize(pAt25) ((pAt25)->pDesc->pageSize) +#define BlockSize(pAt25) ((pAt25)->pDesc->blockSize) +#define Name(pAt25) ((pAt25)->pDesc->name) +#define ManId(pAt25) (((pAt25)->pDesc->jedecId) & 0xFF) +#define PageNumber(pAt25) (Size(pAt25) / PageSize(pAt25)) +#define BlockNumber(pAt25) (Size(pAt25) / BlockSize(pAt25)) +#define PagePerBlock(pAt25) (BlockSize(pAt25) / PageSize(pAt25)) +#define BlockEraseCmd(pAt25) ((pAt25)->pDesc->blockEraseCmd) + +/*---------------------------------------------------------------------------- + * Local definitions + *----------------------------------------------------------------------------*/ + +/** Device is protected, operation cannot be carried out. */ +#define ERROR_PROTECTED 1 +/** Device is busy executing a command. */ +#define ERROR_BUSY 2 +/** There was a problem while trying to program page data. */ +#define ERROR_PROGRAM 3 +/** There was an SPI communication error. */ +#define ERROR_SPI 4 + +/** Device ready/busy status bit. */ +#define STATUS_RDYBSY (1 << 0) +/** Device is ready. */ +#define STATUS_RDYBSY_READY (0 << 0) +/** Device is busy with internal operations. */ +#define STATUS_RDYBSY_BUSY (1 << 0) +/** Write enable latch status bit. */ +#define STATUS_WEL (1 << 1) +/** Device is not write enabled. */ +#define STATUS_WEL_DISABLED (0 << 1) +/** Device is write enabled. */ +#define STATUS_WEL_ENABLED (1 << 1) +/** Software protection status bit-field. */ +#define STATUS_SWP (3 << 2) +/** All sectors are software protected. */ +#define STATUS_SWP_PROTALL (3 << 2) +/** Some sectors are software protected. */ +#define STATUS_SWP_PROTSOME (1 << 2) +/** No sector is software protected. */ +#define STATUS_SWP_PROTNONE (0 << 2) +/** Write protect pin status bit. */ +#define STATUS_WPP (1 << 4) +/** Write protect signal is not asserted. */ +#define STATUS_WPP_NOTASSERTED (0 << 4) +/** Write protect signal is asserted. */ +#define STATUS_WPP_ASSERTED (1 << 4) +/** Erase/program error bit. */ +#define STATUS_EPE (1 << 5) +/** Erase or program operation was successful. */ +#define STATUS_EPE_SUCCESS (0 << 5) +/** Erase or program error detected. */ +#define STATUS_EPE_ERROR (1 << 5) +/** Sector protection registers locked bit. */ +#define STATUS_SPRL (1 << 7) +/** Sector protection registers are unlocked. */ +#define STATUS_SPRL_UNLOCKED (0 << 7) +/** Sector protection registers are locked. */ +#define STATUS_SPRL_LOCKED (1 << 7) + +/** Quad enable bit */ +#define STATUS_QUAD_ENABLE (1 << 1) + /** Quad enable bit */ +#define STATUS_WRAP_ENABLE (0 << 4) + + /** Latency control bits */ +#define STATUS_LATENCY_CTRL (0xF << 0) + +#define STATUS_WRAP_BYTE (1 << 5) + +#define BLOCK_PROTECT_Msk (7 << 2) + +#define TOP_BTM_PROTECT_Msk (1 << 5) + +#define SEC_PROTECT_Msk (1 << 6) + +#define CHIP_PROTECT_Msk (0x1F << 2) + +/** Read array command code. */ +#define READ_ARRAY 0x0B +/** Read array (low frequency) command code. */ +#define READ_ARRAY_LF 0x03 +/** Fast Read array command code. */ +#define READ_ARRAY_DUAL 0x3B +/** Fast Read array command code. */ +#define READ_ARRAY_QUAD 0x6B +/** Fast Read array command code. */ +#define READ_ARRAY_DUAL_IO 0xBB +/** Fast Read array command code. */ +#define READ_ARRAY_QUAD_IO 0xEB +/** Block erase command code (4K block). */ +#define BLOCK_ERASE_4K 0x20 +/** Block erase command code (32K block). */ +#define BLOCK_ERASE_32K 0x52 +/** Block erase command code (64K block). */ +#define BLOCK_ERASE_64K 0xD8 +/** Chip erase command code 1. */ +#define CHIP_ERASE_1 0x60 +/** Chip erase command code 2. */ +#define CHIP_ERASE_2 0xC7 +/** Byte/page program command code. */ +#define BYTE_PAGE_PROGRAM 0x02 +/** Sequential program mode command code 1. */ +#define SEQUENTIAL_PROGRAM_1 0xAD +/** Sequential program mode command code 2. */ +#define SEQUENTIAL_PROGRAM_2 0xAF +/** Write enable command code. */ +#define WRITE_ENABLE 0x06 +/** Write disable command code. */ +#define WRITE_DISABLE 0x04 +/** Protect sector command code. */ +#define PROTECT_SECTOR 0x36 +/** Unprotected sector command code. */ +#define UNPROTECT_SECTOR 0x39 +/** Read sector protection registers command code. */ +#define READ_SECTOR_PROT 0x3C +/** Read status register command code. */ +#define READ_STATUS_1 0x05 + /** Read status register command code. */ +#define READ_STATUS_2 0x35 + /** Read status register command code. */ +#define READ_STATUS_3 0x33 +/** Write status register command code. */ +#define WRITE_STATUS 0x01 +/** Read manufacturer and device ID command code. */ +#define READ_JEDEC_ID 0x9F +/** Deep power-down command code. */ +#define DEEP_PDOWN 0xB9 +/** Resume from deep power-down command code. */ +#define RES_DEEP_PDOWN 0xAB +/** Resume from deep power-down command code. */ +#define SOFT_RESET_ENABLE 0x66 +/** Resume from deep power-down command code. */ +#define SOFT_RESET 0x99 +/** Resume from deep power-down command code. */ +#define WRAP_ENABLE 0x77 +/** Continuous Read Mode Reset command code. */ +#define CONT_MODE_RESET 0xFF + +/** SPI Flash Manufacturer JEDEC ID */ +#define ATMEL_SPI_FLASH 0x1F +#define ST_SPI_FLASH 0x20 +#define WINBOND_SPI_FLASH 0xEF +#define MACRONIX_SPI_FLASH 0xC2 +#define SST_SPI_FLASH 0xBF + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +uint32_t S25FL1D_ReadJedecId(void); + +void S25FL1D_InitFlashInterface(uint8_t Mode); + +void S25FL1D_SoftReset(void); + +void S25FL1D_ContReadModeReset(void); +unsigned char S25FL1D_Unprotect(void); + +unsigned char S25FL1D_Protect(uint32_t StartAddr, uint32_t Size); + +void S25FL1D_QuadMode(uint8_t Enable); + +void S25FL1D_EnableWrap(uint8_t ByetAlign); + +void S25FL1D_SetReadLatencyControl(uint8_t Latency); + +unsigned char S25FL1D_EraseChip(void); + +unsigned char S25FL1D_EraseSector( unsigned int address); + +unsigned char S25FL1D_Erase64KBlock( unsigned int address); + +unsigned char S25FL1D_Write( + uint32_t *pData, + uint32_t size, + uint32_t address, + uint8_t Secure); + +extern unsigned char S25FL1D_Read( + uint32_t *pData, + uint32_t size, + uint32_t address); + +extern unsigned char S25FL1D_ReadDual( + uint32_t *pData, + uint32_t size, + uint32_t address); + +extern unsigned char S25FL1D_ReadQuad( + uint32_t *pData, + uint32_t size, + uint32_t address); + +extern unsigned char S25FL1D_ReadDualIO( + uint32_t *pData, + uint32_t size, + uint32_t address, + uint8_t ContMode, + uint8_t Secure); + +extern unsigned char S25FL1D_ReadQuadIO( + uint32_t *pData, + uint32_t size, + uint32_t address, + uint8_t ContMode, + uint8_t Secure); + +#endif // #ifndef S25FL1_H + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/syscalls.h b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/syscalls.h new file mode 100644 index 00000000..c6c1deaf --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/syscalls.h @@ -0,0 +1,65 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file syscalls.h + * + * Implementation of newlib syscall. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + + +#include +#include +#include +#include + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern caddr_t _sbrk ( int incr ); + +extern int link( char *old, char *new ); + +extern int _close( int file ); + +extern int _fstat( int file, struct stat *st ); + +extern int _isatty( int file ); + +extern int _lseek( int file, int ptr, int dir ); + +extern int _read(int file, char *ptr, int len); + +extern int _write( int file, char *ptr, int len ); diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/wm8904.h b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/wm8904.h new file mode 100644 index 00000000..5f40d572 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libboard_samv7-ek/include/wm8904.h @@ -0,0 +1,160 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Implementation WM8904 driver. + * + */ + +#ifndef WM8904_H +#define WM8904_H + +#include "board.h" + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ +#define WM8904_CSB_STATE (0x0 << 0) + +/** Slave address */ +#define WM8904_SLAVE_ADDRESS 0x1a | WM8904_CSB_STATE +#define CS2100_SLAVE_ADDRESS 0x4E + + +/** Reset register*/ +#define WM8904_REG_RESET 0x00 + +/** Bias control 0 register*/ +#define WM8904_REG_BIAS_CTRL0 0x04 + +/** VMID control 0 register*/ +#define WM8904_REG_VMID_CTRL0 0x05 + +/** MIC Bias control 0 register*/ +#define WM8904_REG_MICBIAS_CTRL0 0x06 + +/** Bias control 1 register*/ +#define WM8904_REG_BIAS_CTRL1 0x07 + +/** Power management control 0 register*/ +#define WM8904_REG_POWER_MANG0 0x0C +/** Power management control 2 register*/ +#define WM8904_REG_POWER_MANG2 0x0E +/** Power management control 3 register*/ +#define WM8904_REG_POWER_MANG3 0x0F +/** Power management control 6 register*/ +#define WM8904_REG_POWER_MANG6 0x12 + +/** Clock rate0 register*/ +#define WM8904_REG_CLOCK_RATE0 0x14 +/** Clock rate1 register*/ +#define WM8904_REG_CLOCK_RATE1 0x15 + +/** Clock rate2 register*/ +#define WM8904_REG_CLOCK_RATE2 0x16 + +/** Audio interface0 register*/ +#define WM8904_REG_AUD_INF0 0x18 + +/** Audio interface1 register*/ +#define WM8904_REG_AUD_INF1 0x19 +/** Audio interface2 register*/ +#define WM8904_REG_AUD_INF2 0x1A +/** Audio interface3 register*/ +#define WM8904_REG_AUD_INF3 0x1B + +/** ADC digital 0 register*/ +#define WM8904_REG_ADC_DIG0 0x20 +/** ADC digital 1 register*/ +#define WM8904_REG_ADC_DIG1 0x21 + +/** Analogue left input 0 register*/ +#define WM8904_REG_ANALOGUE_LIN0 0x2C +/** Analogue right input 0 register*/ +#define WM8904_REG_ANALOGUE_RIN0 0x2D + +/** Analogue left input 1 register*/ +#define WM8904_REG_ANALOGUE_LIN1 0x2E +/** Analogue right input 1 register*/ +#define WM8904_REG_ANALOGUE_RIN1 0x2F + +/** Analogue left output 1 register*/ +#define WM8904_REG_ANALOGUE_LOUT1 0x39 +/** Analogue right output 1 register*/ +#define WM8904_REG_ANALOGUE_ROUT1 0x3A + +/** Analogue left output 2 register*/ +#define WM8904_REG_ANALOGUE_LOUT2 0x3B +/** Analogue right output 2 register*/ +#define WM8904_REG_ANALOGUE_ROUT2 0x3C + +/** Analogue output 12 ZC register*/ +#define WM8904_REG_ANALOGUE_OUT12ZC 0x3D + +/** DC servo 0 register*/ +#define WM8904_REG_DC_SERVO0 0x43 + +/** Analogue HP 0 register*/ +#define WM8904_REG_ANALOGUE_HP0 0x5A + +/** Charge pump 0 register*/ +#define WM8904_REG_CHARGE_PUMP0 0x62 + +/** Class W 0 register*/ +#define WM8904_REG_CLASS0 0x68 + +/** FLL control 1 register*/ +#define WM8904_REG_FLL_CRTL1 0x74 +/** FLL control 2 register*/ +#define WM8904_REG_FLL_CRTL2 0x75 +/** FLL control 3 register*/ +#define WM8904_REG_FLL_CRTL3 0x76 +/** FLL control 4 register*/ +#define WM8904_REG_FLL_CRTL4 0x77 +/** FLL control 5 register*/ +#define WM8904_REG_FLL_CRTL5 0x78 + +/** DUMMY register*/ +#define WM8904_REG_END 0xFF + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern uint16_t WM8904_Read(Twid *pTwid, uint32_t device, uint32_t regAddr); +extern void WM8904_Write(Twid *pTwid, uint32_t device, uint32_t regAddr, + uint16_t data); +extern uint8_t WM8904_Init(Twid *pTwid, uint32_t device, uint32_t PCK); +extern uint8_t WM8904_VolumeSet(Twid *pTwid, uint32_t device, uint16_t value); +extern void WM8904_IN2R_IN1L(Twid *pTwid, uint32_t device); +#endif // WM8904_H + + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/chip.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/chip.h new file mode 100644 index 00000000..0aef4dc6 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/chip.h @@ -0,0 +1,124 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef SAMS7_CHIP_H +#define SAMS7_CHIP_H + +#include "compiler.h" + + +/************************************************* + * Memory type and its attribute + *************************************************/ +#define SHAREABLE 1 +#define NON_SHAREABLE 0 + /********************************************************************************************************************************************************************* + * Memory Type Definition Memory TEX attribute C attribute B attribute S attribute + **********************************************************************************************************************************************************************/ + +#define STRONGLY_ORDERED_SHAREABLE_TYPE (( 0x00 << MPU_RASR_TEX_Pos ) | ( DISABLE << MPU_RASR_C_Pos ) | ( DISABLE << MPU_RASR_B_Pos )) // DO not care // +#define SHAREABLE_DEVICE_TYPE (( 0x00 << MPU_RASR_TEX_Pos ) | ( DISABLE << MPU_RASR_C_Pos ) | ( ENABLE << MPU_RASR_B_Pos )) // DO not care // +#define INNER_OUTER_NORMAL_WT_NWA_TYPE(x) (( 0x00 << MPU_RASR_TEX_Pos ) | ( ENABLE << MPU_RASR_C_Pos ) | ( DISABLE << MPU_RASR_B_Pos ) | ( x << MPU_RASR_S_Pos )) +#define INNER_OUTER_NORMAL_WB_NWA_TYPE(x) (( 0x00 << MPU_RASR_TEX_Pos ) | ( ENABLE << MPU_RASR_C_Pos ) | ( ENABLE << MPU_RASR_B_Pos ) | ( x << MPU_RASR_S_Pos )) +#define INNER_OUTER_NORMAL_NOCACHE_TYPE(x) (( 0x01 << MPU_RASR_TEX_Pos ) | ( DISABLE << MPU_RASR_C_Pos ) | ( DISABLE << MPU_RASR_B_Pos ) | ( x << MPU_RASR_S_Pos )) +#define INNER_OUTER_NORMAL_WB_RWA_TYPE(x) (( 0x01 << MPU_RASR_TEX_Pos ) | ( ENABLE << MPU_RASR_C_Pos ) | ( ENABLE << MPU_RASR_B_Pos ) | ( x << MPU_RASR_S_Pos )) +#define NON_SHAREABLE_DEVICE_TYPE (( 0x02 << MPU_RASR_TEX_Pos ) | ( DISABLE << MPU_RASR_C_Pos ) | ( DISABLE << MPU_RASR_B_Pos )) // DO not care // + + /* Normal memory attributes with outer capability rules to Non_Cacable */ + +#define INNER_NORMAL_NOCACHE_TYPE(x) (( 0x04 << MPU_RASR_TEX_Pos ) | ( DISABLE << MPU_RASR_C_Pos ) | ( DISABLE << MPU_RASR_B_Pos ) | ( x << MPU_RASR_S_Pos )) +#define INNER_NORMAL_WB_RWA_TYPE(x) (( 0x04 << MPU_RASR_TEX_Pos ) | ( DISABLE << MPU_RASR_C_Pos ) | ( ENABLE << MPU_RASR_B_Pos ) | ( x << MPU_RASR_S_Pos )) +#define INNER_NORMAL_WT_NWA_TYPE(x) (( 0x04 << MPU_RASR_TEX_Pos ) | ( ENABLE << MPU_RASR_C_Pos ) | ( DISABLE << MPU_RASR_B_Pos ) | ( x << MPU_RASR_S_Pos )) +#define INNER_NORMAL_WB_NWA_TYPE(x) (( 0x04 << MPU_RASR_TEX_Pos ) | ( ENABLE << MPU_RASR_C_Pos ) | ( ENABLE << MPU_RASR_B_Pos ) | ( x << MPU_RASR_S_Pos )) + +/* SCB Interrupt Control State Register Definitions */ +#ifndef SCB_VTOR_TBLBASE_Pos +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ +#endif + + +/* + * Peripherals + */ +#include "include/acc.h" +#include "include/aes.h" +#include "include/afec.h" +#include "include/efc.h" +#include "include/pio.h" +#include "include/pio_it.h" +#include "include/efc.h" +#include "include/rstc.h" +#include "include/mpu.h" +#include "include/gmac.h" +#include "include/gmacd.h" +#include "include/video.h" +#include "include/icm.h" +#include "include/isi.h" +#include "include/exceptions.h" +#include "include/pio_capture.h" +#include "include/rtc.h" +#include "include/rtt.h" +#include "include/tc.h" +#include "include/timetick.h" +#include "include/twi.h" +#include "include/flashd.h" +#include "include/pmc.h" +#include "include/pwmc.h" +#include "include/mcan.h" +#include "include/supc.h" +#include "include/usart.h" +#include "include/uart.h" +#include "include/isi.h" +#include "include/hsmci.h" +#include "include/ssc.h" +#include "include/twi.h" +#include "include/trng.h" +#include "include/wdt.h" +#include "include/spi.h" +#include "include/qspi.h" +#include "include/trace.h" +#include "include/xdmac.h" +#include "include/xdma_hardware_interface.h" +#include "include/xdmad.h" +#include "include/mcid.h" +#include "include/twid.h" +#include "include/spi_dma.h" +#include "include/qspi_dma.h" +#include "include/uart_dma.h" +#include "include/usart_dma.h" +#include "include/twid.h" +#include "include/afe_dma.h" +#include "include/dac_dma.h" +#include "include/usbhs.h" + +#define ENABLE_PERIPHERAL(dwId) PMC_EnablePeripheral( dwId ) +#define DISABLE_PERIPHERAL(dwId) PMC_DisablePeripheral( dwId ) + +#endif /* SAMS7_CHIP_H */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/compiler.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/compiler.h new file mode 100644 index 00000000..53c0d625 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/compiler.h @@ -0,0 +1,442 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _COMPILER_H_ +#define _COMPILER_H_ + +/* + * Peripherals registers definitions + */ +#include "include/samv7/samv71.h" + + +//_____ D E C L A R A T I O N S ____________________________________________ + +#ifndef __ASSEMBLY__ + +#include +#include +#include +#include + +/* Define WEAK attribute */ +#if defined ( __CC_ARM ) + #define WEAK __attribute__ ((weak)) +#elif defined ( __ICCARM__ ) + #define WEAK __weak +#elif defined ( __GNUC__ ) + #define WEAK __attribute__ ((weak)) +#endif + +/* Define Compiler name of tool chains */ +#if defined ( __CC_ARM ) + #define COMPILER_NAME "KEIL" +#elif defined ( __ICCARM__ ) + #define COMPILER_NAME "IAR" +#elif defined ( __GNUC__ ) + #define COMPILER_NAME "GCC" +#endif + +/* Define NO_INIT attribute */ +#if defined ( __CC_ARM ) + #define NO_INIT +#elif defined ( __ICCARM__ ) + #define NO_INIT __no_init +#elif defined ( __GNUC__ ) + #define NO_INIT +#endif + + +/* Define memory sync for tool chains */ +#if defined ( __CC_ARM ) + #define memory_sync() __dsb(15);__isb(15); +#elif defined ( __ICCARM__ ) + #define memory_sync() __DSB();__ISB(); +#elif defined ( __GNUC__ ) + #define memory_sync() __DSB();__ISB(); +#endif + +/* Define memory barrier for tool chains */ +#if defined ( __CC_ARM ) + #define memory_barrier() __dmb(15); +#elif defined ( __ICCARM__ ) + #define memory_barrier() __DMB(); +#elif defined ( __GNUC__ ) + #define memory_barrier() __DMB(); +#endif + +/*! \name Token Paste + * + * Paste N preprocessing tokens together, these tokens being allowed to be \#defined. + * + * May be used only within macros with the tokens passed as arguments if the tokens are \#defined. + * + * For example, writing TPASTE2(U, WIDTH) within a macro \#defined by + * UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH \#defined as 32 is + * equivalent to writing U32. + */ +//! @{ +#define TPASTE2( a, b) a##b +#define TPASTE3( a, b, c) a##b##c +//! @} + +/*! \name Absolute Token Paste + * + * Paste N preprocessing tokens together, these tokens being allowed to be \#defined. + * + * No restriction of use if the tokens are \#defined. + * + * For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH \#defined + * as 32 is equivalent to writing U32. + */ +//! @{ +#define ATPASTE2( a, b) TPASTE2( a, b) +#define ATPASTE3( a, b, c) TPASTE3( a, b, c) +//! @} + + +/** + * \brief Emit the compiler pragma \a arg. + * + * \param arg The pragma directive as it would appear after \e \#pragma + * (i.e. not stringified). + */ +#define COMPILER_PRAGMA(arg) _Pragma(#arg) + +/** + * \def COMPILER_PACK_SET(alignment) + * \brief Set maximum alignment for subsequent structure and union + * definitions to \a alignment. + */ +#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment)) + +/** + * \def COMPILER_PACK_RESET() + * \brief Set default alignment for subsequent structure and union + * definitions. + */ +#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack()) + +/** + * \brief Set user-defined section. + * Place a data object or a function in a user-defined section. + */ +#if defined ( __CC_ARM ) + #define COMPILER_SECTION(a) __attribute__((__section__(a))) +#elif defined ( __ICCARM__ ) + #define COMPILER_SECTION(a) COMPILER_PRAGMA(location = a) +#elif defined ( __GNUC__ ) + #define COMPILER_SECTION(a) __attribute__((__section__(a))) +#endif + +/** + * \brief Set aligned boundary. + */ +#if defined ( __CC_ARM ) + #define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) +#elif defined ( __ICCARM__ ) + #define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a) +#elif defined ( __GNUC__ ) + #define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) +#endif + +/** + * \brief Set word-aligned boundary. + */ + +#if defined ( __CC_ARM ) + #define COMPILER_WORD_ALIGNED __attribute__((__aligned__(4))) +#elif defined ( __ICCARM__ ) + #define COMPILER_WORD_ALIGNED COMPILER_PRAGMA(data_alignment = 4) +#elif defined ( __GNUC__ ) + #define COMPILER_WORD_ALIGNED __attribute__((__aligned__(4))) +#endif + + + +/*! \name Mathematics + * + * The same considerations as for clz and ctz apply here but GCC does not + * provide built-in functions to access the assembly instructions abs, min and + * max and it does not produce them by itself in most cases, so two sets of + * macros are defined here: + * - Abs, Min and Max to apply to constant expressions (values known at + * compile time); + * - abs, min and max to apply to non-constant expressions (values unknown at + * compile time), abs is found in stdlib.h. + */ +//! @{ + +/*! \brief Takes the absolute value of \a a. + * + * \param a Input value. + * + * \return Absolute value of \a a. + * + * \note More optimized if only used with values known at compile time. + */ +#define Abs(a) (((a) < 0 ) ? -(a) : (a)) + +/*! \brief Takes the minimal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Minimal value of \a a and \a b. + * + * \note More optimized if only used with values known at compile time. + */ +#define Min(a, b) (((a) < (b)) ? (a) : (b)) + +/*! \brief Takes the maximal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Maximal value of \a a and \a b. + * + * \note More optimized if only used with values known at compile time. + */ +#define Max(a, b) (((a) > (b)) ? (a) : (b)) + +// abs() is already defined by stdlib.h + +/*! \brief Takes the minimal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Minimal value of \a a and \a b. + * + * \note More optimized if only used with values unknown at compile time. + */ +#define min(a, b) Min(a, b) + +/*! \brief Takes the maximal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Maximal value of \a a and \a b. + * + * \note More optimized if only used with values unknown at compile time. + */ +#define max(a, b) Max(a, b) + +//! @} + +#define be32_to_cpu(x) __REV(x) +#define cpu_to_be32(x) __REV(x) +#define BE32_TO_CPU(x) __REV(x) +#define CPU_TO_BE32(x) __REV(x) + +/** + * \def UNUSED + * \brief Marking \a v as a unused parameter or value. + */ +#define UNUSED(v) (void)(v) + +/** + * \weakgroup interrupt_group + * + * @{ + */ + +/** + * \name Interrupt Service Routine definition + * + * @{ + */ + +/** + * \brief Initialize interrupt vectors + * + * For NVIC the interrupt vectors are put in vector table. So nothing + * to do to initialize them, except defined the vector function with + * right name. + * + * This must be called prior to \ref irq_register_handler. + */ +# define irq_initialize_vectors() \ + do { \ + } while(0) + +/** + * \brief Register handler for interrupt + * + * For NVIC the interrupt vectors are put in vector table. So nothing + * to do to register them, except defined the vector function with + * right name. + * + * Usage: + * \code + irq_initialize_vectors(); + irq_register_handler(foo_irq_handler); +\endcode + * + * \note The function \a func must be defined with the \ref ISR macro. + * \note The functions prototypes can be found in the device exception header + * files (exceptions.h). + */ +# define irq_register_handler(int_num, int_prio) \ + NVIC_ClearPendingIRQ( (IRQn_Type)int_num); \ + NVIC_SetPriority( (IRQn_Type)int_num, int_prio); \ + NVIC_EnableIRQ( (IRQn_Type)int_num); \ + +//@} + + +# define cpu_irq_enable() \ + do { \ + /*g_interrupt_enabled = true; */ \ + __DMB(); \ + __enable_irq(); \ + } while (0) +# define cpu_irq_disable() \ + do { \ + __disable_irq(); \ + __DMB(); \ + /*g_interrupt_enabled = false; */ \ + } while (0) + +typedef uint32_t irqflags_t; + +#if !defined(__DOXYGEN__) +extern volatile bool g_interrupt_enabled; +#endif + +#define cpu_irq_is_enabled() (__get_PRIMASK() == 0) + +static volatile uint32_t cpu_irq_critical_section_counter; +static volatile bool cpu_irq_prev_interrupt_state; + +static inline irqflags_t cpu_irq_save(void) +{ + irqflags_t flags = cpu_irq_is_enabled(); + cpu_irq_disable(); + return flags; +} + +static inline bool cpu_irq_is_enabled_flags(irqflags_t flags) +{ + return (flags); +} + +static inline void cpu_irq_restore(irqflags_t flags) +{ + if (cpu_irq_is_enabled_flags(flags)) + cpu_irq_enable(); +} +/* +void cpu_irq_enter_critical(void); +void cpu_irq_leave_critical(void);*/ + +/** + * \weakgroup interrupt_deprecated_group + * @{ + */ + +#define Enable_global_interrupt() cpu_irq_enable() +#define Disable_global_interrupt() cpu_irq_disable() +#define Is_global_interrupt_enabled() cpu_irq_is_enabled() + + +//_____ M A C R O S ________________________________________________________ + +/*! \name Usual Constants + */ +//! @{ +#define DISABLE 0 +#define ENABLE 1 +#define DISABLED 0 +#define ENABLED 1 +#define OFF 0 +#define ON 1 +#define FALSE 0 +#define TRUE 1 +#ifndef __cplusplus +#if !defined(__bool_true_false_are_defined) +#define false FALSE +#define true TRUE +#endif +#endif +#define KO 0 +#define OK 1 +#define PASS 0 +#define FAIL 1 +#define LOW 0 +#define HIGH 1 +#define CLR 0 +#define SET 1 +//! @} + +/*! \brief Counts the trailing zero bits of the given value considered as a 32-bit integer. + * + * \param u Value of which to count the trailing zero bits. + * + * \return The count of trailing zero bits in \a u. + */ +#define ctz(u) ((u) & (1ul << 0) ? 0 : \ + (u) & (1ul << 1) ? 1 : \ + (u) & (1ul << 2) ? 2 : \ + (u) & (1ul << 3) ? 3 : \ + (u) & (1ul << 4) ? 4 : \ + (u) & (1ul << 5) ? 5 : \ + (u) & (1ul << 6) ? 6 : \ + (u) & (1ul << 7) ? 7 : \ + (u) & (1ul << 8) ? 8 : \ + (u) & (1ul << 9) ? 9 : \ + (u) & (1ul << 10) ? 10 : \ + (u) & (1ul << 11) ? 11 : \ + (u) & (1ul << 12) ? 12 : \ + (u) & (1ul << 13) ? 13 : \ + (u) & (1ul << 14) ? 14 : \ + (u) & (1ul << 15) ? 15 : \ + (u) & (1ul << 16) ? 16 : \ + (u) & (1ul << 17) ? 17 : \ + (u) & (1ul << 18) ? 18 : \ + (u) & (1ul << 19) ? 19 : \ + (u) & (1ul << 20) ? 20 : \ + (u) & (1ul << 21) ? 21 : \ + (u) & (1ul << 22) ? 22 : \ + (u) & (1ul << 23) ? 23 : \ + (u) & (1ul << 24) ? 24 : \ + (u) & (1ul << 25) ? 25 : \ + (u) & (1ul << 26) ? 26 : \ + (u) & (1ul << 27) ? 27 : \ + (u) & (1ul << 28) ? 28 : \ + (u) & (1ul << 29) ? 29 : \ + (u) & (1ul << 30) ? 30 : \ + (u) & (1ul << 31) ? 31 : \ + 32) + +#endif // __ASSEMBLY__ + +#endif // _COMPILER_H_ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/acc.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/acc.h new file mode 100644 index 00000000..73c945a7 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/acc.h @@ -0,0 +1,151 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \section Purpose + * + * Interface for configuration the Analog-to-Digital Converter (ACC) peripheral. + * + * \section Usage + * + * -# Configurate the pins for ACC + * -# Initialize the ACC with ACC_Initialize(). + * -# Select the active channel using ACC_EnableChannel() + * -# Start the conversion with ACC_StartConversion() + * -# Wait the end of the conversion by polling status with ACC_GetStatus() + * -# Finally, get the converted data using ACC_GetConvertedData() + * + */ +#ifndef _ACC_ +#define _ACC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +#include +#include + +/*------------------------------------------------------------------------------ + * Definitions + *------------------------------------------------------------------------------*/ +#define ACC_SELPLUS_AD12B0 0 +#define ACC_SELPLUS_AD12B1 1 +#define ACC_SELPLUS_AD12B2 2 +#define ACC_SELPLUS_AD12B3 3 +#define ACC_SELPLUS_AD12B4 4 +#define ACC_SELPLUS_AD12B5 5 +#define ACC_SELPLUS_AD12B6 6 +#define ACC_SELPLUS_AD12B7 7 +#define ACC_SELMINUS_TS 0 +#define ACC_SELMINUS_ADVREF 1 +#define ACC_SELMINUS_DAC0 2 +#define ACC_SELMINUS_DAC1 3 +#define ACC_SELMINUS_AD12B0 4 +#define ACC_SELMINUS_AD12B1 5 +#define ACC_SELMINUS_AD12B2 6 +#define ACC_SELMINUS_AD12B3 7 + +#ifdef __cplusplus + extern "C" { +#endif + +/*------------------------------------------------------------------------------ + * Macros function of register access + *------------------------------------------------------------------------------*/ +#define ACC_CfgModeReg(pAcc, mode) { \ + (pAcc)->ACC_MR = (mode);\ + } + +#define ACC_GetModeReg( pAcc ) ((pAcc)->ACC_MR) + +#define ACC_StartConversion( pAcc ) ((pAcc)->ACC_CR = ACC_CR_START) + +#define ACC_SoftReset( pAcc ) ((pAcc)->ACC_CR = ACC_CR_SWRST) + +#define ACC_EnableChannel( pAcc, dwChannel ) {\ + assert( dwChannel < 16 ) ;\ + (pAcc)->ACC_CHER = (1 << (dwChannel));\ + } + +#define ACC_DisableChannel( pAcc, dwChannel ) {\ + assert( dwChannel < 16 ) ;\ + (pAcc)->ACC_CHDR = (1 << (dwChannel));\ + } + +#define ACC_EnableIt( pAcc, dwMode ) {\ + assert( ((dwMode)&0xFFF00000)== 0 ) ;\ + (pAcc)->ACC_IER = (dwMode);\ + } + +#define ACC_DisableIt( pAcc, dwMode ) {\ + assert( ((dwMode)&0xFFF00000)== 0 ) ;\ + (pAcc)->ACC_IDR = (dwMode);\ + } + +#define ACC_EnableDataReadyIt( pAcc ) ((pAcc)->ACC_IER = AT91C_ACC_DRDY) + +#define ACC_GetStatus( pAcc ) ((pAcc)->ACC_ISR) + +#define ACC_GetChannelStatus( pAcc ) ((pAcc)->ACC_CHSR) + +#define ACC_GetInterruptMaskStatus( pAcc ) ((pAcc)->ACC_IMR) + +#define ACC_GetLastConvertedData( pAcc ) ((pAcc)->ACC_LCDR) + +#define ACC_CfgAnalogCtrlReg( pAcc, dwMode ) {\ + assert( ((dwMode) & 0xFFFCFF3C) == 0 ) ;\ + (pAcc)->ACC_ACR = (dwMode);\ + } + +#define ACC_CfgExtModeReg( pAcc, extmode ) {\ + assert( ((extmode) & 0xFF00FFFE) == 0 ) ;\ + (pAcc)->ACC_EMR = (extmode);\ + } + +#define ACC_GetAnalogCtrlReg( pAcc ) ((pAcc)->ACC_ACR) + +/*------------------------------------------------------------------------------ + * Exported functions + *------------------------------------------------------------------------------*/ +extern void ACC_Configure( Acc *pAcc, uint8_t idAcc, uint8_t ucSelplus, + uint8_t ucSelminus, uint16_t wAc_en, uint16_t wEdge, uint16_t wInvert ) ; + +extern void ACC_SetComparisonPair( Acc *pAcc, uint8_t ucSelplus, uint8_t ucSelminus ) ; + +extern uint32_t ACC_GetComparisonResult( Acc* pAcc, uint32_t dwStatus ) ; + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _ACC_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/adc.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/adc.h new file mode 100644 index 00000000..d919742a --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/adc.h @@ -0,0 +1,178 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \section Purpose + * + * Interface for configuration the Analog-to-Digital Converter (ADC) peripheral. + * + * \section Usage + * + * -# Configurate the pins for ADC. + * -# Initialize the ADC with ADC_Initialize(). + * -# Set ADC clock and timing with ADC_SetClock() and ADC_SetTiming(). + * -# Select the active channel using ADC_EnableChannel(). + * -# Start the conversion with ADC_StartConversion(). + * -# Wait the end of the conversion by polling status with ADC_GetStatus(). + * -# Finally, get the converted data using ADC_GetConvertedData() or + * ADC_GetLastConvertedData(). + * +*/ +#ifndef _ADC_ +#define _ADC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include +#include + +/*------------------------------------------------------------------------------ + * Definitions + *------------------------------------------------------------------------------*/ + +/* Max. ADC Clock Frequency (Hz) */ +#define ADC_CLOCK_MAX 20000000 + +/* Max. normal ADC startup time (us) */ +#define ADC_STARTUP_NORMAL_MAX 40 +/* Max. fast ADC startup time (us) */ +#define ADC_STARTUP_FAST_MAX 12 + +/* Definitions for ADC channels */ +#define ADC_CHANNEL_0 0 +#define ADC_CHANNEL_1 1 +#define ADC_CHANNEL_2 2 +#define ADC_CHANNEL_3 3 +#define ADC_CHANNEL_4 4 +#define ADC_CHANNEL_5 5 +#define ADC_CHANNEL_6 6 +#define ADC_CHANNEL_7 7 +#define ADC_CHANNEL_8 8 +#define ADC_CHANNEL_9 9 +#define ADC_CHANNEL_10 10 +#define ADC_CHANNEL_11 11 +#define ADC_CHANNEL_12 12 +#define ADC_CHANNEL_13 13 +#define ADC_CHANNEL_14 14 +#define ADC_CHANNEL_15 15 + +#ifdef __cplusplus + extern "C" { +#endif + +/*------------------------------------------------------------------------------ + * Macros function of register access + *------------------------------------------------------------------------------*/ + +#define ADC_GetModeReg( pAdc ) ((pAdc)->ADC_MR) + +#define ADC_StartConversion( pAdc ) ((pAdc)->ADC_CR = ADC_CR_START) + +#define ADC_SetCalibMode(pAdc) ((pAdc)->ADC_CR |= ADC_CR_AUTOCAL) + +#define ADC_EnableChannel( pAdc, dwChannel ) {\ + (pAdc)->ADC_CHER = (1 << (dwChannel));\ + } + +#define ADC_DisableChannel(pAdc, dwChannel) {\ + (pAdc)->ADC_CHDR = (1 << (dwChannel));\ + } + +#define ADC_EnableIt(pAdc, dwMode) {\ + (pAdc)->ADC_IER = (dwMode);\ + } + +#define ADC_DisableIt(pAdc, dwMode) {\ + (pAdc)->ADC_IDR = (dwMode);\ + } + +#define ADC_SetChannelGain(pAdc,dwMode) {\ + (pAdc)->ADC_CGR = dwMode;\ + } + +#define ADC_SetChannelOffset(pAdc,dwMode) {\ + (pAdc)->ADC_COR = dwMode;\ + } + +#define ADC_EnableDataReadyIt(pAdc) ((pAdc)->ADC_IER = ADC_IER_DRDY) + +#define ADC_GetStatus(pAdc) ((pAdc)->ADC_ISR) + +#define ADC_GetCompareMode(pAdc) (((pAdc)->ADC_EMR)& (ADC_EMR_CMPMODE_Msk)) + +#define ADC_GetChannelStatus(pAdc) ((pAdc)->ADC_CHSR) + +#define ADC_GetInterruptMaskStatus(pAdc) ((pAdc)->ADC_IMR) + +#define ADC_GetLastConvertedData(pAdc) ((pAdc)->ADC_LCDR) + +/*------------------------------------------------------------------------------ + * Exported functions + *------------------------------------------------------------------------------*/ +extern void ADC_Initialize( Adc* pAdc, uint32_t dwId ); +extern uint32_t ADC_SetClock( Adc* pAdc, uint32_t dwPres, uint32_t dwMck ); +extern void ADC_SetTiming( Adc* pAdc, uint32_t dwStartup, uint32_t dwTracking, + uint32_t dwSettling ); +extern void ADC_SetTrigger( Adc* pAdc, uint32_t dwTrgSel ); +extern void ADC_SetTriggerMode(Adc *pAdc, uint32_t dwMode); +extern void ADC_SetLowResolution( Adc* pAdc, uint32_t bEnDis ); +extern void ADC_SetSleepMode( Adc *pAdc, uint8_t bEnDis ); +extern void ADC_SetFastWakeup( Adc *pAdc, uint8_t bEnDis ); +extern void ADC_SetSequenceMode( Adc *pAdc, uint8_t bEnDis ); +extern void ADC_SetSequence( Adc *pAdc, uint32_t dwSEQ1, uint32_t dwSEQ2 ); +extern void ADC_SetSequenceByList( Adc *pAdc, uint8_t ucChList[], uint8_t ucNumCh ); +extern void ADC_SetAnalogChange( Adc *pAdc, uint8_t bEnDis ); +extern void ADC_SetTagEnable( Adc *pAdc, uint8_t bEnDis ); +extern void ADC_SetCompareChannel( Adc* pAdc, uint32_t dwChannel ) ; +extern void ADC_SetCompareMode( Adc* pAdc, uint32_t dwMode ) ; +extern void ADC_SetComparisonWindow( Adc* pAdc, uint32_t dwHi_Lo ) ; +extern uint8_t ADC_CheckConfiguration( Adc* pAdc, uint32_t dwMcK ) ; +extern uint32_t ADC_GetConvertedData( Adc* pAdc, uint32_t dwChannel ) ; +extern void ADC_SetTsAverage(Adc* pADC, uint32_t dwAvg2Conv); +extern uint32_t ADC_GetTsXPosition(Adc *pADC); +extern uint32_t ADC_GetTsYPosition(Adc *pADC); +extern uint32_t ADC_GetTsPressure(Adc *pADC); +extern void ADC_SetTsDebounce(Adc *pADC, uint32_t dwTime); +extern void ADC_SetTsPenDetect(Adc* pADC, uint8_t bEnDis); +extern void ADC_SetStartupTime( Adc *pAdc, uint32_t dwUs ); +extern void ADC_SetTrackingTime( Adc *pAdc, uint32_t dwNs ); +extern void ADC_SetTriggerPeriod(Adc *pAdc, uint32_t dwPeriod); +extern void ADC_SetTsMode(Adc* pADC, uint32_t dwMode); +extern void ADC_TsCalibration( Adc *pAdc ); + + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _ADC_ */ + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/aes.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/aes.h new file mode 100644 index 00000000..d028b3ee --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/aes.h @@ -0,0 +1,68 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _AES_ +#define _AES_ + +/*------------------------------------------------------------------------------ + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + + +/*----------------------------------------------------------------------------*/ +/* Definition */ +/*----------------------------------------------------------------------------*/ +#define AES_MR_CIPHER_ENCRYPT 1 +#define AES_MR_CIPHER_DECRYPT 0 +/*----------------------------------------------------------------------------*/ +/* Exported functions */ +/*----------------------------------------------------------------------------*/ + +extern void AES_Start(void); +extern void AES_SoftReset(void); +extern void AES_Recount(void); +extern void AES_Configure(uint32_t mode); +extern void AES_EnableIt(uint32_t sources); +extern void AES_DisableIt(uint32_t sources); +extern uint32_t AES_GetStatus(void); +extern void AES_WriteKey(const uint32_t *pKey, uint32_t keyLength); +extern void AES_SetInput(uint32_t *data); +extern void AES_GetOutput(uint32_t *data); +extern void AES_SetVector(const uint32_t *pVector); +extern void AES_SetAadLen(uint32_t len); +extern void AES_SetDataLen(uint32_t len); +extern void AES_SetGcmHash(uint32_t * hash); +extern void AES_GetGcmTag(uint32_t * tag); +extern void AES_GetGcmCounter(uint32_t * counter); +extern void AES_GetGcmH(uint32_t *h); + + +#endif /* #ifndef _AES_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/afe_dma.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/afe_dma.h new file mode 100644 index 00000000..d769900c --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/afe_dma.h @@ -0,0 +1,118 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \section Purpose + * + * Interface for configuration the Analog-to-Digital Converter (AFEC) peripheral. + * + * \section Usage + * + * -# Configurate the pins for AFEC. + * -# Initialize the AFEC with AFEC_Initialize(). + * -# Set AFEC clock and timing with AFEC_SetClock() and AFEC_SetTiming(). + * -# Select the active channel using AFEC_EnableChannel(). + * -# Start the conversion with AFEC_StartConversion(). + * -# Wait the end of the conversion by polling status with AFEC_GetStatus(). + * -# Finally, get the converted data using AFEC_GetConvertedData() or + * AFEC_GetLastConvertedData(). + * +*/ +#ifndef _AFE_DMA_ +#define _AFE_DMA_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** AFE transfer complete callback. */ +typedef void (*AfeCallback)( uint8_t, void* ) ; + +/** \brief Spi Transfer Request prepared by the application upper layer. + * + * This structure is sent to the AFE_SendCommand function to start the transfer. + * At the end of the transfer, the callback is invoked by the interrupt handler. + */ +typedef struct +{ + /** Pointer to the Rx data. */ + uint32_t *pRxBuff; + /** Rx size in bytes. */ + uint16_t RxSize; + /** Callback function invoked at the end of transfer. */ + AfeCallback callback; + /** Callback arguments. */ + void *pArgument; +} AfeCmd ; + + +/** Constant structure associated with AFE port. This structure prevents + client applications to have access in the same time. */ +typedef struct +{ + /** Pointer to AFE Hardware registers */ + Afec* pAfeHw ; + /** Current SpiCommand being processed */ + AfeCmd *pCurrentCommand ; + /** Pointer to DMA driver */ + sXdmad* pXdmad; + /** AFEC Id as defined in the product datasheet */ + uint8_t afeId ; + /** Mutual exclusion semaphore. */ + volatile int8_t semaphore ; +} AfeDma; + + +/*------------------------------------------------------------------------------ + * Definitions + *----------------------------------------------------------------------------*/ +#define AFE_OK 0 +#define AFE_ERROR 1 +#define AFE_ERROR_LOCK 2 +/*------------------------------------------------------------------------------ + * Exported functions + *----------------------------------------------------------------------------*/ +extern uint32_t Afe_ConfigureDma( AfeDma *pAfed , + Afec *pAfeHw , + uint8_t AfeId, + sXdmad *pXdmad ); +extern uint32_t Afe_SendData( AfeDma *pAfed, AfeCmd *pCommand); + + +#endif /* #ifndef _AFE_DMA_ */ + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/afec.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/afec.h new file mode 100644 index 00000000..ee9a1646 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/afec.h @@ -0,0 +1,187 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \section Purpose + * + * Interface for configuration the Analog-to-Digital Converter (AFEC) peripheral. + * + * \section Usage + * + * -# Configurate the pins for AFEC. + * -# Initialize the AFEC with AFEC_Initialize(). + * -# Set AFEC clock and timing with AFEC_SetClock() and AFEC_SetTiming(). + * -# Select the active channel using AFEC_EnableChannel(). + * -# Start the conversion with AFEC_StartConversion(). + * -# Wait the end of the conversion by polling status with AFEC_GetStatus(). + * -# Finally, get the converted data using AFEC_GetConvertedData() or + * AFEC_GetLastConvertedData(). + * +*/ +#ifndef _AFEC_ +#define _AFEC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include +#include + +/*------------------------------------------------------------------------------ + * Definitions + *------------------------------------------------------------------------------*/ + +/* -------- AFEC_MR : (AFEC Offset: 0x04) AFEC Mode Register -------- */ +#define AFEC_MR_SETTLING_Pos 20 +#define AFEC_MR_SETTLING_Msk (0x3u << AFEC_MR_SETTLING_Pos) +/**< \brief (AFEC_MR) Trigger Selection */ +#define AFEC_MR_SETTLING_AST3 (0x0u << 20) +/**< \brief (AFEC_MR) ADC_SETTLING_AST3 3 periods of AFEClock */ +#define AFEC_MR_SETTLING_AST5 (0x1u << 20) +/**< \brief (AFEC_MR) ADC_SETTLING_AST5 5 periods of AFEClock */ +#define AFEC_MR_SETTLING_AST9 (0x2u << 20) +/**< \brief (AFEC_MR) ADC_SETTLING_AST9 9 periods of AFEClock*/ +#define AFEC_MR_SETTLING_AST17 (0x3u << 20) +/**< \brief (AFEC_MR) ADC_SETTLING_AST17 17 periods of AFEClock*/ + +/***************************** Single Trigger Mode ****************************/ +#define AFEC_EMR_STM_Pos 25 +#define AFEC_EMR_STM_Msk (0x1u << AFEC_EMR_STM_Pos) +/**< \brief (AFEC_EMR) Single Trigger Mode */ +#define AFEC_EMR_STM_MULTI_TRIG (0x0u << 25) +/**< \brief (AFEC_EMR) Single Trigger Mode: Multiple triggers are required to + get an averaged result. */ +#define AFEC_EMR_STM_SINGLE_TRIG (0x1u << 25) +/**< \brief (AFEC_EMR) Single Trigger Mode: Only a Single Trigger is required + to get an averaged value. */ + +/***************************** TAG of the AFEC_LDCR Register ******************/ +#define AFEC_EMR_TAG_Pos 24 +#define AFEC_EMR_TAG_Msk (0x1u << AFEC_EMR_TAG_Pos) +/**< \brief (AFEC_EMR) TAG of the AFEC_LDCR Register */ +#define AFEC_EMR_TAG_CHNB_ZERO (0x0u << 24) +/**< \brief (AFEC_EMR) TAG of the AFEC_LDCR Register: Sets CHNB to zero +in AFEC_LDCR. */ +#define AFEC_EMR_TAG_APPENDS (0x1u << 24) +/**< \brief (AFEC_EMR) TAG of the AFEC_LDCR Register: Appends the channel +number to the conversion result in AFEC_LDCR register. */ + +/***************************** Compare All Channels ******************/ +#define AFEC_EMR_CMPALL_Pos 9 +#define AFEC_EMR_CMPALL_Msk (0x1u << AFEC_EMR_TAG_Pos) +/**< \brief (AFEC_EMR) Compare All Channels */ +#define AFEC_EMR_CMPALL_ONE_CHANNEL_COMP (0x0u << 9) +/**< \brief (AFEC_EMR) Compare All Channels: Only channel indicated in +CMPSEL field is compared. */ +#define AFEC_EMR_CMPALL_ALL_CHANNELS_COMP (0x1u << 9) +/**< \brief (AFEC_EMR) Compare All Channels: All channels are compared. */ + +#define AFEC_ACR_PGA0_ON (0x1u << 2) +#define AFEC_ACR_PGA1_ON (0x1u << 3) + +#ifdef __cplusplus + extern "C" { +#endif + +/*------------------------------------------------------------------------------ + * Macros function of register access + *------------------------------------------------------------------------------*/ + +#define AFEC_GetModeReg( pAFEC ) ((pAFEC)->AFEC_MR) +#define AFEC_SetModeReg( pAFEC, mode ) ((pAFEC)->AFEC_MR = mode) + +#define AFEC_GetExtModeReg( pAFEC ) ((pAFEC)->AFEC_EMR) +#define AFEC_SetExtModeReg( pAFEC, mode ) ((pAFEC)->AFEC_EMR = mode) + +#define AFEC_StartConversion( pAFEC ) ((pAFEC)->AFEC_CR = AFEC_CR_START) + +#define AFEC_EnableChannel( pAFEC, dwChannel ) {\ + (pAFEC)->AFEC_CHER = (1 << (dwChannel));\ + } + +#define AFEC_DisableChannel(pAFEC, dwChannel) {\ + (pAFEC)->AFEC_CHDR = (1 << (dwChannel));\ + } + +#define AFEC_EnableIt(pAFEC, dwMode) {\ + (pAFEC)->AFEC_IER = (dwMode);\ + } + +#define AFEC_DisableIt(pAFEC, dwMode) {\ + (pAFEC)->AFEC_IDR = (dwMode);\ + } + +#define AFEC_SetChannelGain(pAFEC,dwMode) {\ + (pAFEC)->AFEC_CGR = dwMode;\ + } + +#define AFEC_EnableDataReadyIt(pAFEC) ((pAFEC)->AFEC_IER = AFEC_IER_DRDY) + +#define AFEC_GetStatus(pAFEC) ((pAFEC)->AFEC_ISR) + +#define AFEC_GetCompareMode(pAFEC) (((pAFEC)->AFEC_EMR)& (AFEC_EMR_CMPMODE_Msk)) + +#define AFEC_GetChannelStatus(pAFEC) ((pAFEC)->AFEC_CHSR) + +#define AFEC_GetInterruptMaskStatus(pAFEC) ((pAFEC)->AFEC_IMR) + +#define AFEC_GetLastConvertedData(pAFEC) ((pAFEC)->AFEC_LCDR) + +/*------------------------------------------------------------------------------ + * Exported functions + *------------------------------------------------------------------------------*/ +extern void AFEC_Initialize( Afec* pAFEC, uint32_t dwId ); +extern uint32_t AFEC_SetClock( Afec* pAFEC, uint32_t dwPres, uint32_t dwMck ); +extern void AFEC_SetTiming( Afec* pAFEC, uint32_t dwStartup, uint32_t dwTracking, + uint32_t dwSettling ); +extern void AFEC_SetTrigger( Afec* pAFEC, uint32_t dwTrgSel ); +extern void AFEC_SetAnalogChange( Afec* pAFE, uint8_t bEnDis ); +extern void AFEC_SetSleepMode( Afec* pAFEC, uint8_t bEnDis ); +extern void AFEC_SetFastWakeup( Afec* pAFEC, uint8_t bEnDis ); +extern void AFEC_SetSequenceMode( Afec* pAFEC, uint8_t bEnDis ); +extern void AFEC_SetSequence( Afec* pAFEC, uint32_t dwSEQ1, uint32_t dwSEQ2 ); +extern void AFEC_SetSequenceByList( Afec* pAFEC, uint8_t ucChList[], uint8_t ucNumCh ); +extern void AFEC_SetTagEnable( Afec* pAFEC, uint8_t bEnDis ); +extern void AFEC_SetCompareChannel( Afec* pAFEC, uint32_t dwChannel ) ; +extern void AFEC_SetCompareMode( Afec* pAFEC, uint32_t dwMode ) ; +extern void AFEC_SetComparisonWindow( Afec* pAFEC, uint32_t dwHi_Lo ) ; +extern uint8_t AFEC_CheckConfiguration( Afec* pAFEC, uint32_t dwMcK ) ; +extern uint32_t AFEC_GetConvertedData( Afec* pAFEC, uint32_t dwChannel ) ; +extern void AFEC_SetStartupTime( Afec* pAFEC, uint32_t dwUs ); +extern void AFEC_SetTrackingTime( Afec* pAFEC, uint32_t dwNs ); +extern void AFEC_SetAnalogOffset( Afec *pAFE, uint32_t dwChannel,uint32_t aoffset ); +extern void AFEC_SetAnalogControl( Afec *pAFE, uint32_t control); +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _AFEC_ */ + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/arm_common_tables.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/arm_common_tables.h new file mode 100644 index 00000000..039cc3d6 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/arm_common_tables.h @@ -0,0 +1,136 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 19. March 2015 +* $Revision: V.1.4.5 +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.h +* +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +//extern const q31_t realCoefAQ31[1024]; +//extern const q31_t realCoefBQ31[1024]; +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_4096_q15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + + +/* floating-point bit reversal tables */ +#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) +#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) +#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) +#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; + +/* fixed-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) +#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) +#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) +#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) +#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) +#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/arm_const_structs.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/arm_const_structs.h new file mode 100644 index 00000000..726d06eb --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/arm_const_structs.h @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 19. March 2015 +* $Revision: V.1.4.5 +* +* Project: CMSIS DSP Library +* Title: arm_const_structs.h +* +* Description: This file has constant structs that are initialized for +* user convenience. For example, some can be given as +* arguments to the arm_cfft_f32() function. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/arm_math.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/arm_math.h new file mode 100644 index 00000000..e4b2f62e --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/arm_math.h @@ -0,0 +1,7556 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2015 ARM Limited. All rights reserved. +* +* $Date: 19. March 2015 +* $Revision: V.1.4.5 +* +* Project: CMSIS DSP Library +* Title: arm_math.h +* +* Description: Public header file for CMSIS DSP Library +* +* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7l_math.lib (Little endian on Cortex-M7) + * - arm_cortexM7b_math.lib (Big endian on Cortex-M7) + * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) + * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) + * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) + * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) + * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+) + * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK-ARM version 5.14.0.0 + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. + * + * Pre-processor Macros + * ------------ + * + * Each library project have differant pre-processor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and + * ARM_MATH_CM7 for building the library on cortex-M7. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2015 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" +#define ARM_MATH_CM0_FAMILY + #elif defined (ARM_MATH_CM0PLUS) +#include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI +#define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined __CC_ARM + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED __attribute__((unused)) +#elif defined __ICCARM__ + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED +#elif defined __GNUC__ + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) +#elif defined __CSMC__ /* Cosmic */ + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED +#elif defined __TASKING__ + #define __SIMD32_TYPE __unaligned int32_t + #define CMSIS_UNUSED +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) + +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) + +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif + + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + static __INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + static __INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + static __INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + static __INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + static __INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + +//#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) +//#define __CLZ __clz +//#endif + +//note: function can be removed when all toolchain support __CLZ for Cortex-M0 +#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ) + + static __INLINE uint32_t __CLZ( + q31_t data); + + + static __INLINE uint32_t __CLZ( + q31_t data) + { + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } + + return (count); + + } + +#endif + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + static __INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + + uint32_t out, tempVal; + uint32_t index, i; + uint32_t signBits; + + if(in > 0) + { + signBits = __CLZ(in) - 1; + } + else + { + signBits = __CLZ(-in) - 1; + } + + /* Convert input sample to 1.31 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = (uint32_t) (in >> 24u); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (q31_t) (((q63_t) in * out) >> 31u); + tempVal = 0x7FFFFFFF - tempVal; + /* 1.31 with exp 1 */ + //out = (q31_t) (((q63_t) out * tempVal) >> 30u); + out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); + + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + static __INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + + uint32_t out = 0, tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if(in > 0) + { + signBits = __CLZ(in) - 17; + } + else + { + signBits = __CLZ(-in) - 17; + } + + /* Convert input sample to 1.15 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = in >> 8; + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0; i < 2; i++) + { + tempVal = (q15_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFF - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + + } + + + /* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0_FAMILY) + + static __INLINE q31_t __SSAT( + q31_t x, + uint32_t y) + { + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) + { + posMax = posMax * 2; + } + + if(x > 0) + { + posMax = (posMax - 1); + + if(x > posMax) + { + x = posMax; + } + } + else + { + negMin = -posMax; + + if(x < negMin) + { + x = negMin; + } + } + return (x); + + + } + +#endif /* end of ARM_MATH_CM0_FAMILY */ + + + + /* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + static __INLINE q31_t __QADD8( + q31_t x, + q31_t y) + { + + q31_t sum; + q7_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = __SSAT((q31_t) (r + s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); + t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); + u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); + + sum = + (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | + (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); + + return sum; + + } + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + static __INLINE q31_t __QSUB8( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = __SSAT((r - s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; + t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; + u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; + + sum = + (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & + 0x000000FF); + + return sum; + } + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + static __INLINE q31_t __QADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = __SSAT(r + s, 16); + s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + static __INLINE q31_t __SHADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) + (s >> 1)); + s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + static __INLINE q31_t __QSUB16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = __SSAT(r - s, 16); + s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + static __INLINE q31_t __SHSUB16( + q31_t x, + q31_t y) + { + + q31_t diff; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) - (s >> 1)); + s = (((x >> 17) - (y >> 17)) << 16); + + diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return diff; + } + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + static __INLINE q31_t __QASX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = + ((sum + + clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) + + clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + static __INLINE q31_t __SHASX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) - (y >> 17)); + s = (((x >> 17) + (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + static __INLINE q31_t __QSAX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = + ((sum + + clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) + + clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + static __INLINE q31_t __SHSAX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) + (y >> 17)); + s = (((x >> 17) - (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + static __INLINE q31_t __SMUSDX( + q31_t x, + q31_t y) + { + + return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) - + ((q15_t) (x >> 16) * (q15_t) y))); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + static __INLINE q31_t __SMUADX( + q31_t x, + q31_t y) + { + + return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) + + ((q15_t) (x >> 16) * (q15_t) y))); + } + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + static __INLINE q31_t __QADD( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x + y); + } + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + static __INLINE q31_t __QSUB( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x - y); + } + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + static __INLINE q31_t __SMLAD( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + + ((q15_t) x * (q15_t) y)); + } + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + static __INLINE q31_t __SMLADX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) + + ((q15_t) x * (q15_t) (y >> 16))); + } + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + static __INLINE q31_t __SMLSDX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) + + ((q15_t) x * (q15_t) (y >> 16))); + } + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + static __INLINE q63_t __SMLALD( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + + ((q15_t) x * (q15_t) y)); + } + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + static __INLINE q63_t __SMLALDX( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + + ((q15_t) x * (q15_t) (y >> 16)); + } + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + static __INLINE q31_t __SMUAD( + q31_t x, + q31_t y) + { + + return (((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + static __INLINE q31_t __SMUSD( + q31_t x, + q31_t y) + { + + return (-((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + static __INLINE q31_t __SXTB16( + q31_t x) + { + + return ((((x << 24) >> 24) & 0x0000FFFF) | + (((x << 8) >> 8) & 0xFFFF0000)); + } + + +#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] *S points to an instance of the Q7 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] *S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + * @return none + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] *S points to an instance of the Q15 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] *S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] *S points to an instance of the Q31 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] *S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] *S points to an instance of the floating-point FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] *S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q15; + + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + + + } arm_biquad_casd_df1_inst_f32; + + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q31; + + + + /** + * @brief Floating-point matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q31 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix scaling. + * @param[in] *pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] *pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + /** + * @brief Q15 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#ifdef ARM_MATH_CM0_FAMILY + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] *S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @return none + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @return none + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the q15 PID Control structure + * @return none + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + + + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q31 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q15 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + /** + * @brief Floating-point vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Dot product of floating-point vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + /** + * @brief Dot product of Q7 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + /** + * @brief Dot product of Q15 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Dot product of Q31 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + + + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_f32; + + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the Q15 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + * @return none. + */ + + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + + } arm_lms_instance_q31; + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Correlation of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. + */ + + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + /** + * @brief Correlation of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /* + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cos output. + * @return none. + */ + + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCcosVal); + + /* + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cosine output. + * @return none. + */ + + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + + + static __INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + + static __INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + + static __INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#ifndef ARM_MATH_CM0_FAMILY + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD(S->A0, in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = __SMLALD(S->A1, (q31_t) *vstate, acc); + +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; + +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] *src points to the instance of the input floating-point matrix structure. + * @param[out] *dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] *src points to the instance of the input floating-point matrix structure. + * @param[out] *dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + */ + + static __INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = + ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + + } + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + static __INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + */ + + + static __INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; + + } + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + + static __INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * The function implements the forward Park transform. + * + */ + + static __INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + + } + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + + + static __INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + */ + + static __INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + + static __INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + + static __INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if(i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] *pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + static __INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + + } + + } + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] *pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + static __INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20u); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (y >> 20); + } + + + } + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] *pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + + + static __INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + + if(index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (y >> 20u); + + } + + } + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + + float32_t arm_sin_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q31_t arm_sin_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q15_t arm_sin_q15( + q15_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + + float32_t arm_cos_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q31_t arm_cos_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + + static __INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if(in >= 0.0f) + { + +// #if __FPU_USED +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + + + + + /** + * @brief floating-point Circular write function. + */ + + static __INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + static __INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + /** + * @brief Q15 Circular write function. + */ + + static __INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q15 Circular Read function. + */ + static __INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + + static __INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q7 Circular Read function. + */ + static __INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + /** + * @brief Mean value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Mean value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Floating-point complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + /** + * @brief Q31 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + /** + * @brief Floating-point complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[in] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + * @return none. + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + + + static __INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 + || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + + } + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20u); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20u); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return (acc << 2u); + + } + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return (acc >> 36); + + } + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return (acc >> 40); + + } + + /** + * @} end of BilinearInterpolate group + */ + + +//SMMLAR +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +//SMMLSR +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +//SMMULR +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +//SMMLA +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +//SMMLS +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +//SMMUL +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) //Keil + +//Enter low optimization region - place directly above function definition + #ifdef ARM_MATH_CM4 + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + +//Exit low optimization region - place directly after end of function definition + #ifdef ARM_MATH_CM4 + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + +//Enter low optimization region - place directly above function definition + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + +//Exit low optimization region - place directly after end of function definition + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ICCARM__) //IAR + +//Enter low optimization region - place directly above function definition + #ifdef ARM_MATH_CM4 + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + +//Exit low optimization region - place directly after end of function definition + #define LOW_OPTIMIZATION_EXIT + +//Enter low optimization region - place directly above function definition + #ifdef ARM_MATH_CM4 + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + +//Exit low optimization region - place directly after end of function definition + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__GNUC__) + + #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) + + #define LOW_OPTIMIZATION_EXIT + + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__CSMC__) // Cosmic + +#define LOW_OPTIMIZATION_ENTER +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__TASKING__) // TASKING + +#define LOW_OPTIMIZATION_ENTER +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/core_cm0.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/core_cm0.h new file mode 100644 index 00000000..cf2b5d66 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/core_cm0.h @@ -0,0 +1,740 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V4.10 + * @date 18. March 2015 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M0 + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000 + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31 /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30 /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29 /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28 /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31 /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29 /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28 /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24 /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if((int32_t)(IRQn) < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if((int32_t)(IRQn) < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); + } + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); + } +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1) { __NOP(); } /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */ + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/core_cm0plus.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/core_cm0plus.h new file mode 100644 index 00000000..123cb400 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,854 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V4.10 + * @date 18. March 2015 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0P definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ + __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000 + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0 + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31 /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30 /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29 /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28 /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31 /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29 /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28 /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24 /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if (__VTOR_PRESENT == 1) + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if (__VTOR_PRESENT == 1) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if((int32_t)(IRQn) < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if((int32_t)(IRQn) < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); + } + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); + } +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1) { __NOP(); } /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */ + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/core_cm3.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/core_cm3.h new file mode 100644 index 00000000..092ee23d --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/core_cm3.h @@ -0,0 +1,1693 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V4.10 + * @date 18. March 2015 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200 + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31 /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30 /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29 /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28 /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27 /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31 /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29 /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28 /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27 /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25 /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24 /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if((int32_t)IRQn < 0) { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if((int32_t)IRQn < 0) { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS))); + } + else { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS))); + } +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1) { __NOP(); } /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */ + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0UL) { __NOP(); } + ITM->PORT[0].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/core_cm4.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/core_cm4.h new file mode 100644 index 00000000..9749c27d --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/core_cm4.h @@ -0,0 +1,1858 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V4.10 + * @date 18. March 2015 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ +#include /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000 + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0 + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31 /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30 /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29 /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28 /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27 /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16 /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31 /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29 /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28 /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27 /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25 /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24 /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16 /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if((int32_t)IRQn < 0) { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if((int32_t)IRQn < 0) { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS))); + } + else { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS))); + } +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1) { __NOP(); } /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */ + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0UL) { __NOP(); } + ITM->PORT[0].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/core_cm7.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/core_cm7.h new file mode 100644 index 00000000..842e323f --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/core_cm7.h @@ -0,0 +1,2397 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V4.10 + * @date 18. March 2015 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M7 + @{ + */ + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x07) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ +#include /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000 + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0 + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0 + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0 + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0 + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31 /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30 /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29 /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28 /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27 /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16 /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31 /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29 /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28 /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27 /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25 /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24 /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16 /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1]; + __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93]; + __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15]; + __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ + uint32_t RESERVED5[1]; + __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1]; + __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __O uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6]; + __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1]; + __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* Cache Level ID register */ +#define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* Cache Type register */ +#define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* Cache Size ID Register */ +#define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* Cache Size Selection Register */ +#define SCB_CSSELR_LEVEL_Pos 1 /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register */ +#define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* Instruction Tightly-Coupled Memory Control Register*/ +#define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Registers */ +#define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register */ +#define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register */ +#define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS control register */ +#define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register */ +#define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if((int32_t)IRQn < 0) { + SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if((int32_t)IRQn < 0) { + return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS))); + } + else { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS))); + } +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1) { __NOP(); } /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \fn uint32_t SCB_GetFPUType(void) + \brief get FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & 0x00000FF0UL) == 0x220UL) { + return 2UL; // Double + Single precision FPU + } else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) { + return 1UL; // Single precision FPU + } else { + return 0UL; // No FPU + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) +#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) /*>> SCB_CCSIDR_LINESIZE_Pos*/ ) + + +/** \brief Enable I-Cache + + The function turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache (void) +{ + #if (__ICACHE_PRESENT == 1) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; // invalidate I-Cache + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; // enable I-Cache + __DSB(); + __ISB(); + #endif +} + + +/** \brief Disable I-Cache + + The function turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache (void) +{ + #if (__ICACHE_PRESENT == 1) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; // disable I-Cache + SCB->ICIALLU = 0UL; // invalidate I-Cache + __DSB(); + __ISB(); + #endif +} + + +/** \brief Invalidate I-Cache + + The function invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache (void) +{ + #if (__ICACHE_PRESENT == 1) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** \brief Enable D-Cache + + The function turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache (void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache + ccsidr = SCB->CCSIDR; + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL); + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL); + + __DSB(); + + do { // invalidate D-Cache + uint32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCISW = sw; + } while(tmpways--); + } while(sets--); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; // enable D-Cache + + __DSB(); + __ISB(); + #endif +} + + +/** \brief Disable D-Cache + + The function turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache (void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache + ccsidr = SCB->CCSIDR; + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL); + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL); + + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; // disable D-Cache + + do { // clean & invalidate D-Cache + uint32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCCISW = sw; + } while(tmpways--); + } while(sets--); + + + __DSB(); + __ISB(); + #endif +} + + +/** \brief Invalidate D-Cache + + The function invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache (void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache + ccsidr = SCB->CCSIDR; + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL); + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL); + + __DSB(); + + do { // invalidate D-Cache + uint32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCISW = sw; + } while(tmpways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** \brief Clean D-Cache + + The function cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache (void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache + ccsidr = SCB->CCSIDR; + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL); + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL); + + __DSB(); + + do { // clean D-Cache + uint32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCCSW = sw; + } while(tmpways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** \brief Clean & Invalidate D-Cache + + The function cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache (void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache + ccsidr = SCB->CCSIDR; + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL); + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL); + + __DSB(); + + do { // clean & invalidate D-Cache + uint32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCCISW = sw; + } while(tmpways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** + \fn void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize) + \brief D-Cache Invalidate by address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) + + __DSB(); + + while (op_size > 0) { + SCB->DCIMVAC = op_addr; + op_addr += linesize; + op_size -= (int32_t)linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \fn void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize) + \brief D-Cache Clean by address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += linesize; + op_size -= (int32_t)linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \fn void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize) + \brief D-Cache Clean and Invalidate by address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += linesize; + op_size -= (int32_t)linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */ + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0UL) { __NOP(); } + ITM->PORT[0].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/core_cmFunc.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/core_cmFunc.h new file mode 100644 index 00000000..b6ad0a4c --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/core_cmFunc.h @@ -0,0 +1,664 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.10 + * @date 18. March 2015 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Set Base Priority with condition + + This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** \brief Set Base Priority with condition + + This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/core_cmInstr.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/core_cmInstr.h new file mode 100644 index 00000000..fca425c5 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/core_cmInstr.h @@ -0,0 +1,916 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.10 + * @date 18. March 2015 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0) + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0) + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0) + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end + + result = value; // r will be reversed bits of v; first get LSB of v + for (value >>= 1; value; value >>= 1) + { + result <<= 1; + result |= value & 1; + s--; + } + result <<= s; // shift when v's highest bits are zero + return(result); +} +#endif + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief LDR Exclusive (8 bit) + + This function executes a exclusive LDR instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function executes a exclusive LDR instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function executes a exclusive LDR instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function executes a exclusive STR instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function executes a exclusive STR instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function executes a exclusive STR instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Rotate Right with Extend (32 bit) + + This function moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constrant "l" + * Otherwise, use general registers, specified by constrant "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + uint32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32 - op2)); +} + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end + + result = value; // r will be reversed bits of v; first get LSB of v + for (value >>= 1; value; value >>= 1) + { + result <<= 1; + result |= value & 1; + s--; + } + result <<= s; // shift when v's highest bits are zero +#endif + return(result); +} + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief LDR Exclusive (8 bit) + + This function executes a exclusive LDR instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (16 bit) + + This function executes a exclusive LDR instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (32 bit) + + This function executes a exclusive LDR instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function executes a exclusive STR instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function executes a exclusive STR instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function executes a exclusive STR instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Rotate Right with Extend (32 bit) + + This function moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/core_cmSimd.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/core_cmSimd.h new file mode 100644 index 00000000..7b8e37ff --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/core_cmSimd.h @@ -0,0 +1,697 @@ +/**************************************************************************//** + * @file core_cmSimd.h + * @brief CMSIS Cortex-M SIMD Header File + * @version V4.10 + * @date 18. March 2015 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CMSIMD_H +#define __CORE_CMSIMD_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32) ) >> 32)) + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* not yet supported */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CMSIMD_H */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/core_sc000.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/core_sc000.h new file mode 100644 index 00000000..44cb0274 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/core_sc000.h @@ -0,0 +1,864 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V4.10 + * @date 18. March 2015 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup SC000 + @{ + */ + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (000) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000 + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31 /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30 /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29 /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28 /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31 /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29 /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28 /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24 /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1]; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154]; + __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2]; + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of SC000 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if((int32_t)(IRQn) < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if((int32_t)(IRQn) < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); + } + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); + } +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1) { __NOP(); } /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */ + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/core_sc300.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/core_sc300.h new file mode 100644 index 00000000..7e40672a --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/cmsis/CMSIS/Include/core_sc300.h @@ -0,0 +1,1675 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V4.10 + * @date 18. March 2015 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup SC3000 + @{ + */ + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (300) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000 + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31 /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30 /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29 /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28 /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27 /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31 /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29 /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28 /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27 /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25 /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24 /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129]; + __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if((int32_t)IRQn < 0) { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if((int32_t)IRQn < 0) { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS))); + } + else { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS))); + } +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1) { __NOP(); } /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */ + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0UL) { __NOP(); } + ITM->PORT[0].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/dac_dma.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/dac_dma.h new file mode 100644 index 00000000..71b7da95 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/dac_dma.h @@ -0,0 +1,151 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ +/** + * \file + * + * \section Purpose + * + * Interface for configuration the Analog-to-Digital Converter (DACC) peripheral. + * + * \section Usage + * + * -# Configurate the pins for DACC + * -# Initialize the DACC with DACC_Initialize(). + * -# Select the active channel using DACC_EnableChannel() + * -# Start the conversion with DACC_StartConversion() + * -# Wait the end of the conversion by polling status with DACC_GetStatus() + * -# Finally, get the converted data using DACC_GetConvertedData() + * +*/ +#ifndef _DAC_DMA_ +#define _DAC_DMA_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +#include +#include + + +#ifdef __cplusplus + extern "C" { +#endif + + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** DAC transfer complete callback. */ +typedef void (*DacCallback)( uint8_t, void* ) ; + +/** \brief Dac Transfer Request prepared by the application upper layer. + * + * This structure is sent to the DAC_SendCommand function to start the transfer. + * At the end of the transfer, the callback is invoked by the interrupt handler. + */ +typedef struct +{ + /** Pointer to the Tx data. */ + uint8_t *pTxBuff; + /** Tx size in bytes. */ + uint16_t TxSize; + /** Tx loop back. */ + uint16_t loopback; + /** DACC channel*/ + uint8_t dacChannel; + /** Callback function invoked at the end of transfer. */ + DacCallback callback; + /** Callback arguments. */ + void *pArgument; +} DacCmd ; + + +/** Constant structure associated with DAC port. This structure prevents + client applications to have access in the same time. */ +typedef struct +{ + /** Pointer to DAC Hardware registers */ + Dacc* pDacHw ; + /** Current SpiCommand being processed */ + DacCmd *pCurrentCommand ; + /** Pointer to DMA driver */ + sXdmad* pXdmad ; + /** DACC Id as defined in the product datasheet */ + uint8_t dacId ; + /** Mutual exclusion semaphore. */ + volatile int8_t semaphore ; +} DacDma; + + +/*------------------------------------------------------------------------------ + * Definitions + *------------------------------------------------------------------------------*/ +#define DAC_OK 0 +#define DAC_ERROR 1 +#define DAC_ERROR_LOCK 2 + +#define DACC_CHANNEL_0 0 +#define DACC_CHANNEL_1 1 + +/*------------------------------------------------------------------------------ + * Exported functions + *------------------------------------------------------------------------------*/ +extern uint32_t Dac_ConfigureDma( DacDma *pDacd , + Dacc *pDacHw , + uint8_t DacId, + sXdmad *pXdmad ); +extern uint32_t Dac_SendData( DacDma *pDacd, DacCmd *pCommand); + + +/*------------------------------------------------------------------------------ + * Macros function of register access + *------------------------------------------------------------------------------*/ +#define DACC_SoftReset(pDACC) ((pDACC)->DACC_CR = DACC_CR_SWRST) +#define DACC_CfgModeReg(pDACC, mode) { (pDACC)->DACC_MR = (mode); } +#define DACC_GetModeReg(pDACC) ((pDACC)->DACC_MR) +#define DACC_CfgTrigger(pDACC, mode) { (pDACC)->DACC_TRIGR = (mode); } + +#define DACC_EnableChannel(pDACC, channel) {(pDACC)->DACC_CHER = (1 << (channel));} +#define DACC_DisableChannel(pDACC, channel) {(pDACC)->DACC_CHDR = (1 << (channel));} + +#define DACC_EnableIt(pDACC, mode) {(pDACC)->DACC_IER = (mode);} +#define DACC_DisableIt(pDACC, mode) {(pDACC)->DACC_IDR = (mode);} +#define DACC_GetStatus(pDACC) ((pDACC)->DACC_ISR) +#define DACC_GetChannelStatus(pDACC) ((pDACC)->DACC_CHSR) +#define DACC_GetInterruptMaskStatus(pDACC) ((pDACC)->DACC_IMR) + + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _DAC_DMA_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/efc.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/efc.h new file mode 100644 index 00000000..254333b3 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/efc.h @@ -0,0 +1,128 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \section Purpose + * + * Interface for configuration the Enhanced Embedded Flash Controller (EEFC) + * peripheral. + * + * \section Usage + * + * -# Enable/disable %flash ready interrupt sources using EFC_EnableFrdyIt() + * and EFC_DisableFrdyIt(). + * -# Translates the given address into which EEFC, page and offset values + * for difference density %flash memory using EFC_TranslateAddress(). + * -# Computes the address of a %flash access given the EFC, page and offset + * for difference density %flash memory using EFC_ComputeAddress(). + * -# Start the executing command with EFC_PerformCommand() + * -# Retrieve the current status of the EFC using EFC_GetStatus(). + * -# Retrieve the result of the last executed command with EFC_GetResult(). + */ + +#ifndef _EEFC_ +#define _EEFC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +#include + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ +/* TODO: Temporary definition for missing symbol in header file */ +#define IFLASH_SECTOR_SIZE 65536u + + +/* EFC command */ +#define EFC_FCMD_GETD 0x00 /* Get Flash Descriptor */ +#define EFC_FCMD_WP 0x01 /* Write page */ +#define EFC_FCMD_WPL 0x02 /* Write page and lock */ +#define EFC_FCMD_EWP 0x03 /* Erase page and write page */ +#define EFC_FCMD_EWPL 0x04 /* Erase page and write page then lock */ +#define EFC_FCMD_EA 0x05 /* Erase all */ +#define EFC_FCMD_EPA 0x07 /* Erase pages */ +#define EFC_FCMD_SLB 0x08 /* Set Lock Bit */ +#define EFC_FCMD_CLB 0x09 /* Clear Lock Bit */ +#define EFC_FCMD_GLB 0x0A /* Get Lock Bit */ +#define EFC_FCMD_SFB 0x0B /* Set GPNVM Bit */ +#define EFC_FCMD_CFB 0x0C /* Clear GPNVM Bit */ +#define EFC_FCMD_GFB 0x0D /* Get GPNVM Bit */ +#define EFC_FCMD_STUI 0x0E /* Start unique ID */ +#define EFC_FCMD_SPUI 0x0F /* Stop unique ID */ +#define EFC_FCMD_GCALB 0x10 /* Get CALIB Bit */ +#define EFC_FCMD_ES 0x11 /* Erase Sector */ +#define EFC_FCMD_WUS 0x12 /* Write User Signature */ +#define EFC_FCMD_EUS 0x13 /* Erase User Signature */ +#define EFC_FCMD_STUS 0x14 /* Start Read User Signature */ +#define EFC_FCMD_SPUS 0x15 /* Stop Read User Signature */ + +/* The IAP function entry address */ +#define CHIP_FLASH_IAP_ADDRESS (0x00800008) + +#ifdef __cplusplus + extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void EFC_EnableFrdyIt( Efc* efc ) ; + +extern void EFC_DisableFrdyIt( Efc* efc ) ; + +extern void EFC_SetWaitState( Efc* efc, uint8_t cycles ) ; + +extern void EFC_TranslateAddress( Efc** pEfc, uint32_t dwAddress, + uint16_t *pwPage, uint16_t *pwOffset ) ; + +extern void EFC_ComputeAddress( Efc* efc, uint16_t wPage, uint16_t wOffset, + uint32_t *pdwAddress ) ; + +extern uint32_t EFC_PerformCommand( Efc* efc, uint32_t dwCommand, + uint32_t dwArgument, uint32_t dwUseIAP ) ; + +extern uint32_t EFC_GetStatus( Efc* efc ) ; + +extern uint32_t EFC_GetResult( Efc* efc ) ; + +extern void EFC_SetFlashAccessMode(Efc* efc, uint32_t dwMode) ; + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _EEFC_ */ + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/exceptions.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/exceptions.h new file mode 100644 index 00000000..8683678f --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/exceptions.h @@ -0,0 +1,52 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * Interface for default exception handlers. + */ + +#ifndef _EXCEPTIONS_ +#define _EXCEPTIONS_ + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/* Function prototype for exception table items (interrupt handler). */ +typedef void( *IntFunc )( void ) ; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/* Default empty handler */ +extern void IrqHandlerNotUsed( void ) ; + +#endif /* _EXCEPTIONS_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/flashd.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/flashd.h new file mode 100644 index 00000000..800d0660 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/flashd.h @@ -0,0 +1,91 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- +*/ + +/** + * \file + * + * The flash driver provides the unified interface for flash program operations. + * + */ + +#ifndef _FLASHD_ +#define _FLASHD_ + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +#define GPNVBit_SecurityBit 0 +#define GPNVBit_BootMode 1 +#define GPNVBit_TCMBit1 6 +#define GPNVBit_TCMBit2 7 + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void FLASHD_Initialize( uint32_t dwMCk, uint32_t dwUseIAP ) ; + +extern uint32_t FLASHD_Erase( uint32_t dwAddress ) ; + +extern uint32_t FLASHD_EraseSector( uint32_t dwAddress ) ; + +extern uint32_t FLASHD_ErasePages( uint32_t dwAddress, uint32_t dwPageNum ) ; + +extern uint32_t FLASHD_Write( uint32_t dwAddress, const void *pvBuffer, + uint32_t dwSize ) ; + +extern uint32_t FLASHD_Lock( uint32_t dwStart, uint32_t dwEnd, + uint32_t *pdwActualStart, uint32_t *pdwActualEnd ) ; + +extern uint32_t FLASHD_Unlock( uint32_t dwStart, uint32_t dwEnd, + uint32_t *pdwActualStart, uint32_t *pdwActualEnd ) ; + +extern uint32_t FLASHD_IsLocked( uint32_t dwStart, uint32_t dwEnd ) ; + +extern uint32_t FLASHD_SetGPNVM( uint8_t gpnvm ) ; + +extern uint32_t FLASHD_ClearGPNVM( uint8_t gpnvm ) ; + +extern uint32_t FLASHD_IsGPNVMSet( uint8_t gpnvm ) ; + +#define FLASHD_IsSecurityBitSet() FLASHD_IsGPNVMSet( 0 ) + +#define FLASHD_SetSecurityBit() FLASHD_SetGPNVM( 0 ) + +extern uint32_t FLASHD_ReadUniqueID( uint32_t* pdwUniqueID ) ; + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _FLASHD_ */ + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/gmac.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/gmac.h new file mode 100644 index 00000000..c2f79620 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/gmac.h @@ -0,0 +1,338 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/** \addtogroup gmac_module + * @{ + * Provides the interface to configure and use the GMAC peripheral. + * + * \section gmac_usage Usage + * - Configure Gmac::GMAC_NCFG with GMAC_Configure(), some of related controls + * are also available, such as: + * - GMAC_SetSpeed(): Setup GMAC working clock. + * - GMAC_FullDuplexEnable(): Working in full duplex or not. + * - GMAC_CpyAllEnable(): Copying all valid frames (\ref GMAC_NCFG_CAF). + * - ... + * - Setup Gmac::GMAC_NCR with GMAC_NetworkControl(), more related controls + * can modify with: + * - GMAC_ReceiveEnable(): Enable/Disable Rx. + * - GMAC_TransmitEnable(): Enable/Disable Tx. + * - GMAC_BroadcastDisable(): Enable/Disable broadcast receiving. + * - ... + * - Manage GMAC interrupts with GMAC_EnableIt(), GMAC_DisableIt(), + * GMAC_GetItMask() and GMAC_GetItStatus(). + * - Manage GMAC Tx/Rx status with GMAC_GetTxStatus(), GMAC_GetRxStatus() + * GMAC_ClearTxStatus() and GMAC_ClearRxStatus(). + * - Manage GMAC Queue with GMAC_SetTxQueue(), GMAC_GetTxQueue(), + * GMAC_SetRxQueue() and GMAC_GetRxQueue(), the queue descriptor can define + * by \ref sGmacRxDescriptor and \ref sGmacTxDescriptor. + * - Manage PHY through GMAC is performed by + * - GMAC_ManagementEnable(): Enable/Disable PHY management. + * - GMAC_PHYMaintain(): Execute PHY management commands. + * - GMAC_PHYData(): Return PHY management data. + * - GMAC_IsIdle(): Check if PHY is idle. + * - Setup GMAC parameters with following functions: + * - GMAC_SetHash(): Set Hash value. + * - GMAC_SetAddress(): Set MAC address. + * - Enable/Disable GMAC transceiver clock via GMAC_TransceiverClockEnable() + * - Switch GMAC MII/RMII mode through GMAC_RMIIEnable() + * + * For more accurate information, please look at the GMAC section of the + * Datasheet. + * + * \sa \ref gmacd_module + * + * Related files:\n + * gmac.c\n + * gmac.h.\n + * + * \defgroup gmac_defines GMAC Defines + * \defgroup gmac_structs GMAC Data Structs + * \defgroup gmac_functions GMAC Functions + */ +/**@}*/ + +#ifndef _GMAC_H +#define _GMAC_H + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Defines + *----------------------------------------------------------------------------*/ +/** \addtogroup gmac_defines + @{*/ + +#define NUM_GMAC_QUEUES 3 +/// Board GMAC base address + +#define GMAC_DUPLEX_HALF 0 +#define GMAC_DUPLEX_FULL 1 + +// +#define GMAC_SPEED_10M 0 +#define GMAC_SPEED_100M 1 +#define GMAC_SPEED_1000M 2 + +/*------------------------------------------------------------------------------ + Definitions +------------------------------------------------------------------------------ +*/ +/// The buffer addresses written into the descriptors must be aligned so the +/// last few bits are zero. These bits have special meaning for the GMAC +/// peripheral and cannot be used as part of the address. +#define GMAC_ADDRESS_MASK ((unsigned int)0xFFFFFFFC) +#define GMAC_LENGTH_FRAME ((unsigned int)0x3FFF) /// Length of frame mask + +// receive buffer descriptor bits +#define GMAC_RX_OWNERSHIP_BIT (1u << 0) +#define GMAC_RX_WRAP_BIT (1u << 1) +#define GMAC_RX_SOF_BIT (1u << 14) +#define GMAC_RX_EOF_BIT (1u << 15) + +// Transmit buffer descriptor bits +#define GMAC_TX_LAST_BUFFER_BIT (1u << 15) +#define GMAC_TX_WRAP_BIT (1u << 30) +#define GMAC_TX_USED_BIT (1u << 31) +#define GMAC_TX_RLE_BIT (1u << 29) /// Retry Limit Exceeded +#define GMAC_TX_UND_BIT (1u << 28) /// Tx Buffer Under-run +#define GMAC_TX_ERR_BIT (1u << 27) /// Exhausted in mid-frame +#define GMAC_TX_ERR_BITS \ + (GMAC_TX_RLE_BIT | GMAC_TX_UND_BIT | GMAC_TX_ERR_BIT) + +// Interrupt bits +#define GMAC_INT_RX_BITS \ + (GMAC_IER_RCOMP | GMAC_IER_RXUBR | GMAC_IER_ROVR) +#define GMAC_INT_TX_ERR_BITS \ + (GMAC_IER_TUR | GMAC_IER_RLEX | GMAC_IER_TFC | GMAC_IER_HRESP) +#define GMAC_INT_TX_BITS \ + (GMAC_INT_TX_ERR_BITS | GMAC_IER_TCOMP) +// Interrupt Status bits +#define GMAC_INT_RX_STATUS_BITS \ + (GMAC_ISR_RCOMP | GMAC_ISR_RXUBR | GMAC_ISR_ROVR) +#define GMAC_INT_TX_STATUS_ERR_BITS \ + (GMAC_ISR_TUR | GMAC_ISR_RLEX | GMAC_ISR_TFC | GMAC_ISR_HRESP) +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ +/** \addtogroup gmac_structs + @{*/ + +/* This is the list of GMAC queue */ +typedef enum { + GMAC_QUE_0 = 0, + GMAC_QUE_1 = 1, + GMAC_QUE_2 = 2 +}gmacQueList_t; + +/** Receive buffer descriptor struct */ +typedef struct _GmacRxDescriptor { + union _GmacRxAddr { + uint32_t val; + struct _GmacRxAddrBM { + uint32_t bOwnership:1, /**< User clear, GMAC set this to one once + it has successfully written a frame to + memory */ + bWrap:1, /**< Marks last descriptor in receive buffer */ + addrDW:30; /**< Address in number of DW */ + } bm; + } addr; /**< Address, Wrap & Ownership */ + union _GmacRxStatus { + uint32_t val; + struct _GmacRxStatusBM { + uint32_t len:12, /** Length of frame including FCS */ + offset:2, /** Receive buffer offset, + bits 13:12 of frame length for jumbo + frame */ + bSof:1, /** Start of frame */ + bEof:1, /** End of frame */ + bCFI:1, /** Concatenation Format Indicator */ + vlanPriority:3, /** VLAN priority (if VLAN detected) */ + bPriorityDetected:1, /** Priority tag detected */ + bVlanDetected:1, /**< VLAN tag detected */ + bTypeIDMatch:1, /**< Type ID match */ + bAddr4Match:1, /**< Address register 4 match */ + bAddr3Match:1, /**< Address register 3 match */ + bAddr2Match:1, /**< Address register 2 match */ + bAddr1Match:1, /**< Address register 1 match */ + reserved:1, + bExtAddrMatch:1, /**< External address match */ + bUniHashMatch:1, /**< Unicast hash match */ + bMultiHashMatch:1, /**< Multicast hash match */ + bBroadcastDetected:1; /**< Global all ones broadcast + address detected */ + } bm; + } status; +} sGmacRxDescriptor ; /* GCC */ + +/** Transmit buffer descriptor struct */ +typedef struct _GmacTxDescriptor { + uint32_t addr; + union _GmacTxStatus { + uint32_t val; + struct _GmacTxStatusBM { + uint32_t len:11, /**< Length of buffer */ + reserved:4, + bLastBuffer:1, /**< Last buffer (in the current frame) */ + bNoCRC:1, /**< No CRC */ + reserved1:10, + bExhausted:1, /**< Buffer exhausted in mid frame */ + bUnderrun:1, /**< Transmit under run */ + bError:1, /**< Retry limit exceeded, error detected */ + bWrap:1, /**< Marks last descriptor in TD list */ + bUsed:1; /**< User clear, GMAC sets this once a frame + has been successfully transmitted */ + } bm; + } status; +} sGmacTxDescriptor; /* GCC */ + +/** @}*/ + +//----------------------------------------------------------------------------- +// PHY Exported functions +//----------------------------------------------------------------------------- +extern uint8_t GMAC_IsIdle(Gmac *pGmac); +extern void GMAC_PHYMaintain(Gmac *pGmac, + uint8_t bPhyAddr, + uint8_t bRegAddr, + uint8_t bRW, + uint16_t wData); +extern uint16_t GMAC_PHYData(Gmac *pGmac); +extern void GMAC_ClearStatistics(Gmac *pGmac); +extern void GMAC_IncreaseStatistics(Gmac *pGmac); +extern void GMAC_StatisticsWriteEnable(Gmac *pGmac, uint8_t bEnaDis); +extern uint8_t GMAC_SetMdcClock(Gmac *pGmac, uint32_t mck ); +extern void GMAC_EnableMdio(Gmac *pGmac ); +extern void GMAC_DisableMdio(Gmac *pGmac ); +extern void GMAC_EnableMII(Gmac *pGmac ); +extern void GMAC_EnableRMII(Gmac *pGmac ); +extern void GMAC_EnableGMII( Gmac *pGmac ); +extern void GMAC_SetLinkSpeed(Gmac *pGmac, uint8_t speed, uint8_t fullduplex); +extern void GMAC_EnableIt(Gmac *pGmac, uint32_t dwSources, gmacQueList_t queueIdx); +extern void GMAC_EnableAllQueueIt(Gmac *pGmac, uint32_t dwSources); +extern void GMAC_DisableIt(Gmac *pGmac, uint32_t dwSources, gmacQueList_t queueIdx); +extern void GMAC_DisableAllQueueIt(Gmac *pGmac, uint32_t dwSources); +extern uint32_t GMAC_GetItStatus(Gmac *pGmac, gmacQueList_t queueIdx); +extern uint32_t GMAC_GetItMask(Gmac *pGmac, gmacQueList_t queueIdx); +extern uint32_t GMAC_GetTxStatus(Gmac *pGmac); +extern void GMAC_ClearTxStatus(Gmac *pGmac, uint32_t dwStatus); +extern uint32_t GMAC_GetRxStatus(Gmac *pGmac); +extern void GMAC_ClearRxStatus(Gmac *pGmac, uint32_t dwStatus); +extern void GMAC_ReceiveEnable(Gmac* pGmac, uint8_t bEnaDis); +extern void GMAC_TransmitEnable(Gmac *pGmac, uint8_t bEnaDis); +extern uint32_t GMAC_SetLocalLoopBack(Gmac *pGmac); +extern void GMAC_SetRxQueue(Gmac *pGmac, uint32_t dwAddr, gmacQueList_t queueIdx); +extern uint32_t GMAC_GetRxQueue(Gmac *pGmac, gmacQueList_t queueIdx); +extern void GMAC_SetTxQueue(Gmac *pGmac, uint32_t dwAddr, gmacQueList_t queueIdx); +extern uint32_t GMAC_GetTxQueue(Gmac *pGmac, gmacQueList_t queueIdx); +extern void GMAC_NetworkControl(Gmac *pGmac, uint32_t bmNCR); +extern uint32_t GMAC_GetNetworkControl(Gmac *pGmac); +extern void GMAC_SetAddress(Gmac *pGmac, uint8_t bIndex, uint8_t *pMacAddr); +extern void GMAC_SetAddress32(Gmac *pGmac, uint8_t bIndex, uint32_t dwMacT, uint32_t dwMacB); +extern void GMAC_SetAddress64(Gmac *pGmac, uint8_t bIndex, uint64_t ddwMac); +extern void GMAC_Configure(Gmac *pGmac, uint32_t dwCfg); +extern void GMAC_SetDMAConfig(Gmac *pGmac, uint32_t dwDmaCfg, gmacQueList_t queueIdx); +extern uint32_t GMAC_GetDMAConfig(Gmac *pGmac, gmacQueList_t queueIdx); +extern uint32_t GMAC_GetConfigure(Gmac *pGmac); +extern void GMAC_TransmissionStart(Gmac *pGmac); +extern void GMAC_TransmissionHalt(Gmac *pGmac); +extern void GMAC_EnableRGMII(Gmac *pGmac, uint32_t duplex, uint32_t speed); + +void GMAC_ClearScreener1Reg (Gmac* pGmac, gmacQueList_t queueIdx); + +void GMAC_WriteScreener1Reg(Gmac* pGmac, gmacQueList_t queueIdx, uint32_t regVal); + +void GMAC_ClearScreener2Reg (Gmac* pGmac, gmacQueList_t queueIdx); + +void GMAC_WriteScreener2Reg (Gmac* pGmac, gmacQueList_t queueIdx, uint32_t regVal); + +void GMAC_WriteEthTypeReg (Gmac* pGmac, gmacQueList_t queueIdx, uint16_t etherType); + +void GMAC_WriteCompareReg(Gmac* pGmac, gmacQueList_t queueIdx, uint32_t c0Reg, uint16_t c1Reg); + +void GMAC_EnableCbsQueA(Gmac *pGmac); + +void GMAC_DisableCbsQueA(Gmac *pGmac); + +void GMAC_EnableCbsQueB(Gmac *pGmac); + +void GMAC_DisableCbsQueB(Gmac *pGmac); + +void GMAC_ConfigIdleSlopeA(Gmac *pGmac, uint32_t idleSlopeA); + +void GMAC_ConfigIdleSlopeB(Gmac *pGmac, uint32_t idleSlopeB); + +void GMAC_SetTsuTmrIncReg( Gmac *pGmac, uint32_t nanoSec); + +uint16_t GMAC_GetPtpEvtMsgRxdMsbSec( Gmac *pGmac ); + +uint32_t GMAC_GetPtpEvtMsgRxdLsbSec( Gmac *pGmac ); + +uint32_t GMAC_GetPtpEvtMsgRxdNanoSec( Gmac *pGmac ); + +void GMAC_SetTsuCompare(Gmac *pGmac, uint32_t seconds47, uint32_t seconds31, uint32_t nanosec ); + +void GMAC_SetTsuCompareNanoSec(Gmac *pGmac, uint32_t nanosec); + +void GMAC_SetTsuCompareSec31(Gmac *pGmac, uint32_t seconds31); + +void GMAC_SetTsuCompareSec47(Gmac *pGmac, uint16_t seconds47); + +uint32_t GMAC_GetRxEvtFrameSec(Gmac *pGmac); + +uint32_t GMAC_GetRxEvtFrameNsec(Gmac *pGmac); + +uint32_t GMAC_GetRxPeerEvtFrameSec(Gmac *pGmac); + +uint32_t GMAC_GetRxPeerEvtFrameNsec(Gmac *pGmac); + +uint32_t GMAC_GetTxEvtFrameSec(Gmac *pGmac); + +uint32_t GMAC_GetTxEvtFrameNsec(Gmac *pGmac); + +uint32_t GMAC_GetTxPeerEvtFrameSec(Gmac *pGmac); + +uint32_t GMAC_GetTxPeerEvtFrameNsec(Gmac *pGmac); + +#ifdef __cplusplus +} +#endif + +#endif // #ifndef GMAC_H + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/gmacd.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/gmacd.h new file mode 100644 index 00000000..69f913c2 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/gmacd.h @@ -0,0 +1,284 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/** \addtogroup gmacd_module + * @{ + * Implement GMAC data transfer and PHY management functions. + * + * \section Usage + * -# Implement GMAC interrupt handler, which must invoke GMACD_Handler() + * to handle GMAC interrupt events. + * -# Implement sGmacd instance in application. + * -# Initialize the instance with GMACD_Init() and GMACD_InitTransfer(), + * so that GMAC data can be transmitted/received. + * -# Some management callbacks can be set by GMACD_SetRxCallback() + * and GMACD_SetTxWakeupCallback(). + * -# Send ethernet packets using GMACD_Send(), GMACD_TxLoad() is used + * to check the free space in TX queue. + * -# Check and obtain received ethernet packets via GMACD_Poll(). + * + * \sa \ref gmacb_module, \ref gmac_module + * + * Related files:\n + * \ref gmacd.c\n + * \ref gmacd.h.\n + * + * \defgroup gmacd_defines GMAC Driver Defines + * \defgroup gmacd_types GMAC Driver Types + * \defgroup gmacd_functions GMAC Driver Functions + */ +/**@}*/ + +#ifndef _GMACD_H_ +#define _GMACD_H_ + +/*--------------------------------------------------------------------------- + * Headers + *---------------------------------------------------------------------------*/ + +#include "chip.h" + + +/*--------------------------------------------------------------------------- + * Definitions + *---------------------------------------------------------------------------*/ +/** \addtogroup gmacd_defines + @{*/ + + +/** \addtogroup gmacd_rc GMACD Return Codes + @{*/ +#define GMACD_OK 0 /**< Operation OK */ +#define GMACD_TX_BUSY 1 /**< TX in progress */ +#define GMACD_RX_NULL 1 /**< No data received */ +/** Buffer size not enough */ +#define GMACD_SIZE_TOO_SMALL 2 +/** Parameter error, TX packet invalid or RX size too small */ +#define GMACD_PARAM 3 +/** Transfer is not initialized */ +#define GMACD_NOT_INITIALIZED 4 +/** @}*/ + +/** @}*/ + +/* Should be a power of 2. + - Buffer Length to store the timestamps of 1588 event messages +*/ +#define EFRS_BUFFER_LEN (1u) + +/*--------------------------------------------------------------------------- +* Types +*---------------------------------------------------------------------------*/ +/** \addtogroup gmacd_types + @{*/ + +typedef enum ptpMsgType_t +{ + SYNC_MSG_TYPE = 0, + DELAY_REQ_MSG_TYPE = 1, + PDELAY_REQ_TYPE = 2, + PDELAY_RESP_TYPE = 3, + FOLLOW_UP_MSG_TYPE = 8, + DELAY_RESP_MSG_TYPE = 9 +}ptpMsgType; + + + +/** RX callback */ +typedef void (*fGmacdTransferCallback)(uint32_t status); +/** Wakeup callback */ +typedef void (*fGmacdWakeupCallback)(void); +/** Tx PTP message callback */ +typedef void (*fGmacdTxPtpEvtCallBack) (ptpMsgType msg, uint32_t sec, \ + uint32_t nanosec, uint16_t seqId); + +/** + * GMAC scatter-gather entry. + */ +typedef struct _GmacSG { + uint32_t size; + void *pBuffer; +} sGmacSG; + +/** + * GMAC scatter-gather list. + */ +typedef struct _GmacSGList { + uint32_t len; + sGmacSG *sg; +} sGmacSGList; + +/** + * GMAC Queue driver. + */ +typedef struct _GmacQueueDriver { + uint8_t *pTxBuffer; + /** Pointer to allocated RX buffer */ + uint8_t *pRxBuffer; + + /** Pointer to Rx TDs (must be 8-byte aligned) */ + sGmacRxDescriptor *pRxD; + /** Pointer to Tx TDs (must be 8-byte aligned) */ + sGmacTxDescriptor *pTxD; + + /** Optional callback to be invoked once a frame has been received */ + fGmacdTransferCallback fRxCb; + /** Optional callback to be invoked once several TD have been released */ + fGmacdWakeupCallback fWakupCb; + /** Optional callback list to be invoked once TD has been processed */ + fGmacdTransferCallback *fTxCbList; + + /** Optional callback to be invoked on transmit of PTP Event messages */ + fGmacdTxPtpEvtCallBack fTxPtpEvtCb; + + /** RX TD list size */ + uint16_t wRxListSize; + /** RX index for current processing TD */ + uint16_t wRxI; + + /** TX TD list size */ + uint16_t wTxListSize; + /** Circular buffer head pointer by upper layer (buffer to be sent) */ + uint16_t wTxHead; + /** Circular buffer tail pointer incremented by handlers (buffer sent) */ + uint16_t wTxTail; + + /** Number of free TD before wakeup callback is invoked */ + uint8_t bWakeupThreshold; + + /** RX buffer size */ + uint16_t wTxBufferSize; + uint16_t wRxBufferSize; + +} sGmacQd; + +/** + * GMAC driver struct. + */ +typedef struct _GmacDriver { + + /** Pointer to HW register base */ + Gmac *pHw; + /** HW ID */ + uint8_t bId; + /** Base Queue list params **/ + sGmacQd queueList[NUM_GMAC_QUEUES]; +} sGmacd; + +/** + * GMAC driver init struct. + */ +typedef struct _GmacInit { + uint32_t bIsGem:1; + uint32_t reserved:31; + + uint8_t bDmaBurstLength; + + /** RX descriptor and data buffers */ + uint8_t *pRxBuffer; + /** RX data buffers: should be wRxBufferSize * wRxSize byte long in a DMA + capable memory region */ + sGmacRxDescriptor *pRxD; + /** RX buffer descriptors: should have wRxSize entries in a DMA + capable memory region */ + uint16_t wRxBufferSize; /** size of a single RX data buffer */ + uint16_t wRxSize; /** number of RX descriptor and data buffers */ + + /** TX descriptor and data buffers */ + /** TX data buffers: should be wTxBufferSize * wTxSize byte long + in a DMA capable memory region */ + uint8_t *pTxBuffer; + /** TX buffer descriptors: should have wTxSize entries + in a DMA capable non-cached memory region */ + sGmacTxDescriptor *pTxD; + /** size of a single TX data buffer */ + uint16_t wTxBufferSize; + /** number of TX descriptor and data buffers */ + uint16_t wTxSize; + + fGmacdTransferCallback *pTxCb; /** should have wTxSize entries */ +} sGmacInit; +/** @}*/ + +/** \addtogroup gmacd_functions + @{*/ + +/*--------------------------------------------------------------------------- + * GMAC Exported functions + *---------------------------------------------------------------------------*/ + +extern void GMACD_Handler(sGmacd *pGmacd , gmacQueList_t queIdx); + +extern void GMACD_Init(sGmacd *pGmacd, + Gmac *pHw, + uint8_t bID, + uint8_t enableCAF, + uint8_t enableNBC ); + +extern uint8_t GMACD_InitTransfer(sGmacd *pGmacd, + const sGmacInit *pInit, gmacQueList_t queIdx); + +extern void GMACD_Reset(sGmacd *pGmacd); + +extern uint8_t GMACD_SendSG(sGmacd *pGmacd, + const sGmacSGList *sgl, + fGmacdTransferCallback fTxCb, + gmacQueList_t queIdx); + +extern uint8_t GMACD_Send(sGmacd *pGmacd, + void *pBuffer, + uint32_t size, + fGmacdTransferCallback fTxCb, + gmacQueList_t queIdx ); + +extern uint32_t GMACD_TxLoad(sGmacd *pGmacd, gmacQueList_t queIdx); + +extern uint8_t GMACD_Poll(sGmacd * pGmacd, + uint8_t *pFrame, + uint32_t frameSize, + uint32_t *pRcvSize, + gmacQueList_t queIdx); + +extern void GMACD_SetRxCallback(sGmacd * pGmacd, fGmacdTransferCallback + fRxCb, gmacQueList_t queIdx); + +extern uint8_t GMACD_SetTxWakeupCallback(sGmacd * pGmacd, + fGmacdWakeupCallback fWakeup, + uint8_t bThreshold, + gmacQueList_t queIdx); + +extern void GMACD_TxPtpEvtMsgCBRegister (sGmacd * pGmacd, + fGmacdTxPtpEvtCallBack pTxPtpEvtCb, + gmacQueList_t queIdx); + +/** @}*/ + +#endif // #ifndef _GMACD_H_ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/hsmci.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/hsmci.h new file mode 100644 index 00000000..3fa9427c --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/hsmci.h @@ -0,0 +1,154 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/** \addtogroup hsmci_module Working with HSMCI + * \ingroup mcid_module + * + * \section Purpose + * + * The HSMCI driver provides the interface to configure and use the HSMCI + * peripheral. + * + * \section Usage + * + * -# HSMCI_Enable(), MCI_Disable(): Enable/Disable HSMCI interface. + * -# HSMCI_Reset(): Reset HSMCI interface. + * -# HSMCI_Select(): HSMCI slot and buswidth selection + * (\ref Hsmci::HSMCI_SDCR). + * -# HSMCI_ConfigureMode(): Configure the MCI CLKDIV in the _MR register + * (\ref Hsmci::HSMCI_MR). + * -# HSMCI_EnableIt(), HSMCI_DisableIt(), HSMCI_GetItMask(), HSMCI_GetStatus() + * HSMCI Interrupt control (\ref Hsmci::HSMCI_IER, \ref Hsmci::HSMCI_IDR, + * \ref Hsmci::HSMCI_IMR, \ref Hsmci::HSMCI_SR). + * -# HSMCI_ConfigureTransfer(): Setup block length and count for MCI transfer + * (\ref Hsmci::HSMCI_BLKR). + * -# HSMCI_SendCmd(): Send SD/MMC command with argument + * (\ref Hsmci::HSMCI_ARGR, \ref Hsmci::HSMCI_CMDR). + * -# HSMCI_GetResponse(): Get SD/MMC response after command finished + * (\ref Hsmci::HSMCI_RSPR). + * -# HSMCI_ConfigureDma(): Configure MCI DMA transfer + * (\ref Hsmci::HSMCI_DMA). + * -# HSMCI_Configure(): Configure the HSMCI interface (\ref Hsmci::HSMCI_CFG). + * -# HSMCI_HsEnable(), HSMCI_IsHsEnabled(): High Speed control. + * + * For more accurate information, please look at the HSMCI section of the + * Datasheet. + * + * \sa \ref mcid_module + * + * Related files :\n + * \ref hsmci.h\n + * \ref hsmci.c.\n + */ + +#ifndef HSMCID_H +#define HSMCID_H +/** \addtogroup hsmci_module + *@{ + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +#ifdef __cplusplus + extern "C" { +#endif +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +/** \addtogroup hsmci_functions HSMCI Functions + * @{ + */ + +extern void HSMCI_Enable(Hsmci* pRMci); +extern void HSMCI_Disable(Hsmci* pRMci); +extern void HSMCI_Reset(Hsmci* pRMci, uint8_t bBackup); + +extern void HSMCI_Select(Hsmci * pRMci,uint8_t bSlot,uint8_t bBusWidth); +extern void HSMCI_SetSlot(Hsmci * pRMci,uint8_t bSlot); +extern void HSMCI_SetBusWidth(Hsmci * pRMci,uint8_t bBusWidth); +extern uint8_t HSMCI_GetBusWidth(Hsmci * pRMci); + +extern void HSMCI_ConfigureMode(Hsmci *pRMci, uint32_t dwMode); +extern uint32_t HSMCI_GetMode(Hsmci *pRMci); +extern void HSMCI_ProofEnable(Hsmci *pRMci, uint8_t bRdProof, uint8_t bWrProof); +extern void HSMCI_PadvCtl(Hsmci *pRMci, uint8_t bPadv); +extern void HSMCI_FByteEnable(Hsmci *pRMci, uint8_t bFByteEn); +extern uint8_t HSMCI_IsFByteEnabled(Hsmci * pRMci); +extern void HSMCI_DivCtrl(Hsmci *pRMci, uint32_t bClkDiv, uint8_t bPwsDiv); + +extern void HSMCI_EnableIt(Hsmci *pRMci, uint32_t dwSources); +extern void HSMCI_DisableIt(Hsmci *pRMci, uint32_t dwSources); +extern uint32_t HSMCI_GetItMask(Hsmci *pRMci); + +extern void HSMCI_ConfigureTransfer(Hsmci * pRMci,uint16_t wBlkLen,uint16_t wCnt); +extern void HSMCI_SetBlockLen(Hsmci * pRMci,uint16_t wBlkSize); +extern void HSMCI_SetBlockCount(Hsmci * pRMci,uint16_t wBlkCnt); + +extern void HSMCI_ConfigureCompletionTO(Hsmci *pRMci, uint32_t dwConfigure); +extern void HSMCI_ConfigureDataTO(Hsmci *pRMci, uint32_t dwConfigure); + +extern void HSMCI_SendCmd(Hsmci * pRMci,uint32_t dwCmd,uint32_t dwArg); +extern uint32_t HSMCI_GetResponse(Hsmci *pRMci); +extern uint32_t HSMCI_Read(Hsmci *pRMci); +extern void HSMCI_ReadFifo(Hsmci *pRMci, uint8_t *pdwData, uint32_t dwSize); +extern void HSMCI_Write(Hsmci *pRMci, uint32_t dwData); +extern void HSMCI_WriteFifo(Hsmci *pRMci, uint8_t *pdwData, uint32_t dwSize); + +extern uint32_t HSMCI_GetStatus(Hsmci *pRMci); + +extern void HSMCI_ConfigureDma(Hsmci *pRMci, uint32_t dwConfigure); +extern void HSMCI_EnableDma(Hsmci * pRMci,uint8_t bEnable); + +extern void HSMCI_Configure(Hsmci *pRMci, uint32_t dwConfigure); +extern void HSMCI_HsEnable(Hsmci *pRMci, uint8_t bHsEnable); +extern uint8_t HSMCI_IsHsEnabled(Hsmci *pRMci); + +extern void HSMCI_BusWidthCtl(Hsmci *pRMci, uint8_t bBusWidth); +extern void HSMCI_SlotCtl(Hsmci *pRMci, uint8_t bSlot); +extern uint8_t HSMCI_GetSlot(Hsmci *pRMci); + +extern void HSMCI_ConfigureWP(Hsmci *pRMci, uint32_t dwConfigure); +extern uint32_t HSMCI_GetWPStatus(Hsmci *pRMci); + +#ifdef __cplusplus +} +#endif + +/** @}*/ +/**@}*/ +#endif //#ifndef HSMCID_H + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/icm.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/icm.h new file mode 100644 index 00000000..fd53e4e7 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/icm.h @@ -0,0 +1,113 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _ICM_ +#define _ICM_ + +/*------------------------------------------------------------------------------ + * Headers + *------------------------------------------------------------------------------*/ + +#include "chip.h" + + +/*------------------------------------------------------------------------------*/ +/* Definition */ +/*------------------------------------------------------------------------------*/ +#define ICM_RCFG_CDWBN (0x1u << 0) +/**< \brief (ICM_RCFG) Compare Digest or Write Back Digest */ +#define ICM_RCFG_WRAP (0x1u << 1) +/**< \brief (ICM_RCFG) Wrap Command */ +#define ICM_RCFG_EOM (0x1u << 2) +/**< \brief (ICM_RCFG) End Of Monitoring */ +#define ICM_RCFG_RHIEN (0x1u << 4) +/**< \brief (ICM_RCFG) Region Hash Completed interrupt enable */ +#define ICM_RCFG_DMIEN (0x1u << 5) +/**< \brief (ICM_RCFG) Digest Mismatch interrupt enable */ +#define ICM_RCFG_BEIEN (0x1u << 6) +/**< \brief (ICM_RCFG) Bus error interrupt enable */ +#define ICM_RCFG_WCIEN (0x1u << 7) +/**< \brief (ICM_RCFG) Warp condition interrupt enable */ +#define ICM_RCFG_ECIEN (0x1u << 8) +/**< \brief (ICM_RCFG) End bit condition interrupt enable */ +#define ICM_RCFG_SUIEN (0x1u << 9) +/**< \brief (ICM_RCFG) Monitoring Status Updated Condition Interrupt Enable */ +#define ICM_RCFG_PROCDLY (0x1u << 10) +/**< \brief (ICM_RCFG) Processing Delay*/ +#define ICM_RCFG_UALGO_Pos 12 +#define ICM_RCFG_UALGO_Msk (0x7u << ICM_RCFG_UALGO_Pos) +/**< \brief (ICM_RCFG) User SHA Algorithm */ +#define ICM_RCFG_ALGO_SHA1 (0x0u << 12) +/**< \brief (ICM_RCFG) SHA1 algorithm processed */ +#define ICM_RCFG_ALGO_SHA256 (0x1u << 12) +/**< \brief (ICM_RCFG) SHA256 algorithm processed */ +#define ICM_RCFG_ALGO_SHA224 (0x4u << 12) +/**< \brief (ICM_RCFG) SHA224 algorithm processed */ +#define ICM_RCFG_MRPROT_Pos 24 +#define ICM_RCFG_MRPROT_Msk (0x3fu << ICM_RCFG_MRPROT_Pos) +/**< \brief (ICM_RCFG) Memory Region AHB Protection */ +#define ICM_RCFG_MRPROT(value) \ + ((ICM_RCFG_MRPROT_Msk & ((value) << ICM_RCFG_MRPROT_Pos))) + +/*----------------------------------------------------------------------------*/ +/* Type */ +/*----------------------------------------------------------------------------*/ + +/** \brief Structure ICM region descriptor area. */ +typedef struct _LinkedListDescriporIcmRegion +{ + /** the first byte address of the Region. */ + uint32_t icm_raddr; + /** Configuration Structure Member. */ + uint32_t icm_rcfg; + /** Control Structure Member. */ + uint32_t icm_rctrl; + /** Next Address Structure Member. */ + uint32_t icm_rnext; +}LinkedListDescriporIcmRegion; + +/*----------------------------------------------------------------------------*/ +/* Exported functions */ +/*----------------------------------------------------------------------------*/ +extern void ICM_Enable(void); +extern void ICM_Disable(void); +extern void ICM_SoftReset(void); +extern void ICM_ReComputeHash(uint8_t region); +extern void ICM_EnableMonitor(uint8_t region); +extern void ICM_DisableMonitor(uint8_t region); +extern void ICM_Configure(uint32_t mode); +extern void ICM_EnableIt(uint32_t sources); +extern void ICM_DisableIt(uint32_t sources); +extern uint32_t ICM_GetIntStatus(void); +extern uint32_t ICM_GetStatus(void); +extern uint32_t ICM_GetUStatus(void); +extern void ICM_SetDescStartAddress(uint32_t addr); +extern void ICM_SetHashStartAddress(uint32_t addr); +extern void ICM_SetInitHashValue(uint32_t val); +#endif /* #ifndef _ICM_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/isi.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/isi.h new file mode 100644 index 00000000..05018be0 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/isi.h @@ -0,0 +1,204 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/** \addtogroup isi_module + * @{ + * \section gmac_usage Usage + * - ISI_Init: initialize ISI with default parameters + * - ISI_EnableInterrupt: enable one or more interrupts + * - ISI_DisableInterrupt: disable one or more interrupts + * - ISI_Enable: enable isi module + * - ISI_Disable: disable isi module + * - ISI_CodecPathFull: enable codec path + * - ISI_SetFrame: set frame rate + * - ISI_BytesForOnePixel: return number of byte for one pixel + * - ISI_StatusRegister: return ISI status register + * - ISI_Reset: make a software reset + */ +/**@}*/ + +#ifndef ISI_H +#define ISI_H + + + +/*---------------------------------------------------------------------------- + * Definition + *----------------------------------------------------------------------------*/ +#define YUV_INPUT 0 +#define RGB_INPUT 1 +#define GRAYSCALE_INPUT 2 + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** ISI descriptors */ +typedef struct +{ + /** Current LCD index, used with AT91C_ISI_MAX_PREV_BUFFER */ + uint32_t CurrentLcdIndex; + /** set if Fifo Codec Empty is present */ + volatile uint32_t DisplayCodec; + /** upgrade for each Fifo Codec Overflow (statistics use) */ + uint32_t nb_codec_ovf; + /** upgrade for each Fifo Preview Overflow (statistics use) */ + uint32_t nb_prev_ovf; +}ISI_Descriptors; + +/** Frame Buffer Descriptors */ +typedef struct +{ + /** Address of the Current FrameBuffer */ + uint32_t Current; + /** Address of the Control */ + uint32_t Control; + /** Address of the Next FrameBuffer */ + uint32_t Next; +}ISI_FrameBufferDescriptors; + + +/** ISI Matrix Color Space Conversion YCrCb to RGB */ +typedef struct +{ + /** Color Space Conversion Matrix Coefficient C0*/ + uint8_t C0; + /** Color Space Conversion Matrix Coefficient C1 */ + uint8_t C1; + /** Color Space Conversion Matrix Coefficient C2 */ + uint8_t C2; + /** Color Space Conversion Matrix Coefficient C3 */ + uint8_t C3; + /** Color Space Conversion Red Chrominance Default Offset */ + uint8_t Croff; + /** Color Space Conversion Blue Chrominance Default Offset */ + uint8_t Cboff; + /** Color Space Conversion Luminance Default Offset */ + uint8_t Yoff; + /** Color Space Conversion Matrix Coefficient C4 */ + uint16_t C4; +}ISI_Y2R; + +/** ISI Matrix Color Space Conversion RGB to YCrCb */ +typedef struct +{ + /** Color Space Conversion Matrix Coefficient C0*/ + uint8_t C0; + /** Color Space Conversion Matrix Coefficient C1 */ + uint8_t C1; + /** Color Space Conversion Matrix Coefficient C2 */ + uint8_t C2; + /** Color Space Conversion Red Component Offset */ + uint8_t Roff; + /** Color Space Conversion Matrix Coefficient C3*/ + uint8_t C3; + /** Color Space Conversion Matrix Coefficient C4 */ + uint8_t C4; + /** Color Space Conversion Matrix Coefficient C5 */ + uint8_t C5; + /** Color Space Conversion Green Component Offset */ + uint8_t Goff; + /** Color Space Conversion Matrix Coefficient C6*/ + uint8_t C6; + /** Color Space Conversion Matrix Coefficient C7 */ + uint8_t C7; + /** Color Space Conversion Matrix Coefficient C8 */ + uint8_t C8; + /** Color Space Conversion Blue Component Offset */ + uint8_t Boff; +}ISI_R2Y; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +extern void ISI_Enable(void); + +extern void ISI_Disable(void); + +void ISI_DmaChannelEnable(uint32_t channel); + +void ISI_DmaChannelDisable(uint32_t channel); + +extern void ISI_EnableInterrupt(uint32_t flag); + +extern void ISI_DisableInterrupt(uint32_t flag); + +extern void ISI_CodecPathFull(void); + +extern void ISI_SetFrameRate(uint32_t frame); + +extern uint8_t ISI_BytesForOnePixel(uint8_t bmpRgb); + +extern void ISI_Reset(void); + +extern void ISI_Init(pIsi_Video pVideo); + +extern uint32_t ISI_StatusRegister(void); + +extern void ISI_SetBlank( + uint8_t hBlank, + uint8_t vBlank); + +extern void ISI_SetSensorSize( + uint32_t hSize, + uint32_t vSize); + +extern void ISI_RgbPixelMapping(uint32_t wRgbPixelMapping); + +extern void ISI_RgbSwapMode(uint32_t swapMode); + +extern void ISI_YCrCbFormat(uint32_t wYuvSwapMode); + +extern void ISI_setGrayScaleMode(uint32_t wPixelFormat); + +extern void ISI_setInputStream(uint32_t wStreamMode); + +extern void ISI_setPreviewSize( + uint32_t hSize, + uint32_t vSize); + +extern void ISI_calcScalerFactor( void ); + +extern void ISI_setDmaInPreviewPath( + uint32_t baseFrameBufDesc, + uint32_t dmaCtrl, + uint32_t frameBufferStartAddr); + +extern void ISI_setDmaInCodecPath( + uint32_t baseFrameBufDesc, + uint32_t dmaCtrl, + uint32_t frameBufferStartAddr); + +extern void ISI_SetMatrix4Yuv2Rgb (ISI_Y2R* yuv2rgb); +extern void ISI_SetMatrix4Rgb2Yuv (ISI_R2Y* rgb2yuv); + +#endif //#ifndef ISI_H + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/iso7816_4.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/iso7816_4.h new file mode 100644 index 00000000..4a7b9a78 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/iso7816_4.h @@ -0,0 +1,110 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/** \page + * + * \section Purpose + * + * Definition of methods for ISO7816 driver. + * + * \section Usage + * + * -# ISO7816_Init + * -# ISO7816_IccPowerOff + * -# ISO7816_XfrBlockTPDU_T0 + * -# ISO7816_Escape + * -# ISO7816_RestartClock + * -# ISO7816_StopClock + * -# ISO7816_toAPDU + * -# ISO7816_Datablock_ATR + * -# ISO7816_SetDataRateandClockFrequency + * -# ISO7816_StatusReset + * -# ISO7816_cold_reset + * -# ISO7816_warm_reset + * -# ISO7816_Decode_ATR + *----------------------------------------------------------------------------*/ + +#ifndef ISO7816_4_H +#define ISO7816_4_H + +#include "chip.h" + +/*------------------------------------------------------------------------------ + * Constants Definition + *----------------------------------------------------------------------------*/ + +/** Size max of Answer To Reset */ +#define ATR_SIZE_MAX 55 + +/** NULL byte to restart byte procedure */ +#define ISO_NULL_VAL 0x60 + +/*------------------------------------------------------------------------------ + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void ISO7816_Init( + Usart *pUsart, + uint32_t usartId , + const Pin pPinIso7816RstMC ); + +extern void ISO7816_IccPowerOff( void ); + +extern uint16_t ISO7816_XfrBlockTPDU_T0( + const uint8_t *pAPDU, + uint8_t *pMessage, + uint16_t wLength ); + +extern void ISO7816_Escape( void ); + +extern void ISO7816_RestartClock( void); + +extern void ISO7816_StopClock( void ); + +extern void ISO7816_toAPDU( void ); + +extern void ISO7816_Datablock_ATR( + uint8_t* pAtr, + uint8_t* pLength ); + +extern void ISO7816_SetDataRateandClockFrequency( + uint32_t dwClockFrequency, + uint32_t dwDataRate ); + +extern uint8_t ISO7816_StatusReset( void ); + +extern void ISO7816_cold_reset( void ); + +extern void ISO7816_warm_reset( void ); + +extern void ISO7816_Decode_ATR( uint8_t* pAtr ); + +#endif /* ISO7816_4_H */ + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/mcan.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/mcan.h new file mode 100644 index 00000000..c28a93d0 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/mcan.h @@ -0,0 +1,344 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \section Purpose + * + * Interface for configuring and using Timer Counter (TC) peripherals. + * + * \section Usage + * -# Optionally, use TC_FindMckDivisor() to let the program find the best + * TCCLKS field value automatically. + * -# Configure a Timer Counter in the desired mode using TC_Configure(). + * -# Start or stop the timer clock using TC_Start() and TC_Stop(). + */ + +#ifndef _MCAN_ +#define _MCAN_ + +/*------------------------------------------------------------------------------ + * Headers + *------------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*------------------------------------------------------------------------------ + * Global functions + *------------------------------------------------------------------------------*/ + +#ifdef __cplusplus + extern "C" { +#endif + +typedef enum +{ + CAN_STD_ID = 0, + CAN_EXT_ID = 1 +} MCan_IdType; + +typedef enum +{ + CAN_DLC_0 = 0, + CAN_DLC_1 = 1, + CAN_DLC_2 = 2, + CAN_DLC_3 = 3, + CAN_DLC_4 = 4, + CAN_DLC_5 = 5, + CAN_DLC_6 = 6, + CAN_DLC_7 = 7, + CAN_DLC_8 = 8, + CAN_DLC_12 = 9, + CAN_DLC_16 = 10, + CAN_DLC_20 = 11, + CAN_DLC_24 = 12, + CAN_DLC_32 = 13, + CAN_DLC_48 = 14, + CAN_DLC_64 = 15 +} MCan_DlcType; + +typedef enum +{ + CAN_FIFO_0 = 0, + CAN_FIFO_1 = 1 +} MCan_FifoType; + +typedef enum +{ + CAN_INTR_LINE_0 = 0, + CAN_INTR_LINE_1 = 1 +} MCan_IntrLineType; + +typedef struct MailboxInfoTag +{ + uint32_t id; + uint32_t length; + uint32_t timestamp; +} MailboxInfoType; + + +typedef struct MailBox8Tag +{ + MailboxInfoType info; + uint8_t data[8]; +} Mailbox8Type; + +typedef struct MailBox12Tag +{ + MailboxInfoType info; + uint8_t data[12]; +} Mailbox12Type; + +typedef struct MailBox16Tag +{ + MailboxInfoType info; + uint8_t data[16]; +} Mailbox16Type; + +typedef struct MailBox20Tag +{ + MailboxInfoType info; + uint8_t data[20]; +} Mailbox20Type; + +typedef struct MailBox24Tag +{ + MailboxInfoType info; + uint8_t data[24]; +} Mailbox24Type; + +typedef struct MailBox32Tag +{ + MailboxInfoType info; + uint8_t data[32]; +} Mailbox32ype; + +typedef struct MailBox48Tag +{ + MailboxInfoType info; + uint8_t data[48]; +} Mailbox48Type; + +typedef struct MailBox64Tag +{ + MailboxInfoType info; + uint8_t data[64]; +} Mailbox64Type; + + + +typedef struct MCan_MsgRamPntrsTag +{ + uint32_t * pStdFilts; + uint32_t * pExtFilts; + uint32_t * pRxFifo0; + uint32_t * pRxFifo1; + uint32_t * pRxDedBuf; + uint32_t * pTxEvtFifo; + uint32_t * pTxDedBuf; + uint32_t * pTxFifoQ; +} MCan_MsgRamPntrs; + +typedef struct MCan_ConfigTag +{ + Mcan * pMCan; + uint32_t bitTiming; + uint32_t fastBitTiming; + uint32_t nmbrStdFilts; + uint32_t nmbrExtFilts; + uint32_t nmbrFifo0Elmts; + uint32_t nmbrFifo1Elmts; + uint32_t nmbrRxDedBufElmts; + uint32_t nmbrTxEvtFifoElmts; + uint32_t nmbrTxDedBufElmts; + uint32_t nmbrTxFifoQElmts; + uint32_t rxFifo0ElmtSize; + uint32_t rxFifo1ElmtSize; + uint32_t rxBufElmtSize; + // Element sizes and data sizes (encoded element size) + uint32_t txBufElmtSize; + // Element size and data size (encoded element size) + MCan_MsgRamPntrs msgRam; +} MCan_ConfigType; + +extern const MCan_ConfigType mcan0Config; +extern const MCan_ConfigType mcan1Config; + +__STATIC_INLINE uint32_t MCAN_IsTxComplete( + const MCan_ConfigType * mcanConfig ) +{ + Mcan * mcan = mcanConfig->pMCan; + return ( mcan->MCAN_IR & MCAN_IR_TC ); +} + +__STATIC_INLINE void MCAN_ClearTxComplete( + const MCan_ConfigType * mcanConfig ) +{ + Mcan * mcan = mcanConfig->pMCan; + mcan->MCAN_IR = MCAN_IR_TC; +} + +__STATIC_INLINE uint32_t MCAN_IsMessageStoredToRxDedBuffer( + const MCan_ConfigType * mcanConfig ) +{ + Mcan * mcan = mcanConfig->pMCan; + + return ( mcan->MCAN_IR & MCAN_IR_DRX ); +} + +__STATIC_INLINE void MCAN_ClearMessageStoredToRxBuffer( + const MCan_ConfigType * mcanConfig ) +{ + Mcan * mcan = mcanConfig->pMCan; + mcan->MCAN_IR = MCAN_IR_DRX; +} + +__STATIC_INLINE uint32_t MCAN_IsMessageStoredToRxFifo0( + const MCan_ConfigType * mcanConfig ) +{ + Mcan * mcan = mcanConfig->pMCan; + return ( mcan->MCAN_IR & MCAN_IR_RF0N ); +} + +__STATIC_INLINE void MCAN_ClearMessageStoredToRxFifo0( + const MCan_ConfigType * mcanConfig ) +{ + Mcan * mcan = mcanConfig->pMCan; + mcan->MCAN_IR = MCAN_IR_RF0N; +} + +__STATIC_INLINE uint32_t MCAN_IsMessageStoredToRxFifo1( + const MCan_ConfigType * mcanConfig ) +{ + Mcan * mcan = mcanConfig->pMCan; + return ( mcan->MCAN_IR & MCAN_IR_RF1N ); +} + +__STATIC_INLINE void MCAN_ClearMessageStoredToRxFifo1( + const MCan_ConfigType * mcanConfig ) +{ + Mcan * mcan = mcanConfig->pMCan; + mcan->MCAN_IR = MCAN_IR_RF1N; +} + +void MCAN_Init( + const MCan_ConfigType * mcanConfig ); + +void MCAN_InitFdEnable( + const MCan_ConfigType * mcanConfig ); + +void MCAN_InitFdBitRateSwitchEnable( + const MCan_ConfigType * mcanConfig ); + +void MCAN_InitTxQueue( + const MCan_ConfigType * mcanConfig ); + +void MCAN_InitLoopback( + const MCan_ConfigType * mcanConfig ); + +void MCAN_Enable( + const MCan_ConfigType * mcanConfig ); + +void MCAN_RequestIso11898_1( + const MCan_ConfigType * mcanConfig ); + +void MCAN_RequestFd( + const MCan_ConfigType * mcanConfig ); + +void MCAN_RequestFdBitRateSwitch( + const MCan_ConfigType * mcanConfig ); + +void MCAN_LoopbackOn( + const MCan_ConfigType * mcanConfig ); + +void MCAN_LoopbackOff( + const MCan_ConfigType * mcanConfig ); + +void MCAN_IEnableMessageStoredToRxDedBuffer( + const MCan_ConfigType * mcanConfig, + MCan_IntrLineType line ); + +uint8_t * MCAN_ConfigTxDedBuffer( + const MCan_ConfigType * mcanConfig, + uint8_t buffer, + uint32_t id, + MCan_IdType idType, + MCan_DlcType dlc ); + +void MCAN_SendTxDedBuffer( + const MCan_ConfigType * mcanConfig, + uint8_t buffer ); + +uint32_t MCAN_AddToTxFifoQ( + const MCan_ConfigType * mcanConfig, + uint32_t id, MCan_IdType idType, + MCan_DlcType dlc, uint8_t * data ); + +uint8_t MCAN_IsBufferTxd( + const MCan_ConfigType * mcanConfig, + uint8_t buffer ); + +void MCAN_ConfigRxBufferFilter( + const MCan_ConfigType * mcanConfig, + uint32_t buffer, + uint32_t filter, + uint32_t id, + MCan_IdType idType); + +void MCAN_ConfigRxClassicFilter( + const MCan_ConfigType * mcanConfig, + MCan_FifoType fifo, + uint8_t filter, + uint32_t id, + MCan_IdType idType, + uint32_t mask ); + +uint8_t MCAN_IsNewDataInRxDedBuffer( + const MCan_ConfigType * mcanConfig, + uint8_t buffer ); + +void MCAN_GetRxDedBuffer( + const MCan_ConfigType * mcanConfig, + uint8_t buffer, + Mailbox64Type * pRxMailbox ); + +uint32_t MCAN_GetRxFifoBuffer( + const MCan_ConfigType * mcanConfig, + MCan_FifoType fifo, + Mailbox64Type * pRxMailbox ); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _MCAN_ */ + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/mcid.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/mcid.h new file mode 100644 index 00000000..5b4a118f --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/mcid.h @@ -0,0 +1,172 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + +/** \file */ + +/** + * \ingroup sdmmc_hal + * \addtogroup mcid_module MCI Driver (HAL for SD/MMC Lib) + * + * \section Purpose + * + * This driver implements SD(IO)/MMC command operations and MCI configuration + * routines to perform SD(IO)/MMC access. It's used for upper layer + * (\ref libsdmmc_module "SD/MMC driver") to perform SD/MMC operations. + * + * \section Usage + * + * -# MCID_Init(): Initializes a MCI driver instance and the underlying + * peripheral. + * -# MCID_SendCmd(): Starts a MCI transfer which described by + * \ref sSdmmcCommand. + * -# MCID_CancelCmd(): Cancel a pending command. + * -# MCID_IsCmdCompleted(): Check if MCI transfer is finished. + * -# MCID_Handler(): Interrupt handler which is called by ISR handler. + * -# MCID_IOCtrl(): IO control function to report HW attributes to upper + * layer driver and modify HW settings (such as clock + * frequency, High-speed support, etc. See + * \ref sdmmc_ioctrls). + * + * \sa \ref dmad_module "DMA Driver", \ref hsmci_module "HSMCI", + * \ref libsdmmc_module "SD/MMC Library" + * + * Related files:\n + * \ref mcid.h\n + * \ref mcid_dma.c.\n + */ + +#ifndef MCID_H +#define MCID_H +/** \addtogroup mcid_module + *@{ + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include +#include + +/** \addtogroup mcid_defines MCI Driver Defines + * @{*/ + +/*---------------------------------------------------------------------------- + * Constants + *----------------------------------------------------------------------------*/ + +/** MCI States */ +#define MCID_IDLE 0 /**< Idle */ +#define MCID_LOCKED 1 /**< Locked for specific slot */ +#define MCID_CMD 2 /**< Processing the command */ +#define MCID_ERROR 3 /**< Command error */ + +/** MCI Initialize clock 400K Hz */ +#define MCI_INITIAL_SPEED 400000 + +/** @}*/ + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ +/** \addtogroup mcid_structs MCI Driver Data Structs + * @{ + */ +#ifdef __cplusplus + extern "C" { +#endif + +/** + * \brief MCI Driver + */ +typedef struct _Mcid +{ + /** Pointer to a MCI peripheral. */ + Hsmci *pMciHw; + /** Pointer to a DMA driver */ + sXdmad *pXdmad; + /** Pointer to currently executing command. */ + void *pCmd; + /** MCK source, Hz */ + uint32_t dwMck; + /** DMA transfer channel */ + uint32_t dwDmaCh; + /** DMA transferred data index (bytes) */ + uint32_t dwXfrNdx; + /** DMA transfer size (bytes) */ + uint32_t dwXSize; + /** MCI peripheral identifier. */ + uint8_t bID; + /** Polling mode */ + uint8_t bPolling; + /** Reserved */ + uint8_t reserved; + /** state. */ + volatile uint8_t bState; +} sMcid; + +/** @}*/ +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +/** \addtogroup mcid_functions MCI Driver Functions + @{*/ +extern void MCID_Init(sMcid * pMcid, + Hsmci * pMci, uint8_t bID, uint32_t dwMck, + sXdmad * pXdmad, + uint8_t bPolling); + +extern void MCID_Reset(sMcid * pMcid); + +extern void MCID_SetSlot(Hsmci *pMci, uint8_t slot); + +extern uint32_t MCID_Lock(sMcid * pMcid, uint8_t bSlot); + +extern uint32_t MCID_Release(sMcid * pMcid); + +extern void MCID_Handler(sMcid * pMcid); + +extern uint32_t MCID_SendCmd(sMcid * pMcid, void * pCmd); + +extern uint32_t MCID_CancelCmd(sMcid * pMcid); + +extern uint32_t MCID_IsCmdCompleted(sMcid * pMcid); + +extern uint32_t MCID_IOCtrl(sMcid * pMcid,uint32_t bCtl,uint32_t param); + +#ifdef __cplusplus +} +#endif +/** @}*/ +/**@}*/ +#endif //#ifndef HSMCID_H + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/mediaLB.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/mediaLB.h new file mode 100644 index 00000000..b922a861 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/mediaLB.h @@ -0,0 +1,45 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _MEDILB_H_ +#define _MEDILB_H_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + + + +#endif /* #ifndef _MEDILB_H_ */ + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/mpu.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/mpu.h new file mode 100644 index 00000000..753b3117 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/mpu.h @@ -0,0 +1,172 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _MPU_H_ +#define _MPU_H_ + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ +#define ARM_MODE_USR 0x10 + +#define PRIVILEGE_MODE 0 +#define USER_MODE 1 + +#define MPU_DEFAULT_ITCM_REGION ( 1 ) +#define MPU_DEFAULT_IFLASH_REGION ( 2 ) +#define MPU_DEFAULT_DTCM_REGION ( 3 ) +#define MPU_DEFAULT_SRAM_REGION_1 ( 4 ) +#define MPU_DEFAULT_SRAM_REGION_2 ( 5 ) +#define MPU_PERIPHERALS_REGION ( 6 ) +#define MPU_EXT_EBI_REGION ( 7 ) +#define MPU_DEFAULT_SDRAM_REGION ( 8 ) +#define MPU_QSPIMEM_REGION ( 9 ) +#define MPU_USBHSRAM_REGION ( 10 ) +#if defined MPU_HAS_NOCACHE_REGION +#define MPU_NOCACHE_SRAM_REGION ( 11 ) +#endif + +#define MPU_REGION_VALID ( 0x10 ) +#define MPU_REGION_ENABLE ( 0x01 ) +#define MPU_REGION_DISABLE ( 0x0 ) + +#define MPU_ENABLE ( 0x1 << MPU_CTRL_ENABLE_Pos) +#define MPU_HFNMIENA ( 0x1 << MPU_CTRL_HFNMIENA_Pos ) +#define MPU_PRIVDEFENA ( 0x1 << MPU_CTRL_PRIVDEFENA_Pos ) + + +#define MPU_REGION_BUFFERABLE ( 0x01 << MPU_RASR_B_Pos ) +#define MPU_REGION_CACHEABLE ( 0x01 << MPU_RASR_C_Pos ) +#define MPU_REGION_SHAREABLE ( 0x01 << MPU_RASR_S_Pos ) + +#define MPU_REGION_EXECUTE_NEVER ( 0x01 << MPU_RASR_XN_Pos ) + +#define MPU_AP_NO_ACCESS ( 0x00 << MPU_RASR_AP_Pos ) +#define MPU_AP_PRIVILEGED_READ_WRITE ( 0x01 << MPU_RASR_AP_Pos ) +#define MPU_AP_UNPRIVILEGED_READONLY ( 0x02 << MPU_RASR_AP_Pos ) +#define MPU_AP_FULL_ACCESS ( 0x03 << MPU_RASR_AP_Pos ) +#define MPU_AP_RES ( 0x04 << MPU_RASR_AP_Pos ) +#define MPU_AP_PRIVILEGED_READONLY ( 0x05 << MPU_RASR_AP_Pos ) +#define MPU_AP_READONLY ( 0x06 << MPU_RASR_AP_Pos ) +#define MPU_AP_READONLY2 ( 0x07 << MPU_RASR_AP_Pos ) + +#define MPU_TEX_B000 ( 0x01 << MPU_RASR_TEX_Pos ) +#define MPU_TEX_B001 ( 0x01 << MPU_RASR_TEX_Pos ) +#define MPU_TEX_B010 ( 0x01 << MPU_RASR_TEX_Pos ) +#define MPU_TEX_B011 ( 0x01 << MPU_RASR_TEX_Pos ) +#define MPU_TEX_B100 ( 0x01 << MPU_RASR_TEX_Pos ) +#define MPU_TEX_B101 ( 0x01 << MPU_RASR_TEX_Pos ) +#define MPU_TEX_B110 ( 0x01 << MPU_RASR_TEX_Pos ) +#define MPU_TEX_B111 ( 0x01 << MPU_RASR_TEX_Pos ) + +/* Default memory map + Address range Memory region Memory type Shareability Cache policy + 0x00000000- 0x1FFFFFFF Code Normal Non-shareable WT + 0x20000000- 0x3FFFFFFF SRAM Normal Non-shareable WBWA + 0x40000000- 0x5FFFFFFF Peripheral Device Non-shareable - + 0x60000000- 0x7FFFFFFF RAM Normal Non-shareable WBWA + 0x80000000- 0x9FFFFFFF RAM Normal Non-shareable WT + 0xA0000000- 0xBFFFFFFF Device Device Shareable + 0xC0000000- 0xDFFFFFFF Device Device Non Shareable + 0xE0000000- 0xFFFFFFFF System - - + */ + +/********* IFLASH memory macros *********************/ +#define ITCM_START_ADDRESS 0x00000000UL +#define ITCM_END_ADDRESS 0x003FFFFFUL +#define IFLASH_START_ADDRESS 0x00400000UL +#define IFLASH_END_ADDRESS 0x005FFFFFUL + + +#define IFLASH_PRIVILEGE_START_ADDRESS (IFLASH_START_ADDRESS) +#define IFLASH_PRIVILEGE_END_ADDRESS (IFLASH_START_ADDRESS + 0xFFF) + +#define IFLASH_UNPRIVILEGE_START_ADDRESS (IFLASH_PRIVILEGE_END_ADDRESS + 1) +#define IFLASH_UNPRIVILEGE_END_ADDRESS (IFLASH_END_ADDRESS) + +/**************** DTCM *******************************/ +#define DTCM_START_ADDRESS 0x20000000UL +#define DTCM_END_ADDRESS 0x203FFFFFUL + + +/******* SRAM memory macros ***************************/ + +#define SRAM_START_ADDRESS 0x20400000UL +#define SRAM_END_ADDRESS 0x2045FFFFUL + +#if defined MPU_HAS_NOCACHE_REGION +#define NOCACHE_SRAM_REGION_SIZE 0x1000 +#endif + +/* Regions should be a 2^(N+1) where 4 < N < 31 */ +#define SRAM_FIRST_START_ADDRESS (SRAM_START_ADDRESS) +#define SRAM_FIRST_END_ADDRESS (SRAM_FIRST_START_ADDRESS + 0x3FFFF) // (2^18) 256 KB + +#if defined MPU_HAS_NOCACHE_REGION +#define SRAM_SECOND_START_ADDRESS (SRAM_FIRST_END_ADDRESS+1) +#define SRAM_SECOND_END_ADDRESS (SRAM_END_ADDRESS - NOCACHE_SRAM_REGION_SIZE ) // (2^17) 128 - 0x1000 KB +#define SRAM_NOCACHE_START_ADDRESS (SRAM_SECOND_END_ADDRESS + 1) +#define SRAM_NOCACHE_END_ADDRESS (SRAM_END_ADDRESS ) +#else +#define SRAM_SECOND_START_ADDRESS (SRAM_FIRST_END_ADDRESS + 1) +#define SRAM_SECOND_END_ADDRESS (SRAM_END_ADDRESS) // (2^17) 128 KB +#endif +/************** Peripherals memory region macros ********/ +#define PERIPHERALS_START_ADDRESS 0x40000000UL +#define PERIPHERALS_END_ADDRESS 0x5FFFFFFFUL + +/******* Ext EBI memory macros ***************************/ +#define EXT_EBI_START_ADDRESS 0x60000000UL +#define EXT_EBI_END_ADDRESS 0x6FFFFFFFUL + +/******* Ext-SRAM memory macros ***************************/ +#define SDRAM_START_ADDRESS 0x70000000UL +#define SDRAM_END_ADDRESS 0x7FFFFFFFUL + +/******* QSPI macros ***************************/ +#define QSPI_START_ADDRESS 0x80000000UL +#define QSPI_END_ADDRESS 0x9FFFFFFFUL + +/************** USBHS_RAM region macros ******************/ +#define USBHSRAM_START_ADDRESS 0xA0100000UL +#define USBHSRAM_END_ADDRESS 0xA01FFFFFUL + +/*---------------------------------------------------------------------------- + * Export functions + *----------------------------------------------------------------------------*/ +void MPU_Enable( uint32_t dwMPUEnable ); +void MPU_SetRegion( uint32_t dwRegionBaseAddr, uint32_t dwRegionAttr ); +void MPU_SetRegionNum( uint32_t dwRegionNum ); +void MPU_DisableRegion( void ); +uint32_t MPU_CalMPURegionSize( uint32_t dwActualSizeInBytes ); +void MPU_UpdateRegions( uint32_t dwRegionNum, uint32_t dwRegionBaseAddr, + uint32_t dwRegionAttr); + +#endif /* #ifndef _MMU_ */ + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/pio.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/pio.h new file mode 100644 index 00000000..e9a4bb82 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/pio.h @@ -0,0 +1,218 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \section Purpose + * + * This file provides a basic API for PIO configuration and usage of + * user-controlled pins. Please refer to the board.h file for a list of + * available pin definitions. + * + * \section Usage + * + * -# Define a constant pin description array such as the following one, using + * the existing definitions provided by the board.h file if possible: + * \code + * const Pin pPins[] = {PIN_USART0_TXD, PIN_USART0_RXD}; + * \endcode + * Alternatively, it is possible to add new pins by provided the full Pin + * structure: + * \code + * // Pin instance to configure PA10 & PA11 as inputs with the internal + * // pull-up enabled. + * const Pin pPins = { + * (1 << 10) | (1 << 11), + * REG_PIOA, + * ID_PIOA, + * PIO_INPUT, + * PIO_PULLUP + * }; + * \endcode + * -# Configure a pin array by calling PIO_Configure() with a pointer to the + * array and its size (which is computed using the PIO_LISTSIZE macro). + * -# Change and get the value of a user-controlled pin using the PIO_Set, + * PIO_Clear and PIO_Get methods. + * -# Get the level being currently output by a user-controlled pin configured + * as an output using PIO_GetOutputDataStatus(). + */ + +#ifndef _PIO_ +#define _PIO_ + +/* + * Headers + */ + +#include "chip.h" + +#include + +/* + * Global Definitions + */ + +/** The pin is controlled by the associated signal of peripheral A. */ +#define PIO_PERIPH_A 0 +/** The pin is controlled by the associated signal of peripheral B. */ +#define PIO_PERIPH_B 1 +/** The pin is controlled by the associated signal of peripheral C. */ +#define PIO_PERIPH_C 2 +/** The pin is controlled by the associated signal of peripheral D. */ +#define PIO_PERIPH_D 3 +/** The pin is an input. */ +#define PIO_INPUT 4 +/** The pin is an output and has a default level of 0. */ +#define PIO_OUTPUT_0 5 +/** The pin is an output and has a default level of 1. */ +#define PIO_OUTPUT_1 6 + +/** Default pin configuration (no attribute). */ +#define PIO_DEFAULT (0 << 0) +/** The internal pin pull-up is active. */ +#define PIO_PULLUP (1 << 0) +/** The internal glitch filter is active. */ +#define PIO_DEGLITCH (1 << 1) +/** The pin is open-drain. */ +#define PIO_OPENDRAIN (1 << 2) + +/** The internal debouncing filter is active. */ +#define PIO_DEBOUNCE (1 << 3) + +/** Enable additional interrupt modes. */ +#define PIO_IT_AIME (1 << 4) + +/** Interrupt High Level/Rising Edge detection is active. */ +#define PIO_IT_RE_OR_HL (1 << 5) +/** Interrupt Edge detection is active. */ +#define PIO_IT_EDGE (1 << 6) + +/** Low level interrupt is active */ +#define PIO_IT_LOW_LEVEL (0 | 0 | PIO_IT_AIME) +/** High level interrupt is active */ +#define PIO_IT_HIGH_LEVEL (PIO_IT_RE_OR_HL | 0 | PIO_IT_AIME) +/** Falling edge interrupt is active */ +#define PIO_IT_FALL_EDGE (0 | PIO_IT_EDGE | PIO_IT_AIME) +/** Rising edge interrupt is active */ +#define PIO_IT_RISE_EDGE (PIO_IT_RE_OR_HL | PIO_IT_EDGE | PIO_IT_AIME) +/** The WP is enable */ +#define PIO_WPMR_WPEN_EN ( 0x01 << 0 ) +/** The WP is disable */ +#define PIO_WPMR_WPEN_DIS ( 0x00 << 0 ) +/** Valid WP key */ +#define PIO_WPMR_WPKEY_VALID ( 0x50494F << 8 ) +#ifdef __cplusplus + extern "C" { +#endif + +/* + * Global Macros + */ + +/** + * Calculates the size of an array of Pin instances. The array must be defined + * locally (i.e. not a pointer), otherwise the computation will not be correct. + * \param pPins Local array of Pin instances. + * \return Number of elements in array. + */ +#define PIO_LISTSIZE(pPins) (sizeof(pPins) / sizeof(Pin)) + +/* + * Global Types + */ + + +/* + * Describes the type and attribute of one PIO pin or a group of similar pins. + * The #type# field can have the following values: + * - PIO_PERIPH_A + * - PIO_PERIPH_B + * - PIO_OUTPUT_0 + * - PIO_OUTPUT_1 + * - PIO_INPUT + * + * The #attribute# field is a bitmask that can either be set to PIO_DEFAULt, + * or combine (using bitwise OR '|') any number of the following constants: + * - PIO_PULLUP + * - PIO_DEGLITCH + * - PIO_DEBOUNCE + * - PIO_OPENDRAIN + * - PIO_IT_LOW_LEVEL + * - PIO_IT_HIGH_LEVEL + * - PIO_IT_FALL_EDGE + * - PIO_IT_RISE_EDGE + */ +typedef struct _Pin +{ + /* Bitmask indicating which pin(s) to configure. */ + uint32_t mask; + /* Pointer to the PIO controller which has the pin(s). */ + Pio *pio; + /* Peripheral ID of the PIO controller which has the pin(s). */ + uint8_t id; + /* Pin type. */ + uint8_t type; + /* Pin attribute. */ + uint8_t attribute; +} Pin ; + +/* + * Global Access Macros + */ + +/* + * Global Functions + */ + +extern uint8_t PIO_Configure( const Pin *list, uint32_t size ) ; + +extern void PIO_Set( const Pin *pin ) ; + +extern void PIO_Clear( const Pin *pin ) ; + +extern uint8_t PIO_Get( const Pin *pin ) ; + +extern uint8_t PIO_GetOutputDataStatus( const Pin *pin ) ; + +extern void PIO_SetDebounceFilter( const Pin *pin, uint32_t cuttoff ); + +extern void PIO_EnableWriteProtect( const Pin *pin ); + +extern void PIO_DisableWriteProtect( const Pin *pin ); + +extern void PIO_SetPinType( Pin * pin, uint8_t pinType); + +extern uint32_t PIO_GetWriteProtectViolationInfo( const Pin * pin ); +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _PIO_ */ + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/pio_capture.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/pio_capture.h new file mode 100644 index 00000000..cac9991a --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/pio_capture.h @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef PIO_CAPTURE_H +#define PIO_CAPTURE_H + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** \brief PIO Parallel Capture structure for initialize. + * + * At the end of the transfer, the callback is invoked by the interrupt handler. + */ +typedef struct _SpioCaptureInit { + + /** PIO_PCRHR register is a BYTE, HALF-WORD or WORD */ + uint8_t dsize; + /** PDC size, data to be received */ + uint16_t dPDCsize; + /** Data to be received */ + uint32_t *pData; + /** Parallel Capture Mode Always Sampling */ + uint8_t alwaysSampling; + /** Parallel Capture Mode Half Sampling */ + uint8_t halfSampling; + /** Parallel Capture Mode First Sample */ + uint8_t modeFirstSample; + /** Callback function invoked at Mode Data Ready */ + void (*CbkDataReady)( struct _SpioCaptureInit* ); + /** Callback function invoked at Mode Overrun Error */ + void (*CbkOverrun)( struct _SpioCaptureInit* ); + /** Callback function invoked at End of Reception Transfer */ + void (*CbkEndReception)( struct _SpioCaptureInit* ); + /** Callback function invoked at Reception Buffer Full */ + void (*CbkBuffFull)( struct _SpioCaptureInit* ); + /** Callback arguments.*/ + void *pParam; + +} SpioCaptureInit ; + + +/*---------------------------------------------------------------------------- + * Global Functions + *----------------------------------------------------------------------------*/ +extern void PIO_CaptureDisableIt( uint32_t itToDisable ) ; +extern void PIO_CaptureEnableIt( uint32_t itToEnable ) ; +extern void PIO_CaptureEnable( void ) ; +extern void PIO_CaptureDisable( void ) ; +extern void PIO_CaptureInit( SpioCaptureInit* pInit ) ; + +#endif /* #ifndef PIO_CAPTURE_H */ + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/pio_it.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/pio_it.h new file mode 100644 index 00000000..c8d594c8 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/pio_it.h @@ -0,0 +1,97 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \par Purpose + * + * Configuration and handling of interrupts on PIO status changes. The API + * provided here have several advantages over the traditional PIO interrupt + * configuration approach: + * - It is highly portable + * - It automatically demultiplexes interrupts when multiples pins have been + * configured on a single PIO controller + * - It allows a group of pins to share the same interrupt + * + * However, it also has several minor drawbacks that may prevent from using it + * in particular applications: + * - It enables the clocks of all PIO controllers + * - PIO controllers all share the same interrupt handler, which does the + * demultiplexing and can be slower than direct configuration + * - It reserves space for a fixed number of interrupts, which can be + * increased by modifying the appropriate constant in pio_it.c. + * + * \par Usage + * + * -# Initialize the PIO interrupt mechanism using PIO_InitializeInterrupts() + * with the desired priority (0 ... 7). + * -# Configure a status change interrupt on one or more pin(s) with + * PIO_ConfigureIt(). + * -# Enable & disable interrupts on pins using PIO_EnableIt() and + * PIO_DisableIt(). + */ + +#ifndef _PIO_IT_ +#define _PIO_IT_ + +/* + * Headers + */ + +#include "pio.h" + +#ifdef __cplusplus + extern "C" { +#endif + +/* + * Global functions + */ + +extern void PIO_InitializeInterrupts( uint32_t dwPriority ) ; + +extern void PIO_ConfigureIt( const Pin *pPin, void (*handler)( const Pin* ) ) ; + +extern void PIO_EnableIt( const Pin *pPin ) ; + +extern void PIO_DisableIt( const Pin *pPin ) ; + +extern void PIO_IT_InterruptHandler( void ) ; + +extern void PioInterruptHandler( uint32_t id, Pio *pPio ) ; + +extern void PIO_CaptureHandler( void ) ; + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _PIO_IT_ */ + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/pmc.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/pmc.h new file mode 100644 index 00000000..6c5ba317 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/pmc.h @@ -0,0 +1,101 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _PMC_ +#define _PMC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include + + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ +/* Definition for fast RC frequency */ +#define FAST_RC_4MHZ CKGR_MOR_MOSCRCF_4MHz +#define FAST_RC_8MHZ CKGR_MOR_MOSCRCF_8MHz +#define FAST_RC_12MHZ CKGR_MOR_MOSCRCF_12MHz + +/* Definitions for startup count. + * Note: 1 count unit stand for: 1 / 32768 * 8 = 244 us + */ +/* Default startup count for 4/8/12MHz fast RC (startup time: 10us ) */ +#define DEFAUTL_FAST_RC_COUNT 1 +/* Default startup count for 3-20MHz main oscillator (startup time: 1.4ms ) */ +#define DEFAUTL_MAIN_OSC_COUNT 8 +/* Default startup count for PLLA (startup time: 200us ) */ +#define DEFAUTL_PLLA_COUNT 1 +/* Default startup count for UPLL */ +#define DEFAUTL_UPLL_COUNT 3 +/* No change for default startup count */ +#define DEFAUTL_COUNT_NO_CHANGE 0xFFFF + + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + extern "C" { +#endif + +extern void PMC_EnablePeripheral( uint32_t dwId ) ; +extern void PMC_DisablePeripheral( uint32_t dwId ) ; + +extern void PMC_EnableAllPeripherals( void ) ; +extern void PMC_DisableAllPeripherals( void ) ; + +extern uint32_t PMC_IsPeriphEnabled( uint32_t dwId ) ; + +extern void PMC_SelectExtOsc(void); +extern void PMC_EnableExtOsc(void); +extern void PMC_DisableExtOsc(void); +extern void PMC_SelectExtBypassOsc(void); +extern void PMC_EnableIntRC4_8_12MHz(uint32_t fastRcFreq); +extern void PMC_DisableIntRC4_8_12MHz(void); +extern void PMC_SetPllaClock(uint32_t mul, uint32_t div); +extern void PMC_SetPllbClock(uint32_t mul, uint32_t div); +extern void PMC_SetMckSelection(uint32_t clockSource, uint32_t prescaler); +extern void PMC_DisableAllClocks(void); +extern void PMC_ConfigureMckWithPlla(uint32_t mul, uint32_t div, + uint32_t prescaler); +extern void PMC_ConfigureMckWithPllb(uint32_t mul, uint32_t div, + uint32_t prescaler); +extern void PMC_EnableXT32KFME(void); +extern void PMC_ConfigurePCK0(uint32_t MasterClk, uint32_t prescaler); +extern void PMC_ConfigurePCK1(uint32_t MasterClk, uint32_t prescaler); +extern void PMC_ConfigurePCK2(uint32_t MasterClk, uint32_t prescaler); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _PMC_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/pwmc.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/pwmc.h new file mode 100644 index 00000000..f5bca771 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/pwmc.h @@ -0,0 +1,135 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \par Purpose + * + * Interface for configuration the Pulse Width Modulation Controller (PWM) + * peripheral. + * + * \par Usage + * + * -# Configures PWM clocks A & B to run at the given frequencies using + * \ref PWMC_ConfigureClocks(). + * -# Configure PWMC channel using \ref PWMC_ConfigureChannel(), + * \ref PWMC_ConfigureChannelExt() + * \ref PWMC_SetPeriod(), \ref PWMC_SetDutyCycle() and + * \ref PWMC_SetDeadTime(). + * -# Enable & disable channel using \ref PWMC_EnableChannel() and + * \ref PWMC_DisableChannel(). + * -# Enable & disable the period interrupt for the given PWM channel using + * \ref PWMC_EnableChannelIt() and \ref PWMC_DisableChannelIt(). + * -# Enable & disable the selected interrupts sources on a PWMC peripheral + * using \ref PWMC_EnableIt() and \ref PWMC_DisableIt(). + * -# Control synchronous channel using \ref PWMC_ConfigureSyncChannel(), + * \ref PWMC_SetSyncChannelUpdatePeriod() and + * \ref PWMC_SetSyncChannelUpdateUnlock(). + * -# Control PWM override output using \ref PWMC_SetOverrideValue(), + * \ref PWMC_EnableOverrideOutput() and \ref PWMC_DisableOverrideOutput(). + * -# Send data through the transmitter using \ref PWMC_WriteBuffer(). + * + */ + +#ifndef _PWMC_ +#define _PWMC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void PWMC_ConfigureChannel( + Pwm* pPwm, + uint8_t channel, + uint32_t prescaler, + uint32_t alignment, + uint32_t polarity); +extern void PWMC_ConfigureChannelExt( + Pwm* pPwm, + uint8_t channel, + uint32_t prescaler, + uint32_t alignment, + uint32_t polarity, + uint32_t countEventSelect, + uint32_t DTEnable, + uint32_t DTHInverte, + uint32_t DTLInverte); +extern void PWMC_ConfigureClocks(Pwm* pPwm, uint32_t clka, uint32_t clkb, + uint32_t mck); +extern void PWMC_SetPeriod( Pwm* pPwm, uint8_t channel, uint16_t period); +extern void PWMC_SetDutyCycle( Pwm* pPwm, uint8_t channel, uint16_t duty); +extern void PWMC_SetDeadTime( Pwm* pPwm, uint8_t channel, uint16_t timeH, + uint16_t timeL); +extern void PWMC_ConfigureSyncChannel( Pwm* pPwm, + uint32_t channels, + uint32_t updateMode, + uint32_t requestMode, + uint32_t requestComparisonSelect); +extern void PWMC_SetSyncChannelUpdatePeriod( Pwm* pPwm, uint8_t period); +extern void PWMC_SetSyncChannelUpdateUnlock( Pwm* pPwm ); +extern void PWMC_EnableChannel( Pwm* pPwm, uint8_t channel); +extern void PWMC_DisableChannel( Pwm* pPwm, uint8_t channel); +extern void PWMC_EnableChannelIt( Pwm* pPwm, uint8_t channel); +extern void PWMC_DisableChannelIt( Pwm* pPwm, uint8_t channel); +extern void PWMC_EnableIt( Pwm* pPwm, uint32_t sources1, uint32_t sources2); +extern void PWMC_DisableIt( Pwm* pPwm, uint32_t sources1, uint32_t sources2); +extern uint8_t PWMC_WriteBuffer(Pwm *pwmc, + void *buffer, + uint32_t length); +extern void PWMC_SetOverrideValue( Pwm* pPwm, uint32_t value); +extern void PWMC_EnableOverrideOutput( Pwm* pPwm, uint32_t value, uint32_t sync); +extern void PWMC_OutputOverrideSelection( Pwm* pPwm, uint32_t value ); +extern void PWMC_DisableOverrideOutput( Pwm* pPwm, uint32_t value, uint32_t sync); +extern void PWMC_SetFaultMode( Pwm* pPwm, uint32_t mode); +extern void PWMC_FaultClear( Pwm* pPwm, uint32_t fault); +extern void PWMC_SetFaultProtectionValue( Pwm* pPwm, uint32_t value); +extern void PWMC_EnableFaultProtection( Pwm* pPwm, uint32_t value); +extern void PWMC_ConfigureComparisonUnit( Pwm* pPwm, uint32_t x, + uint32_t value, uint32_t mode); +extern void PWMC_ConfigureEventLineMode( Pwm* pPwm, uint32_t x, uint32_t mode); +extern uint32_t PWMC_GetStatus2( Pwm* pPwm); +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _PWMC_ */ + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/qspi.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/qspi.h new file mode 100644 index 00000000..c1fb81b1 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/qspi.h @@ -0,0 +1,236 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + +/** + * \file + * + * Interface for Serial Peripheral Interface (SPI) controller. + * + */ + +#ifndef _QSPI_ +#define _QSPI_ +/*---------------------------------------------------------------------------- + * Macros + *----------------------------------------------------------------------------*/ + +/** + * + * Here are several macros which should be used when configuring a SPI + * peripheral. + * + * \section qspi_configuration_macros SPI Configuration Macros + * - \ref QSPI_PCS + * - \ref QSPI_SCBR + * - \ref QSPI_DLYBS + * - \ref QSPI_DLYBCT + */ + +/** Calculates the value of the CSR SCBR field given the baudrate and MCK. */ +#define QSPI_SCBR(baudrate, masterClock) \ + ((uint32_t) (masterClock / baudrate) << 8) + +/** Calculates the value of the CSR DLYBS field given the desired delay (in ns) */ +#define QSPI_DLYBS(delay, masterClock) \ + ((uint32_t) (((masterClock / 1000000) * delay) / 1000) << 16) + +/** Calculates the value of the CSR DLYBCT field given the desired delay (in ns) */ +#define QSPI_DLYBCT(delay, masterClock) \ + ((uint32_t) (((masterClock / 1000000) * delay) / 32000) << 24) + +/*--------------------------------------------------------------------------- */ + +#ifdef __cplusplus + extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** \brief qspi access modes + */ +typedef enum{ + CmdAccess = 0, + ReadAccess, + WriteAccess +}Access_t; + +/** \brief qspi modes SPI or QSPI + */ +typedef enum{ + SpiMode = QSPI_MR_SMM_SPI, + QspiMemMode = QSPI_MR_SMM_MEMORY +}QspiMode_t; + + +/** \brief qspi clock modes , regarding clock phase and clock polarity + */ +typedef enum{ + ClockMode_00 = 0, + ClockMode_10, + ClockMode_01, + ClockMode_11 +}QspiClockMode_t; + + +/** \brief qspi status codes + */ +typedef enum{ + QSPI_SUCCESS = 0, + QSPI_BUSY, + QSPI_BUSY_SENDING, + QSPI_READ_ERROR, + QSPI_WRITE_ERROR, + QSPI_UNKNOWN_ERROR, + QSPI_INIT_ERROR, + QSPI_INPUT_ERROR, + QSPI_TOTAL_ERROR +}QspidStatus_t; + + +/** \brief qspi status regiter bits + */ +typedef enum { + IsReceived = QSPI_SR_RDRF, + IsTxSent = QSPI_SR_TDRE, + IsTxEmpty = QSPI_SR_TXEMPTY, + IsOverrun = QSPI_SR_OVRES, + IsCsRise = QSPI_SR_CSR, + IsCsAsserted = QSPI_SR_CSS, + IsEofInst = QSPI_SR_INSTRE, + IsEnabled = QSPI_SR_QSPIENS +}QspiStatus_t; + +/** \brief qspi command structure + */ +typedef struct { + uint8_t Instruction; + uint8_t Option; +}QspiMemCmd_t; + +/** \brief qspi buffer structure + */ +typedef struct { + uint32_t TxDataSize; /* Tx buffer size */ + uint32_t RxDataSize; /* Rx buffer size */ + uint32_t *pDataTx; /* Tx buffer */ + uint32_t *pDataRx; /* Rx buffer */ +}QspiBuffer_t; + + +/** \brief qspi frame structure for QSPI mode + */ +typedef struct { + union _QspiInstFrame { + uint32_t val; + struct _QspiInstFrameBM { + uint32_t bwidth:3, /** Width of QSPI Addr , inst data */ + reserved0:1, /** Reserved*/ + bInstEn:1, /** Enable Inst */ + bAddrEn:1, /** Enable Address */ + bOptEn:1, /** Enable Option */ + bDataEn:1, /** Enable Data */ + bOptLen:2, /** Option Length*/ + bAddrLen:1, /** Addrs Length*/ + reserved1:1, /** Option Length*/ + bXfrType:2, /** Transfer type*/ + bContinuesRead:1, /** Continoues read mode*/ + reserved2:1, /** Reserved*/ + bDummyCycles:5, /**< Unicast hash match */ + reserved3:11; /** Reserved*/ + } bm; + } InstFrame; + uint32_t Addr; +}QspiInstFrame_t; + +/** \brief qspi driver structure + */ +typedef struct { + uint8_t qspiId; /* QSPI ID */ + Qspi *pQspiHw; /* QSPI Hw instance */ + QspiMode_t qspiMode; /* Qspi mode: SPI or QSPI */ + QspiMemCmd_t qspiCommand; /* Qspi command structure*/ + QspiBuffer_t qspiBuffer; /* Qspi buffer*/ + QspiInstFrame_t *pQspiFrame; /* Qspi QSPI mode Fram register informations*/ +}Qspid_t; + + +void QSPI_SwReset( Qspi *pQspi ); + +void QSPI_Disable( Qspi *pQspi ); + +void QSPI_Enable( Qspi *pQspi ); + +QspidStatus_t QSPI_EndTransfer( Qspi *pQspi ); + +uint32_t QSPI_GetStatus( Qspi *pQspi, const QspiStatus_t rStatus ); + +void QSPI_ConfigureClock( Qspi *pQspi, QspiClockMode_t ClockMode, + uint32_t dwClockCfg ); + +QspidStatus_t QSPI_SingleReadSPI( Qspid_t *pQspid, uint16_t* const pData ); + +QspidStatus_t QSPI_MultiReadSPI( Qspid_t *pQspid, uint16_t* + const pData, uint32_t NumOfBytes ); + +QspidStatus_t QSPI_SingleWriteSPI( Qspid_t *pQspid, uint16_t const *pData ); + +QspidStatus_t QSPI_MultiWriteSPI( Qspid_t *pQspid, uint16_t const *pData , + uint32_t NumOfBytes ); + +QspidStatus_t QSPI_EnableIt( Qspi *pQspi, uint32_t dwSources ); + +QspidStatus_t QSPI_DisableIt( Qspi *pQspi, uint32_t dwSources ); + +uint32_t QSPI_GetItMask( Qspi *pQspi ); + +uint32_t QSPI_GetEnabledItStatus( Qspi *pQspi ); + +QspidStatus_t QSPI_ConfigureInterface( Qspid_t *pQspid, QspiMode_t Mode, + uint32_t dwConfiguration ); + +QspidStatus_t QSPI_SendCommand( Qspid_t *pQspi, uint8_t const KeepCfg); + +QspidStatus_t QSPI_SendCommandWithData( Qspid_t *pQspi, uint8_t const KeepCfg); + +QspidStatus_t QSPI_ReadCommand( Qspid_t *pQspi, uint8_t const KeepCfg); + +QspidStatus_t QSPI_EnableMemAccess( Qspid_t *pQspi, uint8_t const KeepCfg, + uint8_t ScrambleFlag); + +QspidStatus_t QSPI_ReadWriteMem( Qspid_t *pQspid, Access_t const ReadWrite); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _QSPI_ */ + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/qspi_dma.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/qspi_dma.h new file mode 100644 index 00000000..686f738d --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/qspi_dma.h @@ -0,0 +1,115 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + +/** + * \file + * + * Implementation of SPI driver, transfer data through DMA. + * + */ + +#ifndef QSPI_DMA_H +#define QSPI_DMA_H + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" +#include "utils/utility.h" + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +/** An unspecified error has occurred.*/ +#define QSPID_ERROR 1 + +/** SPI driver is currently in use.*/ +#define QSPID_ERROR_LOCK 2 + +#define QSPID_CH_NOT_ENABLED 0xFF +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** SPI transfer complete callback. */ +typedef void (*QspidCallback)( uint8_t, void* ) ; + +/** Constant structure associated with SPI port. This structure prevents + client applications to have access in the same time. */ +typedef struct _Qspid +{ + Qspid_t Qspid; + /** Pointer to DMA driver */ + sXdmad* pXdmad; + /** Polling */ + uint8_t Polling ; + /** Tx ch num */ + uint8_t TxChNum ; + /** Rx ch num */ + uint8_t RxChNum ; + /** QSPI Xfr state. */ + volatile uint8_t progress ; +} QspiDma_t ; + +#ifdef __cplusplus + extern "C" { +#endif +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +uint32_t QSPID_Configure( QspiDma_t *pQspidma, QspiMode_t Mode, + uint32_t dwConfiguration, sXdmad* pXdmad); + +uint32_t QSPID_EnableQspiRxChannel(QspiDma_t *pQspidma); + +uint32_t QSPID_EnableQspiTxChannel(QspiDma_t *pQspidma); + +uint32_t QSPID_DisableQspiRxChannel(QspiDma_t *pQspidma); + +uint32_t QSPID_DisableQspiTxChannel(QspiDma_t *pQspidma); + +uint32_t QSPID_DisableSpiChannel(QspiDma_t *pQspidma); + +uint32_t QSPID_EnableSpiChannel(QspiDma_t *pQspidma); + +uint32_t QSPID_ReadWriteQSPI( QspiDma_t *pQspidma, Access_t const ReadWrite); + +uint32_t QSPID_ReadWriteSPI(QspiDma_t *pQspidma, Access_t const ReadWrite); + +uint32_t QSPID_IsBusy( volatile uint8_t *QspiSemaphore) ; + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _SPI_DMA_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/rstc.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/rstc.h new file mode 100644 index 00000000..97efdfa0 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/rstc.h @@ -0,0 +1,64 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _RSTC_H +#define _RSTC_H + +/*--------------------------------------------------------------------------- + * Includes + *---------------------------------------------------------------------------*/ + +#include + +/*--------------------------------------------------------------------------- + * Exported functions + *---------------------------------------------------------------------------*/ + +void RSTC_ConfigureMode(uint32_t rmr); + +void RSTC_SetUserResetEnable(uint8_t enable); + +void RSTC_SetUserResetInterruptEnable(uint8_t enable); + +void RSTC_SetExtResetLength(uint8_t powl); + +void RSTC_ProcessorReset(void); + +void RSTC_ExtReset(void); + +uint8_t RSTC_GetNrstLevel(void); + +uint8_t RSTC_IsUserResetDetected(void); + +uint8_t RSTC_IsBusy(void); + +uint32_t RSTC_GetStatus(void); + +#endif /* #ifndef _RSTC_H */ + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/rtc.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/rtc.h new file mode 100644 index 00000000..7ae27b48 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/rtc.h @@ -0,0 +1,102 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface for Real Time Clock (RTC) controller. + * + */ + +#ifndef _RTC_ +#define _RTC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +#include + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +#define RTC_HOUR_BIT_LEN_MASK 0x3F +#define RTC_MIN_BIT_LEN_MASK 0x7F +#define RTC_SEC_BIT_LEN_MASK 0x7F +#define RTC_CENT_BIT_LEN_MASK 0x7F +#define RTC_YEAR_BIT_LEN_MASK 0xFF +#define RTC_MONTH_BIT_LEN_MASK 0x1F +#define RTC_DATE_BIT_LEN_MASK 0x3F +#define RTC_WEEK_BIT_LEN_MASK 0x07 + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + extern "C" { +#endif + +extern void RTC_SetHourMode( Rtc* pRtc, uint32_t dwMode ) ; + +extern uint32_t RTC_GetHourMode( Rtc* pRtc ) ; + +extern void RTC_EnableIt( Rtc* pRtc, uint32_t dwSources ) ; + +extern void RTC_DisableIt( Rtc* pRtc, uint32_t dwSources ) ; + +extern int RTC_SetTime( Rtc* pRtc, uint8_t ucHour, uint8_t ucMinute, + uint8_t ucSecond ) ; + +extern void RTC_GetTime( Rtc* pRtc, uint8_t *pucHour, uint8_t *pucMinute, + uint8_t *pucSecond ) ; + +extern int RTC_SetTimeAlarm( Rtc* pRtc, uint8_t *pucHour, uint8_t *pucMinute, + uint8_t *pucSecond ) ; + +extern void RTC_GetDate( Rtc* pRtc, uint16_t *pwYear, uint8_t *pucMonth, + uint8_t *pucDay, uint8_t *pucWeek ) ; + +extern int RTC_SetDate( Rtc* pRtc, uint16_t wYear, uint8_t ucMonth, + uint8_t ucDay, uint8_t ucWeek ) ; + +extern int RTC_SetDateAlarm( Rtc* pRtc, uint8_t *pucMonth, uint8_t *pucDay ) ; + +extern void RTC_ClearSCCR( Rtc* pRtc, uint32_t dwMask ) ; + +extern uint32_t RTC_GetSR( Rtc* pRtc, uint32_t dwMask ) ; + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _RTC_ */ + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/rtt.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/rtt.h new file mode 100644 index 00000000..ac2483cb --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/rtt.h @@ -0,0 +1,82 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \par Purpose + * + * Interface for Real Time Timer (RTT) controller. + * + * \par Usage + * + * -# Changes the prescaler value of the given RTT and restarts it + * using \ref RTT_SetPrescaler(). + * -# Get current value of the RTT using \ref RTT_GetTime(). + * -# Enables the specified RTT interrupt using \ref RTT_EnableIT(). + * -# Get the status register value of the given RTT using \ref RTT_GetStatus(). + * -# Configures the RTT to generate an alarm at the given time + * using \ref RTT_SetAlarm(). + */ + +#ifndef _RTT_ +#define _RTT_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + extern "C" { +#endif + +extern void RTT_SetPrescaler( Rtt* pRtt, uint16_t wPrescaler ) ; + +extern uint32_t RTT_GetTime( Rtt* pRtt ) ; + +extern void RTT_EnableIT( Rtt* pRtt, uint32_t dwSources ) ; + +extern uint32_t RTT_GetStatus( Rtt *pRtt ) ; + +extern void RTT_SetAlarm( Rtt *pRtt, uint32_t dwTime ) ; + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef RTT_H */ + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_acc.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_acc.h new file mode 100644 index 00000000..9dd634d1 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_acc.h @@ -0,0 +1,128 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_ACC_COMPONENT_ +#define _SAMV71_ACC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Analog Comparator Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_ACC Analog Comparator Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Acc hardware registers */ +typedef struct { + __O uint32_t ACC_CR; /**< \brief (Acc Offset: 0x00) Control Register */ + __IO uint32_t ACC_MR; /**< \brief (Acc Offset: 0x04) Mode Register */ + __I uint32_t Reserved1[7]; + __O uint32_t ACC_IER; /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */ + __O uint32_t ACC_IDR; /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */ + __I uint32_t ACC_IMR; /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t ACC_ISR; /**< \brief (Acc Offset: 0x30) Interrupt Status Register */ + __I uint32_t Reserved2[24]; + __IO uint32_t ACC_ACR; /**< \brief (Acc Offset: 0x94) Analog Control Register */ + __I uint32_t Reserved3[19]; + __IO uint32_t ACC_WPMR; /**< \brief (Acc Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t ACC_WPSR; /**< \brief (Acc Offset: 0xE8) Write Protection Status Register */ +} Acc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */ +#define ACC_CR_SWRST (0x1u << 0) /**< \brief (ACC_CR) Software Reset */ +/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */ +#define ACC_MR_SELMINUS_Pos 0 +#define ACC_MR_SELMINUS_Msk (0x7u << ACC_MR_SELMINUS_Pos) /**< \brief (ACC_MR) Selection for Minus Comparator Input */ +#define ACC_MR_SELMINUS(value) ((ACC_MR_SELMINUS_Msk & ((value) << ACC_MR_SELMINUS_Pos))) +#define ACC_MR_SELMINUS_TS (0x0u << 0) /**< \brief (ACC_MR) Select TS */ +#define ACC_MR_SELMINUS_ADVREFP (0x1u << 0) /**< \brief (ACC_MR) Select ADVREFP */ +#define ACC_MR_SELMINUS_DAC0 (0x2u << 0) /**< \brief (ACC_MR) Select DAC0 */ +#define ACC_MR_SELMINUS_DAC1 (0x3u << 0) /**< \brief (ACC_MR) Select DAC1 */ +#define ACC_MR_SELMINUS_AFE0_AD0 (0x4u << 0) /**< \brief (ACC_MR) Select AFE0_AD0 */ +#define ACC_MR_SELMINUS_AFE0_AD1 (0x5u << 0) /**< \brief (ACC_MR) Select AFE0_AD1 */ +#define ACC_MR_SELMINUS_AFE0_AD2 (0x6u << 0) /**< \brief (ACC_MR) Select AFE0_AD2 */ +#define ACC_MR_SELMINUS_AFE0_AD3 (0x7u << 0) /**< \brief (ACC_MR) Select AFE0_AD3 */ +#define ACC_MR_SELPLUS_Pos 4 +#define ACC_MR_SELPLUS_Msk (0x7u << ACC_MR_SELPLUS_Pos) /**< \brief (ACC_MR) Selection For Plus Comparator Input */ +#define ACC_MR_SELPLUS(value) ((ACC_MR_SELPLUS_Msk & ((value) << ACC_MR_SELPLUS_Pos))) +#define ACC_MR_SELPLUS_AFE0_AD0 (0x0u << 4) /**< \brief (ACC_MR) Select AFE0_AD0 */ +#define ACC_MR_SELPLUS_AFE0_AD1 (0x1u << 4) /**< \brief (ACC_MR) Select AFE0_AD1 */ +#define ACC_MR_SELPLUS_AFE0_AD2 (0x2u << 4) /**< \brief (ACC_MR) Select AFE0_AD2 */ +#define ACC_MR_SELPLUS_AFE0_AD3 (0x3u << 4) /**< \brief (ACC_MR) Select AFE0_AD3 */ +#define ACC_MR_SELPLUS_AFE0_AD4 (0x4u << 4) /**< \brief (ACC_MR) Select AFE0_AD4 */ +#define ACC_MR_SELPLUS_AFE0_AD5 (0x5u << 4) /**< \brief (ACC_MR) Select AFE0_AD5 */ +#define ACC_MR_SELPLUS_AFE1_AD0 (0x6u << 4) /**< \brief (ACC_MR) Select AFE1_AD0 */ +#define ACC_MR_SELPLUS_AFE1_AD1 (0x7u << 4) /**< \brief (ACC_MR) Select AFE1_AD1 */ +#define ACC_MR_ACEN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator Enable */ +#define ACC_MR_ACEN_DIS (0x0u << 8) /**< \brief (ACC_MR) Analog comparator disabled. */ +#define ACC_MR_ACEN_EN (0x1u << 8) /**< \brief (ACC_MR) Analog comparator enabled. */ +#define ACC_MR_EDGETYP_Pos 9 +#define ACC_MR_EDGETYP_Msk (0x3u << ACC_MR_EDGETYP_Pos) /**< \brief (ACC_MR) Edge Type */ +#define ACC_MR_EDGETYP(value) ((ACC_MR_EDGETYP_Msk & ((value) << ACC_MR_EDGETYP_Pos))) +#define ACC_MR_EDGETYP_RISING (0x0u << 9) /**< \brief (ACC_MR) Only rising edge of comparator output */ +#define ACC_MR_EDGETYP_FALLING (0x1u << 9) /**< \brief (ACC_MR) Falling edge of comparator output */ +#define ACC_MR_EDGETYP_ANY (0x2u << 9) /**< \brief (ACC_MR) Any edge of comparator output */ +#define ACC_MR_INV (0x1u << 12) /**< \brief (ACC_MR) Invert Comparator Output */ +#define ACC_MR_INV_DIS (0x0u << 12) /**< \brief (ACC_MR) Analog comparator output is directly processed. */ +#define ACC_MR_INV_EN (0x1u << 12) /**< \brief (ACC_MR) Analog comparator output is inverted prior to being processed. */ +#define ACC_MR_SELFS (0x1u << 13) /**< \brief (ACC_MR) Selection Of Fault Source */ +#define ACC_MR_SELFS_CE (0x0u << 13) /**< \brief (ACC_MR) The CE flag is used to drive the FAULT output. */ +#define ACC_MR_SELFS_OUTPUT (0x1u << 13) /**< \brief (ACC_MR) The output of the analog comparator flag is used to drive the FAULT output. */ +#define ACC_MR_FE (0x1u << 14) /**< \brief (ACC_MR) Fault Enable */ +#define ACC_MR_FE_DIS (0x0u << 14) /**< \brief (ACC_MR) The FAULT output is tied to 0. */ +#define ACC_MR_FE_EN (0x1u << 14) /**< \brief (ACC_MR) The FAULT output is driven by the signal defined by SELFS. */ +/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */ +#define ACC_IER_CE (0x1u << 0) /**< \brief (ACC_IER) Comparison Edge */ +/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */ +#define ACC_IDR_CE (0x1u << 0) /**< \brief (ACC_IDR) Comparison Edge */ +/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */ +#define ACC_IMR_CE (0x1u << 0) /**< \brief (ACC_IMR) Comparison Edge */ +/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */ +#define ACC_ISR_CE (0x1u << 0) /**< \brief (ACC_ISR) Comparison Edge (cleared on read) */ +#define ACC_ISR_SCO (0x1u << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */ +#define ACC_ISR_MASK (0x1u << 31) /**< \brief (ACC_ISR) Flag Mask */ +/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */ +#define ACC_ACR_ISEL (0x1u << 0) /**< \brief (ACC_ACR) Current Selection */ +#define ACC_ACR_ISEL_LOPW (0x0u << 0) /**< \brief (ACC_ACR) Low-power option. */ +#define ACC_ACR_ISEL_HISP (0x1u << 0) /**< \brief (ACC_ACR) High-speed option. */ +#define ACC_ACR_HYST_Pos 1 +#define ACC_ACR_HYST_Msk (0x3u << ACC_ACR_HYST_Pos) /**< \brief (ACC_ACR) Hysteresis Selection */ +#define ACC_ACR_HYST(value) ((ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos))) +/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protection Mode Register -------- */ +#define ACC_WPMR_WPEN (0x1u << 0) /**< \brief (ACC_WPMR) Write Protection Enable */ +#define ACC_WPMR_WPKEY_Pos 8 +#define ACC_WPMR_WPKEY_Msk (0xffffffu << ACC_WPMR_WPKEY_Pos) /**< \brief (ACC_WPMR) Write Protection Key */ +#define ACC_WPMR_WPKEY(value) ((ACC_WPMR_WPKEY_Msk & ((value) << ACC_WPMR_WPKEY_Pos))) +#define ACC_WPMR_WPKEY_PASSWD (0x414343u << 8) /**< \brief (ACC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protection Status Register -------- */ +#define ACC_WPSR_WPVS (0x1u << 0) /**< \brief (ACC_WPSR) Write Protection Violation Status */ + +/*@}*/ + + +#endif /* _SAMV71_ACC_COMPONENT_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_aes.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_aes.h new file mode 100644 index 00000000..197590d8 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_aes.h @@ -0,0 +1,172 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_AES_COMPONENT_ +#define _SAMV71_AES_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Advanced Encryption Standard */ +/* ============================================================================= */ +/** \addtogroup SAMV71_AES Advanced Encryption Standard */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Aes hardware registers */ +typedef struct { + __O uint32_t AES_CR; /**< \brief (Aes Offset: 0x00) Control Register */ + __IO uint32_t AES_MR; /**< \brief (Aes Offset: 0x04) Mode Register */ + __I uint32_t Reserved1[2]; + __O uint32_t AES_IER; /**< \brief (Aes Offset: 0x10) Interrupt Enable Register */ + __O uint32_t AES_IDR; /**< \brief (Aes Offset: 0x14) Interrupt Disable Register */ + __I uint32_t AES_IMR; /**< \brief (Aes Offset: 0x18) Interrupt Mask Register */ + __I uint32_t AES_ISR; /**< \brief (Aes Offset: 0x1C) Interrupt Status Register */ + __O uint32_t AES_KEYWR[8]; /**< \brief (Aes Offset: 0x20) Key Word Register */ + __O uint32_t AES_IDATAR[4]; /**< \brief (Aes Offset: 0x40) Input Data Register */ + __I uint32_t AES_ODATAR[4]; /**< \brief (Aes Offset: 0x50) Output Data Register */ + __O uint32_t AES_IVR[4]; /**< \brief (Aes Offset: 0x60) Initialization Vector Register */ + __IO uint32_t AES_AADLENR; /**< \brief (Aes Offset: 0x70) Additional Authenticated Data Length Register */ + __IO uint32_t AES_CLENR; /**< \brief (Aes Offset: 0x74) Plaintext/Ciphertext Length Register */ + __IO uint32_t AES_GHASHR[4]; /**< \brief (Aes Offset: 0x78) GCM Intermediate Hash Word Register */ + __I uint32_t AES_TAGR[4]; /**< \brief (Aes Offset: 0x88) GCM Authentication Tag Word Register */ + __I uint32_t AES_CTRR; /**< \brief (Aes Offset: 0x98) GCM Encryption Counter Value Register */ + __IO uint32_t AES_GCMHR[4]; /**< \brief (Aes Offset: 0x9C) GCM H Word Register */ +} Aes; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- AES_CR : (AES Offset: 0x00) Control Register -------- */ +#define AES_CR_START (0x1u << 0) /**< \brief (AES_CR) Start Processing */ +#define AES_CR_SWRST (0x1u << 8) /**< \brief (AES_CR) Software Reset */ +/* -------- AES_MR : (AES Offset: 0x04) Mode Register -------- */ +#define AES_MR_CIPHER (0x1u << 0) /**< \brief (AES_MR) Processing Mode */ +#define AES_MR_GTAGEN (0x1u << 1) /**< \brief (AES_MR) GCM Automatic Tag Generation Enable */ +#define AES_MR_DUALBUFF (0x1u << 3) /**< \brief (AES_MR) Dual Input Buffer */ +#define AES_MR_DUALBUFF_INACTIVE (0x0u << 3) /**< \brief (AES_MR) AES_IDATARx cannot be written during processing of previous block. */ +#define AES_MR_DUALBUFF_ACTIVE (0x1u << 3) /**< \brief (AES_MR) AES_IDATARx can be written during processing of previous block when SMOD = 0x2. It speeds up the overall runtime of large files. */ +#define AES_MR_PROCDLY_Pos 4 +#define AES_MR_PROCDLY_Msk (0xfu << AES_MR_PROCDLY_Pos) /**< \brief (AES_MR) Processing Delay */ +#define AES_MR_PROCDLY(value) ((AES_MR_PROCDLY_Msk & ((value) << AES_MR_PROCDLY_Pos))) +#define AES_MR_SMOD_Pos 8 +#define AES_MR_SMOD_Msk (0x3u << AES_MR_SMOD_Pos) /**< \brief (AES_MR) Start Mode */ +#define AES_MR_SMOD(value) ((AES_MR_SMOD_Msk & ((value) << AES_MR_SMOD_Pos))) +#define AES_MR_SMOD_MANUAL_START (0x0u << 8) /**< \brief (AES_MR) Manual Mode */ +#define AES_MR_SMOD_AUTO_START (0x1u << 8) /**< \brief (AES_MR) Auto Mode */ +#define AES_MR_SMOD_IDATAR0_START (0x2u << 8) /**< \brief (AES_MR) AES_IDATAR0 access only Auto Mode (DMA) */ +#define AES_MR_KEYSIZE_Pos 10 +#define AES_MR_KEYSIZE_Msk (0x3u << AES_MR_KEYSIZE_Pos) /**< \brief (AES_MR) Key Size */ +#define AES_MR_KEYSIZE(value) ((AES_MR_KEYSIZE_Msk & ((value) << AES_MR_KEYSIZE_Pos))) +#define AES_MR_KEYSIZE_AES128 (0x0u << 10) /**< \brief (AES_MR) AES Key Size is 128 bits */ +#define AES_MR_KEYSIZE_AES192 (0x1u << 10) /**< \brief (AES_MR) AES Key Size is 192 bits */ +#define AES_MR_KEYSIZE_AES256 (0x2u << 10) /**< \brief (AES_MR) AES Key Size is 256 bits */ +#define AES_MR_OPMOD_Pos 12 +#define AES_MR_OPMOD_Msk (0x7u << AES_MR_OPMOD_Pos) /**< \brief (AES_MR) Operation Mode */ +#define AES_MR_OPMOD(value) ((AES_MR_OPMOD_Msk & ((value) << AES_MR_OPMOD_Pos))) +#define AES_MR_OPMOD_ECB (0x0u << 12) /**< \brief (AES_MR) ECB: Electronic Code Book mode */ +#define AES_MR_OPMOD_CBC (0x1u << 12) /**< \brief (AES_MR) CBC: Cipher Block Chaining mode */ +#define AES_MR_OPMOD_OFB (0x2u << 12) /**< \brief (AES_MR) OFB: Output Feedback mode */ +#define AES_MR_OPMOD_CFB (0x3u << 12) /**< \brief (AES_MR) CFB: Cipher Feedback mode */ +#define AES_MR_OPMOD_CTR (0x4u << 12) /**< \brief (AES_MR) CTR: Counter mode (16-bit internal counter) */ +#define AES_MR_OPMOD_GCM (0x5u << 12) /**< \brief (AES_MR) GCM: Galois/Counter mode */ +#define AES_MR_LOD (0x1u << 15) /**< \brief (AES_MR) Last Output Data Mode */ +#define AES_MR_CFBS_Pos 16 +#define AES_MR_CFBS_Msk (0x7u << AES_MR_CFBS_Pos) /**< \brief (AES_MR) Cipher Feedback Data Size */ +#define AES_MR_CFBS(value) ((AES_MR_CFBS_Msk & ((value) << AES_MR_CFBS_Pos))) +#define AES_MR_CFBS_SIZE_128BIT (0x0u << 16) /**< \brief (AES_MR) 128-bit */ +#define AES_MR_CFBS_SIZE_64BIT (0x1u << 16) /**< \brief (AES_MR) 64-bit */ +#define AES_MR_CFBS_SIZE_32BIT (0x2u << 16) /**< \brief (AES_MR) 32-bit */ +#define AES_MR_CFBS_SIZE_16BIT (0x3u << 16) /**< \brief (AES_MR) 16-bit */ +#define AES_MR_CFBS_SIZE_8BIT (0x4u << 16) /**< \brief (AES_MR) 8-bit */ +#define AES_MR_CKEY_Pos 20 +#define AES_MR_CKEY_Msk (0xfu << AES_MR_CKEY_Pos) /**< \brief (AES_MR) Key */ +#define AES_MR_CKEY(value) ((AES_MR_CKEY_Msk & ((value) << AES_MR_CKEY_Pos))) +#define AES_MR_CKEY_PASSWD (0xEu << 20) /**< \brief (AES_MR) This field must be written with 0xE the first time that AES_MR is programmed. For subsequent programming of the AES_MR, any value can be written, including that of 0xE.Always reads as 0. */ +/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */ +#define AES_IER_DATRDY (0x1u << 0) /**< \brief (AES_IER) Data Ready Interrupt Enable */ +#define AES_IER_URAD (0x1u << 8) /**< \brief (AES_IER) Unspecified Register Access Detection Interrupt Enable */ +#define AES_IER_TAGRDY (0x1u << 16) /**< \brief (AES_IER) GCM Tag Ready Interrupt Enable */ +/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */ +#define AES_IDR_DATRDY (0x1u << 0) /**< \brief (AES_IDR) Data Ready Interrupt Disable */ +#define AES_IDR_URAD (0x1u << 8) /**< \brief (AES_IDR) Unspecified Register Access Detection Interrupt Disable */ +#define AES_IDR_TAGRDY (0x1u << 16) /**< \brief (AES_IDR) GCM Tag Ready Interrupt Disable */ +/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */ +#define AES_IMR_DATRDY (0x1u << 0) /**< \brief (AES_IMR) Data Ready Interrupt Mask */ +#define AES_IMR_URAD (0x1u << 8) /**< \brief (AES_IMR) Unspecified Register Access Detection Interrupt Mask */ +#define AES_IMR_TAGRDY (0x1u << 16) /**< \brief (AES_IMR) GCM Tag Ready Interrupt Mask */ +/* -------- AES_ISR : (AES Offset: 0x1C) Interrupt Status Register -------- */ +#define AES_ISR_DATRDY (0x1u << 0) /**< \brief (AES_ISR) Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) */ +#define AES_ISR_URAD (0x1u << 8) /**< \brief (AES_ISR) Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) */ +#define AES_ISR_URAT_Pos 12 +#define AES_ISR_URAT_Msk (0xfu << AES_ISR_URAT_Pos) /**< \brief (AES_ISR) Unspecified Register Access (cleared by writing SWRST in AES_CR) */ +#define AES_ISR_URAT_IDR_WR_PROCESSING (0x0u << 12) /**< \brief (AES_ISR) Input Data Register written during the data processing when SMOD = 0x2 mode. */ +#define AES_ISR_URAT_ODR_RD_PROCESSING (0x1u << 12) /**< \brief (AES_ISR) Output Data Register read during the data processing. */ +#define AES_ISR_URAT_MR_WR_PROCESSING (0x2u << 12) /**< \brief (AES_ISR) Mode Register written during the data processing. */ +#define AES_ISR_URAT_ODR_RD_SUBKGEN (0x3u << 12) /**< \brief (AES_ISR) Output Data Register read during the sub-keys generation. */ +#define AES_ISR_URAT_MR_WR_SUBKGEN (0x4u << 12) /**< \brief (AES_ISR) Mode Register written during the sub-keys generation. */ +#define AES_ISR_URAT_WOR_RD_ACCESS (0x5u << 12) /**< \brief (AES_ISR) Write-only register read access. */ +#define AES_ISR_TAGRDY (0x1u << 16) /**< \brief (AES_ISR) GCM Tag Ready */ +/* -------- AES_KEYWR[8] : (AES Offset: 0x20) Key Word Register -------- */ +#define AES_KEYWR_KEYW_Pos 0 +#define AES_KEYWR_KEYW_Msk (0xffffffffu << AES_KEYWR_KEYW_Pos) /**< \brief (AES_KEYWR[8]) Key Word */ +#define AES_KEYWR_KEYW(value) ((AES_KEYWR_KEYW_Msk & ((value) << AES_KEYWR_KEYW_Pos))) +/* -------- AES_IDATAR[4] : (AES Offset: 0x40) Input Data Register -------- */ +#define AES_IDATAR_IDATA_Pos 0 +#define AES_IDATAR_IDATA_Msk (0xffffffffu << AES_IDATAR_IDATA_Pos) /**< \brief (AES_IDATAR[4]) Input Data Word */ +#define AES_IDATAR_IDATA(value) ((AES_IDATAR_IDATA_Msk & ((value) << AES_IDATAR_IDATA_Pos))) +/* -------- AES_ODATAR[4] : (AES Offset: 0x50) Output Data Register -------- */ +#define AES_ODATAR_ODATA_Pos 0 +#define AES_ODATAR_ODATA_Msk (0xffffffffu << AES_ODATAR_ODATA_Pos) /**< \brief (AES_ODATAR[4]) Output Data */ +/* -------- AES_IVR[4] : (AES Offset: 0x60) Initialization Vector Register -------- */ +#define AES_IVR_IV_Pos 0 +#define AES_IVR_IV_Msk (0xffffffffu << AES_IVR_IV_Pos) /**< \brief (AES_IVR[4]) Initialization Vector */ +#define AES_IVR_IV(value) ((AES_IVR_IV_Msk & ((value) << AES_IVR_IV_Pos))) +/* -------- AES_AADLENR : (AES Offset: 0x70) Additional Authenticated Data Length Register -------- */ +#define AES_AADLENR_AADLEN_Pos 0 +#define AES_AADLENR_AADLEN_Msk (0xffffffffu << AES_AADLENR_AADLEN_Pos) /**< \brief (AES_AADLENR) Additional Authenticated Data Length */ +#define AES_AADLENR_AADLEN(value) ((AES_AADLENR_AADLEN_Msk & ((value) << AES_AADLENR_AADLEN_Pos))) +/* -------- AES_CLENR : (AES Offset: 0x74) Plaintext/Ciphertext Length Register -------- */ +#define AES_CLENR_CLEN_Pos 0 +#define AES_CLENR_CLEN_Msk (0xffffffffu << AES_CLENR_CLEN_Pos) /**< \brief (AES_CLENR) Plaintext/Ciphertext Length */ +#define AES_CLENR_CLEN(value) ((AES_CLENR_CLEN_Msk & ((value) << AES_CLENR_CLEN_Pos))) +/* -------- AES_GHASHR[4] : (AES Offset: 0x78) GCM Intermediate Hash Word Register -------- */ +#define AES_GHASHR_GHASH_Pos 0 +#define AES_GHASHR_GHASH_Msk (0xffffffffu << AES_GHASHR_GHASH_Pos) /**< \brief (AES_GHASHR[4]) Intermediate GCM Hash Word x */ +#define AES_GHASHR_GHASH(value) ((AES_GHASHR_GHASH_Msk & ((value) << AES_GHASHR_GHASH_Pos))) +/* -------- AES_TAGR[4] : (AES Offset: 0x88) GCM Authentication Tag Word Register -------- */ +#define AES_TAGR_TAG_Pos 0 +#define AES_TAGR_TAG_Msk (0xffffffffu << AES_TAGR_TAG_Pos) /**< \brief (AES_TAGR[4]) GCM Authentication Tag x */ +/* -------- AES_CTRR : (AES Offset: 0x98) GCM Encryption Counter Value Register -------- */ +#define AES_CTRR_CTR_Pos 0 +#define AES_CTRR_CTR_Msk (0xffffffffu << AES_CTRR_CTR_Pos) /**< \brief (AES_CTRR) GCM Encryption Counter */ +/* -------- AES_GCMHR[4] : (AES Offset: 0x9C) GCM H Word Register -------- */ +#define AES_GCMHR_H_Pos 0 +#define AES_GCMHR_H_Msk (0xffffffffu << AES_GCMHR_H_Pos) /**< \brief (AES_GCMHR[4]) GCM H Word x */ +#define AES_GCMHR_H(value) ((AES_GCMHR_H_Msk & ((value) << AES_GCMHR_H_Pos))) + +/*@}*/ + + +#endif /* _SAMV71_AES_COMPONENT_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_afec.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_afec.h new file mode 100644 index 00000000..72b8a3c3 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_afec.h @@ -0,0 +1,483 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_AFEC_COMPONENT_ +#define _SAMV71_AFEC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Analog Front-End Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_AFEC Analog Front-End Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Afec hardware registers */ +typedef struct { + __O uint32_t AFEC_CR; /**< \brief (Afec Offset: 0x00) AFEC Control Register */ + __IO uint32_t AFEC_MR; /**< \brief (Afec Offset: 0x04) AFEC Mode Register */ + __IO uint32_t AFEC_EMR; /**< \brief (Afec Offset: 0x08) AFEC Extended Mode Register */ + __IO uint32_t AFEC_SEQ1R; /**< \brief (Afec Offset: 0x0C) AFEC Channel Sequence 1 Register */ + __IO uint32_t AFEC_SEQ2R; /**< \brief (Afec Offset: 0x10) AFEC Channel Sequence 2 Register */ + __O uint32_t AFEC_CHER; /**< \brief (Afec Offset: 0x14) AFEC Channel Enable Register */ + __O uint32_t AFEC_CHDR; /**< \brief (Afec Offset: 0x18) AFEC Channel Disable Register */ + __I uint32_t AFEC_CHSR; /**< \brief (Afec Offset: 0x1C) AFEC Channel Status Register */ + __I uint32_t AFEC_LCDR; /**< \brief (Afec Offset: 0x20) AFEC Last Converted Data Register */ + __O uint32_t AFEC_IER; /**< \brief (Afec Offset: 0x24) AFEC Interrupt Enable Register */ + __O uint32_t AFEC_IDR; /**< \brief (Afec Offset: 0x28) AFEC Interrupt Disable Register */ + __I uint32_t AFEC_IMR; /**< \brief (Afec Offset: 0x2C) AFEC Interrupt Mask Register */ + __I uint32_t AFEC_ISR; /**< \brief (Afec Offset: 0x30) AFEC Interrupt Status Register */ + __I uint32_t Reserved1[6]; + __I uint32_t AFEC_OVER; /**< \brief (Afec Offset: 0x4C) AFEC Overrun Status Register */ + __IO uint32_t AFEC_CWR; /**< \brief (Afec Offset: 0x50) AFEC Compare Window Register */ + __IO uint32_t AFEC_CGR; /**< \brief (Afec Offset: 0x54) AFEC Channel Gain Register */ + __I uint32_t Reserved2[2]; + __IO uint32_t AFEC_DIFFR; /**< \brief (Afec Offset: 0x60) AFEC Channel Differential Register */ + __IO uint32_t AFEC_CSELR; /**< \brief (Afec Offset: 0x64) AFEC Channel Selection Register */ + __I uint32_t AFEC_CDR; /**< \brief (Afec Offset: 0x68) AFEC Channel Data Register */ + __IO uint32_t AFEC_COCR; /**< \brief (Afec Offset: 0x6C) AFEC Channel Offset Compensation Register */ + __IO uint32_t AFEC_TEMPMR; /**< \brief (Afec Offset: 0x70) AFEC Temperature Sensor Mode Register */ + __IO uint32_t AFEC_TEMPCWR; /**< \brief (Afec Offset: 0x74) AFEC Temperature Compare Window Register */ + __I uint32_t Reserved3[7]; + __IO uint32_t AFEC_ACR; /**< \brief (Afec Offset: 0x94) AFEC Analog Control Register */ + __I uint32_t Reserved4[2]; + __IO uint32_t AFEC_SHMR; /**< \brief (Afec Offset: 0xA0) AFEC Sample & Hold Mode Register */ + __I uint32_t Reserved5[11]; + __IO uint32_t AFEC_COSR; /**< \brief (Afec Offset: 0xD0) AFEC Correction Select Register */ + __IO uint32_t AFEC_CVR; /**< \brief (Afec Offset: 0xD4) AFEC Correction Values Register */ + __IO uint32_t AFEC_CECR; /**< \brief (Afec Offset: 0xD8) AFEC Channel Error Correction Register */ + __I uint32_t Reserved6[2]; + __IO uint32_t AFEC_WPMR; /**< \brief (Afec Offset: 0xE4) AFEC Write Protection Mode Register */ + __I uint32_t AFEC_WPSR; /**< \brief (Afec Offset: 0xE8) AFEC Write Protection Status Register */ +} Afec; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- AFEC_CR : (AFEC Offset: 0x00) AFEC Control Register -------- */ +#define AFEC_CR_SWRST (0x1u << 0) /**< \brief (AFEC_CR) Software Reset */ +#define AFEC_CR_START (0x1u << 1) /**< \brief (AFEC_CR) Start Conversion */ +/* -------- AFEC_MR : (AFEC Offset: 0x04) AFEC Mode Register -------- */ +#define AFEC_MR_TRGEN (0x1u << 0) /**< \brief (AFEC_MR) Trigger Enable */ +#define AFEC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (AFEC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */ +#define AFEC_MR_TRGEN_EN (0x1u << 0) /**< \brief (AFEC_MR) Hardware trigger selected by TRGSEL field is enabled. */ +#define AFEC_MR_TRGSEL_Pos 1 +#define AFEC_MR_TRGSEL_Msk (0x7u << AFEC_MR_TRGSEL_Pos) /**< \brief (AFEC_MR) Trigger Selection */ +#define AFEC_MR_TRGSEL(value) ((AFEC_MR_TRGSEL_Msk & ((value) << AFEC_MR_TRGSEL_Pos))) +#define AFEC_MR_TRGSEL_AFEC_TRIG0 (0x0u << 1) /**< \brief (AFEC_MR) AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG1 (0x1u << 1) /**< \brief (AFEC_MR) TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG2 (0x2u << 1) /**< \brief (AFEC_MR) TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG3 (0x3u << 1) /**< \brief (AFEC_MR) TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG4 (0x4u << 1) /**< \brief (AFEC_MR) PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG5 (0x5u << 1) /**< \brief (AFEC_MR) PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG6 (0x6u << 1) /**< \brief (AFEC_MR) Analog Comparator */ +#define AFEC_MR_SLEEP (0x1u << 5) /**< \brief (AFEC_MR) Sleep Mode */ +#define AFEC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (AFEC_MR) Normal mode: The AFE and reference voltage circuitry are kept ON between conversions. */ +#define AFEC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (AFEC_MR) Sleep mode: The AFE and reference voltage circuitry are OFF between conversions. */ +#define AFEC_MR_FWUP (0x1u << 6) /**< \brief (AFEC_MR) Fast Wake-up */ +#define AFEC_MR_FWUP_OFF (0x0u << 6) /**< \brief (AFEC_MR) Normal Sleep mode: The sleep mode is defined by the SLEEP bit. */ +#define AFEC_MR_FWUP_ON (0x1u << 6) /**< \brief (AFEC_MR) Fast wake-up Sleep mode: The voltage reference is ON between conversions and AFE is OFF. */ +#define AFEC_MR_FREERUN (0x1u << 7) /**< \brief (AFEC_MR) Free Run Mode */ +#define AFEC_MR_FREERUN_OFF (0x0u << 7) /**< \brief (AFEC_MR) Normal mode */ +#define AFEC_MR_FREERUN_ON (0x1u << 7) /**< \brief (AFEC_MR) Free Run mode: Never wait for any trigger. */ +#define AFEC_MR_PRESCAL_Pos 8 +#define AFEC_MR_PRESCAL_Msk (0xffu << AFEC_MR_PRESCAL_Pos) /**< \brief (AFEC_MR) Prescaler Rate Selection */ +#define AFEC_MR_PRESCAL(value) ((AFEC_MR_PRESCAL_Msk & ((value) << AFEC_MR_PRESCAL_Pos))) +#define AFEC_MR_STARTUP_Pos 16 +#define AFEC_MR_STARTUP_Msk (0xfu << AFEC_MR_STARTUP_Pos) /**< \brief (AFEC_MR) Start-up Time */ +#define AFEC_MR_STARTUP(value) ((AFEC_MR_STARTUP_Msk & ((value) << AFEC_MR_STARTUP_Pos))) +#define AFEC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (AFEC_MR) 0 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (AFEC_MR) 8 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (AFEC_MR) 16 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (AFEC_MR) 24 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (AFEC_MR) 64 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (AFEC_MR) 80 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (AFEC_MR) 96 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (AFEC_MR) 112 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (AFEC_MR) 512 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (AFEC_MR) 576 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (AFEC_MR) 640 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (AFEC_MR) 704 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (AFEC_MR) 768 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (AFEC_MR) 832 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (AFEC_MR) 896 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (AFEC_MR) 960 periods of AFE clock */ +#define AFEC_MR_ONE (0x1u << 23) /**< \brief (AFEC_MR) One */ +#define AFEC_MR_TRACKTIM_Pos 24 +#define AFEC_MR_TRACKTIM_Msk (0xfu << AFEC_MR_TRACKTIM_Pos) /**< \brief (AFEC_MR) Tracking Time */ +#define AFEC_MR_TRACKTIM(value) ((AFEC_MR_TRACKTIM_Msk & ((value) << AFEC_MR_TRACKTIM_Pos))) +#define AFEC_MR_TRANSFER_Pos 28 +#define AFEC_MR_TRANSFER_Msk (0x3u << AFEC_MR_TRANSFER_Pos) /**< \brief (AFEC_MR) Transfer Period */ +#define AFEC_MR_TRANSFER(value) ((AFEC_MR_TRANSFER_Msk & ((value) << AFEC_MR_TRANSFER_Pos))) +#define AFEC_MR_USEQ (0x1u << 31) /**< \brief (AFEC_MR) User Sequence Enable */ +#define AFEC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (AFEC_MR) Normal mode: The controller converts channels in a simple numeric order. */ +#define AFEC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (AFEC_MR) User Sequence mode: The sequence respects what is defined in AFEC_SEQ1R and AFEC_SEQ1R. */ +/* -------- AFEC_EMR : (AFEC Offset: 0x08) AFEC Extended Mode Register -------- */ +#define AFEC_EMR_CMPMODE_Pos 0 +#define AFEC_EMR_CMPMODE_Msk (0x3u << AFEC_EMR_CMPMODE_Pos) /**< \brief (AFEC_EMR) Comparison Mode */ +#define AFEC_EMR_CMPMODE(value) ((AFEC_EMR_CMPMODE_Msk & ((value) << AFEC_EMR_CMPMODE_Pos))) +#define AFEC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */ +#define AFEC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */ +#define AFEC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is in the comparison window. */ +#define AFEC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is out of the comparison window. */ +#define AFEC_EMR_CMPSEL_Pos 3 +#define AFEC_EMR_CMPSEL_Msk (0x1fu << AFEC_EMR_CMPSEL_Pos) /**< \brief (AFEC_EMR) Comparison Selected Channel */ +#define AFEC_EMR_CMPSEL(value) ((AFEC_EMR_CMPSEL_Msk & ((value) << AFEC_EMR_CMPSEL_Pos))) +#define AFEC_EMR_CMPALL (0x1u << 9) /**< \brief (AFEC_EMR) Compare All Channels */ +#define AFEC_EMR_CMPFILTER_Pos 12 +#define AFEC_EMR_CMPFILTER_Msk (0x3u << AFEC_EMR_CMPFILTER_Pos) /**< \brief (AFEC_EMR) Compare Event Filtering */ +#define AFEC_EMR_CMPFILTER(value) ((AFEC_EMR_CMPFILTER_Msk & ((value) << AFEC_EMR_CMPFILTER_Pos))) +#define AFEC_EMR_RES_Pos 16 +#define AFEC_EMR_RES_Msk (0x7u << AFEC_EMR_RES_Pos) /**< \brief (AFEC_EMR) Resolution */ +#define AFEC_EMR_RES(value) ((AFEC_EMR_RES_Msk & ((value) << AFEC_EMR_RES_Pos))) +#define AFEC_EMR_RES_NO_AVERAGE (0x0u << 16) /**< \brief (AFEC_EMR) 12-bit resolution, AFE sample rate is maximum (no averaging). */ +#define AFEC_EMR_RES_OSR4 (0x2u << 16) /**< \brief (AFEC_EMR) 13-bit resolution, AFE sample rate divided by 4 (averaging). */ +#define AFEC_EMR_RES_OSR16 (0x3u << 16) /**< \brief (AFEC_EMR) 14-bit resolution, AFE sample rate divided by 16 (averaging). */ +#define AFEC_EMR_RES_OSR64 (0x4u << 16) /**< \brief (AFEC_EMR) 15-bit resolution, AFE sample rate divided by 64 (averaging). */ +#define AFEC_EMR_RES_OSR256 (0x5u << 16) /**< \brief (AFEC_EMR) 16-bit resolution, AFE sample rate divided by 256 (averaging). */ +#define AFEC_EMR_TAG (0x1u << 24) /**< \brief (AFEC_EMR) TAG of the AFEC_LDCR */ +#define AFEC_EMR_STM (0x1u << 25) /**< \brief (AFEC_EMR) Single Trigger Mode */ +#define AFEC_EMR_SIGNMODE_Pos 28 +#define AFEC_EMR_SIGNMODE_Msk (0x3u << AFEC_EMR_SIGNMODE_Pos) /**< \brief (AFEC_EMR) Sign Mode */ +#define AFEC_EMR_SIGNMODE(value) ((AFEC_EMR_SIGNMODE_Msk & ((value) << AFEC_EMR_SIGNMODE_Pos))) +#define AFEC_EMR_SIGNMODE_SE_UNSG_DF_SIGN (0x0u << 28) /**< \brief (AFEC_EMR) Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions. */ +#define AFEC_EMR_SIGNMODE_SE_SIGN_DF_UNSG (0x1u << 28) /**< \brief (AFEC_EMR) Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions. */ +#define AFEC_EMR_SIGNMODE_ALL_UNSIGNED (0x2u << 28) /**< \brief (AFEC_EMR) All channels: Unsigned conversions. */ +#define AFEC_EMR_SIGNMODE_ALL_SIGNED (0x3u << 28) /**< \brief (AFEC_EMR) All channels: Signed conversions. */ +/* -------- AFEC_SEQ1R : (AFEC Offset: 0x0C) AFEC Channel Sequence 1 Register -------- */ +#define AFEC_SEQ1R_USCH0_Pos 0 +#define AFEC_SEQ1R_USCH0_Msk (0xfu << AFEC_SEQ1R_USCH0_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 0 */ +#define AFEC_SEQ1R_USCH0(value) ((AFEC_SEQ1R_USCH0_Msk & ((value) << AFEC_SEQ1R_USCH0_Pos))) +#define AFEC_SEQ1R_USCH1_Pos 4 +#define AFEC_SEQ1R_USCH1_Msk (0xfu << AFEC_SEQ1R_USCH1_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 1 */ +#define AFEC_SEQ1R_USCH1(value) ((AFEC_SEQ1R_USCH1_Msk & ((value) << AFEC_SEQ1R_USCH1_Pos))) +#define AFEC_SEQ1R_USCH2_Pos 8 +#define AFEC_SEQ1R_USCH2_Msk (0xfu << AFEC_SEQ1R_USCH2_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 2 */ +#define AFEC_SEQ1R_USCH2(value) ((AFEC_SEQ1R_USCH2_Msk & ((value) << AFEC_SEQ1R_USCH2_Pos))) +#define AFEC_SEQ1R_USCH3_Pos 12 +#define AFEC_SEQ1R_USCH3_Msk (0xfu << AFEC_SEQ1R_USCH3_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 3 */ +#define AFEC_SEQ1R_USCH3(value) ((AFEC_SEQ1R_USCH3_Msk & ((value) << AFEC_SEQ1R_USCH3_Pos))) +#define AFEC_SEQ1R_USCH4_Pos 16 +#define AFEC_SEQ1R_USCH4_Msk (0xfu << AFEC_SEQ1R_USCH4_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 4 */ +#define AFEC_SEQ1R_USCH4(value) ((AFEC_SEQ1R_USCH4_Msk & ((value) << AFEC_SEQ1R_USCH4_Pos))) +#define AFEC_SEQ1R_USCH5_Pos 20 +#define AFEC_SEQ1R_USCH5_Msk (0xfu << AFEC_SEQ1R_USCH5_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 5 */ +#define AFEC_SEQ1R_USCH5(value) ((AFEC_SEQ1R_USCH5_Msk & ((value) << AFEC_SEQ1R_USCH5_Pos))) +#define AFEC_SEQ1R_USCH6_Pos 24 +#define AFEC_SEQ1R_USCH6_Msk (0xfu << AFEC_SEQ1R_USCH6_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 6 */ +#define AFEC_SEQ1R_USCH6(value) ((AFEC_SEQ1R_USCH6_Msk & ((value) << AFEC_SEQ1R_USCH6_Pos))) +#define AFEC_SEQ1R_USCH7_Pos 28 +#define AFEC_SEQ1R_USCH7_Msk (0xfu << AFEC_SEQ1R_USCH7_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 7 */ +#define AFEC_SEQ1R_USCH7(value) ((AFEC_SEQ1R_USCH7_Msk & ((value) << AFEC_SEQ1R_USCH7_Pos))) +/* -------- AFEC_SEQ2R : (AFEC Offset: 0x10) AFEC Channel Sequence 2 Register -------- */ +#define AFEC_SEQ2R_USCH8_Pos 0 +#define AFEC_SEQ2R_USCH8_Msk (0xfu << AFEC_SEQ2R_USCH8_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 8 */ +#define AFEC_SEQ2R_USCH8(value) ((AFEC_SEQ2R_USCH8_Msk & ((value) << AFEC_SEQ2R_USCH8_Pos))) +#define AFEC_SEQ2R_USCH9_Pos 4 +#define AFEC_SEQ2R_USCH9_Msk (0xfu << AFEC_SEQ2R_USCH9_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 9 */ +#define AFEC_SEQ2R_USCH9(value) ((AFEC_SEQ2R_USCH9_Msk & ((value) << AFEC_SEQ2R_USCH9_Pos))) +#define AFEC_SEQ2R_USCH10_Pos 8 +#define AFEC_SEQ2R_USCH10_Msk (0xfu << AFEC_SEQ2R_USCH10_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 10 */ +#define AFEC_SEQ2R_USCH10(value) ((AFEC_SEQ2R_USCH10_Msk & ((value) << AFEC_SEQ2R_USCH10_Pos))) +#define AFEC_SEQ2R_USCH11_Pos 12 +#define AFEC_SEQ2R_USCH11_Msk (0xfu << AFEC_SEQ2R_USCH11_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 11 */ +#define AFEC_SEQ2R_USCH11(value) ((AFEC_SEQ2R_USCH11_Msk & ((value) << AFEC_SEQ2R_USCH11_Pos))) +#define AFEC_SEQ2R_USCH12_Pos 16 +#define AFEC_SEQ2R_USCH12_Msk (0xfu << AFEC_SEQ2R_USCH12_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 12 */ +#define AFEC_SEQ2R_USCH12(value) ((AFEC_SEQ2R_USCH12_Msk & ((value) << AFEC_SEQ2R_USCH12_Pos))) +#define AFEC_SEQ2R_USCH13_Pos 20 +#define AFEC_SEQ2R_USCH13_Msk (0xfu << AFEC_SEQ2R_USCH13_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 13 */ +#define AFEC_SEQ2R_USCH13(value) ((AFEC_SEQ2R_USCH13_Msk & ((value) << AFEC_SEQ2R_USCH13_Pos))) +#define AFEC_SEQ2R_USCH14_Pos 24 +#define AFEC_SEQ2R_USCH14_Msk (0xfu << AFEC_SEQ2R_USCH14_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 14 */ +#define AFEC_SEQ2R_USCH14(value) ((AFEC_SEQ2R_USCH14_Msk & ((value) << AFEC_SEQ2R_USCH14_Pos))) +#define AFEC_SEQ2R_USCH15_Pos 28 +#define AFEC_SEQ2R_USCH15_Msk (0xfu << AFEC_SEQ2R_USCH15_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 15 */ +#define AFEC_SEQ2R_USCH15(value) ((AFEC_SEQ2R_USCH15_Msk & ((value) << AFEC_SEQ2R_USCH15_Pos))) +/* -------- AFEC_CHER : (AFEC Offset: 0x14) AFEC Channel Enable Register -------- */ +#define AFEC_CHER_CH0 (0x1u << 0) /**< \brief (AFEC_CHER) Channel 0 Enable */ +#define AFEC_CHER_CH1 (0x1u << 1) /**< \brief (AFEC_CHER) Channel 1 Enable */ +#define AFEC_CHER_CH2 (0x1u << 2) /**< \brief (AFEC_CHER) Channel 2 Enable */ +#define AFEC_CHER_CH3 (0x1u << 3) /**< \brief (AFEC_CHER) Channel 3 Enable */ +#define AFEC_CHER_CH4 (0x1u << 4) /**< \brief (AFEC_CHER) Channel 4 Enable */ +#define AFEC_CHER_CH5 (0x1u << 5) /**< \brief (AFEC_CHER) Channel 5 Enable */ +#define AFEC_CHER_CH6 (0x1u << 6) /**< \brief (AFEC_CHER) Channel 6 Enable */ +#define AFEC_CHER_CH7 (0x1u << 7) /**< \brief (AFEC_CHER) Channel 7 Enable */ +#define AFEC_CHER_CH8 (0x1u << 8) /**< \brief (AFEC_CHER) Channel 8 Enable */ +#define AFEC_CHER_CH9 (0x1u << 9) /**< \brief (AFEC_CHER) Channel 9 Enable */ +#define AFEC_CHER_CH10 (0x1u << 10) /**< \brief (AFEC_CHER) Channel 10 Enable */ +#define AFEC_CHER_CH11 (0x1u << 11) /**< \brief (AFEC_CHER) Channel 11 Enable */ +/* -------- AFEC_CHDR : (AFEC Offset: 0x18) AFEC Channel Disable Register -------- */ +#define AFEC_CHDR_CH0 (0x1u << 0) /**< \brief (AFEC_CHDR) Channel 0 Disable */ +#define AFEC_CHDR_CH1 (0x1u << 1) /**< \brief (AFEC_CHDR) Channel 1 Disable */ +#define AFEC_CHDR_CH2 (0x1u << 2) /**< \brief (AFEC_CHDR) Channel 2 Disable */ +#define AFEC_CHDR_CH3 (0x1u << 3) /**< \brief (AFEC_CHDR) Channel 3 Disable */ +#define AFEC_CHDR_CH4 (0x1u << 4) /**< \brief (AFEC_CHDR) Channel 4 Disable */ +#define AFEC_CHDR_CH5 (0x1u << 5) /**< \brief (AFEC_CHDR) Channel 5 Disable */ +#define AFEC_CHDR_CH6 (0x1u << 6) /**< \brief (AFEC_CHDR) Channel 6 Disable */ +#define AFEC_CHDR_CH7 (0x1u << 7) /**< \brief (AFEC_CHDR) Channel 7 Disable */ +#define AFEC_CHDR_CH8 (0x1u << 8) /**< \brief (AFEC_CHDR) Channel 8 Disable */ +#define AFEC_CHDR_CH9 (0x1u << 9) /**< \brief (AFEC_CHDR) Channel 9 Disable */ +#define AFEC_CHDR_CH10 (0x1u << 10) /**< \brief (AFEC_CHDR) Channel 10 Disable */ +#define AFEC_CHDR_CH11 (0x1u << 11) /**< \brief (AFEC_CHDR) Channel 11 Disable */ +/* -------- AFEC_CHSR : (AFEC Offset: 0x1C) AFEC Channel Status Register -------- */ +#define AFEC_CHSR_CH0 (0x1u << 0) /**< \brief (AFEC_CHSR) Channel 0 Status */ +#define AFEC_CHSR_CH1 (0x1u << 1) /**< \brief (AFEC_CHSR) Channel 1 Status */ +#define AFEC_CHSR_CH2 (0x1u << 2) /**< \brief (AFEC_CHSR) Channel 2 Status */ +#define AFEC_CHSR_CH3 (0x1u << 3) /**< \brief (AFEC_CHSR) Channel 3 Status */ +#define AFEC_CHSR_CH4 (0x1u << 4) /**< \brief (AFEC_CHSR) Channel 4 Status */ +#define AFEC_CHSR_CH5 (0x1u << 5) /**< \brief (AFEC_CHSR) Channel 5 Status */ +#define AFEC_CHSR_CH6 (0x1u << 6) /**< \brief (AFEC_CHSR) Channel 6 Status */ +#define AFEC_CHSR_CH7 (0x1u << 7) /**< \brief (AFEC_CHSR) Channel 7 Status */ +#define AFEC_CHSR_CH8 (0x1u << 8) /**< \brief (AFEC_CHSR) Channel 8 Status */ +#define AFEC_CHSR_CH9 (0x1u << 9) /**< \brief (AFEC_CHSR) Channel 9 Status */ +#define AFEC_CHSR_CH10 (0x1u << 10) /**< \brief (AFEC_CHSR) Channel 10 Status */ +#define AFEC_CHSR_CH11 (0x1u << 11) /**< \brief (AFEC_CHSR) Channel 11 Status */ +/* -------- AFEC_LCDR : (AFEC Offset: 0x20) AFEC Last Converted Data Register -------- */ +#define AFEC_LCDR_LDATA_Pos 0 +#define AFEC_LCDR_LDATA_Msk (0xffffu << AFEC_LCDR_LDATA_Pos) /**< \brief (AFEC_LCDR) Last Data Converted */ +#define AFEC_LCDR_CHNB_Pos 24 +#define AFEC_LCDR_CHNB_Msk (0xfu << AFEC_LCDR_CHNB_Pos) /**< \brief (AFEC_LCDR) Channel Number */ +/* -------- AFEC_IER : (AFEC Offset: 0x24) AFEC Interrupt Enable Register -------- */ +#define AFEC_IER_EOC0 (0x1u << 0) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 0 */ +#define AFEC_IER_EOC1 (0x1u << 1) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 1 */ +#define AFEC_IER_EOC2 (0x1u << 2) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 2 */ +#define AFEC_IER_EOC3 (0x1u << 3) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 3 */ +#define AFEC_IER_EOC4 (0x1u << 4) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 4 */ +#define AFEC_IER_EOC5 (0x1u << 5) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 5 */ +#define AFEC_IER_EOC6 (0x1u << 6) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 6 */ +#define AFEC_IER_EOC7 (0x1u << 7) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 7 */ +#define AFEC_IER_EOC8 (0x1u << 8) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 8 */ +#define AFEC_IER_EOC9 (0x1u << 9) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 9 */ +#define AFEC_IER_EOC10 (0x1u << 10) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 10 */ +#define AFEC_IER_EOC11 (0x1u << 11) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 11 */ +#define AFEC_IER_DRDY (0x1u << 24) /**< \brief (AFEC_IER) Data Ready Interrupt Enable */ +#define AFEC_IER_GOVRE (0x1u << 25) /**< \brief (AFEC_IER) General Overrun Error Interrupt Enable */ +#define AFEC_IER_COMPE (0x1u << 26) /**< \brief (AFEC_IER) Comparison Event Interrupt Enable */ +#define AFEC_IER_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IER) Temperature Change Interrupt Enable */ +/* -------- AFEC_IDR : (AFEC Offset: 0x28) AFEC Interrupt Disable Register -------- */ +#define AFEC_IDR_EOC0 (0x1u << 0) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 0 */ +#define AFEC_IDR_EOC1 (0x1u << 1) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 1 */ +#define AFEC_IDR_EOC2 (0x1u << 2) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 2 */ +#define AFEC_IDR_EOC3 (0x1u << 3) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 3 */ +#define AFEC_IDR_EOC4 (0x1u << 4) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 4 */ +#define AFEC_IDR_EOC5 (0x1u << 5) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 5 */ +#define AFEC_IDR_EOC6 (0x1u << 6) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 6 */ +#define AFEC_IDR_EOC7 (0x1u << 7) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 7 */ +#define AFEC_IDR_EOC8 (0x1u << 8) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 8 */ +#define AFEC_IDR_EOC9 (0x1u << 9) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 9 */ +#define AFEC_IDR_EOC10 (0x1u << 10) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 10 */ +#define AFEC_IDR_EOC11 (0x1u << 11) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 11 */ +#define AFEC_IDR_DRDY (0x1u << 24) /**< \brief (AFEC_IDR) Data Ready Interrupt Disable */ +#define AFEC_IDR_GOVRE (0x1u << 25) /**< \brief (AFEC_IDR) General Overrun Error Interrupt Disable */ +#define AFEC_IDR_COMPE (0x1u << 26) /**< \brief (AFEC_IDR) Comparison Event Interrupt Disable */ +#define AFEC_IDR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IDR) Temperature Change Interrupt Disable */ +/* -------- AFEC_IMR : (AFEC Offset: 0x2C) AFEC Interrupt Mask Register -------- */ +#define AFEC_IMR_EOC0 (0x1u << 0) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 0 */ +#define AFEC_IMR_EOC1 (0x1u << 1) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 1 */ +#define AFEC_IMR_EOC2 (0x1u << 2) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 2 */ +#define AFEC_IMR_EOC3 (0x1u << 3) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 3 */ +#define AFEC_IMR_EOC4 (0x1u << 4) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 4 */ +#define AFEC_IMR_EOC5 (0x1u << 5) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 5 */ +#define AFEC_IMR_EOC6 (0x1u << 6) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 6 */ +#define AFEC_IMR_EOC7 (0x1u << 7) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 7 */ +#define AFEC_IMR_EOC8 (0x1u << 8) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 8 */ +#define AFEC_IMR_EOC9 (0x1u << 9) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 9 */ +#define AFEC_IMR_EOC10 (0x1u << 10) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 10 */ +#define AFEC_IMR_EOC11 (0x1u << 11) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 11 */ +#define AFEC_IMR_DRDY (0x1u << 24) /**< \brief (AFEC_IMR) Data Ready Interrupt Mask */ +#define AFEC_IMR_GOVRE (0x1u << 25) /**< \brief (AFEC_IMR) General Overrun Error Interrupt Mask */ +#define AFEC_IMR_COMPE (0x1u << 26) /**< \brief (AFEC_IMR) Comparison Event Interrupt Mask */ +#define AFEC_IMR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IMR) Temperature Change Interrupt Mask */ +/* -------- AFEC_ISR : (AFEC Offset: 0x30) AFEC Interrupt Status Register -------- */ +#define AFEC_ISR_EOC0 (0x1u << 0) /**< \brief (AFEC_ISR) End of Conversion 0 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC1 (0x1u << 1) /**< \brief (AFEC_ISR) End of Conversion 1 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC2 (0x1u << 2) /**< \brief (AFEC_ISR) End of Conversion 2 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC3 (0x1u << 3) /**< \brief (AFEC_ISR) End of Conversion 3 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC4 (0x1u << 4) /**< \brief (AFEC_ISR) End of Conversion 4 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC5 (0x1u << 5) /**< \brief (AFEC_ISR) End of Conversion 5 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC6 (0x1u << 6) /**< \brief (AFEC_ISR) End of Conversion 6 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC7 (0x1u << 7) /**< \brief (AFEC_ISR) End of Conversion 7 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC8 (0x1u << 8) /**< \brief (AFEC_ISR) End of Conversion 8 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC9 (0x1u << 9) /**< \brief (AFEC_ISR) End of Conversion 9 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC10 (0x1u << 10) /**< \brief (AFEC_ISR) End of Conversion 10 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC11 (0x1u << 11) /**< \brief (AFEC_ISR) End of Conversion 11 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_DRDY (0x1u << 24) /**< \brief (AFEC_ISR) Data Ready (cleared by reading AFEC_LCDR) */ +#define AFEC_ISR_GOVRE (0x1u << 25) /**< \brief (AFEC_ISR) General Overrun Error (cleared by reading AFEC_ISR) */ +#define AFEC_ISR_COMPE (0x1u << 26) /**< \brief (AFEC_ISR) Comparison Error (cleared by reading AFEC_ISR) */ +#define AFEC_ISR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_ISR) Temperature Change (cleared on read) */ +/* -------- AFEC_OVER : (AFEC Offset: 0x4C) AFEC Overrun Status Register -------- */ +#define AFEC_OVER_OVRE0 (0x1u << 0) /**< \brief (AFEC_OVER) Overrun Error 0 */ +#define AFEC_OVER_OVRE1 (0x1u << 1) /**< \brief (AFEC_OVER) Overrun Error 1 */ +#define AFEC_OVER_OVRE2 (0x1u << 2) /**< \brief (AFEC_OVER) Overrun Error 2 */ +#define AFEC_OVER_OVRE3 (0x1u << 3) /**< \brief (AFEC_OVER) Overrun Error 3 */ +#define AFEC_OVER_OVRE4 (0x1u << 4) /**< \brief (AFEC_OVER) Overrun Error 4 */ +#define AFEC_OVER_OVRE5 (0x1u << 5) /**< \brief (AFEC_OVER) Overrun Error 5 */ +#define AFEC_OVER_OVRE6 (0x1u << 6) /**< \brief (AFEC_OVER) Overrun Error 6 */ +#define AFEC_OVER_OVRE7 (0x1u << 7) /**< \brief (AFEC_OVER) Overrun Error 7 */ +#define AFEC_OVER_OVRE8 (0x1u << 8) /**< \brief (AFEC_OVER) Overrun Error 8 */ +#define AFEC_OVER_OVRE9 (0x1u << 9) /**< \brief (AFEC_OVER) Overrun Error 9 */ +#define AFEC_OVER_OVRE10 (0x1u << 10) /**< \brief (AFEC_OVER) Overrun Error 10 */ +#define AFEC_OVER_OVRE11 (0x1u << 11) /**< \brief (AFEC_OVER) Overrun Error 11 */ +/* -------- AFEC_CWR : (AFEC Offset: 0x50) AFEC Compare Window Register -------- */ +#define AFEC_CWR_LOWTHRES_Pos 0 +#define AFEC_CWR_LOWTHRES_Msk (0xffffu << AFEC_CWR_LOWTHRES_Pos) /**< \brief (AFEC_CWR) Low Threshold */ +#define AFEC_CWR_LOWTHRES(value) ((AFEC_CWR_LOWTHRES_Msk & ((value) << AFEC_CWR_LOWTHRES_Pos))) +#define AFEC_CWR_HIGHTHRES_Pos 16 +#define AFEC_CWR_HIGHTHRES_Msk (0xffffu << AFEC_CWR_HIGHTHRES_Pos) /**< \brief (AFEC_CWR) High Threshold */ +#define AFEC_CWR_HIGHTHRES(value) ((AFEC_CWR_HIGHTHRES_Msk & ((value) << AFEC_CWR_HIGHTHRES_Pos))) +/* -------- AFEC_CGR : (AFEC Offset: 0x54) AFEC Channel Gain Register -------- */ +#define AFEC_CGR_GAIN0_Pos 0 +#define AFEC_CGR_GAIN0_Msk (0x3u << AFEC_CGR_GAIN0_Pos) /**< \brief (AFEC_CGR) Gain for Channel 0 */ +#define AFEC_CGR_GAIN0(value) ((AFEC_CGR_GAIN0_Msk & ((value) << AFEC_CGR_GAIN0_Pos))) +#define AFEC_CGR_GAIN1_Pos 2 +#define AFEC_CGR_GAIN1_Msk (0x3u << AFEC_CGR_GAIN1_Pos) /**< \brief (AFEC_CGR) Gain for Channel 1 */ +#define AFEC_CGR_GAIN1(value) ((AFEC_CGR_GAIN1_Msk & ((value) << AFEC_CGR_GAIN1_Pos))) +#define AFEC_CGR_GAIN2_Pos 4 +#define AFEC_CGR_GAIN2_Msk (0x3u << AFEC_CGR_GAIN2_Pos) /**< \brief (AFEC_CGR) Gain for Channel 2 */ +#define AFEC_CGR_GAIN2(value) ((AFEC_CGR_GAIN2_Msk & ((value) << AFEC_CGR_GAIN2_Pos))) +#define AFEC_CGR_GAIN3_Pos 6 +#define AFEC_CGR_GAIN3_Msk (0x3u << AFEC_CGR_GAIN3_Pos) /**< \brief (AFEC_CGR) Gain for Channel 3 */ +#define AFEC_CGR_GAIN3(value) ((AFEC_CGR_GAIN3_Msk & ((value) << AFEC_CGR_GAIN3_Pos))) +#define AFEC_CGR_GAIN4_Pos 8 +#define AFEC_CGR_GAIN4_Msk (0x3u << AFEC_CGR_GAIN4_Pos) /**< \brief (AFEC_CGR) Gain for Channel 4 */ +#define AFEC_CGR_GAIN4(value) ((AFEC_CGR_GAIN4_Msk & ((value) << AFEC_CGR_GAIN4_Pos))) +#define AFEC_CGR_GAIN5_Pos 10 +#define AFEC_CGR_GAIN5_Msk (0x3u << AFEC_CGR_GAIN5_Pos) /**< \brief (AFEC_CGR) Gain for Channel 5 */ +#define AFEC_CGR_GAIN5(value) ((AFEC_CGR_GAIN5_Msk & ((value) << AFEC_CGR_GAIN5_Pos))) +#define AFEC_CGR_GAIN6_Pos 12 +#define AFEC_CGR_GAIN6_Msk (0x3u << AFEC_CGR_GAIN6_Pos) /**< \brief (AFEC_CGR) Gain for Channel 6 */ +#define AFEC_CGR_GAIN6(value) ((AFEC_CGR_GAIN6_Msk & ((value) << AFEC_CGR_GAIN6_Pos))) +#define AFEC_CGR_GAIN7_Pos 14 +#define AFEC_CGR_GAIN7_Msk (0x3u << AFEC_CGR_GAIN7_Pos) /**< \brief (AFEC_CGR) Gain for Channel 7 */ +#define AFEC_CGR_GAIN7(value) ((AFEC_CGR_GAIN7_Msk & ((value) << AFEC_CGR_GAIN7_Pos))) +#define AFEC_CGR_GAIN8_Pos 16 +#define AFEC_CGR_GAIN8_Msk (0x3u << AFEC_CGR_GAIN8_Pos) /**< \brief (AFEC_CGR) Gain for Channel 8 */ +#define AFEC_CGR_GAIN8(value) ((AFEC_CGR_GAIN8_Msk & ((value) << AFEC_CGR_GAIN8_Pos))) +#define AFEC_CGR_GAIN9_Pos 18 +#define AFEC_CGR_GAIN9_Msk (0x3u << AFEC_CGR_GAIN9_Pos) /**< \brief (AFEC_CGR) Gain for Channel 9 */ +#define AFEC_CGR_GAIN9(value) ((AFEC_CGR_GAIN9_Msk & ((value) << AFEC_CGR_GAIN9_Pos))) +#define AFEC_CGR_GAIN10_Pos 20 +#define AFEC_CGR_GAIN10_Msk (0x3u << AFEC_CGR_GAIN10_Pos) /**< \brief (AFEC_CGR) Gain for Channel 10 */ +#define AFEC_CGR_GAIN10(value) ((AFEC_CGR_GAIN10_Msk & ((value) << AFEC_CGR_GAIN10_Pos))) +#define AFEC_CGR_GAIN11_Pos 22 +#define AFEC_CGR_GAIN11_Msk (0x3u << AFEC_CGR_GAIN11_Pos) /**< \brief (AFEC_CGR) Gain for Channel 11 */ +#define AFEC_CGR_GAIN11(value) ((AFEC_CGR_GAIN11_Msk & ((value) << AFEC_CGR_GAIN11_Pos))) +/* -------- AFEC_DIFFR : (AFEC Offset: 0x60) AFEC Channel Differential Register -------- */ +#define AFEC_DIFFR_DIFF0 (0x1u << 0) /**< \brief (AFEC_DIFFR) Differential inputs for channel 0 */ +#define AFEC_DIFFR_DIFF1 (0x1u << 1) /**< \brief (AFEC_DIFFR) Differential inputs for channel 1 */ +#define AFEC_DIFFR_DIFF2 (0x1u << 2) /**< \brief (AFEC_DIFFR) Differential inputs for channel 2 */ +#define AFEC_DIFFR_DIFF3 (0x1u << 3) /**< \brief (AFEC_DIFFR) Differential inputs for channel 3 */ +#define AFEC_DIFFR_DIFF4 (0x1u << 4) /**< \brief (AFEC_DIFFR) Differential inputs for channel 4 */ +#define AFEC_DIFFR_DIFF5 (0x1u << 5) /**< \brief (AFEC_DIFFR) Differential inputs for channel 5 */ +#define AFEC_DIFFR_DIFF6 (0x1u << 6) /**< \brief (AFEC_DIFFR) Differential inputs for channel 6 */ +#define AFEC_DIFFR_DIFF7 (0x1u << 7) /**< \brief (AFEC_DIFFR) Differential inputs for channel 7 */ +#define AFEC_DIFFR_DIFF8 (0x1u << 8) /**< \brief (AFEC_DIFFR) Differential inputs for channel 8 */ +#define AFEC_DIFFR_DIFF9 (0x1u << 9) /**< \brief (AFEC_DIFFR) Differential inputs for channel 9 */ +#define AFEC_DIFFR_DIFF10 (0x1u << 10) /**< \brief (AFEC_DIFFR) Differential inputs for channel 10 */ +#define AFEC_DIFFR_DIFF11 (0x1u << 11) /**< \brief (AFEC_DIFFR) Differential inputs for channel 11 */ +/* -------- AFEC_CSELR : (AFEC Offset: 0x64) AFEC Channel Selection Register -------- */ +#define AFEC_CSELR_CSEL_Pos 0 +#define AFEC_CSELR_CSEL_Msk (0xfu << AFEC_CSELR_CSEL_Pos) /**< \brief (AFEC_CSELR) Channel Selection */ +#define AFEC_CSELR_CSEL(value) ((AFEC_CSELR_CSEL_Msk & ((value) << AFEC_CSELR_CSEL_Pos))) +/* -------- AFEC_CDR : (AFEC Offset: 0x68) AFEC Channel Data Register -------- */ +#define AFEC_CDR_DATA_Pos 0 +#define AFEC_CDR_DATA_Msk (0xffffu << AFEC_CDR_DATA_Pos) /**< \brief (AFEC_CDR) Converted Data */ +/* -------- AFEC_COCR : (AFEC Offset: 0x6C) AFEC Channel Offset Compensation Register -------- */ +#define AFEC_COCR_AOFF_Pos 0 +#define AFEC_COCR_AOFF_Msk (0xfffu << AFEC_COCR_AOFF_Pos) /**< \brief (AFEC_COCR) Analog Offset */ +#define AFEC_COCR_AOFF(value) ((AFEC_COCR_AOFF_Msk & ((value) << AFEC_COCR_AOFF_Pos))) +/* -------- AFEC_TEMPMR : (AFEC Offset: 0x70) AFEC Temperature Sensor Mode Register -------- */ +#define AFEC_TEMPMR_RTCT (0x1u << 0) /**< \brief (AFEC_TEMPMR) Temperature Sensor RTC Trigger Mode */ +#define AFEC_TEMPMR_TEMPCMPMOD_Pos 4 +#define AFEC_TEMPMR_TEMPCMPMOD_Msk (0x3u << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< \brief (AFEC_TEMPMR) Temperature Comparison Mode */ +#define AFEC_TEMPMR_TEMPCMPMOD(value) ((AFEC_TEMPMR_TEMPCMPMOD_Msk & ((value) << AFEC_TEMPMR_TEMPCMPMOD_Pos))) +#define AFEC_TEMPMR_TEMPCMPMOD_LOW (0x0u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is lower than the low threshold of the window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_HIGH (0x1u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is higher than the high threshold of the window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_IN (0x2u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is in the comparison window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_OUT (0x3u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is out of the comparison window. */ +/* -------- AFEC_TEMPCWR : (AFEC Offset: 0x74) AFEC Temperature Compare Window Register -------- */ +#define AFEC_TEMPCWR_TLOWTHRES_Pos 0 +#define AFEC_TEMPCWR_TLOWTHRES_Msk (0xffffu << AFEC_TEMPCWR_TLOWTHRES_Pos) /**< \brief (AFEC_TEMPCWR) Temperature Low Threshold */ +#define AFEC_TEMPCWR_TLOWTHRES(value) ((AFEC_TEMPCWR_TLOWTHRES_Msk & ((value) << AFEC_TEMPCWR_TLOWTHRES_Pos))) +#define AFEC_TEMPCWR_THIGHTHRES_Pos 16 +#define AFEC_TEMPCWR_THIGHTHRES_Msk (0xffffu << AFEC_TEMPCWR_THIGHTHRES_Pos) /**< \brief (AFEC_TEMPCWR) Temperature High Threshold */ +#define AFEC_TEMPCWR_THIGHTHRES(value) ((AFEC_TEMPCWR_THIGHTHRES_Msk & ((value) << AFEC_TEMPCWR_THIGHTHRES_Pos))) +/* -------- AFEC_ACR : (AFEC Offset: 0x94) AFEC Analog Control Register -------- */ +#define AFEC_ACR_PGA0EN (0x1u << 2) /**< \brief (AFEC_ACR) PGA0 Enable */ +#define AFEC_ACR_PGA1EN (0x1u << 3) /**< \brief (AFEC_ACR) PGA1 Enable */ +#define AFEC_ACR_IBCTL_Pos 8 +#define AFEC_ACR_IBCTL_Msk (0x3u << AFEC_ACR_IBCTL_Pos) /**< \brief (AFEC_ACR) AFE Bias Current Control */ +#define AFEC_ACR_IBCTL(value) ((AFEC_ACR_IBCTL_Msk & ((value) << AFEC_ACR_IBCTL_Pos))) +/* -------- AFEC_SHMR : (AFEC Offset: 0xA0) AFEC Sample & Hold Mode Register -------- */ +#define AFEC_SHMR_DUAL0 (0x1u << 0) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 0 */ +#define AFEC_SHMR_DUAL1 (0x1u << 1) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 1 */ +#define AFEC_SHMR_DUAL2 (0x1u << 2) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 2 */ +#define AFEC_SHMR_DUAL3 (0x1u << 3) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 3 */ +#define AFEC_SHMR_DUAL4 (0x1u << 4) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 4 */ +#define AFEC_SHMR_DUAL5 (0x1u << 5) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 5 */ +#define AFEC_SHMR_DUAL6 (0x1u << 6) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 6 */ +#define AFEC_SHMR_DUAL7 (0x1u << 7) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 7 */ +#define AFEC_SHMR_DUAL8 (0x1u << 8) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 8 */ +#define AFEC_SHMR_DUAL9 (0x1u << 9) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 9 */ +#define AFEC_SHMR_DUAL10 (0x1u << 10) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 10 */ +#define AFEC_SHMR_DUAL11 (0x1u << 11) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 11 */ +/* -------- AFEC_COSR : (AFEC Offset: 0xD0) AFEC Correction Select Register -------- */ +#define AFEC_COSR_CSEL (0x1u << 0) /**< \brief (AFEC_COSR) Sample & Hold unit Correction Select */ +/* -------- AFEC_CVR : (AFEC Offset: 0xD4) AFEC Correction Values Register -------- */ +#define AFEC_CVR_OFFSETCORR_Pos 0 +#define AFEC_CVR_OFFSETCORR_Msk (0xffffu << AFEC_CVR_OFFSETCORR_Pos) /**< \brief (AFEC_CVR) Offset Correction */ +#define AFEC_CVR_OFFSETCORR(value) ((AFEC_CVR_OFFSETCORR_Msk & ((value) << AFEC_CVR_OFFSETCORR_Pos))) +#define AFEC_CVR_GAINCORR_Pos 16 +#define AFEC_CVR_GAINCORR_Msk (0xffffu << AFEC_CVR_GAINCORR_Pos) /**< \brief (AFEC_CVR) Gain Correction */ +#define AFEC_CVR_GAINCORR(value) ((AFEC_CVR_GAINCORR_Msk & ((value) << AFEC_CVR_GAINCORR_Pos))) +/* -------- AFEC_CECR : (AFEC Offset: 0xD8) AFEC Channel Error Correction Register -------- */ +#define AFEC_CECR_ECORR0 (0x1u << 0) /**< \brief (AFEC_CECR) Error Correction Enable for channel 0 */ +#define AFEC_CECR_ECORR1 (0x1u << 1) /**< \brief (AFEC_CECR) Error Correction Enable for channel 1 */ +#define AFEC_CECR_ECORR2 (0x1u << 2) /**< \brief (AFEC_CECR) Error Correction Enable for channel 2 */ +#define AFEC_CECR_ECORR3 (0x1u << 3) /**< \brief (AFEC_CECR) Error Correction Enable for channel 3 */ +#define AFEC_CECR_ECORR4 (0x1u << 4) /**< \brief (AFEC_CECR) Error Correction Enable for channel 4 */ +#define AFEC_CECR_ECORR5 (0x1u << 5) /**< \brief (AFEC_CECR) Error Correction Enable for channel 5 */ +#define AFEC_CECR_ECORR6 (0x1u << 6) /**< \brief (AFEC_CECR) Error Correction Enable for channel 6 */ +#define AFEC_CECR_ECORR7 (0x1u << 7) /**< \brief (AFEC_CECR) Error Correction Enable for channel 7 */ +#define AFEC_CECR_ECORR8 (0x1u << 8) /**< \brief (AFEC_CECR) Error Correction Enable for channel 8 */ +#define AFEC_CECR_ECORR9 (0x1u << 9) /**< \brief (AFEC_CECR) Error Correction Enable for channel 9 */ +#define AFEC_CECR_ECORR10 (0x1u << 10) /**< \brief (AFEC_CECR) Error Correction Enable for channel 10 */ +#define AFEC_CECR_ECORR11 (0x1u << 11) /**< \brief (AFEC_CECR) Error Correction Enable for channel 11 */ +/* -------- AFEC_WPMR : (AFEC Offset: 0xE4) AFEC Write Protection Mode Register -------- */ +#define AFEC_WPMR_WPEN (0x1u << 0) /**< \brief (AFEC_WPMR) Write Protection Enable */ +#define AFEC_WPMR_WPKEY_Pos 8 +#define AFEC_WPMR_WPKEY_Msk (0xffffffu << AFEC_WPMR_WPKEY_Pos) /**< \brief (AFEC_WPMR) Write Protect KEY */ +#define AFEC_WPMR_WPKEY(value) ((AFEC_WPMR_WPKEY_Msk & ((value) << AFEC_WPMR_WPKEY_Pos))) +#define AFEC_WPMR_WPKEY_PASSWD (0x414443u << 8) /**< \brief (AFEC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- AFEC_WPSR : (AFEC Offset: 0xE8) AFEC Write Protection Status Register -------- */ +#define AFEC_WPSR_WPVS (0x1u << 0) /**< \brief (AFEC_WPSR) Write Protect Violation Status */ +#define AFEC_WPSR_WPVSRC_Pos 8 +#define AFEC_WPSR_WPVSRC_Msk (0xffffu << AFEC_WPSR_WPVSRC_Pos) /**< \brief (AFEC_WPSR) Write Protect Violation Source */ + +/*@}*/ + + +#endif /* _SAMV71_AFEC_COMPONENT_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_chipid.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_chipid.h new file mode 100644 index 00000000..c9571829 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_chipid.h @@ -0,0 +1,123 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_CHIPID_COMPONENT_ +#define _SAMV71_CHIPID_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Chip Identifier */ +/* ============================================================================= */ +/** \addtogroup SAMV71_CHIPID Chip Identifier */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Chipid hardware registers */ +typedef struct { + __I uint32_t CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */ + __I uint32_t CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */ +} Chipid; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */ +#define CHIPID_CIDR_VERSION_Pos 0 +#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */ +#define CHIPID_CIDR_EPROC_Pos 5 +#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */ +#define CHIPID_CIDR_EPROC_SAMx7 (0x0u << 5) /**< \brief (CHIPID_CIDR) Cortex-M7 */ +#define CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */ +#define CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */ +#define CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */ +#define CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */ +#define CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */ +#define CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */ +#define CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */ +#define CHIPID_CIDR_NVPSIZ_Pos 8 +#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */ +#define CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */ +#define CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_160K (0x8u << 8) /**< \brief (CHIPID_CIDR) 160 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_Pos 12 +#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) Second Nonvolatile Program Memory Size */ +#define CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */ +#define CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_Pos 16 +#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */ +#define CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_192K (0x1u << 16) /**< \brief (CHIPID_CIDR) 192 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_384K (0x2u << 16) /**< \brief (CHIPID_CIDR) 384 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_ARCH_Pos 20 +#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */ +#define CHIPID_CIDR_ARCH_SAME70 (0x10u << 20) /**< \brief (CHIPID_CIDR) SAM E70 */ +#define CHIPID_CIDR_ARCH_SAMS70 (0x11u << 20) /**< \brief (CHIPID_CIDR) SAM S70 */ +#define CHIPID_CIDR_ARCH_SAMV71 (0x12u << 20) /**< \brief (CHIPID_CIDR) SAM V71 */ +#define CHIPID_CIDR_ARCH_SAMV70 (0x13u << 20) /**< \brief (CHIPID_CIDR) SAM V70 */ +#define CHIPID_CIDR_NVPTYP_Pos 28 +#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */ +#define CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */ +#define CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */ +#define CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */ +#define CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size */ +#define CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */ +#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */ +/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */ +#define CHIPID_EXID_EXID_Pos 0 +#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */ + +/*@}*/ + + +#endif /* _SAMV71_CHIPID_COMPONENT_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_dacc.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_dacc.h new file mode 100644 index 00000000..c20cbf38 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_dacc.h @@ -0,0 +1,202 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_DACC_COMPONENT_ +#define _SAMV71_DACC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_DACC Digital-to-Analog Converter Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Dacc hardware registers */ +typedef struct { + __O uint32_t DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */ + __IO uint32_t DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */ + __IO uint32_t DACC_TRIGR; /**< \brief (Dacc Offset: 0x08) Trigger Register */ + __I uint32_t Reserved1[1]; + __O uint32_t DACC_CHER; /**< \brief (Dacc Offset: 0x10) Channel Enable Register */ + __O uint32_t DACC_CHDR; /**< \brief (Dacc Offset: 0x14) Channel Disable Register */ + __I uint32_t DACC_CHSR; /**< \brief (Dacc Offset: 0x18) Channel Status Register */ + __O uint32_t DACC_CDR[2]; /**< \brief (Dacc Offset: 0x1C) Conversion Data Register */ + __O uint32_t DACC_IER; /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */ + __O uint32_t DACC_IDR; /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */ + __I uint32_t DACC_IMR; /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t DACC_ISR; /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */ + __I uint32_t Reserved2[24]; + __IO uint32_t DACC_ACR; /**< \brief (Dacc Offset: 0x94) Analog Current Register */ + __I uint32_t Reserved3[19]; + __IO uint32_t DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protection Mode register */ + __I uint32_t DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protection Status register */ +} Dacc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */ +#define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */ +/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */ +#define DACC_MR_MAXS0 (0x1u << 0) /**< \brief (DACC_MR) Max Speed Mode for Channel 0 */ +#define DACC_MR_MAXS0_TRIG_EVENT (0x0u << 0) /**< \brief (DACC_MR) Triggered by selected event */ +#define DACC_MR_MAXS0_MAXIMUM (0x1u << 0) /**< \brief (DACC_MR) Max Speed Mode enabled */ +#define DACC_MR_MAXS1 (0x1u << 1) /**< \brief (DACC_MR) Max Speed Mode for Channel 1 */ +#define DACC_MR_MAXS1_TRIG_EVENT (0x0u << 1) /**< \brief (DACC_MR) Triggered by selected event */ +#define DACC_MR_MAXS1_MAXIMUM (0x1u << 1) /**< \brief (DACC_MR) Max Speed Mode enabled */ +#define DACC_MR_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer Mode */ +#define DACC_MR_WORD_DISABLED (0x0u << 4) /**< \brief (DACC_MR) One data to convert is written to the FIFO per access to DACC */ +#define DACC_MR_WORD_ENABLED (0x1u << 4) /**< \brief (DACC_MR) Two data to convert are written to the FIFO per access to DACC (reduces number of requests to DMA and the number of system bus accesses) */ +#define DACC_MR_REFRESH_Pos 8 +#define DACC_MR_REFRESH_Msk (0xffu << DACC_MR_REFRESH_Pos) /**< \brief (DACC_MR) Refresh Period */ +#define DACC_MR_REFRESH(value) ((DACC_MR_REFRESH_Msk & ((value) << DACC_MR_REFRESH_Pos))) +#define DACC_MR_DIFF (0x1u << 23) /**< \brief (DACC_MR) Differential Mode */ +#define DACC_MR_DIFF_DISABLED (0x0u << 23) /**< \brief (DACC_MR) DAC0 and DAC1 outputs can be separately configured */ +#define DACC_MR_DIFF_ENABLED (0x1u << 23) /**< \brief (DACC_MR) DACP and DACN outputs are configured by the channel 0 value. */ +#define DACC_MR_PRESCALER_Pos 24 +#define DACC_MR_PRESCALER_Msk (0xfu << DACC_MR_PRESCALER_Pos) /**< \brief (DACC_MR) Peripheral Clock to DAC Clock Ratio */ +#define DACC_MR_PRESCALER(value) ((DACC_MR_PRESCALER_Msk & ((value) << DACC_MR_PRESCALER_Pos))) +/* -------- DACC_TRIGR : (DACC Offset: 0x08) Trigger Register -------- */ +#define DACC_TRIGR_TRGEN0 (0x1u << 0) /**< \brief (DACC_TRIGR) Trigger Enable of Channel 0 */ +#define DACC_TRIGR_TRGEN0_DIS (0x0u << 0) /**< \brief (DACC_TRIGR) External trigger mode disabled. DAC is in free running mode. */ +#define DACC_TRIGR_TRGEN0_EN (0x1u << 0) /**< \brief (DACC_TRIGR) External trigger mode enabled. */ +#define DACC_TRIGR_TRGEN1 (0x1u << 1) /**< \brief (DACC_TRIGR) Trigger Enable of Channel 1 */ +#define DACC_TRIGR_TRGEN1_DIS (0x0u << 1) /**< \brief (DACC_TRIGR) External trigger mode disabled. DAC is in free running mode. */ +#define DACC_TRIGR_TRGEN1_EN (0x1u << 1) /**< \brief (DACC_TRIGR) External trigger mode enabled. */ +#define DACC_TRIGR_TRGSEL0_Pos 4 +#define DACC_TRIGR_TRGSEL0_Msk (0x7u << DACC_TRIGR_TRGSEL0_Pos) /**< \brief (DACC_TRIGR) Trigger Selection of Channel 0 */ +#define DACC_TRIGR_TRGSEL0(value) ((DACC_TRIGR_TRGSEL0_Msk & ((value) << DACC_TRIGR_TRGSEL0_Pos))) +#define DACC_TRIGR_TRGSEL0_TRGSEL0 (0x0u << 4) /**< \brief (DACC_TRIGR) TC0 output */ +#define DACC_TRIGR_TRGSEL0_TRGSEL1 (0x1u << 4) /**< \brief (DACC_TRIGR) TC1 output */ +#define DACC_TRIGR_TRGSEL0_TRGSEL2 (0x2u << 4) /**< \brief (DACC_TRIGR) TC2 output */ +#define DACC_TRIGR_TRGSEL0_TRGSEL3 (0x3u << 4) /**< \brief (DACC_TRIGR) PWM0 event 0 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL4 (0x4u << 4) /**< \brief (DACC_TRIGR) PWM0 event 1 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL5 (0x5u << 4) /**< \brief (DACC_TRIGR) PWM1 event 0 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL6 (0x6u << 4) /**< \brief (DACC_TRIGR) PWM1 event 1 */ +#define DACC_TRIGR_TRGSEL1_Pos 8 +#define DACC_TRIGR_TRGSEL1_Msk (0x7u << DACC_TRIGR_TRGSEL1_Pos) /**< \brief (DACC_TRIGR) Trigger Selection of Channel 1 */ +#define DACC_TRIGR_TRGSEL1(value) ((DACC_TRIGR_TRGSEL1_Msk & ((value) << DACC_TRIGR_TRGSEL1_Pos))) +#define DACC_TRIGR_TRGSEL1_TRGSEL0 (0x0u << 8) /**< \brief (DACC_TRIGR) TC0 output */ +#define DACC_TRIGR_TRGSEL1_TRGSEL1 (0x1u << 8) /**< \brief (DACC_TRIGR) TC1 output */ +#define DACC_TRIGR_TRGSEL1_TRGSEL2 (0x2u << 8) /**< \brief (DACC_TRIGR) TC2 output */ +#define DACC_TRIGR_TRGSEL1_TRGSEL3 (0x3u << 8) /**< \brief (DACC_TRIGR) PWM0 event 0 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL4 (0x4u << 8) /**< \brief (DACC_TRIGR) PWM0 event 1 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL5 (0x5u << 8) /**< \brief (DACC_TRIGR) PWM1 event 0 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL6 (0x6u << 8) /**< \brief (DACC_TRIGR) PWM1 event 1 */ +#define DACC_TRIGR_OSR0_Pos 16 +#define DACC_TRIGR_OSR0_Msk (0x7u << DACC_TRIGR_OSR0_Pos) /**< \brief (DACC_TRIGR) Over Sampling Ratio of Channel 0 */ +#define DACC_TRIGR_OSR0(value) ((DACC_TRIGR_OSR0_Msk & ((value) << DACC_TRIGR_OSR0_Pos))) +#define DACC_TRIGR_OSR0_OSR_1 (0x0u << 16) /**< \brief (DACC_TRIGR) OSR = 1 */ +#define DACC_TRIGR_OSR0_OSR_2 (0x1u << 16) /**< \brief (DACC_TRIGR) OSR = 2 */ +#define DACC_TRIGR_OSR0_OSR_4 (0x2u << 16) /**< \brief (DACC_TRIGR) OSR = 4 */ +#define DACC_TRIGR_OSR0_OSR_8 (0x3u << 16) /**< \brief (DACC_TRIGR) OSR = 8 */ +#define DACC_TRIGR_OSR0_OSR_16 (0x4u << 16) /**< \brief (DACC_TRIGR) OSR = 16 */ +#define DACC_TRIGR_OSR0_OSR_32 (0x5u << 16) /**< \brief (DACC_TRIGR) OSR = 32 */ +#define DACC_TRIGR_OSR1_Pos 20 +#define DACC_TRIGR_OSR1_Msk (0x7u << DACC_TRIGR_OSR1_Pos) /**< \brief (DACC_TRIGR) Over Sampling Ratio of Channel 1 */ +#define DACC_TRIGR_OSR1(value) ((DACC_TRIGR_OSR1_Msk & ((value) << DACC_TRIGR_OSR1_Pos))) +#define DACC_TRIGR_OSR1_OSR_1 (0x0u << 20) /**< \brief (DACC_TRIGR) OSR = 1 */ +#define DACC_TRIGR_OSR1_OSR_2 (0x1u << 20) /**< \brief (DACC_TRIGR) OSR = 2 */ +#define DACC_TRIGR_OSR1_OSR_4 (0x2u << 20) /**< \brief (DACC_TRIGR) OSR = 4 */ +#define DACC_TRIGR_OSR1_OSR_8 (0x3u << 20) /**< \brief (DACC_TRIGR) OSR = 8 */ +#define DACC_TRIGR_OSR1_OSR_16 (0x4u << 20) /**< \brief (DACC_TRIGR) OSR = 16 */ +#define DACC_TRIGR_OSR1_OSR_32 (0x5u << 20) /**< \brief (DACC_TRIGR) OSR = 32 */ +/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */ +#define DACC_CHER_CH0 (0x1u << 0) /**< \brief (DACC_CHER) Channel 0 Enable */ +#define DACC_CHER_CH1 (0x1u << 1) /**< \brief (DACC_CHER) Channel 1 Enable */ +/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */ +#define DACC_CHDR_CH0 (0x1u << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */ +#define DACC_CHDR_CH1 (0x1u << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */ +/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */ +#define DACC_CHSR_CH0 (0x1u << 0) /**< \brief (DACC_CHSR) Channel 0 Status */ +#define DACC_CHSR_CH1 (0x1u << 1) /**< \brief (DACC_CHSR) Channel 1 Status */ +#define DACC_CHSR_DACRDY0 (0x1u << 8) /**< \brief (DACC_CHSR) DAC ready flag */ +#define DACC_CHSR_DACRDY1 (0x1u << 9) /**< \brief (DACC_CHSR) DAC ready flag */ +/* -------- DACC_CDR[2] : (DACC Offset: 0x1C) Conversion Data Register -------- */ +#define DACC_CDR_DATA0_Pos 0 +#define DACC_CDR_DATA0_Msk (0xffffu << DACC_CDR_DATA0_Pos) /**< \brief (DACC_CDR[2]) Data to Convert for channel 0 */ +#define DACC_CDR_DATA0(value) ((DACC_CDR_DATA0_Msk & ((value) << DACC_CDR_DATA0_Pos))) +#define DACC_CDR_DATA1_Pos 16 +#define DACC_CDR_DATA1_Msk (0xffffu << DACC_CDR_DATA1_Pos) /**< \brief (DACC_CDR[2]) Data to Convert for channel 1 */ +#define DACC_CDR_DATA1(value) ((DACC_CDR_DATA1_Msk & ((value) << DACC_CDR_DATA1_Pos))) +/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */ +#define DACC_IER_TXRDY0 (0x1u << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable of channel 0 */ +#define DACC_IER_TXRDY1 (0x1u << 1) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable of channel 1 */ +#define DACC_IER_EOC0 (0x1u << 4) /**< \brief (DACC_IER) End of Conversion Interrupt Enable of channel 0 */ +#define DACC_IER_EOC1 (0x1u << 5) /**< \brief (DACC_IER) End of Conversion Interrupt Enable of channel 1 */ +#define DACC_IER_ENDTX0 (0x1u << 8) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable of channel 0 */ +#define DACC_IER_ENDTX1 (0x1u << 9) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable of channel 1 */ +#define DACC_IER_TXBUFE0 (0x1u << 12) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable of channel 0 */ +#define DACC_IER_TXBUFE1 (0x1u << 13) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable of channel 1 */ +/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */ +#define DACC_IDR_TXRDY0 (0x1u << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable of channel 0 */ +#define DACC_IDR_TXRDY1 (0x1u << 1) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable of channel 1 */ +#define DACC_IDR_EOC0 (0x1u << 4) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable of channel 0 */ +#define DACC_IDR_EOC1 (0x1u << 5) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable of channel 1 */ +#define DACC_IDR_ENDTX0 (0x1u << 8) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable of channel 0 */ +#define DACC_IDR_ENDTX1 (0x1u << 9) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable of channel 1 */ +#define DACC_IDR_TXBUFE0 (0x1u << 12) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable of channel 0 */ +#define DACC_IDR_TXBUFE1 (0x1u << 13) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable of channel 1 */ +/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */ +#define DACC_IMR_TXRDY0 (0x1u << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask of channel 0 */ +#define DACC_IMR_TXRDY1 (0x1u << 1) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask of channel 1 */ +#define DACC_IMR_EOC0 (0x1u << 4) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask of channel 0 */ +#define DACC_IMR_EOC1 (0x1u << 5) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask of channel 1 */ +#define DACC_IMR_ENDTX0 (0x1u << 8) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask of channel 0 */ +#define DACC_IMR_ENDTX1 (0x1u << 9) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask of channel 1 */ +#define DACC_IMR_TXBUFE0 (0x1u << 12) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask of channel 0 */ +#define DACC_IMR_TXBUFE1 (0x1u << 13) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask of channel 1 */ +/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */ +#define DACC_ISR_TXRDY0 (0x1u << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag of channel 0 */ +#define DACC_ISR_TXRDY1 (0x1u << 1) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag of channel 1 */ +#define DACC_ISR_EOC0 (0x1u << 4) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag of channel 0 */ +#define DACC_ISR_EOC1 (0x1u << 5) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag of channel 1 */ +#define DACC_ISR_ENDTX0 (0x1u << 8) /**< \brief (DACC_ISR) End of DMA Interrupt Flag of channel 0 */ +#define DACC_ISR_ENDTX1 (0x1u << 9) /**< \brief (DACC_ISR) End of DMA Interrupt Flag of channel 1 */ +#define DACC_ISR_TXBUFE0 (0x1u << 12) /**< \brief (DACC_ISR) Transmit Buffer Empty of channel 0 */ +#define DACC_ISR_TXBUFE1 (0x1u << 13) /**< \brief (DACC_ISR) Transmit Buffer Empty of channel 1 */ +/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */ +#define DACC_ACR_IBCTLCH0_Pos 0 +#define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */ +#define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos))) +#define DACC_ACR_IBCTLCH1_Pos 2 +#define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */ +#define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos))) +/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protection Mode register -------- */ +#define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protection Enable */ +#define DACC_WPMR_WPKEY_Pos 8 +#define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect Key */ +#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos))) +#define DACC_WPMR_WPKEY_PASSWD (0x444143u << 8) /**< \brief (DACC_WPMR) Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0. */ +/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protection Status register -------- */ +#define DACC_WPSR_WPVS (0x1u << 0) /**< \brief (DACC_WPSR) Write Protection Violation Status */ +#define DACC_WPSR_WPVSRC_Pos 8 +#define DACC_WPSR_WPVSRC_Msk (0xffu << DACC_WPSR_WPVSRC_Pos) /**< \brief (DACC_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAMV71_DACC_COMPONENT_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_efc.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_efc.h new file mode 100644 index 00000000..984492f7 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_efc.h @@ -0,0 +1,118 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_EFC_COMPONENT_ +#define _SAMV71_EFC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_EFC Embedded Flash Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Efc hardware registers */ +typedef struct { + __IO uint32_t EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */ + __O uint32_t EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */ + __I uint32_t EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */ + __I uint32_t EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */ + __I uint32_t Reserved1[1]; + __I uint32_t EEFC_VERSION; /**< \brief (Efc Offset: 0x14) EEFC Version Register */ + __I uint32_t Reserved2[51]; + __IO uint32_t EEFC_WPMR; /**< \brief (Efc Offset: 0xE4) Write Protection Mode Register */ +} Efc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */ +#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Flash Ready Interrupt Enable */ +#define EEFC_FMR_FWS_Pos 8 +#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */ +#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos))) +#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */ +#define EEFC_FMR_CLOE (0x1u << 26) /**< \brief (EEFC_FMR) Code Loop Optimization Enable */ +/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */ +#define EEFC_FCR_FCMD_Pos 0 +#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */ +#define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos))) +#define EEFC_FCR_FCMD_GETD (0x0u << 0) /**< \brief (EEFC_FCR) Get Flash descriptor */ +#define EEFC_FCR_FCMD_WP (0x1u << 0) /**< \brief (EEFC_FCR) Write page */ +#define EEFC_FCR_FCMD_WPL (0x2u << 0) /**< \brief (EEFC_FCR) Write page and lock */ +#define EEFC_FCR_FCMD_EWP (0x3u << 0) /**< \brief (EEFC_FCR) Erase page and write page */ +#define EEFC_FCR_FCMD_EWPL (0x4u << 0) /**< \brief (EEFC_FCR) Erase page and write page then lock */ +#define EEFC_FCR_FCMD_EA (0x5u << 0) /**< \brief (EEFC_FCR) Erase all */ +#define EEFC_FCR_FCMD_EPA (0x7u << 0) /**< \brief (EEFC_FCR) Erase pages */ +#define EEFC_FCR_FCMD_SLB (0x8u << 0) /**< \brief (EEFC_FCR) Set lock bit */ +#define EEFC_FCR_FCMD_CLB (0x9u << 0) /**< \brief (EEFC_FCR) Clear lock bit */ +#define EEFC_FCR_FCMD_GLB (0xAu << 0) /**< \brief (EEFC_FCR) Get lock bit */ +#define EEFC_FCR_FCMD_SGPB (0xBu << 0) /**< \brief (EEFC_FCR) Set GPNVM bit */ +#define EEFC_FCR_FCMD_CGPB (0xCu << 0) /**< \brief (EEFC_FCR) Clear GPNVM bit */ +#define EEFC_FCR_FCMD_GGPB (0xDu << 0) /**< \brief (EEFC_FCR) Get GPNVM bit */ +#define EEFC_FCR_FCMD_STUI (0xEu << 0) /**< \brief (EEFC_FCR) Start read unique identifier */ +#define EEFC_FCR_FCMD_SPUI (0xFu << 0) /**< \brief (EEFC_FCR) Stop read unique identifier */ +#define EEFC_FCR_FCMD_GCALB (0x10u << 0) /**< \brief (EEFC_FCR) Get CALIB bit */ +#define EEFC_FCR_FCMD_ES (0x11u << 0) /**< \brief (EEFC_FCR) Erase sector */ +#define EEFC_FCR_FCMD_WUS (0x12u << 0) /**< \brief (EEFC_FCR) Write user signature */ +#define EEFC_FCR_FCMD_EUS (0x13u << 0) /**< \brief (EEFC_FCR) Erase user signature */ +#define EEFC_FCR_FCMD_STUS (0x14u << 0) /**< \brief (EEFC_FCR) Start read user signature */ +#define EEFC_FCR_FCMD_SPUS (0x15u << 0) /**< \brief (EEFC_FCR) Stop read user signature */ +#define EEFC_FCR_FARG_Pos 8 +#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */ +#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos))) +#define EEFC_FCR_FKEY_Pos 24 +#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */ +#define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos))) +#define EEFC_FCR_FKEY_PASSWD (0x5Au << 24) /**< \brief (EEFC_FCR) The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. */ +/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */ +#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status (cleared when Flash is busy) */ +#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status (cleared on read or by writing EEFC_FCR) */ +#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status (cleared on read) */ +#define EEFC_FSR_FLERR (0x1u << 3) /**< \brief (EEFC_FSR) Flash Error Status (cleared when a programming operation starts) */ +#define EEFC_FSR_UECCELSB (0x1u << 16) /**< \brief (EEFC_FSR) Unique ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) */ +#define EEFC_FSR_MECCELSB (0x1u << 17) /**< \brief (EEFC_FSR) Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) */ +#define EEFC_FSR_UECCEMSB (0x1u << 18) /**< \brief (EEFC_FSR) Unique ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) */ +#define EEFC_FSR_MECCEMSB (0x1u << 19) /**< \brief (EEFC_FSR) Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) */ +/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */ +#define EEFC_FRR_FVALUE_Pos 0 +#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */ +/* -------- EEFC_VERSION : (EFC Offset: 0x14) EEFC Version Register -------- */ +#define EEFC_VERSION_VERSION_Pos 0 +#define EEFC_VERSION_VERSION_Msk (0xfffu << EEFC_VERSION_VERSION_Pos) /**< \brief (EEFC_VERSION) Version of the Hardware Module */ +#define EEFC_VERSION_MFN_Pos 16 +#define EEFC_VERSION_MFN_Msk (0x7u << EEFC_VERSION_MFN_Pos) /**< \brief (EEFC_VERSION) Metal Fix Number */ +/* -------- EEFC_WPMR : (EFC Offset: 0xE4) Write Protection Mode Register -------- */ +#define EEFC_WPMR_WPEN (0x1u << 0) /**< \brief (EEFC_WPMR) Write Protection Enable */ +#define EEFC_WPMR_WPKEY_Pos 8 +#define EEFC_WPMR_WPKEY_Msk (0xffffffu << EEFC_WPMR_WPKEY_Pos) /**< \brief (EEFC_WPMR) Write Protection Key */ +#define EEFC_WPMR_WPKEY(value) ((EEFC_WPMR_WPKEY_Msk & ((value) << EEFC_WPMR_WPKEY_Pos))) +#define EEFC_WPMR_WPKEY_PASSWD (0x454643u << 8) /**< \brief (EEFC_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAMV71_EFC_COMPONENT_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_gmac.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_gmac.h new file mode 100644 index 00000000..152b504f --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_gmac.h @@ -0,0 +1,832 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_GMAC_COMPONENT_ +#define _SAMV71_GMAC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Gigabit Ethernet MAC */ +/* ============================================================================= */ +/** \addtogroup SAMV71_GMAC Gigabit Ethernet MAC */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief GmacSa hardware registers */ +typedef struct { + __IO uint32_t GMAC_SAB; /**< \brief (GmacSa Offset: 0x0) Specific Address 1 Bottom Register */ + __IO uint32_t GMAC_SAT; /**< \brief (GmacSa Offset: 0x4) Specific Address 1 Top Register */ +} GmacSa; + +/** \brief GmacSt2Compare hardware registers */ +typedef struct { + __IO uint32_t GMAC_ST2COM0; /**< \brief 31:16 - Compare Value. 15:0 - Mask Value. */ + __IO uint32_t GMAC_ST2COM1; /**< \brief 31:9 - Reserved; 8:7 - Offset location in frame; 6:0 Offset value in bytes */ +} GmacSt2Compare; + +/** \brief Gmac hardware registers */ +#define GMACSA_NUMBER 4 +#define GMACST2COMPARE_NUMBER 24 +typedef struct { + __IO uint32_t GMAC_NCR; /**< \brief (Gmac Offset: 0x000) Network Control Register */ + __IO uint32_t GMAC_NCFGR; /**< \brief (Gmac Offset: 0x004) Network Configuration Register */ + __I uint32_t GMAC_NSR; /**< \brief (Gmac Offset: 0x008) Network Status Register */ + __IO uint32_t GMAC_UR; /**< \brief (Gmac Offset: 0x00C) User Register */ + __IO uint32_t GMAC_DCFGR; /**< \brief (Gmac Offset: 0x010) DMA Configuration Register */ + __IO uint32_t GMAC_TSR; /**< \brief (Gmac Offset: 0x014) Transmit Status Register */ + __IO uint32_t GMAC_RBQB; /**< \brief (Gmac Offset: 0x018) Receive Buffer Queue Base Address Register */ + __IO uint32_t GMAC_TBQB; /**< \brief (Gmac Offset: 0x01C) Transmit Buffer Queue Base Address Register */ + __IO uint32_t GMAC_RSR; /**< \brief (Gmac Offset: 0x020) Receive Status Register */ + __I uint32_t GMAC_ISR; /**< \brief (Gmac Offset: 0x024) Interrupt Status Register */ + __O uint32_t GMAC_IER; /**< \brief (Gmac Offset: 0x028) Interrupt Enable Register */ + __O uint32_t GMAC_IDR; /**< \brief (Gmac Offset: 0x02C) Interrupt Disable Register */ + __IO uint32_t GMAC_IMR; /**< \brief (Gmac Offset: 0x030) Interrupt Mask Register */ + __IO uint32_t GMAC_MAN; /**< \brief (Gmac Offset: 0x034) PHY Maintenance Register */ + __I uint32_t GMAC_RPQ; /**< \brief (Gmac Offset: 0x038) Received Pause Quantum Register */ + __IO uint32_t GMAC_TPQ; /**< \brief (Gmac Offset: 0x03C) Transmit Pause Quantum Register */ + __IO uint32_t GMAC_TPSF; /**< \brief (Gmac Offset: 0x040) TX Partial Store and Forward Register */ + __IO uint32_t GMAC_RPSF; /**< \brief (Gmac Offset: 0x044) RX Partial Store and Forward Register */ + __IO uint32_t GMAC_RJFML; /**< \brief (Gmac Offset: 0x048) RX Jumbo Frame Max Length Register */ + __I uint32_t Reserved1[13]; + __IO uint32_t GMAC_HRB; /**< \brief (Gmac Offset: 0x080) Hash Register Bottom */ + __IO uint32_t GMAC_HRT; /**< \brief (Gmac Offset: 0x084) Hash Register Top */ + GmacSa GMAC_SA[GMACSA_NUMBER]; /**< \brief (Gmac Offset: 0x088) 1 .. 4 */ + __IO uint32_t GMAC_TIDM1; /**< \brief (Gmac Offset: 0x0A8) Type ID Match 1 Register */ + __IO uint32_t GMAC_TIDM2; /**< \brief (Gmac Offset: 0x0AC) Type ID Match 2 Register */ + __IO uint32_t GMAC_TIDM3; /**< \brief (Gmac Offset: 0x0B0) Type ID Match 3 Register */ + __IO uint32_t GMAC_TIDM4; /**< \brief (Gmac Offset: 0x0B4) Type ID Match 4 Register */ + __IO uint32_t GMAC_WOL; /**< \brief (Gmac Offset: 0x0B8) Wake on LAN Register */ + __IO uint32_t GMAC_IPGS; /**< \brief (Gmac Offset: 0x0BC) IPG Stretch Register */ + __IO uint32_t GMAC_SVLAN; /**< \brief (Gmac Offset: 0x0C0) Stacked VLAN Register */ + __IO uint32_t GMAC_TPFCP; /**< \brief (Gmac Offset: 0x0C4) Transmit PFC Pause Register */ + __IO uint32_t GMAC_SAMB1; /**< \brief (Gmac Offset: 0x0C8) Specific Address 1 Mask Bottom Register */ + __IO uint32_t GMAC_SAMT1; /**< \brief (Gmac Offset: 0x0CC) Specific Address 1 Mask Top Register */ + __I uint32_t Reserved2[3]; + __IO uint32_t GMAC_NSC; /**< \brief (Gmac Offset: 0x0DC) 1588 Timer Nanosecond Comparison Register */ + __IO uint32_t GMAC_SCL; /**< \brief (Gmac Offset: 0x0E0) 1588 Timer Second Comparison Low Register */ + __IO uint32_t GMAC_SCH; /**< \brief (Gmac Offset: 0x0E4) 1588 Timer Second Comparison High Register */ + __I uint32_t GMAC_EFTSH; /**< \brief (Gmac Offset: 0x0E8) PTP Event Frame Transmitted Seconds High Register */ + __I uint32_t GMAC_EFRSH; /**< \brief (Gmac Offset: 0x0EC) PTP Event Frame Received Seconds High Register */ + __I uint32_t GMAC_PEFTSH; /**< \brief (Gmac Offset: 0x0F0) PTP Peer Event Frame Transmitted Seconds High Register */ + __I uint32_t GMAC_PEFRSH; /**< \brief (Gmac Offset: 0x0F4) PTP Peer Event Frame Received Seconds High Register */ + __I uint32_t Reserved3[2]; + __I uint32_t GMAC_OTLO; /**< \brief (Gmac Offset: 0x100) Octets Transmitted Low Register */ + __I uint32_t GMAC_OTHI; /**< \brief (Gmac Offset: 0x104) Octets Transmitted High Register */ + __I uint32_t GMAC_FT; /**< \brief (Gmac Offset: 0x108) Frames Transmitted Register */ + __I uint32_t GMAC_BCFT; /**< \brief (Gmac Offset: 0x10C) Broadcast Frames Transmitted Register */ + __I uint32_t GMAC_MFT; /**< \brief (Gmac Offset: 0x110) Multicast Frames Transmitted Register */ + __I uint32_t GMAC_PFT; /**< \brief (Gmac Offset: 0x114) Pause Frames Transmitted Register */ + __I uint32_t GMAC_BFT64; /**< \brief (Gmac Offset: 0x118) 64 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT127; /**< \brief (Gmac Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT255; /**< \brief (Gmac Offset: 0x120) 128 to 255 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT511; /**< \brief (Gmac Offset: 0x124) 256 to 511 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT1023; /**< \brief (Gmac Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT1518; /**< \brief (Gmac Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register */ + __I uint32_t GMAC_GTBFT1518; /**< \brief (Gmac Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TUR; /**< \brief (Gmac Offset: 0x134) Transmit Underruns Register */ + __I uint32_t GMAC_SCF; /**< \brief (Gmac Offset: 0x138) Single Collision Frames Register */ + __I uint32_t GMAC_MCF; /**< \brief (Gmac Offset: 0x13C) Multiple Collision Frames Register */ + __I uint32_t GMAC_EC; /**< \brief (Gmac Offset: 0x140) Excessive Collisions Register */ + __I uint32_t GMAC_LC; /**< \brief (Gmac Offset: 0x144) Late Collisions Register */ + __I uint32_t GMAC_DTF; /**< \brief (Gmac Offset: 0x148) Deferred Transmission Frames Register */ + __I uint32_t GMAC_CSE; /**< \brief (Gmac Offset: 0x14C) Carrier Sense Errors Register Register */ + __I uint32_t GMAC_ORLO; /**< \brief (Gmac Offset: 0x150) Octets Received Low Received Register */ + __I uint32_t GMAC_ORHI; /**< \brief (Gmac Offset: 0x154) Octets Received High Received Register */ + __I uint32_t GMAC_FR; /**< \brief (Gmac Offset: 0x158) Frames Received Register */ + __I uint32_t GMAC_BCFR; /**< \brief (Gmac Offset: 0x15C) Broadcast Frames Received Register */ + __I uint32_t GMAC_MFR; /**< \brief (Gmac Offset: 0x160) Multicast Frames Received Register */ + __I uint32_t GMAC_PFR; /**< \brief (Gmac Offset: 0x164) Pause Frames Received Register */ + __I uint32_t GMAC_BFR64; /**< \brief (Gmac Offset: 0x168) 64 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR127; /**< \brief (Gmac Offset: 0x16C) 65 to 127 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR255; /**< \brief (Gmac Offset: 0x170) 128 to 255 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR511; /**< \brief (Gmac Offset: 0x174) 256 to 511 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR1023; /**< \brief (Gmac Offset: 0x178) 512 to 1023 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR1518; /**< \brief (Gmac Offset: 0x17C) 1024 to 1518 Byte Frames Received Register */ + __I uint32_t GMAC_TMXBFR; /**< \brief (Gmac Offset: 0x180) 1519 to Maximum Byte Frames Received Register */ + __I uint32_t GMAC_UFR; /**< \brief (Gmac Offset: 0x184) Undersize Frames Received Register */ + __I uint32_t GMAC_OFR; /**< \brief (Gmac Offset: 0x188) Oversize Frames Received Register */ + __I uint32_t GMAC_JR; /**< \brief (Gmac Offset: 0x18C) Jabbers Received Register */ + __I uint32_t GMAC_FCSE; /**< \brief (Gmac Offset: 0x190) Frame Check Sequence Errors Register */ + __I uint32_t GMAC_LFFE; /**< \brief (Gmac Offset: 0x194) Length Field Frame Errors Register */ + __I uint32_t GMAC_RSE; /**< \brief (Gmac Offset: 0x198) Receive Symbol Errors Register */ + __I uint32_t GMAC_AE; /**< \brief (Gmac Offset: 0x19C) Alignment Errors Register */ + __I uint32_t GMAC_RRE; /**< \brief (Gmac Offset: 0x1A0) Receive Resource Errors Register */ + __I uint32_t GMAC_ROE; /**< \brief (Gmac Offset: 0x1A4) Receive Overrun Register */ + __I uint32_t GMAC_IHCE; /**< \brief (Gmac Offset: 0x1A8) IP Header Checksum Errors Register */ + __I uint32_t GMAC_TCE; /**< \brief (Gmac Offset: 0x1AC) TCP Checksum Errors Register */ + __I uint32_t GMAC_UCE; /**< \brief (Gmac Offset: 0x1B0) UDP Checksum Errors Register */ + __I uint32_t Reserved4[2]; + __IO uint32_t GMAC_TISUBN; /**< \brief (Gmac Offset: 0x1BC) 1588 Timer Increment Sub-nanoseconds Register */ + __IO uint32_t GMAC_TSH; /**< \brief (Gmac Offset: 0x1C0) 1588 Timer Seconds High Register */ + __I uint32_t Reserved5[3]; + __IO uint32_t GMAC_TSL; /**< \brief (Gmac Offset: 0x1D0) 1588 Timer Seconds Low Register */ + __IO uint32_t GMAC_TN; /**< \brief (Gmac Offset: 0x1D4) 1588 Timer Nanoseconds Register */ + __O uint32_t GMAC_TA; /**< \brief (Gmac Offset: 0x1D8) 1588 Timer Adjust Register */ + __IO uint32_t GMAC_TI; /**< \brief (Gmac Offset: 0x1DC) 1588 Timer Increment Register */ + __I uint32_t GMAC_EFTSL; /**< \brief (Gmac Offset: 0x1E0) PTP Event Frame Transmitted Seconds Low Register */ + __I uint32_t GMAC_EFTN; /**< \brief (Gmac Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds Register */ + __I uint32_t GMAC_EFRSL; /**< \brief (Gmac Offset: 0x1E8) PTP Event Frame Received Seconds Low Register */ + __I uint32_t GMAC_EFRN; /**< \brief (Gmac Offset: 0x1EC) PTP Event Frame Received Nanoseconds Register */ + __I uint32_t GMAC_PEFTSL; /**< \brief (Gmac Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds Low Register */ + __I uint32_t GMAC_PEFTN; /**< \brief (Gmac Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds Register */ + __I uint32_t GMAC_PEFRSL; /**< \brief (Gmac Offset: 0x1F8) PTP Peer Event Frame Received Seconds Low Register */ + __I uint32_t GMAC_PEFRN; /**< \brief (Gmac Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds Register */ + __I uint32_t Reserved6[128]; + __I uint32_t GMAC_ISRPQ[3]; /**< \brief (Gmac Offset: 0x400) Interrupt Status Register Priority Queue (index = 1) */ + __I uint32_t Reserved7[13]; + __IO uint32_t GMAC_TBQBAPQ[3]; /**< \brief (Gmac Offset: 0x440) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) */ + __I uint32_t Reserved8[13]; + __IO uint32_t GMAC_RBQBAPQ[3]; /**< \brief (Gmac Offset: 0x480) Receive Buffer Queue Base Address Register Priority Queue (index = 1) */ + __I uint32_t Reserved9[5]; + __IO uint32_t GMAC_RBSRPQ[3]; /**< \brief (Gmac Offset: 0x4A0) Receive Buffer Size Register Priority Queue (index = 1) */ + __I uint32_t Reserved10[4]; + __IO uint32_t GMAC_CBSCR; /**< \brief (Gmac Offset: 0x4BC) Credit-Based Shaping Control Register */ + __IO uint32_t GMAC_CBSISQA; /**< \brief (Gmac Offset: 0x4C0) Credit-Based Shaping IdleSlope Register for Queue A */ + __IO uint32_t GMAC_CBSISQB; /**< \brief (Gmac Offset: 0x4C4) Credit-Based Shaping IdleSlope Register for Queue B */ + __I uint32_t Reserved11[14]; + __IO uint32_t GMAC_ST1RPQ[4]; /**< \brief (Gmac Offset: 0x500) Screening Type 1 Register Priority Queue (index = 0) */ + __I uint32_t Reserved12[12]; + __IO uint32_t GMAC_ST2RPQ[8]; /**< \brief (Gmac Offset: 0x540) Screening Type 2 Register Priority Queue (index = 0) */ + __I uint32_t Reserved13[12]; + __I uint32_t Reserved14[28]; + __O uint32_t GMAC_IERPQ[3]; /**< \brief (Gmac Offset: 0x600) Interrupt Enable Register Priority Queue (index = 1) */ + __I uint32_t Reserved15[5]; + __O uint32_t GMAC_IDRPQ[3]; /**< \brief (Gmac Offset: 0x620) Interrupt Disable Register Priority Queue (index = 1) */ + __I uint32_t Reserved16[5]; + __IO uint32_t GMAC_IMRPQ[3]; /**< \brief (Gmac Offset: 0x640) Interrupt Mask Register Priority Queue (index = 1) */ + __I uint32_t Reserved17[37]; + __IO uint32_t GMAC_ST2ER[4]; /**< \brief (Gmac Offset: 0x6E0) Screening Type 2 Ethertype Register (index = 0) */ + __I uint32_t Reserved18[4]; + __IO GmacSt2Compare GMAC_ST2COMP[GMACST2COMPARE_NUMBER];/**< \brief (Gmac Offset: 0x700) Screener Type 2 Compare Registers */ +} Gmac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- GMAC_NCR : (GMAC Offset: 0x000) Network Control Register -------- */ +#define GMAC_NCR_LBL (0x1u << 1) /**< \brief (GMAC_NCR) Loop Back Local */ +#define GMAC_NCR_RXEN (0x1u << 2) /**< \brief (GMAC_NCR) Receive Enable */ +#define GMAC_NCR_TXEN (0x1u << 3) /**< \brief (GMAC_NCR) Transmit Enable */ +#define GMAC_NCR_MPE (0x1u << 4) /**< \brief (GMAC_NCR) Management Port Enable */ +#define GMAC_NCR_CLRSTAT (0x1u << 5) /**< \brief (GMAC_NCR) Clear Statistics Registers */ +#define GMAC_NCR_INCSTAT (0x1u << 6) /**< \brief (GMAC_NCR) Increment Statistics Registers */ +#define GMAC_NCR_WESTAT (0x1u << 7) /**< \brief (GMAC_NCR) Write Enable for Statistics Registers */ +#define GMAC_NCR_BP (0x1u << 8) /**< \brief (GMAC_NCR) Back pressure */ +#define GMAC_NCR_TSTART (0x1u << 9) /**< \brief (GMAC_NCR) Start Transmission */ +#define GMAC_NCR_THALT (0x1u << 10) /**< \brief (GMAC_NCR) Transmit Halt */ +#define GMAC_NCR_TXPF (0x1u << 11) /**< \brief (GMAC_NCR) Transmit Pause Frame */ +#define GMAC_NCR_TXZQPF (0x1u << 12) /**< \brief (GMAC_NCR) Transmit Zero Quantum Pause Frame */ +#define GMAC_NCR_SRTSM (0x1u << 15) /**< \brief (GMAC_NCR) Store Receive Time Stamp to Memory */ +#define GMAC_NCR_ENPBPR (0x1u << 16) /**< \brief (GMAC_NCR) Enable PFC Priority-based Pause Reception */ +#define GMAC_NCR_TXPBPF (0x1u << 17) /**< \brief (GMAC_NCR) Transmit PFC Priority-based Pause Frame */ +#define GMAC_NCR_FNP (0x1u << 18) /**< \brief (GMAC_NCR) Flush Next Packet */ +/* -------- GMAC_NCFGR : (GMAC Offset: 0x004) Network Configuration Register -------- */ +#define GMAC_NCFGR_SPD (0x1u << 0) /**< \brief (GMAC_NCFGR) Speed */ +#define GMAC_NCFGR_FD (0x1u << 1) /**< \brief (GMAC_NCFGR) Full Duplex */ +#define GMAC_NCFGR_DNVLAN (0x1u << 2) /**< \brief (GMAC_NCFGR) Discard Non-VLAN FRAMES */ +#define GMAC_NCFGR_JFRAME (0x1u << 3) /**< \brief (GMAC_NCFGR) Jumbo Frame Size */ +#define GMAC_NCFGR_CAF (0x1u << 4) /**< \brief (GMAC_NCFGR) Copy All Frames */ +#define GMAC_NCFGR_NBC (0x1u << 5) /**< \brief (GMAC_NCFGR) No Broadcast */ +#define GMAC_NCFGR_MTIHEN (0x1u << 6) /**< \brief (GMAC_NCFGR) Multicast Hash Enable */ +#define GMAC_NCFGR_UNIHEN (0x1u << 7) /**< \brief (GMAC_NCFGR) Unicast Hash Enable */ +#define GMAC_NCFGR_MAXFS (0x1u << 8) /**< \brief (GMAC_NCFGR) 1536 Maximum Frame Size */ +#define GMAC_NCFGR_RTY (0x1u << 12) /**< \brief (GMAC_NCFGR) Retry Test */ +#define GMAC_NCFGR_PEN (0x1u << 13) /**< \brief (GMAC_NCFGR) Pause Enable */ +#define GMAC_NCFGR_RXBUFO_Pos 14 +#define GMAC_NCFGR_RXBUFO_Msk (0x3u << GMAC_NCFGR_RXBUFO_Pos) /**< \brief (GMAC_NCFGR) Receive Buffer Offset */ +#define GMAC_NCFGR_RXBUFO(value) ((GMAC_NCFGR_RXBUFO_Msk & ((value) << GMAC_NCFGR_RXBUFO_Pos))) +#define GMAC_NCFGR_LFERD (0x1u << 16) /**< \brief (GMAC_NCFGR) Length Field Error Frame Discard */ +#define GMAC_NCFGR_RFCS (0x1u << 17) /**< \brief (GMAC_NCFGR) Remove FCS */ +#define GMAC_NCFGR_CLK_Pos 18 +#define GMAC_NCFGR_CLK_Msk (0x7u << GMAC_NCFGR_CLK_Pos) /**< \brief (GMAC_NCFGR) MDC CLock Division */ +#define GMAC_NCFGR_CLK(value) ((GMAC_NCFGR_CLK_Msk & ((value) << GMAC_NCFGR_CLK_Pos))) +#define GMAC_NCFGR_CLK_MCK_8 (0x0u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 8 (MCK up to 20 MHz) */ +#define GMAC_NCFGR_CLK_MCK_16 (0x1u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 16 (MCK up to 40 MHz) */ +#define GMAC_NCFGR_CLK_MCK_32 (0x2u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 32 (MCK up to 80 MHz) */ +#define GMAC_NCFGR_CLK_MCK_48 (0x3u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 48 (MCK up to 120 MHz) */ +#define GMAC_NCFGR_CLK_MCK_64 (0x4u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 64 (MCK up to 160 MHz) */ +#define GMAC_NCFGR_CLK_MCK_96 (0x5u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 96 (MCK up to 240 MHz) */ +#define GMAC_NCFGR_DBW_Pos 21 +#define GMAC_NCFGR_DBW_Msk (0x3u << GMAC_NCFGR_DBW_Pos) /**< \brief (GMAC_NCFGR) Data Bus Width */ +#define GMAC_NCFGR_DBW(value) ((GMAC_NCFGR_DBW_Msk & ((value) << GMAC_NCFGR_DBW_Pos))) +#define GMAC_NCFGR_DCPF (0x1u << 23) /**< \brief (GMAC_NCFGR) Disable Copy of Pause Frames */ +#define GMAC_NCFGR_RXCOEN (0x1u << 24) /**< \brief (GMAC_NCFGR) Receive Checksum Offload Enable */ +#define GMAC_NCFGR_EFRHD (0x1u << 25) /**< \brief (GMAC_NCFGR) Enable Frames Received in Half Duplex */ +#define GMAC_NCFGR_IRXFCS (0x1u << 26) /**< \brief (GMAC_NCFGR) Ignore RX FCS */ +#define GMAC_NCFGR_IPGSEN (0x1u << 28) /**< \brief (GMAC_NCFGR) IP Stretch Enable */ +#define GMAC_NCFGR_RXBP (0x1u << 29) /**< \brief (GMAC_NCFGR) Receive Bad Preamble */ +#define GMAC_NCFGR_IRXER (0x1u << 30) /**< \brief (GMAC_NCFGR) Ignore IPG GRXER */ +/* -------- GMAC_NSR : (GMAC Offset: 0x008) Network Status Register -------- */ +#define GMAC_NSR_MDIO (0x1u << 1) /**< \brief (GMAC_NSR) MDIO Input Status */ +#define GMAC_NSR_IDLE (0x1u << 2) /**< \brief (GMAC_NSR) PHY Management Logic Idle */ +/* -------- GMAC_UR : (GMAC Offset: 0x00C) User Register -------- */ +#define GMAC_UR_RMII (0x1u << 0) /**< \brief (GMAC_UR) Reduced MII Mode */ +/* -------- GMAC_DCFGR : (GMAC Offset: 0x010) DMA Configuration Register -------- */ +#define GMAC_DCFGR_FBLDO_Pos 0 +#define GMAC_DCFGR_FBLDO_Msk (0x1fu << GMAC_DCFGR_FBLDO_Pos) /**< \brief (GMAC_DCFGR) Fixed Burst Length for DMA Data Operations: */ +#define GMAC_DCFGR_FBLDO(value) ((GMAC_DCFGR_FBLDO_Msk & ((value) << GMAC_DCFGR_FBLDO_Pos))) +#define GMAC_DCFGR_FBLDO_SINGLE (0x1u << 0) /**< \brief (GMAC_DCFGR) 00001: Always use SINGLE AHB bursts */ +#define GMAC_DCFGR_FBLDO_INCR4 (0x4u << 0) /**< \brief (GMAC_DCFGR) 001xx: Attempt to use INCR4 AHB bursts (Default) */ +#define GMAC_DCFGR_FBLDO_INCR8 (0x8u << 0) /**< \brief (GMAC_DCFGR) 01xxx: Attempt to use INCR8 AHB bursts */ +#define GMAC_DCFGR_FBLDO_INCR16 (0x10u << 0) /**< \brief (GMAC_DCFGR) 1xxxx: Attempt to use INCR16 AHB bursts */ +#define GMAC_DCFGR_ESMA (0x1u << 6) /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Management Descriptor Accesses */ +#define GMAC_DCFGR_ESPA (0x1u << 7) /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Packet Data Accesses */ +#define GMAC_DCFGR_RXBMS_Pos 8 +#define GMAC_DCFGR_RXBMS_Msk (0x3u << GMAC_DCFGR_RXBMS_Pos) /**< \brief (GMAC_DCFGR) Receiver Packet Buffer Memory Size Select */ +#define GMAC_DCFGR_RXBMS(value) ((GMAC_DCFGR_RXBMS_Msk & ((value) << GMAC_DCFGR_RXBMS_Pos))) +#define GMAC_DCFGR_RXBMS_EIGHTH (0x0u << 8) /**< \brief (GMAC_DCFGR) 4/8 Kbyte Memory Size */ +#define GMAC_DCFGR_RXBMS_QUARTER (0x1u << 8) /**< \brief (GMAC_DCFGR) 4/4 Kbytes Memory Size */ +#define GMAC_DCFGR_RXBMS_HALF (0x2u << 8) /**< \brief (GMAC_DCFGR) 4/2 Kbytes Memory Size */ +#define GMAC_DCFGR_RXBMS_FULL (0x3u << 8) /**< \brief (GMAC_DCFGR) 4 Kbytes Memory Size */ +#define GMAC_DCFGR_TXPBMS (0x1u << 10) /**< \brief (GMAC_DCFGR) Transmitter Packet Buffer Memory Size Select */ +#define GMAC_DCFGR_TXCOEN (0x1u << 11) /**< \brief (GMAC_DCFGR) Transmitter Checksum Generation Offload Enable */ +#define GMAC_DCFGR_DRBS_Pos 16 +#define GMAC_DCFGR_DRBS_Msk (0xffu << GMAC_DCFGR_DRBS_Pos) /**< \brief (GMAC_DCFGR) DMA Receive Buffer Size */ +#define GMAC_DCFGR_DRBS(value) ((GMAC_DCFGR_DRBS_Msk & ((value) << GMAC_DCFGR_DRBS_Pos))) +#define GMAC_DCFGR_DDRP (0x1u << 24) /**< \brief (GMAC_DCFGR) DMA Discard Receive Packets */ +/* -------- GMAC_TSR : (GMAC Offset: 0x014) Transmit Status Register -------- */ +#define GMAC_TSR_UBR (0x1u << 0) /**< \brief (GMAC_TSR) Used Bit Read */ +#define GMAC_TSR_COL (0x1u << 1) /**< \brief (GMAC_TSR) Collision Occurred */ +#define GMAC_TSR_RLE (0x1u << 2) /**< \brief (GMAC_TSR) Retry Limit Exceeded */ +#define GMAC_TSR_TXGO (0x1u << 3) /**< \brief (GMAC_TSR) Transmit Go */ +#define GMAC_TSR_TFC (0x1u << 4) /**< \brief (GMAC_TSR) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_TSR_TXCOMP (0x1u << 5) /**< \brief (GMAC_TSR) Transmit Complete */ +#define GMAC_TSR_HRESP (0x1u << 8) /**< \brief (GMAC_TSR) HRESP Not OK */ +/* -------- GMAC_RBQB : (GMAC Offset: 0x018) Receive Buffer Queue Base Address Register -------- */ +#define GMAC_RBQB_ADDR_Pos 2 +#define GMAC_RBQB_ADDR_Msk (0x3fffffffu << GMAC_RBQB_ADDR_Pos) /**< \brief (GMAC_RBQB) Receive Buffer Queue Base Address */ +#define GMAC_RBQB_ADDR(value) ((GMAC_RBQB_ADDR_Msk & ((value) << GMAC_RBQB_ADDR_Pos))) +/* -------- GMAC_TBQB : (GMAC Offset: 0x01C) Transmit Buffer Queue Base Address Register -------- */ +#define GMAC_TBQB_ADDR_Pos 2 +#define GMAC_TBQB_ADDR_Msk (0x3fffffffu << GMAC_TBQB_ADDR_Pos) /**< \brief (GMAC_TBQB) Transmit Buffer Queue Base Address */ +#define GMAC_TBQB_ADDR(value) ((GMAC_TBQB_ADDR_Msk & ((value) << GMAC_TBQB_ADDR_Pos))) +/* -------- GMAC_RSR : (GMAC Offset: 0x020) Receive Status Register -------- */ +#define GMAC_RSR_BNA (0x1u << 0) /**< \brief (GMAC_RSR) Buffer Not Available */ +#define GMAC_RSR_REC (0x1u << 1) /**< \brief (GMAC_RSR) Frame Received */ +#define GMAC_RSR_RXOVR (0x1u << 2) /**< \brief (GMAC_RSR) Receive Overrun */ +#define GMAC_RSR_HNO (0x1u << 3) /**< \brief (GMAC_RSR) HRESP Not OK */ +/* -------- GMAC_ISR : (GMAC Offset: 0x024) Interrupt Status Register -------- */ +#define GMAC_ISR_MFS (0x1u << 0) /**< \brief (GMAC_ISR) Management Frame Sent */ +#define GMAC_ISR_RCOMP (0x1u << 1) /**< \brief (GMAC_ISR) Receive Complete */ +#define GMAC_ISR_RXUBR (0x1u << 2) /**< \brief (GMAC_ISR) RX Used Bit Read */ +#define GMAC_ISR_TXUBR (0x1u << 3) /**< \brief (GMAC_ISR) TX Used Bit Read */ +#define GMAC_ISR_TUR (0x1u << 4) /**< \brief (GMAC_ISR) Transmit Underrun */ +#define GMAC_ISR_RLEX (0x1u << 5) /**< \brief (GMAC_ISR) Retry Limit Exceeded */ +#define GMAC_ISR_TFC (0x1u << 6) /**< \brief (GMAC_ISR) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_ISR_TCOMP (0x1u << 7) /**< \brief (GMAC_ISR) Transmit Complete */ +#define GMAC_ISR_ROVR (0x1u << 10) /**< \brief (GMAC_ISR) Receive Overrun */ +#define GMAC_ISR_HRESP (0x1u << 11) /**< \brief (GMAC_ISR) HRESP Not OK */ +#define GMAC_ISR_PFNZ (0x1u << 12) /**< \brief (GMAC_ISR) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_ISR_PTZ (0x1u << 13) /**< \brief (GMAC_ISR) Pause Time Zero */ +#define GMAC_ISR_PFTR (0x1u << 14) /**< \brief (GMAC_ISR) Pause Frame Transmitted */ +#define GMAC_ISR_DRQFR (0x1u << 18) /**< \brief (GMAC_ISR) PTP Delay Request Frame Received */ +#define GMAC_ISR_SFR (0x1u << 19) /**< \brief (GMAC_ISR) PTP Sync Frame Received */ +#define GMAC_ISR_DRQFT (0x1u << 20) /**< \brief (GMAC_ISR) PTP Delay Request Frame Transmitted */ +#define GMAC_ISR_SFT (0x1u << 21) /**< \brief (GMAC_ISR) PTP Sync Frame Transmitted */ +#define GMAC_ISR_PDRQFR (0x1u << 22) /**< \brief (GMAC_ISR) PDelay Request Frame Received */ +#define GMAC_ISR_PDRSFR (0x1u << 23) /**< \brief (GMAC_ISR) PDelay Response Frame Received */ +#define GMAC_ISR_PDRQFT (0x1u << 24) /**< \brief (GMAC_ISR) PDelay Request Frame Transmitted */ +#define GMAC_ISR_PDRSFT (0x1u << 25) /**< \brief (GMAC_ISR) PDelay Response Frame Transmitted */ +#define GMAC_ISR_SRI (0x1u << 26) /**< \brief (GMAC_ISR) TSU Seconds Register Increment */ +#define GMAC_ISR_LPI (0x1u << 27) /**< \brief (GMAC_ISR) RX LPI indication */ +#define GMAC_ISR_WOL (0x1u << 28) /**< \brief (GMAC_ISR) Wake On LAN */ +#define GMAC_ISR_TSU (0x1u << 29) /**< \brief (GMAC_ISR) TSU timer comparison interrupt */ +/* -------- GMAC_IER : (GMAC Offset: 0x028) Interrupt Enable Register -------- */ +#define GMAC_IER_MFS (0x1u << 0) /**< \brief (GMAC_IER) Management Frame Sent */ +#define GMAC_IER_RCOMP (0x1u << 1) /**< \brief (GMAC_IER) Receive Complete */ +#define GMAC_IER_RXUBR (0x1u << 2) /**< \brief (GMAC_IER) RX Used Bit Read */ +#define GMAC_IER_TXUBR (0x1u << 3) /**< \brief (GMAC_IER) TX Used Bit Read */ +#define GMAC_IER_TUR (0x1u << 4) /**< \brief (GMAC_IER) Transmit Underrun */ +#define GMAC_IER_RLEX (0x1u << 5) /**< \brief (GMAC_IER) Retry Limit Exceeded or Late Collision */ +#define GMAC_IER_TFC (0x1u << 6) /**< \brief (GMAC_IER) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IER_TCOMP (0x1u << 7) /**< \brief (GMAC_IER) Transmit Complete */ +#define GMAC_IER_ROVR (0x1u << 10) /**< \brief (GMAC_IER) Receive Overrun */ +#define GMAC_IER_HRESP (0x1u << 11) /**< \brief (GMAC_IER) HRESP Not OK */ +#define GMAC_IER_PFNZ (0x1u << 12) /**< \brief (GMAC_IER) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_IER_PTZ (0x1u << 13) /**< \brief (GMAC_IER) Pause Time Zero */ +#define GMAC_IER_PFTR (0x1u << 14) /**< \brief (GMAC_IER) Pause Frame Transmitted */ +#define GMAC_IER_EXINT (0x1u << 15) /**< \brief (GMAC_IER) External Interrupt */ +#define GMAC_IER_DRQFR (0x1u << 18) /**< \brief (GMAC_IER) PTP Delay Request Frame Received */ +#define GMAC_IER_SFR (0x1u << 19) /**< \brief (GMAC_IER) PTP Sync Frame Received */ +#define GMAC_IER_DRQFT (0x1u << 20) /**< \brief (GMAC_IER) PTP Delay Request Frame Transmitted */ +#define GMAC_IER_SFT (0x1u << 21) /**< \brief (GMAC_IER) PTP Sync Frame Transmitted */ +#define GMAC_IER_PDRQFR (0x1u << 22) /**< \brief (GMAC_IER) PDelay Request Frame Received */ +#define GMAC_IER_PDRSFR (0x1u << 23) /**< \brief (GMAC_IER) PDelay Response Frame Received */ +#define GMAC_IER_PDRQFT (0x1u << 24) /**< \brief (GMAC_IER) PDelay Request Frame Transmitted */ +#define GMAC_IER_PDRSFT (0x1u << 25) /**< \brief (GMAC_IER) PDelay Response Frame Transmitted */ +#define GMAC_IER_SRI (0x1u << 26) /**< \brief (GMAC_IER) TSU Seconds Register Increment */ +#define GMAC_IER_LPI (0x1u << 27) /**< \brief (GMAC_IER) RX LPI indication */ +#define GMAC_IER_WOL (0x1u << 28) /**< \brief (GMAC_IER) Wake On LAN */ +#define GMAC_IER_TSU (0x1u << 29) /**< \brief (GMAC_IER) TSU timer comparison interrupt*/ +/* -------- GMAC_IDR : (GMAC Offset: 0x02C) Interrupt Disable Register -------- */ +#define GMAC_IDR_MFS (0x1u << 0) /**< \brief (GMAC_IDR) Management Frame Sent */ +#define GMAC_IDR_RCOMP (0x1u << 1) /**< \brief (GMAC_IDR) Receive Complete */ +#define GMAC_IDR_RXUBR (0x1u << 2) /**< \brief (GMAC_IDR) RX Used Bit Read */ +#define GMAC_IDR_TXUBR (0x1u << 3) /**< \brief (GMAC_IDR) TX Used Bit Read */ +#define GMAC_IDR_TUR (0x1u << 4) /**< \brief (GMAC_IDR) Transmit Underrun */ +#define GMAC_IDR_RLEX (0x1u << 5) /**< \brief (GMAC_IDR) Retry Limit Exceeded or Late Collision */ +#define GMAC_IDR_TFC (0x1u << 6) /**< \brief (GMAC_IDR) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IDR_TCOMP (0x1u << 7) /**< \brief (GMAC_IDR) Transmit Complete */ +#define GMAC_IDR_ROVR (0x1u << 10) /**< \brief (GMAC_IDR) Receive Overrun */ +#define GMAC_IDR_HRESP (0x1u << 11) /**< \brief (GMAC_IDR) HRESP Not OK */ +#define GMAC_IDR_PFNZ (0x1u << 12) /**< \brief (GMAC_IDR) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_IDR_PTZ (0x1u << 13) /**< \brief (GMAC_IDR) Pause Time Zero */ +#define GMAC_IDR_PFTR (0x1u << 14) /**< \brief (GMAC_IDR) Pause Frame Transmitted */ +#define GMAC_IDR_EXINT (0x1u << 15) /**< \brief (GMAC_IDR) External Interrupt */ +#define GMAC_IDR_DRQFR (0x1u << 18) /**< \brief (GMAC_IDR) PTP Delay Request Frame Received */ +#define GMAC_IDR_SFR (0x1u << 19) /**< \brief (GMAC_IDR) PTP Sync Frame Received */ +#define GMAC_IDR_DRQFT (0x1u << 20) /**< \brief (GMAC_IDR) PTP Delay Request Frame Transmitted */ +#define GMAC_IDR_SFT (0x1u << 21) /**< \brief (GMAC_IDR) PTP Sync Frame Transmitted */ +#define GMAC_IDR_PDRQFR (0x1u << 22) /**< \brief (GMAC_IDR) PDelay Request Frame Received */ +#define GMAC_IDR_PDRSFR (0x1u << 23) /**< \brief (GMAC_IDR) PDelay Response Frame Received */ +#define GMAC_IDR_PDRQFT (0x1u << 24) /**< \brief (GMAC_IDR) PDelay Request Frame Transmitted */ +#define GMAC_IDR_PDRSFT (0x1u << 25) /**< \brief (GMAC_IDR) PDelay Response Frame Transmitted */ +#define GMAC_IDR_SRI (0x1u << 26) /**< \brief (GMAC_IDR) TSU Seconds Register Increment */ +#define GMAC_IDR_LPI (0x1u << 27) /**< \brief (GMAC_IER) RX LPI indication */ +#define GMAC_IDR_WOL (0x1u << 28) /**< \brief (GMAC_IER) Wake On LAN */ +#define GMAC_IDR_TSU (0x1u << 29) /**< \brief (GMAC_IER) TSU timer comparison interrupt*/ +/* -------- GMAC_IMR : (GMAC Offset: 0x030) Interrupt Mask Register -------- */ +#define GMAC_IMR_MFS (0x1u << 0) /**< \brief (GMAC_IMR) Management Frame Sent */ +#define GMAC_IMR_RCOMP (0x1u << 1) /**< \brief (GMAC_IMR) Receive Complete */ +#define GMAC_IMR_RXUBR (0x1u << 2) /**< \brief (GMAC_IMR) RX Used Bit Read */ +#define GMAC_IMR_TXUBR (0x1u << 3) /**< \brief (GMAC_IMR) TX Used Bit Read */ +#define GMAC_IMR_TUR (0x1u << 4) /**< \brief (GMAC_IMR) Transmit Underrun */ +#define GMAC_IMR_RLEX (0x1u << 5) /**< \brief (GMAC_IMR) Retry Limit Exceeded */ +#define GMAC_IMR_TFC (0x1u << 6) /**< \brief (GMAC_IMR) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IMR_TCOMP (0x1u << 7) /**< \brief (GMAC_IMR) Transmit Complete */ +#define GMAC_IMR_ROVR (0x1u << 10) /**< \brief (GMAC_IMR) Receive Overrun */ +#define GMAC_IMR_HRESP (0x1u << 11) /**< \brief (GMAC_IMR) HRESP Not OK */ +#define GMAC_IMR_PFNZ (0x1u << 12) /**< \brief (GMAC_IMR) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_IMR_PTZ (0x1u << 13) /**< \brief (GMAC_IMR) Pause Time Zero */ +#define GMAC_IMR_PFTR (0x1u << 14) /**< \brief (GMAC_IMR) Pause Frame Transmitted */ +#define GMAC_IMR_EXINT (0x1u << 15) /**< \brief (GMAC_IMR) External Interrupt */ +#define GMAC_IMR_DRQFR (0x1u << 18) /**< \brief (GMAC_IMR) PTP Delay Request Frame Received */ +#define GMAC_IMR_SFR (0x1u << 19) /**< \brief (GMAC_IMR) PTP Sync Frame Received */ +#define GMAC_IMR_DRQFT (0x1u << 20) /**< \brief (GMAC_IMR) PTP Delay Request Frame Transmitted */ +#define GMAC_IMR_SFT (0x1u << 21) /**< \brief (GMAC_IMR) PTP Sync Frame Transmitted */ +#define GMAC_IMR_PDRQFR (0x1u << 22) /**< \brief (GMAC_IMR) PDelay Request Frame Received */ +#define GMAC_IMR_PDRSFR (0x1u << 23) /**< \brief (GMAC_IMR) PDelay Response Frame Received */ +#define GMAC_IMR_PDRQFT (0x1u << 24) /**< \brief (GMAC_IMR) PDelay Request Frame Transmitted */ +#define GMAC_IMR_PDRSFT (0x1u << 25) /**< \brief (GMAC_IMR) PDelay Response Frame Transmitted */ +#define GMAC_IMR_SRI (0x1u << 26) /**< \brief (GMAC_IDR) TSU Seconds Register Increment */ +#define GMAC_IMR_LPI (0x1u << 27) /**< \brief (GMAC_IER) RX LPI indication */ +#define GMAC_IMR_WOL (0x1u << 28) /**< \brief (GMAC_IER) Wake On LAN */ +#define GMAC_IMR_TSU (0x1u << 29) /**< \brief (GMAC_IER) TSU timer comparison interrupt*/ +/* -------- GMAC_MAN : (GMAC Offset: 0x034) PHY Maintenance Register -------- */ +#define GMAC_MAN_DATA_Pos 0 +#define GMAC_MAN_DATA_Msk (0xffffu << GMAC_MAN_DATA_Pos) /**< \brief (GMAC_MAN) PHY Data */ +#define GMAC_MAN_DATA(value) ((GMAC_MAN_DATA_Msk & ((value) << GMAC_MAN_DATA_Pos))) +#define GMAC_MAN_WTN_Pos 16 +#define GMAC_MAN_WTN_Msk (0x3u << GMAC_MAN_WTN_Pos) /**< \brief (GMAC_MAN) Write Ten */ +#define GMAC_MAN_WTN(value) ((GMAC_MAN_WTN_Msk & ((value) << GMAC_MAN_WTN_Pos))) +#define GMAC_MAN_REGA_Pos 18 +#define GMAC_MAN_REGA_Msk (0x1fu << GMAC_MAN_REGA_Pos) /**< \brief (GMAC_MAN) Register Address */ +#define GMAC_MAN_REGA(value) ((GMAC_MAN_REGA_Msk & ((value) << GMAC_MAN_REGA_Pos))) +#define GMAC_MAN_PHYA_Pos 23 +#define GMAC_MAN_PHYA_Msk (0x1fu << GMAC_MAN_PHYA_Pos) /**< \brief (GMAC_MAN) PHY Address */ +#define GMAC_MAN_PHYA(value) ((GMAC_MAN_PHYA_Msk & ((value) << GMAC_MAN_PHYA_Pos))) +#define GMAC_MAN_OP_Pos 28 +#define GMAC_MAN_OP_Msk (0x3u << GMAC_MAN_OP_Pos) /**< \brief (GMAC_MAN) Operation */ +#define GMAC_MAN_OP(value) ((GMAC_MAN_OP_Msk & ((value) << GMAC_MAN_OP_Pos))) +#define GMAC_MAN_CLTTO (0x1u << 30) /**< \brief (GMAC_MAN) Clause 22 Operation */ +#define GMAC_MAN_WZO (0x1u << 31) /**< \brief (GMAC_MAN) Write ZERO */ +/* -------- GMAC_RPQ : (GMAC Offset: 0x038) Received Pause Quantum Register -------- */ +#define GMAC_RPQ_RPQ_Pos 0 +#define GMAC_RPQ_RPQ_Msk (0xffffu << GMAC_RPQ_RPQ_Pos) /**< \brief (GMAC_RPQ) Received Pause Quantum */ +/* -------- GMAC_TPQ : (GMAC Offset: 0x03C) Transmit Pause Quantum Register -------- */ +#define GMAC_TPQ_TPQ_Pos 0 +#define GMAC_TPQ_TPQ_Msk (0xffffu << GMAC_TPQ_TPQ_Pos) /**< \brief (GMAC_TPQ) Transmit Pause Quantum */ +#define GMAC_TPQ_TPQ(value) ((GMAC_TPQ_TPQ_Msk & ((value) << GMAC_TPQ_TPQ_Pos))) +/* -------- GMAC_TPSF : (GMAC Offset: 0x040) TX Partial Store and Forward Register -------- */ +#define GMAC_TPSF_TPB1ADR_Pos 0 +#define GMAC_TPSF_TPB1ADR_Msk (0xfffu << GMAC_TPSF_TPB1ADR_Pos) /**< \brief (GMAC_TPSF) Transmit Partial Store and Forward Address */ +#define GMAC_TPSF_TPB1ADR(value) ((GMAC_TPSF_TPB1ADR_Msk & ((value) << GMAC_TPSF_TPB1ADR_Pos))) +#define GMAC_TPSF_ENTXP (0x1u << 31) /**< \brief (GMAC_TPSF) Enable TX Partial Store and Forward Operation */ +/* -------- GMAC_RPSF : (GMAC Offset: 0x044) RX Partial Store and Forward Register -------- */ +#define GMAC_RPSF_RPB1ADR_Pos 0 +#define GMAC_RPSF_RPB1ADR_Msk (0xfffu << GMAC_RPSF_RPB1ADR_Pos) /**< \brief (GMAC_RPSF) Receive Partial Store and Forward Address */ +#define GMAC_RPSF_RPB1ADR(value) ((GMAC_RPSF_RPB1ADR_Msk & ((value) << GMAC_RPSF_RPB1ADR_Pos))) +#define GMAC_RPSF_ENRXP (0x1u << 31) /**< \brief (GMAC_RPSF) Enable RX Partial Store and Forward Operation */ +/* -------- GMAC_RJFML : (GMAC Offset: 0x048) RX Jumbo Frame Max Length Register -------- */ +#define GMAC_RJFML_FML_Pos 0 +#define GMAC_RJFML_FML_Msk (0x3fffu << GMAC_RJFML_FML_Pos) /**< \brief (GMAC_RJFML) Frame Max Length */ +#define GMAC_RJFML_FML(value) ((GMAC_RJFML_FML_Msk & ((value) << GMAC_RJFML_FML_Pos))) +/* -------- GMAC_HRB : (GMAC Offset: 0x080) Hash Register Bottom -------- */ +#define GMAC_HRB_ADDR_Pos 0 +#define GMAC_HRB_ADDR_Msk (0xffffffffu << GMAC_HRB_ADDR_Pos) /**< \brief (GMAC_HRB) Hash Address */ +#define GMAC_HRB_ADDR(value) ((GMAC_HRB_ADDR_Msk & ((value) << GMAC_HRB_ADDR_Pos))) +/* -------- GMAC_HRT : (GMAC Offset: 0x084) Hash Register Top -------- */ +#define GMAC_HRT_ADDR_Pos 0 +#define GMAC_HRT_ADDR_Msk (0xffffffffu << GMAC_HRT_ADDR_Pos) /**< \brief (GMAC_HRT) Hash Address */ +#define GMAC_HRT_ADDR(value) ((GMAC_HRT_ADDR_Msk & ((value) << GMAC_HRT_ADDR_Pos))) +/* -------- GMAC_SAB : (GMAC Offset: N/A) Specific Address 1 Bottom Register -------- */ +#define GMAC_SAB_ADDR_Pos 0 +#define GMAC_SAB_ADDR_Msk (0xffffffffu << GMAC_SAB_ADDR_Pos) /**< \brief (GMAC_SAB) Specific Address 1 */ +#define GMAC_SAB_ADDR(value) ((GMAC_SAB_ADDR_Msk & ((value) << GMAC_SAB_ADDR_Pos))) +/* -------- GMAC_SAT : (GMAC Offset: N/A) Specific Address 1 Top Register -------- */ +#define GMAC_SAT_ADDR_Pos 0 +#define GMAC_SAT_ADDR_Msk (0xffffu << GMAC_SAT_ADDR_Pos) /**< \brief (GMAC_SAT) Specific Address 1 */ +#define GMAC_SAT_ADDR(value) ((GMAC_SAT_ADDR_Msk & ((value) << GMAC_SAT_ADDR_Pos))) +/* -------- GMAC_TIDM1 : (GMAC Offset: 0x0A8) Type ID Match 1 Register -------- */ +#define GMAC_TIDM1_TID_Pos 0 +#define GMAC_TIDM1_TID_Msk (0xffffu << GMAC_TIDM1_TID_Pos) /**< \brief (GMAC_TIDM1) Type ID Match 1 */ +#define GMAC_TIDM1_TID(value) ((GMAC_TIDM1_TID_Msk & ((value) << GMAC_TIDM1_TID_Pos))) +#define GMAC_TIDM1_ENID1 (0x1u << 31) /**< \brief (GMAC_TIDM1) Enable Copying of TID Matched Frames */ +/* -------- GMAC_TIDM2 : (GMAC Offset: 0x0AC) Type ID Match 2 Register -------- */ +#define GMAC_TIDM2_TID_Pos 0 +#define GMAC_TIDM2_TID_Msk (0xffffu << GMAC_TIDM2_TID_Pos) /**< \brief (GMAC_TIDM2) Type ID Match 2 */ +#define GMAC_TIDM2_TID(value) ((GMAC_TIDM2_TID_Msk & ((value) << GMAC_TIDM2_TID_Pos))) +#define GMAC_TIDM2_ENID2 (0x1u << 31) /**< \brief (GMAC_TIDM2) Enable Copying of TID Matched Frames */ +/* -------- GMAC_TIDM3 : (GMAC Offset: 0x0B0) Type ID Match 3 Register -------- */ +#define GMAC_TIDM3_TID_Pos 0 +#define GMAC_TIDM3_TID_Msk (0xffffu << GMAC_TIDM3_TID_Pos) /**< \brief (GMAC_TIDM3) Type ID Match 3 */ +#define GMAC_TIDM3_TID(value) ((GMAC_TIDM3_TID_Msk & ((value) << GMAC_TIDM3_TID_Pos))) +#define GMAC_TIDM3_ENID3 (0x1u << 31) /**< \brief (GMAC_TIDM3) Enable Copying of TID Matched Frames */ +/* -------- GMAC_TIDM4 : (GMAC Offset: 0x0B4) Type ID Match 4 Register -------- */ +#define GMAC_TIDM4_TID_Pos 0 +#define GMAC_TIDM4_TID_Msk (0xffffu << GMAC_TIDM4_TID_Pos) /**< \brief (GMAC_TIDM4) Type ID Match 4 */ +#define GMAC_TIDM4_TID(value) ((GMAC_TIDM4_TID_Msk & ((value) << GMAC_TIDM4_TID_Pos))) +#define GMAC_TIDM4_ENID4 (0x1u << 31) /**< \brief (GMAC_TIDM4) Enable Copying of TID Matched Frames */ +/* -------- GMAC_WOL : (GMAC Offset: 0x0B8) Wake on LAN Register -------- */ +#define GMAC_WOL_IP_Pos 0 +#define GMAC_WOL_IP_Msk (0xffffu << GMAC_WOL_IP_Pos) /**< \brief (GMAC_WOL) ARP Request IP Address */ +#define GMAC_WOL_IP(value) ((GMAC_WOL_IP_Msk & ((value) << GMAC_WOL_IP_Pos))) +#define GMAC_WOL_MAG (0x1u << 16) /**< \brief (GMAC_WOL) Magic Packet Event Enable */ +#define GMAC_WOL_ARP (0x1u << 17) /**< \brief (GMAC_WOL) ARP Request IP Address */ +#define GMAC_WOL_SA1 (0x1u << 18) /**< \brief (GMAC_WOL) Specific Address Register 1 Event Enable */ +#define GMAC_WOL_MTI (0x1u << 19) /**< \brief (GMAC_WOL) Multicast Hash Event Enable */ +/* -------- GMAC_IPGS : (GMAC Offset: 0x0BC) IPG Stretch Register -------- */ +#define GMAC_IPGS_FL_Pos 0 +#define GMAC_IPGS_FL_Msk (0xffffu << GMAC_IPGS_FL_Pos) /**< \brief (GMAC_IPGS) Frame Length */ +#define GMAC_IPGS_FL(value) ((GMAC_IPGS_FL_Msk & ((value) << GMAC_IPGS_FL_Pos))) +/* -------- GMAC_SVLAN : (GMAC Offset: 0x0C0) Stacked VLAN Register -------- */ +#define GMAC_SVLAN_VLAN_TYPE_Pos 0 +#define GMAC_SVLAN_VLAN_TYPE_Msk (0xffffu << GMAC_SVLAN_VLAN_TYPE_Pos) /**< \brief (GMAC_SVLAN) User Defined VLAN_TYPE Field */ +#define GMAC_SVLAN_VLAN_TYPE(value) ((GMAC_SVLAN_VLAN_TYPE_Msk & ((value) << GMAC_SVLAN_VLAN_TYPE_Pos))) +#define GMAC_SVLAN_ESVLAN (0x1u << 31) /**< \brief (GMAC_SVLAN) Enable Stacked VLAN Processing Mode */ +/* -------- GMAC_TPFCP : (GMAC Offset: 0x0C4) Transmit PFC Pause Register -------- */ +#define GMAC_TPFCP_PEV_Pos 0 +#define GMAC_TPFCP_PEV_Msk (0xffu << GMAC_TPFCP_PEV_Pos) /**< \brief (GMAC_TPFCP) Priority Enable Vector */ +#define GMAC_TPFCP_PEV(value) ((GMAC_TPFCP_PEV_Msk & ((value) << GMAC_TPFCP_PEV_Pos))) +#define GMAC_TPFCP_PQ_Pos 8 +#define GMAC_TPFCP_PQ_Msk (0xffu << GMAC_TPFCP_PQ_Pos) /**< \brief (GMAC_TPFCP) Pause Quantum */ +#define GMAC_TPFCP_PQ(value) ((GMAC_TPFCP_PQ_Msk & ((value) << GMAC_TPFCP_PQ_Pos))) +/* -------- GMAC_SAMB1 : (GMAC Offset: 0x0C8) Specific Address 1 Mask Bottom Register -------- */ +#define GMAC_SAMB1_ADDR_Pos 0 +#define GMAC_SAMB1_ADDR_Msk (0xffffffffu << GMAC_SAMB1_ADDR_Pos) /**< \brief (GMAC_SAMB1) Specific Address 1 Mask */ +#define GMAC_SAMB1_ADDR(value) ((GMAC_SAMB1_ADDR_Msk & ((value) << GMAC_SAMB1_ADDR_Pos))) +/* -------- GMAC_SAMT1 : (GMAC Offset: 0x0CC) Specific Address 1 Mask Top Register -------- */ +#define GMAC_SAMT1_ADDR_Pos 0 +#define GMAC_SAMT1_ADDR_Msk (0xffffu << GMAC_SAMT1_ADDR_Pos) /**< \brief (GMAC_SAMT1) Specific Address 1 Mask */ +#define GMAC_SAMT1_ADDR(value) ((GMAC_SAMT1_ADDR_Msk & ((value) << GMAC_SAMT1_ADDR_Pos))) +/* -------- GMAC_NSC : (GMAC Offset: 0x0DC) 1588 Timer Nanosecond Comparison Register -------- */ +#define GMAC_NSC_NANOSEC_Pos 0 +#define GMAC_NSC_NANOSEC_Msk (0x3fffffu << GMAC_NSC_NANOSEC_Pos) /**< \brief (GMAC_NSC) 1588 Timer Nanosecond Comparison Value */ +#define GMAC_NSC_NANOSEC(value) ((GMAC_NSC_NANOSEC_Msk & ((value) << GMAC_NSC_NANOSEC_Pos))) +/* -------- GMAC_SCL : (GMAC Offset: 0x0E0) 1588 Timer Second Comparison Low Register -------- */ +#define GMAC_SCL_SEC_Pos 0 +#define GMAC_SCL_SEC_Msk (0xffffffffu << GMAC_SCL_SEC_Pos) /**< \brief (GMAC_SCL) 1588 Timer Second Comparison Value */ +#define GMAC_SCL_SEC(value) ((GMAC_SCL_SEC_Msk & ((value) << GMAC_SCL_SEC_Pos))) +/* -------- GMAC_SCH : (GMAC Offset: 0x0E4) 1588 Timer Second Comparison High Register -------- */ +#define GMAC_SCH_SEC_Pos 0 +#define GMAC_SCH_SEC_Msk (0xffffu << GMAC_SCH_SEC_Pos) /**< \brief (GMAC_SCH) 1588 Timer Second Comparison Value */ +#define GMAC_SCH_SEC(value) ((GMAC_SCH_SEC_Msk & ((value) << GMAC_SCH_SEC_Pos))) +/* -------- GMAC_EFTSH : (GMAC Offset: 0x0E8) PTP Event Frame Transmitted Seconds High Register -------- */ +#define GMAC_EFTSH_RUD_Pos 0 +#define GMAC_EFTSH_RUD_Msk (0xffffu << GMAC_EFTSH_RUD_Pos) /**< \brief (GMAC_EFTSH) Register Update */ +/* -------- GMAC_EFRSH : (GMAC Offset: 0x0EC) PTP Event Frame Received Seconds High Register -------- */ +#define GMAC_EFRSH_RUD_Pos 0 +#define GMAC_EFRSH_RUD_Msk (0xffffu << GMAC_EFRSH_RUD_Pos) /**< \brief (GMAC_EFRSH) Register Update */ +/* -------- GMAC_PEFTSH : (GMAC Offset: 0x0F0) PTP Peer Event Frame Transmitted Seconds High Register -------- */ +#define GMAC_PEFTSH_RUD_Pos 0 +#define GMAC_PEFTSH_RUD_Msk (0xffffu << GMAC_PEFTSH_RUD_Pos) /**< \brief (GMAC_PEFTSH) Register Update */ +/* -------- GMAC_PEFRSH : (GMAC Offset: 0x0F4) PTP Peer Event Frame Received Seconds High Register -------- */ +#define GMAC_PEFRSH_RUD_Pos 0 +#define GMAC_PEFRSH_RUD_Msk (0xffffu << GMAC_PEFRSH_RUD_Pos) /**< \brief (GMAC_PEFRSH) Register Update */ +/* -------- GMAC_OTLO : (GMAC Offset: 0x100) Octets Transmitted Low Register -------- */ +#define GMAC_OTLO_TXO_Pos 0 +#define GMAC_OTLO_TXO_Msk (0xffffffffu << GMAC_OTLO_TXO_Pos) /**< \brief (GMAC_OTLO) Transmitted Octets */ +/* -------- GMAC_OTHI : (GMAC Offset: 0x104) Octets Transmitted High Register -------- */ +#define GMAC_OTHI_TXO_Pos 0 +#define GMAC_OTHI_TXO_Msk (0xffffu << GMAC_OTHI_TXO_Pos) /**< \brief (GMAC_OTHI) Transmitted Octets */ +/* -------- GMAC_FT : (GMAC Offset: 0x108) Frames Transmitted Register -------- */ +#define GMAC_FT_FTX_Pos 0 +#define GMAC_FT_FTX_Msk (0xffffffffu << GMAC_FT_FTX_Pos) /**< \brief (GMAC_FT) Frames Transmitted without Error */ +/* -------- GMAC_BCFT : (GMAC Offset: 0x10C) Broadcast Frames Transmitted Register -------- */ +#define GMAC_BCFT_BFTX_Pos 0 +#define GMAC_BCFT_BFTX_Msk (0xffffffffu << GMAC_BCFT_BFTX_Pos) /**< \brief (GMAC_BCFT) Broadcast Frames Transmitted without Error */ +/* -------- GMAC_MFT : (GMAC Offset: 0x110) Multicast Frames Transmitted Register -------- */ +#define GMAC_MFT_MFTX_Pos 0 +#define GMAC_MFT_MFTX_Msk (0xffffffffu << GMAC_MFT_MFTX_Pos) /**< \brief (GMAC_MFT) Multicast Frames Transmitted without Error */ +/* -------- GMAC_PFT : (GMAC Offset: 0x114) Pause Frames Transmitted Register -------- */ +#define GMAC_PFT_PFTX_Pos 0 +#define GMAC_PFT_PFTX_Msk (0xffffu << GMAC_PFT_PFTX_Pos) /**< \brief (GMAC_PFT) Pause Frames Transmitted Register */ +/* -------- GMAC_BFT64 : (GMAC Offset: 0x118) 64 Byte Frames Transmitted Register -------- */ +#define GMAC_BFT64_NFTX_Pos 0 +#define GMAC_BFT64_NFTX_Msk (0xffffffffu << GMAC_BFT64_NFTX_Pos) /**< \brief (GMAC_BFT64) 64 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT127 : (GMAC Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT127_NFTX_Pos 0 +#define GMAC_TBFT127_NFTX_Msk (0xffffffffu << GMAC_TBFT127_NFTX_Pos) /**< \brief (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT255 : (GMAC Offset: 0x120) 128 to 255 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT255_NFTX_Pos 0 +#define GMAC_TBFT255_NFTX_Msk (0xffffffffu << GMAC_TBFT255_NFTX_Pos) /**< \brief (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT511 : (GMAC Offset: 0x124) 256 to 511 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT511_NFTX_Pos 0 +#define GMAC_TBFT511_NFTX_Msk (0xffffffffu << GMAC_TBFT511_NFTX_Pos) /**< \brief (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT1023 : (GMAC Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT1023_NFTX_Pos 0 +#define GMAC_TBFT1023_NFTX_Msk (0xffffffffu << GMAC_TBFT1023_NFTX_Pos) /**< \brief (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT1518 : (GMAC Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT1518_NFTX_Pos 0 +#define GMAC_TBFT1518_NFTX_Msk (0xffffffffu << GMAC_TBFT1518_NFTX_Pos) /**< \brief (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted without Error */ +/* -------- GMAC_GTBFT1518 : (GMAC Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register -------- */ +#define GMAC_GTBFT1518_NFTX_Pos 0 +#define GMAC_GTBFT1518_NFTX_Msk (0xffffffffu << GMAC_GTBFT1518_NFTX_Pos) /**< \brief (GMAC_GTBFT1518) Greater than 1518 Byte Frames Transmitted without Error */ +/* -------- GMAC_TUR : (GMAC Offset: 0x134) Transmit Underruns Register -------- */ +#define GMAC_TUR_TXUNR_Pos 0 +#define GMAC_TUR_TXUNR_Msk (0x3ffu << GMAC_TUR_TXUNR_Pos) /**< \brief (GMAC_TUR) Transmit Underruns */ +/* -------- GMAC_SCF : (GMAC Offset: 0x138) Single Collision Frames Register -------- */ +#define GMAC_SCF_SCOL_Pos 0 +#define GMAC_SCF_SCOL_Msk (0x3ffffu << GMAC_SCF_SCOL_Pos) /**< \brief (GMAC_SCF) Single Collision */ +/* -------- GMAC_MCF : (GMAC Offset: 0x13C) Multiple Collision Frames Register -------- */ +#define GMAC_MCF_MCOL_Pos 0 +#define GMAC_MCF_MCOL_Msk (0x3ffffu << GMAC_MCF_MCOL_Pos) /**< \brief (GMAC_MCF) Multiple Collision */ +/* -------- GMAC_EC : (GMAC Offset: 0x140) Excessive Collisions Register -------- */ +#define GMAC_EC_XCOL_Pos 0 +#define GMAC_EC_XCOL_Msk (0x3ffu << GMAC_EC_XCOL_Pos) /**< \brief (GMAC_EC) Excessive Collisions */ +/* -------- GMAC_LC : (GMAC Offset: 0x144) Late Collisions Register -------- */ +#define GMAC_LC_LCOL_Pos 0 +#define GMAC_LC_LCOL_Msk (0x3ffu << GMAC_LC_LCOL_Pos) /**< \brief (GMAC_LC) Late Collisions */ +/* -------- GMAC_DTF : (GMAC Offset: 0x148) Deferred Transmission Frames Register -------- */ +#define GMAC_DTF_DEFT_Pos 0 +#define GMAC_DTF_DEFT_Msk (0x3ffffu << GMAC_DTF_DEFT_Pos) /**< \brief (GMAC_DTF) Deferred Transmission */ +/* -------- GMAC_CSE : (GMAC Offset: 0x14C) Carrier Sense Errors Register Register -------- */ +#define GMAC_CSE_CSR_Pos 0 +#define GMAC_CSE_CSR_Msk (0x3ffu << GMAC_CSE_CSR_Pos) /**< \brief (GMAC_CSE) Carrier Sense Error */ +/* -------- GMAC_ORLO : (GMAC Offset: 0x150) Octets Received Low Received Register -------- */ +#define GMAC_ORLO_RXO_Pos 0 +#define GMAC_ORLO_RXO_Msk (0xffffffffu << GMAC_ORLO_RXO_Pos) /**< \brief (GMAC_ORLO) Received Octets */ +/* -------- GMAC_ORHI : (GMAC Offset: 0x154) Octets Received High Received Register -------- */ +#define GMAC_ORHI_RXO_Pos 0 +#define GMAC_ORHI_RXO_Msk (0xffffu << GMAC_ORHI_RXO_Pos) /**< \brief (GMAC_ORHI) Received Octets */ +/* -------- GMAC_FR : (GMAC Offset: 0x158) Frames Received Register -------- */ +#define GMAC_FR_FRX_Pos 0 +#define GMAC_FR_FRX_Msk (0xffffffffu << GMAC_FR_FRX_Pos) /**< \brief (GMAC_FR) Frames Received without Error */ +/* -------- GMAC_BCFR : (GMAC Offset: 0x15C) Broadcast Frames Received Register -------- */ +#define GMAC_BCFR_BFRX_Pos 0 +#define GMAC_BCFR_BFRX_Msk (0xffffffffu << GMAC_BCFR_BFRX_Pos) /**< \brief (GMAC_BCFR) Broadcast Frames Received without Error */ +/* -------- GMAC_MFR : (GMAC Offset: 0x160) Multicast Frames Received Register -------- */ +#define GMAC_MFR_MFRX_Pos 0 +#define GMAC_MFR_MFRX_Msk (0xffffffffu << GMAC_MFR_MFRX_Pos) /**< \brief (GMAC_MFR) Multicast Frames Received without Error */ +/* -------- GMAC_PFR : (GMAC Offset: 0x164) Pause Frames Received Register -------- */ +#define GMAC_PFR_PFRX_Pos 0 +#define GMAC_PFR_PFRX_Msk (0xffffu << GMAC_PFR_PFRX_Pos) /**< \brief (GMAC_PFR) Pause Frames Received Register */ +/* -------- GMAC_BFR64 : (GMAC Offset: 0x168) 64 Byte Frames Received Register -------- */ +#define GMAC_BFR64_NFRX_Pos 0 +#define GMAC_BFR64_NFRX_Msk (0xffffffffu << GMAC_BFR64_NFRX_Pos) /**< \brief (GMAC_BFR64) 64 Byte Frames Received without Error */ +/* -------- GMAC_TBFR127 : (GMAC Offset: 0x16C) 65 to 127 Byte Frames Received Register -------- */ +#define GMAC_TBFR127_NFRX_Pos 0 +#define GMAC_TBFR127_NFRX_Msk (0xffffffffu << GMAC_TBFR127_NFRX_Pos) /**< \brief (GMAC_TBFR127) 65 to 127 Byte Frames Received without Error */ +/* -------- GMAC_TBFR255 : (GMAC Offset: 0x170) 128 to 255 Byte Frames Received Register -------- */ +#define GMAC_TBFR255_NFRX_Pos 0 +#define GMAC_TBFR255_NFRX_Msk (0xffffffffu << GMAC_TBFR255_NFRX_Pos) /**< \brief (GMAC_TBFR255) 128 to 255 Byte Frames Received without Error */ +/* -------- GMAC_TBFR511 : (GMAC Offset: 0x174) 256 to 511 Byte Frames Received Register -------- */ +#define GMAC_TBFR511_NFRX_Pos 0 +#define GMAC_TBFR511_NFRX_Msk (0xffffffffu << GMAC_TBFR511_NFRX_Pos) /**< \brief (GMAC_TBFR511) 256 to 511 Byte Frames Received without Error */ +/* -------- GMAC_TBFR1023 : (GMAC Offset: 0x178) 512 to 1023 Byte Frames Received Register -------- */ +#define GMAC_TBFR1023_NFRX_Pos 0 +#define GMAC_TBFR1023_NFRX_Msk (0xffffffffu << GMAC_TBFR1023_NFRX_Pos) /**< \brief (GMAC_TBFR1023) 512 to 1023 Byte Frames Received without Error */ +/* -------- GMAC_TBFR1518 : (GMAC Offset: 0x17C) 1024 to 1518 Byte Frames Received Register -------- */ +#define GMAC_TBFR1518_NFRX_Pos 0 +#define GMAC_TBFR1518_NFRX_Msk (0xffffffffu << GMAC_TBFR1518_NFRX_Pos) /**< \brief (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received without Error */ +/* -------- GMAC_TMXBFR : (GMAC Offset: 0x180) 1519 to Maximum Byte Frames Received Register -------- */ +#define GMAC_TMXBFR_NFRX_Pos 0 +#define GMAC_TMXBFR_NFRX_Msk (0xffffffffu << GMAC_TMXBFR_NFRX_Pos) /**< \brief (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received without Error */ +/* -------- GMAC_UFR : (GMAC Offset: 0x184) Undersize Frames Received Register -------- */ +#define GMAC_UFR_UFRX_Pos 0 +#define GMAC_UFR_UFRX_Msk (0x3ffu << GMAC_UFR_UFRX_Pos) /**< \brief (GMAC_UFR) Undersize Frames Received */ +/* -------- GMAC_OFR : (GMAC Offset: 0x188) Oversize Frames Received Register -------- */ +#define GMAC_OFR_OFRX_Pos 0 +#define GMAC_OFR_OFRX_Msk (0x3ffu << GMAC_OFR_OFRX_Pos) /**< \brief (GMAC_OFR) Oversized Frames Received */ +/* -------- GMAC_JR : (GMAC Offset: 0x18C) Jabbers Received Register -------- */ +#define GMAC_JR_JRX_Pos 0 +#define GMAC_JR_JRX_Msk (0x3ffu << GMAC_JR_JRX_Pos) /**< \brief (GMAC_JR) Jabbers Received */ +/* -------- GMAC_FCSE : (GMAC Offset: 0x190) Frame Check Sequence Errors Register -------- */ +#define GMAC_FCSE_FCKR_Pos 0 +#define GMAC_FCSE_FCKR_Msk (0x3ffu << GMAC_FCSE_FCKR_Pos) /**< \brief (GMAC_FCSE) Frame Check Sequence Errors */ +/* -------- GMAC_LFFE : (GMAC Offset: 0x194) Length Field Frame Errors Register -------- */ +#define GMAC_LFFE_LFER_Pos 0 +#define GMAC_LFFE_LFER_Msk (0x3ffu << GMAC_LFFE_LFER_Pos) /**< \brief (GMAC_LFFE) Length Field Frame Errors */ +/* -------- GMAC_RSE : (GMAC Offset: 0x198) Receive Symbol Errors Register -------- */ +#define GMAC_RSE_RXSE_Pos 0 +#define GMAC_RSE_RXSE_Msk (0x3ffu << GMAC_RSE_RXSE_Pos) /**< \brief (GMAC_RSE) Receive Symbol Errors */ +/* -------- GMAC_AE : (GMAC Offset: 0x19C) Alignment Errors Register -------- */ +#define GMAC_AE_AER_Pos 0 +#define GMAC_AE_AER_Msk (0x3ffu << GMAC_AE_AER_Pos) /**< \brief (GMAC_AE) Alignment Errors */ +/* -------- GMAC_RRE : (GMAC Offset: 0x1A0) Receive Resource Errors Register -------- */ +#define GMAC_RRE_RXRER_Pos 0 +#define GMAC_RRE_RXRER_Msk (0x3ffffu << GMAC_RRE_RXRER_Pos) /**< \brief (GMAC_RRE) Receive Resource Errors */ +/* -------- GMAC_ROE : (GMAC Offset: 0x1A4) Receive Overrun Register -------- */ +#define GMAC_ROE_RXOVR_Pos 0 +#define GMAC_ROE_RXOVR_Msk (0x3ffu << GMAC_ROE_RXOVR_Pos) /**< \brief (GMAC_ROE) Receive Overruns */ +/* -------- GMAC_IHCE : (GMAC Offset: 0x1A8) IP Header Checksum Errors Register -------- */ +#define GMAC_IHCE_HCKER_Pos 0 +#define GMAC_IHCE_HCKER_Msk (0xffu << GMAC_IHCE_HCKER_Pos) /**< \brief (GMAC_IHCE) IP Header Checksum Errors */ +/* -------- GMAC_TCE : (GMAC Offset: 0x1AC) TCP Checksum Errors Register -------- */ +#define GMAC_TCE_TCKER_Pos 0 +#define GMAC_TCE_TCKER_Msk (0xffu << GMAC_TCE_TCKER_Pos) /**< \brief (GMAC_TCE) TCP Checksum Errors */ +/* -------- GMAC_UCE : (GMAC Offset: 0x1B0) UDP Checksum Errors Register -------- */ +#define GMAC_UCE_UCKER_Pos 0 +#define GMAC_UCE_UCKER_Msk (0xffu << GMAC_UCE_UCKER_Pos) /**< \brief (GMAC_UCE) UDP Checksum Errors */ +/* -------- GMAC_TISUBN : (GMAC Offset: 0x1BC) 1588 Timer Increment Sub-nanoseconds Register -------- */ +#define GMAC_TISUBN_LSBTIR_Pos 0 +#define GMAC_TISUBN_LSBTIR_Msk (0xffffu << GMAC_TISUBN_LSBTIR_Pos) /**< \brief (GMAC_TISUBN) Lower Significant Bits of Timer Increment Register */ +#define GMAC_TISUBN_LSBTIR(value) ((GMAC_TISUBN_LSBTIR_Msk & ((value) << GMAC_TISUBN_LSBTIR_Pos))) +/* -------- GMAC_TSH : (GMAC Offset: 0x1C0) 1588 Timer Seconds High Register -------- */ +#define GMAC_TSH_TCS_Pos 0 +#define GMAC_TSH_TCS_Msk (0xffffu << GMAC_TSH_TCS_Pos) /**< \brief (GMAC_TSH) Timer Count in Seconds */ +#define GMAC_TSH_TCS(value) ((GMAC_TSH_TCS_Msk & ((value) << GMAC_TSH_TCS_Pos))) +/* -------- GMAC_TSL : (GMAC Offset: 0x1D0) 1588 Timer Seconds Low Register -------- */ +#define GMAC_TSL_TCS_Pos 0 +#define GMAC_TSL_TCS_Msk (0xffffffffu << GMAC_TSL_TCS_Pos) /**< \brief (GMAC_TSL) Timer Count in Seconds */ +#define GMAC_TSL_TCS(value) ((GMAC_TSL_TCS_Msk & ((value) << GMAC_TSL_TCS_Pos))) +/* -------- GMAC_TN : (GMAC Offset: 0x1D4) 1588 Timer Nanoseconds Register -------- */ +#define GMAC_TN_TNS_Pos 0 +#define GMAC_TN_TNS_Msk (0x3fffffffu << GMAC_TN_TNS_Pos) /**< \brief (GMAC_TN) Timer Count in Nanoseconds */ +#define GMAC_TN_TNS(value) ((GMAC_TN_TNS_Msk & ((value) << GMAC_TN_TNS_Pos))) +/* -------- GMAC_TA : (GMAC Offset: 0x1D8) 1588 Timer Adjust Register -------- */ +#define GMAC_TA_ITDT_Pos 0 +#define GMAC_TA_ITDT_Msk (0x3fffffffu << GMAC_TA_ITDT_Pos) /**< \brief (GMAC_TA) Increment/Decrement */ +#define GMAC_TA_ITDT(value) ((GMAC_TA_ITDT_Msk & ((value) << GMAC_TA_ITDT_Pos))) +#define GMAC_TA_ADJ (0x1u << 31) /**< \brief (GMAC_TA) Adjust 1588 Timer */ +/* -------- GMAC_TI : (GMAC Offset: 0x1DC) 1588 Timer Increment Register -------- */ +#define GMAC_TI_CNS_Pos 0 +#define GMAC_TI_CNS_Msk (0xffu << GMAC_TI_CNS_Pos) /**< \brief (GMAC_TI) Count Nanoseconds */ +#define GMAC_TI_CNS(value) ((GMAC_TI_CNS_Msk & ((value) << GMAC_TI_CNS_Pos))) +#define GMAC_TI_ACNS_Pos 8 +#define GMAC_TI_ACNS_Msk (0xffu << GMAC_TI_ACNS_Pos) /**< \brief (GMAC_TI) Alternative Count Nanoseconds */ +#define GMAC_TI_ACNS(value) ((GMAC_TI_ACNS_Msk & ((value) << GMAC_TI_ACNS_Pos))) +#define GMAC_TI_NIT_Pos 16 +#define GMAC_TI_NIT_Msk (0xffu << GMAC_TI_NIT_Pos) /**< \brief (GMAC_TI) Number of Increments */ +#define GMAC_TI_NIT(value) ((GMAC_TI_NIT_Msk & ((value) << GMAC_TI_NIT_Pos))) +/* -------- GMAC_EFTSL : (GMAC Offset: 0x1E0) PTP Event Frame Transmitted Seconds Low Register -------- */ +#define GMAC_EFTSL_RUD_Pos 0 +#define GMAC_EFTSL_RUD_Msk (0xffffffffu << GMAC_EFTSL_RUD_Pos) /**< \brief (GMAC_EFTSL) Register Update */ +/* -------- GMAC_EFTN : (GMAC Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds Register -------- */ +#define GMAC_EFTN_RUD_Pos 0 +#define GMAC_EFTN_RUD_Msk (0x3fffffffu << GMAC_EFTN_RUD_Pos) /**< \brief (GMAC_EFTN) Register Update */ +/* -------- GMAC_EFRSL : (GMAC Offset: 0x1E8) PTP Event Frame Received Seconds Low Register -------- */ +#define GMAC_EFRSL_RUD_Pos 0 +#define GMAC_EFRSL_RUD_Msk (0xffffffffu << GMAC_EFRSL_RUD_Pos) /**< \brief (GMAC_EFRSL) Register Update */ +/* -------- GMAC_EFRN : (GMAC Offset: 0x1EC) PTP Event Frame Received Nanoseconds Register -------- */ +#define GMAC_EFRN_RUD_Pos 0 +#define GMAC_EFRN_RUD_Msk (0x3fffffffu << GMAC_EFRN_RUD_Pos) /**< \brief (GMAC_EFRN) Register Update */ +/* -------- GMAC_PEFTSL : (GMAC Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds Low Register -------- */ +#define GMAC_PEFTSL_RUD_Pos 0 +#define GMAC_PEFTSL_RUD_Msk (0xffffffffu << GMAC_PEFTSL_RUD_Pos) /**< \brief (GMAC_PEFTSL) Register Update */ +/* -------- GMAC_PEFTN : (GMAC Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds Register -------- */ +#define GMAC_PEFTN_RUD_Pos 0 +#define GMAC_PEFTN_RUD_Msk (0x3fffffffu << GMAC_PEFTN_RUD_Pos) /**< \brief (GMAC_PEFTN) Register Update */ +/* -------- GMAC_PEFRSL : (GMAC Offset: 0x1F8) PTP Peer Event Frame Received Seconds Low Register -------- */ +#define GMAC_PEFRSL_RUD_Pos 0 +#define GMAC_PEFRSL_RUD_Msk (0xffffffffu << GMAC_PEFRSL_RUD_Pos) /**< \brief (GMAC_PEFRSL) Register Update */ +/* -------- GMAC_PEFRN : (GMAC Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds Register -------- */ +#define GMAC_PEFRN_RUD_Pos 0 +#define GMAC_PEFRN_RUD_Msk (0x3fffffffu << GMAC_PEFRN_RUD_Pos) /**< \brief (GMAC_PEFRN) Register Update */ +/* -------- GMAC_ISRPQ[3] : (GMAC Offset: 0x400) Interrupt Status Register Priority Queue (index = 1) -------- */ +#define GMAC_ISRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_ISRPQ[3]) Receive Complete */ +#define GMAC_ISRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_ISRPQ[3]) RX Used Bit Read */ +#define GMAC_ISRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_ISRPQ[3]) Retry Limit Exceeded or Late Collision */ +#define GMAC_ISRPQ_TFC (0x1u << 6) /**< \brief (GMAC_ISRPQ[3]) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_ISRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_ISRPQ[3]) Transmit Complete */ +#define GMAC_ISRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_ISRPQ[3]) Receive Overrun */ +#define GMAC_ISRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_ISRPQ[3]) HRESP Not OK */ +/* -------- GMAC_TBQBAPQ[3] : (GMAC Offset: 0x440) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) -------- */ +#define GMAC_TBQBAPQ_TXBQBA_Pos 2 +#define GMAC_TBQBAPQ_TXBQBA_Msk (0x3fu << GMAC_TBQBAPQ_TXBQBA_Pos) /**< \brief (GMAC_TBQBAPQ[3]) Transmit Buffer Queue Base Address */ +#define GMAC_TBQBAPQ_TXBQBA(value) ((GMAC_TBQBAPQ_TXBQBA_Msk & ((value) << GMAC_TBQBAPQ_TXBQBA_Pos))) +/* -------- GMAC_RBQBAPQ[3] : (GMAC Offset: 0x480) Receive Buffer Queue Base Address Register Priority Queue (index = 1) -------- */ +#define GMAC_RBQBAPQ_RXBQBA_Pos 2 +#define GMAC_RBQBAPQ_RXBQBA_Msk (0x3fu << GMAC_RBQBAPQ_RXBQBA_Pos) /**< \brief (GMAC_RBQBAPQ[3]) Receive Buffer Queue Base Address */ +#define GMAC_RBQBAPQ_RXBQBA(value) ((GMAC_RBQBAPQ_RXBQBA_Msk & ((value) << GMAC_RBQBAPQ_RXBQBA_Pos))) +/* -------- GMAC_RBSRPQ[3] : (GMAC Offset: 0x4A0) Receive Buffer Size Register Priority Queue (index = 1) -------- */ +#define GMAC_RBSRPQ_RBS_Pos 0 +#define GMAC_RBSRPQ_RBS_Msk (0xffffu << GMAC_RBSRPQ_RBS_Pos) /**< \brief (GMAC_RBSRPQ[3]) Receive Buffer Size */ +#define GMAC_RBSRPQ_RBS(value) ((GMAC_RBSRPQ_RBS_Msk & ((value) << GMAC_RBSRPQ_RBS_Pos))) +/* -------- GMAC_CBSCR : (GMAC Offset: 0x4BC) Credit-Based Shaping Control Register -------- */ +#define GMAC_CBSCR_QBE (0x1u << 0) /**< \brief (GMAC_CBSCR) Queue B CBS Enable */ +#define GMAC_CBSCR_QAE (0x1u << 1) /**< \brief (GMAC_CBSCR) Queue A CBS Enable */ +/* -------- GMAC_CBSISQA : (GMAC Offset: 0x4C0) Credit-Based Shaping IdleSlope Register for Queue A -------- */ +#define GMAC_CBSISQA_IS_Pos 0 +#define GMAC_CBSISQA_IS_Msk (0xffffffffu << GMAC_CBSISQA_IS_Pos) /**< \brief (GMAC_CBSISQA) IdleSlope */ +#define GMAC_CBSISQA_IS(value) ((GMAC_CBSISQA_IS_Msk & ((value) << GMAC_CBSISQA_IS_Pos))) +/* -------- GMAC_CBSISQB : (GMAC Offset: 0x4C4) Credit-Based Shaping IdleSlope Register for Queue B -------- */ +#define GMAC_CBSISQB_IS_Pos 0 +#define GMAC_CBSISQB_IS_Msk (0xffffffffu << GMAC_CBSISQB_IS_Pos) /**< \brief (GMAC_CBSISQB) IdleSlope */ +#define GMAC_CBSISQB_IS(value) ((GMAC_CBSISQB_IS_Msk & ((value) << GMAC_CBSISQB_IS_Pos))) +/* -------- GMAC_ST1RPQ[4] : (GMAC Offset: 0x500) Screening Type 1 Register Priority Queue (index = 0) -------- */ +#define GMAC_ST1RPQ_QNB_Pos 0 +#define GMAC_ST1RPQ_QNB_Msk (0x7u << GMAC_ST1RPQ_QNB_Pos) /**< \brief (GMAC_ST1RPQ[4]) Queue Number (0-2) */ +#define GMAC_ST1RPQ_QNB(value) ((GMAC_ST1RPQ_QNB_Msk & ((value) << GMAC_ST1RPQ_QNB_Pos))) +#define GMAC_ST1RPQ_DSTCM_Pos 4 +#define GMAC_ST1RPQ_DSTCM_Msk (0xffu << GMAC_ST1RPQ_DSTCM_Pos) /**< \brief (GMAC_ST1RPQ[4]) Differentiated Services or Traffic Class Match */ +#define GMAC_ST1RPQ_DSTCM(value) ((GMAC_ST1RPQ_DSTCM_Msk & ((value) << GMAC_ST1RPQ_DSTCM_Pos))) +#define GMAC_ST1RPQ_UDPM_Pos 12 +#define GMAC_ST1RPQ_UDPM_Msk (0xffffu << GMAC_ST1RPQ_UDPM_Pos) /**< \brief (GMAC_ST1RPQ[4]) UDP Port Match */ +#define GMAC_ST1RPQ_UDPM(value) ((GMAC_ST1RPQ_UDPM_Msk & ((value) << GMAC_ST1RPQ_UDPM_Pos))) +#define GMAC_ST1RPQ_DSTCE (0x1u << 28) /**< \brief (GMAC_ST1RPQ[4]) Differentiated Services or Traffic Class Match Enable */ +#define GMAC_ST1RPQ_UDPE (0x1u << 29) /**< \brief (GMAC_ST1RPQ[4]) UDP Port Match Enable */ +/* -------- GMAC_ST2RPQ[8] : (GMAC Offset: 0x540) Screening Type 2 Register Priority Queue (index = 0) -------- */ +#define GMAC_ST2RPQ_QNB_Pos 0 +#define GMAC_ST2RPQ_QNB_Msk (0x7u << GMAC_ST2RPQ_QNB_Pos) /**< \brief (GMAC_ST2RPQ[8]) Queue Number (0-2) */ +#define GMAC_ST2RPQ_QNB(value) ((GMAC_ST2RPQ_QNB_Msk & ((value) << GMAC_ST2RPQ_QNB_Pos))) +#define GMAC_ST2RPQ_VLANP_Pos 4 +#define GMAC_ST2RPQ_VLANP_Msk (0x7u << GMAC_ST2RPQ_VLANP_Pos) /**< \brief (GMAC_ST2RPQ[8]) VLAN Priority */ +#define GMAC_ST2RPQ_VLANP(value) ((GMAC_ST2RPQ_VLANP_Msk & ((value) << GMAC_ST2RPQ_VLANP_Pos))) +#define GMAC_ST2RPQ_VLANE (0x1u << 8) /**< \brief (GMAC_ST2RPQ[8]) VLAN Enable */ +#define GMAC_ST2RPQ_I2ETH_Pos 9 +#define GMAC_ST2RPQ_I2ETH_Msk (0x7u << GMAC_ST2RPQ_I2ETH_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 EtherType register x */ +#define GMAC_ST2RPQ_I2ETH(value) ((GMAC_ST2RPQ_I2ETH_Msk & ((value) << GMAC_ST2RPQ_I2ETH_Pos))) +#define GMAC_ST2RPQ_ETHE (0x1u << 12) /**< \brief (GMAC_ST2RPQ[8]) EtherType Enable */ +#define GMAC_ST2RPQ_COMPA_Pos 13 +#define GMAC_ST2RPQ_COMPA_Msk (0x1fu << GMAC_ST2RPQ_COMPA_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 Compare Word 0/Word 1 register x */ +#define GMAC_ST2RPQ_COMPA(value) ((GMAC_ST2RPQ_COMPA_Msk & ((value) << GMAC_ST2RPQ_COMPA_Pos))) +#define GMAC_ST2RPQ_COMPAE (0x1u << 18) /**< \brief (GMAC_ST2RPQ[8]) Compare A Enable */ +#define GMAC_ST2RPQ_COMPB_Pos 19 +#define GMAC_ST2RPQ_COMPB_Msk (0x1fu << GMAC_ST2RPQ_COMPB_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 Compare Word 0/Word 1 register x */ +#define GMAC_ST2RPQ_COMPB(value) ((GMAC_ST2RPQ_COMPB_Msk & ((value) << GMAC_ST2RPQ_COMPB_Pos))) +#define GMAC_ST2RPQ_COMPBE (0x1u << 24) /**< \brief (GMAC_ST2RPQ[8]) Compare B Enable */ +#define GMAC_ST2RPQ_COMPC_Pos 25 +#define GMAC_ST2RPQ_COMPC_Msk (0x1fu << GMAC_ST2RPQ_COMPC_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 Compare Word 0/Word 1 register x */ +#define GMAC_ST2RPQ_COMPC(value) ((GMAC_ST2RPQ_COMPC_Msk & ((value) << GMAC_ST2RPQ_COMPC_Pos))) +#define GMAC_ST2RPQ_COMPCE (0x1u << 30) /**< \brief (GMAC_ST2RPQ[8]) Compare C Enable */ +/* -------- GMAC_IERPQ[3] : (GMAC Offset: 0x600) Interrupt Enable Register Priority Queue (index = 1) -------- */ +#define GMAC_IERPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IERPQ[3]) Receive Complete */ +#define GMAC_IERPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IERPQ[3]) RX Used Bit Read */ +#define GMAC_IERPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IERPQ[3]) Retry Limit Exceeded or Late Collision */ +#define GMAC_IERPQ_TFC (0x1u << 6) /**< \brief (GMAC_IERPQ[3]) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IERPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IERPQ[3]) Transmit Complete */ +#define GMAC_IERPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IERPQ[3]) Receive Overrun */ +#define GMAC_IERPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IERPQ[3]) HRESP Not OK */ +/* -------- GMAC_IDRPQ[3] : (GMAC Offset: 0x620) Interrupt Disable Register Priority Queue (index = 1) -------- */ +#define GMAC_IDRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IDRPQ[3]) Receive Complete */ +#define GMAC_IDRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IDRPQ[3]) RX Used Bit Read */ +#define GMAC_IDRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IDRPQ[3]) Retry Limit Exceeded or Late Collision */ +#define GMAC_IDRPQ_TFC (0x1u << 6) /**< \brief (GMAC_IDRPQ[3]) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IDRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IDRPQ[3]) Transmit Complete */ +#define GMAC_IDRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IDRPQ[3]) Receive Overrun */ +#define GMAC_IDRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IDRPQ[3]) HRESP Not OK */ +/* -------- GMAC_IMRPQ[3] : (GMAC Offset: 0x640) Interrupt Mask Register Priority Queue (index = 1) -------- */ +#define GMAC_IMRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IMRPQ[3]) Receive Complete */ +#define GMAC_IMRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IMRPQ[3]) RX Used Bit Read */ +#define GMAC_IMRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IMRPQ[3]) Retry Limit Exceeded or Late Collision */ +#define GMAC_IMRPQ_AHB (0x1u << 6) /**< \brief (GMAC_IMRPQ[3]) AHB Error */ +#define GMAC_IMRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IMRPQ[3]) Transmit Complete */ +#define GMAC_IMRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IMRPQ[3]) Receive Overrun */ +#define GMAC_IMRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IMRPQ[3]) HRESP Not OK */ +/* -------- GMAC_ST2ER[4] : (GMAC Offset: 0x6E0) Screening Type 2 Ethertype Register (index = 0) -------- */ +#define GMAC_ST2ER_COMPVAL_Pos 0 +#define GMAC_ST2ER_COMPVAL_Msk (0xffffu << GMAC_ST2ER_COMPVAL_Pos) /**< \brief (GMAC_ST2ER[4]) Ethertype Compare Value */ +#define GMAC_ST2ER_COMPVAL(value) ((GMAC_ST2ER_COMPVAL_Msk & ((value) << GMAC_ST2ER_COMPVAL_Pos))) + +/* -------- GMAC_ST2COM0[32] : (GMAC Offset: 0x700) Type2 Compare # x, Word 0 -------- */ +#define GMAC_ST2COM0_2BMASK_Pos 0 +#define GMAC_ST2COM0_2BMASK_Msk (0xffffu << GMAC_ST2COM0_2BMASK_Pos) /**< 2-byte Mask Value */ +#define GMAC_ST2COM0_2BMASK(value) ((GMAC_ST2COM0_2BMASK_Msk & ((value) << GMAC_ST2COM0_2BMASK_Pos))) +#define GMAC_ST2COM0_2BCOMP_Pos 16 +#define GMAC_ST2COM0_2BCOMP_Msk (0xffffu << GMAC_ST2COM0_2BCOMP_Pos) /**< 2-byte Compare Value */ +#define GMAC_ST2COM0_2BCOMP(value) ((GMAC_ST2COM0_2BCOMP_Msk & ((value) << GMAC_ST2COM0_2BCOMP_Pos))) +/* -------- GMAC_ST2COM1[32] : (GMAC Offset: 0x704) Type2 Compare # x, Word 1 -------- */ +#define GMAC_ST2COM1_OFFSET_Pos 0 +#define GMAC_ST2COM1_OFFSET_Msk (0x3fu << GMAC_ST2COM1_OFFSET_Pos) /**< Offset value in bytes */ +#define GMAC_ST2COM1_OFFSET(value) ((GMAC_ST2COM1_OFFSET_Msk & ((value) << GMAC_ST2COM1_OFFSET_Pos))) +#define GMAC_ST2COM1_OFFSET_TYPE_Pos 7 +#define GMAC_ST2COM1_OFFSET_TYPE_Msk (0x3u << GMAC_ST2COM1_OFFSET_TYPE_Pos) /**< Offset start location type */ +#define GMAC_ST2COM1_OFFSET_TYPE(value) ((GMAC_ST2COM1_OFFSET_TYPE_Msk & ((value) << GMAC_ST2COM1_OFFSET_TYPE_Pos))) + +/*@}*/ + + +#endif /* _SAMV71_GMAC_COMPONENT_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_gpbr.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_gpbr.h new file mode 100644 index 00000000..f77042ce --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_gpbr.h @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_GPBR_COMPONENT_ +#define _SAMV71_GPBR_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR General Purpose Backup Registers */ +/* ============================================================================= */ +/** \addtogroup SAMV71_GPBR General Purpose Backup Registers */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Gpbr hardware registers */ +typedef struct { + __IO uint32_t SYS_GPBR[8]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */ +} Gpbr; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SYS_GPBR[8] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */ +#define SYS_GPBR_GPBR_VALUE_Pos 0 +#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[8]) Value of GPBR x */ +#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos))) + +/*@}*/ + + +#endif /* _SAMV71_GPBR_COMPONENT_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_hsmci.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_hsmci.h new file mode 100644 index 00000000..52c3f74f --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_hsmci.h @@ -0,0 +1,335 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_HSMCI_COMPONENT_ +#define _SAMV71_HSMCI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */ +/* ============================================================================= */ +/** \addtogroup SAMV71_HSMCI High Speed MultiMedia Card Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Hsmci hardware registers */ +typedef struct { + __O uint32_t HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */ + __IO uint32_t HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */ + __IO uint32_t HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */ + __IO uint32_t HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */ + __IO uint32_t HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */ + __O uint32_t HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */ + __IO uint32_t HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */ + __IO uint32_t HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */ + __I uint32_t HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */ + __I uint32_t HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */ + __O uint32_t HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */ + __I uint32_t Reserved1[2]; + __I uint32_t HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */ + __O uint32_t HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */ + __O uint32_t HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */ + __I uint32_t HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */ + __IO uint32_t HSMCI_DMA; /**< \brief (Hsmci Offset: 0x50) DMA Configuration Register */ + __IO uint32_t HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */ + __I uint32_t Reserved2[35]; + __IO uint32_t HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved3[69]; + __IO uint32_t HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */ +} Hsmci; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */ +#define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */ +#define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */ +#define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */ +#define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */ +#define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */ +/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */ +#define HSMCI_MR_CLKDIV_Pos 0 +#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */ +#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos))) +#define HSMCI_MR_PWSDIV_Pos 8 +#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */ +#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos))) +#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR) Read Proof Enable */ +#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR) Write Proof Enable */ +#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */ +#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */ +#define HSMCI_MR_CLKODD (0x1u << 16) /**< \brief (HSMCI_MR) Clock divider is odd */ +/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */ +#define HSMCI_DTOR_DTOCYC_Pos 0 +#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */ +#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos))) +#define HSMCI_DTOR_DTOMUL_Pos 4 +#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */ +#define HSMCI_DTOR_DTOMUL(value) ((HSMCI_DTOR_DTOMUL_Msk & ((value) << HSMCI_DTOR_DTOMUL_Pos))) +#define HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */ +#define HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */ +#define HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */ +#define HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */ +#define HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */ +#define HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */ +#define HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */ +#define HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */ +/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */ +#define HSMCI_SDCR_SDCSEL_Pos 0 +#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */ +#define HSMCI_SDCR_SDCSEL(value) ((HSMCI_SDCR_SDCSEL_Msk & ((value) << HSMCI_SDCR_SDCSEL_Pos))) +#define HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */ +#define HSMCI_SDCR_SDCBUS_Pos 6 +#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */ +#define HSMCI_SDCR_SDCBUS(value) ((HSMCI_SDCR_SDCBUS_Msk & ((value) << HSMCI_SDCR_SDCBUS_Pos))) +#define HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */ +#define HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bits */ +#define HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bits */ +/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */ +#define HSMCI_ARGR_ARG_Pos 0 +#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */ +#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos))) +/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */ +#define HSMCI_CMDR_CMDNB_Pos 0 +#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */ +#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos))) +#define HSMCI_CMDR_RSPTYP_Pos 6 +#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */ +#define HSMCI_CMDR_RSPTYP(value) ((HSMCI_CMDR_RSPTYP_Msk & ((value) << HSMCI_CMDR_RSPTYP_Pos))) +#define HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response */ +#define HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response */ +#define HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response */ +#define HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */ +#define HSMCI_CMDR_SPCMD_Pos 8 +#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */ +#define HSMCI_CMDR_SPCMD(value) ((HSMCI_CMDR_SPCMD_Msk & ((value) << HSMCI_CMDR_SPCMD_Pos))) +#define HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */ +#define HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */ +#define HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */ +#define HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */ +#define HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */ +#define HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */ +#define HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */ +#define HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */ +#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */ +#define HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */ +#define HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */ +#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */ +#define HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */ +#define HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */ +#define HSMCI_CMDR_TRCMD_Pos 16 +#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */ +#define HSMCI_CMDR_TRCMD(value) ((HSMCI_CMDR_TRCMD_Msk & ((value) << HSMCI_CMDR_TRCMD_Pos))) +#define HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */ +#define HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */ +#define HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */ +#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */ +#define HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */ +#define HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */ +#define HSMCI_CMDR_TRTYP_Pos 19 +#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */ +#define HSMCI_CMDR_TRTYP(value) ((HSMCI_CMDR_TRTYP_Msk & ((value) << HSMCI_CMDR_TRTYP_Pos))) +#define HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SD Card Single Block */ +#define HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SD Card Multiple Block */ +#define HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */ +#define HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */ +#define HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */ +#define HSMCI_CMDR_IOSPCMD_Pos 24 +#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */ +#define HSMCI_CMDR_IOSPCMD(value) ((HSMCI_CMDR_IOSPCMD_Msk & ((value) << HSMCI_CMDR_IOSPCMD_Pos))) +#define HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */ +#define HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */ +#define HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */ +#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */ +#define HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */ +#define HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */ +#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge */ +/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */ +#define HSMCI_BLKR_BCNT_Pos 0 +#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */ +#define HSMCI_BLKR_BCNT(value) ((HSMCI_BLKR_BCNT_Msk & ((value) << HSMCI_BLKR_BCNT_Pos))) +#define HSMCI_BLKR_BLKLEN_Pos 16 +#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */ +#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos))) +/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */ +#define HSMCI_CSTOR_CSTOCYC_Pos 0 +#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */ +#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos))) +#define HSMCI_CSTOR_CSTOMUL_Pos 4 +#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */ +#define HSMCI_CSTOR_CSTOMUL(value) ((HSMCI_CSTOR_CSTOMUL_Msk & ((value) << HSMCI_CSTOR_CSTOMUL_Pos))) +#define HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */ +#define HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */ +#define HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */ +#define HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */ +#define HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */ +#define HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */ +#define HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */ +#define HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */ +/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */ +#define HSMCI_RSPR_RSP_Pos 0 +#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */ +/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */ +#define HSMCI_RDR_DATA_Pos 0 +#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */ +/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */ +#define HSMCI_TDR_DATA_Pos 0 +#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */ +#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos))) +/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */ +#define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready (cleared by reading HSMCI_RDR) */ +#define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready (cleared by writing in HSMCI_TDR) */ +#define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended (cleared on read) */ +#define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress (cleared at the end of CRC16 calculation) */ +#define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */ +#define HSMCI_SR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A (cleared on read) */ +#define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */ +#define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received (cleared on read) */ +#define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error (cleared on read) */ +#define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error (cleared on read) */ +#define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error (cleared on read) */ +#define HSMCI_SR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_SR) DMA Block Overrun Error (cleared on read) */ +#define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */ +#define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */ +#define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received (cleared on read) */ +#define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error (cleared on read) */ +#define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) */ +#define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) */ +/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */ +#define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */ +#define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */ +#define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */ +#define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */ +#define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */ +#define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */ +#define HSMCI_IER_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */ +#define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */ +#define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */ +#define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */ +#define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */ +#define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */ +#define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */ +#define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */ +#define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */ +#define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */ +#define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */ +#define HSMCI_IER_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IER) DMA Block Overrun Error Interrupt Enable */ +#define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */ +#define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */ +#define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */ +#define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */ +#define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */ +#define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */ +/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */ +#define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */ +#define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */ +#define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */ +#define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */ +#define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */ +#define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */ +#define HSMCI_IDR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */ +#define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */ +#define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */ +#define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */ +#define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */ +#define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */ +#define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */ +#define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */ +#define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */ +#define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */ +#define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */ +#define HSMCI_IDR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable */ +#define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */ +#define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */ +#define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */ +#define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */ +#define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */ +#define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */ +/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */ +#define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */ +#define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */ +#define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */ +#define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */ +#define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */ +#define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */ +#define HSMCI_IMR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */ +#define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */ +#define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */ +#define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */ +#define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */ +#define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */ +#define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */ +#define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */ +#define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */ +#define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */ +#define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */ +#define HSMCI_IMR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask */ +#define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */ +#define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */ +#define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */ +#define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */ +#define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */ +#define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */ +/* -------- HSMCI_DMA : (HSMCI Offset: 0x50) DMA Configuration Register -------- */ +#define HSMCI_DMA_CHKSIZE_Pos 4 +#define HSMCI_DMA_CHKSIZE_Msk (0x7u << HSMCI_DMA_CHKSIZE_Pos) /**< \brief (HSMCI_DMA) DMA Channel Read and Write Chunk Size */ +#define HSMCI_DMA_CHKSIZE(value) ((HSMCI_DMA_CHKSIZE_Msk & ((value) << HSMCI_DMA_CHKSIZE_Pos))) +#define HSMCI_DMA_CHKSIZE_1 (0x0u << 4) /**< \brief (HSMCI_DMA) 1 data available */ +#define HSMCI_DMA_CHKSIZE_2 (0x1u << 4) /**< \brief (HSMCI_DMA) 2 data available */ +#define HSMCI_DMA_CHKSIZE_4 (0x2u << 4) /**< \brief (HSMCI_DMA) 4 data available */ +#define HSMCI_DMA_CHKSIZE_8 (0x3u << 4) /**< \brief (HSMCI_DMA) 8 data available */ +#define HSMCI_DMA_CHKSIZE_16 (0x4u << 4) /**< \brief (HSMCI_DMA) 16 data available */ +#define HSMCI_DMA_DMAEN (0x1u << 8) /**< \brief (HSMCI_DMA) DMA Hardware Handshaking Enable */ +/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */ +#define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */ +#define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */ +#define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */ +#define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */ +/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */ +#define HSMCI_WPMR_WPEN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protect Enable */ +#define HSMCI_WPMR_WPKEY_Pos 8 +#define HSMCI_WPMR_WPKEY_Msk (0xffffffu << HSMCI_WPMR_WPKEY_Pos) /**< \brief (HSMCI_WPMR) Write Protect Key */ +#define HSMCI_WPMR_WPKEY(value) ((HSMCI_WPMR_WPKEY_Msk & ((value) << HSMCI_WPMR_WPKEY_Pos))) +#define HSMCI_WPMR_WPKEY_PASSWD (0x4D4349u << 8) /**< \brief (HSMCI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */ +#define HSMCI_WPSR_WPVS (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */ +#define HSMCI_WPSR_WPVSRC_Pos 8 +#define HSMCI_WPSR_WPVSRC_Msk (0xffffu << HSMCI_WPSR_WPVSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Source */ +/* -------- HSMCI_FIFO[256] : (HSMCI Offset: 0x200) FIFO Memory Aperture0 -------- */ +#define HSMCI_FIFO_DATA_Pos 0 +#define HSMCI_FIFO_DATA_Msk (0xffffffffu << HSMCI_FIFO_DATA_Pos) /**< \brief (HSMCI_FIFO[256]) Data to Read or Data to Write */ +#define HSMCI_FIFO_DATA(value) ((HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos))) + +/*@}*/ + + +#endif /* _SAMV71_HSMCI_COMPONENT_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_icm.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_icm.h new file mode 100644 index 00000000..0aa35989 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_icm.h @@ -0,0 +1,192 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_ICM_COMPONENT_ +#define _SAMV71_ICM_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Integrity Check Monitor */ +/* ============================================================================= */ +/** \addtogroup SAMV71_ICM Integrity Check Monitor */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Icm hardware registers */ +typedef struct { + __IO uint32_t ICM_CFG; /**< \brief (Icm Offset: 0x00) Configuration Register */ + __O uint32_t ICM_CTRL; /**< \brief (Icm Offset: 0x04) Control Register */ + __O uint32_t ICM_SR; /**< \brief (Icm Offset: 0x08) Status Register */ + __I uint32_t Reserved1[1]; + __O uint32_t ICM_IER; /**< \brief (Icm Offset: 0x10) Interrupt Enable Register */ + __O uint32_t ICM_IDR; /**< \brief (Icm Offset: 0x14) Interrupt Disable Register */ + __I uint32_t ICM_IMR; /**< \brief (Icm Offset: 0x18) Interrupt Mask Register */ + __I uint32_t ICM_ISR; /**< \brief (Icm Offset: 0x1C) Interrupt Status Register */ + __I uint32_t ICM_UASR; /**< \brief (Icm Offset: 0x20) Undefined Access Status Register */ + __I uint32_t Reserved2[3]; + __IO uint32_t ICM_DSCR; /**< \brief (Icm Offset: 0x30) Region Descriptor Area Start Address Register */ + __IO uint32_t ICM_HASH; /**< \brief (Icm Offset: 0x34) Region Hash Area Start Address Register */ + __O uint32_t ICM_UIHVAL[8]; /**< \brief (Icm Offset: 0x38) User Initial Hash Value 0 Register */ +} Icm; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- ICM_CFG : (ICM Offset: 0x00) Configuration Register -------- */ +#define ICM_CFG_WBDIS (0x1u << 0) /**< \brief (ICM_CFG) Write Back Disable */ +#define ICM_CFG_EOMDIS (0x1u << 1) /**< \brief (ICM_CFG) End of Monitoring Disable */ +#define ICM_CFG_SLBDIS (0x1u << 2) /**< \brief (ICM_CFG) Secondary List Branching Disable */ +#define ICM_CFG_BBC_Pos 4 +#define ICM_CFG_BBC_Msk (0xfu << ICM_CFG_BBC_Pos) /**< \brief (ICM_CFG) Bus Burden Control */ +#define ICM_CFG_BBC(value) ((ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos))) +#define ICM_CFG_ASCD (0x1u << 8) /**< \brief (ICM_CFG) Automatic Switch To Compare Digest */ +#define ICM_CFG_DUALBUFF (0x1u << 9) /**< \brief (ICM_CFG) Dual Input Buffer */ +#define ICM_CFG_UIHASH (0x1u << 12) /**< \brief (ICM_CFG) User Initial Hash Value */ +#define ICM_CFG_UALGO_Pos 13 +#define ICM_CFG_UALGO_Msk (0x7u << ICM_CFG_UALGO_Pos) /**< \brief (ICM_CFG) User SHA Algorithm */ +#define ICM_CFG_UALGO(value) ((ICM_CFG_UALGO_Msk & ((value) << ICM_CFG_UALGO_Pos))) +#define ICM_CFG_UALGO_SHA1 (0x0u << 13) /**< \brief (ICM_CFG) SHA1 algorithm processed */ +#define ICM_CFG_UALGO_SHA256 (0x1u << 13) /**< \brief (ICM_CFG) SHA256 algorithm processed */ +#define ICM_CFG_UALGO_SHA224 (0x4u << 13) /**< \brief (ICM_CFG) SHA224 algorithm processed */ +#define ICM_CFG_HAPROT_Pos 16 +#define ICM_CFG_HAPROT_Msk (0x3fu << ICM_CFG_HAPROT_Pos) /**< \brief (ICM_CFG) Region Hash Area Protection */ +#define ICM_CFG_HAPROT(value) ((ICM_CFG_HAPROT_Msk & ((value) << ICM_CFG_HAPROT_Pos))) +#define ICM_CFG_DAPROT_Pos 24 +#define ICM_CFG_DAPROT_Msk (0x3fu << ICM_CFG_DAPROT_Pos) /**< \brief (ICM_CFG) Region Descriptor Area Protection */ +#define ICM_CFG_DAPROT(value) ((ICM_CFG_DAPROT_Msk & ((value) << ICM_CFG_DAPROT_Pos))) +/* -------- ICM_CTRL : (ICM Offset: 0x04) Control Register -------- */ +#define ICM_CTRL_ENABLE (0x1u << 0) /**< \brief (ICM_CTRL) ICM Enable */ +#define ICM_CTRL_DISABLE (0x1u << 1) /**< \brief (ICM_CTRL) ICM Disable Register */ +#define ICM_CTRL_SWRST (0x1u << 2) /**< \brief (ICM_CTRL) Software Reset */ +#define ICM_CTRL_REHASH_Pos 4 +#define ICM_CTRL_REHASH_Msk (0xfu << ICM_CTRL_REHASH_Pos) /**< \brief (ICM_CTRL) Recompute Internal Hash */ +#define ICM_CTRL_REHASH(value) ((ICM_CTRL_REHASH_Msk & ((value) << ICM_CTRL_REHASH_Pos))) +#define ICM_CTRL_RMDIS_Pos 8 +#define ICM_CTRL_RMDIS_Msk (0xfu << ICM_CTRL_RMDIS_Pos) /**< \brief (ICM_CTRL) Region Monitoring Disable */ +#define ICM_CTRL_RMDIS(value) ((ICM_CTRL_RMDIS_Msk & ((value) << ICM_CTRL_RMDIS_Pos))) +#define ICM_CTRL_RMEN_Pos 12 +#define ICM_CTRL_RMEN_Msk (0xfu << ICM_CTRL_RMEN_Pos) /**< \brief (ICM_CTRL) Region Monitoring Enable */ +#define ICM_CTRL_RMEN(value) ((ICM_CTRL_RMEN_Msk & ((value) << ICM_CTRL_RMEN_Pos))) +/* -------- ICM_SR : (ICM Offset: 0x08) Status Register -------- */ +#define ICM_SR_ENABLE (0x1u << 0) /**< \brief (ICM_SR) ICM Controller Enable Register */ +#define ICM_SR_RAWRMDIS_Pos 8 +#define ICM_SR_RAWRMDIS_Msk (0xfu << ICM_SR_RAWRMDIS_Pos) /**< \brief (ICM_SR) RAW Region Monitoring Disabled Status */ +#define ICM_SR_RAWRMDIS(value) ((ICM_SR_RAWRMDIS_Msk & ((value) << ICM_SR_RAWRMDIS_Pos))) +#define ICM_SR_RMDIS_Pos 12 +#define ICM_SR_RMDIS_Msk (0xfu << ICM_SR_RMDIS_Pos) /**< \brief (ICM_SR) Region Monitoring Disabled Status */ +#define ICM_SR_RMDIS(value) ((ICM_SR_RMDIS_Msk & ((value) << ICM_SR_RMDIS_Pos))) +/* -------- ICM_IER : (ICM Offset: 0x10) Interrupt Enable Register -------- */ +#define ICM_IER_RHC_Pos 0 +#define ICM_IER_RHC_Msk (0xfu << ICM_IER_RHC_Pos) /**< \brief (ICM_IER) Region Hash Completed Interrupt Enable */ +#define ICM_IER_RHC(value) ((ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos))) +#define ICM_IER_RDM_Pos 4 +#define ICM_IER_RDM_Msk (0xfu << ICM_IER_RDM_Pos) /**< \brief (ICM_IER) Region Digest Mismatch Interrupt Enable */ +#define ICM_IER_RDM(value) ((ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos))) +#define ICM_IER_RBE_Pos 8 +#define ICM_IER_RBE_Msk (0xfu << ICM_IER_RBE_Pos) /**< \brief (ICM_IER) Region Bus Error Interrupt Enable */ +#define ICM_IER_RBE(value) ((ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos))) +#define ICM_IER_RWC_Pos 12 +#define ICM_IER_RWC_Msk (0xfu << ICM_IER_RWC_Pos) /**< \brief (ICM_IER) Region Wrap Condition detected Interrupt Enable */ +#define ICM_IER_RWC(value) ((ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos))) +#define ICM_IER_REC_Pos 16 +#define ICM_IER_REC_Msk (0xfu << ICM_IER_REC_Pos) /**< \brief (ICM_IER) Region End bit Condition Detected Interrupt Enable */ +#define ICM_IER_REC(value) ((ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos))) +#define ICM_IER_RSU_Pos 20 +#define ICM_IER_RSU_Msk (0xfu << ICM_IER_RSU_Pos) /**< \brief (ICM_IER) Region Status Updated Interrupt Disable */ +#define ICM_IER_RSU(value) ((ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos))) +#define ICM_IER_URAD (0x1u << 24) /**< \brief (ICM_IER) Undefined Register Access Detection Interrupt Enable */ +/* -------- ICM_IDR : (ICM Offset: 0x14) Interrupt Disable Register -------- */ +#define ICM_IDR_RHC_Pos 0 +#define ICM_IDR_RHC_Msk (0xfu << ICM_IDR_RHC_Pos) /**< \brief (ICM_IDR) Region Hash Completed Interrupt Disable */ +#define ICM_IDR_RHC(value) ((ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos))) +#define ICM_IDR_RDM_Pos 4 +#define ICM_IDR_RDM_Msk (0xfu << ICM_IDR_RDM_Pos) /**< \brief (ICM_IDR) Region Digest Mismatch Interrupt Disable */ +#define ICM_IDR_RDM(value) ((ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos))) +#define ICM_IDR_RBE_Pos 8 +#define ICM_IDR_RBE_Msk (0xfu << ICM_IDR_RBE_Pos) /**< \brief (ICM_IDR) Region Bus Error Interrupt Disable */ +#define ICM_IDR_RBE(value) ((ICM_IDR_RBE_Msk & ((value) << ICM_IDR_RBE_Pos))) +#define ICM_IDR_RWC_Pos 12 +#define ICM_IDR_RWC_Msk (0xfu << ICM_IDR_RWC_Pos) /**< \brief (ICM_IDR) Region Wrap Condition Detected Interrupt Disable */ +#define ICM_IDR_RWC(value) ((ICM_IDR_RWC_Msk & ((value) << ICM_IDR_RWC_Pos))) +#define ICM_IDR_REC_Pos 16 +#define ICM_IDR_REC_Msk (0xfu << ICM_IDR_REC_Pos) /**< \brief (ICM_IDR) Region End bit Condition detected Interrupt Disable */ +#define ICM_IDR_REC(value) ((ICM_IDR_REC_Msk & ((value) << ICM_IDR_REC_Pos))) +#define ICM_IDR_RSU_Pos 20 +#define ICM_IDR_RSU_Msk (0xfu << ICM_IDR_RSU_Pos) /**< \brief (ICM_IDR) Region Status Updated Interrupt Disable */ +#define ICM_IDR_RSU(value) ((ICM_IDR_RSU_Msk & ((value) << ICM_IDR_RSU_Pos))) +#define ICM_IDR_URAD (0x1u << 24) /**< \brief (ICM_IDR) Undefined Register Access Detection Interrupt Disable */ +/* -------- ICM_IMR : (ICM Offset: 0x18) Interrupt Mask Register -------- */ +#define ICM_IMR_RHC_Pos 0 +#define ICM_IMR_RHC_Msk (0xfu << ICM_IMR_RHC_Pos) /**< \brief (ICM_IMR) Region Hash Completed Interrupt Mask */ +#define ICM_IMR_RDM_Pos 4 +#define ICM_IMR_RDM_Msk (0xfu << ICM_IMR_RDM_Pos) /**< \brief (ICM_IMR) Region Digest Mismatch Interrupt Mask */ +#define ICM_IMR_RBE_Pos 8 +#define ICM_IMR_RBE_Msk (0xfu << ICM_IMR_RBE_Pos) /**< \brief (ICM_IMR) Region Bus Error Interrupt Mask */ +#define ICM_IMR_RWC_Pos 12 +#define ICM_IMR_RWC_Msk (0xfu << ICM_IMR_RWC_Pos) /**< \brief (ICM_IMR) Region Wrap Condition Detected Interrupt Mask */ +#define ICM_IMR_REC_Pos 16 +#define ICM_IMR_REC_Msk (0xfu << ICM_IMR_REC_Pos) /**< \brief (ICM_IMR) Region End bit Condition Detected Interrupt Mask */ +#define ICM_IMR_RSU_Pos 20 +#define ICM_IMR_RSU_Msk (0xfu << ICM_IMR_RSU_Pos) /**< \brief (ICM_IMR) Region Status Updated Interrupt Mask */ +#define ICM_IMR_URAD (0x1u << 24) /**< \brief (ICM_IMR) Undefined Register Access Detection Interrupt Mask */ +/* -------- ICM_ISR : (ICM Offset: 0x1C) Interrupt Status Register -------- */ +#define ICM_ISR_RHC_Pos 0 +#define ICM_ISR_RHC_Msk (0xfu << ICM_ISR_RHC_Pos) /**< \brief (ICM_ISR) Region Hash Completed */ +#define ICM_ISR_RDM_Pos 4 +#define ICM_ISR_RDM_Msk (0xfu << ICM_ISR_RDM_Pos) /**< \brief (ICM_ISR) Region Digest Mismatch */ +#define ICM_ISR_RBE_Pos 8 +#define ICM_ISR_RBE_Msk (0xfu << ICM_ISR_RBE_Pos) /**< \brief (ICM_ISR) Region Bus Error */ +#define ICM_ISR_RWC_Pos 12 +#define ICM_ISR_RWC_Msk (0xfu << ICM_ISR_RWC_Pos) /**< \brief (ICM_ISR) Region Wrap Condition Detected */ +#define ICM_ISR_REC_Pos 16 +#define ICM_ISR_REC_Msk (0xfu << ICM_ISR_REC_Pos) /**< \brief (ICM_ISR) Region End bit Condition Detected */ +#define ICM_ISR_RSU_Pos 20 +#define ICM_ISR_RSU_Msk (0xfu << ICM_ISR_RSU_Pos) /**< \brief (ICM_ISR) Region Status Updated Detected */ +#define ICM_ISR_URAD (0x1u << 24) /**< \brief (ICM_ISR) Undefined Register Access Detection Status */ +/* -------- ICM_UASR : (ICM Offset: 0x20) Undefined Access Status Register -------- */ +#define ICM_UASR_URAT_Pos 0 +#define ICM_UASR_URAT_Msk (0x7u << ICM_UASR_URAT_Pos) /**< \brief (ICM_UASR) Undefined Register Access Trace */ +#define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER (0x0u << 0) /**< \brief (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded. */ +#define ICM_UASR_URAT_ICM_CFG_MODIFIED (0x1u << 0) /**< \brief (ICM_UASR) ICM_CFG modified during active monitoring. */ +#define ICM_UASR_URAT_ICM_DSCR_MODIFIED (0x2u << 0) /**< \brief (ICM_UASR) ICM_DSCR modified during active monitoring. */ +#define ICM_UASR_URAT_ICM_HASH_MODIFIED (0x3u << 0) /**< \brief (ICM_UASR) ICM_HASH modified during active monitoring */ +#define ICM_UASR_URAT_READ_ACCESS (0x4u << 0) /**< \brief (ICM_UASR) Write-only register read access */ +/* -------- ICM_DSCR : (ICM Offset: 0x30) Region Descriptor Area Start Address Register -------- */ +#define ICM_DSCR_DASA_Pos 6 +#define ICM_DSCR_DASA_Msk (0x3ffffffu << ICM_DSCR_DASA_Pos) /**< \brief (ICM_DSCR) Descriptor Area Start Address */ +#define ICM_DSCR_DASA(value) ((ICM_DSCR_DASA_Msk & ((value) << ICM_DSCR_DASA_Pos))) +/* -------- ICM_HASH : (ICM Offset: 0x34) Region Hash Area Start Address Register -------- */ +#define ICM_HASH_HASA_Pos 7 +#define ICM_HASH_HASA_Msk (0x1ffffffu << ICM_HASH_HASA_Pos) /**< \brief (ICM_HASH) Hash Area Start Address */ +#define ICM_HASH_HASA(value) ((ICM_HASH_HASA_Msk & ((value) << ICM_HASH_HASA_Pos))) +/* -------- ICM_UIHVAL[8] : (ICM Offset: 0x38) User Initial Hash Value 0 Register -------- */ +#define ICM_UIHVAL_VAL_Pos 0 +#define ICM_UIHVAL_VAL_Msk (0xffffffffu << ICM_UIHVAL_VAL_Pos) /**< \brief (ICM_UIHVAL[8]) Initial Hash Value */ +#define ICM_UIHVAL_VAL(value) ((ICM_UIHVAL_VAL_Msk & ((value) << ICM_UIHVAL_VAL_Pos))) + +/*@}*/ + + +#endif /* _SAMV71_ICM_COMPONENT_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_isi.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_isi.h new file mode 100644 index 00000000..bcaebcb9 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_isi.h @@ -0,0 +1,280 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_ISI_COMPONENT_ +#define _SAMV71_ISI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Image Sensor Interface */ +/* ============================================================================= */ +/** \addtogroup SAMV71_ISI Image Sensor Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Isi hardware registers */ +typedef struct { + __IO uint32_t ISI_CFG1; /**< \brief (Isi Offset: 0x00) ISI Configuration 1 Register */ + __IO uint32_t ISI_CFG2; /**< \brief (Isi Offset: 0x04) ISI Configuration 2 Register */ + __IO uint32_t ISI_PSIZE; /**< \brief (Isi Offset: 0x08) ISI Preview Size Register */ + __IO uint32_t ISI_PDECF; /**< \brief (Isi Offset: 0x0C) ISI Preview Decimation Factor Register */ + __IO uint32_t ISI_Y2R_SET0; /**< \brief (Isi Offset: 0x10) ISI Color Space Conversion YCrCb To RGB Set 0 Register */ + __IO uint32_t ISI_Y2R_SET1; /**< \brief (Isi Offset: 0x14) ISI Color Space Conversion YCrCb To RGB Set 1 Register */ + __IO uint32_t ISI_R2Y_SET0; /**< \brief (Isi Offset: 0x18) ISI Color Space Conversion RGB To YCrCb Set 0 Register */ + __IO uint32_t ISI_R2Y_SET1; /**< \brief (Isi Offset: 0x1C) ISI Color Space Conversion RGB To YCrCb Set 1 Register */ + __IO uint32_t ISI_R2Y_SET2; /**< \brief (Isi Offset: 0x20) ISI Color Space Conversion RGB To YCrCb Set 2 Register */ + __O uint32_t ISI_CR; /**< \brief (Isi Offset: 0x24) ISI Control Register */ + __I uint32_t ISI_SR; /**< \brief (Isi Offset: 0x28) ISI Status Register */ + __O uint32_t ISI_IER; /**< \brief (Isi Offset: 0x2C) ISI Interrupt Enable Register */ + __O uint32_t ISI_IDR; /**< \brief (Isi Offset: 0x30) ISI Interrupt Disable Register */ + __I uint32_t ISI_IMR; /**< \brief (Isi Offset: 0x34) ISI Interrupt Mask Register */ + __O uint32_t ISI_DMA_CHER; /**< \brief (Isi Offset: 0x38) DMA Channel Enable Register */ + __O uint32_t ISI_DMA_CHDR; /**< \brief (Isi Offset: 0x3C) DMA Channel Disable Register */ + __I uint32_t ISI_DMA_CHSR; /**< \brief (Isi Offset: 0x40) DMA Channel Status Register */ + __IO uint32_t ISI_DMA_P_ADDR; /**< \brief (Isi Offset: 0x44) DMA Preview Base Address Register */ + __IO uint32_t ISI_DMA_P_CTRL; /**< \brief (Isi Offset: 0x48) DMA Preview Control Register */ + __IO uint32_t ISI_DMA_P_DSCR; /**< \brief (Isi Offset: 0x4C) DMA Preview Descriptor Address Register */ + __IO uint32_t ISI_DMA_C_ADDR; /**< \brief (Isi Offset: 0x50) DMA Codec Base Address Register */ + __IO uint32_t ISI_DMA_C_CTRL; /**< \brief (Isi Offset: 0x54) DMA Codec Control Register */ + __IO uint32_t ISI_DMA_C_DSCR; /**< \brief (Isi Offset: 0x58) DMA Codec Descriptor Address Register */ + __I uint32_t Reserved1[34]; + __IO uint32_t ISI_WPMR; /**< \brief (Isi Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t ISI_WPSR; /**< \brief (Isi Offset: 0xE8) Write Protection Status Register */ +} Isi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- ISI_CFG1 : (ISI Offset: 0x00) ISI Configuration 1 Register -------- */ +#define ISI_CFG1_HSYNC_POL (0x1u << 2) /**< \brief (ISI_CFG1) Horizontal Synchronization Polarity */ +#define ISI_CFG1_VSYNC_POL (0x1u << 3) /**< \brief (ISI_CFG1) Vertical Synchronization Polarity */ +#define ISI_CFG1_PIXCLK_POL (0x1u << 4) /**< \brief (ISI_CFG1) Pixel Clock Polarity */ +#define ISI_CFG1_EMB_SYNC (0x1u << 6) /**< \brief (ISI_CFG1) Embedded Synchronization */ +#define ISI_CFG1_CRC_SYNC (0x1u << 7) /**< \brief (ISI_CFG1) Embedded Synchronization Correction */ +#define ISI_CFG1_FRATE_Pos 8 +#define ISI_CFG1_FRATE_Msk (0x7u << ISI_CFG1_FRATE_Pos) /**< \brief (ISI_CFG1) Frame Rate [0..7] */ +#define ISI_CFG1_FRATE(value) ((ISI_CFG1_FRATE_Msk & ((value) << ISI_CFG1_FRATE_Pos))) +#define ISI_CFG1_DISCR (0x1u << 11) /**< \brief (ISI_CFG1) Disable Codec Request */ +#define ISI_CFG1_FULL (0x1u << 12) /**< \brief (ISI_CFG1) Full Mode is Allowed */ +#define ISI_CFG1_THMASK_Pos 13 +#define ISI_CFG1_THMASK_Msk (0x3u << ISI_CFG1_THMASK_Pos) /**< \brief (ISI_CFG1) Threshold Mask */ +#define ISI_CFG1_THMASK(value) ((ISI_CFG1_THMASK_Msk & ((value) << ISI_CFG1_THMASK_Pos))) +#define ISI_CFG1_THMASK_BEATS_4 (0x0u << 13) /**< \brief (ISI_CFG1) Only 4 beats AHB burst allowed */ +#define ISI_CFG1_THMASK_BEATS_8 (0x1u << 13) /**< \brief (ISI_CFG1) Only 4 and 8 beats AHB burst allowed */ +#define ISI_CFG1_THMASK_BEATS_16 (0x2u << 13) /**< \brief (ISI_CFG1) 4, 8 and 16 beats AHB burst allowed */ +#define ISI_CFG1_SLD_Pos 16 +#define ISI_CFG1_SLD_Msk (0xffu << ISI_CFG1_SLD_Pos) /**< \brief (ISI_CFG1) Start of Line Delay */ +#define ISI_CFG1_SLD(value) ((ISI_CFG1_SLD_Msk & ((value) << ISI_CFG1_SLD_Pos))) +#define ISI_CFG1_SFD_Pos 24 +#define ISI_CFG1_SFD_Msk (0xffu << ISI_CFG1_SFD_Pos) /**< \brief (ISI_CFG1) Start of Frame Delay */ +#define ISI_CFG1_SFD(value) ((ISI_CFG1_SFD_Msk & ((value) << ISI_CFG1_SFD_Pos))) +/* -------- ISI_CFG2 : (ISI Offset: 0x04) ISI Configuration 2 Register -------- */ +#define ISI_CFG2_IM_VSIZE_Pos 0 +#define ISI_CFG2_IM_VSIZE_Msk (0x7ffu << ISI_CFG2_IM_VSIZE_Pos) /**< \brief (ISI_CFG2) Vertical Size of the Image Sensor [0..2047] */ +#define ISI_CFG2_IM_VSIZE(value) ((ISI_CFG2_IM_VSIZE_Msk & ((value) << ISI_CFG2_IM_VSIZE_Pos))) +#define ISI_CFG2_GS_MODE (0x1u << 11) /**< \brief (ISI_CFG2) Grayscale Pixel Format Mode */ +#define ISI_CFG2_RGB_MODE (0x1u << 12) /**< \brief (ISI_CFG2) RGB Input Mode */ +#define ISI_CFG2_GRAYSCALE (0x1u << 13) /**< \brief (ISI_CFG2) Grayscale Mode Format Enable */ +#define ISI_CFG2_RGB_SWAP (0x1u << 14) /**< \brief (ISI_CFG2) RGB Format Swap Mode */ +#define ISI_CFG2_COL_SPACE (0x1u << 15) /**< \brief (ISI_CFG2) Color Space for the Image Data */ +#define ISI_CFG2_IM_HSIZE_Pos 16 +#define ISI_CFG2_IM_HSIZE_Msk (0x7ffu << ISI_CFG2_IM_HSIZE_Pos) /**< \brief (ISI_CFG2) Horizontal Size of the Image Sensor [0..2047] */ +#define ISI_CFG2_IM_HSIZE(value) ((ISI_CFG2_IM_HSIZE_Msk & ((value) << ISI_CFG2_IM_HSIZE_Pos))) +#define ISI_CFG2_YCC_SWAP_Pos 28 +#define ISI_CFG2_YCC_SWAP_Msk (0x3u << ISI_CFG2_YCC_SWAP_Pos) /**< \brief (ISI_CFG2) YCrCb Format Swap Mode */ +#define ISI_CFG2_YCC_SWAP(value) ((ISI_CFG2_YCC_SWAP_Msk & ((value) << ISI_CFG2_YCC_SWAP_Pos))) +#define ISI_CFG2_YCC_SWAP_DEFAULT (0x0u << 28) /**< \brief (ISI_CFG2) Byte 0 Cb(i)Byte 1 Y(i)Byte 2 Cr(i)Byte 3 Y(i+1) */ +#define ISI_CFG2_YCC_SWAP_MODE1 (0x1u << 28) /**< \brief (ISI_CFG2) Byte 0 Cr(i)Byte 1 Y(i)Byte 2 Cb(i)Byte 3 Y(i+1) */ +#define ISI_CFG2_YCC_SWAP_MODE2 (0x2u << 28) /**< \brief (ISI_CFG2) Byte 0 Y(i)Byte 1 Cb(i)Byte 2 Y(i+1)Byte 3 Cr(i) */ +#define ISI_CFG2_YCC_SWAP_MODE3 (0x3u << 28) /**< \brief (ISI_CFG2) Byte 0 Y(i)Byte 1 Cr(i)Byte 2 Y(i+1)Byte 3 Cb(i) */ +#define ISI_CFG2_RGB_CFG_Pos 30 +#define ISI_CFG2_RGB_CFG_Msk (0x3u << ISI_CFG2_RGB_CFG_Pos) /**< \brief (ISI_CFG2) RGB Pixel Mapping Configuration */ +#define ISI_CFG2_RGB_CFG(value) ((ISI_CFG2_RGB_CFG_Msk & ((value) << ISI_CFG2_RGB_CFG_Pos))) +#define ISI_CFG2_RGB_CFG_DEFAULT (0x0u << 30) /**< \brief (ISI_CFG2) Byte 0 R/G(MSB)Byte 1 G(LSB)/BByte 2 R/G(MSB)Byte 3 G(LSB)/B */ +#define ISI_CFG2_RGB_CFG_MODE1 (0x1u << 30) /**< \brief (ISI_CFG2) Byte 0 B/G(MSB)Byte 1 G(LSB)/RByte 2 B/G(MSB)Byte 3 G(LSB)/R */ +#define ISI_CFG2_RGB_CFG_MODE2 (0x2u << 30) /**< \brief (ISI_CFG2) Byte 0 G(LSB)/RByte 1 B/G(MSB)Byte 2 G(LSB)/RByte 3 B/G(MSB) */ +#define ISI_CFG2_RGB_CFG_MODE3 (0x3u << 30) /**< \brief (ISI_CFG2) Byte 0 G(LSB)/BByte 1 R/G(MSB)Byte 2 G(LSB)/BByte 3 R/G(MSB) */ +/* -------- ISI_PSIZE : (ISI Offset: 0x08) ISI Preview Size Register -------- */ +#define ISI_PSIZE_PREV_VSIZE_Pos 0 +#define ISI_PSIZE_PREV_VSIZE_Msk (0x3ffu << ISI_PSIZE_PREV_VSIZE_Pos) /**< \brief (ISI_PSIZE) Vertical Size for the Preview Path */ +#define ISI_PSIZE_PREV_VSIZE(value) ((ISI_PSIZE_PREV_VSIZE_Msk & ((value) << ISI_PSIZE_PREV_VSIZE_Pos))) +#define ISI_PSIZE_PREV_HSIZE_Pos 16 +#define ISI_PSIZE_PREV_HSIZE_Msk (0x3ffu << ISI_PSIZE_PREV_HSIZE_Pos) /**< \brief (ISI_PSIZE) Horizontal Size for the Preview Path */ +#define ISI_PSIZE_PREV_HSIZE(value) ((ISI_PSIZE_PREV_HSIZE_Msk & ((value) << ISI_PSIZE_PREV_HSIZE_Pos))) +/* -------- ISI_PDECF : (ISI Offset: 0x0C) ISI Preview Decimation Factor Register -------- */ +#define ISI_PDECF_DEC_FACTOR_Pos 0 +#define ISI_PDECF_DEC_FACTOR_Msk (0xffu << ISI_PDECF_DEC_FACTOR_Pos) /**< \brief (ISI_PDECF) Decimation Factor */ +#define ISI_PDECF_DEC_FACTOR(value) ((ISI_PDECF_DEC_FACTOR_Msk & ((value) << ISI_PDECF_DEC_FACTOR_Pos))) +/* -------- ISI_Y2R_SET0 : (ISI Offset: 0x10) ISI Color Space Conversion YCrCb To RGB Set 0 Register -------- */ +#define ISI_Y2R_SET0_C0_Pos 0 +#define ISI_Y2R_SET0_C0_Msk (0xffu << ISI_Y2R_SET0_C0_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C0 */ +#define ISI_Y2R_SET0_C0(value) ((ISI_Y2R_SET0_C0_Msk & ((value) << ISI_Y2R_SET0_C0_Pos))) +#define ISI_Y2R_SET0_C1_Pos 8 +#define ISI_Y2R_SET0_C1_Msk (0xffu << ISI_Y2R_SET0_C1_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C1 */ +#define ISI_Y2R_SET0_C1(value) ((ISI_Y2R_SET0_C1_Msk & ((value) << ISI_Y2R_SET0_C1_Pos))) +#define ISI_Y2R_SET0_C2_Pos 16 +#define ISI_Y2R_SET0_C2_Msk (0xffu << ISI_Y2R_SET0_C2_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C2 */ +#define ISI_Y2R_SET0_C2(value) ((ISI_Y2R_SET0_C2_Msk & ((value) << ISI_Y2R_SET0_C2_Pos))) +#define ISI_Y2R_SET0_C3_Pos 24 +#define ISI_Y2R_SET0_C3_Msk (0xffu << ISI_Y2R_SET0_C3_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C3 */ +#define ISI_Y2R_SET0_C3(value) ((ISI_Y2R_SET0_C3_Msk & ((value) << ISI_Y2R_SET0_C3_Pos))) +/* -------- ISI_Y2R_SET1 : (ISI Offset: 0x14) ISI Color Space Conversion YCrCb To RGB Set 1 Register -------- */ +#define ISI_Y2R_SET1_C4_Pos 0 +#define ISI_Y2R_SET1_C4_Msk (0x1ffu << ISI_Y2R_SET1_C4_Pos) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Matrix Coefficient C4 */ +#define ISI_Y2R_SET1_C4(value) ((ISI_Y2R_SET1_C4_Msk & ((value) << ISI_Y2R_SET1_C4_Pos))) +#define ISI_Y2R_SET1_Yoff (0x1u << 12) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Luminance Default Offset */ +#define ISI_Y2R_SET1_Croff (0x1u << 13) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Red Chrominance Default Offset */ +#define ISI_Y2R_SET1_Cboff (0x1u << 14) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Blue Chrominance Default Offset */ +/* -------- ISI_R2Y_SET0 : (ISI Offset: 0x18) ISI Color Space Conversion RGB To YCrCb Set 0 Register -------- */ +#define ISI_R2Y_SET0_C0_Pos 0 +#define ISI_R2Y_SET0_C0_Msk (0x7fu << ISI_R2Y_SET0_C0_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C0 */ +#define ISI_R2Y_SET0_C0(value) ((ISI_R2Y_SET0_C0_Msk & ((value) << ISI_R2Y_SET0_C0_Pos))) +#define ISI_R2Y_SET0_C1_Pos 8 +#define ISI_R2Y_SET0_C1_Msk (0x7fu << ISI_R2Y_SET0_C1_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C1 */ +#define ISI_R2Y_SET0_C1(value) ((ISI_R2Y_SET0_C1_Msk & ((value) << ISI_R2Y_SET0_C1_Pos))) +#define ISI_R2Y_SET0_C2_Pos 16 +#define ISI_R2Y_SET0_C2_Msk (0x7fu << ISI_R2Y_SET0_C2_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C2 */ +#define ISI_R2Y_SET0_C2(value) ((ISI_R2Y_SET0_C2_Msk & ((value) << ISI_R2Y_SET0_C2_Pos))) +#define ISI_R2Y_SET0_Roff (0x1u << 24) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Red Component Offset */ +/* -------- ISI_R2Y_SET1 : (ISI Offset: 0x1C) ISI Color Space Conversion RGB To YCrCb Set 1 Register -------- */ +#define ISI_R2Y_SET1_C3_Pos 0 +#define ISI_R2Y_SET1_C3_Msk (0x7fu << ISI_R2Y_SET1_C3_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C3 */ +#define ISI_R2Y_SET1_C3(value) ((ISI_R2Y_SET1_C3_Msk & ((value) << ISI_R2Y_SET1_C3_Pos))) +#define ISI_R2Y_SET1_C4_Pos 8 +#define ISI_R2Y_SET1_C4_Msk (0x7fu << ISI_R2Y_SET1_C4_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C4 */ +#define ISI_R2Y_SET1_C4(value) ((ISI_R2Y_SET1_C4_Msk & ((value) << ISI_R2Y_SET1_C4_Pos))) +#define ISI_R2Y_SET1_C5_Pos 16 +#define ISI_R2Y_SET1_C5_Msk (0x7fu << ISI_R2Y_SET1_C5_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C5 */ +#define ISI_R2Y_SET1_C5(value) ((ISI_R2Y_SET1_C5_Msk & ((value) << ISI_R2Y_SET1_C5_Pos))) +#define ISI_R2Y_SET1_Goff (0x1u << 24) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Green Component Offset */ +/* -------- ISI_R2Y_SET2 : (ISI Offset: 0x20) ISI Color Space Conversion RGB To YCrCb Set 2 Register -------- */ +#define ISI_R2Y_SET2_C6_Pos 0 +#define ISI_R2Y_SET2_C6_Msk (0x7fu << ISI_R2Y_SET2_C6_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C6 */ +#define ISI_R2Y_SET2_C6(value) ((ISI_R2Y_SET2_C6_Msk & ((value) << ISI_R2Y_SET2_C6_Pos))) +#define ISI_R2Y_SET2_C7_Pos 8 +#define ISI_R2Y_SET2_C7_Msk (0x7fu << ISI_R2Y_SET2_C7_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C7 */ +#define ISI_R2Y_SET2_C7(value) ((ISI_R2Y_SET2_C7_Msk & ((value) << ISI_R2Y_SET2_C7_Pos))) +#define ISI_R2Y_SET2_C8_Pos 16 +#define ISI_R2Y_SET2_C8_Msk (0x7fu << ISI_R2Y_SET2_C8_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C8 */ +#define ISI_R2Y_SET2_C8(value) ((ISI_R2Y_SET2_C8_Msk & ((value) << ISI_R2Y_SET2_C8_Pos))) +#define ISI_R2Y_SET2_Boff (0x1u << 24) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Blue Component Offset */ +/* -------- ISI_CR : (ISI Offset: 0x24) ISI Control Register -------- */ +#define ISI_CR_ISI_EN (0x1u << 0) /**< \brief (ISI_CR) ISI Module Enable Request */ +#define ISI_CR_ISI_DIS (0x1u << 1) /**< \brief (ISI_CR) ISI Module Disable Request */ +#define ISI_CR_ISI_SRST (0x1u << 2) /**< \brief (ISI_CR) ISI Software Reset Request */ +#define ISI_CR_ISI_CDC (0x1u << 8) /**< \brief (ISI_CR) ISI Codec Request */ +/* -------- ISI_SR : (ISI Offset: 0x28) ISI Status Register -------- */ +#define ISI_SR_ENABLE (0x1u << 0) /**< \brief (ISI_SR) Module Enable */ +#define ISI_SR_DIS_DONE (0x1u << 1) /**< \brief (ISI_SR) Module Disable Request has Terminated (cleared on read) */ +#define ISI_SR_SRST (0x1u << 2) /**< \brief (ISI_SR) Module Software Reset Request has Terminated (cleared on read) */ +#define ISI_SR_CDC_PND (0x1u << 8) /**< \brief (ISI_SR) Pending Codec Request */ +#define ISI_SR_VSYNC (0x1u << 10) /**< \brief (ISI_SR) Vertical Synchronization (cleared on read) */ +#define ISI_SR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_SR) Preview DMA Transfer has Terminated (cleared on read) */ +#define ISI_SR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_SR) Codec DMA Transfer has Terminated (cleared on read) */ +#define ISI_SR_SIP (0x1u << 19) /**< \brief (ISI_SR) Synchronization in Progress */ +#define ISI_SR_P_OVR (0x1u << 24) /**< \brief (ISI_SR) Preview Datapath Overflow (cleared on read) */ +#define ISI_SR_C_OVR (0x1u << 25) /**< \brief (ISI_SR) Codec Datapath Overflow (cleared on read) */ +#define ISI_SR_CRC_ERR (0x1u << 26) /**< \brief (ISI_SR) CRC Synchronization Error (cleared on read) */ +#define ISI_SR_FR_OVR (0x1u << 27) /**< \brief (ISI_SR) Frame Rate Overrun (cleared on read) */ +/* -------- ISI_IER : (ISI Offset: 0x2C) ISI Interrupt Enable Register -------- */ +#define ISI_IER_DIS_DONE (0x1u << 1) /**< \brief (ISI_IER) Disable Done Interrupt Enable */ +#define ISI_IER_SRST (0x1u << 2) /**< \brief (ISI_IER) Software Reset Interrupt Enable */ +#define ISI_IER_VSYNC (0x1u << 10) /**< \brief (ISI_IER) Vertical Synchronization Interrupt Enable */ +#define ISI_IER_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IER) Preview DMA Transfer Done Interrupt Enable */ +#define ISI_IER_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IER) Codec DMA Transfer Done Interrupt Enable */ +#define ISI_IER_P_OVR (0x1u << 24) /**< \brief (ISI_IER) Preview Datapath Overflow Interrupt Enable */ +#define ISI_IER_C_OVR (0x1u << 25) /**< \brief (ISI_IER) Codec Datapath Overflow Interrupt Enable */ +#define ISI_IER_CRC_ERR (0x1u << 26) /**< \brief (ISI_IER) Embedded Synchronization CRC Error Interrupt Enable */ +#define ISI_IER_FR_OVR (0x1u << 27) /**< \brief (ISI_IER) Frame Rate Overflow Interrupt Enable */ +/* -------- ISI_IDR : (ISI Offset: 0x30) ISI Interrupt Disable Register -------- */ +#define ISI_IDR_DIS_DONE (0x1u << 1) /**< \brief (ISI_IDR) Disable Done Interrupt Disable */ +#define ISI_IDR_SRST (0x1u << 2) /**< \brief (ISI_IDR) Software Reset Interrupt Disable */ +#define ISI_IDR_VSYNC (0x1u << 10) /**< \brief (ISI_IDR) Vertical Synchronization Interrupt Disable */ +#define ISI_IDR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IDR) Preview DMA Transfer Done Interrupt Disable */ +#define ISI_IDR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IDR) Codec DMA Transfer Done Interrupt Disable */ +#define ISI_IDR_P_OVR (0x1u << 24) /**< \brief (ISI_IDR) Preview Datapath Overflow Interrupt Disable */ +#define ISI_IDR_C_OVR (0x1u << 25) /**< \brief (ISI_IDR) Codec Datapath Overflow Interrupt Disable */ +#define ISI_IDR_CRC_ERR (0x1u << 26) /**< \brief (ISI_IDR) Embedded Synchronization CRC Error Interrupt Disable */ +#define ISI_IDR_FR_OVR (0x1u << 27) /**< \brief (ISI_IDR) Frame Rate Overflow Interrupt Disable */ +/* -------- ISI_IMR : (ISI Offset: 0x34) ISI Interrupt Mask Register -------- */ +#define ISI_IMR_DIS_DONE (0x1u << 1) /**< \brief (ISI_IMR) Module Disable Operation Completed */ +#define ISI_IMR_SRST (0x1u << 2) /**< \brief (ISI_IMR) Software Reset Completed */ +#define ISI_IMR_VSYNC (0x1u << 10) /**< \brief (ISI_IMR) Vertical Synchronization */ +#define ISI_IMR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IMR) Preview DMA Transfer Completed */ +#define ISI_IMR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IMR) Codec DMA Transfer Completed */ +#define ISI_IMR_P_OVR (0x1u << 24) /**< \brief (ISI_IMR) Preview FIFO Overflow */ +#define ISI_IMR_C_OVR (0x1u << 25) /**< \brief (ISI_IMR) Codec FIFO Overflow */ +#define ISI_IMR_CRC_ERR (0x1u << 26) /**< \brief (ISI_IMR) CRC Synchronization Error */ +#define ISI_IMR_FR_OVR (0x1u << 27) /**< \brief (ISI_IMR) Frame Rate Overrun */ +/* -------- ISI_DMA_CHER : (ISI Offset: 0x38) DMA Channel Enable Register -------- */ +#define ISI_DMA_CHER_P_CH_EN (0x1u << 0) /**< \brief (ISI_DMA_CHER) Preview Channel Enable */ +#define ISI_DMA_CHER_C_CH_EN (0x1u << 1) /**< \brief (ISI_DMA_CHER) Codec Channel Enable */ +/* -------- ISI_DMA_CHDR : (ISI Offset: 0x3C) DMA Channel Disable Register -------- */ +#define ISI_DMA_CHDR_P_CH_DIS (0x1u << 0) /**< \brief (ISI_DMA_CHDR) Preview Channel Disable Request */ +#define ISI_DMA_CHDR_C_CH_DIS (0x1u << 1) /**< \brief (ISI_DMA_CHDR) Codec Channel Disable Request */ +/* -------- ISI_DMA_CHSR : (ISI Offset: 0x40) DMA Channel Status Register -------- */ +#define ISI_DMA_CHSR_P_CH_S (0x1u << 0) /**< \brief (ISI_DMA_CHSR) Preview DMA Channel Status */ +#define ISI_DMA_CHSR_C_CH_S (0x1u << 1) /**< \brief (ISI_DMA_CHSR) Code DMA Channel Status */ +/* -------- ISI_DMA_P_ADDR : (ISI Offset: 0x44) DMA Preview Base Address Register -------- */ +#define ISI_DMA_P_ADDR_P_ADDR_Pos 2 +#define ISI_DMA_P_ADDR_P_ADDR_Msk (0x3fffffffu << ISI_DMA_P_ADDR_P_ADDR_Pos) /**< \brief (ISI_DMA_P_ADDR) Preview Image Base Address */ +#define ISI_DMA_P_ADDR_P_ADDR(value) ((ISI_DMA_P_ADDR_P_ADDR_Msk & ((value) << ISI_DMA_P_ADDR_P_ADDR_Pos))) +/* -------- ISI_DMA_P_CTRL : (ISI Offset: 0x48) DMA Preview Control Register -------- */ +#define ISI_DMA_P_CTRL_P_FETCH (0x1u << 0) /**< \brief (ISI_DMA_P_CTRL) Descriptor Fetch Control Bit */ +#define ISI_DMA_P_CTRL_P_WB (0x1u << 1) /**< \brief (ISI_DMA_P_CTRL) Descriptor Writeback Control Bit */ +#define ISI_DMA_P_CTRL_P_IEN (0x1u << 2) /**< \brief (ISI_DMA_P_CTRL) Transfer Done Flag Control */ +#define ISI_DMA_P_CTRL_P_DONE (0x1u << 3) /**< \brief (ISI_DMA_P_CTRL) Preview Transfer Done */ +/* -------- ISI_DMA_P_DSCR : (ISI Offset: 0x4C) DMA Preview Descriptor Address Register -------- */ +#define ISI_DMA_P_DSCR_P_DSCR_Pos 2 +#define ISI_DMA_P_DSCR_P_DSCR_Msk (0x3fffffffu << ISI_DMA_P_DSCR_P_DSCR_Pos) /**< \brief (ISI_DMA_P_DSCR) Preview Descriptor Base Address */ +#define ISI_DMA_P_DSCR_P_DSCR(value) ((ISI_DMA_P_DSCR_P_DSCR_Msk & ((value) << ISI_DMA_P_DSCR_P_DSCR_Pos))) +/* -------- ISI_DMA_C_ADDR : (ISI Offset: 0x50) DMA Codec Base Address Register -------- */ +#define ISI_DMA_C_ADDR_C_ADDR_Pos 2 +#define ISI_DMA_C_ADDR_C_ADDR_Msk (0x3fffffffu << ISI_DMA_C_ADDR_C_ADDR_Pos) /**< \brief (ISI_DMA_C_ADDR) Codec Image Base Address */ +#define ISI_DMA_C_ADDR_C_ADDR(value) ((ISI_DMA_C_ADDR_C_ADDR_Msk & ((value) << ISI_DMA_C_ADDR_C_ADDR_Pos))) +/* -------- ISI_DMA_C_CTRL : (ISI Offset: 0x54) DMA Codec Control Register -------- */ +#define ISI_DMA_C_CTRL_C_FETCH (0x1u << 0) /**< \brief (ISI_DMA_C_CTRL) Descriptor Fetch Control Bit */ +#define ISI_DMA_C_CTRL_C_WB (0x1u << 1) /**< \brief (ISI_DMA_C_CTRL) Descriptor Writeback Control Bit */ +#define ISI_DMA_C_CTRL_C_IEN (0x1u << 2) /**< \brief (ISI_DMA_C_CTRL) Transfer Done Flag Control */ +#define ISI_DMA_C_CTRL_C_DONE (0x1u << 3) /**< \brief (ISI_DMA_C_CTRL) Codec Transfer Done */ +/* -------- ISI_DMA_C_DSCR : (ISI Offset: 0x58) DMA Codec Descriptor Address Register -------- */ +#define ISI_DMA_C_DSCR_C_DSCR_Pos 2 +#define ISI_DMA_C_DSCR_C_DSCR_Msk (0x3fffffffu << ISI_DMA_C_DSCR_C_DSCR_Pos) /**< \brief (ISI_DMA_C_DSCR) Codec Descriptor Base Address */ +#define ISI_DMA_C_DSCR_C_DSCR(value) ((ISI_DMA_C_DSCR_C_DSCR_Msk & ((value) << ISI_DMA_C_DSCR_C_DSCR_Pos))) +/* -------- ISI_WPMR : (ISI Offset: 0xE4) Write Protection Mode Register -------- */ +#define ISI_WPMR_WPEN (0x1u << 0) /**< \brief (ISI_WPMR) Write Protection Enable */ +#define ISI_WPMR_WPKEY_Pos 8 +#define ISI_WPMR_WPKEY_Msk (0xffffffu << ISI_WPMR_WPKEY_Pos) /**< \brief (ISI_WPMR) Write Protection Key Password */ +#define ISI_WPMR_WPKEY(value) ((ISI_WPMR_WPKEY_Msk & ((value) << ISI_WPMR_WPKEY_Pos))) +#define ISI_WPMR_WPKEY_PASSWD (0x495349u << 8) /**< \brief (ISI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- ISI_WPSR : (ISI Offset: 0xE8) Write Protection Status Register -------- */ +#define ISI_WPSR_WPVS (0x1u << 0) /**< \brief (ISI_WPSR) Write Protection Violation Status */ +#define ISI_WPSR_WPVSRC_Pos 8 +#define ISI_WPSR_WPVSRC_Msk (0xffffu << ISI_WPSR_WPVSRC_Pos) /**< \brief (ISI_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAMV71_ISI_COMPONENT_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_matrix.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_matrix.h new file mode 100644 index 00000000..2a337bb8 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_matrix.h @@ -0,0 +1,174 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_MATRIX_COMPONENT_ +#define _SAMV71_MATRIX_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */ +/* ============================================================================= */ +/** \addtogroup SAMV71_MATRIX AHB Bus Matrix */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief MatrixPr hardware registers */ +typedef struct { + __IO uint32_t MATRIX_PRAS; /**< \brief (MatrixPr Offset: 0x0) Priority Register A for Slave 0 */ + __IO uint32_t MATRIX_PRBS; /**< \brief (MatrixPr Offset: 0x4) Priority Register B for Slave 0 */ +} MatrixPr; +/** \brief Matrix hardware registers */ +#define MATRIXPR_NUMBER 9 +typedef struct { + __IO uint32_t MATRIX_MCFG[12]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */ + __I uint32_t Reserved1[4]; + __IO uint32_t MATRIX_SCFG[9]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */ + __I uint32_t Reserved2[7]; + MatrixPr MATRIX_PR[MATRIXPR_NUMBER]; /**< \brief (Matrix Offset: 0x0080) 0 .. 8 */ + __I uint32_t Reserved3[14]; + __IO uint32_t MATRIX_MRCR; /**< \brief (Matrix Offset: 0x0100) Master Remap Control Register */ + __I uint32_t Reserved4[3]; + __IO uint32_t CCFG_CAN0; /**< \brief (Matrix Offset: 0x0110) CAN0 Configuration Register */ + __IO uint32_t CCFG_SYSIO; /**< \brief (Matrix Offset: 0x0114) System I/O and CAN1 Configuration Register */ + __I uint32_t Reserved5[3]; + __IO uint32_t CCFG_SMCNFCS; /**< \brief (Matrix Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register */ + __I uint32_t Reserved6[47]; + __IO uint32_t MATRIX_WPMR; /**< \brief (Matrix Offset: 0x01E4) Write Protection Mode Register */ + __I uint32_t MATRIX_WPSR; /**< \brief (Matrix Offset: 0x01E8) Write Protection Status Register */ +} Matrix; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- MATRIX_MCFG[12] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */ +#define MATRIX_MCFG_ULBT_Pos 0 +#define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) /**< \brief (MATRIX_MCFG[12]) Undefined Length Burst Type */ +#define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos))) +#define MATRIX_MCFG_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG[12]) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG[12]) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG[12]) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG[12]) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG[12]) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG[12]) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG[12]) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG[12]) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_SCFG[9] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */ +#define MATRIX_SCFG_SLOT_CYCLE_Pos 0 +#define MATRIX_SCFG_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[9]) Maximum Bus Grant Duration for Masters */ +#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos))) +#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16 +#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[9]) Default Master Type */ +#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos))) +#define MATRIX_SCFG_DEFMSTR_TYPE_NONE (0x0u << 16) /**< \brief (MATRIX_SCFG[9]) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */ +#define MATRIX_SCFG_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG[9]) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */ +#define MATRIX_SCFG_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG[9]) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */ +#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18 +#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[9]) Fixed Default Master */ +#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos))) +/* -------- MATRIX_PRAS : (MATRIX Offset: N/A) Priority Register A for Slave 0 -------- */ +#define MATRIX_PRAS_M0PR_Pos 0 +#define MATRIX_PRAS_M0PR_Msk (0x3u << MATRIX_PRAS_M0PR_Pos) /**< \brief (MATRIX_PRAS) Master 0 Priority */ +#define MATRIX_PRAS_M0PR(value) ((MATRIX_PRAS_M0PR_Msk & ((value) << MATRIX_PRAS_M0PR_Pos))) +#define MATRIX_PRAS_M1PR_Pos 4 +#define MATRIX_PRAS_M1PR_Msk (0x3u << MATRIX_PRAS_M1PR_Pos) /**< \brief (MATRIX_PRAS) Master 1 Priority */ +#define MATRIX_PRAS_M1PR(value) ((MATRIX_PRAS_M1PR_Msk & ((value) << MATRIX_PRAS_M1PR_Pos))) +#define MATRIX_PRAS_M2PR_Pos 8 +#define MATRIX_PRAS_M2PR_Msk (0x3u << MATRIX_PRAS_M2PR_Pos) /**< \brief (MATRIX_PRAS) Master 2 Priority */ +#define MATRIX_PRAS_M2PR(value) ((MATRIX_PRAS_M2PR_Msk & ((value) << MATRIX_PRAS_M2PR_Pos))) +#define MATRIX_PRAS_M3PR_Pos 12 +#define MATRIX_PRAS_M3PR_Msk (0x3u << MATRIX_PRAS_M3PR_Pos) /**< \brief (MATRIX_PRAS) Master 3 Priority */ +#define MATRIX_PRAS_M3PR(value) ((MATRIX_PRAS_M3PR_Msk & ((value) << MATRIX_PRAS_M3PR_Pos))) +#define MATRIX_PRAS_M4PR_Pos 16 +#define MATRIX_PRAS_M4PR_Msk (0x3u << MATRIX_PRAS_M4PR_Pos) /**< \brief (MATRIX_PRAS) Master 4 Priority */ +#define MATRIX_PRAS_M4PR(value) ((MATRIX_PRAS_M4PR_Msk & ((value) << MATRIX_PRAS_M4PR_Pos))) +#define MATRIX_PRAS_M5PR_Pos 20 +#define MATRIX_PRAS_M5PR_Msk (0x3u << MATRIX_PRAS_M5PR_Pos) /**< \brief (MATRIX_PRAS) Master 5 Priority */ +#define MATRIX_PRAS_M5PR(value) ((MATRIX_PRAS_M5PR_Msk & ((value) << MATRIX_PRAS_M5PR_Pos))) +#define MATRIX_PRAS_M6PR_Pos 24 +#define MATRIX_PRAS_M6PR_Msk (0x3u << MATRIX_PRAS_M6PR_Pos) /**< \brief (MATRIX_PRAS) Master 6 Priority */ +#define MATRIX_PRAS_M6PR(value) ((MATRIX_PRAS_M6PR_Msk & ((value) << MATRIX_PRAS_M6PR_Pos))) +#define MATRIX_PRAS_M7PR_Pos 28 +#define MATRIX_PRAS_M7PR_Msk (0x3u << MATRIX_PRAS_M7PR_Pos) /**< \brief (MATRIX_PRAS) Master 7 Priority */ +#define MATRIX_PRAS_M7PR(value) ((MATRIX_PRAS_M7PR_Msk & ((value) << MATRIX_PRAS_M7PR_Pos))) +/* -------- MATRIX_PRBS : (MATRIX Offset: N/A) Priority Register B for Slave 0 -------- */ +#define MATRIX_PRBS_M8PR_Pos 0 +#define MATRIX_PRBS_M8PR_Msk (0x3u << MATRIX_PRBS_M8PR_Pos) /**< \brief (MATRIX_PRBS) Master 8 Priority */ +#define MATRIX_PRBS_M8PR(value) ((MATRIX_PRBS_M8PR_Msk & ((value) << MATRIX_PRBS_M8PR_Pos))) +#define MATRIX_PRBS_M9PR_Pos 4 +#define MATRIX_PRBS_M9PR_Msk (0x3u << MATRIX_PRBS_M9PR_Pos) /**< \brief (MATRIX_PRBS) Master 9 Priority */ +#define MATRIX_PRBS_M9PR(value) ((MATRIX_PRBS_M9PR_Msk & ((value) << MATRIX_PRBS_M9PR_Pos))) +#define MATRIX_PRBS_M10PR_Pos 8 +#define MATRIX_PRBS_M10PR_Msk (0x3u << MATRIX_PRBS_M10PR_Pos) /**< \brief (MATRIX_PRBS) Master 10 Priority */ +#define MATRIX_PRBS_M10PR(value) ((MATRIX_PRBS_M10PR_Msk & ((value) << MATRIX_PRBS_M10PR_Pos))) +#define MATRIX_PRBS_M11PR_Pos 12 +#define MATRIX_PRBS_M11PR_Msk (0x3u << MATRIX_PRBS_M11PR_Pos) /**< \brief (MATRIX_PRBS) Master 11 Priority */ +#define MATRIX_PRBS_M11PR(value) ((MATRIX_PRBS_M11PR_Msk & ((value) << MATRIX_PRBS_M11PR_Pos))) +/* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */ +#define MATRIX_MRCR_RCB0 (0x1u << 0) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 0 */ +#define MATRIX_MRCR_RCB1 (0x1u << 1) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 1 */ +#define MATRIX_MRCR_RCB2 (0x1u << 2) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 2 */ +#define MATRIX_MRCR_RCB3 (0x1u << 3) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 3 */ +#define MATRIX_MRCR_RCB4 (0x1u << 4) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 4 */ +#define MATRIX_MRCR_RCB5 (0x1u << 5) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 5 */ +#define MATRIX_MRCR_RCB6 (0x1u << 6) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 6 */ +#define MATRIX_MRCR_RCB7 (0x1u << 7) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 7 */ +#define MATRIX_MRCR_RCB8 (0x1u << 8) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 8 */ +#define MATRIX_MRCR_RCB9 (0x1u << 9) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 9 */ +#define MATRIX_MRCR_RCB10 (0x1u << 10) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 10 */ +#define MATRIX_MRCR_RCB11 (0x1u << 11) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 11 */ +/* -------- CCFG_CAN0 : (MATRIX Offset: 0x0110) CAN0 Configuration Register -------- */ +#define CCFG_CAN0_CAN0DMABA_Pos 16 +#define CCFG_CAN0_CAN0DMABA_Msk (0xffffu << CCFG_CAN0_CAN0DMABA_Pos) /**< \brief (CCFG_CAN0) CAN0 DMA Base Address */ +#define CCFG_CAN0_CAN0DMABA(value) ((CCFG_CAN0_CAN0DMABA_Msk & ((value) << CCFG_CAN0_CAN0DMABA_Pos))) +/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O and CAN1 Configuration Register -------- */ +#define CCFG_SYSIO_SYSIO4 (0x1u << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */ +#define CCFG_SYSIO_SYSIO5 (0x1u << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */ +#define CCFG_SYSIO_SYSIO6 (0x1u << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */ +#define CCFG_SYSIO_SYSIO7 (0x1u << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */ +#define CCFG_SYSIO_SYSIO12 (0x1u << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */ +#define CCFG_SYSIO_CAN1DMABA_Pos 16 +#define CCFG_SYSIO_CAN1DMABA_Msk (0xffffu << CCFG_SYSIO_CAN1DMABA_Pos) /**< \brief (CCFG_SYSIO) CAN0 DMA Base Address */ +#define CCFG_SYSIO_CAN1DMABA(value) ((CCFG_SYSIO_CAN1DMABA_Msk & ((value) << CCFG_SYSIO_CAN1DMABA_Pos))) +/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register -------- */ +#define CCFG_SMCNFCS_SMC_NFCS0 (0x1u << 0) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS1 (0x1u << 1) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS2 (0x1u << 2) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS3 (0x1u << 3) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment */ +#define CCFG_SMCNFCS_SDRAMEN (0x1u << 4) /**< \brief (CCFG_SMCNFCS) SDRAM Enable */ +/* -------- MATRIX_WPMR : (MATRIX Offset: 0x01E4) Write Protection Mode Register -------- */ +#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protection Enable */ +#define MATRIX_WPMR_WPKEY_Pos 8 +#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protection Key */ +#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos))) +#define MATRIX_WPMR_WPKEY_PASSWD (0x4D4154u << 8) /**< \brief (MATRIX_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- MATRIX_WPSR : (MATRIX Offset: 0x01E8) Write Protection Status Register -------- */ +#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protection Violation Status */ +#define MATRIX_WPSR_WPVSRC_Pos 8 +#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAMV71_MATRIX_COMPONENT_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_mcan.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_mcan.h new file mode 100644 index 00000000..d3bfa010 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_mcan.h @@ -0,0 +1,845 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_MCAN_COMPONENT_ +#define _SAMV71_MCAN_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Controller Area Network */ +/* ============================================================================= */ +/** \addtogroup SAMV71_MCAN Controller Area Network */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Mcan hardware registers */ +typedef struct { + __I uint32_t Reserved1[2]; + __IO uint32_t MCAN_CUST; /**< \brief (Mcan Offset: 0x08) Customer Register */ + __IO uint32_t MCAN_FBTP; /**< \brief (Mcan Offset: 0x0C) Fast Bit Timing and Prescaler Register */ + __IO uint32_t MCAN_TEST; /**< \brief (Mcan Offset: 0x10) Test Register */ + __IO uint32_t MCAN_RWD; /**< \brief (Mcan Offset: 0x14) RAM Watchdog Register */ + __IO uint32_t MCAN_CCCR; /**< \brief (Mcan Offset: 0x18) CC Control Register */ + __IO uint32_t MCAN_BTP; /**< \brief (Mcan Offset: 0x1C) Bit Timing and Prescaler Register */ + __IO uint32_t MCAN_TSCC; /**< \brief (Mcan Offset: 0x20) Timestamp Counter Configuration Register */ + __IO uint32_t MCAN_TSCV; /**< \brief (Mcan Offset: 0x24) Timestamp Counter Value Register */ + __IO uint32_t MCAN_TOCC; /**< \brief (Mcan Offset: 0x28) Timeout Counter Configuration Register */ + __IO uint32_t MCAN_TOCV; /**< \brief (Mcan Offset: 0x2C) Timeout Counter Value Register */ + __I uint32_t Reserved2[4]; + __I uint32_t MCAN_ECR; /**< \brief (Mcan Offset: 0x40) Error Counter Register */ + __I uint32_t MCAN_PSR; /**< \brief (Mcan Offset: 0x44) Protocol Status Register */ + __I uint32_t Reserved3[2]; + __IO uint32_t MCAN_IR; /**< \brief (Mcan Offset: 0x50) Interrupt Register */ + __IO uint32_t MCAN_IE; /**< \brief (Mcan Offset: 0x54) Interrupt Enable Register */ + __IO uint32_t MCAN_ILS; /**< \brief (Mcan Offset: 0x58) Interrupt Line Select Register */ + __IO uint32_t MCAN_ILE; /**< \brief (Mcan Offset: 0x5C) Interrupt Line Enable Register */ + __I uint32_t Reserved4[8]; + __IO uint32_t MCAN_GFC; /**< \brief (Mcan Offset: 0x80) Global Filter Configuration Register */ + __IO uint32_t MCAN_SIDFC; /**< \brief (Mcan Offset: 0x84) Standard ID Filter Configuration Register */ + __IO uint32_t MCAN_XIDFC; /**< \brief (Mcan Offset: 0x88) Extended ID Filter Configuration Register */ + __I uint32_t Reserved5[1]; + __IO uint32_t MCAN_XIDAM; /**< \brief (Mcan Offset: 0x90) Extended ID AND Mask Register */ + __I uint32_t MCAN_HPMS; /**< \brief (Mcan Offset: 0x94) High Priority Message Status Register */ + __IO uint32_t MCAN_NDAT1; /**< \brief (Mcan Offset: 0x98) New Data 1 Register */ + __IO uint32_t MCAN_NDAT2; /**< \brief (Mcan Offset: 0x9C) New Data 2 Register */ + __IO uint32_t MCAN_RXF0C; /**< \brief (Mcan Offset: 0xA0) Receive FIFO 0 Configuration Register */ + __I uint32_t MCAN_RXF0S; /**< \brief (Mcan Offset: 0xA4) Receive FIFO 0 Status Register */ + __IO uint32_t MCAN_RXF0A; /**< \brief (Mcan Offset: 0xA8) Receive FIFO 0 Acknowledge Register */ + __IO uint32_t MCAN_RXBC; /**< \brief (Mcan Offset: 0xAC) Receive Rx Buffer Configuration Register */ + __IO uint32_t MCAN_RXF1C; /**< \brief (Mcan Offset: 0xB0) Receive FIFO 1 Configuration Register */ + __I uint32_t MCAN_RXF1S; /**< \brief (Mcan Offset: 0xB4) Receive FIFO 1 Status Register */ + __IO uint32_t MCAN_RXF1A; /**< \brief (Mcan Offset: 0xB8) Receive FIFO 1 Acknowledge Register */ + __IO uint32_t MCAN_RXESC; /**< \brief (Mcan Offset: 0xBC) Receive Buffer / FIFO Element Size Configuration Register */ + __IO uint32_t MCAN_TXBC; /**< \brief (Mcan Offset: 0xC0) Transmit Buffer Configuration Register */ + __I uint32_t MCAN_TXFQS; /**< \brief (Mcan Offset: 0xC4) Transmit FIFO/Queue Status Register */ + __IO uint32_t MCAN_TXESC; /**< \brief (Mcan Offset: 0xC8) Transmit Buffer Element Size Configuration Register */ + __I uint32_t MCAN_TXBRP; /**< \brief (Mcan Offset: 0xCC) Transmit Buffer Request Pending Register */ + __IO uint32_t MCAN_TXBAR; /**< \brief (Mcan Offset: 0xD0) Transmit Buffer Add Request Register */ + __IO uint32_t MCAN_TXBCR; /**< \brief (Mcan Offset: 0xD4) Transmit Buffer Cancellation Request Register */ + __I uint32_t MCAN_TXBTO; /**< \brief (Mcan Offset: 0xD8) Transmit Buffer Transmission Occurred Register */ + __I uint32_t MCAN_TXBCF; /**< \brief (Mcan Offset: 0xDC) Transmit Buffer Cancellation Finished Register */ + __IO uint32_t MCAN_TXBTIE; /**< \brief (Mcan Offset: 0xE0) Transmit Buffer Transmission Interrupt Enable Register */ + __IO uint32_t MCAN_TXBCIE; /**< \brief (Mcan Offset: 0xE4) Transmit Buffer Cancellation Finished Interrupt Enable Register */ + __I uint32_t Reserved6[2]; + __IO uint32_t MCAN_TXEFC; /**< \brief (Mcan Offset: 0xF0) Transmit Event FIFO Configuration Register */ + __I uint32_t MCAN_TXEFS; /**< \brief (Mcan Offset: 0xF4) Transmit Event FIFO Status Register */ + __IO uint32_t MCAN_TXEFA; /**< \brief (Mcan Offset: 0xF8) Transmit Event FIFO Acknowledge Register */ +} Mcan; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- MCAN_CUST : (MCAN Offset: 0x08) Customer Register -------- */ +#define MCAN_CUST_CSV_Pos 0 +#define MCAN_CUST_CSV_Msk (0xffffffffu << MCAN_CUST_CSV_Pos) /**< \brief (MCAN_CUST) Customer-specific Value */ +#define MCAN_CUST_CSV(value) ((MCAN_CUST_CSV_Msk & ((value) << MCAN_CUST_CSV_Pos))) +/* -------- MCAN_FBTP : (MCAN Offset: 0x0C) Fast Bit Timing and Prescaler Register -------- */ +#define MCAN_FBTP_FSJW_Pos 0 +#define MCAN_FBTP_FSJW_Msk (0x3u << MCAN_FBTP_FSJW_Pos) /**< \brief (MCAN_FBTP) Fast (Re) Synchronization Jump Width */ +#define MCAN_FBTP_FSJW(value) ((MCAN_FBTP_FSJW_Msk & ((value) << MCAN_FBTP_FSJW_Pos))) +#define MCAN_FBTP_FTSEG2_Pos 4 +#define MCAN_FBTP_FTSEG2_Msk (0x7u << MCAN_FBTP_FTSEG2_Pos) /**< \brief (MCAN_FBTP) Fast Time Segment After Sample Point */ +#define MCAN_FBTP_FTSEG2(value) ((MCAN_FBTP_FTSEG2_Msk & ((value) << MCAN_FBTP_FTSEG2_Pos))) +#define MCAN_FBTP_FTSEG1_Pos 8 +#define MCAN_FBTP_FTSEG1_Msk (0xfu << MCAN_FBTP_FTSEG1_Pos) /**< \brief (MCAN_FBTP) Fast Time Segment Before Sample Point */ +#define MCAN_FBTP_FTSEG1(value) ((MCAN_FBTP_FTSEG1_Msk & ((value) << MCAN_FBTP_FTSEG1_Pos))) +#define MCAN_FBTP_FBRP_Pos 16 +#define MCAN_FBTP_FBRP_Msk (0x1fu << MCAN_FBTP_FBRP_Pos) /**< \brief (MCAN_FBTP) Fast Baud Rate Prescaler */ +#define MCAN_FBTP_FBRP(value) ((MCAN_FBTP_FBRP_Msk & ((value) << MCAN_FBTP_FBRP_Pos))) +#define MCAN_FBTP_TDC (0x1u << 23) /**< \brief (MCAN_FBTP) Transceiver Delay Compensation */ +#define MCAN_FBTP_TDC_DISABLED (0x0u << 23) /**< \brief (MCAN_FBTP) Transceiver Delay Compensation disabled. */ +#define MCAN_FBTP_TDC_ENABLED (0x1u << 23) /**< \brief (MCAN_FBTP) Transceiver Delay Compensation enabled. */ +#define MCAN_FBTP_TDCO_Pos 24 +#define MCAN_FBTP_TDCO_Msk (0x1fu << MCAN_FBTP_TDCO_Pos) /**< \brief (MCAN_FBTP) Transce iver Delay Compensation Offset */ +#define MCAN_FBTP_TDCO(value) ((MCAN_FBTP_TDCO_Msk & ((value) << MCAN_FBTP_TDCO_Pos))) +/* -------- MCAN_TEST : (MCAN Offset: 0x10) Test Register -------- */ +#define MCAN_TEST_LBCK (0x1u << 4) /**< \brief (MCAN_TEST) Loop Back Mode (read/write) */ +#define MCAN_TEST_LBCK_DISABLED (0x0u << 4) /**< \brief (MCAN_TEST) Reset value. Loop Back mode is disabled. */ +#define MCAN_TEST_LBCK_ENABLED (0x1u << 4) /**< \brief (MCAN_TEST) Loop Back mode is enabled (see Section 6.1.9). */ +#define MCAN_TEST_TX_Pos 5 +#define MCAN_TEST_TX_Msk (0x3u << MCAN_TEST_TX_Pos) /**< \brief (MCAN_TEST) Control of Transmit Pin (read/write) */ +#define MCAN_TEST_TX(value) ((MCAN_TEST_TX_Msk & ((value) << MCAN_TEST_TX_Pos))) +#define MCAN_TEST_TX_RESET (0x0u << 5) /**< \brief (MCAN_TEST) Reset value, CANTX controlled by the CAN Core, updated at the end of the CAN bit time. */ +#define MCAN_TEST_TX_SAMPLE_POINT_MONITORING (0x1u << 5) /**< \brief (MCAN_TEST) Sample Point can be monitored at pin CANTX. */ +#define MCAN_TEST_TX_DOMINANT (0x2u << 5) /**< \brief (MCAN_TEST) Dominant ('0') level at pin CANTX. */ +#define MCAN_TEST_TX_RECESSIVE (0x3u << 5) /**< \brief (MCAN_TEST) Recessive ('1') at pin CANTX. */ +#define MCAN_TEST_RX (0x1u << 7) /**< \brief (MCAN_TEST) Receive Pin (read-only) */ +#define MCAN_TEST_TDCV_Pos 8 +#define MCAN_TEST_TDCV_Msk (0x3fu << MCAN_TEST_TDCV_Pos) /**< \brief (MCAN_TEST) Transceiver Delay Compensation Value (read-only) */ +#define MCAN_TEST_TDCV(value) ((MCAN_TEST_TDCV_Msk & ((value) << MCAN_TEST_TDCV_Pos))) +/* -------- MCAN_RWD : (MCAN Offset: 0x14) RAM Watchdog Register -------- */ +#define MCAN_RWD_WDC_Pos 0 +#define MCAN_RWD_WDC_Msk (0xffu << MCAN_RWD_WDC_Pos) /**< \brief (MCAN_RWD) Watchdog Configuration (read/write) */ +#define MCAN_RWD_WDC(value) ((MCAN_RWD_WDC_Msk & ((value) << MCAN_RWD_WDC_Pos))) +#define MCAN_RWD_WDV_Pos 8 +#define MCAN_RWD_WDV_Msk (0xffu << MCAN_RWD_WDV_Pos) /**< \brief (MCAN_RWD) Watchdog Value (read-only) */ +#define MCAN_RWD_WDV(value) ((MCAN_RWD_WDV_Msk & ((value) << MCAN_RWD_WDV_Pos))) +/* -------- MCAN_CCCR : (MCAN Offset: 0x18) CC Control Register -------- */ +#define MCAN_CCCR_INIT (0x1u << 0) /**< \brief (MCAN_CCCR) Initialization (read/write) */ +#define MCAN_CCCR_INIT_DISABLED (0x0u << 0) /**< \brief (MCAN_CCCR) Normal operation. */ +#define MCAN_CCCR_INIT_ENABLED (0x1u << 0) /**< \brief (MCAN_CCCR) Initialization is started. */ +#define MCAN_CCCR_CCE (0x1u << 1) /**< \brief (MCAN_CCCR) Configuration Change Enable (read/write, write protection) */ +#define MCAN_CCCR_CCE_PROTECTED (0x0u << 1) /**< \brief (MCAN_CCCR) The processor has no write access to the protected configuration registers. */ +#define MCAN_CCCR_CCE_CONFIGURABLE (0x1u << 1) /**< \brief (MCAN_CCCR) The processor has write access to the protected configuration registers (while MCAN_CCCR.INIT = '1'). */ +#define MCAN_CCCR_ASM (0x1u << 2) /**< \brief (MCAN_CCCR) Restricted Operation Mode (read/write, write protection against '1') */ +#define MCAN_CCCR_ASM_NORMAL (0x0u << 2) /**< \brief (MCAN_CCCR) Normal CAN operation. */ +#define MCAN_CCCR_ASM_RESTRICTED (0x1u << 2) /**< \brief (MCAN_CCCR) Restricted operation mode active. */ +#define MCAN_CCCR_CSA (0x1u << 3) /**< \brief (MCAN_CCCR) Clock Stop Acknowledge (read-only) */ +#define MCAN_CCCR_CSR (0x1u << 4) /**< \brief (MCAN_CCCR) Clock Stop Request (read/write) */ +#define MCAN_CCCR_CSR_NO_CLOCK_STOP (0x0u << 4) /**< \brief (MCAN_CCCR) No clock stop is requested. */ +#define MCAN_CCCR_CSR_CLOCK_STOP (0x1u << 4) /**< \brief (MCAN_CCCR) Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pend-ing transfer requests have been completed and the CAN bus reached idle. */ +#define MCAN_CCCR_MON (0x1u << 5) /**< \brief (MCAN_CCCR) Bus Monitoring Mode (read/write, write protection against '1') */ +#define MCAN_CCCR_MON_DISABLED (0x0u << 5) /**< \brief (MCAN_CCCR) Bus Monitoring mode is disabled. */ +#define MCAN_CCCR_MON_ENABLED (0x1u << 5) /**< \brief (MCAN_CCCR) Bus Monitoring mode is enabled. */ +#define MCAN_CCCR_DAR (0x1u << 6) /**< \brief (MCAN_CCCR) Disable Automatic Retransmission (read/write, write protection) */ +#define MCAN_CCCR_DAR_AUTO_RETX (0x0u << 6) /**< \brief (MCAN_CCCR) Automatic retransmission of messages not transmitted successfully enabled. */ +#define MCAN_CCCR_DAR_NO_AUTO_RETX (0x1u << 6) /**< \brief (MCAN_CCCR) Automatic retransmission disabled. */ +#define MCAN_CCCR_TEST (0x1u << 7) /**< \brief (MCAN_CCCR) Test Mode Enable (read/write, write protection against '1') */ +#define MCAN_CCCR_TEST_DISABLED (0x0u << 7) /**< \brief (MCAN_CCCR) Normal operation, MCAN_TEST register holds reset values. */ +#define MCAN_CCCR_TEST_ENABLED (0x1u << 7) /**< \brief (MCAN_CCCR) Test mode, write access to MCAN_TEST register enabled. */ +#define MCAN_CCCR_CME_Pos 8 +#define MCAN_CCCR_CME_Msk (0x3u << MCAN_CCCR_CME_Pos) /**< \brief (MCAN_CCCR) CAN Mode Enable (read/write, write protection) */ +#define MCAN_CCCR_CME(value) ((MCAN_CCCR_CME_Msk & ((value) << MCAN_CCCR_CME_Pos))) +#define MCAN_CCCR_CME_ISO11898_1 (0x0u << 8) /**< \brief (MCAN_CCCR) CAN operation according to ISO11898-1 enabled */ +#define MCAN_CCCR_CME_FD (0x1u << 8) /**< \brief (MCAN_CCCR) CAN FD operation enabled */ +#define MCAN_CCCR_CMR_Pos 10 +#define MCAN_CCCR_CMR_Msk (0x3u << MCAN_CCCR_CMR_Pos) /**< \brief (MCAN_CCCR) CAN Mode Request (read/write) */ +#define MCAN_CCCR_CMR(value) ((MCAN_CCCR_CMR_Msk & ((value) << MCAN_CCCR_CMR_Pos))) +#define MCAN_CCCR_CMR_NO_CHANGE (0x0u << 10) /**< \brief (MCAN_CCCR) No mode change */ +#define MCAN_CCCR_CMR_FD (0x1u << 10) /**< \brief (MCAN_CCCR) Request CAN FD operation */ +#define MCAN_CCCR_CMR_FD_BITRATE_SWITCH (0x2u << 10) /**< \brief (MCAN_CCCR) Request CAN FD operation with bit rate switching */ +#define MCAN_CCCR_CMR_ISO11898_1 (0x3u << 10) /**< \brief (MCAN_CCCR) Request CAN operation according ISO11898-1 */ +#define MCAN_CCCR_FDO (0x1u << 12) /**< \brief (MCAN_CCCR) CAN FD Operation (read-only) */ +#define MCAN_CCCR_FDBS (0x1u << 13) /**< \brief (MCAN_CCCR) CAN FD Bit Rate Switching (read-only) */ +#define MCAN_CCCR_TXP (0x1u << 14) /**< \brief (MCAN_CCCR) Transmit Pause (read/write, write protection) */ +/* -------- MCAN_BTP : (MCAN Offset: 0x1C) Bit Timing and Prescaler Register -------- */ +#define MCAN_BTP_SJW_Pos 0 +#define MCAN_BTP_SJW_Msk (0xfu << MCAN_BTP_SJW_Pos) /**< \brief (MCAN_BTP) (Re) Synchronization Jump Width */ +#define MCAN_BTP_SJW(value) ((MCAN_BTP_SJW_Msk & ((value) << MCAN_BTP_SJW_Pos))) +#define MCAN_BTP_TSEG2_Pos 4 +#define MCAN_BTP_TSEG2_Msk (0xfu << MCAN_BTP_TSEG2_Pos) /**< \brief (MCAN_BTP) Time Segment After Sample Point */ +#define MCAN_BTP_TSEG2(value) ((MCAN_BTP_TSEG2_Msk & ((value) << MCAN_BTP_TSEG2_Pos))) +#define MCAN_BTP_TSEG1_Pos 8 +#define MCAN_BTP_TSEG1_Msk (0x3fu << MCAN_BTP_TSEG1_Pos) /**< \brief (MCAN_BTP) Time Segment Before Sample Point */ +#define MCAN_BTP_TSEG1(value) ((MCAN_BTP_TSEG1_Msk & ((value) << MCAN_BTP_TSEG1_Pos))) +#define MCAN_BTP_BRP_Pos 16 +#define MCAN_BTP_BRP_Msk (0x3ffu << MCAN_BTP_BRP_Pos) /**< \brief (MCAN_BTP) Baud Rate Prescaler */ +#define MCAN_BTP_BRP(value) ((MCAN_BTP_BRP_Msk & ((value) << MCAN_BTP_BRP_Pos))) +/* -------- MCAN_TSCC : (MCAN Offset: 0x20) Timestamp Counter Configuration Register -------- */ +#define MCAN_TSCC_TSS_Pos 0 +#define MCAN_TSCC_TSS_Msk (0x3u << MCAN_TSCC_TSS_Pos) /**< \brief (MCAN_TSCC) Timestamp Select */ +#define MCAN_TSCC_TSS(value) ((MCAN_TSCC_TSS_Msk & ((value) << MCAN_TSCC_TSS_Pos))) +#define MCAN_TSCC_TSS_ALWAYS_0 (0x0u << 0) /**< \brief (MCAN_TSCC) Timestamp counter value always 0x0000 */ +#define MCAN_TSCC_TSS_TCP_INC (0x1u << 0) /**< \brief (MCAN_TSCC) Timestamp counter value incremented according to TCP */ +#define MCAN_TSCC_TSS_EXT_TIMESTAMP (0x2u << 0) /**< \brief (MCAN_TSCC) External timestamp counter value used */ +#define MCAN_TSCC_TCP_Pos 16 +#define MCAN_TSCC_TCP_Msk (0xfu << MCAN_TSCC_TCP_Pos) /**< \brief (MCAN_TSCC) Timestamp Counter Prescaler */ +#define MCAN_TSCC_TCP(value) ((MCAN_TSCC_TCP_Msk & ((value) << MCAN_TSCC_TCP_Pos))) +/* -------- MCAN_TSCV : (MCAN Offset: 0x24) Timestamp Counter Value Register -------- */ +#define MCAN_TSCV_TSC_Pos 0 +#define MCAN_TSCV_TSC_Msk (0xffffu << MCAN_TSCV_TSC_Pos) /**< \brief (MCAN_TSCV) Timestamp Counter (cleared on write) */ +#define MCAN_TSCV_TSC(value) ((MCAN_TSCV_TSC_Msk & ((value) << MCAN_TSCV_TSC_Pos))) +/* -------- MCAN_TOCC : (MCAN Offset: 0x28) Timeout Counter Configuration Register -------- */ +#define MCAN_TOCC_ETOC (0x1u << 0) /**< \brief (MCAN_TOCC) Enable Timeout Counter */ +#define MCAN_TOCC_ETOC_NO_TIMEOUT (0x0u << 0) /**< \brief (MCAN_TOCC) Timeout Counter disabled. */ +#define MCAN_TOCC_ETOC_TOS_CONTROLLED (0x1u << 0) /**< \brief (MCAN_TOCC) Timeout Counter enabled. */ +#define MCAN_TOCC_TOS_Pos 1 +#define MCAN_TOCC_TOS_Msk (0x3u << MCAN_TOCC_TOS_Pos) /**< \brief (MCAN_TOCC) Timeout Select */ +#define MCAN_TOCC_TOS(value) ((MCAN_TOCC_TOS_Msk & ((value) << MCAN_TOCC_TOS_Pos))) +#define MCAN_TOCC_TOS_CONTINUOUS (0x0u << 1) /**< \brief (MCAN_TOCC) Continuous operation */ +#define MCAN_TOCC_TOS_TX_EV_TIMEOUT (0x1u << 1) /**< \brief (MCAN_TOCC) Timeout controlled by Tx Event FIFO */ +#define MCAN_TOCC_TOS_RX0_EV_TIMEOUT (0x2u << 1) /**< \brief (MCAN_TOCC) Timeout controlled by Receive FIFO 0 */ +#define MCAN_TOCC_TOS_RX1_EV_TIMEOUT (0x3u << 1) /**< \brief (MCAN_TOCC) Timeout controlled by Receive FIFO 1 */ +#define MCAN_TOCC_TOP_Pos 16 +#define MCAN_TOCC_TOP_Msk (0xffffu << MCAN_TOCC_TOP_Pos) /**< \brief (MCAN_TOCC) Timeout Period */ +#define MCAN_TOCC_TOP(value) ((MCAN_TOCC_TOP_Msk & ((value) << MCAN_TOCC_TOP_Pos))) +/* -------- MCAN_TOCV : (MCAN Offset: 0x2C) Timeout Counter Value Register -------- */ +#define MCAN_TOCV_TOC_Pos 0 +#define MCAN_TOCV_TOC_Msk (0xffffu << MCAN_TOCV_TOC_Pos) /**< \brief (MCAN_TOCV) Timeout Counter (cleared on write) */ +#define MCAN_TOCV_TOC(value) ((MCAN_TOCV_TOC_Msk & ((value) << MCAN_TOCV_TOC_Pos))) +/* -------- MCAN_ECR : (MCAN Offset: 0x40) Error Counter Register -------- */ +#define MCAN_ECR_TEC_Pos 0 +#define MCAN_ECR_TEC_Msk (0xffu << MCAN_ECR_TEC_Pos) /**< \brief (MCAN_ECR) Transmit Error Counter */ +#define MCAN_ECR_REC_Pos 8 +#define MCAN_ECR_REC_Msk (0x7fu << MCAN_ECR_REC_Pos) /**< \brief (MCAN_ECR) Receive Error Counter */ +#define MCAN_ECR_RP (0x1u << 15) /**< \brief (MCAN_ECR) Receive Error Passive */ +#define MCAN_ECR_CEL_Pos 16 +#define MCAN_ECR_CEL_Msk (0xffu << MCAN_ECR_CEL_Pos) /**< \brief (MCAN_ECR) CAN Error Logging (cleared on read) */ +/* -------- MCAN_PSR : (MCAN Offset: 0x44) Protocol Status Register -------- */ +#define MCAN_PSR_LEC_Pos 0 +#define MCAN_PSR_LEC_Msk (0x7u << MCAN_PSR_LEC_Pos) /**< \brief (MCAN_PSR) Last Error Code (set to 111 on read) */ +#define MCAN_PSR_LEC_NO_ERROR (0x0u << 0) /**< \brief (MCAN_PSR) No error occurred since LEC has been reset by successful reception or transmission. */ +#define MCAN_PSR_LEC_STUFF_ERROR (0x1u << 0) /**< \brief (MCAN_PSR) More than 5 equal bits in a sequence have occurred in a part of a received meSsage where this is not allowed. */ +#define MCAN_PSR_LEC_FORM_ERROR (0x2u << 0) /**< \brief (MCAN_PSR) A fixed format part of a received frame has the wrong format. */ +#define MCAN_PSR_LEC_ACK_ERROR (0x3u << 0) /**< \brief (MCAN_PSR) The message transmitted by the MCAN was not acknowledged by another node. */ +#define MCAN_PSR_LEC_BIT1_ERROR (0x4u << 0) /**< \brief (MCAN_PSR) During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant. */ +#define MCAN_PSR_LEC_BIT0_ERROR (0x5u << 0) /**< \brief (MCAN_PSR) During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the processor to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). */ +#define MCAN_PSR_LEC_CRC_ERROR (0x6u << 0) /**< \brief (MCAN_PSR) The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. */ +#define MCAN_PSR_LEC_NO_CHANGE (0x7u << 0) /**< \brief (MCAN_PSR) Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows the value '7', no CAN bus event was detected since the last processor read access to the Protocol Status Register. */ +#define MCAN_PSR_ACT_Pos 3 +#define MCAN_PSR_ACT_Msk (0x3u << MCAN_PSR_ACT_Pos) /**< \brief (MCAN_PSR) Activity */ +#define MCAN_PSR_ACT_SYNCHRONIZING (0x0u << 3) /**< \brief (MCAN_PSR) Node is synchronizing on CAN communication */ +#define MCAN_PSR_ACT_IDLE (0x1u << 3) /**< \brief (MCAN_PSR) Node is neither receiver nor transmitter */ +#define MCAN_PSR_ACT_RECEIVER (0x2u << 3) /**< \brief (MCAN_PSR) Node is operating as receiver */ +#define MCAN_PSR_ACT_TRANSMITTER (0x3u << 3) /**< \brief (MCAN_PSR) Node is operating as transmitter */ +#define MCAN_PSR_EP (0x1u << 5) /**< \brief (MCAN_PSR) Error Passive */ +#define MCAN_PSR_EW (0x1u << 6) /**< \brief (MCAN_PSR) Warning Status */ +#define MCAN_PSR_BO (0x1u << 7) /**< \brief (MCAN_PSR) Bus_Off Status */ +#define MCAN_PSR_FLEC_Pos 8 +#define MCAN_PSR_FLEC_Msk (0x7u << MCAN_PSR_FLEC_Pos) /**< \brief (MCAN_PSR) Fast Last Error Code (set to 111 on read) */ +#define MCAN_PSR_RESI (0x1u << 11) /**< \brief (MCAN_PSR) ESI Flag of Last Received CAN FD Message (cleared on read) */ +#define MCAN_PSR_RBRS (0x1u << 12) /**< \brief (MCAN_PSR) BRS Flag of Last Received CAN FD Message (cleared on read) */ +#define MCAN_PSR_REDL (0x1u << 13) /**< \brief (MCAN_PSR) Received a CAN FD Message (cleared on read) */ +/* -------- MCAN_IR : (MCAN Offset: 0x50) Interrupt Register -------- */ +#define MCAN_IR_RF0N (0x1u << 0) /**< \brief (MCAN_IR) Receive FIFO 0 New Message */ +#define MCAN_IR_RF0W (0x1u << 1) /**< \brief (MCAN_IR) Receive FIFO 0 Watermark Reached */ +#define MCAN_IR_RF0F (0x1u << 2) /**< \brief (MCAN_IR) Receive FIFO 0 Full */ +#define MCAN_IR_RF0L (0x1u << 3) /**< \brief (MCAN_IR) Receive FIFO 0 Message Lost */ +#define MCAN_IR_RF1N (0x1u << 4) /**< \brief (MCAN_IR) Receive FIFO 1 New Message */ +#define MCAN_IR_RF1W (0x1u << 5) /**< \brief (MCAN_IR) Receive FIFO 1 Watermark Reached */ +#define MCAN_IR_RF1F (0x1u << 6) /**< \brief (MCAN_IR) Receive FIFO 1 Full */ +#define MCAN_IR_RF1L (0x1u << 7) /**< \brief (MCAN_IR) Receive FIFO 1 Message Lost */ +#define MCAN_IR_HPM (0x1u << 8) /**< \brief (MCAN_IR) High Priority Message */ +#define MCAN_IR_TC (0x1u << 9) /**< \brief (MCAN_IR) Transmission Completed */ +#define MCAN_IR_TCF (0x1u << 10) /**< \brief (MCAN_IR) Transmission Cancellation Finished */ +#define MCAN_IR_TFE (0x1u << 11) /**< \brief (MCAN_IR) Tx FIFO Empty */ +#define MCAN_IR_TEFN (0x1u << 12) /**< \brief (MCAN_IR) Tx Event FIFO New Entry */ +#define MCAN_IR_TEFW (0x1u << 13) /**< \brief (MCAN_IR) Tx Event FIFO Watermark Reached */ +#define MCAN_IR_TEFF (0x1u << 14) /**< \brief (MCAN_IR) Tx Event FIFO Full */ +#define MCAN_IR_TEFL (0x1u << 15) /**< \brief (MCAN_IR) Tx Event FIFO Element Lost */ +#define MCAN_IR_TSW (0x1u << 16) /**< \brief (MCAN_IR) Timestamp Wraparound */ +#define MCAN_IR_MRAF (0x1u << 17) /**< \brief (MCAN_IR) Message RAM Access Failure */ +#define MCAN_IR_TOO (0x1u << 18) /**< \brief (MCAN_IR) Timeout Occurred */ +#define MCAN_IR_DRX (0x1u << 19) /**< \brief (MCAN_IR) Message stored to Dedicated Receive Buffer */ +#define MCAN_IR_ELO (0x1u << 22) /**< \brief (MCAN_IR) Error Logging Overflow */ +#define MCAN_IR_EP (0x1u << 23) /**< \brief (MCAN_IR) Error Passive */ +#define MCAN_IR_EW (0x1u << 24) /**< \brief (MCAN_IR) Warning Status */ +#define MCAN_IR_BO (0x1u << 25) /**< \brief (MCAN_IR) Bus_Off Status */ +#define MCAN_IR_WDI (0x1u << 26) /**< \brief (MCAN_IR) Watchdog Interrupt */ +#define MCAN_IR_CRCE (0x1u << 27) /**< \brief (MCAN_IR) CRC Error */ +#define MCAN_IR_BE (0x1u << 28) /**< \brief (MCAN_IR) Bit Error */ +#define MCAN_IR_ACKE (0x1u << 29) /**< \brief (MCAN_IR) Acknowledge Error */ +#define MCAN_IR_FOE (0x1u << 30) /**< \brief (MCAN_IR) Format Error */ +#define MCAN_IR_STE (0x1u << 31) /**< \brief (MCAN_IR) Stuff Error */ +/* -------- MCAN_IE : (MCAN Offset: 0x54) Interrupt Enable Register -------- */ +#define MCAN_IE_RF0NE (0x1u << 0) /**< \brief (MCAN_IE) Receive FIFO 0 New Message Interrupt Enable */ +#define MCAN_IE_RF0WE (0x1u << 1) /**< \brief (MCAN_IE) Receive FIFO 0 Watermark Reached Interrupt Enable */ +#define MCAN_IE_RF0FE (0x1u << 2) /**< \brief (MCAN_IE) Receive FIFO 0 Full Interrupt Enable */ +#define MCAN_IE_RF0LE (0x1u << 3) /**< \brief (MCAN_IE) Receive FIFO 0 Message Lost Interrupt Enable */ +#define MCAN_IE_RF1NE (0x1u << 4) /**< \brief (MCAN_IE) Receive FIFO 1 New Message Interrupt Enable */ +#define MCAN_IE_RF1WE (0x1u << 5) /**< \brief (MCAN_IE) Receive FIFO 1 Watermark Reached Interrupt Enable */ +#define MCAN_IE_RF1FE (0x1u << 6) /**< \brief (MCAN_IE) Receive FIFO 1 Full Interrupt Enable */ +#define MCAN_IE_RF1LE (0x1u << 7) /**< \brief (MCAN_IE) Receive FIFO 1 Message Lost Interrupt Enable */ +#define MCAN_IE_HPME (0x1u << 8) /**< \brief (MCAN_IE) High Priority Message Interrupt Enable */ +#define MCAN_IE_TCE (0x1u << 9) /**< \brief (MCAN_IE) Transmission Completed Interrupt Enable */ +#define MCAN_IE_TCFE (0x1u << 10) /**< \brief (MCAN_IE) Transmission Cancellation Finished Interrupt Enable */ +#define MCAN_IE_TFEE (0x1u << 11) /**< \brief (MCAN_IE) Tx FIFO Empty Interrupt Enable */ +#define MCAN_IE_TEFNE (0x1u << 12) /**< \brief (MCAN_IE) Tx Event FIFO New Entry Interrupt Enable */ +#define MCAN_IE_TEFWE (0x1u << 13) /**< \brief (MCAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable */ +#define MCAN_IE_TEFFE (0x1u << 14) /**< \brief (MCAN_IE) Tx Event FIFO Full Interrupt Enable */ +#define MCAN_IE_TEFLE (0x1u << 15) /**< \brief (MCAN_IE) Tx Event FIFO Event Lost Interrupt Enable */ +#define MCAN_IE_TSWE (0x1u << 16) /**< \brief (MCAN_IE) Timestamp Wraparound Interrupt Enable */ +#define MCAN_IE_MRAFE (0x1u << 17) /**< \brief (MCAN_IE) Message RAM Access Failure Interrupt Enable */ +#define MCAN_IE_TOOE (0x1u << 18) /**< \brief (MCAN_IE) Timeout Occurred Interrupt Enable */ +#define MCAN_IE_DRXE (0x1u << 19) /**< \brief (MCAN_IE) Message stored to Dedicated Receive Buffer Interrupt Enable */ +#define MCAN_IE_ELOE (0x1u << 22) /**< \brief (MCAN_IE) Error Logging Overflow Interrupt Enable */ +#define MCAN_IE_EPE (0x1u << 23) /**< \brief (MCAN_IE) Error Passive Interrupt Enable */ +#define MCAN_IE_EWE (0x1u << 24) /**< \brief (MCAN_IE) Warning Status Interrupt Enable */ +#define MCAN_IE_BOE (0x1u << 25) /**< \brief (MCAN_IE) Bus_Off Status Interrupt Enable */ +#define MCAN_IE_WDIE (0x1u << 26) /**< \brief (MCAN_IE) Watchdog Interrupt Enable */ +#define MCAN_IE_CRCEE (0x1u << 27) /**< \brief (MCAN_IE) CRC Error Interrupt Enable */ +#define MCAN_IE_BEE (0x1u << 28) /**< \brief (MCAN_IE) Bit Error Interrupt Enable */ +#define MCAN_IE_ACKEE (0x1u << 29) /**< \brief (MCAN_IE) Acknowledge Error Interrupt Enable */ +#define MCAN_IE_FOEE (0x1u << 30) /**< \brief (MCAN_IE) Format Error Interrupt Enable */ +#define MCAN_IE_STEE (0x1u << 31) /**< \brief (MCAN_IE) Stuff Error Interrupt Enable */ +/* -------- MCAN_ILS : (MCAN Offset: 0x58) Interrupt Line Select Register -------- */ +#define MCAN_ILS_RF0NL (0x1u << 0) /**< \brief (MCAN_ILS) Receive FIFO 0 New Message Interrupt Line */ +#define MCAN_ILS_RF0WL (0x1u << 1) /**< \brief (MCAN_ILS) Receive FIFO 0 Watermark Reached Interrupt Line */ +#define MCAN_ILS_RF0FL (0x1u << 2) /**< \brief (MCAN_ILS) Receive FIFO 0 Full Interrupt Line */ +#define MCAN_ILS_RF0LL (0x1u << 3) /**< \brief (MCAN_ILS) Receive FIFO 0 Message Lost Interrupt Line */ +#define MCAN_ILS_RF1NL (0x1u << 4) /**< \brief (MCAN_ILS) Receive FIFO 1 New Message Interrupt Line */ +#define MCAN_ILS_RF1WL (0x1u << 5) /**< \brief (MCAN_ILS) Receive FIFO 1 Watermark Reached Interrupt Line */ +#define MCAN_ILS_RF1FL (0x1u << 6) /**< \brief (MCAN_ILS) Receive FIFO 1 Full Interrupt Line */ +#define MCAN_ILS_RF1LL (0x1u << 7) /**< \brief (MCAN_ILS) Receive FIFO 1 Message Lost Interrupt Line */ +#define MCAN_ILS_HPML (0x1u << 8) /**< \brief (MCAN_ILS) High Priority Message Interrupt Line */ +#define MCAN_ILS_TCL (0x1u << 9) /**< \brief (MCAN_ILS) Transmission Completed Interrupt Line */ +#define MCAN_ILS_TCFL (0x1u << 10) /**< \brief (MCAN_ILS) Transmission Cancellation Finished Interrupt Line */ +#define MCAN_ILS_TFEL (0x1u << 11) /**< \brief (MCAN_ILS) Tx FIFO Empty Interrupt Line */ +#define MCAN_ILS_TEFNL (0x1u << 12) /**< \brief (MCAN_ILS) Tx Event FIFO New Entry Interrupt Line */ +#define MCAN_ILS_TEFWL (0x1u << 13) /**< \brief (MCAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line */ +#define MCAN_ILS_TEFFL (0x1u << 14) /**< \brief (MCAN_ILS) Tx Event FIFO Full Interrupt Line */ +#define MCAN_ILS_TEFLL (0x1u << 15) /**< \brief (MCAN_ILS) Tx Event FIFO Event Lost Interrupt Line */ +#define MCAN_ILS_TSWL (0x1u << 16) /**< \brief (MCAN_ILS) Timestamp Wraparound Interrupt Line */ +#define MCAN_ILS_MRAFL (0x1u << 17) /**< \brief (MCAN_ILS) Message RAM Access Failure Interrupt Line */ +#define MCAN_ILS_TOOL (0x1u << 18) /**< \brief (MCAN_ILS) Timeout Occurred Interrupt Line */ +#define MCAN_ILS_DRXL (0x1u << 19) /**< \brief (MCAN_ILS) Message stored to Dedicated Receive Buffer Interrupt Line */ +#define MCAN_ILS_ELOL (0x1u << 22) /**< \brief (MCAN_ILS) Error Logging Overflow Interrupt Line */ +#define MCAN_ILS_EPL (0x1u << 23) /**< \brief (MCAN_ILS) Error Passive Interrupt Line */ +#define MCAN_ILS_EWL (0x1u << 24) /**< \brief (MCAN_ILS) Warning Status Interrupt Line */ +#define MCAN_ILS_BOL (0x1u << 25) /**< \brief (MCAN_ILS) Bus_Off Status Interrupt Line */ +#define MCAN_ILS_WDIL (0x1u << 26) /**< \brief (MCAN_ILS) Watchdog Interrupt Line */ +#define MCAN_ILS_CRCEL (0x1u << 27) /**< \brief (MCAN_ILS) CRC Error Interrupt Line */ +#define MCAN_ILS_BEL (0x1u << 28) /**< \brief (MCAN_ILS) Bit Error Interrupt Line */ +#define MCAN_ILS_ACKEL (0x1u << 29) /**< \brief (MCAN_ILS) Acknowledge Error Interrupt Line */ +#define MCAN_ILS_FOEL (0x1u << 30) /**< \brief (MCAN_ILS) Format Error Interrupt Line */ +#define MCAN_ILS_STEL (0x1u << 31) /**< \brief (MCAN_ILS) Stuff Error Interrupt Line */ +/* -------- MCAN_ILE : (MCAN Offset: 0x5C) Interrupt Line Enable Register -------- */ +#define MCAN_ILE_EINT0 (0x1u << 0) /**< \brief (MCAN_ILE) Enable Interrupt Line 0 */ +#define MCAN_ILE_EINT1 (0x1u << 1) /**< \brief (MCAN_ILE) Enable Interrupt Line 1 */ +/* -------- MCAN_GFC : (MCAN Offset: 0x80) Global Filter Configuration Register -------- */ +#define MCAN_GFC_RRFE (0x1u << 0) /**< \brief (MCAN_GFC) Reject Remote Frames Extended */ +#define MCAN_GFC_RRFE_FILTER (0x0u << 0) /**< \brief (MCAN_GFC) Filter remote frames with 29-bit extended IDs. */ +#define MCAN_GFC_RRFE_REJECT (0x1u << 0) /**< \brief (MCAN_GFC) Reject all remote frames with 29-bit extended IDs. */ +#define MCAN_GFC_RRFS (0x1u << 1) /**< \brief (MCAN_GFC) Reject Remote Frames Standard */ +#define MCAN_GFC_RRFS_FILTER (0x0u << 1) /**< \brief (MCAN_GFC) Filter remote frames with 11-bit standard IDs. */ +#define MCAN_GFC_RRFS_REJECT (0x1u << 1) /**< \brief (MCAN_GFC) Reject all remote frames with 11-bit standard IDs. */ +#define MCAN_GFC_ANFE_Pos 2 +#define MCAN_GFC_ANFE_Msk (0x3u << MCAN_GFC_ANFE_Pos) /**< \brief (MCAN_GFC) Accept Non-matching Frames Extended */ +#define MCAN_GFC_ANFE(value) ((MCAN_GFC_ANFE_Msk & ((value) << MCAN_GFC_ANFE_Pos))) +#define MCAN_GFC_ANFE_RX_FIFO_0 (0x0u << 2) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 0 */ +#define MCAN_GFC_ANFE_RX_FIFO_1 (0x1u << 2) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 1 */ +#define MCAN_GFC_ANFS_Pos 4 +#define MCAN_GFC_ANFS_Msk (0x3u << MCAN_GFC_ANFS_Pos) /**< \brief (MCAN_GFC) Accept Non-matching Frames Standard */ +#define MCAN_GFC_ANFS(value) ((MCAN_GFC_ANFS_Msk & ((value) << MCAN_GFC_ANFS_Pos))) +#define MCAN_GFC_ANFS_RX_FIFO_0 (0x0u << 4) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 0 */ +#define MCAN_GFC_ANFS_RX_FIFO_1 (0x1u << 4) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 1 */ +/* -------- MCAN_SIDFC : (MCAN Offset: 0x84) Standard ID Filter Configuration Register -------- */ +#define MCAN_SIDFC_FLSSA_Pos 2 +#define MCAN_SIDFC_FLSSA_Msk (0x3fffu << MCAN_SIDFC_FLSSA_Pos) /**< \brief (MCAN_SIDFC) Filter List Standard Start Address */ +#define MCAN_SIDFC_FLSSA(value) ((MCAN_SIDFC_FLSSA_Msk & ((value) << MCAN_SIDFC_FLSSA_Pos))) +#define MCAN_SIDFC_LSS_Pos 16 +#define MCAN_SIDFC_LSS_Msk (0xffu << MCAN_SIDFC_LSS_Pos) /**< \brief (MCAN_SIDFC) List Size Standard */ +#define MCAN_SIDFC_LSS(value) ((MCAN_SIDFC_LSS_Msk & ((value) << MCAN_SIDFC_LSS_Pos))) +/* -------- MCAN_XIDFC : (MCAN Offset: 0x88) Extended ID Filter Configuration Register -------- */ +#define MCAN_XIDFC_FLESA_Pos 2 +#define MCAN_XIDFC_FLESA_Msk (0x3fffu << MCAN_XIDFC_FLESA_Pos) /**< \brief (MCAN_XIDFC) Filter List Extended Start Address */ +#define MCAN_XIDFC_FLESA(value) ((MCAN_XIDFC_FLESA_Msk & ((value) << MCAN_XIDFC_FLESA_Pos))) +#define MCAN_XIDFC_LSE_Pos 16 +#define MCAN_XIDFC_LSE_Msk (0x7fu << MCAN_XIDFC_LSE_Pos) /**< \brief (MCAN_XIDFC) List Size Extended */ +#define MCAN_XIDFC_LSE(value) ((MCAN_XIDFC_LSE_Msk & ((value) << MCAN_XIDFC_LSE_Pos))) +/* -------- MCAN_XIDAM : (MCAN Offset: 0x90) Extended ID AND Mask Register -------- */ +#define MCAN_XIDAM_EIDM_Pos 0 +#define MCAN_XIDAM_EIDM_Msk (0x1fffffffu << MCAN_XIDAM_EIDM_Pos) /**< \brief (MCAN_XIDAM) Extended ID Mask */ +#define MCAN_XIDAM_EIDM(value) ((MCAN_XIDAM_EIDM_Msk & ((value) << MCAN_XIDAM_EIDM_Pos))) +/* -------- MCAN_HPMS : (MCAN Offset: 0x94) High Priority Message Status Register -------- */ +#define MCAN_HPMS_BIDX_Pos 0 +#define MCAN_HPMS_BIDX_Msk (0x3fu << MCAN_HPMS_BIDX_Pos) /**< \brief (MCAN_HPMS) Buffer Index */ +#define MCAN_HPMS_MSI_Pos 6 +#define MCAN_HPMS_MSI_Msk (0x3u << MCAN_HPMS_MSI_Pos) /**< \brief (MCAN_HPMS) Message Storage Indicator */ +#define MCAN_HPMS_MSI_NO_FIFO_SEL (0x0u << 6) /**< \brief (MCAN_HPMS) No FIFO selected. */ +#define MCAN_HPMS_MSI_LOST (0x1u << 6) /**< \brief (MCAN_HPMS) FIFO message. */ +#define MCAN_HPMS_MSI_FIFO_0 (0x2u << 6) /**< \brief (MCAN_HPMS) Message stored in FIFO 0. */ +#define MCAN_HPMS_MSI_FIFO_1 (0x3u << 6) /**< \brief (MCAN_HPMS) Message stored in FIFO 1. */ +#define MCAN_HPMS_FIDX_Pos 8 +#define MCAN_HPMS_FIDX_Msk (0x7fu << MCAN_HPMS_FIDX_Pos) /**< \brief (MCAN_HPMS) Filter Index */ +#define MCAN_HPMS_FLST (0x1u << 15) /**< \brief (MCAN_HPMS) Filter List */ +/* -------- MCAN_NDAT1 : (MCAN Offset: 0x98) New Data 1 Register -------- */ +#define MCAN_NDAT1_ND0 (0x1u << 0) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND1 (0x1u << 1) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND2 (0x1u << 2) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND3 (0x1u << 3) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND4 (0x1u << 4) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND5 (0x1u << 5) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND6 (0x1u << 6) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND7 (0x1u << 7) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND8 (0x1u << 8) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND9 (0x1u << 9) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND10 (0x1u << 10) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND11 (0x1u << 11) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND12 (0x1u << 12) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND13 (0x1u << 13) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND14 (0x1u << 14) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND15 (0x1u << 15) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND16 (0x1u << 16) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND17 (0x1u << 17) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND18 (0x1u << 18) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND19 (0x1u << 19) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND20 (0x1u << 20) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND21 (0x1u << 21) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND22 (0x1u << 22) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND23 (0x1u << 23) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND24 (0x1u << 24) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND25 (0x1u << 25) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND26 (0x1u << 26) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND27 (0x1u << 27) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND28 (0x1u << 28) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND29 (0x1u << 29) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND30 (0x1u << 30) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND31 (0x1u << 31) /**< \brief (MCAN_NDAT1) New Data */ +/* -------- MCAN_NDAT2 : (MCAN Offset: 0x9C) New Data 2 Register -------- */ +#define MCAN_NDAT2_ND32 (0x1u << 0) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND33 (0x1u << 1) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND34 (0x1u << 2) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND35 (0x1u << 3) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND36 (0x1u << 4) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND37 (0x1u << 5) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND38 (0x1u << 6) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND39 (0x1u << 7) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND40 (0x1u << 8) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND41 (0x1u << 9) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND42 (0x1u << 10) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND43 (0x1u << 11) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND44 (0x1u << 12) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND45 (0x1u << 13) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND46 (0x1u << 14) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND47 (0x1u << 15) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND48 (0x1u << 16) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND49 (0x1u << 17) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND50 (0x1u << 18) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND51 (0x1u << 19) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND52 (0x1u << 20) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND53 (0x1u << 21) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND54 (0x1u << 22) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND55 (0x1u << 23) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND56 (0x1u << 24) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND57 (0x1u << 25) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND58 (0x1u << 26) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND59 (0x1u << 27) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND60 (0x1u << 28) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND61 (0x1u << 29) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND62 (0x1u << 30) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND63 (0x1u << 31) /**< \brief (MCAN_NDAT2) New Data */ +/* -------- MCAN_RXF0C : (MCAN Offset: 0xA0) Receive FIFO 0 Configuration Register -------- */ +#define MCAN_RXF0C_F0SA_Pos 2 +#define MCAN_RXF0C_F0SA_Msk (0x3fffu << MCAN_RXF0C_F0SA_Pos) /**< \brief (MCAN_RXF0C) Receive FIFO 0 Start Address */ +#define MCAN_RXF0C_F0SA(value) ((MCAN_RXF0C_F0SA_Msk & ((value) << MCAN_RXF0C_F0SA_Pos))) +#define MCAN_RXF0C_F0S_Pos 16 +#define MCAN_RXF0C_F0S_Msk (0x7fu << MCAN_RXF0C_F0S_Pos) /**< \brief (MCAN_RXF0C) Receive FIFO 0 Start Address */ +#define MCAN_RXF0C_F0S(value) ((MCAN_RXF0C_F0S_Msk & ((value) << MCAN_RXF0C_F0S_Pos))) +#define MCAN_RXF0C_F0WM_Pos 24 +#define MCAN_RXF0C_F0WM_Msk (0x7fu << MCAN_RXF0C_F0WM_Pos) /**< \brief (MCAN_RXF0C) Receive FIFO 0 Watermark */ +#define MCAN_RXF0C_F0WM(value) ((MCAN_RXF0C_F0WM_Msk & ((value) << MCAN_RXF0C_F0WM_Pos))) +#define MCAN_RXF0C_F0OM (0x1u << 31) /**< \brief (MCAN_RXF0C) FIFO 0 Operation Mode */ +/* -------- MCAN_RXF0S : (MCAN Offset: 0xA4) Receive FIFO 0 Status Register -------- */ +#define MCAN_RXF0S_F0FL_Pos 0 +#define MCAN_RXF0S_F0FL_Msk (0x7fu << MCAN_RXF0S_F0FL_Pos) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Fill Level */ +#define MCAN_RXF0S_F0GI_Pos 8 +#define MCAN_RXF0S_F0GI_Msk (0x3fu << MCAN_RXF0S_F0GI_Pos) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Get Index */ +#define MCAN_RXF0S_F0PI_Pos 16 +#define MCAN_RXF0S_F0PI_Msk (0x3fu << MCAN_RXF0S_F0PI_Pos) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Put Index */ +#define MCAN_RXF0S_F0F (0x1u << 24) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Fill Level */ +#define MCAN_RXF0S_RF0L (0x1u << 25) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Message Lost */ +/* -------- MCAN_RXF0A : (MCAN Offset: 0xA8) Receive FIFO 0 Acknowledge Register -------- */ +#define MCAN_RXF0A_F0AI_Pos 0 +#define MCAN_RXF0A_F0AI_Msk (0x3fu << MCAN_RXF0A_F0AI_Pos) /**< \brief (MCAN_RXF0A) Receive FIFO 0 Acknowledge Index */ +#define MCAN_RXF0A_F0AI(value) ((MCAN_RXF0A_F0AI_Msk & ((value) << MCAN_RXF0A_F0AI_Pos))) +/* -------- MCAN_RXBC : (MCAN Offset: 0xAC) Receive Rx Buffer Configuration Register -------- */ +#define MCAN_RXBC_RBSA_Pos 2 +#define MCAN_RXBC_RBSA_Msk (0x3fffu << MCAN_RXBC_RBSA_Pos) /**< \brief (MCAN_RXBC) Receive Buffer Start Address */ +#define MCAN_RXBC_RBSA(value) ((MCAN_RXBC_RBSA_Msk & ((value) << MCAN_RXBC_RBSA_Pos))) +/* -------- MCAN_RXF1C : (MCAN Offset: 0xB0) Receive FIFO 1 Configuration Register -------- */ +#define MCAN_RXF1C_F1SA_Pos 2 +#define MCAN_RXF1C_F1SA_Msk (0x3fffu << MCAN_RXF1C_F1SA_Pos) /**< \brief (MCAN_RXF1C) Receive FIFO 1 Start Address */ +#define MCAN_RXF1C_F1SA(value) ((MCAN_RXF1C_F1SA_Msk & ((value) << MCAN_RXF1C_F1SA_Pos))) +#define MCAN_RXF1C_F1S_Pos 16 +#define MCAN_RXF1C_F1S_Msk (0x7fu << MCAN_RXF1C_F1S_Pos) /**< \brief (MCAN_RXF1C) Receive FIFO 1 Start Address */ +#define MCAN_RXF1C_F1S(value) ((MCAN_RXF1C_F1S_Msk & ((value) << MCAN_RXF1C_F1S_Pos))) +#define MCAN_RXF1C_F1WM_Pos 24 +#define MCAN_RXF1C_F1WM_Msk (0x7fu << MCAN_RXF1C_F1WM_Pos) /**< \brief (MCAN_RXF1C) Receive FIFO 1 Watermark */ +#define MCAN_RXF1C_F1WM(value) ((MCAN_RXF1C_F1WM_Msk & ((value) << MCAN_RXF1C_F1WM_Pos))) +#define MCAN_RXF1C_F1OM (0x1u << 31) /**< \brief (MCAN_RXF1C) FIFO 1 Operation Mode */ +/* -------- MCAN_RXF1S : (MCAN Offset: 0xB4) Receive FIFO 1 Status Register -------- */ +#define MCAN_RXF1S_F1FL_Pos 0 +#define MCAN_RXF1S_F1FL_Msk (0x7fu << MCAN_RXF1S_F1FL_Pos) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Fill Level */ +#define MCAN_RXF1S_F1GI_Pos 8 +#define MCAN_RXF1S_F1GI_Msk (0x3fu << MCAN_RXF1S_F1GI_Pos) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Get Index */ +#define MCAN_RXF1S_F1PI_Pos 16 +#define MCAN_RXF1S_F1PI_Msk (0x3fu << MCAN_RXF1S_F1PI_Pos) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Put Index */ +#define MCAN_RXF1S_F1F (0x1u << 24) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Fill Level */ +#define MCAN_RXF1S_RF1L (0x1u << 25) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Message Lost */ +#define MCAN_RXF1S_DMS_Pos 30 +#define MCAN_RXF1S_DMS_Msk (0x3u << MCAN_RXF1S_DMS_Pos) /**< \brief (MCAN_RXF1S) Debug Message Status */ +#define MCAN_RXF1S_DMS_IDLE (0x0u << 30) /**< \brief (MCAN_RXF1S) Idle state, wait for reception of debug messages, DMA request is cleared. */ +#define MCAN_RXF1S_DMS_MSG_A (0x1u << 30) /**< \brief (MCAN_RXF1S) Debug message A received. */ +#define MCAN_RXF1S_DMS_MSG_AB (0x2u << 30) /**< \brief (MCAN_RXF1S) Debug messages A, B received. */ +#define MCAN_RXF1S_DMS_MSG_ABC (0x3u << 30) /**< \brief (MCAN_RXF1S) Debug messages A, B, C received, DMA request is set. */ +/* -------- MCAN_RXF1A : (MCAN Offset: 0xB8) Receive FIFO 1 Acknowledge Register -------- */ +#define MCAN_RXF1A_F1AI_Pos 0 +#define MCAN_RXF1A_F1AI_Msk (0x3fu << MCAN_RXF1A_F1AI_Pos) /**< \brief (MCAN_RXF1A) Receive FIFO 1 Acknowledge Index */ +#define MCAN_RXF1A_F1AI(value) ((MCAN_RXF1A_F1AI_Msk & ((value) << MCAN_RXF1A_F1AI_Pos))) +/* -------- MCAN_RXESC : (MCAN Offset: 0xBC) Receive Buffer / FIFO Element Size Configuration Register -------- */ +#define MCAN_RXESC_F0DS_Pos 0 +#define MCAN_RXESC_F0DS_Msk (0x7u << MCAN_RXESC_F0DS_Pos) /**< \brief (MCAN_RXESC) Receive FIFO 0 Data Field Size */ +#define MCAN_RXESC_F0DS(value) ((MCAN_RXESC_F0DS_Msk & ((value) << MCAN_RXESC_F0DS_Pos))) +#define MCAN_RXESC_F0DS_8_BYTE (0x0u << 0) /**< \brief (MCAN_RXESC) 8 byte data field */ +#define MCAN_RXESC_F0DS_12_BYTE (0x1u << 0) /**< \brief (MCAN_RXESC) 12 byte data field */ +#define MCAN_RXESC_F0DS_16_BYTE (0x2u << 0) /**< \brief (MCAN_RXESC) 16 byte data field */ +#define MCAN_RXESC_F0DS_20_BYTE (0x3u << 0) /**< \brief (MCAN_RXESC) 20 byte data field */ +#define MCAN_RXESC_F0DS_24_BYTE (0x4u << 0) /**< \brief (MCAN_RXESC) 24 byte data field */ +#define MCAN_RXESC_F0DS_32_BYTE (0x5u << 0) /**< \brief (MCAN_RXESC) 32 byte data field */ +#define MCAN_RXESC_F0DS_48_BYTE (0x6u << 0) /**< \brief (MCAN_RXESC) 48 byte data field */ +#define MCAN_RXESC_F0DS_64_BYTE (0x7u << 0) /**< \brief (MCAN_RXESC) 64 byte data field */ +#define MCAN_RXESC_F1DS_Pos 4 +#define MCAN_RXESC_F1DS_Msk (0x7u << MCAN_RXESC_F1DS_Pos) /**< \brief (MCAN_RXESC) Receive FIFO 1 Data Field Size */ +#define MCAN_RXESC_F1DS(value) ((MCAN_RXESC_F1DS_Msk & ((value) << MCAN_RXESC_F1DS_Pos))) +#define MCAN_RXESC_F1DS_8_BYTE (0x0u << 4) /**< \brief (MCAN_RXESC) 8 byte data field */ +#define MCAN_RXESC_F1DS_12_BYTE (0x1u << 4) /**< \brief (MCAN_RXESC) 12 byte data field */ +#define MCAN_RXESC_F1DS_16_BYTE (0x2u << 4) /**< \brief (MCAN_RXESC) 16 byte data field */ +#define MCAN_RXESC_F1DS_20_BYTE (0x3u << 4) /**< \brief (MCAN_RXESC) 20 byte data field */ +#define MCAN_RXESC_F1DS_24_BYTE (0x4u << 4) /**< \brief (MCAN_RXESC) 24 byte data field */ +#define MCAN_RXESC_F1DS_32_BYTE (0x5u << 4) /**< \brief (MCAN_RXESC) 32 byte data field */ +#define MCAN_RXESC_F1DS_48_BYTE (0x6u << 4) /**< \brief (MCAN_RXESC) 48 byte data field */ +#define MCAN_RXESC_F1DS_64_BYTE (0x7u << 4) /**< \brief (MCAN_RXESC) 64 byte data field */ +#define MCAN_RXESC_RBDS_Pos 8 +#define MCAN_RXESC_RBDS_Msk (0x7u << MCAN_RXESC_RBDS_Pos) /**< \brief (MCAN_RXESC) Receive Buffer Data Field Size */ +#define MCAN_RXESC_RBDS(value) ((MCAN_RXESC_RBDS_Msk & ((value) << MCAN_RXESC_RBDS_Pos))) +#define MCAN_RXESC_RBDS_8_BYTE (0x0u << 8) /**< \brief (MCAN_RXESC) 8 byte data field */ +#define MCAN_RXESC_RBDS_12_BYTE (0x1u << 8) /**< \brief (MCAN_RXESC) 12 byte data field */ +#define MCAN_RXESC_RBDS_16_BYTE (0x2u << 8) /**< \brief (MCAN_RXESC) 16 byte data field */ +#define MCAN_RXESC_RBDS_20_BYTE (0x3u << 8) /**< \brief (MCAN_RXESC) 20 byte data field */ +#define MCAN_RXESC_RBDS_24_BYTE (0x4u << 8) /**< \brief (MCAN_RXESC) 24 byte data field */ +#define MCAN_RXESC_RBDS_32_BYTE (0x5u << 8) /**< \brief (MCAN_RXESC) 32 byte data field */ +#define MCAN_RXESC_RBDS_48_BYTE (0x6u << 8) /**< \brief (MCAN_RXESC) 48 byte data field */ +#define MCAN_RXESC_RBDS_64_BYTE (0x7u << 8) /**< \brief (MCAN_RXESC) 64 byte data field */ +/* -------- MCAN_TXBC : (MCAN Offset: 0xC0) Transmit Buffer Configuration Register -------- */ +#define MCAN_TXBC_TBSA_Pos 2 +#define MCAN_TXBC_TBSA_Msk (0x3fffu << MCAN_TXBC_TBSA_Pos) /**< \brief (MCAN_TXBC) Tx Buffers Start Address */ +#define MCAN_TXBC_TBSA(value) ((MCAN_TXBC_TBSA_Msk & ((value) << MCAN_TXBC_TBSA_Pos))) +#define MCAN_TXBC_NDTB_Pos 16 +#define MCAN_TXBC_NDTB_Msk (0x3fu << MCAN_TXBC_NDTB_Pos) /**< \brief (MCAN_TXBC) Number of Dedicated Transmit Buffers */ +#define MCAN_TXBC_NDTB(value) ((MCAN_TXBC_NDTB_Msk & ((value) << MCAN_TXBC_NDTB_Pos))) +#define MCAN_TXBC_TFQS_Pos 24 +#define MCAN_TXBC_TFQS_Msk (0x3fu << MCAN_TXBC_TFQS_Pos) /**< \brief (MCAN_TXBC) Transmit FIFO/Queue Size */ +#define MCAN_TXBC_TFQS(value) ((MCAN_TXBC_TFQS_Msk & ((value) << MCAN_TXBC_TFQS_Pos))) +#define MCAN_TXBC_TFQM (0x1u << 30) /**< \brief (MCAN_TXBC) Tx FIFO/Queue Mode */ +/* -------- MCAN_TXFQS : (MCAN Offset: 0xC4) Transmit FIFO/Queue Status Register -------- */ +#define MCAN_TXFQS_TFFL_Pos 0 +#define MCAN_TXFQS_TFFL_Msk (0x3fu << MCAN_TXFQS_TFFL_Pos) /**< \brief (MCAN_TXFQS) Tx FIFO Free Level */ +#define MCAN_TXFQS_TFGI_Pos 8 +#define MCAN_TXFQS_TFGI_Msk (0x1fu << MCAN_TXFQS_TFGI_Pos) /**< \brief (MCAN_TXFQS) Tx FIFO Get Index */ +#define MCAN_TXFQS_TFQPI_Pos 16 +#define MCAN_TXFQS_TFQPI_Msk (0x1fu << MCAN_TXFQS_TFQPI_Pos) /**< \brief (MCAN_TXFQS) Tx FIFO/Queue Put Index */ +#define MCAN_TXFQS_TFQF (0x1u << 21) /**< \brief (MCAN_TXFQS) Tx FIFO/Queue Full */ +/* -------- MCAN_TXESC : (MCAN Offset: 0xC8) Transmit Buffer Element Size Configuration Register -------- */ +#define MCAN_TXESC_TBDS_Pos 0 +#define MCAN_TXESC_TBDS_Msk (0x7u << MCAN_TXESC_TBDS_Pos) /**< \brief (MCAN_TXESC) Tx Buffer Data Field Size */ +#define MCAN_TXESC_TBDS(value) ((MCAN_TXESC_TBDS_Msk & ((value) << MCAN_TXESC_TBDS_Pos))) +#define MCAN_TXESC_TBDS_8_BYTE (0x0u << 0) /**< \brief (MCAN_TXESC) 8 byte data field */ +#define MCAN_TXESC_TBDS_12_BYTE (0x1u << 0) /**< \brief (MCAN_TXESC) 12 byte data field */ +#define MCAN_TXESC_TBDS_16_BYTE (0x2u << 0) /**< \brief (MCAN_TXESC) 16 byte data field */ +#define MCAN_TXESC_TBDS_20_BYTE (0x3u << 0) /**< \brief (MCAN_TXESC) 20 byte data field */ +#define MCAN_TXESC_TBDS_24_BYTE (0x4u << 0) /**< \brief (MCAN_TXESC) 24 byte data field */ +#define MCAN_TXESC_TBDS_32_BYTE (0x5u << 0) /**< \brief (MCAN_TXESC) 32 byte data field */ +#define MCAN_TXESC_TBDS_48_BYTE (0x6u << 0) /**< \brief (MCAN_TXESC) 48 byte data field */ +#define MCAN_TXESC_TBDS_64_BYTE (0x7u << 0) /**< \brief (MCAN_TXESC) 64 byte data field */ +/* -------- MCAN_TXBRP : (MCAN Offset: 0xCC) Transmit Buffer Request Pending Register -------- */ +#define MCAN_TXBRP_TRP0 (0x1u << 0) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 0 */ +#define MCAN_TXBRP_TRP1 (0x1u << 1) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 1 */ +#define MCAN_TXBRP_TRP2 (0x1u << 2) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 2 */ +#define MCAN_TXBRP_TRP3 (0x1u << 3) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 3 */ +#define MCAN_TXBRP_TRP4 (0x1u << 4) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 4 */ +#define MCAN_TXBRP_TRP5 (0x1u << 5) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 5 */ +#define MCAN_TXBRP_TRP6 (0x1u << 6) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 6 */ +#define MCAN_TXBRP_TRP7 (0x1u << 7) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 7 */ +#define MCAN_TXBRP_TRP8 (0x1u << 8) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 8 */ +#define MCAN_TXBRP_TRP9 (0x1u << 9) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 9 */ +#define MCAN_TXBRP_TRP10 (0x1u << 10) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 10 */ +#define MCAN_TXBRP_TRP11 (0x1u << 11) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 11 */ +#define MCAN_TXBRP_TRP12 (0x1u << 12) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 12 */ +#define MCAN_TXBRP_TRP13 (0x1u << 13) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 13 */ +#define MCAN_TXBRP_TRP14 (0x1u << 14) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 14 */ +#define MCAN_TXBRP_TRP15 (0x1u << 15) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 15 */ +#define MCAN_TXBRP_TRP16 (0x1u << 16) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 16 */ +#define MCAN_TXBRP_TRP17 (0x1u << 17) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 17 */ +#define MCAN_TXBRP_TRP18 (0x1u << 18) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 18 */ +#define MCAN_TXBRP_TRP19 (0x1u << 19) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 19 */ +#define MCAN_TXBRP_TRP20 (0x1u << 20) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 20 */ +#define MCAN_TXBRP_TRP21 (0x1u << 21) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 21 */ +#define MCAN_TXBRP_TRP22 (0x1u << 22) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 22 */ +#define MCAN_TXBRP_TRP23 (0x1u << 23) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 23 */ +#define MCAN_TXBRP_TRP24 (0x1u << 24) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 24 */ +#define MCAN_TXBRP_TRP25 (0x1u << 25) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 25 */ +#define MCAN_TXBRP_TRP26 (0x1u << 26) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 26 */ +#define MCAN_TXBRP_TRP27 (0x1u << 27) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 27 */ +#define MCAN_TXBRP_TRP28 (0x1u << 28) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 28 */ +#define MCAN_TXBRP_TRP29 (0x1u << 29) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 29 */ +#define MCAN_TXBRP_TRP30 (0x1u << 30) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 30 */ +#define MCAN_TXBRP_TRP31 (0x1u << 31) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 31 */ +/* -------- MCAN_TXBAR : (MCAN Offset: 0xD0) Transmit Buffer Add Request Register -------- */ +#define MCAN_TXBAR_AR0 (0x1u << 0) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 0 */ +#define MCAN_TXBAR_AR1 (0x1u << 1) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 1 */ +#define MCAN_TXBAR_AR2 (0x1u << 2) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 2 */ +#define MCAN_TXBAR_AR3 (0x1u << 3) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 3 */ +#define MCAN_TXBAR_AR4 (0x1u << 4) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 4 */ +#define MCAN_TXBAR_AR5 (0x1u << 5) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 5 */ +#define MCAN_TXBAR_AR6 (0x1u << 6) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 6 */ +#define MCAN_TXBAR_AR7 (0x1u << 7) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 7 */ +#define MCAN_TXBAR_AR8 (0x1u << 8) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 8 */ +#define MCAN_TXBAR_AR9 (0x1u << 9) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 9 */ +#define MCAN_TXBAR_AR10 (0x1u << 10) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 10 */ +#define MCAN_TXBAR_AR11 (0x1u << 11) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 11 */ +#define MCAN_TXBAR_AR12 (0x1u << 12) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 12 */ +#define MCAN_TXBAR_AR13 (0x1u << 13) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 13 */ +#define MCAN_TXBAR_AR14 (0x1u << 14) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 14 */ +#define MCAN_TXBAR_AR15 (0x1u << 15) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 15 */ +#define MCAN_TXBAR_AR16 (0x1u << 16) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 16 */ +#define MCAN_TXBAR_AR17 (0x1u << 17) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 17 */ +#define MCAN_TXBAR_AR18 (0x1u << 18) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 18 */ +#define MCAN_TXBAR_AR19 (0x1u << 19) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 19 */ +#define MCAN_TXBAR_AR20 (0x1u << 20) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 20 */ +#define MCAN_TXBAR_AR21 (0x1u << 21) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 21 */ +#define MCAN_TXBAR_AR22 (0x1u << 22) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 22 */ +#define MCAN_TXBAR_AR23 (0x1u << 23) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 23 */ +#define MCAN_TXBAR_AR24 (0x1u << 24) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 24 */ +#define MCAN_TXBAR_AR25 (0x1u << 25) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 25 */ +#define MCAN_TXBAR_AR26 (0x1u << 26) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 26 */ +#define MCAN_TXBAR_AR27 (0x1u << 27) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 27 */ +#define MCAN_TXBAR_AR28 (0x1u << 28) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 28 */ +#define MCAN_TXBAR_AR29 (0x1u << 29) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 29 */ +#define MCAN_TXBAR_AR30 (0x1u << 30) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 30 */ +#define MCAN_TXBAR_AR31 (0x1u << 31) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 31 */ +/* -------- MCAN_TXBCR : (MCAN Offset: 0xD4) Transmit Buffer Cancellation Request Register -------- */ +#define MCAN_TXBCR_CR0 (0x1u << 0) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 0 */ +#define MCAN_TXBCR_CR1 (0x1u << 1) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 1 */ +#define MCAN_TXBCR_CR2 (0x1u << 2) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 2 */ +#define MCAN_TXBCR_CR3 (0x1u << 3) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 3 */ +#define MCAN_TXBCR_CR4 (0x1u << 4) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 4 */ +#define MCAN_TXBCR_CR5 (0x1u << 5) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 5 */ +#define MCAN_TXBCR_CR6 (0x1u << 6) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 6 */ +#define MCAN_TXBCR_CR7 (0x1u << 7) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 7 */ +#define MCAN_TXBCR_CR8 (0x1u << 8) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 8 */ +#define MCAN_TXBCR_CR9 (0x1u << 9) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 9 */ +#define MCAN_TXBCR_CR10 (0x1u << 10) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 10 */ +#define MCAN_TXBCR_CR11 (0x1u << 11) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 11 */ +#define MCAN_TXBCR_CR12 (0x1u << 12) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 12 */ +#define MCAN_TXBCR_CR13 (0x1u << 13) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 13 */ +#define MCAN_TXBCR_CR14 (0x1u << 14) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 14 */ +#define MCAN_TXBCR_CR15 (0x1u << 15) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 15 */ +#define MCAN_TXBCR_CR16 (0x1u << 16) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 16 */ +#define MCAN_TXBCR_CR17 (0x1u << 17) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 17 */ +#define MCAN_TXBCR_CR18 (0x1u << 18) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 18 */ +#define MCAN_TXBCR_CR19 (0x1u << 19) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 19 */ +#define MCAN_TXBCR_CR20 (0x1u << 20) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 20 */ +#define MCAN_TXBCR_CR21 (0x1u << 21) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 21 */ +#define MCAN_TXBCR_CR22 (0x1u << 22) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 22 */ +#define MCAN_TXBCR_CR23 (0x1u << 23) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 23 */ +#define MCAN_TXBCR_CR24 (0x1u << 24) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 24 */ +#define MCAN_TXBCR_CR25 (0x1u << 25) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 25 */ +#define MCAN_TXBCR_CR26 (0x1u << 26) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 26 */ +#define MCAN_TXBCR_CR27 (0x1u << 27) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 27 */ +#define MCAN_TXBCR_CR28 (0x1u << 28) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 28 */ +#define MCAN_TXBCR_CR29 (0x1u << 29) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 29 */ +#define MCAN_TXBCR_CR30 (0x1u << 30) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 30 */ +#define MCAN_TXBCR_CR31 (0x1u << 31) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 31 */ +/* -------- MCAN_TXBTO : (MCAN Offset: 0xD8) Transmit Buffer Transmission Occurred Register -------- */ +#define MCAN_TXBTO_TO0 (0x1u << 0) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 0 */ +#define MCAN_TXBTO_TO1 (0x1u << 1) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 1 */ +#define MCAN_TXBTO_TO2 (0x1u << 2) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 2 */ +#define MCAN_TXBTO_TO3 (0x1u << 3) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 3 */ +#define MCAN_TXBTO_TO4 (0x1u << 4) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 4 */ +#define MCAN_TXBTO_TO5 (0x1u << 5) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 5 */ +#define MCAN_TXBTO_TO6 (0x1u << 6) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 6 */ +#define MCAN_TXBTO_TO7 (0x1u << 7) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 7 */ +#define MCAN_TXBTO_TO8 (0x1u << 8) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 8 */ +#define MCAN_TXBTO_TO9 (0x1u << 9) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 9 */ +#define MCAN_TXBTO_TO10 (0x1u << 10) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 10 */ +#define MCAN_TXBTO_TO11 (0x1u << 11) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 11 */ +#define MCAN_TXBTO_TO12 (0x1u << 12) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 12 */ +#define MCAN_TXBTO_TO13 (0x1u << 13) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 13 */ +#define MCAN_TXBTO_TO14 (0x1u << 14) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 14 */ +#define MCAN_TXBTO_TO15 (0x1u << 15) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 15 */ +#define MCAN_TXBTO_TO16 (0x1u << 16) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 16 */ +#define MCAN_TXBTO_TO17 (0x1u << 17) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 17 */ +#define MCAN_TXBTO_TO18 (0x1u << 18) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 18 */ +#define MCAN_TXBTO_TO19 (0x1u << 19) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 19 */ +#define MCAN_TXBTO_TO20 (0x1u << 20) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 20 */ +#define MCAN_TXBTO_TO21 (0x1u << 21) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 21 */ +#define MCAN_TXBTO_TO22 (0x1u << 22) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 22 */ +#define MCAN_TXBTO_TO23 (0x1u << 23) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 23 */ +#define MCAN_TXBTO_TO24 (0x1u << 24) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 24 */ +#define MCAN_TXBTO_TO25 (0x1u << 25) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 25 */ +#define MCAN_TXBTO_TO26 (0x1u << 26) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 26 */ +#define MCAN_TXBTO_TO27 (0x1u << 27) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 27 */ +#define MCAN_TXBTO_TO28 (0x1u << 28) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 28 */ +#define MCAN_TXBTO_TO29 (0x1u << 29) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 29 */ +#define MCAN_TXBTO_TO30 (0x1u << 30) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 30 */ +#define MCAN_TXBTO_TO31 (0x1u << 31) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 31 */ +/* -------- MCAN_TXBCF : (MCAN Offset: 0xDC) Transmit Buffer Cancellation Finished Register -------- */ +#define MCAN_TXBCF_CF0 (0x1u << 0) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 0 */ +#define MCAN_TXBCF_CF1 (0x1u << 1) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 1 */ +#define MCAN_TXBCF_CF2 (0x1u << 2) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 2 */ +#define MCAN_TXBCF_CF3 (0x1u << 3) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 3 */ +#define MCAN_TXBCF_CF4 (0x1u << 4) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 4 */ +#define MCAN_TXBCF_CF5 (0x1u << 5) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 5 */ +#define MCAN_TXBCF_CF6 (0x1u << 6) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 6 */ +#define MCAN_TXBCF_CF7 (0x1u << 7) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 7 */ +#define MCAN_TXBCF_CF8 (0x1u << 8) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 8 */ +#define MCAN_TXBCF_CF9 (0x1u << 9) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 9 */ +#define MCAN_TXBCF_CF10 (0x1u << 10) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 10 */ +#define MCAN_TXBCF_CF11 (0x1u << 11) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 11 */ +#define MCAN_TXBCF_CF12 (0x1u << 12) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 12 */ +#define MCAN_TXBCF_CF13 (0x1u << 13) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 13 */ +#define MCAN_TXBCF_CF14 (0x1u << 14) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 14 */ +#define MCAN_TXBCF_CF15 (0x1u << 15) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 15 */ +#define MCAN_TXBCF_CF16 (0x1u << 16) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 16 */ +#define MCAN_TXBCF_CF17 (0x1u << 17) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 17 */ +#define MCAN_TXBCF_CF18 (0x1u << 18) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 18 */ +#define MCAN_TXBCF_CF19 (0x1u << 19) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 19 */ +#define MCAN_TXBCF_CF20 (0x1u << 20) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 20 */ +#define MCAN_TXBCF_CF21 (0x1u << 21) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 21 */ +#define MCAN_TXBCF_CF22 (0x1u << 22) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 22 */ +#define MCAN_TXBCF_CF23 (0x1u << 23) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 23 */ +#define MCAN_TXBCF_CF24 (0x1u << 24) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 24 */ +#define MCAN_TXBCF_CF25 (0x1u << 25) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 25 */ +#define MCAN_TXBCF_CF26 (0x1u << 26) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 26 */ +#define MCAN_TXBCF_CF27 (0x1u << 27) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 27 */ +#define MCAN_TXBCF_CF28 (0x1u << 28) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 28 */ +#define MCAN_TXBCF_CF29 (0x1u << 29) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 29 */ +#define MCAN_TXBCF_CF30 (0x1u << 30) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 30 */ +#define MCAN_TXBCF_CF31 (0x1u << 31) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 31 */ +/* -------- MCAN_TXBTIE : (MCAN Offset: 0xE0) Transmit Buffer Transmission Interrupt Enable Register -------- */ +#define MCAN_TXBTIE_TIE0 (0x1u << 0) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 0 */ +#define MCAN_TXBTIE_TIE1 (0x1u << 1) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 1 */ +#define MCAN_TXBTIE_TIE2 (0x1u << 2) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 2 */ +#define MCAN_TXBTIE_TIE3 (0x1u << 3) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 3 */ +#define MCAN_TXBTIE_TIE4 (0x1u << 4) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 4 */ +#define MCAN_TXBTIE_TIE5 (0x1u << 5) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 5 */ +#define MCAN_TXBTIE_TIE6 (0x1u << 6) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 6 */ +#define MCAN_TXBTIE_TIE7 (0x1u << 7) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 7 */ +#define MCAN_TXBTIE_TIE8 (0x1u << 8) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 8 */ +#define MCAN_TXBTIE_TIE9 (0x1u << 9) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 9 */ +#define MCAN_TXBTIE_TIE10 (0x1u << 10) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 10 */ +#define MCAN_TXBTIE_TIE11 (0x1u << 11) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 11 */ +#define MCAN_TXBTIE_TIE12 (0x1u << 12) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 12 */ +#define MCAN_TXBTIE_TIE13 (0x1u << 13) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 13 */ +#define MCAN_TXBTIE_TIE14 (0x1u << 14) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 14 */ +#define MCAN_TXBTIE_TIE15 (0x1u << 15) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 15 */ +#define MCAN_TXBTIE_TIE16 (0x1u << 16) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 16 */ +#define MCAN_TXBTIE_TIE17 (0x1u << 17) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 17 */ +#define MCAN_TXBTIE_TIE18 (0x1u << 18) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 18 */ +#define MCAN_TXBTIE_TIE19 (0x1u << 19) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 19 */ +#define MCAN_TXBTIE_TIE20 (0x1u << 20) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 20 */ +#define MCAN_TXBTIE_TIE21 (0x1u << 21) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 21 */ +#define MCAN_TXBTIE_TIE22 (0x1u << 22) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 22 */ +#define MCAN_TXBTIE_TIE23 (0x1u << 23) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 23 */ +#define MCAN_TXBTIE_TIE24 (0x1u << 24) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 24 */ +#define MCAN_TXBTIE_TIE25 (0x1u << 25) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 25 */ +#define MCAN_TXBTIE_TIE26 (0x1u << 26) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 26 */ +#define MCAN_TXBTIE_TIE27 (0x1u << 27) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 27 */ +#define MCAN_TXBTIE_TIE28 (0x1u << 28) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 28 */ +#define MCAN_TXBTIE_TIE29 (0x1u << 29) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 29 */ +#define MCAN_TXBTIE_TIE30 (0x1u << 30) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 30 */ +#define MCAN_TXBTIE_TIE31 (0x1u << 31) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 31 */ +/* -------- MCAN_TXBCIE : (MCAN Offset: 0xE4) Transmit Buffer Cancellation Finished Interrupt Enable Register -------- */ +#define MCAN_TXBCIE_CFIE0 (0x1u << 0) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 0 */ +#define MCAN_TXBCIE_CFIE1 (0x1u << 1) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 1 */ +#define MCAN_TXBCIE_CFIE2 (0x1u << 2) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 2 */ +#define MCAN_TXBCIE_CFIE3 (0x1u << 3) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 3 */ +#define MCAN_TXBCIE_CFIE4 (0x1u << 4) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 4 */ +#define MCAN_TXBCIE_CFIE5 (0x1u << 5) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 5 */ +#define MCAN_TXBCIE_CFIE6 (0x1u << 6) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 6 */ +#define MCAN_TXBCIE_CFIE7 (0x1u << 7) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 7 */ +#define MCAN_TXBCIE_CFIE8 (0x1u << 8) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 8 */ +#define MCAN_TXBCIE_CFIE9 (0x1u << 9) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 9 */ +#define MCAN_TXBCIE_CFIE10 (0x1u << 10) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 10 */ +#define MCAN_TXBCIE_CFIE11 (0x1u << 11) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 11 */ +#define MCAN_TXBCIE_CFIE12 (0x1u << 12) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 12 */ +#define MCAN_TXBCIE_CFIE13 (0x1u << 13) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 13 */ +#define MCAN_TXBCIE_CFIE14 (0x1u << 14) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 14 */ +#define MCAN_TXBCIE_CFIE15 (0x1u << 15) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 15 */ +#define MCAN_TXBCIE_CFIE16 (0x1u << 16) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 16 */ +#define MCAN_TXBCIE_CFIE17 (0x1u << 17) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 17 */ +#define MCAN_TXBCIE_CFIE18 (0x1u << 18) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 18 */ +#define MCAN_TXBCIE_CFIE19 (0x1u << 19) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 19 */ +#define MCAN_TXBCIE_CFIE20 (0x1u << 20) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 20 */ +#define MCAN_TXBCIE_CFIE21 (0x1u << 21) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 21 */ +#define MCAN_TXBCIE_CFIE22 (0x1u << 22) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 22 */ +#define MCAN_TXBCIE_CFIE23 (0x1u << 23) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 23 */ +#define MCAN_TXBCIE_CFIE24 (0x1u << 24) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 24 */ +#define MCAN_TXBCIE_CFIE25 (0x1u << 25) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 25 */ +#define MCAN_TXBCIE_CFIE26 (0x1u << 26) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 26 */ +#define MCAN_TXBCIE_CFIE27 (0x1u << 27) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 27 */ +#define MCAN_TXBCIE_CFIE28 (0x1u << 28) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 28 */ +#define MCAN_TXBCIE_CFIE29 (0x1u << 29) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 29 */ +#define MCAN_TXBCIE_CFIE30 (0x1u << 30) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 30 */ +#define MCAN_TXBCIE_CFIE31 (0x1u << 31) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 31 */ +/* -------- MCAN_TXEFC : (MCAN Offset: 0xF0) Transmit Event FIFO Configuration Register -------- */ +#define MCAN_TXEFC_EFSA_Pos 2 +#define MCAN_TXEFC_EFSA_Msk (0x3fffu << MCAN_TXEFC_EFSA_Pos) /**< \brief (MCAN_TXEFC) Event FIFO Start Address */ +#define MCAN_TXEFC_EFSA(value) ((MCAN_TXEFC_EFSA_Msk & ((value) << MCAN_TXEFC_EFSA_Pos))) +#define MCAN_TXEFC_EFS_Pos 16 +#define MCAN_TXEFC_EFS_Msk (0x3fu << MCAN_TXEFC_EFS_Pos) /**< \brief (MCAN_TXEFC) Event FIFO Size */ +#define MCAN_TXEFC_EFS(value) ((MCAN_TXEFC_EFS_Msk & ((value) << MCAN_TXEFC_EFS_Pos))) +#define MCAN_TXEFC_EFWM_Pos 24 +#define MCAN_TXEFC_EFWM_Msk (0x3fu << MCAN_TXEFC_EFWM_Pos) /**< \brief (MCAN_TXEFC) Event FIFO Watermark */ +#define MCAN_TXEFC_EFWM(value) ((MCAN_TXEFC_EFWM_Msk & ((value) << MCAN_TXEFC_EFWM_Pos))) +/* -------- MCAN_TXEFS : (MCAN Offset: 0xF4) Transmit Event FIFO Status Register -------- */ +#define MCAN_TXEFS_EFFL_Pos 0 +#define MCAN_TXEFS_EFFL_Msk (0x3fu << MCAN_TXEFS_EFFL_Pos) /**< \brief (MCAN_TXEFS) Event FIFO Fill Level */ +#define MCAN_TXEFS_EFGI_Pos 8 +#define MCAN_TXEFS_EFGI_Msk (0x1fu << MCAN_TXEFS_EFGI_Pos) /**< \brief (MCAN_TXEFS) Event FIFO Get Index */ +#define MCAN_TXEFS_EFPI_Pos 16 +#define MCAN_TXEFS_EFPI_Msk (0x1fu << MCAN_TXEFS_EFPI_Pos) /**< \brief (MCAN_TXEFS) Event FIFO Put Index */ +#define MCAN_TXEFS_EFF (0x1u << 24) /**< \brief (MCAN_TXEFS) Event FIFO Full */ +#define MCAN_TXEFS_TEFL (0x1u << 25) /**< \brief (MCAN_TXEFS) Tx Event FIFO Element Lost */ +/* -------- MCAN_TXEFA : (MCAN Offset: 0xF8) Transmit Event FIFO Acknowledge Register -------- */ +#define MCAN_TXEFA_EFAI_Pos 0 +#define MCAN_TXEFA_EFAI_Msk (0x1fu << MCAN_TXEFA_EFAI_Pos) /**< \brief (MCAN_TXEFA) Event FIFO Acknowledge Index */ +#define MCAN_TXEFA_EFAI(value) ((MCAN_TXEFA_EFAI_Msk & ((value) << MCAN_TXEFA_EFAI_Pos))) + +/*@}*/ + + +#endif /* _SAMV71_MCAN_COMPONENT_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_mlb.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_mlb.h new file mode 100644 index 00000000..2c7b92dd --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_mlb.h @@ -0,0 +1,192 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_MLB_COMPONENT_ +#define _SAMV71_MLB_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Media LB */ +/* ============================================================================= */ +/** \addtogroup SAMV71_MLB Media LB */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Mlb hardware registers */ +typedef struct { + __IO uint32_t MLB_MLBC0; /**< \brief (Mlb Offset: 0x000) MediaLB Control 0 Register */ + __I uint32_t Reserved1[2]; + __IO uint32_t MLB_MS0; /**< \brief (Mlb Offset: 0x00C) MediaLB Channel Status 0 Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t MLB_MS1; /**< \brief (Mlb Offset: 0x014) MediaLB Channel Status1 Register */ + __I uint32_t Reserved3[2]; + __IO uint32_t MLB_MSS; /**< \brief (Mlb Offset: 0x020) MediaLB System Status Register */ + __I uint32_t MLB_MSD; /**< \brief (Mlb Offset: 0x024) MediaLB System Data Register */ + __I uint32_t Reserved4[1]; + __IO uint32_t MLB_MIEN; /**< \brief (Mlb Offset: 0x02C) MediaLB Interrupt Enable Register */ + __I uint32_t Reserved5[3]; + __IO uint32_t MLB_MLBC1; /**< \brief (Mlb Offset: 0x03C) MediaLB Control 1 Register */ + __I uint32_t Reserved6[1]; + __I uint32_t Reserved7[15]; + __IO uint32_t MLB_HCTL; /**< \brief (Mlb Offset: 0x080) HBI Control Register */ + __I uint32_t Reserved8[1]; + __IO uint32_t MLB_HCMR[2]; /**< \brief (Mlb Offset: 0x088) HBI Channel Mask 0 Register */ + __I uint32_t MLB_HCER[2]; /**< \brief (Mlb Offset: 0x090) HBI Channel Error 0 Register */ + __I uint32_t MLB_HCBR[2]; /**< \brief (Mlb Offset: 0x098) HBI Channel Busy 0 Register */ + __I uint32_t Reserved9[8]; + __IO uint32_t MLB_MDAT[4]; /**< \brief (Mlb Offset: 0x0C0) MIF Data 0 Register */ + __IO uint32_t MLB_MDWE[4]; /**< \brief (Mlb Offset: 0x0D0) MIF Data Write Enable 0 Register */ + __IO uint32_t MLB_MCTL; /**< \brief (Mlb Offset: 0x0E0) MIF Control Register */ + __IO uint32_t MLB_MADR; /**< \brief (Mlb Offset: 0x0E4) MIF Address Register */ + __I uint32_t Reserved10[182]; + __IO uint32_t MLB_ACTL; /**< \brief (Mlb Offset: 0x3C0) AHB Control Register */ + __I uint32_t Reserved11[3]; + __IO uint32_t MLB_ACSR[2]; /**< \brief (Mlb Offset: 0x3D0) AHB Channel Status 0 Register */ + __IO uint32_t MLB_ACMR[2]; /**< \brief (Mlb Offset: 0x3D8) AHB Channel Mask 0 Register */ +} Mlb; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- MLB_MLBC0 : (MLB Offset: 0x000) MediaLB Control 0 Register -------- */ +#define MLB_MLBC0_MLBEN (0x1u << 0) /**< \brief (MLB_MLBC0) MediaLB Enable */ +#define MLB_MLBC0_MLBCLK_Pos 2 +#define MLB_MLBC0_MLBCLK_Msk (0x7u << MLB_MLBC0_MLBCLK_Pos) /**< \brief (MLB_MLBC0) MLB_CLK (MediaLB clock) speed select */ +#define MLB_MLBC0_MLBCLK(value) ((MLB_MLBC0_MLBCLK_Msk & ((value) << MLB_MLBC0_MLBCLK_Pos))) +#define MLB_MLBC0_MLBCLK_256_FS (0x0u << 2) /**< \brief (MLB_MLBC0) 256xFs (for MLBPEN = 0) */ +#define MLB_MLBC0_MLBCLK_512_FS (0x1u << 2) /**< \brief (MLB_MLBC0) 512xFs (for MLBPEN = 0) */ +#define MLB_MLBC0_MLBCLK_1024_FS (0x2u << 2) /**< \brief (MLB_MLBC0) 1024xFs (for MLBPEN = 0) */ +#define MLB_MLBC0_ZERO (0x1u << 5) /**< \brief (MLB_MLBC0) Must be Written to 0 */ +#define MLB_MLBC0_MLBLK (0x1u << 7) /**< \brief (MLB_MLBC0) MediaLB Lock Status (read-only) */ +#define MLB_MLBC0_ASYRETRY (0x1u << 12) /**< \brief (MLB_MLBC0) Asynchronous Tx Packet Retry */ +#define MLB_MLBC0_CTLRETRY (0x1u << 14) /**< \brief (MLB_MLBC0) Control Tx Packet Retry */ +#define MLB_MLBC0_FCNT_Pos 15 +#define MLB_MLBC0_FCNT_Msk (0x7u << MLB_MLBC0_FCNT_Pos) /**< \brief (MLB_MLBC0) The number of frames per sub-buffer for synchronous channels */ +#define MLB_MLBC0_FCNT(value) ((MLB_MLBC0_FCNT_Msk & ((value) << MLB_MLBC0_FCNT_Pos))) +#define MLB_MLBC0_FCNT_1_FRAME (0x0u << 15) /**< \brief (MLB_MLBC0) 1 frame per sub-buffer (Operation is the same as Standard mode.) */ +#define MLB_MLBC0_FCNT_2_FRAMES (0x1u << 15) /**< \brief (MLB_MLBC0) 2 frames per sub-buffer */ +#define MLB_MLBC0_FCNT_4_FRAMES (0x2u << 15) /**< \brief (MLB_MLBC0) 4 frames per sub-buffer */ +#define MLB_MLBC0_FCNT_8_FRAMES (0x3u << 15) /**< \brief (MLB_MLBC0) 8 frames per sub-buffer */ +#define MLB_MLBC0_FCNT_16_FRAMES (0x4u << 15) /**< \brief (MLB_MLBC0) 16 frames per sub-buffer */ +#define MLB_MLBC0_FCNT_32_FRAMES (0x5u << 15) /**< \brief (MLB_MLBC0) 32 frames per sub-buffer */ +#define MLB_MLBC0_FCNT_64_FRAMES (0x6u << 15) /**< \brief (MLB_MLBC0) 64 frames per sub-buffer */ +/* -------- MLB_MS0 : (MLB Offset: 0x00C) MediaLB Channel Status 0 Register -------- */ +#define MLB_MS0_MCS_Pos 0 +#define MLB_MS0_MCS_Msk (0xffffffffu << MLB_MS0_MCS_Pos) /**< \brief (MLB_MS0) MediaLB Channel Status [31:0] (cleared by writing a 0) */ +#define MLB_MS0_MCS(value) ((MLB_MS0_MCS_Msk & ((value) << MLB_MS0_MCS_Pos))) +/* -------- MLB_MS1 : (MLB Offset: 0x014) MediaLB Channel Status1 Register -------- */ +#define MLB_MS1_MCS_Pos 0 +#define MLB_MS1_MCS_Msk (0xffffffffu << MLB_MS1_MCS_Pos) /**< \brief (MLB_MS1) MediaLB Channel Status [63:32] (cleared by writing a 0) */ +#define MLB_MS1_MCS(value) ((MLB_MS1_MCS_Msk & ((value) << MLB_MS1_MCS_Pos))) +/* -------- MLB_MSS : (MLB Offset: 0x020) MediaLB System Status Register -------- */ +#define MLB_MSS_RSTSYSCMD (0x1u << 0) /**< \brief (MLB_MSS) Reset System Command Detected in the System Quadlet (cleared by writing a 0) */ +#define MLB_MSS_LKSYSCMD (0x1u << 1) /**< \brief (MLB_MSS) Network Lock System Command Detected in the System Quadlet (cleared by writing a 0) */ +#define MLB_MSS_ULKSYSCMD (0x1u << 2) /**< \brief (MLB_MSS) Network Unlock System Command Detected in the System Quadlet (cleared by writing a 0) */ +#define MLB_MSS_CSSYSCMD (0x1u << 3) /**< \brief (MLB_MSS) Channel Scan System Command Detected in the System Quadlet (cleared by writing a 0) */ +#define MLB_MSS_SWSYSCMD (0x1u << 4) /**< \brief (MLB_MSS) Software System Command Detected in the System Quadlet (cleared by writing a 0) */ +#define MLB_MSS_SERVREQ (0x1u << 5) /**< \brief (MLB_MSS) Service Request Enabled */ +/* -------- MLB_MSD : (MLB Offset: 0x024) MediaLB System Data Register -------- */ +#define MLB_MSD_SD0_Pos 0 +#define MLB_MSD_SD0_Msk (0xffu << MLB_MSD_SD0_Pos) /**< \brief (MLB_MSD) System Data (Byte 0) */ +#define MLB_MSD_SD1_Pos 8 +#define MLB_MSD_SD1_Msk (0xffu << MLB_MSD_SD1_Pos) /**< \brief (MLB_MSD) System Data (Byte 1) */ +#define MLB_MSD_SD2_Pos 16 +#define MLB_MSD_SD2_Msk (0xffu << MLB_MSD_SD2_Pos) /**< \brief (MLB_MSD) System Data (Byte 2) */ +#define MLB_MSD_SD3_Pos 24 +#define MLB_MSD_SD3_Msk (0xffu << MLB_MSD_SD3_Pos) /**< \brief (MLB_MSD) System Data (Byte 3) */ +/* -------- MLB_MIEN : (MLB Offset: 0x02C) MediaLB Interrupt Enable Register -------- */ +#define MLB_MIEN_ISOC_PE (0x1u << 0) /**< \brief (MLB_MIEN) Isochronous Rx Protocol Error Enable */ +#define MLB_MIEN_ISOC_BUFO (0x1u << 1) /**< \brief (MLB_MIEN) Isochronous Rx Buffer Overflow Enable */ +#define MLB_MIEN_SYNC_PE (0x1u << 16) /**< \brief (MLB_MIEN) Synchronous Protocol Error Enable */ +#define MLB_MIEN_ARX_DONE (0x1u << 17) /**< \brief (MLB_MIEN) Asynchronous Rx Done Enable */ +#define MLB_MIEN_ARX_PE (0x1u << 18) /**< \brief (MLB_MIEN) Asynchronous Rx Protocol Error Enable */ +#define MLB_MIEN_ARX_BREAK (0x1u << 19) /**< \brief (MLB_MIEN) Asynchronous Rx Break Enable */ +#define MLB_MIEN_ATX_DONE (0x1u << 20) /**< \brief (MLB_MIEN) Asynchronous Tx Packet Done Enable */ +#define MLB_MIEN_ATX_PE (0x1u << 21) /**< \brief (MLB_MIEN) Asynchronous Tx Protocol Error Enable */ +#define MLB_MIEN_ATX_BREAK (0x1u << 22) /**< \brief (MLB_MIEN) Asynchronous Tx Break Enable */ +#define MLB_MIEN_CRX_DONE (0x1u << 24) /**< \brief (MLB_MIEN) Control Rx Packet Done Enable */ +#define MLB_MIEN_CRX_PE (0x1u << 25) /**< \brief (MLB_MIEN) Control Rx Protocol Error Enable */ +#define MLB_MIEN_CRX_BREAK (0x1u << 26) /**< \brief (MLB_MIEN) Control Rx Break Enable */ +#define MLB_MIEN_CTX_DONE (0x1u << 27) /**< \brief (MLB_MIEN) Control Tx Packet Done Enable */ +#define MLB_MIEN_CTX_PE (0x1u << 28) /**< \brief (MLB_MIEN) Control Tx Protocol Error Enable */ +#define MLB_MIEN_CTX_BREAK (0x1u << 29) /**< \brief (MLB_MIEN) Control Tx Break Enable */ +/* -------- MLB_MLBC1 : (MLB Offset: 0x03C) MediaLB Control 1 Register -------- */ +#define MLB_MLBC1_LOCK (0x1u << 6) /**< \brief (MLB_MLBC1) MediaLB Lock Error Status (cleared by writing a 0) */ +#define MLB_MLBC1_CLKM (0x1u << 7) /**< \brief (MLB_MLBC1) MediaLB Clock Missing Status (cleared by writing a 0) */ +#define MLB_MLBC1_NDA_Pos 8 +#define MLB_MLBC1_NDA_Msk (0xffu << MLB_MLBC1_NDA_Pos) /**< \brief (MLB_MLBC1) Node Device Address */ +#define MLB_MLBC1_NDA(value) ((MLB_MLBC1_NDA_Msk & ((value) << MLB_MLBC1_NDA_Pos))) +/* -------- MLB_HCTL : (MLB Offset: 0x080) HBI Control Register -------- */ +#define MLB_HCTL_RST0 (0x1u << 0) /**< \brief (MLB_HCTL) Address Generation Unit 0 Software Reset */ +#define MLB_HCTL_RST1 (0x1u << 1) /**< \brief (MLB_HCTL) Address Generation Unit 1 Software Reset */ +#define MLB_HCTL_EN (0x1u << 15) /**< \brief (MLB_HCTL) HBI Enable */ +/* -------- MLB_HCMR[2] : (MLB Offset: 0x088) HBI Channel Mask 0 Register -------- */ +#define MLB_HCMR_CHM_Pos 0 +#define MLB_HCMR_CHM_Msk (0xffffffffu << MLB_HCMR_CHM_Pos) /**< \brief (MLB_HCMR[2]) Bitwise Channel Mask Bit [31:0] */ +#define MLB_HCMR_CHM(value) ((MLB_HCMR_CHM_Msk & ((value) << MLB_HCMR_CHM_Pos))) +/* -------- MLB_HCER[2] : (MLB Offset: 0x090) HBI Channel Error 0 Register -------- */ +#define MLB_HCER_CERR_Pos 0 +#define MLB_HCER_CERR_Msk (0xffffffffu << MLB_HCER_CERR_Pos) /**< \brief (MLB_HCER[2]) Bitwise Channel Error Bit [31:0] */ +/* -------- MLB_HCBR[2] : (MLB Offset: 0x098) HBI Channel Busy 0 Register -------- */ +#define MLB_HCBR_CHB_Pos 0 +#define MLB_HCBR_CHB_Msk (0xffffffffu << MLB_HCBR_CHB_Pos) /**< \brief (MLB_HCBR[2]) Bitwise Channel Busy Bit [31:0] */ +/* -------- MLB_MDAT[4] : (MLB Offset: 0x0C0) MIF Data 0 Register -------- */ +#define MLB_MDAT_DATA_Pos 0 +#define MLB_MDAT_DATA_Msk (0xffffffffu << MLB_MDAT_DATA_Pos) /**< \brief (MLB_MDAT[4]) CRT or DBR Data */ +#define MLB_MDAT_DATA(value) ((MLB_MDAT_DATA_Msk & ((value) << MLB_MDAT_DATA_Pos))) +/* -------- MLB_MDWE[4] : (MLB Offset: 0x0D0) MIF Data Write Enable 0 Register -------- */ +#define MLB_MDWE_MASK_Pos 0 +#define MLB_MDWE_MASK_Msk (0xffffffffu << MLB_MDWE_MASK_Pos) /**< \brief (MLB_MDWE[4]) Bitwise write enable for CTR data - bits[31:0] */ +#define MLB_MDWE_MASK(value) ((MLB_MDWE_MASK_Msk & ((value) << MLB_MDWE_MASK_Pos))) +/* -------- MLB_MCTL : (MLB Offset: 0x0E0) MIF Control Register -------- */ +#define MLB_MCTL_XCMP (0x1u << 0) /**< \brief (MLB_MCTL) Transfer Complete (Write 0 to Clear) */ +/* -------- MLB_MADR : (MLB Offset: 0x0E4) MIF Address Register -------- */ +#define MLB_MADR_ADDR_Pos 0 +#define MLB_MADR_ADDR_Msk (0x3fffu << MLB_MADR_ADDR_Pos) /**< \brief (MLB_MADR) CTR or DBR Address */ +#define MLB_MADR_ADDR(value) ((MLB_MADR_ADDR_Msk & ((value) << MLB_MADR_ADDR_Pos))) +#define MLB_MADR_TB (0x1u << 30) /**< \brief (MLB_MADR) Target Location Bit */ +#define MLB_MADR_TB_CTR (0x0u << 30) /**< \brief (MLB_MADR) Selects CTR */ +#define MLB_MADR_TB_DBR (0x1u << 30) /**< \brief (MLB_MADR) Selects DBR */ +#define MLB_MADR_WNR (0x1u << 31) /**< \brief (MLB_MADR) Write-Not-Read Selection */ +/* -------- MLB_ACTL : (MLB Offset: 0x3C0) AHB Control Register -------- */ +#define MLB_ACTL_SCE (0x1u << 0) /**< \brief (MLB_ACTL) Software Clear Enable */ +#define MLB_ACTL_SMX (0x1u << 1) /**< \brief (MLB_ACTL) AHB Interrupt Mux Enable */ +#define MLB_ACTL_DMA_MODE (0x1u << 2) /**< \brief (MLB_ACTL) DMA Mode */ +#define MLB_ACTL_MPB (0x1u << 4) /**< \brief (MLB_ACTL) DMA Packet Buffering Mode */ +#define MLB_ACTL_MPB_SINGLE_PACKET (0x0u << 4) /**< \brief (MLB_ACTL) Single-packet mode */ +#define MLB_ACTL_MPB_MULTIPLE_PACKET (0x1u << 4) /**< \brief (MLB_ACTL) Multiple-packet mode */ +/* -------- MLB_ACSR[2] : (MLB Offset: 0x3D0) AHB Channel Status 0 Register -------- */ +#define MLB_ACSR_CHS_Pos 0 +#define MLB_ACSR_CHS_Msk (0xffffffffu << MLB_ACSR_CHS_Pos) /**< \brief (MLB_ACSR[2]) Interrupt Status for Logical Channels [31:0] (cleared by writing a 1) */ +#define MLB_ACSR_CHS(value) ((MLB_ACSR_CHS_Msk & ((value) << MLB_ACSR_CHS_Pos))) +/* -------- MLB_ACMR[2] : (MLB Offset: 0x3D8) AHB Channel Mask 0 Register -------- */ +#define MLB_ACMR_CHM_Pos 0 +#define MLB_ACMR_CHM_Msk (0xffffffffu << MLB_ACMR_CHM_Pos) /**< \brief (MLB_ACMR[2]) Bitwise Channel Mask Bits 31 to 0 */ +#define MLB_ACMR_CHM(value) ((MLB_ACMR_CHM_Msk & ((value) << MLB_ACMR_CHM_Pos))) + +/*@}*/ + + +#endif /* _SAMV71_MLB_COMPONENT_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_pio.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_pio.h new file mode 100644 index 00000000..0fa6802f --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_pio.h @@ -0,0 +1,1785 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_PIO_COMPONENT_ +#define _SAMV71_PIO_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_PIO Parallel Input/Output Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Pio hardware registers */ +typedef struct { + __O uint32_t PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */ + __O uint32_t PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */ + __I uint32_t PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */ + __I uint32_t Reserved1[1]; + __O uint32_t PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */ + __O uint32_t PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */ + __I uint32_t PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */ + __I uint32_t Reserved2[1]; + __O uint32_t PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */ + __O uint32_t PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */ + __I uint32_t PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */ + __I uint32_t Reserved3[1]; + __O uint32_t PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */ + __O uint32_t PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */ + __IO uint32_t PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */ + __I uint32_t PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */ + __O uint32_t PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */ + __O uint32_t PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */ + __I uint32_t PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */ + __I uint32_t PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */ + __O uint32_t PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */ + __O uint32_t PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */ + __I uint32_t PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */ + __I uint32_t Reserved4[1]; + __O uint32_t PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */ + __O uint32_t PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */ + __I uint32_t PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */ + __I uint32_t Reserved5[1]; + __IO uint32_t PIO_ABCDSR[2]; /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */ + __I uint32_t Reserved6[2]; + __O uint32_t PIO_IFSCDR; /**< \brief (Pio Offset: 0x0080) Input Filter Slow Clock Disable Register */ + __O uint32_t PIO_IFSCER; /**< \brief (Pio Offset: 0x0084) Input Filter Slow Clock Enable Register */ + __I uint32_t PIO_IFSCSR; /**< \brief (Pio Offset: 0x0088) Input Filter Slow Clock Status Register */ + __IO uint32_t PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */ + __O uint32_t PIO_PPDDR; /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */ + __O uint32_t PIO_PPDER; /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */ + __I uint32_t PIO_PPDSR; /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */ + __I uint32_t Reserved7[1]; + __O uint32_t PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */ + __O uint32_t PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */ + __I uint32_t PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */ + __I uint32_t Reserved8[1]; + __O uint32_t PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */ + __O uint32_t PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disable Register */ + __I uint32_t PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */ + __I uint32_t Reserved9[1]; + __O uint32_t PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */ + __O uint32_t PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */ + __I uint32_t PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */ + __I uint32_t Reserved10[1]; + __O uint32_t PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low-Level Select Register */ + __O uint32_t PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/High-Level Select Register */ + __I uint32_t PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */ + __I uint32_t Reserved11[1]; + __I uint32_t PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */ + __IO uint32_t PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protection Mode Register */ + __I uint32_t PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protection Status Register */ + __I uint32_t Reserved12[5]; + __IO uint32_t PIO_SCHMITT; /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */ + __I uint32_t Reserved13[5]; + __IO uint32_t PIO_DRIVER; /**< \brief (Pio Offset: 0x0118) I/O Drive Register */ + __I uint32_t Reserved14[1]; + __IO uint32_t PIO_KER; /**< \brief (Pio Offset: 0x0120) Keypad Controller Enable Register */ + __IO uint32_t PIO_KRCR; /**< \brief (Pio Offset: 0x0124) Keypad Controller Row Column Register */ + __IO uint32_t PIO_KDR; /**< \brief (Pio Offset: 0x0128) Keypad Controller Debouncing Register */ + __I uint32_t Reserved15[1]; + __O uint32_t PIO_KIER; /**< \brief (Pio Offset: 0x0130) Keypad Controller Interrupt Enable Register */ + __O uint32_t PIO_KIDR; /**< \brief (Pio Offset: 0x0134) Keypad Controller Interrupt Disable Register */ + __I uint32_t PIO_KIMR; /**< \brief (Pio Offset: 0x0138) Keypad Controller Interrupt Mask Register */ + __I uint32_t PIO_KSR; /**< \brief (Pio Offset: 0x013C) Keypad Controller Status Register */ + __I uint32_t PIO_KKPR; /**< \brief (Pio Offset: 0x0140) Keypad Controller Key Press Register */ + __I uint32_t PIO_KKRR; /**< \brief (Pio Offset: 0x0144) Keypad Controller Key Release Register */ + __I uint32_t Reserved16[2]; + __IO uint32_t PIO_PCMR; /**< \brief (Pio Offset: 0x0150) Parallel Capture Mode Register */ + __O uint32_t PIO_PCIER; /**< \brief (Pio Offset: 0x0154) Parallel Capture Interrupt Enable Register */ + __O uint32_t PIO_PCIDR; /**< \brief (Pio Offset: 0x0158) Parallel Capture Interrupt Disable Register */ + __I uint32_t PIO_PCIMR; /**< \brief (Pio Offset: 0x015C) Parallel Capture Interrupt Mask Register */ + __I uint32_t PIO_PCISR; /**< \brief (Pio Offset: 0x0160) Parallel Capture Interrupt Status Register */ + __I uint32_t PIO_PCRHR; /**< \brief (Pio Offset: 0x0164) Parallel Capture Reception Holding Register */ +} Pio; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */ +#define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */ +/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */ +#define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */ +/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */ +#define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */ +/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */ +#define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */ +/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */ +#define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */ +/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */ +#define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */ +/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */ +#define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */ +/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */ +#define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */ +/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */ +#define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filter Status */ +/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */ +#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */ +/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */ +#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */ +/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */ +#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */ +/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */ +#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */ +/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */ +#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */ +#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */ +#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */ +#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */ +#define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi-drive Enable */ +/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */ +#define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi-drive Disable */ +/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */ +#define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi-drive Status */ +/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */ +#define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull-Up Disable */ +/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */ +#define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull-Up Enable */ +/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */ +#define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull-Up Status */ +/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */ +#define PIO_ABCDSR_P0 (0x1u << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P1 (0x1u << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P2 (0x1u << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P3 (0x1u << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P4 (0x1u << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P5 (0x1u << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P6 (0x1u << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P7 (0x1u << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P8 (0x1u << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P9 (0x1u << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P10 (0x1u << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P11 (0x1u << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P12 (0x1u << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P13 (0x1u << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P14 (0x1u << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P15 (0x1u << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P16 (0x1u << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P17 (0x1u << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P18 (0x1u << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P19 (0x1u << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P20 (0x1u << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P21 (0x1u << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P22 (0x1u << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P23 (0x1u << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P24 (0x1u << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P25 (0x1u << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P26 (0x1u << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P27 (0x1u << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P28 (0x1u << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P29 (0x1u << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P30 (0x1u << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P31 (0x1u << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +/* -------- PIO_IFSCDR : (PIO Offset: 0x0080) Input Filter Slow Clock Disable Register -------- */ +#define PIO_IFSCDR_P0 (0x1u << 0) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P1 (0x1u << 1) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P2 (0x1u << 2) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P3 (0x1u << 3) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P4 (0x1u << 4) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P5 (0x1u << 5) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P6 (0x1u << 6) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P7 (0x1u << 7) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P8 (0x1u << 8) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P9 (0x1u << 9) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P10 (0x1u << 10) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P11 (0x1u << 11) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P12 (0x1u << 12) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P13 (0x1u << 13) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P14 (0x1u << 14) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P15 (0x1u << 15) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P16 (0x1u << 16) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P17 (0x1u << 17) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P18 (0x1u << 18) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P19 (0x1u << 19) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P20 (0x1u << 20) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P21 (0x1u << 21) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P22 (0x1u << 22) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P23 (0x1u << 23) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P24 (0x1u << 24) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P25 (0x1u << 25) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P26 (0x1u << 26) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P27 (0x1u << 27) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P28 (0x1u << 28) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P29 (0x1u << 29) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P30 (0x1u << 30) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P31 (0x1u << 31) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +/* -------- PIO_IFSCER : (PIO Offset: 0x0084) Input Filter Slow Clock Enable Register -------- */ +#define PIO_IFSCER_P0 (0x1u << 0) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P1 (0x1u << 1) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P2 (0x1u << 2) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P3 (0x1u << 3) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P4 (0x1u << 4) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P5 (0x1u << 5) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P6 (0x1u << 6) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P7 (0x1u << 7) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P8 (0x1u << 8) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P9 (0x1u << 9) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P10 (0x1u << 10) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P11 (0x1u << 11) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P12 (0x1u << 12) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P13 (0x1u << 13) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P14 (0x1u << 14) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P15 (0x1u << 15) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P16 (0x1u << 16) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P17 (0x1u << 17) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P18 (0x1u << 18) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P19 (0x1u << 19) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P20 (0x1u << 20) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P21 (0x1u << 21) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P22 (0x1u << 22) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P23 (0x1u << 23) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P24 (0x1u << 24) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P25 (0x1u << 25) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P26 (0x1u << 26) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P27 (0x1u << 27) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P28 (0x1u << 28) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P29 (0x1u << 29) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P30 (0x1u << 30) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P31 (0x1u << 31) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +/* -------- PIO_IFSCSR : (PIO Offset: 0x0088) Input Filter Slow Clock Status Register -------- */ +#define PIO_IFSCSR_P0 (0x1u << 0) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P1 (0x1u << 1) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P2 (0x1u << 2) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P3 (0x1u << 3) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P4 (0x1u << 4) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P5 (0x1u << 5) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P6 (0x1u << 6) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P7 (0x1u << 7) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P8 (0x1u << 8) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P9 (0x1u << 9) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P10 (0x1u << 10) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P11 (0x1u << 11) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P12 (0x1u << 12) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P13 (0x1u << 13) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P14 (0x1u << 14) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P15 (0x1u << 15) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P16 (0x1u << 16) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P17 (0x1u << 17) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P18 (0x1u << 18) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P19 (0x1u << 19) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P20 (0x1u << 20) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P21 (0x1u << 21) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P22 (0x1u << 22) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P23 (0x1u << 23) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P24 (0x1u << 24) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P25 (0x1u << 25) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P26 (0x1u << 26) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P27 (0x1u << 27) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P28 (0x1u << 28) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P29 (0x1u << 29) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P30 (0x1u << 30) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P31 (0x1u << 31) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */ +#define PIO_SCDR_DIV_Pos 0 +#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos))) +/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */ +#define PIO_PPDDR_P0 (0x1u << 0) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P1 (0x1u << 1) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P2 (0x1u << 2) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P3 (0x1u << 3) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P4 (0x1u << 4) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P5 (0x1u << 5) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P6 (0x1u << 6) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P7 (0x1u << 7) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P8 (0x1u << 8) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P9 (0x1u << 9) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P10 (0x1u << 10) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P11 (0x1u << 11) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P12 (0x1u << 12) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P13 (0x1u << 13) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P14 (0x1u << 14) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P15 (0x1u << 15) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P16 (0x1u << 16) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P17 (0x1u << 17) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P18 (0x1u << 18) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P19 (0x1u << 19) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P20 (0x1u << 20) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P21 (0x1u << 21) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P22 (0x1u << 22) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P23 (0x1u << 23) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P24 (0x1u << 24) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P25 (0x1u << 25) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P26 (0x1u << 26) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P27 (0x1u << 27) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P28 (0x1u << 28) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P29 (0x1u << 29) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P30 (0x1u << 30) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P31 (0x1u << 31) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */ +#define PIO_PPDER_P0 (0x1u << 0) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P1 (0x1u << 1) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P2 (0x1u << 2) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P3 (0x1u << 3) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P4 (0x1u << 4) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P5 (0x1u << 5) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P6 (0x1u << 6) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P7 (0x1u << 7) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P8 (0x1u << 8) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P9 (0x1u << 9) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P10 (0x1u << 10) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P11 (0x1u << 11) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P12 (0x1u << 12) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P13 (0x1u << 13) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P14 (0x1u << 14) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P15 (0x1u << 15) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P16 (0x1u << 16) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P17 (0x1u << 17) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P18 (0x1u << 18) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P19 (0x1u << 19) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P20 (0x1u << 20) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P21 (0x1u << 21) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P22 (0x1u << 22) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P23 (0x1u << 23) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P24 (0x1u << 24) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P25 (0x1u << 25) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P26 (0x1u << 26) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P27 (0x1u << 27) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P28 (0x1u << 28) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P29 (0x1u << 29) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P30 (0x1u << 30) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P31 (0x1u << 31) /**< \brief (PIO_PPDER) Pull-Down Enable */ +/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */ +#define PIO_PPDSR_P0 (0x1u << 0) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P1 (0x1u << 1) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P2 (0x1u << 2) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P3 (0x1u << 3) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P4 (0x1u << 4) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P5 (0x1u << 5) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P6 (0x1u << 6) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P7 (0x1u << 7) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P8 (0x1u << 8) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P9 (0x1u << 9) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P10 (0x1u << 10) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P11 (0x1u << 11) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P12 (0x1u << 12) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P13 (0x1u << 13) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P14 (0x1u << 14) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P15 (0x1u << 15) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P16 (0x1u << 16) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P17 (0x1u << 17) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P18 (0x1u << 18) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P19 (0x1u << 19) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P20 (0x1u << 20) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P21 (0x1u << 21) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P22 (0x1u << 22) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P23 (0x1u << 23) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P24 (0x1u << 24) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P25 (0x1u << 25) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P26 (0x1u << 26) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P27 (0x1u << 27) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P28 (0x1u << 28) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P29 (0x1u << 29) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P30 (0x1u << 30) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P31 (0x1u << 31) /**< \brief (PIO_PPDSR) Pull-Down Status */ +/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */ +#define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable */ +/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */ +#define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable */ +/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */ +#define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status */ +/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */ +#define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disable Register -------- */ +#define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */ +#define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) IO Line Index */ +/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */ +#define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */ +#define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection */ +/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */ +#define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low-Level Select Register -------- */ +#define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/High-Level Select Register -------- */ +#define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */ +#define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */ +#define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status */ +/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protection Mode Register -------- */ +#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protection Enable */ +#define PIO_WPMR_WPKEY_Pos 8 +#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protection Key */ +#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos))) +#define PIO_WPMR_WPKEY_PASSWD (0x50494Fu << 8) /**< \brief (PIO_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protection Status Register -------- */ +#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protection Violation Status */ +#define PIO_WPSR_WPVSRC_Pos 8 +#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protection Violation Source */ +/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */ +#define PIO_SCHMITT_SCHMITT0 (0x1u << 0) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT1 (0x1u << 1) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT2 (0x1u << 2) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT3 (0x1u << 3) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT4 (0x1u << 4) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT5 (0x1u << 5) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT6 (0x1u << 6) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT7 (0x1u << 7) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT8 (0x1u << 8) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT9 (0x1u << 9) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT10 (0x1u << 10) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT11 (0x1u << 11) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT12 (0x1u << 12) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT13 (0x1u << 13) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT14 (0x1u << 14) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT15 (0x1u << 15) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT16 (0x1u << 16) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT17 (0x1u << 17) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT18 (0x1u << 18) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT19 (0x1u << 19) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT20 (0x1u << 20) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT21 (0x1u << 21) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT22 (0x1u << 22) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT23 (0x1u << 23) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT24 (0x1u << 24) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT25 (0x1u << 25) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT26 (0x1u << 26) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT27 (0x1u << 27) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT28 (0x1u << 28) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT29 (0x1u << 29) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT30 (0x1u << 30) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT31 (0x1u << 31) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +/* -------- PIO_DRIVER : (PIO Offset: 0x0118) I/O Drive Register -------- */ +#define PIO_DRIVER_LINE0 (0x1u << 0) /**< \brief (PIO_DRIVER) Drive of PIO Line 0 */ +#define PIO_DRIVER_LINE0_LOW_DRIVE (0x0u << 0) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE0_HIGH_DRIVE (0x1u << 0) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE1 (0x1u << 1) /**< \brief (PIO_DRIVER) Drive of PIO Line 1 */ +#define PIO_DRIVER_LINE1_LOW_DRIVE (0x0u << 1) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE1_HIGH_DRIVE (0x1u << 1) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE2 (0x1u << 2) /**< \brief (PIO_DRIVER) Drive of PIO Line 2 */ +#define PIO_DRIVER_LINE2_LOW_DRIVE (0x0u << 2) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE2_HIGH_DRIVE (0x1u << 2) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE3 (0x1u << 3) /**< \brief (PIO_DRIVER) Drive of PIO Line 3 */ +#define PIO_DRIVER_LINE3_LOW_DRIVE (0x0u << 3) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE3_HIGH_DRIVE (0x1u << 3) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE4 (0x1u << 4) /**< \brief (PIO_DRIVER) Drive of PIO Line 4 */ +#define PIO_DRIVER_LINE4_LOW_DRIVE (0x0u << 4) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE4_HIGH_DRIVE (0x1u << 4) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE5 (0x1u << 5) /**< \brief (PIO_DRIVER) Drive of PIO Line 5 */ +#define PIO_DRIVER_LINE5_LOW_DRIVE (0x0u << 5) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE5_HIGH_DRIVE (0x1u << 5) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE6 (0x1u << 6) /**< \brief (PIO_DRIVER) Drive of PIO Line 6 */ +#define PIO_DRIVER_LINE6_LOW_DRIVE (0x0u << 6) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE6_HIGH_DRIVE (0x1u << 6) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE7 (0x1u << 7) /**< \brief (PIO_DRIVER) Drive of PIO Line 7 */ +#define PIO_DRIVER_LINE7_LOW_DRIVE (0x0u << 7) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE7_HIGH_DRIVE (0x1u << 7) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE8 (0x1u << 8) /**< \brief (PIO_DRIVER) Drive of PIO Line 8 */ +#define PIO_DRIVER_LINE8_LOW_DRIVE (0x0u << 8) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE8_HIGH_DRIVE (0x1u << 8) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE9 (0x1u << 9) /**< \brief (PIO_DRIVER) Drive of PIO Line 9 */ +#define PIO_DRIVER_LINE9_LOW_DRIVE (0x0u << 9) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE9_HIGH_DRIVE (0x1u << 9) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE10 (0x1u << 10) /**< \brief (PIO_DRIVER) Drive of PIO Line 10 */ +#define PIO_DRIVER_LINE10_LOW_DRIVE (0x0u << 10) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE10_HIGH_DRIVE (0x1u << 10) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE11 (0x1u << 11) /**< \brief (PIO_DRIVER) Drive of PIO Line 11 */ +#define PIO_DRIVER_LINE11_LOW_DRIVE (0x0u << 11) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE11_HIGH_DRIVE (0x1u << 11) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE12 (0x1u << 12) /**< \brief (PIO_DRIVER) Drive of PIO Line 12 */ +#define PIO_DRIVER_LINE12_LOW_DRIVE (0x0u << 12) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE12_HIGH_DRIVE (0x1u << 12) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE13 (0x1u << 13) /**< \brief (PIO_DRIVER) Drive of PIO Line 13 */ +#define PIO_DRIVER_LINE13_LOW_DRIVE (0x0u << 13) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE13_HIGH_DRIVE (0x1u << 13) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE14 (0x1u << 14) /**< \brief (PIO_DRIVER) Drive of PIO Line 14 */ +#define PIO_DRIVER_LINE14_LOW_DRIVE (0x0u << 14) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE14_HIGH_DRIVE (0x1u << 14) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE15 (0x1u << 15) /**< \brief (PIO_DRIVER) Drive of PIO Line 15 */ +#define PIO_DRIVER_LINE15_LOW_DRIVE (0x0u << 15) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE15_HIGH_DRIVE (0x1u << 15) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE16 (0x1u << 16) /**< \brief (PIO_DRIVER) Drive of PIO Line 16 */ +#define PIO_DRIVER_LINE16_LOW_DRIVE (0x0u << 16) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE16_HIGH_DRIVE (0x1u << 16) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE17 (0x1u << 17) /**< \brief (PIO_DRIVER) Drive of PIO Line 17 */ +#define PIO_DRIVER_LINE17_LOW_DRIVE (0x0u << 17) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE17_HIGH_DRIVE (0x1u << 17) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE18 (0x1u << 18) /**< \brief (PIO_DRIVER) Drive of PIO Line 18 */ +#define PIO_DRIVER_LINE18_LOW_DRIVE (0x0u << 18) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE18_HIGH_DRIVE (0x1u << 18) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE19 (0x1u << 19) /**< \brief (PIO_DRIVER) Drive of PIO Line 19 */ +#define PIO_DRIVER_LINE19_LOW_DRIVE (0x0u << 19) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE19_HIGH_DRIVE (0x1u << 19) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE20 (0x1u << 20) /**< \brief (PIO_DRIVER) Drive of PIO Line 20 */ +#define PIO_DRIVER_LINE20_LOW_DRIVE (0x0u << 20) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE20_HIGH_DRIVE (0x1u << 20) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE21 (0x1u << 21) /**< \brief (PIO_DRIVER) Drive of PIO Line 21 */ +#define PIO_DRIVER_LINE21_LOW_DRIVE (0x0u << 21) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE21_HIGH_DRIVE (0x1u << 21) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE22 (0x1u << 22) /**< \brief (PIO_DRIVER) Drive of PIO Line 22 */ +#define PIO_DRIVER_LINE22_LOW_DRIVE (0x0u << 22) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE22_HIGH_DRIVE (0x1u << 22) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE23 (0x1u << 23) /**< \brief (PIO_DRIVER) Drive of PIO Line 23 */ +#define PIO_DRIVER_LINE23_LOW_DRIVE (0x0u << 23) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE23_HIGH_DRIVE (0x1u << 23) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE24 (0x1u << 24) /**< \brief (PIO_DRIVER) Drive of PIO Line 24 */ +#define PIO_DRIVER_LINE24_LOW_DRIVE (0x0u << 24) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE24_HIGH_DRIVE (0x1u << 24) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE25 (0x1u << 25) /**< \brief (PIO_DRIVER) Drive of PIO Line 25 */ +#define PIO_DRIVER_LINE25_LOW_DRIVE (0x0u << 25) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE25_HIGH_DRIVE (0x1u << 25) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE26 (0x1u << 26) /**< \brief (PIO_DRIVER) Drive of PIO Line 26 */ +#define PIO_DRIVER_LINE26_LOW_DRIVE (0x0u << 26) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE26_HIGH_DRIVE (0x1u << 26) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE27 (0x1u << 27) /**< \brief (PIO_DRIVER) Drive of PIO Line 27 */ +#define PIO_DRIVER_LINE27_LOW_DRIVE (0x0u << 27) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE27_HIGH_DRIVE (0x1u << 27) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE28 (0x1u << 28) /**< \brief (PIO_DRIVER) Drive of PIO Line 28 */ +#define PIO_DRIVER_LINE28_LOW_DRIVE (0x0u << 28) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE28_HIGH_DRIVE (0x1u << 28) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE29 (0x1u << 29) /**< \brief (PIO_DRIVER) Drive of PIO Line 29 */ +#define PIO_DRIVER_LINE29_LOW_DRIVE (0x0u << 29) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE29_HIGH_DRIVE (0x1u << 29) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE30 (0x1u << 30) /**< \brief (PIO_DRIVER) Drive of PIO Line 30 */ +#define PIO_DRIVER_LINE30_LOW_DRIVE (0x0u << 30) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE30_HIGH_DRIVE (0x1u << 30) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE31 (0x1u << 31) /**< \brief (PIO_DRIVER) Drive of PIO Line 31 */ +#define PIO_DRIVER_LINE31_LOW_DRIVE (0x0u << 31) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE31_HIGH_DRIVE (0x1u << 31) /**< \brief (PIO_DRIVER) Highest drive */ +/* -------- PIO_KER : (PIO Offset: 0x0120) Keypad Controller Enable Register -------- */ +#define PIO_KER_KCE (0x1u << 0) /**< \brief (PIO_KER) Keypad Controller Enable */ +/* -------- PIO_KRCR : (PIO Offset: 0x0124) Keypad Controller Row Column Register -------- */ +#define PIO_KRCR_NBR_Pos 0 +#define PIO_KRCR_NBR_Msk (0x7u << PIO_KRCR_NBR_Pos) /**< \brief (PIO_KRCR) Number of Columns of the Keypad Matrix */ +#define PIO_KRCR_NBR(value) ((PIO_KRCR_NBR_Msk & ((value) << PIO_KRCR_NBR_Pos))) +#define PIO_KRCR_NBC_Pos 8 +#define PIO_KRCR_NBC_Msk (0x7u << PIO_KRCR_NBC_Pos) /**< \brief (PIO_KRCR) Number of Rows of the Keypad Matrix */ +#define PIO_KRCR_NBC(value) ((PIO_KRCR_NBC_Msk & ((value) << PIO_KRCR_NBC_Pos))) +/* -------- PIO_KDR : (PIO Offset: 0x0128) Keypad Controller Debouncing Register -------- */ +#define PIO_KDR_DBC_Pos 0 +#define PIO_KDR_DBC_Msk (0x3ffu << PIO_KDR_DBC_Pos) /**< \brief (PIO_KDR) Debouncing Value */ +#define PIO_KDR_DBC(value) ((PIO_KDR_DBC_Msk & ((value) << PIO_KDR_DBC_Pos))) +/* -------- PIO_KIER : (PIO Offset: 0x0130) Keypad Controller Interrupt Enable Register -------- */ +#define PIO_KIER_KPR (0x1u << 0) /**< \brief (PIO_KIER) Key Press Interrupt Enable */ +#define PIO_KIER_KRL (0x1u << 1) /**< \brief (PIO_KIER) Key Release Interrupt Enable */ +/* -------- PIO_KIDR : (PIO Offset: 0x0134) Keypad Controller Interrupt Disable Register -------- */ +#define PIO_KIDR_KPR (0x1u << 0) /**< \brief (PIO_KIDR) Key Press Interrupt Disable */ +#define PIO_KIDR_KRL (0x1u << 1) /**< \brief (PIO_KIDR) Key Release Interrupt Disable */ +/* -------- PIO_KIMR : (PIO Offset: 0x0138) Keypad Controller Interrupt Mask Register -------- */ +#define PIO_KIMR_KPR (0x1u << 0) /**< \brief (PIO_KIMR) Key Press Interrupt Mask */ +#define PIO_KIMR_KRL (0x1u << 1) /**< \brief (PIO_KIMR) Key Release Interrupt Mask */ +/* -------- PIO_KSR : (PIO Offset: 0x013C) Keypad Controller Status Register -------- */ +#define PIO_KSR_KPR (0x1u << 0) /**< \brief (PIO_KSR) Key Press Status */ +#define PIO_KSR_KRL (0x1u << 1) /**< \brief (PIO_KSR) Key Release Status */ +#define PIO_KSR_NBKPR_Pos 8 +#define PIO_KSR_NBKPR_Msk (0x3u << PIO_KSR_NBKPR_Pos) /**< \brief (PIO_KSR) Number of Simultaneous Key Presses */ +#define PIO_KSR_NBKRL_Pos 16 +#define PIO_KSR_NBKRL_Msk (0x3u << PIO_KSR_NBKRL_Pos) /**< \brief (PIO_KSR) Number of Simultaneous Key Releases */ +/* -------- PIO_KKPR : (PIO Offset: 0x0140) Keypad Controller Key Press Register -------- */ +#define PIO_KKPR_KEY0ROW_Pos 0 +#define PIO_KKPR_KEY0ROW_Msk (0x7u << PIO_KKPR_KEY0ROW_Pos) /**< \brief (PIO_KKPR) Row Index of the First Detected Key Press */ +#define PIO_KKPR_KEY0COL_Pos 4 +#define PIO_KKPR_KEY0COL_Msk (0x7u << PIO_KKPR_KEY0COL_Pos) /**< \brief (PIO_KKPR) Column Index of the First Detected Key Press */ +#define PIO_KKPR_KEY1ROW_Pos 8 +#define PIO_KKPR_KEY1ROW_Msk (0x7u << PIO_KKPR_KEY1ROW_Pos) /**< \brief (PIO_KKPR) Row Index of the Second Detected Key Press */ +#define PIO_KKPR_KEY1COL_Pos 12 +#define PIO_KKPR_KEY1COL_Msk (0x7u << PIO_KKPR_KEY1COL_Pos) /**< \brief (PIO_KKPR) Column Index of the Second Detected Key Press */ +#define PIO_KKPR_KEY2ROW_Pos 16 +#define PIO_KKPR_KEY2ROW_Msk (0x7u << PIO_KKPR_KEY2ROW_Pos) /**< \brief (PIO_KKPR) Row Index of the Third Detected Key Press */ +#define PIO_KKPR_KEY2COL_Pos 20 +#define PIO_KKPR_KEY2COL_Msk (0x7u << PIO_KKPR_KEY2COL_Pos) /**< \brief (PIO_KKPR) Column Index of the Third Detected Key Press */ +#define PIO_KKPR_KEY3ROW_Pos 24 +#define PIO_KKPR_KEY3ROW_Msk (0x7u << PIO_KKPR_KEY3ROW_Pos) /**< \brief (PIO_KKPR) Row Index of the Fourth Detected Key Press */ +#define PIO_KKPR_KEY3COL_Pos 28 +#define PIO_KKPR_KEY3COL_Msk (0x7u << PIO_KKPR_KEY3COL_Pos) /**< \brief (PIO_KKPR) Column Index of the Fourth Detected Key Press */ +/* -------- PIO_KKRR : (PIO Offset: 0x0144) Keypad Controller Key Release Register -------- */ +#define PIO_KKRR_KEY0ROW_Pos 0 +#define PIO_KKRR_KEY0ROW_Msk (0x7u << PIO_KKRR_KEY0ROW_Pos) /**< \brief (PIO_KKRR) Row Index of the First Detected Key Release */ +#define PIO_KKRR_KEY0COL_Pos 4 +#define PIO_KKRR_KEY0COL_Msk (0x7u << PIO_KKRR_KEY0COL_Pos) /**< \brief (PIO_KKRR) Column Index of the First Detected Key Release */ +#define PIO_KKRR_KEY1ROW_Pos 8 +#define PIO_KKRR_KEY1ROW_Msk (0x7u << PIO_KKRR_KEY1ROW_Pos) /**< \brief (PIO_KKRR) Row Index of the Second Detected Key Release */ +#define PIO_KKRR_KEY1COL_Pos 12 +#define PIO_KKRR_KEY1COL_Msk (0x7u << PIO_KKRR_KEY1COL_Pos) /**< \brief (PIO_KKRR) Column Index of the Second Detected Key Release */ +#define PIO_KKRR_KEY2ROW_Pos 16 +#define PIO_KKRR_KEY2ROW_Msk (0x7u << PIO_KKRR_KEY2ROW_Pos) /**< \brief (PIO_KKRR) Row Index of the Third Detected Key Release */ +#define PIO_KKRR_KEY2COL_Pos 20 +#define PIO_KKRR_KEY2COL_Msk (0x7u << PIO_KKRR_KEY2COL_Pos) /**< \brief (PIO_KKRR) Column Index of the Third Detected Key Release */ +#define PIO_KKRR_KEY3ROW_Pos 24 +#define PIO_KKRR_KEY3ROW_Msk (0x7u << PIO_KKRR_KEY3ROW_Pos) /**< \brief (PIO_KKRR) Row Index of the Fourth Detected Key Release */ +#define PIO_KKRR_KEY3COL_Pos 28 +#define PIO_KKRR_KEY3COL_Msk (0x7u << PIO_KKRR_KEY3COL_Pos) /**< \brief (PIO_KKRR) Column Index of the Fourth Detected Key Release */ +/* -------- PIO_PCMR : (PIO Offset: 0x0150) Parallel Capture Mode Register -------- */ +#define PIO_PCMR_PCEN (0x1u << 0) /**< \brief (PIO_PCMR) Parallel Capture Mode Enable */ +#define PIO_PCMR_DSIZE_Pos 4 +#define PIO_PCMR_DSIZE_Msk (0x3u << PIO_PCMR_DSIZE_Pos) /**< \brief (PIO_PCMR) Parallel Capture Mode Data Size */ +#define PIO_PCMR_DSIZE(value) ((PIO_PCMR_DSIZE_Msk & ((value) << PIO_PCMR_DSIZE_Pos))) +#define PIO_PCMR_DSIZE_BYTE (0x0u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a byte (8-bit) */ +#define PIO_PCMR_DSIZE_HALFWORD (0x1u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a half-word (16-bit) */ +#define PIO_PCMR_DSIZE_WORD (0x2u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a word (32-bit) */ +#define PIO_PCMR_ALWYS (0x1u << 9) /**< \brief (PIO_PCMR) Parallel Capture Mode Always Sampling */ +#define PIO_PCMR_HALFS (0x1u << 10) /**< \brief (PIO_PCMR) Parallel Capture Mode Half Sampling */ +#define PIO_PCMR_FRSTS (0x1u << 11) /**< \brief (PIO_PCMR) Parallel Capture Mode First Sample */ +/* -------- PIO_PCIER : (PIO Offset: 0x0154) Parallel Capture Interrupt Enable Register -------- */ +#define PIO_PCIER_DRDY (0x1u << 0) /**< \brief (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable */ +#define PIO_PCIER_OVRE (0x1u << 1) /**< \brief (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable */ +#define PIO_PCIER_ENDRX (0x1u << 2) /**< \brief (PIO_PCIER) End of Reception Transfer Interrupt Enable */ +#define PIO_PCIER_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIER) Reception Buffer Full Interrupt Enable */ +/* -------- PIO_PCIDR : (PIO Offset: 0x0158) Parallel Capture Interrupt Disable Register -------- */ +#define PIO_PCIDR_DRDY (0x1u << 0) /**< \brief (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable */ +#define PIO_PCIDR_OVRE (0x1u << 1) /**< \brief (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable */ +#define PIO_PCIDR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIDR) End of Reception Transfer Interrupt Disable */ +#define PIO_PCIDR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIDR) Reception Buffer Full Interrupt Disable */ +/* -------- PIO_PCIMR : (PIO Offset: 0x015C) Parallel Capture Interrupt Mask Register -------- */ +#define PIO_PCIMR_DRDY (0x1u << 0) /**< \brief (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask */ +#define PIO_PCIMR_OVRE (0x1u << 1) /**< \brief (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask */ +#define PIO_PCIMR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIMR) End of Reception Transfer Interrupt Mask */ +#define PIO_PCIMR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIMR) Reception Buffer Full Interrupt Mask */ +/* -------- PIO_PCISR : (PIO Offset: 0x0160) Parallel Capture Interrupt Status Register -------- */ +#define PIO_PCISR_DRDY (0x1u << 0) /**< \brief (PIO_PCISR) Parallel Capture Mode Data Ready */ +#define PIO_PCISR_OVRE (0x1u << 1) /**< \brief (PIO_PCISR) Parallel Capture Mode Overrun Error */ +/* -------- PIO_PCRHR : (PIO Offset: 0x0164) Parallel Capture Reception Holding Register -------- */ +#define PIO_PCRHR_RDATA_Pos 0 +#define PIO_PCRHR_RDATA_Msk (0xffffffffu << PIO_PCRHR_RDATA_Pos) /**< \brief (PIO_PCRHR) Parallel Capture Mode Reception Data */ + +/*@}*/ + + +#endif /* _SAMV71_PIO_COMPONENT_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_pmc.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_pmc.h new file mode 100644 index 00000000..540791f1 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_pmc.h @@ -0,0 +1,721 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_PMC_COMPONENT_ +#define _SAMV71_PMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Power Management Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_PMC Power Management Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Pmc hardware registers */ +typedef struct { + __O uint32_t PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */ + __O uint32_t PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */ + __I uint32_t PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */ + __I uint32_t Reserved1[1]; + __O uint32_t PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */ + __O uint32_t PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */ + __I uint32_t PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */ + __IO uint32_t CKGR_UCKR; /**< \brief (Pmc Offset: 0x001C) UTMI Clock Register */ + __IO uint32_t CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */ + __IO uint32_t CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */ + __IO uint32_t CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */ + __I uint32_t Reserved3[1]; + __IO uint32_t PMC_USB; /**< \brief (Pmc Offset: 0x0038) USB Clock Register */ + __I uint32_t Reserved4[1]; + __IO uint32_t PMC_PCK[7]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */ + __I uint32_t Reserved5[1]; + __O uint32_t PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */ + __O uint32_t PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */ + __I uint32_t PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */ + __I uint32_t PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */ + __IO uint32_t PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */ + __IO uint32_t PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */ + __O uint32_t PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */ + __I uint32_t Reserved6[26]; + __IO uint32_t PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protection Mode Register */ + __I uint32_t PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protection Status Register */ + __I uint32_t Reserved7[5]; + __O uint32_t PMC_PCER1; /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */ + __O uint32_t PMC_PCDR1; /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */ + __I uint32_t PMC_PCSR1; /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */ + __IO uint32_t PMC_PCR; /**< \brief (Pmc Offset: 0x010C) Peripheral Control Register */ + __IO uint32_t PMC_OCR; /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */ + __O uint32_t PMC_SLPWK_ER0; /**< \brief (Pmc Offset: 0x0114) SleepWalking Enable Register 0 */ + __O uint32_t PMC_SLPWK_DR0; /**< \brief (Pmc Offset: 0x0118) SleepWalking Disable Register 0 */ + __I uint32_t PMC_SLPWK_SR0; /**< \brief (Pmc Offset: 0x011C) SleepWalking Status Register 0 */ + __I uint32_t PMC_SLPWK_ASR0; /**< \brief (Pmc Offset: 0x0120) SleepWalking Activity Status Register 0 */ + __I uint32_t Reserved8[4]; + __O uint32_t PMC_SLPWK_ER1; /**< \brief (Pmc Offset: 0x0134) SleepWalking Enable Register 1 */ + __O uint32_t PMC_SLPWK_DR1; /**< \brief (Pmc Offset: 0x0138) SleepWalking Disable Register 1 */ + __I uint32_t PMC_SLPWK_SR1; /**< \brief (Pmc Offset: 0x013C) SleepWalking Status Register 1 */ + __I uint32_t PMC_SLPWK_ASR1; /**< \brief (Pmc Offset: 0x0140) SleepWalking Activity Status Register 1 */ + __I uint32_t PMC_SLPWK_AIPR; /**< \brief (Pmc Offset: 0x0144) SleepWalking Activity In Progress Register */ +} Pmc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */ +#define PMC_SCER_USBCLK (0x1u << 5) /**< \brief (PMC_SCER) Enable USB FS Clock */ +#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */ +#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */ +#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */ +#define PMC_SCER_PCK3 (0x1u << 11) /**< \brief (PMC_SCER) Programmable Clock 3 Output Enable */ +#define PMC_SCER_PCK4 (0x1u << 12) /**< \brief (PMC_SCER) Programmable Clock 4 Output Enable */ +#define PMC_SCER_PCK5 (0x1u << 13) /**< \brief (PMC_SCER) Programmable Clock 5 Output Enable */ +#define PMC_SCER_PCK6 (0x1u << 14) /**< \brief (PMC_SCER) Programmable Clock 6 Output Enable */ +/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */ +#define PMC_SCDR_USBCLK (0x1u << 5) /**< \brief (PMC_SCDR) Disable USB FS Clock */ +#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */ +#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */ +#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */ +#define PMC_SCDR_PCK3 (0x1u << 11) /**< \brief (PMC_SCDR) Programmable Clock 3 Output Disable */ +#define PMC_SCDR_PCK4 (0x1u << 12) /**< \brief (PMC_SCDR) Programmable Clock 4 Output Disable */ +#define PMC_SCDR_PCK5 (0x1u << 13) /**< \brief (PMC_SCDR) Programmable Clock 5 Output Disable */ +#define PMC_SCDR_PCK6 (0x1u << 14) /**< \brief (PMC_SCDR) Programmable Clock 6 Output Disable */ +/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */ +#define PMC_SCSR_USBCLK (0x1u << 5) /**< \brief (PMC_SCSR) USB FS Clock Status */ +#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */ +#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */ +#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */ +#define PMC_SCSR_PCK3 (0x1u << 11) /**< \brief (PMC_SCSR) Programmable Clock 3 Output Status */ +#define PMC_SCSR_PCK4 (0x1u << 12) /**< \brief (PMC_SCSR) Programmable Clock 4 Output Status */ +#define PMC_SCSR_PCK5 (0x1u << 13) /**< \brief (PMC_SCSR) Programmable Clock 5 Output Status */ +#define PMC_SCSR_PCK6 (0x1u << 14) /**< \brief (PMC_SCSR) Programmable Clock 6 Output Status */ +/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */ +#define PMC_PCER0_PID7 (0x1u << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */ +#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */ +#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */ +#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */ +#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */ +#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */ +#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */ +#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */ +#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */ +#define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */ +#define PMC_PCER0_PID17 (0x1u << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */ +#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */ +#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */ +#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */ +#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */ +#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */ +#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */ +#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */ +#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */ +#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */ +#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */ +#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */ +#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */ +#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */ +#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */ +/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */ +#define PMC_PCDR0_PID7 (0x1u << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */ +#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */ +#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */ +#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */ +#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */ +#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */ +#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */ +#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */ +#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */ +#define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */ +#define PMC_PCDR0_PID17 (0x1u << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */ +#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */ +#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */ +#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */ +#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */ +#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */ +#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */ +#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */ +#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */ +#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */ +#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */ +#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */ +#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */ +#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */ +#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */ +/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */ +#define PMC_PCSR0_PID7 (0x1u << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */ +#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */ +#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */ +#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */ +#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */ +#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */ +#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */ +#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */ +#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */ +#define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */ +#define PMC_PCSR0_PID17 (0x1u << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */ +#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */ +#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */ +#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */ +#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */ +#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */ +#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */ +#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */ +#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */ +#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */ +#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */ +#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */ +#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */ +#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */ +#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */ +/* -------- CKGR_UCKR : (PMC Offset: 0x001C) UTMI Clock Register -------- */ +#define CKGR_UCKR_UPLLEN (0x1u << 16) /**< \brief (CKGR_UCKR) UTMI PLL Enable */ +#define CKGR_UCKR_UPLLCOUNT_Pos 20 +#define CKGR_UCKR_UPLLCOUNT_Msk (0xfu << CKGR_UCKR_UPLLCOUNT_Pos) /**< \brief (CKGR_UCKR) UTMI PLL Start-up Time */ +#define CKGR_UCKR_UPLLCOUNT(value) ((CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos))) +/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */ +#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */ +#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */ +#define CKGR_MOR_WAITMODE (0x1u << 2) /**< \brief (CKGR_MOR) Wait Mode Command (Write-only) */ +#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */ +#define CKGR_MOR_MOSCRCF_Pos 4 +#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */ +#define CKGR_MOR_MOSCRCF(value) ((CKGR_MOR_MOSCRCF_Msk & ((value) << CKGR_MOR_MOSCRCF_Pos))) +#define CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) /**< \brief (CKGR_MOR) Fast RC oscillator frequency is at 4 MHz (default) */ +#define CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) /**< \brief (CKGR_MOR) Fast RC oscillator frequency is at 8 MHz */ +#define CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) /**< \brief (CKGR_MOR) Fast RC oscillator frequency is at 12 MHz */ +#define CKGR_MOR_MOSCXTST_Pos 8 +#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */ +#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos))) +#define CKGR_MOR_KEY_Pos 16 +#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Write Access Password */ +#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos))) +#define CKGR_MOR_KEY_PASSWD (0x37u << 16) /**< \brief (CKGR_MOR) Writing any other value in this field aborts the write operation.Always reads as 0. */ +#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */ +#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */ +#define CKGR_MOR_XT32KFME (0x1u << 26) /**< \brief (CKGR_MOR) Slow Crystal Oscillator Frequency Monitoring Enable */ +/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */ +#define CKGR_MCFR_MAINF_Pos 0 +#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */ +#define CKGR_MCFR_MAINF(value) ((CKGR_MCFR_MAINF_Msk & ((value) << CKGR_MCFR_MAINF_Pos))) +#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Frequency Measure Ready */ +#define CKGR_MCFR_RCMEAS (0x1u << 20) /**< \brief (CKGR_MCFR) RC Oscillator Frequency Measure (write-only) */ +#define CKGR_MCFR_CCSS (0x1u << 24) /**< \brief (CKGR_MCFR) Counter Clock Source Selection */ +/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */ +#define CKGR_PLLAR_DIVA_Pos 0 +#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) PLLA Front End Divider */ +#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos))) +#define CKGR_PLLAR_DIVA_0 (0x0u << 0) /**< \brief (CKGR_PLLAR) Divider output is 0 and PLLA is disabled. */ +#define CKGR_PLLAR_DIVA_BYPASS (0x1u << 0) /**< \brief (CKGR_PLLAR) Divider is bypassed (divide by 1) and PLLA is enabled. */ +#define CKGR_PLLAR_PLLACOUNT_Pos 8 +#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */ +#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos))) +#define CKGR_PLLAR_MULA_Pos 16 +#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */ +#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos))) +#define CKGR_PLLAR_ONE (0x1u << 29) /**< \brief (CKGR_PLLAR) Must Be Set to 1 */ +/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */ +#define PMC_MCKR_CSS_Pos 0 +#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */ +#define PMC_MCKR_CSS(value) ((PMC_MCKR_CSS_Msk & ((value) << PMC_MCKR_CSS_Pos))) +#define PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */ +#define PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */ +#define PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */ +#define PMC_MCKR_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_MCKR) Divided UPLL Clock is selected */ +#define PMC_MCKR_PRES_Pos 4 +#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */ +#define PMC_MCKR_PRES(value) ((PMC_MCKR_PRES_Msk & ((value) << PMC_MCKR_PRES_Pos))) +#define PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */ +#define PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */ +#define PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */ +#define PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */ +#define PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */ +#define PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */ +#define PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */ +#define PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */ +#define PMC_MCKR_MDIV_Pos 8 +#define PMC_MCKR_MDIV_Msk (0x3u << PMC_MCKR_MDIV_Pos) /**< \brief (PMC_MCKR) Master Clock Division */ +#define PMC_MCKR_MDIV(value) ((PMC_MCKR_MDIV_Msk & ((value) << PMC_MCKR_MDIV_Pos))) +#define PMC_MCKR_MDIV_EQ_PCK (0x0u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 1. */ +#define PMC_MCKR_MDIV_PCK_DIV2 (0x1u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 2. */ +#define PMC_MCKR_MDIV_PCK_DIV4 (0x2u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 4. */ +#define PMC_MCKR_MDIV_PCK_DIV3 (0x3u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 3. */ +#define PMC_MCKR_UPLLDIV2 (0x1u << 13) /**< \brief (PMC_MCKR) UPLL Divisor by 2 */ +/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */ +#define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB Input Clock Selection */ +#define PMC_USB_USBDIV_Pos 8 +#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock */ +#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos))) +/* -------- PMC_PCK[7] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */ +#define PMC_PCK_CSS_Pos 0 +#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[7]) Master Clock Source Selection */ +#define PMC_PCK_CSS(value) ((PMC_PCK_CSS_Msk & ((value) << PMC_PCK_CSS_Pos))) +#define PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[7]) Slow Clock is selected */ +#define PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[7]) Main Clock is selected */ +#define PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[7]) PLLA Clock is selected */ +#define PMC_PCK_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_PCK[7]) Divided UPLL Clock is selected */ +#define PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[7]) Master Clock is selected */ +#define PMC_PCK_PRES_Pos 4 +#define PMC_PCK_PRES_Msk (0xffu << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[7]) Programmable Clock Prescaler */ +#define PMC_PCK_PRES(value) ((PMC_PCK_PRES_Msk & ((value) << PMC_PCK_PRES_Pos))) +/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */ +#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */ +#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */ +#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */ +#define PMC_IER_LOCKU (0x1u << 6) /**< \brief (PMC_IER) UTMI PLL Lock Interrupt Enable */ +#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */ +#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */ +#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */ +#define PMC_IER_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IER) Programmable Clock Ready 3 Interrupt Enable */ +#define PMC_IER_PCKRDY4 (0x1u << 12) /**< \brief (PMC_IER) Programmable Clock Ready 4 Interrupt Enable */ +#define PMC_IER_PCKRDY5 (0x1u << 13) /**< \brief (PMC_IER) Programmable Clock Ready 5 Interrupt Enable */ +#define PMC_IER_PCKRDY6 (0x1u << 14) /**< \brief (PMC_IER) Programmable Clock Ready 6 Interrupt Enable */ +#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */ +#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */ +#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */ +#define PMC_IER_XT32KERR (0x1u << 21) /**< \brief (PMC_IER) Slow Crystal Oscillator Error Interrupt Enable */ +/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */ +#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */ +#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */ +#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */ +#define PMC_IDR_LOCKU (0x1u << 6) /**< \brief (PMC_IDR) UTMI PLL Lock Interrupt Disable */ +#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */ +#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */ +#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */ +#define PMC_IDR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IDR) Programmable Clock Ready 3 Interrupt Disable */ +#define PMC_IDR_PCKRDY4 (0x1u << 12) /**< \brief (PMC_IDR) Programmable Clock Ready 4 Interrupt Disable */ +#define PMC_IDR_PCKRDY5 (0x1u << 13) /**< \brief (PMC_IDR) Programmable Clock Ready 5 Interrupt Disable */ +#define PMC_IDR_PCKRDY6 (0x1u << 14) /**< \brief (PMC_IDR) Programmable Clock Ready 6 Interrupt Disable */ +#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */ +#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */ +#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */ +#define PMC_IDR_XT32KERR (0x1u << 21) /**< \brief (PMC_IDR) Slow Crystal Oscillator Error Interrupt Disable */ +/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */ +#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main Crystal Oscillator Status */ +#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */ +#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */ +#define PMC_SR_LOCKU (0x1u << 6) /**< \brief (PMC_SR) UTMI PLL Lock Status */ +#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */ +#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY4 (0x1u << 12) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY5 (0x1u << 13) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY6 (0x1u << 14) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */ +#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */ +#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */ +#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */ +#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */ +#define PMC_SR_XT32KERR (0x1u << 21) /**< \brief (PMC_SR) Slow Crystal Oscillator Error */ +/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */ +#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */ +#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */ +#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */ +#define PMC_IMR_LOCKU (0x1u << 6) /**< \brief (PMC_IMR) UTMI PLL Lock Interrupt Mask */ +#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */ +#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */ +#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */ +#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */ +#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */ +#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */ +#define PMC_IMR_XT32KERR (0x1u << 21) /**< \brief (PMC_IMR) Slow Crystal Oscillator Error Interrupt Mask */ +/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */ +#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */ +#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */ +#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */ +#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */ +#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */ +#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */ +#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */ +#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */ +#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */ +#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */ +#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */ +#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */ +#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */ +#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */ +#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */ +#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */ +#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */ +#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */ +#define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */ +#define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low-power Mode */ +#define PMC_FSMR_FLPM_Pos 21 +#define PMC_FSMR_FLPM_Msk (0x3u << PMC_FSMR_FLPM_Pos) /**< \brief (PMC_FSMR) Flash Low-power Mode */ +#define PMC_FSMR_FLPM(value) ((PMC_FSMR_FLPM_Msk & ((value) << PMC_FSMR_FLPM_Pos))) +#define PMC_FSMR_FLPM_FLASH_STANDBY (0x0u << 21) /**< \brief (PMC_FSMR) Flash is in Standby Mode when system enters Wait Mode */ +#define PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN (0x1u << 21) /**< \brief (PMC_FSMR) Flash is in Deep-power-down mode when system enters Wait Mode */ +#define PMC_FSMR_FLPM_FLASH_IDLE (0x2u << 21) /**< \brief (PMC_FSMR) Idle mode */ +#define PMC_FSMR_FFLPM (0x1u << 23) /**< \brief (PMC_FSMR) Force Flash Low-power Mode */ +/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */ +#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 0 */ +#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 1 */ +#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 2 */ +#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 3 */ +#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 4 */ +#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 5 */ +#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 6 */ +#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 7 */ +#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 8 */ +#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 9 */ +#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 10 */ +#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 11 */ +#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 12 */ +#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 13 */ +#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 14 */ +#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 15 */ +/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */ +#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */ +/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protection Mode Register -------- */ +#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protection Enable */ +#define PMC_WPMR_WPKEY_Pos 8 +#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protection Key */ +#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos))) +#define PMC_WPMR_WPKEY_PASSWD (0x504D43u << 8) /**< \brief (PMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protection Status Register -------- */ +#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protection Violation Status */ +#define PMC_WPSR_WPVSRC_Pos 8 +#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protection Violation Source */ +/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */ +#define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */ +#define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */ +#define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */ +#define PMC_PCER1_PID35 (0x1u << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */ +#define PMC_PCER1_PID37 (0x1u << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */ +#define PMC_PCER1_PID39 (0x1u << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */ +#define PMC_PCER1_PID40 (0x1u << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */ +#define PMC_PCER1_PID41 (0x1u << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */ +#define PMC_PCER1_PID42 (0x1u << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */ +#define PMC_PCER1_PID43 (0x1u << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */ +#define PMC_PCER1_PID44 (0x1u << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */ +#define PMC_PCER1_PID45 (0x1u << 13) /**< \brief (PMC_PCER1) Peripheral Clock 45 Enable */ +#define PMC_PCER1_PID46 (0x1u << 14) /**< \brief (PMC_PCER1) Peripheral Clock 46 Enable */ +#define PMC_PCER1_PID47 (0x1u << 15) /**< \brief (PMC_PCER1) Peripheral Clock 47 Enable */ +#define PMC_PCER1_PID48 (0x1u << 16) /**< \brief (PMC_PCER1) Peripheral Clock 48 Enable */ +#define PMC_PCER1_PID49 (0x1u << 17) /**< \brief (PMC_PCER1) Peripheral Clock 49 Enable */ +#define PMC_PCER1_PID50 (0x1u << 18) /**< \brief (PMC_PCER1) Peripheral Clock 50 Enable */ +#define PMC_PCER1_PID51 (0x1u << 19) /**< \brief (PMC_PCER1) Peripheral Clock 51 Enable */ +#define PMC_PCER1_PID52 (0x1u << 20) /**< \brief (PMC_PCER1) Peripheral Clock 52 Enable */ +#define PMC_PCER1_PID53 (0x1u << 21) /**< \brief (PMC_PCER1) Peripheral Clock 53 Enable */ +#define PMC_PCER1_PID56 (0x1u << 24) /**< \brief (PMC_PCER1) Peripheral Clock 56 Enable */ +#define PMC_PCER1_PID57 (0x1u << 25) /**< \brief (PMC_PCER1) Peripheral Clock 57 Enable */ +#define PMC_PCER1_PID58 (0x1u << 26) /**< \brief (PMC_PCER1) Peripheral Clock 58 Enable */ +#define PMC_PCER1_PID59 (0x1u << 27) /**< \brief (PMC_PCER1) Peripheral Clock 59 Enable */ +#define PMC_PCER1_PID60 (0x1u << 28) /**< \brief (PMC_PCER1) Peripheral Clock 60 Enable */ +/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */ +#define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */ +#define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */ +#define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */ +#define PMC_PCDR1_PID35 (0x1u << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */ +#define PMC_PCDR1_PID37 (0x1u << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */ +#define PMC_PCDR1_PID39 (0x1u << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */ +#define PMC_PCDR1_PID40 (0x1u << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */ +#define PMC_PCDR1_PID41 (0x1u << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */ +#define PMC_PCDR1_PID42 (0x1u << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */ +#define PMC_PCDR1_PID43 (0x1u << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */ +#define PMC_PCDR1_PID44 (0x1u << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */ +#define PMC_PCDR1_PID45 (0x1u << 13) /**< \brief (PMC_PCDR1) Peripheral Clock 45 Disable */ +#define PMC_PCDR1_PID46 (0x1u << 14) /**< \brief (PMC_PCDR1) Peripheral Clock 46 Disable */ +#define PMC_PCDR1_PID47 (0x1u << 15) /**< \brief (PMC_PCDR1) Peripheral Clock 47 Disable */ +#define PMC_PCDR1_PID48 (0x1u << 16) /**< \brief (PMC_PCDR1) Peripheral Clock 48 Disable */ +#define PMC_PCDR1_PID49 (0x1u << 17) /**< \brief (PMC_PCDR1) Peripheral Clock 49 Disable */ +#define PMC_PCDR1_PID50 (0x1u << 18) /**< \brief (PMC_PCDR1) Peripheral Clock 50 Disable */ +#define PMC_PCDR1_PID51 (0x1u << 19) /**< \brief (PMC_PCDR1) Peripheral Clock 51 Disable */ +#define PMC_PCDR1_PID52 (0x1u << 20) /**< \brief (PMC_PCDR1) Peripheral Clock 52 Disable */ +#define PMC_PCDR1_PID53 (0x1u << 21) /**< \brief (PMC_PCDR1) Peripheral Clock 53 Disable */ +#define PMC_PCDR1_PID56 (0x1u << 24) /**< \brief (PMC_PCDR1) Peripheral Clock 56 Disable */ +#define PMC_PCDR1_PID57 (0x1u << 25) /**< \brief (PMC_PCDR1) Peripheral Clock 57 Disable */ +#define PMC_PCDR1_PID58 (0x1u << 26) /**< \brief (PMC_PCDR1) Peripheral Clock 58 Disable */ +#define PMC_PCDR1_PID59 (0x1u << 27) /**< \brief (PMC_PCDR1) Peripheral Clock 59 Disable */ +#define PMC_PCDR1_PID60 (0x1u << 28) /**< \brief (PMC_PCDR1) Peripheral Clock 60 Disable */ +/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */ +#define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */ +#define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */ +#define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */ +#define PMC_PCSR1_PID35 (0x1u << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */ +#define PMC_PCSR1_PID37 (0x1u << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */ +#define PMC_PCSR1_PID39 (0x1u << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */ +#define PMC_PCSR1_PID40 (0x1u << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */ +#define PMC_PCSR1_PID41 (0x1u << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */ +#define PMC_PCSR1_PID42 (0x1u << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */ +#define PMC_PCSR1_PID43 (0x1u << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */ +#define PMC_PCSR1_PID44 (0x1u << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */ +#define PMC_PCSR1_PID45 (0x1u << 13) /**< \brief (PMC_PCSR1) Peripheral Clock 45 Status */ +#define PMC_PCSR1_PID46 (0x1u << 14) /**< \brief (PMC_PCSR1) Peripheral Clock 46 Status */ +#define PMC_PCSR1_PID47 (0x1u << 15) /**< \brief (PMC_PCSR1) Peripheral Clock 47 Status */ +#define PMC_PCSR1_PID48 (0x1u << 16) /**< \brief (PMC_PCSR1) Peripheral Clock 48 Status */ +#define PMC_PCSR1_PID49 (0x1u << 17) /**< \brief (PMC_PCSR1) Peripheral Clock 49 Status */ +#define PMC_PCSR1_PID50 (0x1u << 18) /**< \brief (PMC_PCSR1) Peripheral Clock 50 Status */ +#define PMC_PCSR1_PID51 (0x1u << 19) /**< \brief (PMC_PCSR1) Peripheral Clock 51 Status */ +#define PMC_PCSR1_PID52 (0x1u << 20) /**< \brief (PMC_PCSR1) Peripheral Clock 52 Status */ +#define PMC_PCSR1_PID53 (0x1u << 21) /**< \brief (PMC_PCSR1) Peripheral Clock 53 Status */ +#define PMC_PCSR1_PID56 (0x1u << 24) /**< \brief (PMC_PCSR1) Peripheral Clock 56 Status */ +#define PMC_PCSR1_PID57 (0x1u << 25) /**< \brief (PMC_PCSR1) Peripheral Clock 57 Status */ +#define PMC_PCSR1_PID58 (0x1u << 26) /**< \brief (PMC_PCSR1) Peripheral Clock 58 Status */ +#define PMC_PCSR1_PID59 (0x1u << 27) /**< \brief (PMC_PCSR1) Peripheral Clock 59 Status */ +#define PMC_PCSR1_PID60 (0x1u << 28) /**< \brief (PMC_PCSR1) Peripheral Clock 60 Status */ +/* -------- PMC_PCR : (PMC Offset: 0x010C) Peripheral Control Register -------- */ +#define PMC_PCR_PID_Pos 0 +#define PMC_PCR_PID_Msk (0x3fu << PMC_PCR_PID_Pos) /**< \brief (PMC_PCR) Peripheral ID */ +#define PMC_PCR_PID(value) ((PMC_PCR_PID_Msk & ((value) << PMC_PCR_PID_Pos))) +#define PMC_PCR_CMD (0x1u << 12) /**< \brief (PMC_PCR) Command */ +#define PMC_PCR_DIV_Pos 16 +#define PMC_PCR_DIV_Msk (0x3u << PMC_PCR_DIV_Pos) /**< \brief (PMC_PCR) Divisor Value */ +#define PMC_PCR_DIV(value) ((PMC_PCR_DIV_Msk & ((value) << PMC_PCR_DIV_Pos))) +#define PMC_PCR_DIV_PERIPH_DIV_MCK (0x0u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK */ +#define PMC_PCR_DIV_PERIPH_DIV2_MCK (0x1u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/2 */ +#define PMC_PCR_DIV_PERIPH_DIV4_MCK (0x2u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/4 */ +#define PMC_PCR_DIV_PERIPH_DIV8_MCK (0x3u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/8 */ +#define PMC_PCR_EN (0x1u << 28) /**< \brief (PMC_PCR) Enable */ +/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */ +#define PMC_OCR_CAL4_Pos 0 +#define PMC_OCR_CAL4_Msk (0x7fu << PMC_OCR_CAL4_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 MHz */ +#define PMC_OCR_CAL4(value) ((PMC_OCR_CAL4_Msk & ((value) << PMC_OCR_CAL4_Pos))) +#define PMC_OCR_SEL4 (0x1u << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 MHz */ +#define PMC_OCR_CAL8_Pos 8 +#define PMC_OCR_CAL8_Msk (0x7fu << PMC_OCR_CAL8_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 MHz */ +#define PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos))) +#define PMC_OCR_SEL8 (0x1u << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 MHz */ +#define PMC_OCR_CAL12_Pos 16 +#define PMC_OCR_CAL12_Msk (0x7fu << PMC_OCR_CAL12_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 MHz */ +#define PMC_OCR_CAL12(value) ((PMC_OCR_CAL12_Msk & ((value) << PMC_OCR_CAL12_Pos))) +#define PMC_OCR_SEL12 (0x1u << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 MHz */ +/* -------- PMC_SLPWK_ER0 : (PMC Offset: 0x0114) SleepWalking Enable Register 0 -------- */ +#define PMC_SLPWK_ER0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_ER0) Peripheral 7 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_ER0) Peripheral 8 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_ER0) Peripheral 9 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_ER0) Peripheral 10 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_ER0) Peripheral 11 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_ER0) Peripheral 12 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_ER0) Peripheral 13 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_ER0) Peripheral 14 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_ER0) Peripheral 15 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_ER0) Peripheral 16 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_ER0) Peripheral 17 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_ER0) Peripheral 18 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_ER0) Peripheral 19 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_ER0) Peripheral 20 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_ER0) Peripheral 21 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_ER0) Peripheral 22 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_ER0) Peripheral 23 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_ER0) Peripheral 24 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_ER0) Peripheral 25 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_ER0) Peripheral 26 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_ER0) Peripheral 27 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_ER0) Peripheral 28 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_ER0) Peripheral 29 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_ER0) Peripheral 30 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_ER0) Peripheral 31 SleepWalking Enable */ +/* -------- PMC_SLPWK_DR0 : (PMC Offset: 0x0118) SleepWalking Disable Register 0 -------- */ +#define PMC_SLPWK_DR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_DR0) Peripheral 7 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_DR0) Peripheral 8 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_DR0) Peripheral 9 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_DR0) Peripheral 10 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_DR0) Peripheral 11 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_DR0) Peripheral 12 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_DR0) Peripheral 13 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_DR0) Peripheral 14 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_DR0) Peripheral 15 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_DR0) Peripheral 16 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_DR0) Peripheral 17 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_DR0) Peripheral 18 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_DR0) Peripheral 19 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_DR0) Peripheral 20 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_DR0) Peripheral 21 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_DR0) Peripheral 22 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_DR0) Peripheral 23 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_DR0) Peripheral 24 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_DR0) Peripheral 25 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_DR0) Peripheral 26 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_DR0) Peripheral 27 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_DR0) Peripheral 28 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_DR0) Peripheral 29 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_DR0) Peripheral 30 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_DR0) Peripheral 31 SleepWalking Disable */ +/* -------- PMC_SLPWK_SR0 : (PMC Offset: 0x011C) SleepWalking Status Register 0 -------- */ +#define PMC_SLPWK_SR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_SR0) Peripheral 7 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_SR0) Peripheral 8 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_SR0) Peripheral 9 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_SR0) Peripheral 10 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_SR0) Peripheral 11 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_SR0) Peripheral 12 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_SR0) Peripheral 13 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_SR0) Peripheral 14 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_SR0) Peripheral 15 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_SR0) Peripheral 16 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_SR0) Peripheral 17 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_SR0) Peripheral 18 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_SR0) Peripheral 19 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_SR0) Peripheral 20 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_SR0) Peripheral 21 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_SR0) Peripheral 22 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_SR0) Peripheral 23 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_SR0) Peripheral 24 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_SR0) Peripheral 25 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_SR0) Peripheral 26 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_SR0) Peripheral 27 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_SR0) Peripheral 28 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_SR0) Peripheral 29 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_SR0) Peripheral 30 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_SR0) Peripheral 31 SleepWalking Status */ +/* -------- PMC_SLPWK_ASR0 : (PMC Offset: 0x0120) SleepWalking Activity Status Register 0 -------- */ +#define PMC_SLPWK_ASR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_ASR0) Peripheral 7 Activity Status */ +#define PMC_SLPWK_ASR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_ASR0) Peripheral 8 Activity Status */ +#define PMC_SLPWK_ASR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_ASR0) Peripheral 9 Activity Status */ +#define PMC_SLPWK_ASR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_ASR0) Peripheral 10 Activity Status */ +#define PMC_SLPWK_ASR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_ASR0) Peripheral 11 Activity Status */ +#define PMC_SLPWK_ASR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_ASR0) Peripheral 12 Activity Status */ +#define PMC_SLPWK_ASR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_ASR0) Peripheral 13 Activity Status */ +#define PMC_SLPWK_ASR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_ASR0) Peripheral 14 Activity Status */ +#define PMC_SLPWK_ASR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_ASR0) Peripheral 15 Activity Status */ +#define PMC_SLPWK_ASR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_ASR0) Peripheral 16 Activity Status */ +#define PMC_SLPWK_ASR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_ASR0) Peripheral 17 Activity Status */ +#define PMC_SLPWK_ASR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_ASR0) Peripheral 18 Activity Status */ +#define PMC_SLPWK_ASR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_ASR0) Peripheral 19 Activity Status */ +#define PMC_SLPWK_ASR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_ASR0) Peripheral 20 Activity Status */ +#define PMC_SLPWK_ASR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_ASR0) Peripheral 21 Activity Status */ +#define PMC_SLPWK_ASR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_ASR0) Peripheral 22 Activity Status */ +#define PMC_SLPWK_ASR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_ASR0) Peripheral 23 Activity Status */ +#define PMC_SLPWK_ASR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_ASR0) Peripheral 24 Activity Status */ +#define PMC_SLPWK_ASR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_ASR0) Peripheral 25 Activity Status */ +#define PMC_SLPWK_ASR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_ASR0) Peripheral 26 Activity Status */ +#define PMC_SLPWK_ASR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_ASR0) Peripheral 27 Activity Status */ +#define PMC_SLPWK_ASR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_ASR0) Peripheral 28 Activity Status */ +#define PMC_SLPWK_ASR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_ASR0) Peripheral 29 Activity Status */ +#define PMC_SLPWK_ASR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_ASR0) Peripheral 30 Activity Status */ +#define PMC_SLPWK_ASR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_ASR0) Peripheral 31 Activity Status */ +/* -------- PMC_SLPWK_ER1 : (PMC Offset: 0x0134) SleepWalking Enable Register 1 -------- */ +#define PMC_SLPWK_ER1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_ER1) Peripheral 32 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_ER1) Peripheral 33 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_ER1) Peripheral 34 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_ER1) Peripheral 35 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_ER1) Peripheral 37 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_ER1) Peripheral 39 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_ER1) Peripheral 40 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_ER1) Peripheral 41 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_ER1) Peripheral 42 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_ER1) Peripheral 43 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_ER1) Peripheral 44 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_ER1) Peripheral 45 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_ER1) Peripheral 46 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_ER1) Peripheral 47 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_ER1) Peripheral 48 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_ER1) Peripheral 49 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_ER1) Peripheral 50 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_ER1) Peripheral 51 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_ER1) Peripheral 52 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_ER1) Peripheral 53 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_ER1) Peripheral 56 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_ER1) Peripheral 57 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_ER1) Peripheral 58 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_ER1) Peripheral 59 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_ER1) Peripheral 60 SleepWalking Enable */ +/* -------- PMC_SLPWK_DR1 : (PMC Offset: 0x0138) SleepWalking Disable Register 1 -------- */ +#define PMC_SLPWK_DR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_DR1) Peripheral 32 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_DR1) Peripheral 33 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_DR1) Peripheral 34 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_DR1) Peripheral 35 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_DR1) Peripheral 37 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_DR1) Peripheral 39 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_DR1) Peripheral 40 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_DR1) Peripheral 41 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_DR1) Peripheral 42 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_DR1) Peripheral 43 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_DR1) Peripheral 44 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_DR1) Peripheral 45 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_DR1) Peripheral 46 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_DR1) Peripheral 47 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_DR1) Peripheral 48 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_DR1) Peripheral 49 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_DR1) Peripheral 50 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_DR1) Peripheral 51 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_DR1) Peripheral 52 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_DR1) Peripheral 53 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_DR1) Peripheral 56 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_DR1) Peripheral 57 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_DR1) Peripheral 58 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_DR1) Peripheral 59 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_DR1) Peripheral 60 SleepWalking Disable */ +/* -------- PMC_SLPWK_SR1 : (PMC Offset: 0x013C) SleepWalking Status Register 1 -------- */ +#define PMC_SLPWK_SR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_SR1) Peripheral 32 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_SR1) Peripheral 33 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_SR1) Peripheral 34 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_SR1) Peripheral 35 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_SR1) Peripheral 37 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_SR1) Peripheral 39 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_SR1) Peripheral 40 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_SR1) Peripheral 41 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_SR1) Peripheral 42 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_SR1) Peripheral 43 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_SR1) Peripheral 44 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_SR1) Peripheral 45 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_SR1) Peripheral 46 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_SR1) Peripheral 47 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_SR1) Peripheral 48 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_SR1) Peripheral 49 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_SR1) Peripheral 50 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_SR1) Peripheral 51 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_SR1) Peripheral 52 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_SR1) Peripheral 53 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_SR1) Peripheral 56 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_SR1) Peripheral 57 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_SR1) Peripheral 58 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_SR1) Peripheral 59 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_SR1) Peripheral 60 SleepWalking Status */ +/* -------- PMC_SLPWK_ASR1 : (PMC Offset: 0x0140) SleepWalking Activity Status Register 1 -------- */ +#define PMC_SLPWK_ASR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_ASR1) Peripheral 32 Activity Status */ +#define PMC_SLPWK_ASR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_ASR1) Peripheral 33 Activity Status */ +#define PMC_SLPWK_ASR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_ASR1) Peripheral 34 Activity Status */ +#define PMC_SLPWK_ASR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_ASR1) Peripheral 35 Activity Status */ +#define PMC_SLPWK_ASR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_ASR1) Peripheral 37 Activity Status */ +#define PMC_SLPWK_ASR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_ASR1) Peripheral 39 Activity Status */ +#define PMC_SLPWK_ASR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_ASR1) Peripheral 40 Activity Status */ +#define PMC_SLPWK_ASR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_ASR1) Peripheral 41 Activity Status */ +#define PMC_SLPWK_ASR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_ASR1) Peripheral 42 Activity Status */ +#define PMC_SLPWK_ASR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_ASR1) Peripheral 43 Activity Status */ +#define PMC_SLPWK_ASR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_ASR1) Peripheral 44 Activity Status */ +#define PMC_SLPWK_ASR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_ASR1) Peripheral 45 Activity Status */ +#define PMC_SLPWK_ASR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_ASR1) Peripheral 46 Activity Status */ +#define PMC_SLPWK_ASR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_ASR1) Peripheral 47 Activity Status */ +#define PMC_SLPWK_ASR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_ASR1) Peripheral 48 Activity Status */ +#define PMC_SLPWK_ASR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_ASR1) Peripheral 49 Activity Status */ +#define PMC_SLPWK_ASR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_ASR1) Peripheral 50 Activity Status */ +#define PMC_SLPWK_ASR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_ASR1) Peripheral 51 Activity Status */ +#define PMC_SLPWK_ASR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_ASR1) Peripheral 52 Activity Status */ +#define PMC_SLPWK_ASR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_ASR1) Peripheral 53 Activity Status */ +#define PMC_SLPWK_ASR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_ASR1) Peripheral 56 Activity Status */ +#define PMC_SLPWK_ASR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_ASR1) Peripheral 57 Activity Status */ +#define PMC_SLPWK_ASR1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_ASR1) Peripheral 58 Activity Status */ +#define PMC_SLPWK_ASR1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_ASR1) Peripheral 59 Activity Status */ +#define PMC_SLPWK_ASR1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_ASR1) Peripheral 60 Activity Status */ +/* -------- PMC_SLPWK_AIPR : (PMC Offset: 0x0144) SleepWalking Activity In Progress Register -------- */ +#define PMC_SLPWK_AIPR_AIP (0x1u << 0) /**< \brief (PMC_SLPWK_AIPR) Activity In Progress */ + +/*@}*/ + + +#endif /* _SAMV71_PMC_COMPONENT_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_pwm.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_pwm.h new file mode 100644 index 00000000..50d92f43 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_pwm.h @@ -0,0 +1,700 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_PWM_COMPONENT_ +#define _SAMV71_PWM_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_PWM Pulse Width Modulation Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief PwmCh_num hardware registers */ +typedef struct { + __IO uint32_t PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */ + __IO uint32_t PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */ + __O uint32_t PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */ + __IO uint32_t PWM_CPRD; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */ + __O uint32_t PWM_CPRDUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */ + __I uint32_t PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */ + __IO uint32_t PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */ + __O uint32_t PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */ +} PwmCh_num; +/** \brief PwmCmp hardware registers */ +typedef struct { + __IO uint32_t PWM_CMPV; /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */ + __O uint32_t PWM_CMPVUPD; /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */ + __IO uint32_t PWM_CMPM; /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */ + __O uint32_t PWM_CMPMUPD; /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */ +} PwmCmp; +/** \brief Pwm hardware registers */ +#define PWMCMP_NUMBER 8 +#define PWMCH_NUM_NUMBER 4 +typedef struct { + __IO uint32_t PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */ + __O uint32_t PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */ + __O uint32_t PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */ + __I uint32_t PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */ + __O uint32_t PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */ + __O uint32_t PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */ + __I uint32_t PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */ + __I uint32_t PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */ + __IO uint32_t PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */ + __O uint32_t PWM_DMAR; /**< \brief (Pwm Offset: 0x24) PWM DMA Register */ + __IO uint32_t PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */ + __IO uint32_t PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */ + __O uint32_t PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */ + __O uint32_t PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */ + __O uint32_t PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */ + __I uint32_t PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */ + __I uint32_t PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */ + __IO uint32_t PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */ + __IO uint32_t PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */ + __O uint32_t PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */ + __O uint32_t PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */ + __O uint32_t PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */ + __O uint32_t PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */ + __IO uint32_t PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */ + __I uint32_t PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */ + __O uint32_t PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */ + __IO uint32_t PWM_FPV1; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register 1 */ + __IO uint32_t PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */ + __I uint32_t Reserved1[3]; + __IO uint32_t PWM_ELMR[8]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t PWM_SSPR; /**< \brief (Pwm Offset: 0xA0) PWM Spread Spectrum Register */ + __O uint32_t PWM_SSPUP; /**< \brief (Pwm Offset: 0xA4) PWM Spread Spectrum Update Register */ + __I uint32_t Reserved3[2]; + __IO uint32_t PWM_SMMR; /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */ + __I uint32_t Reserved4[3]; + __IO uint32_t PWM_FPV2; /**< \brief (Pwm Offset: 0xC0) PWM Fault Protection Value 2 Register */ + __I uint32_t Reserved5[8]; + __O uint32_t PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protection Control Register */ + __I uint32_t PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protection Status Register */ + __I uint32_t Reserved6[17]; + PwmCmp PWM_CMP[PWMCMP_NUMBER]; /**< \brief (Pwm Offset: 0x130) 0 .. 7 */ + __I uint32_t Reserved7[20]; + PwmCh_num PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */ + __I uint32_t Reserved8[96]; + __O uint32_t PWM_CMUPD0; /**< \brief (Pwm Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) */ + __I uint32_t Reserved9[7]; + __O uint32_t PWM_CMUPD1; /**< \brief (Pwm Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) */ + __I uint32_t Reserved10[2]; + __IO uint32_t PWM_ETRG1; /**< \brief (Pwm Offset: 0x42C) PWM External Trigger Register (trg_num = 1) */ + __IO uint32_t PWM_LEBR1; /**< \brief (Pwm Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1) */ + __I uint32_t Reserved11[3]; + __O uint32_t PWM_CMUPD2; /**< \brief (Pwm Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) */ + __I uint32_t Reserved12[2]; + __IO uint32_t PWM_ETRG2; /**< \brief (Pwm Offset: 0x44C) PWM External Trigger Register (trg_num = 2) */ + __IO uint32_t PWM_LEBR2; /**< \brief (Pwm Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2) */ + __I uint32_t Reserved13[3]; + __O uint32_t PWM_CMUPD3; /**< \brief (Pwm Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) */ + __I uint32_t Reserved14[2]; + __IO uint32_t PWM_ETRG3; /**< \brief (Pwm Offset: 0x46C) PWM External Trigger Register (trg_num = 3) */ + __IO uint32_t PWM_LEBR3; /**< \brief (Pwm Offset: 0x470) PWM Leading-Edge Blanking Register (trg_num = 3) */ + __I uint32_t Reserved15[6]; + __IO uint32_t PWM_ETRG4; /**< \brief (Pwm Offset: 0x48C) PWM External Trigger Register (trg_num = 4) */ + __IO uint32_t PWM_LEBR4; /**< \brief (Pwm Offset: 0x490) PWM Leading-Edge Blanking Register (trg_num = 4) */ +} Pwm; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */ +#define PWM_CLK_DIVA_Pos 0 +#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA Divide Factor */ +#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos))) +#define PWM_CLK_DIVA_CLKA_POFF (0x0u << 0) /**< \brief (PWM_CLK) CLKA clock is turned off */ +#define PWM_CLK_DIVA_PREA (0x1u << 0) /**< \brief (PWM_CLK) CLKA clock is clock selected by PREA */ +#define PWM_CLK_PREA_Pos 8 +#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA Source Clock Selection */ +#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos))) +#define PWM_CLK_PREA_CLK (0x0u << 8) /**< \brief (PWM_CLK) Peripheral clock */ +#define PWM_CLK_PREA_CLK_DIV2 (0x1u << 8) /**< \brief (PWM_CLK) Peripheral clock/2 */ +#define PWM_CLK_PREA_CLK_DIV4 (0x2u << 8) /**< \brief (PWM_CLK) Peripheral clock/4 */ +#define PWM_CLK_PREA_CLK_DIV8 (0x3u << 8) /**< \brief (PWM_CLK) Peripheral clock/8 */ +#define PWM_CLK_PREA_CLK_DIV16 (0x4u << 8) /**< \brief (PWM_CLK) Peripheral clock/16 */ +#define PWM_CLK_PREA_CLK_DIV32 (0x5u << 8) /**< \brief (PWM_CLK) Peripheral clock/32 */ +#define PWM_CLK_PREA_CLK_DIV64 (0x6u << 8) /**< \brief (PWM_CLK) Peripheral clock/64 */ +#define PWM_CLK_PREA_CLK_DIV128 (0x7u << 8) /**< \brief (PWM_CLK) Peripheral clock/128 */ +#define PWM_CLK_PREA_CLK_DIV256 (0x8u << 8) /**< \brief (PWM_CLK) Peripheral clock/256 */ +#define PWM_CLK_PREA_CLK_DIV512 (0x9u << 8) /**< \brief (PWM_CLK) Peripheral clock/512 */ +#define PWM_CLK_PREA_CLK_DIV1024 (0xAu << 8) /**< \brief (PWM_CLK) Peripheral clock/1024 */ +#define PWM_CLK_DIVB_Pos 16 +#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKB Divide Factor */ +#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos))) +#define PWM_CLK_DIVB_CLKB_POFF (0x0u << 16) /**< \brief (PWM_CLK) CLKB clock is turned off */ +#define PWM_CLK_DIVB_PREB (0x1u << 16) /**< \brief (PWM_CLK) CLKB clock is clock selected by PREB */ +#define PWM_CLK_PREB_Pos 24 +#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKB Source Clock Selection */ +#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos))) +#define PWM_CLK_PREB_CLK (0x0u << 24) /**< \brief (PWM_CLK) Peripheral clock */ +#define PWM_CLK_PREB_CLK_DIV2 (0x1u << 24) /**< \brief (PWM_CLK) Peripheral clock/2 */ +#define PWM_CLK_PREB_CLK_DIV4 (0x2u << 24) /**< \brief (PWM_CLK) Peripheral clock/4 */ +#define PWM_CLK_PREB_CLK_DIV8 (0x3u << 24) /**< \brief (PWM_CLK) Peripheral clock/8 */ +#define PWM_CLK_PREB_CLK_DIV16 (0x4u << 24) /**< \brief (PWM_CLK) Peripheral clock/16 */ +#define PWM_CLK_PREB_CLK_DIV32 (0x5u << 24) /**< \brief (PWM_CLK) Peripheral clock/32 */ +#define PWM_CLK_PREB_CLK_DIV64 (0x6u << 24) /**< \brief (PWM_CLK) Peripheral clock/64 */ +#define PWM_CLK_PREB_CLK_DIV128 (0x7u << 24) /**< \brief (PWM_CLK) Peripheral clock/128 */ +#define PWM_CLK_PREB_CLK_DIV256 (0x8u << 24) /**< \brief (PWM_CLK) Peripheral clock/256 */ +#define PWM_CLK_PREB_CLK_DIV512 (0x9u << 24) /**< \brief (PWM_CLK) Peripheral clock/512 */ +#define PWM_CLK_PREB_CLK_DIV1024 (0xAu << 24) /**< \brief (PWM_CLK) Peripheral clock/1024 */ +/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */ +#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */ +/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */ +#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */ +/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */ +#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */ +/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */ +#define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */ +#define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */ +#define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */ +#define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */ +#define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */ +#define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */ +#define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */ +#define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */ +/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */ +#define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */ +#define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */ +#define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */ +#define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */ +#define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */ +#define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */ +#define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */ +#define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */ +/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */ +#define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */ +#define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */ +#define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */ +#define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */ +#define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */ +#define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */ +#define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */ +#define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */ +/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */ +#define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */ +#define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */ +#define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */ +#define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */ +#define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */ +#define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */ +#define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */ +#define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */ +/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */ +#define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */ +#define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */ +#define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */ +#define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */ +#define PWM_SCM_UPDM_Pos 16 +#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */ +#define PWM_SCM_UPDM(value) ((PWM_SCM_UPDM_Msk & ((value) << PWM_SCM_UPDM_Pos))) +#define PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */ +#define PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */ +#define PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the DMA and automatic update of synchronous channels */ +#define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) DMA Transfer Request Mode */ +#define PWM_SCM_PTRCS_Pos 21 +#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) DMA Transfer Request Comparison Selection */ +#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos))) +/* -------- PWM_DMAR : (PWM Offset: 0x24) PWM DMA Register -------- */ +#define PWM_DMAR_DMADUTY_Pos 0 +#define PWM_DMAR_DMADUTY_Msk (0xffffffu << PWM_DMAR_DMADUTY_Pos) /**< \brief (PWM_DMAR) Duty-Cycle Holding Register for DMA Access */ +#define PWM_DMAR_DMADUTY(value) ((PWM_DMAR_DMADUTY_Msk & ((value) << PWM_DMAR_DMADUTY_Pos))) +/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */ +#define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */ +/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */ +#define PWM_SCUP_UPR_Pos 0 +#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */ +#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos))) +#define PWM_SCUP_UPRCNT_Pos 4 +#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */ +#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos))) +/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */ +#define PWM_SCUPUPD_UPRUPD_Pos 0 +#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */ +#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos))) +/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */ +#define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */ +#define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */ +#define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */ +#define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */ +#define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */ +#define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */ +#define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */ +#define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */ +#define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */ +#define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */ +#define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */ +#define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */ +#define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */ +#define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */ +#define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */ +#define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */ +#define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */ +#define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */ +/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */ +#define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */ +#define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */ +#define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */ +#define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */ +#define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */ +#define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */ +#define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */ +#define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */ +#define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */ +#define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */ +#define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */ +#define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */ +#define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */ +#define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */ +#define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */ +#define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */ +#define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */ +#define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */ +/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */ +#define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */ +#define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */ +#define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */ +#define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */ +#define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */ +#define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */ +#define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */ +#define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */ +#define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */ +#define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */ +#define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */ +#define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */ +#define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */ +#define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */ +#define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */ +#define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */ +#define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */ +#define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */ +/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */ +#define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */ +#define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */ +#define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */ +#define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */ +#define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */ +#define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */ +#define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */ +#define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */ +#define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */ +#define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */ +#define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */ +#define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */ +#define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */ +#define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */ +#define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */ +#define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */ +#define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */ +#define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */ +/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */ +#define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */ +#define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */ +#define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */ +#define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */ +#define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */ +#define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */ +#define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */ +#define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */ +/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */ +#define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */ +#define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */ +#define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */ +#define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */ +#define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */ +#define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */ +#define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */ +#define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */ +/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */ +#define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */ +#define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */ +#define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */ +#define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */ +#define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */ +#define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */ +#define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */ +#define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */ +/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */ +#define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */ +#define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */ +#define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */ +#define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */ +#define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */ +#define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */ +#define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */ +#define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */ +/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */ +#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */ +#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */ +#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */ +#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */ +#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */ +#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */ +#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */ +#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */ +/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */ +#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */ +#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */ +#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */ +#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */ +#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */ +#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */ +#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */ +#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */ +/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */ +#define PWM_FMR_FPOL_Pos 0 +#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity */ +#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos))) +#define PWM_FMR_FMOD_Pos 8 +#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode */ +#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos))) +#define PWM_FMR_FFIL_Pos 16 +#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering */ +#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos))) +/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */ +#define PWM_FSR_FIV_Pos 0 +#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value */ +#define PWM_FSR_FS_Pos 8 +#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status */ +/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */ +#define PWM_FCR_FCLR_Pos 0 +#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear */ +#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos))) +/* -------- PWM_FPV1 : (PWM Offset: 0x68) PWM Fault Protection Value Register 1 -------- */ +#define PWM_FPV1_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 0 */ +#define PWM_FPV1_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 1 */ +#define PWM_FPV1_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 2 */ +#define PWM_FPV1_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 3 */ +#define PWM_FPV1_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 0 */ +#define PWM_FPV1_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 1 */ +#define PWM_FPV1_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 2 */ +#define PWM_FPV1_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 3 */ +/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */ +#define PWM_FPE_FPE0_Pos 0 +#define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 0 */ +#define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos))) +#define PWM_FPE_FPE1_Pos 8 +#define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 1 */ +#define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos))) +#define PWM_FPE_FPE2_Pos 16 +#define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 2 */ +#define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos))) +#define PWM_FPE_FPE3_Pos 24 +#define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 3 */ +#define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos))) +/* -------- PWM_ELMR[8] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */ +#define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[8]) Comparison 0 Selection */ +#define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[8]) Comparison 1 Selection */ +#define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[8]) Comparison 2 Selection */ +#define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[8]) Comparison 3 Selection */ +#define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[8]) Comparison 4 Selection */ +#define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[8]) Comparison 5 Selection */ +#define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[8]) Comparison 6 Selection */ +#define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[8]) Comparison 7 Selection */ +/* -------- PWM_SSPR : (PWM Offset: 0xA0) PWM Spread Spectrum Register -------- */ +#define PWM_SSPR_SPRD_Pos 0 +#define PWM_SSPR_SPRD_Msk (0xffffffu << PWM_SSPR_SPRD_Pos) /**< \brief (PWM_SSPR) Spread Spectrum Limit Value */ +#define PWM_SSPR_SPRD(value) ((PWM_SSPR_SPRD_Msk & ((value) << PWM_SSPR_SPRD_Pos))) +#define PWM_SSPR_SPRDM (0x1u << 24) /**< \brief (PWM_SSPR) Spread Spectrum Counter Mode */ +/* -------- PWM_SSPUP : (PWM Offset: 0xA4) PWM Spread Spectrum Update Register -------- */ +#define PWM_SSPUP_SPRDUP_Pos 0 +#define PWM_SSPUP_SPRDUP_Msk (0xffffffu << PWM_SSPUP_SPRDUP_Pos) /**< \brief (PWM_SSPUP) Spread Spectrum Limit Value Update */ +#define PWM_SSPUP_SPRDUP(value) ((PWM_SSPUP_SPRDUP_Msk & ((value) << PWM_SSPUP_SPRDUP_Pos))) +/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */ +#define PWM_SMMR_GCEN0 (0x1u << 0) /**< \brief (PWM_SMMR) Gray Count ENable */ +#define PWM_SMMR_GCEN1 (0x1u << 1) /**< \brief (PWM_SMMR) Gray Count ENable */ +#define PWM_SMMR_DOWN0 (0x1u << 16) /**< \brief (PWM_SMMR) DOWN Count */ +#define PWM_SMMR_DOWN1 (0x1u << 17) /**< \brief (PWM_SMMR) DOWN Count */ +/* -------- PWM_FPV2 : (PWM Offset: 0xC0) PWM Fault Protection Value 2 Register -------- */ +#define PWM_FPV2_FPZH0 (0x1u << 0) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 0 */ +#define PWM_FPV2_FPZH1 (0x1u << 1) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 1 */ +#define PWM_FPV2_FPZH2 (0x1u << 2) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 2 */ +#define PWM_FPV2_FPZH3 (0x1u << 3) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 3 */ +#define PWM_FPV2_FPZL0 (0x1u << 16) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 0 */ +#define PWM_FPV2_FPZL1 (0x1u << 17) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 1 */ +#define PWM_FPV2_FPZL2 (0x1u << 18) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 2 */ +#define PWM_FPV2_FPZL3 (0x1u << 19) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 3 */ +/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protection Control Register -------- */ +#define PWM_WPCR_WPCMD_Pos 0 +#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protection Command */ +#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos))) +#define PWM_WPCR_WPCMD_DISABLE_SW_PROT (0x0u << 0) /**< \brief (PWM_WPCR) Disables the software write protection of the register groups of which the bit WPRGx is at '1'. */ +#define PWM_WPCR_WPCMD_ENABLE_SW_PROT (0x1u << 0) /**< \brief (PWM_WPCR) Enables the software write protection of the register groups of which the bit WPRGx is at '1'. */ +#define PWM_WPCR_WPCMD_ENABLE_HW_PROT (0x2u << 0) /**< \brief (PWM_WPCR) Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface. */ +#define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protection Register Group 0 */ +#define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protection Register Group 1 */ +#define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protection Register Group 2 */ +#define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protection Register Group 3 */ +#define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protection Register Group 4 */ +#define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protection Register Group 5 */ +#define PWM_WPCR_WPKEY_Pos 8 +#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protection Key */ +#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos))) +#define PWM_WPCR_WPKEY_PASSWD (0x50574Du << 8) /**< \brief (PWM_WPCR) Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0 */ +/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protection Status Register -------- */ +#define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */ +#define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPVSRC_Pos 16 +#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */ +/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */ +#define PWM_CMPV_CV_Pos 0 +#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */ +#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos))) +#define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */ +/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */ +#define PWM_CMPVUPD_CVUPD_Pos 0 +#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */ +#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos))) +#define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */ +/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */ +#define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */ +#define PWM_CMPM_CTR_Pos 4 +#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */ +#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos))) +#define PWM_CMPM_CPR_Pos 8 +#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */ +#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos))) +#define PWM_CMPM_CPRCNT_Pos 12 +#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */ +#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos))) +#define PWM_CMPM_CUPR_Pos 16 +#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */ +#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos))) +#define PWM_CMPM_CUPRCNT_Pos 20 +#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */ +#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos))) +/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */ +#define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */ +#define PWM_CMPMUPD_CTRUPD_Pos 4 +#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */ +#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos))) +#define PWM_CMPMUPD_CPRUPD_Pos 8 +#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */ +#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos))) +#define PWM_CMPMUPD_CUPRUPD_Pos 16 +#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */ +#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos))) +/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */ +#define PWM_CMR_CPRE_Pos 0 +#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */ +#define PWM_CMR_CPRE(value) ((PWM_CMR_CPRE_Msk & ((value) << PWM_CMR_CPRE_Pos))) +#define PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Peripheral clock */ +#define PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Peripheral clock/2 */ +#define PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Peripheral clock/4 */ +#define PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Peripheral clock/8 */ +#define PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Peripheral clock/16 */ +#define PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Peripheral clock/32 */ +#define PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Peripheral clock/64 */ +#define PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Peripheral clock/128 */ +#define PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Peripheral clock/256 */ +#define PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Peripheral clock/512 */ +#define PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Peripheral clock/1024 */ +#define PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */ +#define PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */ +#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */ +#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */ +#define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */ +#define PWM_CMR_UPDS (0x1u << 11) /**< \brief (PWM_CMR) Update Selection */ +#define PWM_CMR_DPOLI (0x1u << 12) /**< \brief (PWM_CMR) Disabled Polarity Inverted */ +#define PWM_CMR_TCTS (0x1u << 13) /**< \brief (PWM_CMR) Timer Counter Trigger Selection */ +#define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */ +#define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */ +#define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */ +#define PWM_CMR_PPM (0x1u << 19) /**< \brief (PWM_CMR) Push-Pull Mode */ +/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */ +#define PWM_CDTY_CDTY_Pos 0 +#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */ +#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos))) +/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */ +#define PWM_CDTYUPD_CDTYUPD_Pos 0 +#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */ +#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos))) +/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */ +#define PWM_CPRD_CPRD_Pos 0 +#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */ +#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos))) +/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */ +#define PWM_CPRDUPD_CPRDUPD_Pos 0 +#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */ +#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos))) +/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */ +#define PWM_CCNT_CNT_Pos 0 +#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */ +/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */ +#define PWM_DT_DTH_Pos 0 +#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */ +#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos))) +#define PWM_DT_DTL_Pos 16 +#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */ +#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos))) +/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */ +#define PWM_DTUPD_DTHUPD_Pos 0 +#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */ +#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos))) +#define PWM_DTUPD_DTLUPD_Pos 16 +#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */ +#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos))) +/* -------- PWM_CMUPD0 : (PWM Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) -------- */ +#define PWM_CMUPD0_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD0) Channel Polarity Update */ +#define PWM_CMUPD0_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD0) Channel Polarity Inversion Update */ +/* -------- PWM_CMUPD1 : (PWM Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) -------- */ +#define PWM_CMUPD1_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD1) Channel Polarity Update */ +#define PWM_CMUPD1_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD1) Channel Polarity Inversion Update */ +/* -------- PWM_ETRG1 : (PWM Offset: 0x42C) PWM External Trigger Register (trg_num = 1) -------- */ +#define PWM_ETRG1_MAXCNT_Pos 0 +#define PWM_ETRG1_MAXCNT_Msk (0xffffffu << PWM_ETRG1_MAXCNT_Pos) /**< \brief (PWM_ETRG1) Maximum Counter value */ +#define PWM_ETRG1_MAXCNT(value) ((PWM_ETRG1_MAXCNT_Msk & ((value) << PWM_ETRG1_MAXCNT_Pos))) +#define PWM_ETRG1_TRGMODE_Pos 24 +#define PWM_ETRG1_TRGMODE_Msk (0x3u << PWM_ETRG1_TRGMODE_Pos) /**< \brief (PWM_ETRG1) External Trigger Mode */ +#define PWM_ETRG1_TRGMODE(value) ((PWM_ETRG1_TRGMODE_Msk & ((value) << PWM_ETRG1_TRGMODE_Pos))) +#define PWM_ETRG1_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG1) External trigger is not enabled. */ +#define PWM_ETRG1_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG1) External PWM Reset Mode */ +#define PWM_ETRG1_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG1) External PWM Start Mode */ +#define PWM_ETRG1_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG1) Cycle-by-cycle Duty Mode */ +#define PWM_ETRG1_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG1) Edge Selection */ +#define PWM_ETRG1_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */ +#define PWM_ETRG1_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */ +#define PWM_ETRG1_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG1) Filtered input */ +#define PWM_ETRG1_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG1) Trigger Source */ +#define PWM_ETRG1_RFEN (0x1u << 31) /**< \brief (PWM_ETRG1) Recoverable Fault Enable */ +/* -------- PWM_LEBR1 : (PWM Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1) -------- */ +#define PWM_LEBR1_LEBDELAY_Pos 0 +#define PWM_LEBR1_LEBDELAY_Msk (0x7fu << PWM_LEBR1_LEBDELAY_Pos) /**< \brief (PWM_LEBR1) Leading-Edge Blanking Delay for TRGINx */ +#define PWM_LEBR1_LEBDELAY(value) ((PWM_LEBR1_LEBDELAY_Msk & ((value) << PWM_LEBR1_LEBDELAY_Pos))) +#define PWM_LEBR1_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR1) PWML Falling Edge Enable */ +#define PWM_LEBR1_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR1) PWML Rising Edge Enable */ +#define PWM_LEBR1_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR1) PWMH Falling Edge Enable */ +#define PWM_LEBR1_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR1) PWMH Rising Edge Enable */ +/* -------- PWM_CMUPD2 : (PWM Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) -------- */ +#define PWM_CMUPD2_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD2) Channel Polarity Update */ +#define PWM_CMUPD2_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD2) Channel Polarity Inversion Update */ +/* -------- PWM_ETRG2 : (PWM Offset: 0x44C) PWM External Trigger Register (trg_num = 2) -------- */ +#define PWM_ETRG2_MAXCNT_Pos 0 +#define PWM_ETRG2_MAXCNT_Msk (0xffffffu << PWM_ETRG2_MAXCNT_Pos) /**< \brief (PWM_ETRG2) Maximum Counter value */ +#define PWM_ETRG2_MAXCNT(value) ((PWM_ETRG2_MAXCNT_Msk & ((value) << PWM_ETRG2_MAXCNT_Pos))) +#define PWM_ETRG2_TRGMODE_Pos 24 +#define PWM_ETRG2_TRGMODE_Msk (0x3u << PWM_ETRG2_TRGMODE_Pos) /**< \brief (PWM_ETRG2) External Trigger Mode */ +#define PWM_ETRG2_TRGMODE(value) ((PWM_ETRG2_TRGMODE_Msk & ((value) << PWM_ETRG2_TRGMODE_Pos))) +#define PWM_ETRG2_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG2) External trigger is not enabled. */ +#define PWM_ETRG2_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG2) External PWM Reset Mode */ +#define PWM_ETRG2_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG2) External PWM Start Mode */ +#define PWM_ETRG2_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG2) Cycle-by-cycle Duty Mode */ +#define PWM_ETRG2_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG2) Edge Selection */ +#define PWM_ETRG2_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */ +#define PWM_ETRG2_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */ +#define PWM_ETRG2_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG2) Filtered input */ +#define PWM_ETRG2_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG2) Trigger Source */ +#define PWM_ETRG2_RFEN (0x1u << 31) /**< \brief (PWM_ETRG2) Recoverable Fault Enable */ +/* -------- PWM_LEBR2 : (PWM Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2) -------- */ +#define PWM_LEBR2_LEBDELAY_Pos 0 +#define PWM_LEBR2_LEBDELAY_Msk (0x7fu << PWM_LEBR2_LEBDELAY_Pos) /**< \brief (PWM_LEBR2) Leading-Edge Blanking Delay for TRGINx */ +#define PWM_LEBR2_LEBDELAY(value) ((PWM_LEBR2_LEBDELAY_Msk & ((value) << PWM_LEBR2_LEBDELAY_Pos))) +#define PWM_LEBR2_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR2) PWML Falling Edge Enable */ +#define PWM_LEBR2_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR2) PWML Rising Edge Enable */ +#define PWM_LEBR2_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR2) PWMH Falling Edge Enable */ +#define PWM_LEBR2_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR2) PWMH Rising Edge Enable */ +/* -------- PWM_CMUPD3 : (PWM Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) -------- */ +#define PWM_CMUPD3_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD3) Channel Polarity Update */ +#define PWM_CMUPD3_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD3) Channel Polarity Inversion Update */ +/* -------- PWM_ETRG3 : (PWM Offset: 0x46C) PWM External Trigger Register (trg_num = 3) -------- */ +#define PWM_ETRG3_MAXCNT_Pos 0 +#define PWM_ETRG3_MAXCNT_Msk (0xffffffu << PWM_ETRG3_MAXCNT_Pos) /**< \brief (PWM_ETRG3) Maximum Counter value */ +#define PWM_ETRG3_MAXCNT(value) ((PWM_ETRG3_MAXCNT_Msk & ((value) << PWM_ETRG3_MAXCNT_Pos))) +#define PWM_ETRG3_TRGMODE_Pos 24 +#define PWM_ETRG3_TRGMODE_Msk (0x3u << PWM_ETRG3_TRGMODE_Pos) /**< \brief (PWM_ETRG3) External Trigger Mode */ +#define PWM_ETRG3_TRGMODE(value) ((PWM_ETRG3_TRGMODE_Msk & ((value) << PWM_ETRG3_TRGMODE_Pos))) +#define PWM_ETRG3_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG3) External trigger is not enabled. */ +#define PWM_ETRG3_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG3) External PWM Reset Mode */ +#define PWM_ETRG3_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG3) External PWM Start Mode */ +#define PWM_ETRG3_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG3) Cycle-by-cycle Duty Mode */ +#define PWM_ETRG3_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG3) Edge Selection */ +#define PWM_ETRG3_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG3) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */ +#define PWM_ETRG3_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG3) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */ +#define PWM_ETRG3_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG3) Filtered input */ +#define PWM_ETRG3_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG3) Trigger Source */ +#define PWM_ETRG3_RFEN (0x1u << 31) /**< \brief (PWM_ETRG3) Recoverable Fault Enable */ +/* -------- PWM_LEBR3 : (PWM Offset: 0x470) PWM Leading-Edge Blanking Register (trg_num = 3) -------- */ +#define PWM_LEBR3_LEBDELAY_Pos 0 +#define PWM_LEBR3_LEBDELAY_Msk (0x7fu << PWM_LEBR3_LEBDELAY_Pos) /**< \brief (PWM_LEBR3) Leading-Edge Blanking Delay for TRGINx */ +#define PWM_LEBR3_LEBDELAY(value) ((PWM_LEBR3_LEBDELAY_Msk & ((value) << PWM_LEBR3_LEBDELAY_Pos))) +#define PWM_LEBR3_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR3) PWML Falling Edge Enable */ +#define PWM_LEBR3_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR3) PWML Rising Edge Enable */ +#define PWM_LEBR3_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR3) PWMH Falling Edge Enable */ +#define PWM_LEBR3_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR3) PWMH Rising Edge Enable */ +/* -------- PWM_ETRG4 : (PWM Offset: 0x48C) PWM External Trigger Register (trg_num = 4) -------- */ +#define PWM_ETRG4_MAXCNT_Pos 0 +#define PWM_ETRG4_MAXCNT_Msk (0xffffffu << PWM_ETRG4_MAXCNT_Pos) /**< \brief (PWM_ETRG4) Maximum Counter value */ +#define PWM_ETRG4_MAXCNT(value) ((PWM_ETRG4_MAXCNT_Msk & ((value) << PWM_ETRG4_MAXCNT_Pos))) +#define PWM_ETRG4_TRGMODE_Pos 24 +#define PWM_ETRG4_TRGMODE_Msk (0x3u << PWM_ETRG4_TRGMODE_Pos) /**< \brief (PWM_ETRG4) External Trigger Mode */ +#define PWM_ETRG4_TRGMODE(value) ((PWM_ETRG4_TRGMODE_Msk & ((value) << PWM_ETRG4_TRGMODE_Pos))) +#define PWM_ETRG4_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG4) External trigger is not enabled. */ +#define PWM_ETRG4_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG4) External PWM Reset Mode */ +#define PWM_ETRG4_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG4) External PWM Start Mode */ +#define PWM_ETRG4_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG4) Cycle-by-cycle Duty Mode */ +#define PWM_ETRG4_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG4) Edge Selection */ +#define PWM_ETRG4_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG4) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */ +#define PWM_ETRG4_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG4) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */ +#define PWM_ETRG4_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG4) Filtered input */ +#define PWM_ETRG4_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG4) Trigger Source */ +#define PWM_ETRG4_RFEN (0x1u << 31) /**< \brief (PWM_ETRG4) Recoverable Fault Enable */ +/* -------- PWM_LEBR4 : (PWM Offset: 0x490) PWM Leading-Edge Blanking Register (trg_num = 4) -------- */ +#define PWM_LEBR4_LEBDELAY_Pos 0 +#define PWM_LEBR4_LEBDELAY_Msk (0x7fu << PWM_LEBR4_LEBDELAY_Pos) /**< \brief (PWM_LEBR4) Leading-Edge Blanking Delay for TRGINx */ +#define PWM_LEBR4_LEBDELAY(value) ((PWM_LEBR4_LEBDELAY_Msk & ((value) << PWM_LEBR4_LEBDELAY_Pos))) +#define PWM_LEBR4_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR4) PWML Falling Edge Enable */ +#define PWM_LEBR4_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR4) PWML Rising Edge Enable */ +#define PWM_LEBR4_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR4) PWMH Falling Edge Enable */ +#define PWM_LEBR4_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR4) PWMH Rising Edge Enable */ + +/*@}*/ + + +#endif /* _SAMV71_PWM_COMPONENT_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_qspi.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_qspi.h new file mode 100644 index 00000000..5644fc47 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_qspi.h @@ -0,0 +1,223 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_QSPI_COMPONENT_ +#define _SAMV71_QSPI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Quad Serial Peripheral Interface */ +/* ============================================================================= */ +/** \addtogroup SAMV71_QSPI Quad Serial Peripheral Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Qspi hardware registers */ +typedef struct { + __O uint32_t QSPI_CR; /**< \brief (Qspi Offset: 0x00) Control Register */ + __IO uint32_t QSPI_MR; /**< \brief (Qspi Offset: 0x04) Mode Register */ + __I uint32_t QSPI_RDR; /**< \brief (Qspi Offset: 0x08) Receive Data Register */ + __O uint32_t QSPI_TDR; /**< \brief (Qspi Offset: 0x0C) Transmit Data Register */ + __I uint32_t QSPI_SR; /**< \brief (Qspi Offset: 0x10) Status Register */ + __O uint32_t QSPI_IER; /**< \brief (Qspi Offset: 0x14) Interrupt Enable Register */ + __O uint32_t QSPI_IDR; /**< \brief (Qspi Offset: 0x18) Interrupt Disable Register */ + __I uint32_t QSPI_IMR; /**< \brief (Qspi Offset: 0x1C) Interrupt Mask Register */ + __IO uint32_t QSPI_SCR; /**< \brief (Qspi Offset: 0x20) Serial Clock Register */ + __I uint32_t Reserved1[3]; + __IO uint32_t QSPI_IAR; /**< \brief (Qspi Offset: 0x30) Instruction Address Register */ + __IO uint32_t QSPI_ICR; /**< \brief (Qspi Offset: 0x34) Instruction Code Register */ + __IO uint32_t QSPI_IFR; /**< \brief (Qspi Offset: 0x38) Instruction Frame Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t QSPI_SMR; /**< \brief (Qspi Offset: 0x40) Scrambling Mode Register */ + __O uint32_t QSPI_SKR; /**< \brief (Qspi Offset: 0x44) Scrambling Key Register */ + __I uint32_t Reserved3[39]; + __IO uint32_t QSPI_WPMR; /**< \brief (Qspi Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t QSPI_WPSR; /**< \brief (Qspi Offset: 0xE8) Write Protection Status Register */ +} Qspi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- QSPI_CR : (QSPI Offset: 0x00) Control Register -------- */ +#define QSPI_CR_QSPIEN (0x1u << 0) /**< \brief (QSPI_CR) QSPI Enable */ +#define QSPI_CR_QSPIDIS (0x1u << 1) /**< \brief (QSPI_CR) QSPI Disable */ +#define QSPI_CR_SWRST (0x1u << 7) /**< \brief (QSPI_CR) QSPI Software Reset */ +#define QSPI_CR_LASTXFER (0x1u << 24) /**< \brief (QSPI_CR) Last Transfer */ +/* -------- QSPI_MR : (QSPI Offset: 0x04) Mode Register -------- */ +#define QSPI_MR_SMM (0x1u << 0) /**< \brief (QSPI_MR) Serial Memory Mode */ +#define QSPI_MR_SMM_SPI (0x0u << 0) /**< \brief (QSPI_MR) The QSPI is in SPI mode. */ +#define QSPI_MR_SMM_MEMORY (0x1u << 0) /**< \brief (QSPI_MR) The QSPI is in Serial Memory mode. */ +#define QSPI_MR_LLB (0x1u << 1) /**< \brief (QSPI_MR) Local Loopback Enable */ +#define QSPI_MR_LLB_DISABLED (0x0u << 1) /**< \brief (QSPI_MR) Local loopback path disabled. */ +#define QSPI_MR_LLB_ENABLED (0x1u << 1) /**< \brief (QSPI_MR) Local loopback path enabled. */ +#define QSPI_MR_WDRBT (0x1u << 2) /**< \brief (QSPI_MR) Wait Data Read Before Transfer */ +#define QSPI_MR_WDRBT_DISABLED (0x0u << 2) /**< \brief (QSPI_MR) No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is. */ +#define QSPI_MR_WDRBT_ENABLED (0x1u << 2) /**< \brief (QSPI_MR) In SPI mode, a transfer can start only if the QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception. */ +#define QSPI_MR_CSMODE_Pos 4 +#define QSPI_MR_CSMODE_Msk (0x3u << QSPI_MR_CSMODE_Pos) /**< \brief (QSPI_MR) Chip Select Mode */ +#define QSPI_MR_CSMODE(value) ((QSPI_MR_CSMODE_Msk & ((value) << QSPI_MR_CSMODE_Pos))) +#define QSPI_MR_CSMODE_NOT_RELOADED (0x0u << 4) /**< \brief (QSPI_MR) The chip select is deasserted if TD has not been reloaded before the end of the current transfer. */ +#define QSPI_MR_CSMODE_LASTXFER (0x1u << 4) /**< \brief (QSPI_MR) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred. */ +#define QSPI_MR_CSMODE_SYSTEMATICALLY (0x2u << 4) /**< \brief (QSPI_MR) The chip select is deasserted systematically after each transfer. */ +#define QSPI_MR_NBBITS_Pos 8 +#define QSPI_MR_NBBITS_Msk (0xfu << QSPI_MR_NBBITS_Pos) /**< \brief (QSPI_MR) Number Of Bits Per Transfer */ +#define QSPI_MR_NBBITS(value) ((QSPI_MR_NBBITS_Msk & ((value) << QSPI_MR_NBBITS_Pos))) +#define QSPI_MR_NBBITS_8_BIT (0x0u << 8) /**< \brief (QSPI_MR) 8 bits for transfer */ +#define QSPI_MR_NBBITS_9_BIT (0x1u << 8) /**< \brief (QSPI_MR) 9 bits for transfer */ +#define QSPI_MR_NBBITS_10_BIT (0x2u << 8) /**< \brief (QSPI_MR) 10 bits for transfer */ +#define QSPI_MR_NBBITS_11_BIT (0x3u << 8) /**< \brief (QSPI_MR) 11 bits for transfer */ +#define QSPI_MR_NBBITS_12_BIT (0x4u << 8) /**< \brief (QSPI_MR) 12 bits for transfer */ +#define QSPI_MR_NBBITS_13_BIT (0x5u << 8) /**< \brief (QSPI_MR) 13 bits for transfer */ +#define QSPI_MR_NBBITS_14_BIT (0x6u << 8) /**< \brief (QSPI_MR) 14 bits for transfer */ +#define QSPI_MR_NBBITS_15_BIT (0x7u << 8) /**< \brief (QSPI_MR) 15 bits for transfer */ +#define QSPI_MR_NBBITS_16_BIT (0x8u << 8) /**< \brief (QSPI_MR) 16 bits for transfer */ +#define QSPI_MR_DLYBCT_Pos 16 +#define QSPI_MR_DLYBCT_Msk (0xffu << QSPI_MR_DLYBCT_Pos) /**< \brief (QSPI_MR) Delay Between Consecutive Transfers */ +#define QSPI_MR_DLYBCT(value) ((QSPI_MR_DLYBCT_Msk & ((value) << QSPI_MR_DLYBCT_Pos))) +#define QSPI_MR_DLYCS_Pos 24 +#define QSPI_MR_DLYCS_Msk (0xffu << QSPI_MR_DLYCS_Pos) /**< \brief (QSPI_MR) Minimum Inactive QCS Delay */ +#define QSPI_MR_DLYCS(value) ((QSPI_MR_DLYCS_Msk & ((value) << QSPI_MR_DLYCS_Pos))) +/* -------- QSPI_RDR : (QSPI Offset: 0x08) Receive Data Register -------- */ +#define QSPI_RDR_RD_Pos 0 +#define QSPI_RDR_RD_Msk (0xffffu << QSPI_RDR_RD_Pos) /**< \brief (QSPI_RDR) Receive Data */ +/* -------- QSPI_TDR : (QSPI Offset: 0x0C) Transmit Data Register -------- */ +#define QSPI_TDR_TD_Pos 0 +#define QSPI_TDR_TD_Msk (0xffffu << QSPI_TDR_TD_Pos) /**< \brief (QSPI_TDR) Transmit Data */ +#define QSPI_TDR_TD(value) ((QSPI_TDR_TD_Msk & ((value) << QSPI_TDR_TD_Pos))) +/* -------- QSPI_SR : (QSPI Offset: 0x10) Status Register -------- */ +#define QSPI_SR_RDRF (0x1u << 0) /**< \brief (QSPI_SR) Receive Data Register Full */ +#define QSPI_SR_TDRE (0x1u << 1) /**< \brief (QSPI_SR) Transmit Data Register Empty */ +#define QSPI_SR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_SR) Transmission Registers Empty */ +#define QSPI_SR_OVRES (0x1u << 3) /**< \brief (QSPI_SR) Overrun Error Status */ +#define QSPI_SR_CSR (0x1u << 8) /**< \brief (QSPI_SR) Chip Select Rise */ +#define QSPI_SR_CSS (0x1u << 9) /**< \brief (QSPI_SR) Chip Select Status */ +#define QSPI_SR_INSTRE (0x1u << 10) /**< \brief (QSPI_SR) Instruction End Status */ +#define QSPI_SR_QSPIENS (0x1u << 24) /**< \brief (QSPI_SR) QSPI Enable Status */ +/* -------- QSPI_IER : (QSPI Offset: 0x14) Interrupt Enable Register -------- */ +#define QSPI_IER_RDRF (0x1u << 0) /**< \brief (QSPI_IER) Receive Data Register Full Interrupt Enable */ +#define QSPI_IER_TDRE (0x1u << 1) /**< \brief (QSPI_IER) Transmit Data Register Empty Interrupt Enable */ +#define QSPI_IER_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IER) Transmission Registers Empty Enable */ +#define QSPI_IER_OVRES (0x1u << 3) /**< \brief (QSPI_IER) Overrun Error Interrupt Enable */ +#define QSPI_IER_CSR (0x1u << 8) /**< \brief (QSPI_IER) Chip Select Rise Interrupt Enable */ +#define QSPI_IER_CSS (0x1u << 9) /**< \brief (QSPI_IER) Chip Select Status Interrupt Enable */ +#define QSPI_IER_INSTRE (0x1u << 10) /**< \brief (QSPI_IER) Instruction End Interrupt Enable */ +/* -------- QSPI_IDR : (QSPI Offset: 0x18) Interrupt Disable Register -------- */ +#define QSPI_IDR_RDRF (0x1u << 0) /**< \brief (QSPI_IDR) Receive Data Register Full Interrupt Disable */ +#define QSPI_IDR_TDRE (0x1u << 1) /**< \brief (QSPI_IDR) Transmit Data Register Empty Interrupt Disable */ +#define QSPI_IDR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IDR) Transmission Registers Empty Disable */ +#define QSPI_IDR_OVRES (0x1u << 3) /**< \brief (QSPI_IDR) Overrun Error Interrupt Disable */ +#define QSPI_IDR_CSR (0x1u << 8) /**< \brief (QSPI_IDR) Chip Select Rise Interrupt Disable */ +#define QSPI_IDR_CSS (0x1u << 9) /**< \brief (QSPI_IDR) Chip Select Status Interrupt Disable */ +#define QSPI_IDR_INSTRE (0x1u << 10) /**< \brief (QSPI_IDR) Instruction End Interrupt Disable */ +/* -------- QSPI_IMR : (QSPI Offset: 0x1C) Interrupt Mask Register -------- */ +#define QSPI_IMR_RDRF (0x1u << 0) /**< \brief (QSPI_IMR) Receive Data Register Full Interrupt Mask */ +#define QSPI_IMR_TDRE (0x1u << 1) /**< \brief (QSPI_IMR) Transmit Data Register Empty Interrupt Mask */ +#define QSPI_IMR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IMR) Transmission Registers Empty Mask */ +#define QSPI_IMR_OVRES (0x1u << 3) /**< \brief (QSPI_IMR) Overrun Error Interrupt Mask */ +#define QSPI_IMR_CSR (0x1u << 8) /**< \brief (QSPI_IMR) Chip Select Rise Interrupt Mask */ +#define QSPI_IMR_CSS (0x1u << 9) /**< \brief (QSPI_IMR) Chip Select Status Interrupt Mask */ +#define QSPI_IMR_INSTRE (0x1u << 10) /**< \brief (QSPI_IMR) Instruction End Interrupt Mask */ +/* -------- QSPI_SCR : (QSPI Offset: 0x20) Serial Clock Register -------- */ +#define QSPI_SCR_CPOL (0x1u << 0) /**< \brief (QSPI_SCR) Clock Polarity */ +#define QSPI_SCR_CPHA (0x1u << 1) /**< \brief (QSPI_SCR) Clock Phase */ +#define QSPI_SCR_SCBR_Pos 8 +#define QSPI_SCR_SCBR_Msk (0xffu << QSPI_SCR_SCBR_Pos) /**< \brief (QSPI_SCR) Serial Clock Baud Rate */ +#define QSPI_SCR_SCBR(value) ((QSPI_SCR_SCBR_Msk & ((value) << QSPI_SCR_SCBR_Pos))) +#define QSPI_SCR_DLYBS_Pos 16 +#define QSPI_SCR_DLYBS_Msk (0xffu << QSPI_SCR_DLYBS_Pos) /**< \brief (QSPI_SCR) Delay Before QSCK */ +#define QSPI_SCR_DLYBS(value) ((QSPI_SCR_DLYBS_Msk & ((value) << QSPI_SCR_DLYBS_Pos))) +/* -------- QSPI_IAR : (QSPI Offset: 0x30) Instruction Address Register -------- */ +#define QSPI_IAR_ADDR_Pos 0 +#define QSPI_IAR_ADDR_Msk (0xffffffffu << QSPI_IAR_ADDR_Pos) /**< \brief (QSPI_IAR) Address */ +#define QSPI_IAR_ADDR(value) ((QSPI_IAR_ADDR_Msk & ((value) << QSPI_IAR_ADDR_Pos))) +/* -------- QSPI_ICR : (QSPI Offset: 0x34) Instruction Code Register -------- */ +#define QSPI_ICR_INST_Pos 0 +#define QSPI_ICR_INST_Msk (0xffu << QSPI_ICR_INST_Pos) /**< \brief (QSPI_ICR) Instruction Code */ +#define QSPI_ICR_INST(value) ((QSPI_ICR_INST_Msk & ((value) << QSPI_ICR_INST_Pos))) +#define QSPI_ICR_OPT_Pos 16 +#define QSPI_ICR_OPT_Msk (0xffu << QSPI_ICR_OPT_Pos) /**< \brief (QSPI_ICR) Option Code */ +#define QSPI_ICR_OPT(value) ((QSPI_ICR_OPT_Msk & ((value) << QSPI_ICR_OPT_Pos))) +/* -------- QSPI_IFR : (QSPI Offset: 0x38) Instruction Frame Register -------- */ +#define QSPI_IFR_WIDTH_Pos 0 +#define QSPI_IFR_WIDTH_Msk (0x7u << QSPI_IFR_WIDTH_Pos) /**< \brief (QSPI_IFR) Width of Instruction Code, Address, Option Code and Data */ +#define QSPI_IFR_WIDTH(value) ((QSPI_IFR_WIDTH_Msk & ((value) << QSPI_IFR_WIDTH_Pos))) +#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0x0u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI */ +#define QSPI_IFR_WIDTH_DUAL_OUTPUT (0x1u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_OUTPUT (0x2u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI */ +#define QSPI_IFR_WIDTH_DUAL_IO (0x3u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_IO (0x4u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI */ +#define QSPI_IFR_WIDTH_DUAL_CMD (0x5u << 0) /**< \brief (QSPI_IFR) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_CMD (0x6u << 0) /**< \brief (QSPI_IFR) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI */ +#define QSPI_IFR_INSTEN (0x1u << 4) /**< \brief (QSPI_IFR) Instruction Enable */ +#define QSPI_IFR_ADDREN (0x1u << 5) /**< \brief (QSPI_IFR) Address Enable */ +#define QSPI_IFR_OPTEN (0x1u << 6) /**< \brief (QSPI_IFR) Option Enable */ +#define QSPI_IFR_DATAEN (0x1u << 7) /**< \brief (QSPI_IFR) Data Enable */ +#define QSPI_IFR_OPTL_Pos 8 +#define QSPI_IFR_OPTL_Msk (0x3u << QSPI_IFR_OPTL_Pos) /**< \brief (QSPI_IFR) Option Code Length */ +#define QSPI_IFR_OPTL(value) ((QSPI_IFR_OPTL_Msk & ((value) << QSPI_IFR_OPTL_Pos))) +#define QSPI_IFR_OPTL_OPTION_1BIT (0x0u << 8) /**< \brief (QSPI_IFR) The option code is 1 bit long. */ +#define QSPI_IFR_OPTL_OPTION_2BIT (0x1u << 8) /**< \brief (QSPI_IFR) The option code is 2 bits long. */ +#define QSPI_IFR_OPTL_OPTION_4BIT (0x2u << 8) /**< \brief (QSPI_IFR) The option code is 4 bits long. */ +#define QSPI_IFR_OPTL_OPTION_8BIT (0x3u << 8) /**< \brief (QSPI_IFR) The option code is 8 bits long. */ +#define QSPI_IFR_ADDRL (0x1u << 10) /**< \brief (QSPI_IFR) Address Length */ +#define QSPI_IFR_ADDRL_24_BIT (0x0u << 10) /**< \brief (QSPI_IFR) The address is 24 bits long. */ +#define QSPI_IFR_ADDRL_32_BIT (0x1u << 10) /**< \brief (QSPI_IFR) The address is 32 bits long. */ +#define QSPI_IFR_TFRTYP_Pos 12 +#define QSPI_IFR_TFRTYP_Msk (0x3u << QSPI_IFR_TFRTYP_Pos) /**< \brief (QSPI_IFR) Data Transfer Type */ +#define QSPI_IFR_TFRTYP(value) ((QSPI_IFR_TFRTYP_Msk & ((value) << QSPI_IFR_TFRTYP_Pos))) +#define QSPI_IFR_TFRTYP_TRSFR_READ (0x0u << 12) /**< \brief (QSPI_IFR) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial Flash memory is not possible. */ +#define QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY (0x1u << 12) /**< \brief (QSPI_IFR) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial Flash memory is possible. */ +#define QSPI_IFR_TFRTYP_TRSFR_WRITE (0x2u << 12) /**< \brief (QSPI_IFR) Write transfer into the serial memory.Scrambling is not performed. */ +#define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY (0x3u << 12) /**< \brief (QSPI_IFR) Write data transfer into the serial memory.If enabled, scrambling is performed. */ +#define QSPI_IFR_CRM (0x1u << 14) /**< \brief (QSPI_IFR) Continuous Read Mode */ +#define QSPI_IFR_CRM_DISABLED (0x0u << 14) /**< \brief (QSPI_IFR) The Continuous Read mode is disabled. */ +#define QSPI_IFR_CRM_ENABLED (0x1u << 14) /**< \brief (QSPI_IFR) The Continuous Read mode is enabled. */ +#define QSPI_IFR_NBDUM_Pos 16 +#define QSPI_IFR_NBDUM_Msk (0x1fu << QSPI_IFR_NBDUM_Pos) /**< \brief (QSPI_IFR) Number Of Dummy Cycles */ +#define QSPI_IFR_NBDUM(value) ((QSPI_IFR_NBDUM_Msk & ((value) << QSPI_IFR_NBDUM_Pos))) +/* -------- QSPI_SMR : (QSPI Offset: 0x40) Scrambling Mode Register -------- */ +#define QSPI_SMR_SCREN (0x1u << 0) /**< \brief (QSPI_SMR) Scrambling/Unscrambling Enable */ +#define QSPI_SMR_SCREN_DISABLED (0x0u << 0) /**< \brief (QSPI_SMR) The scrambling/unscrambling is disabled. */ +#define QSPI_SMR_SCREN_ENABLED (0x1u << 0) /**< \brief (QSPI_SMR) The scrambling/unscrambling is enabled. */ +#define QSPI_SMR_RVDIS (0x1u << 1) /**< \brief (QSPI_SMR) Scrambling/Unscrambling Random Value Disable */ +/* -------- QSPI_SKR : (QSPI Offset: 0x44) Scrambling Key Register -------- */ +#define QSPI_SKR_USRK_Pos 0 +#define QSPI_SKR_USRK_Msk (0xffffffffu << QSPI_SKR_USRK_Pos) /**< \brief (QSPI_SKR) Scrambling User Key */ +#define QSPI_SKR_USRK(value) ((QSPI_SKR_USRK_Msk & ((value) << QSPI_SKR_USRK_Pos))) +/* -------- QSPI_WPMR : (QSPI Offset: 0xE4) Write Protection Mode Register -------- */ +#define QSPI_WPMR_WPEN (0x1u << 0) /**< \brief (QSPI_WPMR) Write Protection Enable */ +#define QSPI_WPMR_WPKEY_Pos 8 +#define QSPI_WPMR_WPKEY_Msk (0xffffffu << QSPI_WPMR_WPKEY_Pos) /**< \brief (QSPI_WPMR) Write Protection Key */ +#define QSPI_WPMR_WPKEY(value) ((QSPI_WPMR_WPKEY_Msk & ((value) << QSPI_WPMR_WPKEY_Pos))) +#define QSPI_WPMR_WPKEY_PASSWD (0x515350u << 8) /**< \brief (QSPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- QSPI_WPSR : (QSPI Offset: 0xE8) Write Protection Status Register -------- */ +#define QSPI_WPSR_WPVS (0x1u << 0) /**< \brief (QSPI_WPSR) Write Protection Violation Status */ +#define QSPI_WPSR_WPVSRC_Pos 8 +#define QSPI_WPSR_WPVSRC_Msk (0xffu << QSPI_WPSR_WPVSRC_Pos) /**< \brief (QSPI_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAMV71_QSPI_COMPONENT_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_rstc.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_rstc.h new file mode 100644 index 00000000..29e113a7 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_rstc.h @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_RSTC_COMPONENT_ +#define _SAMV71_RSTC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Reset Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_RSTC Reset Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rstc hardware registers */ +typedef struct { + __O uint32_t RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */ + __I uint32_t RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */ + __IO uint32_t RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */ +} Rstc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */ +#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */ +#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */ +#define RSTC_CR_KEY_Pos 24 +#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) System Reset Key */ +#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos))) +#define RSTC_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_CR) Writing any other value in this field aborts the write operation. */ +/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */ +#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */ +#define RSTC_SR_RSTTYP_Pos 8 +#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */ +#define RSTC_SR_RSTTYP_GENERAL_RST (0x0u << 8) /**< \brief (RSTC_SR) First power-up reset */ +#define RSTC_SR_RSTTYP_BACKUP_RST (0x1u << 8) /**< \brief (RSTC_SR) Return from Backup Mode */ +#define RSTC_SR_RSTTYP_WDT_RST (0x2u << 8) /**< \brief (RSTC_SR) Watchdog fault occurred */ +#define RSTC_SR_RSTTYP_SOFT_RST (0x3u << 8) /**< \brief (RSTC_SR) Processor reset required by the software */ +#define RSTC_SR_RSTTYP_USER_RST (0x4u << 8) /**< \brief (RSTC_SR) NRST pin detected low */ +#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */ +#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */ +/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */ +#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */ +#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */ +#define RSTC_MR_ERSTL_Pos 8 +#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */ +#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos))) +#define RSTC_MR_KEY_Pos 24 +#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Write Access Password */ +#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos))) +#define RSTC_MR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_MR) Writing any other value in this field aborts the write operation.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAMV71_RSTC_COMPONENT_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_rswdt.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_rswdt.h new file mode 100644 index 00000000..c455a0fe --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_rswdt.h @@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_RSWDT_COMPONENT_ +#define _SAMV71_RSWDT_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Reinforced Safety Watchdog Timer */ +/* ============================================================================= */ +/** \addtogroup SAMV71_RSWDT Reinforced Safety Watchdog Timer */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rswdt hardware registers */ +typedef struct { + __O uint32_t RSWDT_CR; /**< \brief (Rswdt Offset: 0x00) Control Register */ + __IO uint32_t RSWDT_MR; /**< \brief (Rswdt Offset: 0x04) Mode Register */ + __I uint32_t RSWDT_SR; /**< \brief (Rswdt Offset: 0x08) Status Register */ +} Rswdt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RSWDT_CR : (RSWDT Offset: 0x00) Control Register -------- */ +#define RSWDT_CR_WDRSTT (0x1u << 0) /**< \brief (RSWDT_CR) Watchdog Restart */ +#define RSWDT_CR_KEY_Pos 24 +#define RSWDT_CR_KEY_Msk (0xffu << RSWDT_CR_KEY_Pos) /**< \brief (RSWDT_CR) Password */ +#define RSWDT_CR_KEY(value) ((RSWDT_CR_KEY_Msk & ((value) << RSWDT_CR_KEY_Pos))) +#define RSWDT_CR_KEY_PASSWD (0xC4u << 24) /**< \brief (RSWDT_CR) Writing any other value in this field aborts the write operation. */ +/* -------- RSWDT_MR : (RSWDT Offset: 0x04) Mode Register -------- */ +#define RSWDT_MR_WDV_Pos 0 +#define RSWDT_MR_WDV_Msk (0xfffu << RSWDT_MR_WDV_Pos) /**< \brief (RSWDT_MR) Watchdog Counter Value */ +#define RSWDT_MR_WDV(value) ((RSWDT_MR_WDV_Msk & ((value) << RSWDT_MR_WDV_Pos))) +#define RSWDT_MR_WDFIEN (0x1u << 12) /**< \brief (RSWDT_MR) Watchdog Fault Interrupt Enable */ +#define RSWDT_MR_WDRSTEN (0x1u << 13) /**< \brief (RSWDT_MR) Watchdog Reset Enable */ +#define RSWDT_MR_WDRPROC (0x1u << 14) /**< \brief (RSWDT_MR) Watchdog Reset Processor */ +#define RSWDT_MR_WDDIS (0x1u << 15) /**< \brief (RSWDT_MR) Watchdog Disable */ +#define RSWDT_MR_ALLONES_Pos 16 +#define RSWDT_MR_ALLONES_Msk (0xfffu << RSWDT_MR_ALLONES_Pos) /**< \brief (RSWDT_MR) Must Always Be Written with 0xFFF */ +#define RSWDT_MR_ALLONES(value) ((RSWDT_MR_ALLONES_Msk & ((value) << RSWDT_MR_ALLONES_Pos))) +#define RSWDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (RSWDT_MR) Watchdog Debug Halt */ +#define RSWDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (RSWDT_MR) Watchdog Idle Halt */ +/* -------- RSWDT_SR : (RSWDT Offset: 0x08) Status Register -------- */ +#define RSWDT_SR_WDUNF (0x1u << 0) /**< \brief (RSWDT_SR) Watchdog Underflow */ + +/*@}*/ + + +#endif /* _SAMV71_RSWDT_COMPONENT_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_rtc.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_rtc.h new file mode 100644 index 00000000..ccc26e66 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_rtc.h @@ -0,0 +1,226 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_RTC_COMPONENT_ +#define _SAMV71_RTC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Real-time Clock */ +/* ============================================================================= */ +/** \addtogroup SAMV71_RTC Real-time Clock */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rtc hardware registers */ +typedef struct { + __IO uint32_t RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */ + __IO uint32_t RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */ + __IO uint32_t RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */ + __IO uint32_t RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */ + __IO uint32_t RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */ + __IO uint32_t RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */ + __I uint32_t RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */ + __O uint32_t RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */ + __O uint32_t RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */ + __O uint32_t RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */ + __I uint32_t RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */ + __I uint32_t RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */ +} Rtc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */ +#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */ +#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */ +#define RTC_CR_TIMEVSEL_Pos 8 +#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */ +#define RTC_CR_TIMEVSEL(value) ((RTC_CR_TIMEVSEL_Msk & ((value) << RTC_CR_TIMEVSEL_Pos))) +#define RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */ +#define RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */ +#define RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */ +#define RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */ +#define RTC_CR_CALEVSEL_Pos 16 +#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */ +#define RTC_CR_CALEVSEL(value) ((RTC_CR_CALEVSEL_Msk & ((value) << RTC_CR_CALEVSEL_Pos))) +#define RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */ +#define RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */ +#define RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */ +/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */ +#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */ +#define RTC_MR_PERSIAN (0x1u << 1) /**< \brief (RTC_MR) PERSIAN Calendar */ +#define RTC_MR_NEGPPM (0x1u << 4) /**< \brief (RTC_MR) NEGative PPM Correction */ +#define RTC_MR_CORRECTION_Pos 8 +#define RTC_MR_CORRECTION_Msk (0x7fu << RTC_MR_CORRECTION_Pos) /**< \brief (RTC_MR) Slow Clock Correction */ +#define RTC_MR_CORRECTION(value) ((RTC_MR_CORRECTION_Msk & ((value) << RTC_MR_CORRECTION_Pos))) +#define RTC_MR_HIGHPPM (0x1u << 15) /**< \brief (RTC_MR) HIGH PPM Correction */ +#define RTC_MR_OUT0_Pos 16 +#define RTC_MR_OUT0_Msk (0x7u << RTC_MR_OUT0_Pos) /**< \brief (RTC_MR) RTCOUT0 OutputSource Selection */ +#define RTC_MR_OUT0(value) ((RTC_MR_OUT0_Msk & ((value) << RTC_MR_OUT0_Pos))) +#define RTC_MR_OUT0_NO_WAVE (0x0u << 16) /**< \brief (RTC_MR) No waveform, stuck at '0' */ +#define RTC_MR_OUT0_FREQ1HZ (0x1u << 16) /**< \brief (RTC_MR) 1 Hz square wave */ +#define RTC_MR_OUT0_FREQ32HZ (0x2u << 16) /**< \brief (RTC_MR) 32 Hz square wave */ +#define RTC_MR_OUT0_FREQ64HZ (0x3u << 16) /**< \brief (RTC_MR) 64 Hz square wave */ +#define RTC_MR_OUT0_FREQ512HZ (0x4u << 16) /**< \brief (RTC_MR) 512 Hz square wave */ +#define RTC_MR_OUT0_ALARM_TOGGLE (0x5u << 16) /**< \brief (RTC_MR) Output toggles when alarm flag rises */ +#define RTC_MR_OUT0_ALARM_FLAG (0x6u << 16) /**< \brief (RTC_MR) Output is a copy of the alarm flag */ +#define RTC_MR_OUT0_PROG_PULSE (0x7u << 16) /**< \brief (RTC_MR) Duty cycle programmable pulse */ +#define RTC_MR_OUT1_Pos 20 +#define RTC_MR_OUT1_Msk (0x7u << RTC_MR_OUT1_Pos) /**< \brief (RTC_MR) RTCOUT1 Output Source Selection */ +#define RTC_MR_OUT1(value) ((RTC_MR_OUT1_Msk & ((value) << RTC_MR_OUT1_Pos))) +#define RTC_MR_OUT1_NO_WAVE (0x0u << 20) /**< \brief (RTC_MR) No waveform, stuck at '0' */ +#define RTC_MR_OUT1_FREQ1HZ (0x1u << 20) /**< \brief (RTC_MR) 1 Hz square wave */ +#define RTC_MR_OUT1_FREQ32HZ (0x2u << 20) /**< \brief (RTC_MR) 32 Hz square wave */ +#define RTC_MR_OUT1_FREQ64HZ (0x3u << 20) /**< \brief (RTC_MR) 64 Hz square wave */ +#define RTC_MR_OUT1_FREQ512HZ (0x4u << 20) /**< \brief (RTC_MR) 512 Hz square wave */ +#define RTC_MR_OUT1_ALARM_TOGGLE (0x5u << 20) /**< \brief (RTC_MR) Output toggles when alarm flag rises */ +#define RTC_MR_OUT1_ALARM_FLAG (0x6u << 20) /**< \brief (RTC_MR) Output is a copy of the alarm flag */ +#define RTC_MR_OUT1_PROG_PULSE (0x7u << 20) /**< \brief (RTC_MR) Duty cycle programmable pulse */ +#define RTC_MR_THIGH_Pos 24 +#define RTC_MR_THIGH_Msk (0x7u << RTC_MR_THIGH_Pos) /**< \brief (RTC_MR) High Duration of the Output Pulse */ +#define RTC_MR_THIGH(value) ((RTC_MR_THIGH_Msk & ((value) << RTC_MR_THIGH_Pos))) +#define RTC_MR_THIGH_H_31MS (0x0u << 24) /**< \brief (RTC_MR) 31.2 ms */ +#define RTC_MR_THIGH_H_16MS (0x1u << 24) /**< \brief (RTC_MR) 15.6 ms */ +#define RTC_MR_THIGH_H_4MS (0x2u << 24) /**< \brief (RTC_MR) 3.91 ms */ +#define RTC_MR_THIGH_H_976US (0x3u << 24) /**< \brief (RTC_MR) 976 us */ +#define RTC_MR_THIGH_H_488US (0x4u << 24) /**< \brief (RTC_MR) 488 us */ +#define RTC_MR_THIGH_H_122US (0x5u << 24) /**< \brief (RTC_MR) 122 us */ +#define RTC_MR_THIGH_H_30US (0x6u << 24) /**< \brief (RTC_MR) 30.5 us */ +#define RTC_MR_THIGH_H_15US (0x7u << 24) /**< \brief (RTC_MR) 15.2 us */ +#define RTC_MR_TPERIOD_Pos 28 +#define RTC_MR_TPERIOD_Msk (0x3u << RTC_MR_TPERIOD_Pos) /**< \brief (RTC_MR) Period of the Output Pulse */ +#define RTC_MR_TPERIOD(value) ((RTC_MR_TPERIOD_Msk & ((value) << RTC_MR_TPERIOD_Pos))) +#define RTC_MR_TPERIOD_P_1S (0x0u << 28) /**< \brief (RTC_MR) 1 second */ +#define RTC_MR_TPERIOD_P_500MS (0x1u << 28) /**< \brief (RTC_MR) 500 ms */ +#define RTC_MR_TPERIOD_P_250MS (0x2u << 28) /**< \brief (RTC_MR) 250 ms */ +#define RTC_MR_TPERIOD_P_125MS (0x3u << 28) /**< \brief (RTC_MR) 125 ms */ +/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */ +#define RTC_TIMR_SEC_Pos 0 +#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */ +#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos))) +#define RTC_TIMR_MIN_Pos 8 +#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */ +#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos))) +#define RTC_TIMR_HOUR_Pos 16 +#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */ +#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos))) +#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */ +/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */ +#define RTC_CALR_CENT_Pos 0 +#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */ +#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos))) +#define RTC_CALR_YEAR_Pos 8 +#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */ +#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos))) +#define RTC_CALR_MONTH_Pos 16 +#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */ +#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos))) +#define RTC_CALR_DAY_Pos 21 +#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */ +#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos))) +#define RTC_CALR_DATE_Pos 24 +#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */ +#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos))) +/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */ +#define RTC_TIMALR_SEC_Pos 0 +#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */ +#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos))) +#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */ +#define RTC_TIMALR_MIN_Pos 8 +#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */ +#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos))) +#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */ +#define RTC_TIMALR_HOUR_Pos 16 +#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */ +#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos))) +#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */ +#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */ +/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */ +#define RTC_CALALR_MONTH_Pos 16 +#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */ +#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos))) +#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */ +#define RTC_CALALR_DATE_Pos 24 +#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */ +#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos))) +#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */ +/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */ +#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */ +#define RTC_SR_ACKUPD_FREERUN (0x0u << 0) /**< \brief (RTC_SR) Time and calendar registers cannot be updated. */ +#define RTC_SR_ACKUPD_UPDATE (0x1u << 0) /**< \brief (RTC_SR) Time and calendar registers can be updated. */ +#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */ +#define RTC_SR_ALARM_NO_ALARMEVENT (0x0u << 1) /**< \brief (RTC_SR) No alarm matching condition occurred. */ +#define RTC_SR_ALARM_ALARMEVENT (0x1u << 1) /**< \brief (RTC_SR) An alarm matching condition has occurred. */ +#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */ +#define RTC_SR_SEC_NO_SECEVENT (0x0u << 2) /**< \brief (RTC_SR) No second event has occurred since the last clear. */ +#define RTC_SR_SEC_SECEVENT (0x1u << 2) /**< \brief (RTC_SR) At least one second event has occurred since the last clear. */ +#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */ +#define RTC_SR_TIMEV_NO_TIMEVENT (0x0u << 3) /**< \brief (RTC_SR) No time event has occurred since the last clear. */ +#define RTC_SR_TIMEV_TIMEVENT (0x1u << 3) /**< \brief (RTC_SR) At least one time event has occurred since the last clear. */ +#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */ +#define RTC_SR_CALEV_NO_CALEVENT (0x0u << 4) /**< \brief (RTC_SR) No calendar event has occurred since the last clear. */ +#define RTC_SR_CALEV_CALEVENT (0x1u << 4) /**< \brief (RTC_SR) At least one calendar event has occurred since the last clear. */ +#define RTC_SR_TDERR (0x1u << 5) /**< \brief (RTC_SR) Time and/or Date Free Running Error */ +#define RTC_SR_TDERR_CORRECT (0x0u << 5) /**< \brief (RTC_SR) The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR). */ +#define RTC_SR_TDERR_ERR_TIMEDATE (0x1u << 5) /**< \brief (RTC_SR) The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. */ +/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */ +#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */ +#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */ +#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */ +#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */ +#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */ +#define RTC_SCCR_TDERRCLR (0x1u << 5) /**< \brief (RTC_SCCR) Time and/or Date Free Running Error Clear */ +/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */ +#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */ +#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */ +#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */ +#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */ +#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */ +#define RTC_IER_TDERREN (0x1u << 5) /**< \brief (RTC_IER) Time and/or Date Error Interrupt Enable */ +/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */ +#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */ +#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */ +#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */ +#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */ +#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */ +#define RTC_IDR_TDERRDIS (0x1u << 5) /**< \brief (RTC_IDR) Time and/or Date Error Interrupt Disable */ +/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */ +#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */ +#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */ +#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */ +#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */ +#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */ +#define RTC_IMR_TDERR (0x1u << 5) /**< \brief (RTC_IMR) Time and/or Date Error Mask */ +/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */ +#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */ +#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */ +#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */ +#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */ + +/*@}*/ + + +#endif /* _SAMV71_RTC_COMPONENT_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_rtt.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_rtt.h new file mode 100644 index 00000000..e208e1e0 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_rtt.h @@ -0,0 +1,71 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_RTT_COMPONENT_ +#define _SAMV71_RTT_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Real-time Timer */ +/* ============================================================================= */ +/** \addtogroup SAMV71_RTT Real-time Timer */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rtt hardware registers */ +typedef struct { + __IO uint32_t RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */ + __IO uint32_t RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */ + __I uint32_t RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */ + __I uint32_t RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */ +} Rtt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */ +#define RTT_MR_RTPRES_Pos 0 +#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */ +#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos))) +#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */ +#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */ +#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */ +#define RTT_MR_RTTDIS (0x1u << 20) /**< \brief (RTT_MR) Real-time Timer Disable */ +#define RTT_MR_RTC1HZ (0x1u << 24) /**< \brief (RTT_MR) Real-Time Clock 1Hz Clock Selection */ +/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */ +#define RTT_AR_ALMV_Pos 0 +#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */ +#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos))) +/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */ +#define RTT_VR_CRTV_Pos 0 +#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */ +/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */ +#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status (cleared on read) */ +#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Prescaler Roll-over Status (cleared on read) */ + +/*@}*/ + + +#endif /* _SAMV71_RTT_COMPONENT_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_sdramc.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_sdramc.h new file mode 100644 index 00000000..10ff9805 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_sdramc.h @@ -0,0 +1,173 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_SDRAMC_COMPONENT_ +#define _SAMV71_SDRAMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR SDRAM Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_SDRAMC SDRAM Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Sdramc hardware registers */ +typedef struct { + __IO uint32_t SDRAMC_MR; /**< \brief (Sdramc Offset: 0x00) SDRAMC Mode Register */ + __IO uint32_t SDRAMC_TR; /**< \brief (Sdramc Offset: 0x04) SDRAMC Refresh Timer Register */ + __IO uint32_t SDRAMC_CR; /**< \brief (Sdramc Offset: 0x08) SDRAMC Configuration Register */ + __I uint32_t Reserved1[1]; + __IO uint32_t SDRAMC_LPR; /**< \brief (Sdramc Offset: 0x10) SDRAMC Low Power Register */ + __O uint32_t SDRAMC_IER; /**< \brief (Sdramc Offset: 0x14) SDRAMC Interrupt Enable Register */ + __O uint32_t SDRAMC_IDR; /**< \brief (Sdramc Offset: 0x18) SDRAMC Interrupt Disable Register */ + __I uint32_t SDRAMC_IMR; /**< \brief (Sdramc Offset: 0x1C) SDRAMC Interrupt Mask Register */ + __I uint32_t SDRAMC_ISR; /**< \brief (Sdramc Offset: 0x20) SDRAMC Interrupt Status Register */ + __IO uint32_t SDRAMC_MDR; /**< \brief (Sdramc Offset: 0x24) SDRAMC Memory Device Register */ + __IO uint32_t SDRAMC_CFR1; /**< \brief (Sdramc Offset: 0x28) SDRAMC Configuration Register 1 */ + __IO uint32_t SDRAMC_OCMS; /**< \brief (Sdramc Offset: 0x2C) SDRAMC OCMS Register */ + __O uint32_t SDRAMC_OCMS_KEY1; /**< \brief (Sdramc Offset: 0x30) SDRAMC OCMS KEY1 Register */ + __O uint32_t SDRAMC_OCMS_KEY2; /**< \brief (Sdramc Offset: 0x34) SDRAMC OCMS KEY2 Register */ +} Sdramc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SDRAMC_MR : (SDRAMC Offset: 0x00) SDRAMC Mode Register -------- */ +#define SDRAMC_MR_MODE_Pos 0 +#define SDRAMC_MR_MODE_Msk (0x7u << SDRAMC_MR_MODE_Pos) /**< \brief (SDRAMC_MR) SDRAMC Command Mode */ +#define SDRAMC_MR_MODE(value) ((SDRAMC_MR_MODE_Msk & ((value) << SDRAMC_MR_MODE_Pos))) +#define SDRAMC_MR_MODE_NORMAL (0x0u << 0) /**< \brief (SDRAMC_MR) Normal mode. Any access to the SDRAM is decoded normally. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_NOP (0x1u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_ALLBANKS_PRECHARGE (0x2u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues an "All Banks Precharge" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_LOAD_MODEREG (0x3u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues a "Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_AUTO_REFRESH (0x4u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues an "Auto-Refresh" Command when the SDRAM device is accessed regardless of the cycle. Previously, an "All Banks Precharge" command must be issued. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_EXT_LOAD_MODEREG (0x5u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues an "Extended Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the "Extended Load Mode Register" command must be followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank; most low-power SDRAM devices use the bank 1. */ +#define SDRAMC_MR_MODE_DEEP_POWERDOWN (0x6u << 0) /**< \brief (SDRAMC_MR) Deep power-down mode. Enters deep power-down mode. */ +/* -------- SDRAMC_TR : (SDRAMC Offset: 0x04) SDRAMC Refresh Timer Register -------- */ +#define SDRAMC_TR_COUNT_Pos 0 +#define SDRAMC_TR_COUNT_Msk (0xfffu << SDRAMC_TR_COUNT_Pos) /**< \brief (SDRAMC_TR) SDRAMC Refresh Timer Count */ +#define SDRAMC_TR_COUNT(value) ((SDRAMC_TR_COUNT_Msk & ((value) << SDRAMC_TR_COUNT_Pos))) +/* -------- SDRAMC_CR : (SDRAMC Offset: 0x08) SDRAMC Configuration Register -------- */ +#define SDRAMC_CR_NC_Pos 0 +#define SDRAMC_CR_NC_Msk (0x3u << SDRAMC_CR_NC_Pos) /**< \brief (SDRAMC_CR) Number of Column Bits */ +#define SDRAMC_CR_NC(value) ((SDRAMC_CR_NC_Msk & ((value) << SDRAMC_CR_NC_Pos))) +#define SDRAMC_CR_NC_COL8 (0x0u << 0) /**< \brief (SDRAMC_CR) 8 column bits */ +#define SDRAMC_CR_NC_COL9 (0x1u << 0) /**< \brief (SDRAMC_CR) 9 column bits */ +#define SDRAMC_CR_NC_COL10 (0x2u << 0) /**< \brief (SDRAMC_CR) 10 column bits */ +#define SDRAMC_CR_NC_COL11 (0x3u << 0) /**< \brief (SDRAMC_CR) 11 column bits */ +#define SDRAMC_CR_NR_Pos 2 +#define SDRAMC_CR_NR_Msk (0x3u << SDRAMC_CR_NR_Pos) /**< \brief (SDRAMC_CR) Number of Row Bits */ +#define SDRAMC_CR_NR(value) ((SDRAMC_CR_NR_Msk & ((value) << SDRAMC_CR_NR_Pos))) +#define SDRAMC_CR_NR_ROW11 (0x0u << 2) /**< \brief (SDRAMC_CR) 11 row bits */ +#define SDRAMC_CR_NR_ROW12 (0x1u << 2) /**< \brief (SDRAMC_CR) 12 row bits */ +#define SDRAMC_CR_NR_ROW13 (0x2u << 2) /**< \brief (SDRAMC_CR) 13 row bits */ +#define SDRAMC_CR_NB (0x1u << 4) /**< \brief (SDRAMC_CR) Number of Banks */ +#define SDRAMC_CR_NB_BANK2 (0x0u << 4) /**< \brief (SDRAMC_CR) 2 banks */ +#define SDRAMC_CR_NB_BANK4 (0x1u << 4) /**< \brief (SDRAMC_CR) 4 banks */ +#define SDRAMC_CR_CAS_Pos 5 +#define SDRAMC_CR_CAS_Msk (0x3u << SDRAMC_CR_CAS_Pos) /**< \brief (SDRAMC_CR) CAS Latency */ +#define SDRAMC_CR_CAS(value) ((SDRAMC_CR_CAS_Msk & ((value) << SDRAMC_CR_CAS_Pos))) +#define SDRAMC_CR_CAS_LATENCY1 (0x0u << 5) /**< \brief (SDRAMC_CR) 1 cycle CAS latency */ +#define SDRAMC_CR_CAS_LATENCY2 (0x1u << 5) /**< \brief (SDRAMC_CR) 2 cycle CAS latency */ +#define SDRAMC_CR_CAS_LATENCY3 (0x2u << 5) /**< \brief (SDRAMC_CR) 3 cycle CAS latency */ +#define SDRAMC_CR_DBW (0x1u << 7) /**< \brief (SDRAMC_CR) Data Bus Width */ +#define SDRAMC_CR_TWR_Pos 8 +#define SDRAMC_CR_TWR_Msk (0xfu << SDRAMC_CR_TWR_Pos) /**< \brief (SDRAMC_CR) Write Recovery Delay */ +#define SDRAMC_CR_TWR(value) ((SDRAMC_CR_TWR_Msk & ((value) << SDRAMC_CR_TWR_Pos))) +#define SDRAMC_CR_TRC_TRFC_Pos 12 +#define SDRAMC_CR_TRC_TRFC_Msk (0xfu << SDRAMC_CR_TRC_TRFC_Pos) /**< \brief (SDRAMC_CR) Row Cycle Delay and Row Refresh Cycle */ +#define SDRAMC_CR_TRC_TRFC(value) ((SDRAMC_CR_TRC_TRFC_Msk & ((value) << SDRAMC_CR_TRC_TRFC_Pos))) +#define SDRAMC_CR_TRP_Pos 16 +#define SDRAMC_CR_TRP_Msk (0xfu << SDRAMC_CR_TRP_Pos) /**< \brief (SDRAMC_CR) Row Precharge Delay */ +#define SDRAMC_CR_TRP(value) ((SDRAMC_CR_TRP_Msk & ((value) << SDRAMC_CR_TRP_Pos))) +#define SDRAMC_CR_TRCD_Pos 20 +#define SDRAMC_CR_TRCD_Msk (0xfu << SDRAMC_CR_TRCD_Pos) /**< \brief (SDRAMC_CR) Row to Column Delay */ +#define SDRAMC_CR_TRCD(value) ((SDRAMC_CR_TRCD_Msk & ((value) << SDRAMC_CR_TRCD_Pos))) +#define SDRAMC_CR_TRAS_Pos 24 +#define SDRAMC_CR_TRAS_Msk (0xfu << SDRAMC_CR_TRAS_Pos) /**< \brief (SDRAMC_CR) Active to Precharge Delay */ +#define SDRAMC_CR_TRAS(value) ((SDRAMC_CR_TRAS_Msk & ((value) << SDRAMC_CR_TRAS_Pos))) +#define SDRAMC_CR_TXSR_Pos 28 +#define SDRAMC_CR_TXSR_Msk (0xfu << SDRAMC_CR_TXSR_Pos) /**< \brief (SDRAMC_CR) Exit Self Refresh to Active Delay */ +#define SDRAMC_CR_TXSR(value) ((SDRAMC_CR_TXSR_Msk & ((value) << SDRAMC_CR_TXSR_Pos))) +/* -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAMC Low Power Register -------- */ +#define SDRAMC_LPR_LPCB_Pos 0 +#define SDRAMC_LPR_LPCB_Msk (0x3u << SDRAMC_LPR_LPCB_Pos) /**< \brief (SDRAMC_LPR) Low-power Configuration Bits */ +#define SDRAMC_LPR_LPCB(value) ((SDRAMC_LPR_LPCB_Msk & ((value) << SDRAMC_LPR_LPCB_Pos))) +#define SDRAMC_LPR_LPCB_DISABLED (0x0u << 0) /**< \brief (SDRAMC_LPR) Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM device. */ +#define SDRAMC_LPR_LPCB_SELF_REFRESH (0x1u << 0) /**< \brief (SDRAMC_LPR) The SDRAMC issues a Self-refresh command to the SDRAM device, the SDCK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self Refresh Mode when accessed and enters it after the access. */ +#define SDRAMC_LPR_LPCB_POWER_DOWN (0x2u << 0) /**< \brief (SDRAMC_LPR) The SDRAMC issues a Power-down Command to the SDRAM device after each access, the SDCKE signal is set to low. The SDRAM device leaves the Power-down Mode when accessed and enters it after the access. */ +#define SDRAMC_LPR_LPCB_DEEP_POWER_DOWN (0x3u << 0) /**< \brief (SDRAMC_LPR) The SDRAMC issues a Deep Power-down command to the SDRAM device. This mode is unique to low-power SDRAM. */ +#define SDRAMC_LPR_PASR_Pos 4 +#define SDRAMC_LPR_PASR_Msk (0x7u << SDRAMC_LPR_PASR_Pos) /**< \brief (SDRAMC_LPR) Partial Array Self-refresh (only for low-power SDRAM) */ +#define SDRAMC_LPR_PASR(value) ((SDRAMC_LPR_PASR_Msk & ((value) << SDRAMC_LPR_PASR_Pos))) +#define SDRAMC_LPR_TCSR_Pos 8 +#define SDRAMC_LPR_TCSR_Msk (0x3u << SDRAMC_LPR_TCSR_Pos) /**< \brief (SDRAMC_LPR) Temperature Compensated Self-Refresh (only for low-power SDRAM) */ +#define SDRAMC_LPR_TCSR(value) ((SDRAMC_LPR_TCSR_Msk & ((value) << SDRAMC_LPR_TCSR_Pos))) +#define SDRAMC_LPR_DS_Pos 10 +#define SDRAMC_LPR_DS_Msk (0x3u << SDRAMC_LPR_DS_Pos) /**< \brief (SDRAMC_LPR) Drive Strength (only for low-power SDRAM) */ +#define SDRAMC_LPR_DS(value) ((SDRAMC_LPR_DS_Msk & ((value) << SDRAMC_LPR_DS_Pos))) +#define SDRAMC_LPR_TIMEOUT_Pos 12 +#define SDRAMC_LPR_TIMEOUT_Msk (0x3u << SDRAMC_LPR_TIMEOUT_Pos) /**< \brief (SDRAMC_LPR) Time to Define When Low-power Mode Is Enabled */ +#define SDRAMC_LPR_TIMEOUT(value) ((SDRAMC_LPR_TIMEOUT_Msk & ((value) << SDRAMC_LPR_TIMEOUT_Pos))) +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER (0x0u << 12) /**< \brief (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode immediately after the end of the last transfer. */ +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_64 (0x1u << 12) /**< \brief (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer. */ +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_128 (0x2u << 12) /**< \brief (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer. */ +/* -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAMC Interrupt Enable Register -------- */ +#define SDRAMC_IER_RES (0x1u << 0) /**< \brief (SDRAMC_IER) Refresh Error Status */ +/* -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAMC Interrupt Disable Register -------- */ +#define SDRAMC_IDR_RES (0x1u << 0) /**< \brief (SDRAMC_IDR) Refresh Error Status */ +/* -------- SDRAMC_IMR : (SDRAMC Offset: 0x1C) SDRAMC Interrupt Mask Register -------- */ +#define SDRAMC_IMR_RES (0x1u << 0) /**< \brief (SDRAMC_IMR) Refresh Error Status */ +/* -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAMC Interrupt Status Register -------- */ +#define SDRAMC_ISR_RES (0x1u << 0) /**< \brief (SDRAMC_ISR) Refresh Error Status (cleared on read) */ +/* -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAMC Memory Device Register -------- */ +#define SDRAMC_MDR_MD_Pos 0 +#define SDRAMC_MDR_MD_Msk (0x3u << SDRAMC_MDR_MD_Pos) /**< \brief (SDRAMC_MDR) Memory Device Type */ +#define SDRAMC_MDR_MD(value) ((SDRAMC_MDR_MD_Msk & ((value) << SDRAMC_MDR_MD_Pos))) +#define SDRAMC_MDR_MD_SDRAM (0x0u << 0) /**< \brief (SDRAMC_MDR) SDRAM */ +#define SDRAMC_MDR_MD_LPSDRAM (0x1u << 0) /**< \brief (SDRAMC_MDR) Low-power SDRAM */ +/* -------- SDRAMC_CFR1 : (SDRAMC Offset: 0x28) SDRAMC Configuration Register 1 -------- */ +#define SDRAMC_CFR1_TMRD_Pos 0 +#define SDRAMC_CFR1_TMRD_Msk (0xfu << SDRAMC_CFR1_TMRD_Pos) /**< \brief (SDRAMC_CFR1) Load Mode Register Command to Active or Refresh Command */ +#define SDRAMC_CFR1_TMRD(value) ((SDRAMC_CFR1_TMRD_Msk & ((value) << SDRAMC_CFR1_TMRD_Pos))) +#define SDRAMC_CFR1_UNAL (0x1u << 8) /**< \brief (SDRAMC_CFR1) Support Unaligned Access */ +#define SDRAMC_CFR1_UNAL_UNSUPPORTED (0x0u << 8) /**< \brief (SDRAMC_CFR1) Unaligned access is not supported. */ +#define SDRAMC_CFR1_UNAL_SUPPORTED (0x1u << 8) /**< \brief (SDRAMC_CFR1) Unaligned access is supported. */ +/* -------- SDRAMC_OCMS : (SDRAMC Offset: 0x2C) SDRAMC OCMS Register -------- */ +#define SDRAMC_OCMS_SDR_SE (0x1u << 0) /**< \brief (SDRAMC_OCMS) SDRAM Memory Controller Scrambling Enable */ +/* -------- SDRAMC_OCMS_KEY1 : (SDRAMC Offset: 0x30) SDRAMC OCMS KEY1 Register -------- */ +#define SDRAMC_OCMS_KEY1_KEY1_Pos 0 +#define SDRAMC_OCMS_KEY1_KEY1_Msk (0xffffffffu << SDRAMC_OCMS_KEY1_KEY1_Pos) /**< \brief (SDRAMC_OCMS_KEY1) Off-chip Memory Scrambling (OCMS) Key Part 1 */ +#define SDRAMC_OCMS_KEY1_KEY1(value) ((SDRAMC_OCMS_KEY1_KEY1_Msk & ((value) << SDRAMC_OCMS_KEY1_KEY1_Pos))) +/* -------- SDRAMC_OCMS_KEY2 : (SDRAMC Offset: 0x34) SDRAMC OCMS KEY2 Register -------- */ +#define SDRAMC_OCMS_KEY2_KEY2_Pos 0 +#define SDRAMC_OCMS_KEY2_KEY2_Msk (0xffffffffu << SDRAMC_OCMS_KEY2_KEY2_Pos) /**< \brief (SDRAMC_OCMS_KEY2) Off-chip Memory Scrambling (OCMS) Key Part 2 */ +#define SDRAMC_OCMS_KEY2_KEY2(value) ((SDRAMC_OCMS_KEY2_KEY2_Msk & ((value) << SDRAMC_OCMS_KEY2_KEY2_Pos))) + +/*@}*/ + + +#endif /* _SAMV71_SDRAMC_COMPONENT_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_smc.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_smc.h new file mode 100644 index 00000000..e4dc38c7 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_smc.h @@ -0,0 +1,144 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_SMC_COMPONENT_ +#define _SAMV71_SMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Static Memory Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_SMC Static Memory Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief SmcCs_number hardware registers */ +typedef struct { + __IO uint32_t SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */ + __IO uint32_t SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */ + __IO uint32_t SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */ + __IO uint32_t SMC_MODE; /**< \brief (SmcCs_number Offset: 0xC) SMC MODE Register */ +} SmcCs_number; +/** \brief Smc hardware registers */ +#define SMCCS_NUMBER_NUMBER 4 +typedef struct { + SmcCs_number SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x0) CS_number = 0 .. 3 */ + __I uint32_t Reserved1[16]; + __IO uint32_t SMC_OCMS; /**< \brief (Smc Offset: 0x80) SMC OCMS MODE Register */ + __O uint32_t SMC_KEY1; /**< \brief (Smc Offset: 0x84) SMC OCMS KEY1 Register */ + __O uint32_t SMC_KEY2; /**< \brief (Smc Offset: 0x88) SMC OCMS KEY2 Register */ + __I uint32_t Reserved2[22]; + __IO uint32_t SMC_WPMR; /**< \brief (Smc Offset: 0xE4) SMC Write Protection Mode Register */ + __I uint32_t SMC_WPSR; /**< \brief (Smc Offset: 0xE8) SMC Write Protection Status Register */ +} Smc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */ +#define SMC_SETUP_NWE_SETUP_Pos 0 +#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */ +#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos))) +#define SMC_SETUP_NCS_WR_SETUP_Pos 8 +#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in WRITE Access */ +#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos))) +#define SMC_SETUP_NRD_SETUP_Pos 16 +#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */ +#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos))) +#define SMC_SETUP_NCS_RD_SETUP_Pos 24 +#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in READ Access */ +#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos))) +/* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */ +#define SMC_PULSE_NWE_PULSE_Pos 0 +#define SMC_PULSE_NWE_PULSE_Msk (0x7fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */ +#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos))) +#define SMC_PULSE_NCS_WR_PULSE_Pos 8 +#define SMC_PULSE_NCS_WR_PULSE_Msk (0x7fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */ +#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos))) +#define SMC_PULSE_NRD_PULSE_Pos 16 +#define SMC_PULSE_NRD_PULSE_Msk (0x7fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */ +#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos))) +#define SMC_PULSE_NCS_RD_PULSE_Pos 24 +#define SMC_PULSE_NCS_RD_PULSE_Msk (0x7fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */ +#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos))) +/* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */ +#define SMC_CYCLE_NWE_CYCLE_Pos 0 +#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */ +#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos))) +#define SMC_CYCLE_NRD_CYCLE_Pos 16 +#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */ +#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos))) +/* -------- SMC_MODE : (SMC Offset: N/A) SMC MODE Register -------- */ +#define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE) Read Mode */ +#define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE) Write Mode */ +#define SMC_MODE_EXNW_MODE_Pos 4 +#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */ +#define SMC_MODE_EXNW_MODE(value) ((SMC_MODE_EXNW_MODE_Msk & ((value) << SMC_MODE_EXNW_MODE_Pos))) +#define SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled */ +#define SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode */ +#define SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode */ +#define SMC_MODE_BAT (0x1u << 8) /**< \brief (SMC_MODE) Byte Access Type */ +#define SMC_MODE_BAT_BYTE_SELECT (0x0u << 8) /**< \brief (SMC_MODE) Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1. */ +#define SMC_MODE_BAT_BYTE_WRITE (0x1u << 8) /**< \brief (SMC_MODE) Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD. */ +#define SMC_MODE_DBW (0x1u << 12) /**< \brief (SMC_MODE) Data Bus Width */ +#define SMC_MODE_DBW_8_BIT (0x0u << 12) /**< \brief (SMC_MODE) 8-bit Data Bus */ +#define SMC_MODE_DBW_16_BIT (0x1u << 12) /**< \brief (SMC_MODE) 16-bit Data Bus */ +#define SMC_MODE_TDF_CYCLES_Pos 16 +#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */ +#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos))) +#define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */ +#define SMC_MODE_PMEN (0x1u << 24) /**< \brief (SMC_MODE) Page Mode Enabled */ +#define SMC_MODE_PS_Pos 28 +#define SMC_MODE_PS_Msk (0x3u << SMC_MODE_PS_Pos) /**< \brief (SMC_MODE) Page Size */ +#define SMC_MODE_PS(value) ((SMC_MODE_PS_Msk & ((value) << SMC_MODE_PS_Pos))) +#define SMC_MODE_PS_4_BYTE (0x0u << 28) /**< \brief (SMC_MODE) 4-byte page */ +#define SMC_MODE_PS_8_BYTE (0x1u << 28) /**< \brief (SMC_MODE) 8-byte page */ +#define SMC_MODE_PS_16_BYTE (0x2u << 28) /**< \brief (SMC_MODE) 16-byte page */ +#define SMC_MODE_PS_32_BYTE (0x3u << 28) /**< \brief (SMC_MODE) 32-byte page */ +/* -------- SMC_OCMS : (SMC Offset: 0x80) SMC OCMS MODE Register -------- */ +#define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */ +/* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC OCMS KEY1 Register -------- */ +#define SMC_KEY1_KEY1_Pos 0 +#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */ +#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos))) +/* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC OCMS KEY2 Register -------- */ +#define SMC_KEY2_KEY2_Pos 0 +#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */ +#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos))) +/* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protection Mode Register -------- */ +#define SMC_WPMR_WPEN (0x1u << 0) /**< \brief (SMC_WPMR) Write Protect Enable */ +#define SMC_WPMR_WPKEY_Pos 8 +#define SMC_WPMR_WPKEY_Msk (0xffffffu << SMC_WPMR_WPKEY_Pos) /**< \brief (SMC_WPMR) Write Protection Key */ +#define SMC_WPMR_WPKEY(value) ((SMC_WPMR_WPKEY_Msk & ((value) << SMC_WPMR_WPKEY_Pos))) +#define SMC_WPMR_WPKEY_PASSWD (0x534D43u << 8) /**< \brief (SMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protection Status Register -------- */ +#define SMC_WPSR_WPVS (0x1u << 0) /**< \brief (SMC_WPSR) Write Protection Violation Status */ +#define SMC_WPSR_WPVSRC_Pos 8 +#define SMC_WPSR_WPVSRC_Msk (0xffffu << SMC_WPSR_WPVSRC_Pos) /**< \brief (SMC_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAMV71_SMC_COMPONENT_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_spi.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_spi.h new file mode 100644 index 00000000..913fddad --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_spi.h @@ -0,0 +1,161 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_SPI_COMPONENT_ +#define _SAMV71_SPI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */ +/* ============================================================================= */ +/** \addtogroup SAMV71_SPI Serial Peripheral Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Spi hardware registers */ +typedef struct { + __O uint32_t SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */ + __IO uint32_t SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */ + __I uint32_t SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */ + __O uint32_t SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */ + __I uint32_t SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */ + __O uint32_t SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */ + __O uint32_t SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */ + __I uint32_t SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */ + __I uint32_t Reserved1[4]; + __IO uint32_t SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */ + __I uint32_t Reserved2[41]; + __IO uint32_t SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */ +} Spi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */ +#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */ +#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */ +#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */ +#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */ +/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */ +#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */ +#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */ +#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */ +#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */ +#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */ +#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */ +#define SPI_MR_PCS_Pos 16 +#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */ +#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos))) +#define SPI_MR_DLYBCS_Pos 24 +#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */ +#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos))) +/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */ +#define SPI_RDR_RD_Pos 0 +#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */ +#define SPI_RDR_PCS_Pos 16 +#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */ +/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */ +#define SPI_TDR_TD_Pos 0 +#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */ +#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos))) +#define SPI_TDR_PCS_Pos 16 +#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */ +#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos))) +#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */ +/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ +#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full (cleared by reading SPI_RDR) */ +#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR) */ +#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error (cleared on read) */ +#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status (cleared on read) */ +#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising (cleared on read) */ +#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty (cleared by writing SPI_TDR) */ +#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave mode only) (cleared on read) */ +#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */ +/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ +#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */ +#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */ +#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */ +#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */ +#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */ +#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */ +#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */ +/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */ +#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */ +#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */ +#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */ +#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */ +#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */ +#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */ +/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */ +#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */ +#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */ +#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */ +#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */ +#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */ +#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */ +#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */ +/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */ +#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */ +#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */ +#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ +#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Active After Transfer */ +#define SPI_CSR_BITS_Pos 4 +#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */ +#define SPI_CSR_BITS(value) ((SPI_CSR_BITS_Msk & ((value) << SPI_CSR_BITS_Pos))) +#define SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */ +#define SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */ +#define SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */ +#define SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */ +#define SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */ +#define SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */ +#define SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */ +#define SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */ +#define SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */ +#define SPI_CSR_SCBR_Pos 8 +#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Bit Rate */ +#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos))) +#define SPI_CSR_DLYBS_Pos 16 +#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */ +#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos))) +#define SPI_CSR_DLYBCT_Pos 24 +#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */ +#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos))) +/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Mode Register -------- */ +#define SPI_WPMR_WPEN (0x1u << 0) /**< \brief (SPI_WPMR) Write Protection Enable */ +#define SPI_WPMR_WPKEY_Pos 8 +#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) /**< \brief (SPI_WPMR) Write Protection Key */ +#define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos))) +#define SPI_WPMR_WPKEY_PASSWD (0x535049u << 8) /**< \brief (SPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */ +#define SPI_WPSR_WPVS (0x1u << 0) /**< \brief (SPI_WPSR) Write Protection Violation Status */ +#define SPI_WPSR_WPVSRC_Pos 8 +#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAMV71_SPI_COMPONENT_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_ssc.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_ssc.h new file mode 100644 index 00000000..e95900ae --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_ssc.h @@ -0,0 +1,280 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_SSC_COMPONENT_ +#define _SAMV71_SSC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_SSC Synchronous Serial Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Ssc hardware registers */ +typedef struct { + __O uint32_t SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */ + __IO uint32_t SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */ + __I uint32_t Reserved1[2]; + __IO uint32_t SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */ + __IO uint32_t SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */ + __IO uint32_t SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */ + __IO uint32_t SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */ + __I uint32_t SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */ + __O uint32_t SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */ + __I uint32_t Reserved2[2]; + __I uint32_t SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */ + __IO uint32_t SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */ + __IO uint32_t SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */ + __IO uint32_t SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */ + __I uint32_t SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */ + __O uint32_t SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */ + __O uint32_t SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */ + __I uint32_t SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */ + __I uint32_t Reserved3[37]; + __IO uint32_t SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protection Status Register */ +} Ssc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */ +#define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */ +#define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */ +#define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */ +#define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */ +#define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */ +/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */ +#define SSC_CMR_DIV_Pos 0 +#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */ +#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos))) +/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */ +#define SSC_RCMR_CKS_Pos 0 +#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */ +#define SSC_RCMR_CKS(value) ((SSC_RCMR_CKS_Msk & ((value) << SSC_RCMR_CKS_Pos))) +#define SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */ +#define SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */ +#define SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */ +#define SSC_RCMR_CKO_Pos 2 +#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */ +#define SSC_RCMR_CKO(value) ((SSC_RCMR_CKO_Msk & ((value) << SSC_RCMR_CKO_Pos))) +#define SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None, RK pin is an input */ +#define SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock, RK pin is an output */ +#define SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers, RK pin is an output */ +#define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */ +#define SSC_RCMR_CKG_Pos 6 +#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */ +#define SSC_RCMR_CKG(value) ((SSC_RCMR_CKG_Msk & ((value) << SSC_RCMR_CKG_Pos))) +#define SSC_RCMR_CKG_CONTINUOUS (0x0u << 6) /**< \brief (SSC_RCMR) None */ +#define SSC_RCMR_CKG_EN_RF_LOW (0x1u << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF Low */ +#define SSC_RCMR_CKG_EN_RF_HIGH (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF High */ +#define SSC_RCMR_START_Pos 8 +#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */ +#define SSC_RCMR_START(value) ((SSC_RCMR_START_Msk & ((value) << SSC_RCMR_START_Pos))) +#define SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */ +#define SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */ +#define SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */ +#define SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */ +#define SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */ +#define SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */ +#define SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */ +#define SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */ +#define SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */ +#define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */ +#define SSC_RCMR_STTDLY_Pos 16 +#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */ +#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos))) +#define SSC_RCMR_PERIOD_Pos 24 +#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */ +#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos))) +/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */ +#define SSC_RFMR_DATLEN_Pos 0 +#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */ +#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos))) +#define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */ +#define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */ +#define SSC_RFMR_DATNB_Pos 8 +#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */ +#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos))) +#define SSC_RFMR_FSLEN_Pos 16 +#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */ +#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos))) +#define SSC_RFMR_FSOS_Pos 20 +#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */ +#define SSC_RFMR_FSOS(value) ((SSC_RFMR_FSOS_Msk & ((value) << SSC_RFMR_FSOS_Pos))) +#define SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None, RF pin is an input */ +#define SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse, RF pin is an output */ +#define SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse, RF pin is an output */ +#define SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer, RF pin is an output */ +#define SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer, RF pin is an output */ +#define SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer, RF pin is an output */ +#define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */ +#define SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */ +#define SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */ +#define SSC_RFMR_FSLEN_EXT_Pos 28 +#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */ +#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos))) +/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */ +#define SSC_TCMR_CKS_Pos 0 +#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */ +#define SSC_TCMR_CKS(value) ((SSC_TCMR_CKS_Msk & ((value) << SSC_TCMR_CKS_Pos))) +#define SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */ +#define SSC_TCMR_CKS_RK (0x1u << 0) /**< \brief (SSC_TCMR) RK Clock signal */ +#define SSC_TCMR_CKS_TK (0x2u << 0) /**< \brief (SSC_TCMR) TK pin */ +#define SSC_TCMR_CKO_Pos 2 +#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */ +#define SSC_TCMR_CKO(value) ((SSC_TCMR_CKO_Msk & ((value) << SSC_TCMR_CKO_Pos))) +#define SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None, TK pin is an input */ +#define SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Transmit Clock, TK pin is an output */ +#define SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers, TK pin is an output */ +#define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */ +#define SSC_TCMR_CKG_Pos 6 +#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */ +#define SSC_TCMR_CKG(value) ((SSC_TCMR_CKG_Msk & ((value) << SSC_TCMR_CKG_Pos))) +#define SSC_TCMR_CKG_CONTINUOUS (0x0u << 6) /**< \brief (SSC_TCMR) None */ +#define SSC_TCMR_CKG_EN_TF_LOW (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */ +#define SSC_TCMR_CKG_EN_TF_HIGH (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */ +#define SSC_TCMR_START_Pos 8 +#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */ +#define SSC_TCMR_START(value) ((SSC_TCMR_START_Msk & ((value) << SSC_TCMR_START_Pos))) +#define SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data */ +#define SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */ +#define SSC_TCMR_START_TF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */ +#define SSC_TCMR_START_TF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */ +#define SSC_TCMR_START_TF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */ +#define SSC_TCMR_START_TF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */ +#define SSC_TCMR_START_TF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */ +#define SSC_TCMR_START_TF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */ +#define SSC_TCMR_STTDLY_Pos 16 +#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */ +#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos))) +#define SSC_TCMR_PERIOD_Pos 24 +#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */ +#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos))) +/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */ +#define SSC_TFMR_DATLEN_Pos 0 +#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */ +#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos))) +#define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */ +#define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */ +#define SSC_TFMR_DATNB_Pos 8 +#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per Frame */ +#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos))) +#define SSC_TFMR_FSLEN_Pos 16 +#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */ +#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos))) +#define SSC_TFMR_FSOS_Pos 20 +#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */ +#define SSC_TFMR_FSOS(value) ((SSC_TFMR_FSOS_Msk & ((value) << SSC_TFMR_FSOS_Pos))) +#define SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None, TF pin is an input */ +#define SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse, TF pin is an output */ +#define SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse, TF pin is an output */ +#define SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */ +#define SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */ +#define SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */ +#define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */ +#define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */ +#define SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */ +#define SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */ +#define SSC_TFMR_FSLEN_EXT_Pos 28 +#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */ +#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos))) +/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */ +#define SSC_RHR_RDAT_Pos 0 +#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */ +/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */ +#define SSC_THR_TDAT_Pos 0 +#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */ +#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos))) +/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */ +#define SSC_RSHR_RSDAT_Pos 0 +#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */ +/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */ +#define SSC_TSHR_TSDAT_Pos 0 +#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */ +#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos))) +/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */ +#define SSC_RC0R_CP0_Pos 0 +#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */ +#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos))) +/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */ +#define SSC_RC1R_CP1_Pos 0 +#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */ +#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos))) +/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */ +#define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */ +#define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */ +#define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */ +#define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */ +#define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */ +#define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */ +#define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */ +#define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */ +#define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */ +#define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */ +/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */ +#define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */ +#define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */ +#define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */ +#define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */ +#define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */ +#define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */ +#define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */ +#define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */ +/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */ +#define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */ +#define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */ +#define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */ +#define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */ +#define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */ +#define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */ +#define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */ +#define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */ +/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */ +#define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */ +#define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */ +#define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */ +#define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */ +#define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */ +#define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */ +#define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */ +#define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */ +/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protection Mode Register -------- */ +#define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protection Enable */ +#define SSC_WPMR_WPKEY_Pos 8 +#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protection Key */ +#define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos))) +#define SSC_WPMR_WPKEY_PASSWD (0x535343u << 8) /**< \brief (SSC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protection Status Register -------- */ +#define SSC_WPSR_WPVS (0x1u << 0) /**< \brief (SSC_WPSR) Write Protection Violation Status */ +#define SSC_WPSR_WPVSRC_Pos 8 +#define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos) /**< \brief (SSC_WPSR) Write Protect Violation Source */ + +/*@}*/ + + +#endif /* _SAMV71_SSC_COMPONENT_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_supc.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_supc.h new file mode 100644 index 00000000..8ddeb97d --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_supc.h @@ -0,0 +1,295 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_SUPC_COMPONENT_ +#define _SAMV71_SUPC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Supply Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_SUPC Supply Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Supc hardware registers */ +typedef struct { + __O uint32_t SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */ + __IO uint32_t SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */ + __IO uint32_t SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */ + __IO uint32_t SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake-up Mode Register */ + __IO uint32_t SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake-up Inputs Register */ + __I uint32_t SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */ +} Supc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */ +#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */ +#define SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) No effect. */ +#define SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) If KEY is correct, VROFF asserts the vddcore_nreset and stops the voltage regulator. */ +#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */ +#define SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) No effect. */ +#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) If KEY is correct, XTALSEL switches the slow clock on the crystal oscillator output. */ +#define SUPC_CR_KEY_Pos 24 +#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */ +#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos))) +#define SUPC_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (SUPC_CR) Writing any other value in this field aborts the write operation. */ +/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */ +#define SUPC_SMMR_SMTH_Pos 0 +#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */ +#define SUPC_SMMR_SMTH(value) ((SUPC_SMMR_SMTH_Msk & ((value) << SUPC_SMMR_SMTH_Pos))) +#define SUPC_SMMR_SMSMPL_Pos 8 +#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */ +#define SUPC_SMMR_SMSMPL(value) ((SUPC_SMMR_SMSMPL_Msk & ((value) << SUPC_SMMR_SMSMPL_Pos))) +#define SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */ +#define SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */ +#define SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */ +#define SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */ +#define SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */ +#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */ +#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) The core reset signal vddcore_nreset is not affected when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */ +#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) The SUPC interrupt signal is not affected when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) The SUPC interrupt signal is asserted when a supply monitor detection occurs. */ +/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */ +#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */ +#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) The core reset signal vddcore_nreset is not affected when a brownout detection occurs. */ +#define SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) The core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */ +#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */ +#define SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) The core brownout detector is enabled. */ +#define SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) The core brownout detector is disabled. */ +#define SUPC_MR_ONREG (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator Enable */ +#define SUPC_MR_ONREG_ONREG_UNUSED (0x0u << 14) /**< \brief (SUPC_MR) Internal voltage regulator is not used (external power supply is used). */ +#define SUPC_MR_ONREG_ONREG_USED (0x1u << 14) /**< \brief (SUPC_MR) Internal voltage regulator is used. */ +#define SUPC_MR_BKUPRETON (0x1u << 17) /**< \brief (SUPC_MR) SRAM On In Backup Mode */ +#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */ +#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) No effect. Clock selection depends on the value of XTALSEL (SUPC_CR). */ +#define SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) The 32 kHz crystal oscillator is bypassed if XTALSEL (SUPC_CR) is set. OSCBYPASS must be set prior to setting XTALSEL. */ +#define SUPC_MR_KEY_Pos 24 +#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */ +#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos))) +#define SUPC_MR_KEY_PASSWD (0xA5u << 24) /**< \brief (SUPC_MR) Writing any other value in this field aborts the write operation. */ +/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake-up Mode Register -------- */ +#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake-up Enable */ +#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) The supply monitor detection has no wake-up effect. */ +#define SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) The supply monitor detection forces the wake-up of the core power supply. */ +#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real-time Timer Wake-up Enable */ +#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) The RTT alarm signal has no wake-up effect. */ +#define SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) The RTT alarm signal forces the wake-up of the core power supply. */ +#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real-time Clock Wake-up Enable */ +#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) The RTC alarm signal has no wake-up effect. */ +#define SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) The RTC alarm signal forces the wake-up of the core power supply. */ +#define SUPC_WUMR_LPDBCEN0 (0x1u << 5) /**< \brief (SUPC_WUMR) Low-power Debouncer Enable WKUP0 */ +#define SUPC_WUMR_LPDBCEN0_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUMR) The WKUP0 input pin is not connected to the low-power debouncer. */ +#define SUPC_WUMR_LPDBCEN0_ENABLE (0x1u << 5) /**< \brief (SUPC_WUMR) The WKUP0 input pin is connected to the low-power debouncer and forces a system wake-up. */ +#define SUPC_WUMR_LPDBCEN1 (0x1u << 6) /**< \brief (SUPC_WUMR) Low-power Debouncer Enable WKUP1 */ +#define SUPC_WUMR_LPDBCEN1_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUMR) The WKUP1 input pin is not connected to the low-power debouncer. */ +#define SUPC_WUMR_LPDBCEN1_ENABLE (0x1u << 6) /**< \brief (SUPC_WUMR) The WKUP1 input pin is connected to the low-power debouncer and forces a system wake-up. */ +#define SUPC_WUMR_LPDBCCLR (0x1u << 7) /**< \brief (SUPC_WUMR) Low-power Debouncer Clear */ +#define SUPC_WUMR_LPDBCCLR_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUMR) A low-power debounce event does not create an immediate clear on the first half of GPBR registers. */ +#define SUPC_WUMR_LPDBCCLR_ENABLE (0x1u << 7) /**< \brief (SUPC_WUMR) A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR registers. */ +#define SUPC_WUMR_WKUPDBC_Pos 12 +#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake-up Inputs Debouncer Period */ +#define SUPC_WUMR_WKUPDBC(value) ((SUPC_WUMR_WKUPDBC_Msk & ((value) << SUPC_WUMR_WKUPDBC_Pos))) +#define SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */ +#define SUPC_WUMR_WKUPDBC_3_SLCK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_32_SLCK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_512_SLCK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_4096_SLCK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_32768_SLCK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */ +#define SUPC_WUMR_LPDBC_Pos 16 +#define SUPC_WUMR_LPDBC_Msk (0x7u << SUPC_WUMR_LPDBC_Pos) /**< \brief (SUPC_WUMR) Low-power Debouncer Period */ +#define SUPC_WUMR_LPDBC(value) ((SUPC_WUMR_LPDBC_Msk & ((value) << SUPC_WUMR_LPDBC_Pos))) +#define SUPC_WUMR_LPDBC_DISABLE (0x0u << 16) /**< \brief (SUPC_WUMR) Disable the low-power debouncers. */ +#define SUPC_WUMR_LPDBC_2_RTCOUT (0x1u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 2 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_3_RTCOUT (0x2u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 3 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_4_RTCOUT (0x3u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 4 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_5_RTCOUT (0x4u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 5 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_6_RTCOUT (0x5u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 6 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_7_RTCOUT (0x6u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 7 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_8_RTCOUT (0x7u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 8 RTCOUTx clock periods */ +/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake-up Inputs Register -------- */ +#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 0 */ +#define SUPC_WUIR_WKUPEN0_DISABLE (0x0u << 0) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 1 */ +#define SUPC_WUIR_WKUPEN1_DISABLE (0x0u << 1) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 2 */ +#define SUPC_WUIR_WKUPEN2_DISABLE (0x0u << 2) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 3 */ +#define SUPC_WUIR_WKUPEN3_DISABLE (0x0u << 3) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 4 */ +#define SUPC_WUIR_WKUPEN4_DISABLE (0x0u << 4) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 5 */ +#define SUPC_WUIR_WKUPEN5_DISABLE (0x0u << 5) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 6 */ +#define SUPC_WUIR_WKUPEN6_DISABLE (0x0u << 6) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 7 */ +#define SUPC_WUIR_WKUPEN7_DISABLE (0x0u << 7) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 8 */ +#define SUPC_WUIR_WKUPEN8_DISABLE (0x0u << 8) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 9 */ +#define SUPC_WUIR_WKUPEN9_DISABLE (0x0u << 9) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 10 */ +#define SUPC_WUIR_WKUPEN10_DISABLE (0x0u << 10) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 11 */ +#define SUPC_WUIR_WKUPEN11_DISABLE (0x0u << 11) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 12 */ +#define SUPC_WUIR_WKUPEN12_DISABLE (0x0u << 12) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 13 */ +#define SUPC_WUIR_WKUPEN13_DISABLE (0x0u << 13) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 0 */ +#define SUPC_WUIR_WKUPT0_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT0_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 1 */ +#define SUPC_WUIR_WKUPT1_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT1_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 2 */ +#define SUPC_WUIR_WKUPT2_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT2_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 3 */ +#define SUPC_WUIR_WKUPT3_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT3_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 4 */ +#define SUPC_WUIR_WKUPT4_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT4_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 5 */ +#define SUPC_WUIR_WKUPT5_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT5_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 6 */ +#define SUPC_WUIR_WKUPT6_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT6_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 7 */ +#define SUPC_WUIR_WKUPT7_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT7_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 8 */ +#define SUPC_WUIR_WKUPT8_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT8_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 9 */ +#define SUPC_WUIR_WKUPT9_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT9_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 10 */ +#define SUPC_WUIR_WKUPT10_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT10_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 11 */ +#define SUPC_WUIR_WKUPT11_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT11_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 12 */ +#define SUPC_WUIR_WKUPT12_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT12_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 13 */ +#define SUPC_WUIR_WKUPT13_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT13_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */ +#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake-up Status (cleared on read) */ +#define SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake-up Status (cleared on read) */ +#define SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) No wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) At least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status (cleared on read) */ +#define SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) No core brownout rising edge event has been detected since the last read of the SUPC_SR. */ +#define SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) At least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */ +#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status (cleared on read) */ +#define SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) No supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ +#define SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ +#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status (cleared on read) */ +#define SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) No supply monitor detection since the last read of SUPC_SR. */ +#define SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) At least one supply monitor detection since the last read of SUPC_SR. */ +#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */ +#define SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) The supply monitor detected VDDIO higher than its threshold at its last measurement. */ +#define SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) The supply monitor detected VDDIO lower than its threshold at its last measurement. */ +#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */ +#define SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) The slow clock, SLCK, is generated by the embedded 32 kHz RC oscillator. */ +#define SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) The slow clock, SLCK, is generated by the 32 kHz crystal oscillator. */ +#define SUPC_SR_LPDBCS0 (0x1u << 13) /**< \brief (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP0 (cleared on read) */ +#define SUPC_SR_LPDBCS0_NO (0x0u << 13) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS0_PRESENT (0x1u << 13) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS1 (0x1u << 14) /**< \brief (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP1 (cleared on read) */ +#define SUPC_SR_LPDBCS1_NO (0x0u << 14) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS1_PRESENT (0x1u << 14) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ + +/*@}*/ + + +#endif /* _SAMV71_SUPC_COMPONENT_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_tc.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_tc.h new file mode 100644 index 00000000..680faee9 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_tc.h @@ -0,0 +1,346 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_TC_COMPONENT_ +#define _SAMV71_TC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Timer Counter */ +/* ============================================================================= */ +/** \addtogroup SAMV71_TC Timer Counter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief TcChannel hardware registers */ +typedef struct { + __O uint32_t TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */ + __IO uint32_t TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */ + __IO uint32_t TC_SMMR; /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */ + __I uint32_t TC_RAB; /**< \brief (TcChannel Offset: 0xC) Register AB */ + __I uint32_t TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */ + __IO uint32_t TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */ + __IO uint32_t TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */ + __IO uint32_t TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */ + __I uint32_t TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */ + __O uint32_t TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */ + __O uint32_t TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */ + __I uint32_t TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */ + __IO uint32_t TC_EMR; /**< \brief (TcChannel Offset: 0x30) Extended Mode Register */ + __I uint32_t Reserved1[3]; +} TcChannel; +/** \brief Tc hardware registers */ +#define TCCHANNEL_NUMBER 3 +typedef struct { + TcChannel TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */ + __O uint32_t TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */ + __IO uint32_t TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */ + __O uint32_t TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */ + __O uint32_t TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */ + __I uint32_t TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */ + __I uint32_t TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */ + __IO uint32_t TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */ + __I uint32_t Reserved1[2]; + __IO uint32_t TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protection Mode Register */ +} Tc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */ +#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */ +#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */ +#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */ +/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */ +#define TC_CMR_TCCLKS_Pos 0 +#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */ +#define TC_CMR_TCCLKS(value) ((TC_CMR_TCCLKS_Msk & ((value) << TC_CMR_TCCLKS_Pos))) +#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: internal PCK6 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/8 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/32 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/128 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: internal SLCK clock signal (from PMC) */ +#define TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */ +#define TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */ +#define TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */ +#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */ +#define TC_CMR_BURST_Pos 4 +#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */ +#define TC_CMR_BURST(value) ((TC_CMR_BURST_Msk & ((value) << TC_CMR_BURST_Pos))) +#define TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ +#define TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */ +#define TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */ +#define TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */ +#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */ +#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */ +#define TC_CMR_ETRGEDG_Pos 8 +#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */ +#define TC_CMR_ETRGEDG(value) ((TC_CMR_ETRGEDG_Msk & ((value) << TC_CMR_ETRGEDG_Pos))) +#define TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ +#define TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ +#define TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ +#define TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ +#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */ +#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */ +#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */ +#define TC_CMR_LDRA_Pos 16 +#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */ +#define TC_CMR_LDRA(value) ((TC_CMR_LDRA_Msk & ((value) << TC_CMR_LDRA_Pos))) +#define TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ +#define TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */ +#define TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */ +#define TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */ +#define TC_CMR_LDRB_Pos 18 +#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */ +#define TC_CMR_LDRB(value) ((TC_CMR_LDRB_Msk & ((value) << TC_CMR_LDRB_Pos))) +#define TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ +#define TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */ +#define TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */ +#define TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */ +#define TC_CMR_SBSMPLR_Pos 20 +#define TC_CMR_SBSMPLR_Msk (0x7u << TC_CMR_SBSMPLR_Pos) /**< \brief (TC_CMR) Loading Edge Subsampling Ratio */ +#define TC_CMR_SBSMPLR(value) ((TC_CMR_SBSMPLR_Msk & ((value) << TC_CMR_SBSMPLR_Pos))) +#define TC_CMR_SBSMPLR_ONE (0x0u << 20) /**< \brief (TC_CMR) Load a Capture Register each selected edge */ +#define TC_CMR_SBSMPLR_HALF (0x1u << 20) /**< \brief (TC_CMR) Load a Capture Register every 2 selected edges */ +#define TC_CMR_SBSMPLR_FOURTH (0x2u << 20) /**< \brief (TC_CMR) Load a Capture Register every 4 selected edges */ +#define TC_CMR_SBSMPLR_EIGHTH (0x3u << 20) /**< \brief (TC_CMR) Load a Capture Register every 8 selected edges */ +#define TC_CMR_SBSMPLR_SIXTEENTH (0x4u << 20) /**< \brief (TC_CMR) Load a Capture Register every 16 selected edges */ +#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */ +#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */ +#define TC_CMR_EEVTEDG_Pos 8 +#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */ +#define TC_CMR_EEVTEDG(value) ((TC_CMR_EEVTEDG_Msk & ((value) << TC_CMR_EEVTEDG_Pos))) +#define TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */ +#define TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ +#define TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ +#define TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ +#define TC_CMR_EEVT_Pos 10 +#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */ +#define TC_CMR_EEVT(value) ((TC_CMR_EEVT_Msk & ((value) << TC_CMR_EEVT_Pos))) +#define TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */ +#define TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */ +#define TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */ +#define TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */ +#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */ +#define TC_CMR_WAVSEL_Pos 13 +#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */ +#define TC_CMR_WAVSEL(value) ((TC_CMR_WAVSEL_Msk & ((value) << TC_CMR_WAVSEL_Pos))) +#define TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */ +#define TC_CMR_ACPA_Pos 16 +#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */ +#define TC_CMR_ACPA(value) ((TC_CMR_ACPA_Msk & ((value) << TC_CMR_ACPA_Pos))) +#define TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ +#define TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_ACPC_Pos 18 +#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */ +#define TC_CMR_ACPC(value) ((TC_CMR_ACPC_Msk & ((value) << TC_CMR_ACPC_Pos))) +#define TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ +#define TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_AEEVT_Pos 20 +#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */ +#define TC_CMR_AEEVT(value) ((TC_CMR_AEEVT_Msk & ((value) << TC_CMR_AEEVT_Pos))) +#define TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */ +#define TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */ +#define TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_ASWTRG_Pos 22 +#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */ +#define TC_CMR_ASWTRG(value) ((TC_CMR_ASWTRG_Msk & ((value) << TC_CMR_ASWTRG_Pos))) +#define TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */ +#define TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BCPB_Pos 24 +#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */ +#define TC_CMR_BCPB(value) ((TC_CMR_BCPB_Msk & ((value) << TC_CMR_BCPB_Pos))) +#define TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */ +#define TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BCPC_Pos 26 +#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */ +#define TC_CMR_BCPC(value) ((TC_CMR_BCPC_Msk & ((value) << TC_CMR_BCPC_Pos))) +#define TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */ +#define TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BEEVT_Pos 28 +#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */ +#define TC_CMR_BEEVT(value) ((TC_CMR_BEEVT_Msk & ((value) << TC_CMR_BEEVT_Pos))) +#define TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */ +#define TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BSWTRG_Pos 30 +#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */ +#define TC_CMR_BSWTRG(value) ((TC_CMR_BSWTRG_Msk & ((value) << TC_CMR_BSWTRG_Pos))) +#define TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */ +#define TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */ +/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */ +#define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */ +#define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) Down Count */ +/* -------- TC_RAB : (TC Offset: N/A) Register AB -------- */ +#define TC_RAB_RAB_Pos 0 +#define TC_RAB_RAB_Msk (0xffffffffu << TC_RAB_RAB_Pos) /**< \brief (TC_RAB) Register A or Register B */ +/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */ +#define TC_CV_CV_Pos 0 +#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */ +/* -------- TC_RA : (TC Offset: N/A) Register A -------- */ +#define TC_RA_RA_Pos 0 +#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */ +#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos))) +/* -------- TC_RB : (TC Offset: N/A) Register B -------- */ +#define TC_RB_RB_Pos 0 +#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */ +#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos))) +/* -------- TC_RC : (TC Offset: N/A) Register C -------- */ +#define TC_RC_RC_Pos 0 +#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */ +#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos))) +/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */ +#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status (cleared on read) */ +#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status (cleared on read) */ +#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status (cleared on read) */ +#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status (cleared on read) */ +#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status (cleared on read) */ +#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status (cleared on read) */ +#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status (cleared on read) */ +#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status (cleared on read) */ +#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */ +#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */ +#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */ +/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */ +#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */ +#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */ +#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */ +#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */ +#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */ +#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */ +#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */ +#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */ +/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */ +#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */ +#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */ +#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */ +#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */ +#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */ +#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */ +#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */ +#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */ +/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */ +#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */ +#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */ +#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */ +#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */ +#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */ +#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */ +#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */ +#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */ +/* -------- TC_EMR : (TC Offset: N/A) Extended Mode Register -------- */ +#define TC_EMR_TRIGSRCA_Pos 0 +#define TC_EMR_TRIGSRCA_Msk (0x3u << TC_EMR_TRIGSRCA_Pos) /**< \brief (TC_EMR) Trigger Source for Input A */ +#define TC_EMR_TRIGSRCA(value) ((TC_EMR_TRIGSRCA_Msk & ((value) << TC_EMR_TRIGSRCA_Pos))) +#define TC_EMR_TRIGSRCA_EXTERNAL_TIOAx (0x0u << 0) /**< \brief (TC_EMR) The trigger/capture input A is driven by external pin TIOAx */ +#define TC_EMR_TRIGSRCA_PWMx (0x1u << 0) /**< \brief (TC_EMR) The trigger/capture input A is driven internally by PWMx */ +#define TC_EMR_TRIGSRCB_Pos 4 +#define TC_EMR_TRIGSRCB_Msk (0x3u << TC_EMR_TRIGSRCB_Pos) /**< \brief (TC_EMR) Trigger Source for Input B */ +#define TC_EMR_TRIGSRCB(value) ((TC_EMR_TRIGSRCB_Msk & ((value) << TC_EMR_TRIGSRCB_Pos))) +#define TC_EMR_TRIGSRCB_EXTERNAL_TIOBx (0x0u << 4) /**< \brief (TC_EMR) The trigger/capture input B is driven by external pin TIOBx */ +#define TC_EMR_TRIGSRCB_PWMx (0x1u << 4) /**< \brief (TC_EMR) The trigger/capture input B is driven internally by PWMx */ +#define TC_EMR_NODIVCLK (0x1u << 8) /**< \brief (TC_EMR) No Divided Clock */ +/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */ +#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */ +/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */ +#define TC_BMR_TC0XC0S_Pos 0 +#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */ +#define TC_BMR_TC0XC0S(value) ((TC_BMR_TC0XC0S_Msk & ((value) << TC_BMR_TC0XC0S_Pos))) +#define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */ +#define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */ +#define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */ +#define TC_BMR_TC1XC1S_Pos 2 +#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */ +#define TC_BMR_TC1XC1S(value) ((TC_BMR_TC1XC1S_Msk & ((value) << TC_BMR_TC1XC1S_Pos))) +#define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */ +#define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */ +#define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */ +#define TC_BMR_TC2XC2S_Pos 4 +#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */ +#define TC_BMR_TC2XC2S(value) ((TC_BMR_TC2XC2S_Msk & ((value) << TC_BMR_TC2XC2S_Pos))) +#define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */ +#define TC_BMR_TC2XC2S_TIOA0 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA0 */ +#define TC_BMR_TC2XC2S_TIOA1 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */ +#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder Enabled */ +#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) Position Enabled */ +#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) Speed Enabled */ +#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding Transparent */ +#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) Edge on PHA Count Mode */ +#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) Inverted PHA */ +#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) Inverted PHB */ +#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) Inverted Index */ +#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) Swap PHA and PHB */ +#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) Index Pin is PHB Pin */ +#define TC_BMR_MAXFILT_Pos 20 +#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) Maximum Filter */ +#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos))) +/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */ +#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) Index */ +#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) Direction Change */ +#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature Error */ +/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */ +#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) Index */ +#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) Direction Change */ +#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature Error */ +/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */ +#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) Index */ +#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) Direction Change */ +#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature Error */ +/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */ +#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) Index */ +#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) Direction Change */ +#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature Error */ +#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) Direction */ +/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */ +#define TC_FMR_ENCF0 (0x1u << 0) /**< \brief (TC_FMR) Enable Compare Fault Channel 0 */ +#define TC_FMR_ENCF1 (0x1u << 1) /**< \brief (TC_FMR) Enable Compare Fault Channel 1 */ +/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protection Mode Register -------- */ +#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protection Enable */ +#define TC_WPMR_WPKEY_Pos 8 +#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protection Key */ +#define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos))) +#define TC_WPMR_WPKEY_PASSWD (0x54494Du << 8) /**< \brief (TC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAMV71_TC_COMPONENT_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_trng.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_trng.h new file mode 100644 index 00000000..bf5a25fc --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_trng.h @@ -0,0 +1,73 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_TRNG_COMPONENT_ +#define _SAMV71_TRNG_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR True Random Number Generator */ +/* ============================================================================= */ +/** \addtogroup SAMV71_TRNG True Random Number Generator */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Trng hardware registers */ +typedef struct { + __O uint32_t TRNG_CR; /**< \brief (Trng Offset: 0x00) Control Register */ + __I uint32_t Reserved1[3]; + __O uint32_t TRNG_IER; /**< \brief (Trng Offset: 0x10) Interrupt Enable Register */ + __O uint32_t TRNG_IDR; /**< \brief (Trng Offset: 0x14) Interrupt Disable Register */ + __I uint32_t TRNG_IMR; /**< \brief (Trng Offset: 0x18) Interrupt Mask Register */ + __I uint32_t TRNG_ISR; /**< \brief (Trng Offset: 0x1C) Interrupt Status Register */ + __I uint32_t Reserved2[12]; + __I uint32_t TRNG_ODATA; /**< \brief (Trng Offset: 0x50) Output Data Register */ +} Trng; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TRNG_CR : (TRNG Offset: 0x00) Control Register -------- */ +#define TRNG_CR_ENABLE (0x1u << 0) /**< \brief (TRNG_CR) Enables the TRNG to provide random values */ +#define TRNG_CR_KEY_Pos 8 +#define TRNG_CR_KEY_Msk (0xffffffu << TRNG_CR_KEY_Pos) /**< \brief (TRNG_CR) Security Key. */ +#define TRNG_CR_KEY(value) ((TRNG_CR_KEY_Msk & ((value) << TRNG_CR_KEY_Pos))) +#define TRNG_CR_KEY_PASSWD (0x524E47u << 8) /**< \brief (TRNG_CR) Writing any other value in this field aborts the write operation. */ +/* -------- TRNG_IER : (TRNG Offset: 0x10) Interrupt Enable Register -------- */ +#define TRNG_IER_DATRDY (0x1u << 0) /**< \brief (TRNG_IER) Data Ready Interrupt Enable */ +/* -------- TRNG_IDR : (TRNG Offset: 0x14) Interrupt Disable Register -------- */ +#define TRNG_IDR_DATRDY (0x1u << 0) /**< \brief (TRNG_IDR) Data Ready Interrupt Disable */ +/* -------- TRNG_IMR : (TRNG Offset: 0x18) Interrupt Mask Register -------- */ +#define TRNG_IMR_DATRDY (0x1u << 0) /**< \brief (TRNG_IMR) Data Ready Interrupt Mask */ +/* -------- TRNG_ISR : (TRNG Offset: 0x1C) Interrupt Status Register -------- */ +#define TRNG_ISR_DATRDY (0x1u << 0) /**< \brief (TRNG_ISR) Data Ready */ +/* -------- TRNG_ODATA : (TRNG Offset: 0x50) Output Data Register -------- */ +#define TRNG_ODATA_ODATA_Pos 0 +#define TRNG_ODATA_ODATA_Msk (0xffffffffu << TRNG_ODATA_ODATA_Pos) /**< \brief (TRNG_ODATA) Output Data */ + +/*@}*/ + + +#endif /* _SAMV71_TRNG_COMPONENT_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_twi.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_twi.h new file mode 100644 index 00000000..b07b0232 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_twi.h @@ -0,0 +1,165 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM_TWI_COMPONENT_ +#define _SAM_TWI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Two-wire Interface */ +/* ============================================================================= */ +/** \addtogroup SAM_TWI Two-wire Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Twi hardware registers */ +typedef struct { + __O uint32_t TWI_CR; /**< \brief (Twi Offset: 0x00) Control Register */ + __IO uint32_t TWI_MMR; /**< \brief (Twi Offset: 0x04) Master Mode Register */ + __IO uint32_t TWI_SMR; /**< \brief (Twi Offset: 0x08) Slave Mode Register */ + __IO uint32_t TWI_IADR; /**< \brief (Twi Offset: 0x0C) Internal Address Register */ + __IO uint32_t TWI_CWGR; /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */ + __I uint32_t Reserved1[3]; + __I uint32_t TWI_SR; /**< \brief (Twi Offset: 0x20) Status Register */ + __O uint32_t TWI_IER; /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */ + __O uint32_t TWI_IDR; /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */ + __I uint32_t TWI_IMR; /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t TWI_RHR; /**< \brief (Twi Offset: 0x30) Receive Holding Register */ + __O uint32_t TWI_THR; /**< \brief (Twi Offset: 0x34) Transmit Holding Register */ + __I uint32_t Reserved2[43]; + __IO uint32_t TWI_WPMR; /**< \brief (Twi Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t TWI_WPSR; /**< \brief (Twi Offset: 0xE8) Write Protection Status Register */ +} Twi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */ +#define TWI_CR_START (0x1u << 0) /**< \brief (TWI_CR) Send a START Condition */ +#define TWI_CR_STOP (0x1u << 1) /**< \brief (TWI_CR) Send a STOP Condition */ +#define TWI_CR_MSEN (0x1u << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */ +#define TWI_CR_MSDIS (0x1u << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */ +#define TWI_CR_SVEN (0x1u << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */ +#define TWI_CR_SVDIS (0x1u << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */ +#define TWI_CR_QUICK (0x1u << 6) /**< \brief (TWI_CR) SMBUS Quick Command */ +#define TWI_CR_SWRST (0x1u << 7) /**< \brief (TWI_CR) Software Reset */ +/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */ +#define TWI_MMR_IADRSZ_Pos 8 +#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /**< \brief (TWI_MMR) Internal Device Address Size */ +#define TWI_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWI_MMR) No internal device address */ +#define TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWI_MMR) One-byte internal device address */ +#define TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWI_MMR) Two-byte internal device address */ +#define TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWI_MMR) Three-byte internal device address */ +#define TWI_MMR_MREAD (0x1u << 12) /**< \brief (TWI_MMR) Master Read Direction */ +#define TWI_MMR_DADR_Pos 16 +#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */ +#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos))) +/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */ +#define TWI_SMR_SADR_Pos 16 +#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */ +#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos))) +/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */ +#define TWI_IADR_IADR_Pos 0 +#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */ +#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos))) +/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */ +#define TWI_CWGR_CLDIV_Pos 0 +#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */ +#define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos))) +#define TWI_CWGR_CHDIV_Pos 8 +#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */ +#define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos))) +#define TWI_CWGR_CKDIV_Pos 16 +#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */ +#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos))) +#define TWI_CWGR_HOLD_Pos 24 +#define TWI_CWGR_HOLD_Msk (0x1fu << TWI_CWGR_HOLD_Pos) /**< \brief (TWI_CWGR) TWD Hold Time versus TWCK falling */ +#define TWI_CWGR_HOLD(value) ((TWI_CWGR_HOLD_Msk & ((value) << TWI_CWGR_HOLD_Pos))) +/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */ +#define TWI_SR_TXCOMP (0x1u << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */ +#define TWI_SR_RXRDY (0x1u << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */ +#define TWI_SR_TXRDY (0x1u << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */ +#define TWI_SR_SVREAD (0x1u << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */ +#define TWI_SR_SVACC (0x1u << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */ +#define TWI_SR_GACC (0x1u << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */ +#define TWI_SR_OVRE (0x1u << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */ +#define TWI_SR_NACK (0x1u << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */ +#define TWI_SR_ARBLST (0x1u << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */ +#define TWI_SR_SCLWS (0x1u << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */ +#define TWI_SR_EOSACC (0x1u << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */ +/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */ +#define TWI_IER_TXCOMP (0x1u << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */ +#define TWI_IER_RXRDY (0x1u << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */ +#define TWI_IER_TXRDY (0x1u << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */ +#define TWI_IER_SVACC (0x1u << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */ +#define TWI_IER_GACC (0x1u << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */ +#define TWI_IER_OVRE (0x1u << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */ +#define TWI_IER_NACK (0x1u << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */ +#define TWI_IER_ARBLST (0x1u << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */ +#define TWI_IER_SCL_WS (0x1u << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */ +#define TWI_IER_EOSACC (0x1u << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */ +/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */ +#define TWI_IDR_TXCOMP (0x1u << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */ +#define TWI_IDR_RXRDY (0x1u << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */ +#define TWI_IDR_TXRDY (0x1u << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */ +#define TWI_IDR_SVACC (0x1u << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */ +#define TWI_IDR_GACC (0x1u << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */ +#define TWI_IDR_OVRE (0x1u << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */ +#define TWI_IDR_NACK (0x1u << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */ +#define TWI_IDR_ARBLST (0x1u << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */ +#define TWI_IDR_SCL_WS (0x1u << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */ +#define TWI_IDR_EOSACC (0x1u << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */ +/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */ +#define TWI_IMR_TXCOMP (0x1u << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */ +#define TWI_IMR_RXRDY (0x1u << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */ +#define TWI_IMR_TXRDY (0x1u << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */ +#define TWI_IMR_SVACC (0x1u << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */ +#define TWI_IMR_GACC (0x1u << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */ +#define TWI_IMR_OVRE (0x1u << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */ +#define TWI_IMR_NACK (0x1u << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */ +#define TWI_IMR_ARBLST (0x1u << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */ +#define TWI_IMR_SCL_WS (0x1u << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */ +#define TWI_IMR_EOSACC (0x1u << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */ +/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */ +#define TWI_RHR_RXDATA_Pos 0 +#define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */ +/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */ +#define TWI_THR_TXDATA_Pos 0 +#define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */ +#define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos))) +/* -------- TWI_WPMR : (TWI Offset: 0xE4) Write Protection Mode Register -------- */ +#define TWI_WPMR_WPEN (0x1u << 0) /**< \brief (TWI_WPMR) Write Protection Enable */ +#define TWI_WPMR_WPKEY_Pos 8 +#define TWI_WPMR_WPKEY_Msk (0xffffffu << TWI_WPMR_WPKEY_Pos) /**< \brief (TWI_WPMR) Write Protection Key */ +#define TWI_WPMR_WPKEY_PASSWD (0x545749u << 8) /**< \brief (TWI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 */ +/* -------- TWI_WPSR : (TWI Offset: 0xE8) Write Protection Status Register -------- */ +#define TWI_WPSR_WPVS (0x1u << 0) /**< \brief (TWI_WPSR) Write Protection Violation Status */ +#define TWI_WPSR_WPVSRC_Pos 8 +#define TWI_WPSR_WPVSRC_Msk (0xffffffu << TWI_WPSR_WPVSRC_Pos) /**< \brief (TWI_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAM_TWI_COMPONENT_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_twihs.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_twihs.h new file mode 100644 index 00000000..7473b074 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_twihs.h @@ -0,0 +1,250 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_TWIHS_COMPONENT_ +#define _SAMV71_TWIHS_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Two-wire Interface High Speed */ +/* ============================================================================= */ +/** \addtogroup SAMV71_TWIHS Two-wire Interface High Speed */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Twihs hardware registers */ +typedef struct { + __O uint32_t TWIHS_CR; /**< \brief (Twihs Offset: 0x00) Control Register */ + __IO uint32_t TWIHS_MMR; /**< \brief (Twihs Offset: 0x04) Master Mode Register */ + __IO uint32_t TWIHS_SMR; /**< \brief (Twihs Offset: 0x08) Slave Mode Register */ + __IO uint32_t TWIHS_IADR; /**< \brief (Twihs Offset: 0x0C) Internal Address Register */ + __IO uint32_t TWIHS_CWGR; /**< \brief (Twihs Offset: 0x10) Clock Waveform Generator Register */ + __I uint32_t Reserved1[3]; + __I uint32_t TWIHS_SR; /**< \brief (Twihs Offset: 0x20) Status Register */ + __O uint32_t TWIHS_IER; /**< \brief (Twihs Offset: 0x24) Interrupt Enable Register */ + __O uint32_t TWIHS_IDR; /**< \brief (Twihs Offset: 0x28) Interrupt Disable Register */ + __I uint32_t TWIHS_IMR; /**< \brief (Twihs Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t TWIHS_RHR; /**< \brief (Twihs Offset: 0x30) Receive Holding Register */ + __O uint32_t TWIHS_THR; /**< \brief (Twihs Offset: 0x34) Transmit Holding Register */ + __IO uint32_t TWIHS_SMBTR; /**< \brief (Twihs Offset: 0x38) SMBus Timing Register */ + __I uint32_t Reserved2[2]; + __IO uint32_t TWIHS_FILTR; /**< \brief (Twihs Offset: 0x44) Filter Register */ + __I uint32_t Reserved3[1]; + __IO uint32_t TWIHS_SWMR; /**< \brief (Twihs Offset: 0x4C) SleepWalking Matching Register */ + __I uint32_t Reserved4[37]; + __IO uint32_t TWIHS_WPMR; /**< \brief (Twihs Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t TWIHS_WPSR; /**< \brief (Twihs Offset: 0xE8) Write Protection Status Register */ +} Twihs; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TWIHS_CR : (TWIHS Offset: 0x00) Control Register -------- */ +#define TWIHS_CR_START (0x1u << 0) /**< \brief (TWIHS_CR) Send a START Condition */ +#define TWIHS_CR_STOP (0x1u << 1) /**< \brief (TWIHS_CR) Send a STOP Condition */ +#define TWIHS_CR_MSEN (0x1u << 2) /**< \brief (TWIHS_CR) TWIHS Master Mode Enabled */ +#define TWIHS_CR_MSDIS (0x1u << 3) /**< \brief (TWIHS_CR) TWIHS Master Mode Disabled */ +#define TWIHS_CR_SVEN (0x1u << 4) /**< \brief (TWIHS_CR) TWIHS Slave Mode Enabled */ +#define TWIHS_CR_SVDIS (0x1u << 5) /**< \brief (TWIHS_CR) TWIHS Slave Mode Disabled */ +#define TWIHS_CR_QUICK (0x1u << 6) /**< \brief (TWIHS_CR) SMBus Quick Command */ +#define TWIHS_CR_SWRST (0x1u << 7) /**< \brief (TWIHS_CR) Software Reset */ +#define TWIHS_CR_HSEN (0x1u << 8) /**< \brief (TWIHS_CR) TWIHS High-Speed Mode Enabled */ +#define TWIHS_CR_HSDIS (0x1u << 9) /**< \brief (TWIHS_CR) TWIHS High-Speed Mode Disabled */ +#define TWIHS_CR_SMBEN (0x1u << 10) /**< \brief (TWIHS_CR) SMBus Mode Enabled */ +#define TWIHS_CR_SMBDIS (0x1u << 11) /**< \brief (TWIHS_CR) SMBus Mode Disabled */ +#define TWIHS_CR_PECEN (0x1u << 12) /**< \brief (TWIHS_CR) Packet Error Checking Enable */ +#define TWIHS_CR_PECDIS (0x1u << 13) /**< \brief (TWIHS_CR) Packet Error Checking Disable */ +#define TWIHS_CR_PECRQ (0x1u << 14) /**< \brief (TWIHS_CR) PEC Request */ +#define TWIHS_CR_CLEAR (0x1u << 15) /**< \brief (TWIHS_CR) Bus CLEAR Command */ +/* -------- TWIHS_MMR : (TWIHS Offset: 0x04) Master Mode Register -------- */ +#define TWIHS_MMR_IADRSZ_Pos 8 +#define TWIHS_MMR_IADRSZ_Msk (0x3u << TWIHS_MMR_IADRSZ_Pos) /**< \brief (TWIHS_MMR) Internal Device Address Size */ +#define TWIHS_MMR_IADRSZ(value) ((TWIHS_MMR_IADRSZ_Msk & ((value) << TWIHS_MMR_IADRSZ_Pos))) +#define TWIHS_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWIHS_MMR) No internal device address */ +#define TWIHS_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWIHS_MMR) One-byte internal device address */ +#define TWIHS_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWIHS_MMR) Two-byte internal device address */ +#define TWIHS_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWIHS_MMR) Three-byte internal device address */ +#define TWIHS_MMR_MREAD (0x1u << 12) /**< \brief (TWIHS_MMR) Master Read Direction */ +#define TWIHS_MMR_DADR_Pos 16 +#define TWIHS_MMR_DADR_Msk (0x7fu << TWIHS_MMR_DADR_Pos) /**< \brief (TWIHS_MMR) Device Address */ +#define TWIHS_MMR_DADR(value) ((TWIHS_MMR_DADR_Msk & ((value) << TWIHS_MMR_DADR_Pos))) +/* -------- TWIHS_SMR : (TWIHS Offset: 0x08) Slave Mode Register -------- */ +#define TWIHS_SMR_NACKEN (0x1u << 0) /**< \brief (TWIHS_SMR) Slave Receiver Data Phase NACK enable */ +#define TWIHS_SMR_SMDA (0x1u << 2) /**< \brief (TWIHS_SMR) SMBus Default Address */ +#define TWIHS_SMR_SMHH (0x1u << 3) /**< \brief (TWIHS_SMR) SMBus Host Header */ +#define TWIHS_SMR_SCLWSDIS (0x1u << 6) /**< \brief (TWIHS_SMR) Clock Wait State Disable */ +#define TWIHS_SMR_MASK_Pos 8 +#define TWIHS_SMR_MASK_Msk (0x7fu << TWIHS_SMR_MASK_Pos) /**< \brief (TWIHS_SMR) Slave Address Mask */ +#define TWIHS_SMR_MASK(value) ((TWIHS_SMR_MASK_Msk & ((value) << TWIHS_SMR_MASK_Pos))) +#define TWIHS_SMR_SADR_Pos 16 +#define TWIHS_SMR_SADR_Msk (0x7fu << TWIHS_SMR_SADR_Pos) /**< \brief (TWIHS_SMR) Slave Address */ +#define TWIHS_SMR_SADR(value) ((TWIHS_SMR_SADR_Msk & ((value) << TWIHS_SMR_SADR_Pos))) +#define TWIHS_SMR_SADR1EN (0x1u << 28) /**< \brief (TWIHS_SMR) Slave Address 1 Enable */ +#define TWIHS_SMR_SADR2EN (0x1u << 29) /**< \brief (TWIHS_SMR) Slave Address 2 Enable */ +#define TWIHS_SMR_SADR3EN (0x1u << 30) /**< \brief (TWIHS_SMR) Slave Address 3 Enable */ +#define TWIHS_SMR_DATAMEN (0x1u << 31) /**< \brief (TWIHS_SMR) Data Matching Enable */ +/* -------- TWIHS_IADR : (TWIHS Offset: 0x0C) Internal Address Register -------- */ +#define TWIHS_IADR_IADR_Pos 0 +#define TWIHS_IADR_IADR_Msk (0xffffffu << TWIHS_IADR_IADR_Pos) /**< \brief (TWIHS_IADR) Internal Address */ +#define TWIHS_IADR_IADR(value) ((TWIHS_IADR_IADR_Msk & ((value) << TWIHS_IADR_IADR_Pos))) +/* -------- TWIHS_CWGR : (TWIHS Offset: 0x10) Clock Waveform Generator Register -------- */ +#define TWIHS_CWGR_CLDIV_Pos 0 +#define TWIHS_CWGR_CLDIV_Msk (0xffu << TWIHS_CWGR_CLDIV_Pos) /**< \brief (TWIHS_CWGR) Clock Low Divider */ +#define TWIHS_CWGR_CLDIV(value) ((TWIHS_CWGR_CLDIV_Msk & ((value) << TWIHS_CWGR_CLDIV_Pos))) +#define TWIHS_CWGR_CHDIV_Pos 8 +#define TWIHS_CWGR_CHDIV_Msk (0xffu << TWIHS_CWGR_CHDIV_Pos) /**< \brief (TWIHS_CWGR) Clock High Divider */ +#define TWIHS_CWGR_CHDIV(value) ((TWIHS_CWGR_CHDIV_Msk & ((value) << TWIHS_CWGR_CHDIV_Pos))) +#define TWIHS_CWGR_CKDIV_Pos 16 +#define TWIHS_CWGR_CKDIV_Msk (0x7u << TWIHS_CWGR_CKDIV_Pos) /**< \brief (TWIHS_CWGR) Clock Divider */ +#define TWIHS_CWGR_CKDIV(value) ((TWIHS_CWGR_CKDIV_Msk & ((value) << TWIHS_CWGR_CKDIV_Pos))) +#define TWIHS_CWGR_HOLD_Pos 24 +#define TWIHS_CWGR_HOLD_Msk (0x1fu << TWIHS_CWGR_HOLD_Pos) /**< \brief (TWIHS_CWGR) TWD Hold Time Versus TWCK Falling */ +#define TWIHS_CWGR_HOLD(value) ((TWIHS_CWGR_HOLD_Msk & ((value) << TWIHS_CWGR_HOLD_Pos))) +/* -------- TWIHS_SR : (TWIHS Offset: 0x20) Status Register -------- */ +#define TWIHS_SR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_SR) Transmission Completed (cleared by writing TWIHS_THR) */ +#define TWIHS_SR_RXRDY (0x1u << 1) /**< \brief (TWIHS_SR) Receive Holding Register Ready (cleared by reading TWIHS_RHR) */ +#define TWIHS_SR_TXRDY (0x1u << 2) /**< \brief (TWIHS_SR) Transmit Holding Register Ready (cleared by writing TWIHS_THR) */ +#define TWIHS_SR_SVREAD (0x1u << 3) /**< \brief (TWIHS_SR) Slave Read */ +#define TWIHS_SR_SVACC (0x1u << 4) /**< \brief (TWIHS_SR) Slave Access */ +#define TWIHS_SR_GACC (0x1u << 5) /**< \brief (TWIHS_SR) General Call Access (cleared on read) */ +#define TWIHS_SR_OVRE (0x1u << 6) /**< \brief (TWIHS_SR) Overrun Error (cleared on read) */ +#define TWIHS_SR_UNRE (0x1u << 7) /**< \brief (TWIHS_SR) Underrun Error (cleared on read) */ +#define TWIHS_SR_NACK (0x1u << 8) /**< \brief (TWIHS_SR) Not Acknowledged (cleared on read) */ +#define TWIHS_SR_ARBLST (0x1u << 9) /**< \brief (TWIHS_SR) Arbitration Lost (cleared on read) */ +#define TWIHS_SR_SCLWS (0x1u << 10) /**< \brief (TWIHS_SR) Clock Wait State */ +#define TWIHS_SR_EOSACC (0x1u << 11) /**< \brief (TWIHS_SR) End Of Slave Access (cleared on read) */ +#define TWIHS_SR_MCACK (0x1u << 16) /**< \brief (TWIHS_SR) Master Code Acknowledge (cleared on read) */ +#define TWIHS_SR_TOUT (0x1u << 18) /**< \brief (TWIHS_SR) Timeout Error (cleared on read) */ +#define TWIHS_SR_PECERR (0x1u << 19) /**< \brief (TWIHS_SR) PEC Error (cleared on read) */ +#define TWIHS_SR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_SR) SMBus Default Address Match (cleared on read) */ +#define TWIHS_SR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_SR) SMBus Host Header Address Match (cleared on read) */ +#define TWIHS_SR_SCL (0x1u << 24) /**< \brief (TWIHS_SR) SCL line value */ +#define TWIHS_SR_SDA (0x1u << 25) /**< \brief (TWIHS_SR) SDA line value */ +/* -------- TWIHS_IER : (TWIHS Offset: 0x24) Interrupt Enable Register -------- */ +#define TWIHS_IER_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IER) Transmission Completed Interrupt Enable */ +#define TWIHS_IER_RXRDY (0x1u << 1) /**< \brief (TWIHS_IER) Receive Holding Register Ready Interrupt Enable */ +#define TWIHS_IER_TXRDY (0x1u << 2) /**< \brief (TWIHS_IER) Transmit Holding Register Ready Interrupt Enable */ +#define TWIHS_IER_SVACC (0x1u << 4) /**< \brief (TWIHS_IER) Slave Access Interrupt Enable */ +#define TWIHS_IER_GACC (0x1u << 5) /**< \brief (TWIHS_IER) General Call Access Interrupt Enable */ +#define TWIHS_IER_OVRE (0x1u << 6) /**< \brief (TWIHS_IER) Overrun Error Interrupt Enable */ +#define TWIHS_IER_UNRE (0x1u << 7) /**< \brief (TWIHS_IER) Underrun Error Interrupt Enable */ +#define TWIHS_IER_NACK (0x1u << 8) /**< \brief (TWIHS_IER) Not Acknowledge Interrupt Enable */ +#define TWIHS_IER_ARBLST (0x1u << 9) /**< \brief (TWIHS_IER) Arbitration Lost Interrupt Enable */ +#define TWIHS_IER_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IER) Clock Wait State Interrupt Enable */ +#define TWIHS_IER_EOSACC (0x1u << 11) /**< \brief (TWIHS_IER) End Of Slave Access Interrupt Enable */ +#define TWIHS_IER_MCACK (0x1u << 16) /**< \brief (TWIHS_IER) Master Code Acknowledge Interrupt Enable */ +#define TWIHS_IER_TOUT (0x1u << 18) /**< \brief (TWIHS_IER) Timeout Error Interrupt Enable */ +#define TWIHS_IER_PECERR (0x1u << 19) /**< \brief (TWIHS_IER) PEC Error Interrupt Enable */ +#define TWIHS_IER_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IER) SMBus Default Address Match Interrupt Enable */ +#define TWIHS_IER_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IER) SMBus Host Header Address Match Interrupt Enable */ +/* -------- TWIHS_IDR : (TWIHS Offset: 0x28) Interrupt Disable Register -------- */ +#define TWIHS_IDR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IDR) Transmission Completed Interrupt Disable */ +#define TWIHS_IDR_RXRDY (0x1u << 1) /**< \brief (TWIHS_IDR) Receive Holding Register Ready Interrupt Disable */ +#define TWIHS_IDR_TXRDY (0x1u << 2) /**< \brief (TWIHS_IDR) Transmit Holding Register Ready Interrupt Disable */ +#define TWIHS_IDR_SVACC (0x1u << 4) /**< \brief (TWIHS_IDR) Slave Access Interrupt Disable */ +#define TWIHS_IDR_GACC (0x1u << 5) /**< \brief (TWIHS_IDR) General Call Access Interrupt Disable */ +#define TWIHS_IDR_OVRE (0x1u << 6) /**< \brief (TWIHS_IDR) Overrun Error Interrupt Disable */ +#define TWIHS_IDR_UNRE (0x1u << 7) /**< \brief (TWIHS_IDR) Underrun Error Interrupt Disable */ +#define TWIHS_IDR_NACK (0x1u << 8) /**< \brief (TWIHS_IDR) Not Acknowledge Interrupt Disable */ +#define TWIHS_IDR_ARBLST (0x1u << 9) /**< \brief (TWIHS_IDR) Arbitration Lost Interrupt Disable */ +#define TWIHS_IDR_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IDR) Clock Wait State Interrupt Disable */ +#define TWIHS_IDR_EOSACC (0x1u << 11) /**< \brief (TWIHS_IDR) End Of Slave Access Interrupt Disable */ +#define TWIHS_IDR_MCACK (0x1u << 16) /**< \brief (TWIHS_IDR) Master Code Acknowledge Interrupt Disable */ +#define TWIHS_IDR_TOUT (0x1u << 18) /**< \brief (TWIHS_IDR) Timeout Error Interrupt Disable */ +#define TWIHS_IDR_PECERR (0x1u << 19) /**< \brief (TWIHS_IDR) PEC Error Interrupt Disable */ +#define TWIHS_IDR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IDR) SMBus Default Address Match Interrupt Disable */ +#define TWIHS_IDR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IDR) SMBus Host Header Address Match Interrupt Disable */ +/* -------- TWIHS_IMR : (TWIHS Offset: 0x2C) Interrupt Mask Register -------- */ +#define TWIHS_IMR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IMR) Transmission Completed Interrupt Mask */ +#define TWIHS_IMR_RXRDY (0x1u << 1) /**< \brief (TWIHS_IMR) Receive Holding Register Ready Interrupt Mask */ +#define TWIHS_IMR_TXRDY (0x1u << 2) /**< \brief (TWIHS_IMR) Transmit Holding Register Ready Interrupt Mask */ +#define TWIHS_IMR_SVACC (0x1u << 4) /**< \brief (TWIHS_IMR) Slave Access Interrupt Mask */ +#define TWIHS_IMR_GACC (0x1u << 5) /**< \brief (TWIHS_IMR) General Call Access Interrupt Mask */ +#define TWIHS_IMR_OVRE (0x1u << 6) /**< \brief (TWIHS_IMR) Overrun Error Interrupt Mask */ +#define TWIHS_IMR_UNRE (0x1u << 7) /**< \brief (TWIHS_IMR) Underrun Error Interrupt Mask */ +#define TWIHS_IMR_NACK (0x1u << 8) /**< \brief (TWIHS_IMR) Not Acknowledge Interrupt Mask */ +#define TWIHS_IMR_ARBLST (0x1u << 9) /**< \brief (TWIHS_IMR) Arbitration Lost Interrupt Mask */ +#define TWIHS_IMR_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IMR) Clock Wait State Interrupt Mask */ +#define TWIHS_IMR_EOSACC (0x1u << 11) /**< \brief (TWIHS_IMR) End Of Slave Access Interrupt Mask */ +#define TWIHS_IMR_MCACK (0x1u << 16) /**< \brief (TWIHS_IMR) Master Code Acknowledge Interrupt Mask */ +#define TWIHS_IMR_TOUT (0x1u << 18) /**< \brief (TWIHS_IMR) Timeout Error Interrupt Mask */ +#define TWIHS_IMR_PECERR (0x1u << 19) /**< \brief (TWIHS_IMR) PEC Error Interrupt Mask */ +#define TWIHS_IMR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IMR) SMBus Default Address Match Interrupt Mask */ +#define TWIHS_IMR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IMR) SMBus Host Header Address Match Interrupt Mask */ +/* -------- TWIHS_RHR : (TWIHS Offset: 0x30) Receive Holding Register -------- */ +#define TWIHS_RHR_RXDATA_Pos 0 +#define TWIHS_RHR_RXDATA_Msk (0xffu << TWIHS_RHR_RXDATA_Pos) /**< \brief (TWIHS_RHR) Master or Slave Receive Holding Data */ +/* -------- TWIHS_THR : (TWIHS Offset: 0x34) Transmit Holding Register -------- */ +#define TWIHS_THR_TXDATA_Pos 0 +#define TWIHS_THR_TXDATA_Msk (0xffu << TWIHS_THR_TXDATA_Pos) /**< \brief (TWIHS_THR) Master or Slave Transmit Holding Data */ +#define TWIHS_THR_TXDATA(value) ((TWIHS_THR_TXDATA_Msk & ((value) << TWIHS_THR_TXDATA_Pos))) +/* -------- TWIHS_SMBTR : (TWIHS Offset: 0x38) SMBus Timing Register -------- */ +#define TWIHS_SMBTR_PRESC_Pos 0 +#define TWIHS_SMBTR_PRESC_Msk (0xfu << TWIHS_SMBTR_PRESC_Pos) /**< \brief (TWIHS_SMBTR) SMBus Clock Prescaler */ +#define TWIHS_SMBTR_PRESC(value) ((TWIHS_SMBTR_PRESC_Msk & ((value) << TWIHS_SMBTR_PRESC_Pos))) +#define TWIHS_SMBTR_TLOWS_Pos 8 +#define TWIHS_SMBTR_TLOWS_Msk (0xffu << TWIHS_SMBTR_TLOWS_Pos) /**< \brief (TWIHS_SMBTR) Slave Clock Stretch Maximum Cycles */ +#define TWIHS_SMBTR_TLOWS(value) ((TWIHS_SMBTR_TLOWS_Msk & ((value) << TWIHS_SMBTR_TLOWS_Pos))) +#define TWIHS_SMBTR_TLOWM_Pos 16 +#define TWIHS_SMBTR_TLOWM_Msk (0xffu << TWIHS_SMBTR_TLOWM_Pos) /**< \brief (TWIHS_SMBTR) Master Clock Stretch Maximum Cycles */ +#define TWIHS_SMBTR_TLOWM(value) ((TWIHS_SMBTR_TLOWM_Msk & ((value) << TWIHS_SMBTR_TLOWM_Pos))) +#define TWIHS_SMBTR_THMAX_Pos 24 +#define TWIHS_SMBTR_THMAX_Msk (0xffu << TWIHS_SMBTR_THMAX_Pos) /**< \brief (TWIHS_SMBTR) Clock High Maximum Cycles */ +#define TWIHS_SMBTR_THMAX(value) ((TWIHS_SMBTR_THMAX_Msk & ((value) << TWIHS_SMBTR_THMAX_Pos))) +/* -------- TWIHS_FILTR : (TWIHS Offset: 0x44) Filter Register -------- */ +#define TWIHS_FILTR_FILT (0x1u << 0) /**< \brief (TWIHS_FILTR) RX Digital Filter */ +#define TWIHS_FILTR_PADFEN (0x1u << 1) /**< \brief (TWIHS_FILTR) PAD Filter Enable */ +#define TWIHS_FILTR_PADFCFG (0x1u << 2) /**< \brief (TWIHS_FILTR) PAD Filter Config */ +#define TWIHS_FILTR_THRES_Pos 8 +#define TWIHS_FILTR_THRES_Msk (0x7u << TWIHS_FILTR_THRES_Pos) /**< \brief (TWIHS_FILTR) Digital Filter Threshold */ +#define TWIHS_FILTR_THRES(value) ((TWIHS_FILTR_THRES_Msk & ((value) << TWIHS_FILTR_THRES_Pos))) +/* -------- TWIHS_SWMR : (TWIHS Offset: 0x4C) SleepWalking Matching Register -------- */ +#define TWIHS_SWMR_SADR1_Pos 0 +#define TWIHS_SWMR_SADR1_Msk (0x7fu << TWIHS_SWMR_SADR1_Pos) /**< \brief (TWIHS_SWMR) Slave Address 1 */ +#define TWIHS_SWMR_SADR1(value) ((TWIHS_SWMR_SADR1_Msk & ((value) << TWIHS_SWMR_SADR1_Pos))) +#define TWIHS_SWMR_SADR2_Pos 8 +#define TWIHS_SWMR_SADR2_Msk (0x7fu << TWIHS_SWMR_SADR2_Pos) /**< \brief (TWIHS_SWMR) Slave Address 2 */ +#define TWIHS_SWMR_SADR2(value) ((TWIHS_SWMR_SADR2_Msk & ((value) << TWIHS_SWMR_SADR2_Pos))) +#define TWIHS_SWMR_SADR3_Pos 16 +#define TWIHS_SWMR_SADR3_Msk (0x7fu << TWIHS_SWMR_SADR3_Pos) /**< \brief (TWIHS_SWMR) Slave Address 3 */ +#define TWIHS_SWMR_SADR3(value) ((TWIHS_SWMR_SADR3_Msk & ((value) << TWIHS_SWMR_SADR3_Pos))) +#define TWIHS_SWMR_DATAM_Pos 24 +#define TWIHS_SWMR_DATAM_Msk (0xffu << TWIHS_SWMR_DATAM_Pos) /**< \brief (TWIHS_SWMR) Data Match */ +#define TWIHS_SWMR_DATAM(value) ((TWIHS_SWMR_DATAM_Msk & ((value) << TWIHS_SWMR_DATAM_Pos))) +/* -------- TWIHS_WPMR : (TWIHS Offset: 0xE4) Write Protection Mode Register -------- */ +#define TWIHS_WPMR_WPEN (0x1u << 0) /**< \brief (TWIHS_WPMR) Write Protection Enable */ +#define TWIHS_WPMR_WPKEY_Pos 8 +#define TWIHS_WPMR_WPKEY_Msk (0xffffffu << TWIHS_WPMR_WPKEY_Pos) /**< \brief (TWIHS_WPMR) Write Protection Key */ +#define TWIHS_WPMR_WPKEY(value) ((TWIHS_WPMR_WPKEY_Msk & ((value) << TWIHS_WPMR_WPKEY_Pos))) +#define TWIHS_WPMR_WPKEY_PASSWD (0x545749u << 8) /**< \brief (TWIHS_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 */ +/* -------- TWIHS_WPSR : (TWIHS Offset: 0xE8) Write Protection Status Register -------- */ +#define TWIHS_WPSR_WPVS (0x1u << 0) /**< \brief (TWIHS_WPSR) Write Protection Violation Status */ +#define TWIHS_WPSR_WPVSRC_Pos 8 +#define TWIHS_WPSR_WPVSRC_Msk (0xffffffu << TWIHS_WPSR_WPVSRC_Pos) /**< \brief (TWIHS_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAMV71_TWIHS_COMPONENT_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_uart.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_uart.h new file mode 100644 index 00000000..0f8b5fc7 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_uart.h @@ -0,0 +1,151 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_UART_COMPONENT_ +#define _SAMV71_UART_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */ +/* ============================================================================= */ +/** \addtogroup SAMV71_UART Universal Asynchronous Receiver Transmitter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Uart hardware registers */ +typedef struct { + __O uint32_t UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */ + __IO uint32_t UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */ + __O uint32_t UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */ + __O uint32_t UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */ + __I uint32_t UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */ + __I uint32_t UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */ + __I uint32_t UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */ + __O uint32_t UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */ + __IO uint32_t UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */ + __IO uint32_t UART_CMPR; /**< \brief (Uart Offset: 0x0024) Comparison Register */ + __I uint32_t Reserved1[47]; + __IO uint32_t UART_WPMR; /**< \brief (Uart Offset: 0x00E4) Write Protection Mode Register */ +} Uart; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */ +#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */ +#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */ +#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */ +#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */ +#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */ +#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */ +#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status */ +#define UART_CR_REQCLR (0x1u << 12) /**< \brief (UART_CR) Request Clear */ +/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */ +#define UART_MR_FILTER (0x1u << 4) /**< \brief (UART_MR) Receiver Digital Filter */ +#define UART_MR_FILTER_DISABLED (0x0u << 4) /**< \brief (UART_MR) UART does not filter the receive line. */ +#define UART_MR_FILTER_ENABLED (0x1u << 4) /**< \brief (UART_MR) UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). */ +#define UART_MR_PAR_Pos 9 +#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */ +#define UART_MR_PAR(value) ((UART_MR_PAR_Msk & ((value) << UART_MR_PAR_Pos))) +#define UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even Parity */ +#define UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd Parity */ +#define UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */ +#define UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */ +#define UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */ +#define UART_MR_BRSRCCK (0x1u << 12) /**< \brief (UART_MR) Baud Rate Source Clock */ +#define UART_MR_BRSRCCK_PERIPH_CLK (0x0u << 12) /**< \brief (UART_MR) The baud rate is driven by the peripheral clock */ +#define UART_MR_BRSRCCK_PMC_PCK (0x1u << 12) /**< \brief (UART_MR) The baud rate is driven by a PMC programmable clock PCK (see section Power Management Controller (PMC)). */ +#define UART_MR_CHMODE_Pos 14 +#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */ +#define UART_MR_CHMODE(value) ((UART_MR_CHMODE_Msk & ((value) << UART_MR_CHMODE_Pos))) +#define UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal mode */ +#define UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic echo */ +#define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local loopback */ +#define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote loopback */ +/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */ +#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */ +#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */ +#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */ +#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */ +#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */ +#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */ +#define UART_IER_CMP (0x1u << 15) /**< \brief (UART_IER) Enable Comparison Interrupt */ +/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */ +#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */ +#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */ +#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */ +#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */ +#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */ +#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */ +#define UART_IDR_CMP (0x1u << 15) /**< \brief (UART_IDR) Disable Comparison Interrupt */ +/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */ +#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */ +#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */ +#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */ +#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */ +#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */ +#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */ +#define UART_IMR_CMP (0x1u << 15) /**< \brief (UART_IMR) Mask Comparison Interrupt */ +/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */ +#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */ +#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */ +#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */ +#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */ +#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */ +#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */ +#define UART_SR_CMP (0x1u << 15) /**< \brief (UART_SR) Comparison Match */ +/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */ +#define UART_RHR_RXCHR_Pos 0 +#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */ +/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */ +#define UART_THR_TXCHR_Pos 0 +#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */ +#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos))) +/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */ +#define UART_BRGR_CD_Pos 0 +#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */ +#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos))) +/* -------- UART_CMPR : (UART Offset: 0x0024) Comparison Register -------- */ +#define UART_CMPR_VAL1_Pos 0 +#define UART_CMPR_VAL1_Msk (0xffu << UART_CMPR_VAL1_Pos) /**< \brief (UART_CMPR) First Comparison Value for Received Character */ +#define UART_CMPR_VAL1(value) ((UART_CMPR_VAL1_Msk & ((value) << UART_CMPR_VAL1_Pos))) +#define UART_CMPR_CMPMODE (0x1u << 12) /**< \brief (UART_CMPR) Comparison Mode */ +#define UART_CMPR_CMPMODE_FLAG_ONLY (0x0u << 12) /**< \brief (UART_CMPR) Any character is received and comparison function drives CMP flag. */ +#define UART_CMPR_CMPMODE_START_CONDITION (0x1u << 12) /**< \brief (UART_CMPR) Comparison condition must be met to start reception. */ +#define UART_CMPR_CMPPAR (0x1u << 14) /**< \brief (UART_CMPR) Compare Parity */ +#define UART_CMPR_VAL2_Pos 16 +#define UART_CMPR_VAL2_Msk (0xffu << UART_CMPR_VAL2_Pos) /**< \brief (UART_CMPR) Second Comparison Value for Received Character */ +#define UART_CMPR_VAL2(value) ((UART_CMPR_VAL2_Msk & ((value) << UART_CMPR_VAL2_Pos))) +/* -------- UART_WPMR : (UART Offset: 0x00E4) Write Protection Mode Register -------- */ +#define UART_WPMR_WPEN (0x1u << 0) /**< \brief (UART_WPMR) Write Protection Enable */ +#define UART_WPMR_WPKEY_Pos 8 +#define UART_WPMR_WPKEY_Msk (0xffffffu << UART_WPMR_WPKEY_Pos) /**< \brief (UART_WPMR) Write Protection Key */ +#define UART_WPMR_WPKEY(value) ((UART_WPMR_WPKEY_Msk & ((value) << UART_WPMR_WPKEY_Pos))) +#define UART_WPMR_WPKEY_PASSWD (0x554152u << 8) /**< \brief (UART_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAMV71_UART_COMPONENT_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_uotghs.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_uotghs.h new file mode 100644 index 00000000..09e596d3 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_uotghs.h @@ -0,0 +1,1033 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM_UOTGHS_COMPONENT_ +#define _SAM_UOTGHS_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR USB On-The-Go Interface */ +/* ============================================================================= */ +/** \addtogroup SAM_UOTGHS USB On-The-Go Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief UotghsDevdma hardware registers */ +typedef struct { + __IO uint32_t UOTGHS_DEVDMANXTDSC; /**< \brief (UotghsDevdma Offset: 0x0) Device DMA Channel Next Descriptor Address Register */ + __IO uint32_t UOTGHS_DEVDMAADDRESS; /**< \brief (UotghsDevdma Offset: 0x4) Device DMA Channel Address Register */ + __IO uint32_t UOTGHS_DEVDMACONTROL; /**< \brief (UotghsDevdma Offset: 0x8) Device DMA Channel Control Register */ + __IO uint32_t UOTGHS_DEVDMASTATUS; /**< \brief (UotghsDevdma Offset: 0xC) Device DMA Channel Status Register */ +} UotghsDevdma; +/** \brief UotghsHstdma hardware registers */ +typedef struct { + __IO uint32_t UOTGHS_HSTDMANXTDSC; /**< \brief (UotghsHstdma Offset: 0x0) Host DMA Channel Next Descriptor Address Register */ + __IO uint32_t UOTGHS_HSTDMAADDRESS; /**< \brief (UotghsHstdma Offset: 0x4) Host DMA Channel Address Register */ + __IO uint32_t UOTGHS_HSTDMACONTROL; /**< \brief (UotghsHstdma Offset: 0x8) Host DMA Channel Control Register */ + __IO uint32_t UOTGHS_HSTDMASTATUS; /**< \brief (UotghsHstdma Offset: 0xC) Host DMA Channel Status Register */ +} UotghsHstdma; +/** \brief Uotghs hardware registers */ +#define UOTGHSDEVDMA_NUMBER 7 +#define UOTGHSHSTDMA_NUMBER 7 +typedef struct { + __IO uint32_t UOTGHS_DEVCTRL; /**< \brief (Uotghs Offset: 0x0000) Device General Control Register */ + __I uint32_t UOTGHS_DEVISR; /**< \brief (Uotghs Offset: 0x0004) Device Global Interrupt Status Register */ + __O uint32_t UOTGHS_DEVICR; /**< \brief (Uotghs Offset: 0x0008) Device Global Interrupt Clear Register */ + __O uint32_t UOTGHS_DEVIFR; /**< \brief (Uotghs Offset: 0x000C) Device Global Interrupt Set Register */ + __I uint32_t UOTGHS_DEVIMR; /**< \brief (Uotghs Offset: 0x0010) Device Global Interrupt Mask Register */ + __O uint32_t UOTGHS_DEVIDR; /**< \brief (Uotghs Offset: 0x0014) Device Global Interrupt Disable Register */ + __O uint32_t UOTGHS_DEVIER; /**< \brief (Uotghs Offset: 0x0018) Device Global Interrupt Enable Register */ + __IO uint32_t UOTGHS_DEVEPT; /**< \brief (Uotghs Offset: 0x001C) Device Endpoint Register */ + __I uint32_t UOTGHS_DEVFNUM; /**< \brief (Uotghs Offset: 0x0020) Device Frame Number Register */ + __I uint32_t Reserved1[55]; + __IO uint32_t UOTGHS_DEVEPTCFG[12]; /**< \brief (Uotghs Offset: 0x100) Device Endpoint Configuration Register (n = 0) */ + __I uint32_t UOTGHS_DEVEPTISR[12]; /**< \brief (Uotghs Offset: 0x130) Device Endpoint Status Register (n = 0) */ + __O uint32_t UOTGHS_DEVEPTICR[12]; /**< \brief (Uotghs Offset: 0x160) Device Endpoint Clear Register (n = 0) */ + __O uint32_t UOTGHS_DEVEPTIFR[12]; /**< \brief (Uotghs Offset: 0x190) Device Endpoint Set Register (n = 0) */ + __I uint32_t UOTGHS_DEVEPTIMR[12]; /**< \brief (Uotghs Offset: 0x1C0) Device Endpoint Mask Register (n = 0) */ + __O uint32_t UOTGHS_DEVEPTIER[12]; /**< \brief (Uotghs Offset: 0x1F0) Device Endpoint Enable Register (n = 0) */ + __O uint32_t UOTGHS_DEVEPTIDR[12]; /**< \brief (Uotghs Offset: 0x220) Device Endpoint Disable Register (n = 0) */ + __I uint32_t Reserved2[48]; + UotghsDevdma UOTGHS_DEVDMA[UOTGHSDEVDMA_NUMBER]; /**< \brief (Uotghs Offset: 0x310) n = 1 .. 7 */ + __I uint32_t Reserved3[32]; + __IO uint32_t UOTGHS_HSTCTRL; /**< \brief (Uotghs Offset: 0x0400) Host General Control Register */ + __I uint32_t UOTGHS_HSTISR; /**< \brief (Uotghs Offset: 0x0404) Host Global Interrupt Status Register */ + __O uint32_t UOTGHS_HSTICR; /**< \brief (Uotghs Offset: 0x0408) Host Global Interrupt Clear Register */ + __O uint32_t UOTGHS_HSTIFR; /**< \brief (Uotghs Offset: 0x040C) Host Global Interrupt Set Register */ + __I uint32_t UOTGHS_HSTIMR; /**< \brief (Uotghs Offset: 0x0410) Host Global Interrupt Mask Register */ + __O uint32_t UOTGHS_HSTIDR; /**< \brief (Uotghs Offset: 0x0414) Host Global Interrupt Disable Register */ + __O uint32_t UOTGHS_HSTIER; /**< \brief (Uotghs Offset: 0x0418) Host Global Interrupt Enable Register */ + __IO uint32_t UOTGHS_HSTPIP; /**< \brief (Uotghs Offset: 0x0041C) Host Pipe Register */ + __IO uint32_t UOTGHS_HSTFNUM; /**< \brief (Uotghs Offset: 0x0420) Host Frame Number Register */ + __IO uint32_t UOTGHS_HSTADDR1; /**< \brief (Uotghs Offset: 0x0424) Host Address 1 Register */ + __IO uint32_t UOTGHS_HSTADDR2; /**< \brief (Uotghs Offset: 0x0428) Host Address 2 Register */ + __IO uint32_t UOTGHS_HSTADDR3; /**< \brief (Uotghs Offset: 0x042C) Host Address 3 Register */ + __I uint32_t Reserved4[52]; + __IO uint32_t UOTGHS_HSTPIPCFG[12]; /**< \brief (Uotghs Offset: 0x500) Host Pipe Configuration Register (n = 0) */ + __I uint32_t UOTGHS_HSTPIPISR[12]; /**< \brief (Uotghs Offset: 0x530) Host Pipe Status Register (n = 0) */ + __O uint32_t UOTGHS_HSTPIPICR[12]; /**< \brief (Uotghs Offset: 0x560) Host Pipe Clear Register (n = 0) */ + __O uint32_t UOTGHS_HSTPIPIFR[12]; /**< \brief (Uotghs Offset: 0x590) Host Pipe Set Register (n = 0) */ + __I uint32_t UOTGHS_HSTPIPIMR[12]; /**< \brief (Uotghs Offset: 0x5C0) Host Pipe Mask Register (n = 0) */ + __O uint32_t UOTGHS_HSTPIPIER[12]; /**< \brief (Uotghs Offset: 0x5F0) Host Pipe Enable Register (n = 0) */ + __O uint32_t UOTGHS_HSTPIPIDR[12]; /**< \brief (Uotghs Offset: 0x620) Host Pipe Disable Register (n = 0) */ + __IO uint32_t UOTGHS_HSTPIPINRQ[12]; /**< \brief (Uotghs Offset: 0x650) Host Pipe IN Request Register (n = 0) */ + __IO uint32_t UOTGHS_HSTPIPERR[12]; /**< \brief (Uotghs Offset: 0x680) Host Pipe Error Register (n = 0) */ + __I uint32_t Reserved5[24]; + UotghsHstdma UOTGHS_HSTDMA[UOTGHSHSTDMA_NUMBER]; /**< \brief (Uotghs Offset: 0x710) n = 1 .. 7 */ + __I uint32_t Reserved6[32]; + __IO uint32_t UOTGHS_CTRL; /**< \brief (Uotghs Offset: 0x0800) General Control Register */ + __I uint32_t UOTGHS_SR; /**< \brief (Uotghs Offset: 0x0804) General Status Register */ + __O uint32_t UOTGHS_SCR; /**< \brief (Uotghs Offset: 0x0808) General Status Clear Register */ + __O uint32_t UOTGHS_SFR; /**< \brief (Uotghs Offset: 0x080C) General Status Set Register */ + __IO uint32_t UOTGHS_TSTA1; /**< \brief (Uotghs Offset: 0x0810) General Test A1 Register */ + __IO uint32_t UOTGHS_TSTA2; /**< \brief (Uotghs Offset: 0x0814) General Test A2 Register */ + __I uint32_t UOTGHS_VERSION; /**< \brief (Uotghs Offset: 0x0818) General Version Register */ + __I uint32_t UOTGHS_FEATURES; /**< \brief (Uotghs Offset: 0x081C) General Features Register */ + __I uint32_t UOTGHS_ADDRSIZE; /**< \brief (Uotghs Offset: 0x0820) General APB Address Size Register */ + __I uint32_t UOTGHS_IPNAME1; /**< \brief (Uotghs Offset: 0x0824) General Name Register 1 */ + __I uint32_t UOTGHS_IPNAME2; /**< \brief (Uotghs Offset: 0x0828) General Name Register 2 */ + __I uint32_t UOTGHS_FSM; /**< \brief (Uotghs Offset: 0x082C) General Finite State Machine Register */ +} Uotghs; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- UOTGHS_DEVCTRL : (UOTGHS Offset: 0x0000) Device General Control Register -------- */ +#define UOTGHS_DEVCTRL_UADD_Pos 0 +#define UOTGHS_DEVCTRL_UADD_Msk (0x7fu << UOTGHS_DEVCTRL_UADD_Pos) /**< \brief (UOTGHS_DEVCTRL) USB Address */ +#define UOTGHS_DEVCTRL_UADD(value) ((UOTGHS_DEVCTRL_UADD_Msk & ((value) << UOTGHS_DEVCTRL_UADD_Pos))) +#define UOTGHS_DEVCTRL_ADDEN (0x1u << 7) /**< \brief (UOTGHS_DEVCTRL) Address Enable */ +#define UOTGHS_DEVCTRL_DETACH (0x1u << 8) /**< \brief (UOTGHS_DEVCTRL) Detach */ +#define UOTGHS_DEVCTRL_RMWKUP (0x1u << 9) /**< \brief (UOTGHS_DEVCTRL) Remote Wake-Up */ +#define UOTGHS_DEVCTRL_SPDCONF_Pos 10 +#define UOTGHS_DEVCTRL_SPDCONF_Msk (0x3u << UOTGHS_DEVCTRL_SPDCONF_Pos) /**< \brief (UOTGHS_DEVCTRL) Mode Configuration */ +#define UOTGHS_DEVCTRL_SPDCONF_NORMAL (0x0u << 10) /**< \brief (UOTGHS_DEVCTRL) The peripheral starts in full-speed mode and performs a high-speed reset to switch to the high-speed mode if the host is high-speed capable. */ +#define UOTGHS_DEVCTRL_SPDCONF_LOW_POWER (0x1u << 10) /**< \brief (UOTGHS_DEVCTRL) For a better consumption, if high-speed is not needed. */ +#define UOTGHS_DEVCTRL_SPDCONF_HIGH_SPEED (0x2u << 10) /**< \brief (UOTGHS_DEVCTRL) Forced high speed. */ +#define UOTGHS_DEVCTRL_SPDCONF_FORCED_FS (0x3u << 10) /**< \brief (UOTGHS_DEVCTRL) The peripheral remains in full-speed mode whatever the host speed capability. */ +#define UOTGHS_DEVCTRL_LS (0x1u << 12) /**< \brief (UOTGHS_DEVCTRL) Low-Speed Mode Force */ +#define UOTGHS_DEVCTRL_TSTJ (0x1u << 13) /**< \brief (UOTGHS_DEVCTRL) Test mode J */ +#define UOTGHS_DEVCTRL_TSTK (0x1u << 14) /**< \brief (UOTGHS_DEVCTRL) Test mode K */ +#define UOTGHS_DEVCTRL_TSTPCKT (0x1u << 15) /**< \brief (UOTGHS_DEVCTRL) Test packet mode */ +#define UOTGHS_DEVCTRL_OPMODE2 (0x1u << 16) /**< \brief (UOTGHS_DEVCTRL) Specific Operational mode */ +/* -------- UOTGHS_DEVISR : (UOTGHS Offset: 0x0004) Device Global Interrupt Status Register -------- */ +#define UOTGHS_DEVISR_SUSP (0x1u << 0) /**< \brief (UOTGHS_DEVISR) Suspend Interrupt */ +#define UOTGHS_DEVISR_MSOF (0x1u << 1) /**< \brief (UOTGHS_DEVISR) Micro Start of Frame Interrupt */ +#define UOTGHS_DEVISR_SOF (0x1u << 2) /**< \brief (UOTGHS_DEVISR) Start of Frame Interrupt */ +#define UOTGHS_DEVISR_EORST (0x1u << 3) /**< \brief (UOTGHS_DEVISR) End of Reset Interrupt */ +#define UOTGHS_DEVISR_WAKEUP (0x1u << 4) /**< \brief (UOTGHS_DEVISR) Wake-Up Interrupt */ +#define UOTGHS_DEVISR_EORSM (0x1u << 5) /**< \brief (UOTGHS_DEVISR) End of Resume Interrupt */ +#define UOTGHS_DEVISR_UPRSM (0x1u << 6) /**< \brief (UOTGHS_DEVISR) Upstream Resume Interrupt */ +#define UOTGHS_DEVISR_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVISR) Endpoint 0 Interrupt */ +#define UOTGHS_DEVISR_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVISR) Endpoint 1 Interrupt */ +#define UOTGHS_DEVISR_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVISR) Endpoint 2 Interrupt */ +#define UOTGHS_DEVISR_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVISR) Endpoint 3 Interrupt */ +#define UOTGHS_DEVISR_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVISR) Endpoint 4 Interrupt */ +#define UOTGHS_DEVISR_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVISR) Endpoint 5 Interrupt */ +#define UOTGHS_DEVISR_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVISR) Endpoint 6 Interrupt */ +#define UOTGHS_DEVISR_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVISR) Endpoint 7 Interrupt */ +#define UOTGHS_DEVISR_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVISR) Endpoint 8 Interrupt */ +#define UOTGHS_DEVISR_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVISR) Endpoint 9 Interrupt */ +#define UOTGHS_DEVISR_PEP_10 (0x1u << 22) /**< \brief (UOTGHS_DEVISR) Endpoint 10 Interrupt */ +#define UOTGHS_DEVISR_PEP_11 (0x1u << 23) /**< \brief (UOTGHS_DEVISR) Endpoint 11 Interrupt */ +#define UOTGHS_DEVISR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVISR) DMA Channel 1 Interrupt */ +#define UOTGHS_DEVISR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVISR) DMA Channel 2 Interrupt */ +#define UOTGHS_DEVISR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVISR) DMA Channel 3 Interrupt */ +#define UOTGHS_DEVISR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVISR) DMA Channel 4 Interrupt */ +#define UOTGHS_DEVISR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVISR) DMA Channel 5 Interrupt */ +#define UOTGHS_DEVISR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVISR) DMA Channel 6 Interrupt */ +#define UOTGHS_DEVISR_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_DEVISR) DMA Channel 7 Interrupt */ +/* -------- UOTGHS_DEVICR : (UOTGHS Offset: 0x0008) Device Global Interrupt Clear Register -------- */ +#define UOTGHS_DEVICR_SUSPC (0x1u << 0) /**< \brief (UOTGHS_DEVICR) Suspend Interrupt Clear */ +#define UOTGHS_DEVICR_MSOFC (0x1u << 1) /**< \brief (UOTGHS_DEVICR) Micro Start of Frame Interrupt Clear */ +#define UOTGHS_DEVICR_SOFC (0x1u << 2) /**< \brief (UOTGHS_DEVICR) Start of Frame Interrupt Clear */ +#define UOTGHS_DEVICR_EORSTC (0x1u << 3) /**< \brief (UOTGHS_DEVICR) End of Reset Interrupt Clear */ +#define UOTGHS_DEVICR_WAKEUPC (0x1u << 4) /**< \brief (UOTGHS_DEVICR) Wake-Up Interrupt Clear */ +#define UOTGHS_DEVICR_EORSMC (0x1u << 5) /**< \brief (UOTGHS_DEVICR) End of Resume Interrupt Clear */ +#define UOTGHS_DEVICR_UPRSMC (0x1u << 6) /**< \brief (UOTGHS_DEVICR) Upstream Resume Interrupt Clear */ +/* -------- UOTGHS_DEVIFR : (UOTGHS Offset: 0x000C) Device Global Interrupt Set Register -------- */ +#define UOTGHS_DEVIFR_SUSPS (0x1u << 0) /**< \brief (UOTGHS_DEVIFR) Suspend Interrupt Set */ +#define UOTGHS_DEVIFR_MSOFS (0x1u << 1) /**< \brief (UOTGHS_DEVIFR) Micro Start of Frame Interrupt Set */ +#define UOTGHS_DEVIFR_SOFS (0x1u << 2) /**< \brief (UOTGHS_DEVIFR) Start of Frame Interrupt Set */ +#define UOTGHS_DEVIFR_EORSTS (0x1u << 3) /**< \brief (UOTGHS_DEVIFR) End of Reset Interrupt Set */ +#define UOTGHS_DEVIFR_WAKEUPS (0x1u << 4) /**< \brief (UOTGHS_DEVIFR) Wake-Up Interrupt Set */ +#define UOTGHS_DEVIFR_EORSMS (0x1u << 5) /**< \brief (UOTGHS_DEVIFR) End of Resume Interrupt Set */ +#define UOTGHS_DEVIFR_UPRSMS (0x1u << 6) /**< \brief (UOTGHS_DEVIFR) Upstream Resume Interrupt Set */ +#define UOTGHS_DEVIFR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIFR) DMA Channel 1 Interrupt Set */ +#define UOTGHS_DEVIFR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIFR) DMA Channel 2 Interrupt Set */ +#define UOTGHS_DEVIFR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIFR) DMA Channel 3 Interrupt Set */ +#define UOTGHS_DEVIFR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIFR) DMA Channel 4 Interrupt Set */ +#define UOTGHS_DEVIFR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIFR) DMA Channel 5 Interrupt Set */ +#define UOTGHS_DEVIFR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIFR) DMA Channel 6 Interrupt Set */ +#define UOTGHS_DEVIFR_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_DEVIFR) DMA Channel 7 Interrupt Set */ +/* -------- UOTGHS_DEVIMR : (UOTGHS Offset: 0x0010) Device Global Interrupt Mask Register -------- */ +#define UOTGHS_DEVIMR_SUSPE (0x1u << 0) /**< \brief (UOTGHS_DEVIMR) Suspend Interrupt Mask */ +#define UOTGHS_DEVIMR_MSOFE (0x1u << 1) /**< \brief (UOTGHS_DEVIMR) Micro Start of Frame Interrupt Mask */ +#define UOTGHS_DEVIMR_SOFE (0x1u << 2) /**< \brief (UOTGHS_DEVIMR) Start of Frame Interrupt Mask */ +#define UOTGHS_DEVIMR_EORSTE (0x1u << 3) /**< \brief (UOTGHS_DEVIMR) End of Reset Interrupt Mask */ +#define UOTGHS_DEVIMR_WAKEUPE (0x1u << 4) /**< \brief (UOTGHS_DEVIMR) Wake-Up Interrupt Mask */ +#define UOTGHS_DEVIMR_EORSME (0x1u << 5) /**< \brief (UOTGHS_DEVIMR) End of Resume Interrupt Mask */ +#define UOTGHS_DEVIMR_UPRSME (0x1u << 6) /**< \brief (UOTGHS_DEVIMR) Upstream Resume Interrupt Mask */ +#define UOTGHS_DEVIMR_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVIMR) Endpoint 0 Interrupt Mask */ +#define UOTGHS_DEVIMR_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVIMR) Endpoint 1 Interrupt Mask */ +#define UOTGHS_DEVIMR_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVIMR) Endpoint 2 Interrupt Mask */ +#define UOTGHS_DEVIMR_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVIMR) Endpoint 3 Interrupt Mask */ +#define UOTGHS_DEVIMR_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVIMR) Endpoint 4 Interrupt Mask */ +#define UOTGHS_DEVIMR_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVIMR) Endpoint 5 Interrupt Mask */ +#define UOTGHS_DEVIMR_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVIMR) Endpoint 6 Interrupt Mask */ +#define UOTGHS_DEVIMR_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVIMR) Endpoint 7 Interrupt Mask */ +#define UOTGHS_DEVIMR_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVIMR) Endpoint 8 Interrupt Mask */ +#define UOTGHS_DEVIMR_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVIMR) Endpoint 9 Interrupt Mask */ +#define UOTGHS_DEVIMR_PEP_10 (0x1u << 22) /**< \brief (UOTGHS_DEVIMR) Endpoint 10 Interrupt Mask */ +#define UOTGHS_DEVIMR_PEP_11 (0x1u << 23) /**< \brief (UOTGHS_DEVIMR) Endpoint 11 Interrupt Mask */ +#define UOTGHS_DEVIMR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIMR) DMA Channel 1 Interrupt Mask */ +#define UOTGHS_DEVIMR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIMR) DMA Channel 2 Interrupt Mask */ +#define UOTGHS_DEVIMR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIMR) DMA Channel 3 Interrupt Mask */ +#define UOTGHS_DEVIMR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIMR) DMA Channel 4 Interrupt Mask */ +#define UOTGHS_DEVIMR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIMR) DMA Channel 5 Interrupt Mask */ +#define UOTGHS_DEVIMR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIMR) DMA Channel 6 Interrupt Mask */ +#define UOTGHS_DEVIMR_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_DEVIMR) DMA Channel 7 Interrupt Mask */ +/* -------- UOTGHS_DEVIDR : (UOTGHS Offset: 0x0014) Device Global Interrupt Disable Register -------- */ +#define UOTGHS_DEVIDR_SUSPEC (0x1u << 0) /**< \brief (UOTGHS_DEVIDR) Suspend Interrupt Disable */ +#define UOTGHS_DEVIDR_MSOFEC (0x1u << 1) /**< \brief (UOTGHS_DEVIDR) Micro Start of Frame Interrupt Disable */ +#define UOTGHS_DEVIDR_SOFEC (0x1u << 2) /**< \brief (UOTGHS_DEVIDR) Start of Frame Interrupt Disable */ +#define UOTGHS_DEVIDR_EORSTEC (0x1u << 3) /**< \brief (UOTGHS_DEVIDR) End of Reset Interrupt Disable */ +#define UOTGHS_DEVIDR_WAKEUPEC (0x1u << 4) /**< \brief (UOTGHS_DEVIDR) Wake-Up Interrupt Disable */ +#define UOTGHS_DEVIDR_EORSMEC (0x1u << 5) /**< \brief (UOTGHS_DEVIDR) End of Resume Interrupt Disable */ +#define UOTGHS_DEVIDR_UPRSMEC (0x1u << 6) /**< \brief (UOTGHS_DEVIDR) Upstream Resume Interrupt Disable */ +#define UOTGHS_DEVIDR_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVIDR) Endpoint 0 Interrupt Disable */ +#define UOTGHS_DEVIDR_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVIDR) Endpoint 1 Interrupt Disable */ +#define UOTGHS_DEVIDR_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVIDR) Endpoint 2 Interrupt Disable */ +#define UOTGHS_DEVIDR_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVIDR) Endpoint 3 Interrupt Disable */ +#define UOTGHS_DEVIDR_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVIDR) Endpoint 4 Interrupt Disable */ +#define UOTGHS_DEVIDR_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVIDR) Endpoint 5 Interrupt Disable */ +#define UOTGHS_DEVIDR_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVIDR) Endpoint 6 Interrupt Disable */ +#define UOTGHS_DEVIDR_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVIDR) Endpoint 7 Interrupt Disable */ +#define UOTGHS_DEVIDR_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVIDR) Endpoint 8 Interrupt Disable */ +#define UOTGHS_DEVIDR_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVIDR) Endpoint 9 Interrupt Disable */ +#define UOTGHS_DEVIDR_PEP_10 (0x1u << 22) /**< \brief (UOTGHS_DEVIDR) Endpoint 10 Interrupt Disable */ +#define UOTGHS_DEVIDR_PEP_11 (0x1u << 23) /**< \brief (UOTGHS_DEVIDR) Endpoint 11 Interrupt Disable */ +#define UOTGHS_DEVIDR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIDR) DMA Channel 1 Interrupt Disable */ +#define UOTGHS_DEVIDR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIDR) DMA Channel 2 Interrupt Disable */ +#define UOTGHS_DEVIDR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIDR) DMA Channel 3 Interrupt Disable */ +#define UOTGHS_DEVIDR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIDR) DMA Channel 4 Interrupt Disable */ +#define UOTGHS_DEVIDR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIDR) DMA Channel 5 Interrupt Disable */ +#define UOTGHS_DEVIDR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIDR) DMA Channel 6 Interrupt Disable */ +#define UOTGHS_DEVIDR_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_DEVIDR) DMA Channel 7 Interrupt Disable */ +/* -------- UOTGHS_DEVIER : (UOTGHS Offset: 0x0018) Device Global Interrupt Enable Register -------- */ +#define UOTGHS_DEVIER_SUSPES (0x1u << 0) /**< \brief (UOTGHS_DEVIER) Suspend Interrupt Enable */ +#define UOTGHS_DEVIER_MSOFES (0x1u << 1) /**< \brief (UOTGHS_DEVIER) Micro Start of Frame Interrupt Enable */ +#define UOTGHS_DEVIER_SOFES (0x1u << 2) /**< \brief (UOTGHS_DEVIER) Start of Frame Interrupt Enable */ +#define UOTGHS_DEVIER_EORSTES (0x1u << 3) /**< \brief (UOTGHS_DEVIER) End of Reset Interrupt Enable */ +#define UOTGHS_DEVIER_WAKEUPES (0x1u << 4) /**< \brief (UOTGHS_DEVIER) Wake-Up Interrupt Enable */ +#define UOTGHS_DEVIER_EORSMES (0x1u << 5) /**< \brief (UOTGHS_DEVIER) End of Resume Interrupt Enable */ +#define UOTGHS_DEVIER_UPRSMES (0x1u << 6) /**< \brief (UOTGHS_DEVIER) Upstream Resume Interrupt Enable */ +#define UOTGHS_DEVIER_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVIER) Endpoint 0 Interrupt Enable */ +#define UOTGHS_DEVIER_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVIER) Endpoint 1 Interrupt Enable */ +#define UOTGHS_DEVIER_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVIER) Endpoint 2 Interrupt Enable */ +#define UOTGHS_DEVIER_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVIER) Endpoint 3 Interrupt Enable */ +#define UOTGHS_DEVIER_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVIER) Endpoint 4 Interrupt Enable */ +#define UOTGHS_DEVIER_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVIER) Endpoint 5 Interrupt Enable */ +#define UOTGHS_DEVIER_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVIER) Endpoint 6 Interrupt Enable */ +#define UOTGHS_DEVIER_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVIER) Endpoint 7 Interrupt Enable */ +#define UOTGHS_DEVIER_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVIER) Endpoint 8 Interrupt Enable */ +#define UOTGHS_DEVIER_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVIER) Endpoint 9 Interrupt Enable */ +#define UOTGHS_DEVIER_PEP_10 (0x1u << 22) /**< \brief (UOTGHS_DEVIER) Endpoint 10 Interrupt Enable */ +#define UOTGHS_DEVIER_PEP_11 (0x1u << 23) /**< \brief (UOTGHS_DEVIER) Endpoint 11 Interrupt Enable */ +#define UOTGHS_DEVIER_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIER) DMA Channel 1 Interrupt Enable */ +#define UOTGHS_DEVIER_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIER) DMA Channel 2 Interrupt Enable */ +#define UOTGHS_DEVIER_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIER) DMA Channel 3 Interrupt Enable */ +#define UOTGHS_DEVIER_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIER) DMA Channel 4 Interrupt Enable */ +#define UOTGHS_DEVIER_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIER) DMA Channel 5 Interrupt Enable */ +#define UOTGHS_DEVIER_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIER) DMA Channel 6 Interrupt Enable */ +#define UOTGHS_DEVIER_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_DEVIER) DMA Channel 7 Interrupt Enable */ +/* -------- UOTGHS_DEVEPT : (UOTGHS Offset: 0x001C) Device Endpoint Register -------- */ +#define UOTGHS_DEVEPT_EPEN0 (0x1u << 0) /**< \brief (UOTGHS_DEVEPT) Endpoint 0 Enable */ +#define UOTGHS_DEVEPT_EPEN1 (0x1u << 1) /**< \brief (UOTGHS_DEVEPT) Endpoint 1 Enable */ +#define UOTGHS_DEVEPT_EPEN2 (0x1u << 2) /**< \brief (UOTGHS_DEVEPT) Endpoint 2 Enable */ +#define UOTGHS_DEVEPT_EPEN3 (0x1u << 3) /**< \brief (UOTGHS_DEVEPT) Endpoint 3 Enable */ +#define UOTGHS_DEVEPT_EPEN4 (0x1u << 4) /**< \brief (UOTGHS_DEVEPT) Endpoint 4 Enable */ +#define UOTGHS_DEVEPT_EPEN5 (0x1u << 5) /**< \brief (UOTGHS_DEVEPT) Endpoint 5 Enable */ +#define UOTGHS_DEVEPT_EPEN6 (0x1u << 6) /**< \brief (UOTGHS_DEVEPT) Endpoint 6 Enable */ +#define UOTGHS_DEVEPT_EPEN7 (0x1u << 7) /**< \brief (UOTGHS_DEVEPT) Endpoint 7 Enable */ +#define UOTGHS_DEVEPT_EPEN8 (0x1u << 8) /**< \brief (UOTGHS_DEVEPT) Endpoint 8 Enable */ +#define UOTGHS_DEVEPT_EPRST0 (0x1u << 16) /**< \brief (UOTGHS_DEVEPT) Endpoint 0 Reset */ +#define UOTGHS_DEVEPT_EPRST1 (0x1u << 17) /**< \brief (UOTGHS_DEVEPT) Endpoint 1 Reset */ +#define UOTGHS_DEVEPT_EPRST2 (0x1u << 18) /**< \brief (UOTGHS_DEVEPT) Endpoint 2 Reset */ +#define UOTGHS_DEVEPT_EPRST3 (0x1u << 19) /**< \brief (UOTGHS_DEVEPT) Endpoint 3 Reset */ +#define UOTGHS_DEVEPT_EPRST4 (0x1u << 20) /**< \brief (UOTGHS_DEVEPT) Endpoint 4 Reset */ +#define UOTGHS_DEVEPT_EPRST5 (0x1u << 21) /**< \brief (UOTGHS_DEVEPT) Endpoint 5 Reset */ +#define UOTGHS_DEVEPT_EPRST6 (0x1u << 22) /**< \brief (UOTGHS_DEVEPT) Endpoint 6 Reset */ +#define UOTGHS_DEVEPT_EPRST7 (0x1u << 23) /**< \brief (UOTGHS_DEVEPT) Endpoint 7 Reset */ +#define UOTGHS_DEVEPT_EPRST8 (0x1u << 24) /**< \brief (UOTGHS_DEVEPT) Endpoint 8 Reset */ +/* -------- UOTGHS_DEVFNUM : (UOTGHS Offset: 0x0020) Device Frame Number Register -------- */ +#define UOTGHS_DEVFNUM_MFNUM_Pos 0 +#define UOTGHS_DEVFNUM_MFNUM_Msk (0x7u << UOTGHS_DEVFNUM_MFNUM_Pos) /**< \brief (UOTGHS_DEVFNUM) Micro Frame Number */ +#define UOTGHS_DEVFNUM_FNUM_Pos 3 +#define UOTGHS_DEVFNUM_FNUM_Msk (0x7ffu << UOTGHS_DEVFNUM_FNUM_Pos) /**< \brief (UOTGHS_DEVFNUM) Frame Number */ +#define UOTGHS_DEVFNUM_FNCERR (0x1u << 15) /**< \brief (UOTGHS_DEVFNUM) Frame Number CRC Error */ +/* -------- UOTGHS_DEVEPTCFG[12] : (UOTGHS Offset: 0x100) Device Endpoint Configuration Register (n = 0) -------- */ +#define UOTGHS_DEVEPTCFG_ALLOC (0x1u << 1) /**< \brief (UOTGHS_DEVEPTCFG[12]) Endpoint Memory Allocate */ +#define UOTGHS_DEVEPTCFG_EPBK_Pos 2 +#define UOTGHS_DEVEPTCFG_EPBK_Msk (0x3u << UOTGHS_DEVEPTCFG_EPBK_Pos) /**< \brief (UOTGHS_DEVEPTCFG[12]) Endpoint Banks */ +#define UOTGHS_DEVEPTCFG_EPBK_1_BANK (0x0u << 2) /**< \brief (UOTGHS_DEVEPTCFG[12]) Single-bank endpoint */ +#define UOTGHS_DEVEPTCFG_EPBK_2_BANK (0x1u << 2) /**< \brief (UOTGHS_DEVEPTCFG[12]) Double-bank endpoint */ +#define UOTGHS_DEVEPTCFG_EPBK_3_BANK (0x2u << 2) /**< \brief (UOTGHS_DEVEPTCFG[12]) Triple-bank endpoint */ +#define UOTGHS_DEVEPTCFG_EPSIZE_Pos 4 +#define UOTGHS_DEVEPTCFG_EPSIZE_Msk (0x7u << UOTGHS_DEVEPTCFG_EPSIZE_Pos) /**< \brief (UOTGHS_DEVEPTCFG[12]) Endpoint Size */ +#define UOTGHS_DEVEPTCFG_EPSIZE_8_BYTE (0x0u << 4) /**< \brief (UOTGHS_DEVEPTCFG[12]) 8 bytes */ +#define UOTGHS_DEVEPTCFG_EPSIZE_16_BYTE (0x1u << 4) /**< \brief (UOTGHS_DEVEPTCFG[12]) 16 bytes */ +#define UOTGHS_DEVEPTCFG_EPSIZE_32_BYTE (0x2u << 4) /**< \brief (UOTGHS_DEVEPTCFG[12]) 32 bytes */ +#define UOTGHS_DEVEPTCFG_EPSIZE_64_BYTE (0x3u << 4) /**< \brief (UOTGHS_DEVEPTCFG[12]) 64 bytes */ +#define UOTGHS_DEVEPTCFG_EPSIZE_128_BYTE (0x4u << 4) /**< \brief (UOTGHS_DEVEPTCFG[12]) 128 bytes */ +#define UOTGHS_DEVEPTCFG_EPSIZE_256_BYTE (0x5u << 4) /**< \brief (UOTGHS_DEVEPTCFG[12]) 256 bytes */ +#define UOTGHS_DEVEPTCFG_EPSIZE_512_BYTE (0x6u << 4) /**< \brief (UOTGHS_DEVEPTCFG[12]) 512 bytes */ +#define UOTGHS_DEVEPTCFG_EPSIZE_1024_BYTE (0x7u << 4) /**< \brief (UOTGHS_DEVEPTCFG[12]) 1024 bytes */ +#define UOTGHS_DEVEPTCFG_EPDIR (0x1u << 8) /**< \brief (UOTGHS_DEVEPTCFG[12]) Endpoint Direction */ +#define UOTGHS_DEVEPTCFG_EPDIR_OUT (0x0u << 8) /**< \brief (UOTGHS_DEVEPTCFG[12]) The endpoint direction is OUT. */ +#define UOTGHS_DEVEPTCFG_EPDIR_IN (0x1u << 8) /**< \brief (UOTGHS_DEVEPTCFG[12]) The endpoint direction is IN (nor for control endpoints). */ +#define UOTGHS_DEVEPTCFG_AUTOSW (0x1u << 9) /**< \brief (UOTGHS_DEVEPTCFG[12]) Automatic Switch */ +#define UOTGHS_DEVEPTCFG_EPTYPE_Pos 11 +#define UOTGHS_DEVEPTCFG_EPTYPE_Msk (0x3u << UOTGHS_DEVEPTCFG_EPTYPE_Pos) /**< \brief (UOTGHS_DEVEPTCFG[12]) Endpoint Type */ +#define UOTGHS_DEVEPTCFG_EPTYPE_CTRL (0x0u << 11) /**< \brief (UOTGHS_DEVEPTCFG[12]) Control */ +#define UOTGHS_DEVEPTCFG_EPTYPE_ISO (0x1u << 11) /**< \brief (UOTGHS_DEVEPTCFG[12]) Isochronous */ +#define UOTGHS_DEVEPTCFG_EPTYPE_BLK (0x2u << 11) /**< \brief (UOTGHS_DEVEPTCFG[12]) Bulk */ +#define UOTGHS_DEVEPTCFG_EPTYPE_INTRPT (0x3u << 11) /**< \brief (UOTGHS_DEVEPTCFG[12]) Interrupt */ +#define UOTGHS_DEVEPTCFG_NBTRANS_Pos 13 +#define UOTGHS_DEVEPTCFG_NBTRANS_Msk (0x3u << UOTGHS_DEVEPTCFG_NBTRANS_Pos) /**< \brief (UOTGHS_DEVEPTCFG[12]) Number of transaction per microframe for isochronous endpoint */ +#define UOTGHS_DEVEPTCFG_NBTRANS_0_TRANS (0x0u << 13) /**< \brief (UOTGHS_DEVEPTCFG[12]) reserved to endpoint that does not have the high-bandwidth isochronous capability. */ +#define UOTGHS_DEVEPTCFG_NBTRANS_1_TRANS (0x1u << 13) /**< \brief (UOTGHS_DEVEPTCFG[12]) default value: one transaction per micro-frame. */ +#define UOTGHS_DEVEPTCFG_NBTRANS_2_TRANS (0x2u << 13) /**< \brief (UOTGHS_DEVEPTCFG[12]) 2 transactions per micro-frame. This endpoint should be configured as double-bank. */ +#define UOTGHS_DEVEPTCFG_NBTRANS_3_TRANS (0x3u << 13) /**< \brief (UOTGHS_DEVEPTCFG[12]) 3 transactions per micro-frame. This endpoint should be configured as triple-bank. */ +/* -------- UOTGHS_DEVEPTISR[12] : (UOTGHS Offset: 0x130) Device Endpoint Status Register (n = 0) -------- */ +#define UOTGHS_DEVEPTISR_TXINI (0x1u << 0) /**< \brief (UOTGHS_DEVEPTISR[12]) Transmitted IN Data Interrupt */ +#define UOTGHS_DEVEPTISR_RXOUTI (0x1u << 1) /**< \brief (UOTGHS_DEVEPTISR[12]) Received OUT Data Interrupt */ +#define UOTGHS_DEVEPTISR_RXSTPI (0x1u << 2) /**< \brief (UOTGHS_DEVEPTISR[12]) Received SETUP Interrupt */ +#define UOTGHS_DEVEPTISR_NAKOUTI (0x1u << 3) /**< \brief (UOTGHS_DEVEPTISR[12]) NAKed OUT Interrupt */ +#define UOTGHS_DEVEPTISR_NAKINI (0x1u << 4) /**< \brief (UOTGHS_DEVEPTISR[12]) NAKed IN Interrupt */ +#define UOTGHS_DEVEPTISR_OVERFI (0x1u << 5) /**< \brief (UOTGHS_DEVEPTISR[12]) Overflow Interrupt */ +#define UOTGHS_DEVEPTISR_STALLEDI (0x1u << 6) /**< \brief (UOTGHS_DEVEPTISR[12]) STALLed Interrupt */ +#define UOTGHS_DEVEPTISR_SHORTPACKET (0x1u << 7) /**< \brief (UOTGHS_DEVEPTISR[12]) Short Packet Interrupt */ +#define UOTGHS_DEVEPTISR_DTSEQ_Pos 8 +#define UOTGHS_DEVEPTISR_DTSEQ_Msk (0x3u << UOTGHS_DEVEPTISR_DTSEQ_Pos) /**< \brief (UOTGHS_DEVEPTISR[12]) Data Toggle Sequence */ +#define UOTGHS_DEVEPTISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (UOTGHS_DEVEPTISR[12]) Data0 toggle sequence */ +#define UOTGHS_DEVEPTISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (UOTGHS_DEVEPTISR[12]) Data1 toggle sequence */ +#define UOTGHS_DEVEPTISR_DTSEQ_DATA2 (0x2u << 8) /**< \brief (UOTGHS_DEVEPTISR[12]) Reserved for high-bandwidth isochronous endpoint */ +#define UOTGHS_DEVEPTISR_DTSEQ_MDATA (0x3u << 8) /**< \brief (UOTGHS_DEVEPTISR[12]) Reserved for high-bandwidth isochronous endpoint */ +#define UOTGHS_DEVEPTISR_NBUSYBK_Pos 12 +#define UOTGHS_DEVEPTISR_NBUSYBK_Msk (0x3u << UOTGHS_DEVEPTISR_NBUSYBK_Pos) /**< \brief (UOTGHS_DEVEPTISR[12]) Number of Busy Banks */ +#define UOTGHS_DEVEPTISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (UOTGHS_DEVEPTISR[12]) 0 busy bank (all banks free) */ +#define UOTGHS_DEVEPTISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (UOTGHS_DEVEPTISR[12]) 1 busy bank */ +#define UOTGHS_DEVEPTISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (UOTGHS_DEVEPTISR[12]) 2 busy banks */ +#define UOTGHS_DEVEPTISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (UOTGHS_DEVEPTISR[12]) 3 busy banks */ +#define UOTGHS_DEVEPTISR_CURRBK_Pos 14 +#define UOTGHS_DEVEPTISR_CURRBK_Msk (0x3u << UOTGHS_DEVEPTISR_CURRBK_Pos) /**< \brief (UOTGHS_DEVEPTISR[12]) Current Bank */ +#define UOTGHS_DEVEPTISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (UOTGHS_DEVEPTISR[12]) Current bank is bank0 */ +#define UOTGHS_DEVEPTISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (UOTGHS_DEVEPTISR[12]) Current bank is bank1 */ +#define UOTGHS_DEVEPTISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (UOTGHS_DEVEPTISR[12]) Current bank is bank2 */ +#define UOTGHS_DEVEPTISR_RWALL (0x1u << 16) /**< \brief (UOTGHS_DEVEPTISR[12]) Read-write Allowed */ +#define UOTGHS_DEVEPTISR_CTRLDIR (0x1u << 17) /**< \brief (UOTGHS_DEVEPTISR[12]) Control Direction */ +#define UOTGHS_DEVEPTISR_CFGOK (0x1u << 18) /**< \brief (UOTGHS_DEVEPTISR[12]) Configuration OK Status */ +#define UOTGHS_DEVEPTISR_BYCT_Pos 20 +#define UOTGHS_DEVEPTISR_BYCT_Msk (0x7ffu << UOTGHS_DEVEPTISR_BYCT_Pos) /**< \brief (UOTGHS_DEVEPTISR[12]) Byte Count */ +#define UOTGHS_DEVEPTISR_UNDERFI (0x1u << 2) /**< \brief (UOTGHS_DEVEPTISR[12]) Underflow Interrupt */ +#define UOTGHS_DEVEPTISR_HBISOINERRI (0x1u << 3) /**< \brief (UOTGHS_DEVEPTISR[12]) High Bandwidth Isochronous IN Underflow Error Interrupt */ +#define UOTGHS_DEVEPTISR_HBISOFLUSHI (0x1u << 4) /**< \brief (UOTGHS_DEVEPTISR[12]) High Bandwidth Isochronous IN Flush Interrupt */ +#define UOTGHS_DEVEPTISR_CRCERRI (0x1u << 6) /**< \brief (UOTGHS_DEVEPTISR[12]) CRC Error Interrupt */ +#define UOTGHS_DEVEPTISR_ERRORTRANS (0x1u << 10) /**< \brief (UOTGHS_DEVEPTISR[12]) High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt */ +/* -------- UOTGHS_DEVEPTICR[12] : (UOTGHS Offset: 0x160) Device Endpoint Clear Register (n = 0) -------- */ +#define UOTGHS_DEVEPTICR_TXINIC (0x1u << 0) /**< \brief (UOTGHS_DEVEPTICR[12]) Transmitted IN Data Interrupt Clear */ +#define UOTGHS_DEVEPTICR_RXOUTIC (0x1u << 1) /**< \brief (UOTGHS_DEVEPTICR[12]) Received OUT Data Interrupt Clear */ +#define UOTGHS_DEVEPTICR_RXSTPIC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTICR[12]) Received SETUP Interrupt Clear */ +#define UOTGHS_DEVEPTICR_NAKOUTIC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTICR[12]) NAKed OUT Interrupt Clear */ +#define UOTGHS_DEVEPTICR_NAKINIC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTICR[12]) NAKed IN Interrupt Clear */ +#define UOTGHS_DEVEPTICR_OVERFIC (0x1u << 5) /**< \brief (UOTGHS_DEVEPTICR[12]) Overflow Interrupt Clear */ +#define UOTGHS_DEVEPTICR_STALLEDIC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTICR[12]) STALLed Interrupt Clear */ +#define UOTGHS_DEVEPTICR_SHORTPACKETC (0x1u << 7) /**< \brief (UOTGHS_DEVEPTICR[12]) Short Packet Interrupt Clear */ +#define UOTGHS_DEVEPTICR_UNDERFIC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTICR[12]) Underflow Interrupt Clear */ +#define UOTGHS_DEVEPTICR_HBISOINERRIC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTICR[12]) High bandwidth isochronous IN Underflow Error Interrupt Clear */ +#define UOTGHS_DEVEPTICR_HBISOFLUSHIC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTICR[12]) High Bandwidth Isochronous IN Flush Interrupt Clear */ +#define UOTGHS_DEVEPTICR_CRCERRIC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTICR[12]) CRC Error Interrupt Clear */ +/* -------- UOTGHS_DEVEPTIFR[12] : (UOTGHS Offset: 0x190) Device Endpoint Set Register (n = 0) -------- */ +#define UOTGHS_DEVEPTIFR_TXINIS (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIFR[12]) Transmitted IN Data Interrupt Set */ +#define UOTGHS_DEVEPTIFR_RXOUTIS (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIFR[12]) Received OUT Data Interrupt Set */ +#define UOTGHS_DEVEPTIFR_RXSTPIS (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIFR[12]) Received SETUP Interrupt Set */ +#define UOTGHS_DEVEPTIFR_NAKOUTIS (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIFR[12]) NAKed OUT Interrupt Set */ +#define UOTGHS_DEVEPTIFR_NAKINIS (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIFR[12]) NAKed IN Interrupt Set */ +#define UOTGHS_DEVEPTIFR_OVERFIS (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIFR[12]) Overflow Interrupt Set */ +#define UOTGHS_DEVEPTIFR_STALLEDIS (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIFR[12]) STALLed Interrupt Set */ +#define UOTGHS_DEVEPTIFR_SHORTPACKETS (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIFR[12]) Short Packet Interrupt Set */ +#define UOTGHS_DEVEPTIFR_NBUSYBKS (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIFR[12]) Number of Busy Banks Interrupt Set */ +#define UOTGHS_DEVEPTIFR_UNDERFIS (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIFR[12]) Underflow Interrupt Set */ +#define UOTGHS_DEVEPTIFR_HBISOINERRIS (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIFR[12]) High bandwidth isochronous IN Underflow Error Interrupt Set */ +#define UOTGHS_DEVEPTIFR_HBISOFLUSHIS (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIFR[12]) High Bandwidth Isochronous IN Flush Interrupt Set */ +#define UOTGHS_DEVEPTIFR_CRCERRIS (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIFR[12]) CRC Error Interrupt Set */ +/* -------- UOTGHS_DEVEPTIMR[12] : (UOTGHS Offset: 0x1C0) Device Endpoint Mask Register (n = 0) -------- */ +#define UOTGHS_DEVEPTIMR_TXINE (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIMR[12]) Transmitted IN Data Interrupt */ +#define UOTGHS_DEVEPTIMR_RXOUTE (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIMR[12]) Received OUT Data Interrupt */ +#define UOTGHS_DEVEPTIMR_RXSTPE (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIMR[12]) Received SETUP Interrupt */ +#define UOTGHS_DEVEPTIMR_NAKOUTE (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIMR[12]) NAKed OUT Interrupt */ +#define UOTGHS_DEVEPTIMR_NAKINE (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIMR[12]) NAKed IN Interrupt */ +#define UOTGHS_DEVEPTIMR_OVERFE (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIMR[12]) Overflow Interrupt */ +#define UOTGHS_DEVEPTIMR_STALLEDE (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIMR[12]) STALLed Interrupt */ +#define UOTGHS_DEVEPTIMR_SHORTPACKETE (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIMR[12]) Short Packet Interrupt */ +#define UOTGHS_DEVEPTIMR_NBUSYBKE (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIMR[12]) Number of Busy Banks Interrupt */ +#define UOTGHS_DEVEPTIMR_KILLBK (0x1u << 13) /**< \brief (UOTGHS_DEVEPTIMR[12]) Kill IN Bank */ +#define UOTGHS_DEVEPTIMR_FIFOCON (0x1u << 14) /**< \brief (UOTGHS_DEVEPTIMR[12]) FIFO Control */ +#define UOTGHS_DEVEPTIMR_EPDISHDMA (0x1u << 16) /**< \brief (UOTGHS_DEVEPTIMR[12]) Endpoint Interrupts Disable HDMA Request */ +#define UOTGHS_DEVEPTIMR_NYETDIS (0x1u << 17) /**< \brief (UOTGHS_DEVEPTIMR[12]) NYET Token Disable */ +#define UOTGHS_DEVEPTIMR_RSTDT (0x1u << 18) /**< \brief (UOTGHS_DEVEPTIMR[12]) Reset Data Toggle */ +#define UOTGHS_DEVEPTIMR_STALLRQ (0x1u << 19) /**< \brief (UOTGHS_DEVEPTIMR[12]) STALL Request */ +#define UOTGHS_DEVEPTIMR_UNDERFE (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIMR[12]) Underflow Interrupt */ +#define UOTGHS_DEVEPTIMR_HBISOINERRE (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIMR[12]) High Bandwidth Isochronous IN Error Interrupt */ +#define UOTGHS_DEVEPTIMR_HBISOFLUSHE (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIMR[12]) High Bandwidth Isochronous IN Flush Interrupt */ +#define UOTGHS_DEVEPTIMR_CRCERRE (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIMR[12]) CRC Error Interrupt */ +#define UOTGHS_DEVEPTIMR_MDATAE (0x1u << 8) /**< \brief (UOTGHS_DEVEPTIMR[12]) MData Interrupt */ +#define UOTGHS_DEVEPTIMR_DATAXE (0x1u << 9) /**< \brief (UOTGHS_DEVEPTIMR[12]) DataX Interrupt */ +#define UOTGHS_DEVEPTIMR_ERRORTRANSE (0x1u << 10) /**< \brief (UOTGHS_DEVEPTIMR[12]) Transaction Error Interrupt */ +/* -------- UOTGHS_DEVEPTIER[12] : (UOTGHS Offset: 0x1F0) Device Endpoint Enable Register (n = 0) -------- */ +#define UOTGHS_DEVEPTIER_TXINES (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIER[12]) Transmitted IN Data Interrupt Enable */ +#define UOTGHS_DEVEPTIER_RXOUTES (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIER[12]) Received OUT Data Interrupt Enable */ +#define UOTGHS_DEVEPTIER_RXSTPES (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIER[12]) Received SETUP Interrupt Enable */ +#define UOTGHS_DEVEPTIER_NAKOUTES (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIER[12]) NAKed OUT Interrupt Enable */ +#define UOTGHS_DEVEPTIER_NAKINES (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIER[12]) NAKed IN Interrupt Enable */ +#define UOTGHS_DEVEPTIER_OVERFES (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIER[12]) Overflow Interrupt Enable */ +#define UOTGHS_DEVEPTIER_STALLEDES (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIER[12]) STALLed Interrupt Enable */ +#define UOTGHS_DEVEPTIER_SHORTPACKETES (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIER[12]) Short Packet Interrupt Enable */ +#define UOTGHS_DEVEPTIER_NBUSYBKES (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIER[12]) Number of Busy Banks Interrupt Enable */ +#define UOTGHS_DEVEPTIER_KILLBKS (0x1u << 13) /**< \brief (UOTGHS_DEVEPTIER[12]) Kill IN Bank */ +#define UOTGHS_DEVEPTIER_FIFOCONS (0x1u << 14) /**< \brief (UOTGHS_DEVEPTIER[12]) FIFO Control */ +#define UOTGHS_DEVEPTIER_EPDISHDMAS (0x1u << 16) /**< \brief (UOTGHS_DEVEPTIER[12]) Endpoint Interrupts Disable HDMA Request Enable */ +#define UOTGHS_DEVEPTIER_NYETDISS (0x1u << 17) /**< \brief (UOTGHS_DEVEPTIER[12]) NYET Token Disable Enable */ +#define UOTGHS_DEVEPTIER_RSTDTS (0x1u << 18) /**< \brief (UOTGHS_DEVEPTIER[12]) Reset Data Toggle Enable */ +#define UOTGHS_DEVEPTIER_STALLRQS (0x1u << 19) /**< \brief (UOTGHS_DEVEPTIER[12]) STALL Request Enable */ +#define UOTGHS_DEVEPTIER_UNDERFES (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIER[12]) Underflow Interrupt Enable */ +#define UOTGHS_DEVEPTIER_HBISOINERRES (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIER[12]) High Bandwidth Isochronous IN Error Interrupt Enable */ +#define UOTGHS_DEVEPTIER_HBISOFLUSHES (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIER[12]) High Bandwidth Isochronous IN Flush Interrupt Enable */ +#define UOTGHS_DEVEPTIER_CRCERRES (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIER[12]) CRC Error Interrupt Enable */ +#define UOTGHS_DEVEPTIER_MDATAES (0x1u << 8) /**< \brief (UOTGHS_DEVEPTIER[12]) MData Interrupt Enable */ +#define UOTGHS_DEVEPTIER_DATAXES (0x1u << 9) /**< \brief (UOTGHS_DEVEPTIER[12]) DataX Interrupt Enable */ +#define UOTGHS_DEVEPTIER_ERRORTRANSES (0x1u << 10) /**< \brief (UOTGHS_DEVEPTIER[12]) Transaction Error Interrupt Enable */ +/* -------- UOTGHS_DEVEPTIDR[12] : (UOTGHS Offset: 0x220) Device Endpoint Disable Register (n = 0) -------- */ +#define UOTGHS_DEVEPTIDR_TXINEC (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIDR[12]) Transmitted IN Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_RXOUTEC (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIDR[12]) Received OUT Data Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_RXSTPEC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIDR[12]) Received SETUP Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_NAKOUTEC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIDR[12]) NAKed OUT Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_NAKINEC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIDR[12]) NAKed IN Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_OVERFEC (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIDR[12]) Overflow Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_STALLEDEC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIDR[12]) STALLed Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_SHORTPACKETEC (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIDR[12]) Shortpacket Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_NBUSYBKEC (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIDR[12]) Number of Busy Banks Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_FIFOCONC (0x1u << 14) /**< \brief (UOTGHS_DEVEPTIDR[12]) FIFO Control Clear */ +#define UOTGHS_DEVEPTIDR_EPDISHDMAC (0x1u << 16) /**< \brief (UOTGHS_DEVEPTIDR[12]) Endpoint Interrupts Disable HDMA Request Clear */ +#define UOTGHS_DEVEPTIDR_NYETDISC (0x1u << 17) /**< \brief (UOTGHS_DEVEPTIDR[12]) NYET Token Disable Clear */ +#define UOTGHS_DEVEPTIDR_STALLRQC (0x1u << 19) /**< \brief (UOTGHS_DEVEPTIDR[12]) STALL Request Clear */ +#define UOTGHS_DEVEPTIDR_UNDERFEC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIDR[12]) Underflow Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_HBISOINERREC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIDR[12]) High Bandwidth Isochronous IN Error Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_HBISOFLUSHEC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIDR[12]) High Bandwidth Isochronous IN Flush Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_CRCERREC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIDR[12]) CRC Error Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_MDATEC (0x1u << 8) /**< \brief (UOTGHS_DEVEPTIDR[12]) MData Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_DATAXEC (0x1u << 9) /**< \brief (UOTGHS_DEVEPTIDR[12]) DataX Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_ERRORTRANSEC (0x1u << 10) /**< \brief (UOTGHS_DEVEPTIDR[12]) Transaction Error Interrupt Clear */ +/* -------- UOTGHS_DEVDMANXTDSC : (UOTGHS Offset: N/A) Device DMA Channel Next Descriptor Address Register -------- */ +#define UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos 0 +#define UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (UOTGHS_DEVDMANXTDSC) Next Descriptor Address */ +#define UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD(value) ((UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos))) +/* -------- UOTGHS_DEVDMAADDRESS : (UOTGHS Offset: N/A) Device DMA Channel Address Register -------- */ +#define UOTGHS_DEVDMAADDRESS_BUFF_ADD_Pos 0 +#define UOTGHS_DEVDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << UOTGHS_DEVDMAADDRESS_BUFF_ADD_Pos) /**< \brief (UOTGHS_DEVDMAADDRESS) Buffer Address */ +#define UOTGHS_DEVDMAADDRESS_BUFF_ADD(value) ((UOTGHS_DEVDMAADDRESS_BUFF_ADD_Msk & ((value) << UOTGHS_DEVDMAADDRESS_BUFF_ADD_Pos))) +/* -------- UOTGHS_DEVDMACONTROL : (UOTGHS Offset: N/A) Device DMA Channel Control Register -------- */ +#define UOTGHS_DEVDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_DEVDMACONTROL) Channel Enable Command */ +#define UOTGHS_DEVDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (UOTGHS_DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */ +#define UOTGHS_DEVDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (UOTGHS_DEVDMACONTROL) End of Transfer Enable Control */ +#define UOTGHS_DEVDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (UOTGHS_DEVDMACONTROL) End of Buffer Enable Control */ +#define UOTGHS_DEVDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (UOTGHS_DEVDMACONTROL) End of Transfer Interrupt Enable */ +#define UOTGHS_DEVDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (UOTGHS_DEVDMACONTROL) End of Buffer Interrupt Enable */ +#define UOTGHS_DEVDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (UOTGHS_DEVDMACONTROL) Descriptor Loaded Interrupt Enable */ +#define UOTGHS_DEVDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (UOTGHS_DEVDMACONTROL) Burst Lock Enable */ +#define UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Pos 16 +#define UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Msk (0xffffu << UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (UOTGHS_DEVDMACONTROL) Buffer Byte Length (Write-only) */ +#define UOTGHS_DEVDMACONTROL_BUFF_LENGTH(value) ((UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Msk & ((value) << UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Pos))) +/* -------- UOTGHS_DEVDMASTATUS : (UOTGHS Offset: N/A) Device DMA Channel Status Register -------- */ +#define UOTGHS_DEVDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_DEVDMASTATUS) Channel Enable Status */ +#define UOTGHS_DEVDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (UOTGHS_DEVDMASTATUS) Channel Active Status */ +#define UOTGHS_DEVDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (UOTGHS_DEVDMASTATUS) End of Channel Transfer Status */ +#define UOTGHS_DEVDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (UOTGHS_DEVDMASTATUS) End of Channel Buffer Status */ +#define UOTGHS_DEVDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (UOTGHS_DEVDMASTATUS) Descriptor Loaded Status */ +#define UOTGHS_DEVDMASTATUS_BUFF_COUNT_Pos 16 +#define UOTGHS_DEVDMASTATUS_BUFF_COUNT_Msk (0xffffu << UOTGHS_DEVDMASTATUS_BUFF_COUNT_Pos) /**< \brief (UOTGHS_DEVDMASTATUS) Buffer Byte Count */ +#define UOTGHS_DEVDMASTATUS_BUFF_COUNT(value) ((UOTGHS_DEVDMASTATUS_BUFF_COUNT_Msk & ((value) << UOTGHS_DEVDMASTATUS_BUFF_COUNT_Pos))) +/* -------- UOTGHS_HSTCTRL : (UOTGHS Offset: 0x0400) Host General Control Register -------- */ +#define UOTGHS_HSTCTRL_SOFE (0x1u << 8) /**< \brief (UOTGHS_HSTCTRL) Start of Frame Generation Enable */ +#define UOTGHS_HSTCTRL_RESET (0x1u << 9) /**< \brief (UOTGHS_HSTCTRL) Send USB Reset */ +#define UOTGHS_HSTCTRL_RESUME (0x1u << 10) /**< \brief (UOTGHS_HSTCTRL) Send USB Resume */ +#define UOTGHS_HSTCTRL_SPDCONF_Pos 12 +#define UOTGHS_HSTCTRL_SPDCONF_Msk (0x3u << UOTGHS_HSTCTRL_SPDCONF_Pos) /**< \brief (UOTGHS_HSTCTRL) Mode Configuration */ +#define UOTGHS_HSTCTRL_SPDCONF_NORMAL (0x0u << 12) /**< \brief (UOTGHS_HSTCTRL) The host starts in full-speed mode and performs a high-speed reset to switch to the high-speed mode if the downstream peripheral is high-speed capable. */ +#define UOTGHS_HSTCTRL_SPDCONF_LOW_POWER (0x1u << 12) /**< \brief (UOTGHS_HSTCTRL) For a better consumption, if high-speed is not needed. */ +#define UOTGHS_HSTCTRL_SPDCONF_HIGH_SPEED (0x2u << 12) /**< \brief (UOTGHS_HSTCTRL) Forced high speed. */ +#define UOTGHS_HSTCTRL_SPDCONF_FORCED_FS (0x3u << 12) /**< \brief (UOTGHS_HSTCTRL) The host remains to full-speed mode whatever the peripheral speed capability. */ +/* -------- UOTGHS_HSTISR : (UOTGHS Offset: 0x0404) Host Global Interrupt Status Register -------- */ +#define UOTGHS_HSTISR_DCONNI (0x1u << 0) /**< \brief (UOTGHS_HSTISR) Device Connection Interrupt */ +#define UOTGHS_HSTISR_DDISCI (0x1u << 1) /**< \brief (UOTGHS_HSTISR) Device Disconnection Interrupt */ +#define UOTGHS_HSTISR_RSTI (0x1u << 2) /**< \brief (UOTGHS_HSTISR) USB Reset Sent Interrupt */ +#define UOTGHS_HSTISR_RSMEDI (0x1u << 3) /**< \brief (UOTGHS_HSTISR) Downstream Resume Sent Interrupt */ +#define UOTGHS_HSTISR_RXRSMI (0x1u << 4) /**< \brief (UOTGHS_HSTISR) Upstream Resume Received Interrupt */ +#define UOTGHS_HSTISR_HSOFI (0x1u << 5) /**< \brief (UOTGHS_HSTISR) Host Start of Frame Interrupt */ +#define UOTGHS_HSTISR_HWUPI (0x1u << 6) /**< \brief (UOTGHS_HSTISR) Host Wake-Up Interrupt */ +#define UOTGHS_HSTISR_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTISR) Pipe 0 Interrupt */ +#define UOTGHS_HSTISR_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTISR) Pipe 1 Interrupt */ +#define UOTGHS_HSTISR_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTISR) Pipe 2 Interrupt */ +#define UOTGHS_HSTISR_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTISR) Pipe 3 Interrupt */ +#define UOTGHS_HSTISR_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTISR) Pipe 4 Interrupt */ +#define UOTGHS_HSTISR_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTISR) Pipe 5 Interrupt */ +#define UOTGHS_HSTISR_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTISR) Pipe 6 Interrupt */ +#define UOTGHS_HSTISR_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTISR) Pipe 7 Interrupt */ +#define UOTGHS_HSTISR_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTISR) Pipe 8 Interrupt */ +#define UOTGHS_HSTISR_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTISR) Pipe 9 Interrupt */ +#define UOTGHS_HSTISR_PEP_10 (0x1u << 18) /**< \brief (UOTGHS_HSTISR) Pipe 10 Interrupt */ +#define UOTGHS_HSTISR_PEP_11 (0x1u << 19) /**< \brief (UOTGHS_HSTISR) Pipe 11 Interrupt */ +#define UOTGHS_HSTISR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTISR) DMA Channel 1 Interrupt */ +#define UOTGHS_HSTISR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTISR) DMA Channel 2 Interrupt */ +#define UOTGHS_HSTISR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTISR) DMA Channel 3 Interrupt */ +#define UOTGHS_HSTISR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTISR) DMA Channel 4 Interrupt */ +#define UOTGHS_HSTISR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTISR) DMA Channel 5 Interrupt */ +#define UOTGHS_HSTISR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTISR) DMA Channel 6 Interrupt */ +#define UOTGHS_HSTISR_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_HSTISR) DMA Channel 7 Interrupt */ +/* -------- UOTGHS_HSTICR : (UOTGHS Offset: 0x0408) Host Global Interrupt Clear Register -------- */ +#define UOTGHS_HSTICR_DCONNIC (0x1u << 0) /**< \brief (UOTGHS_HSTICR) Device Connection Interrupt Clear */ +#define UOTGHS_HSTICR_DDISCIC (0x1u << 1) /**< \brief (UOTGHS_HSTICR) Device Disconnection Interrupt Clear */ +#define UOTGHS_HSTICR_RSTIC (0x1u << 2) /**< \brief (UOTGHS_HSTICR) USB Reset Sent Interrupt Clear */ +#define UOTGHS_HSTICR_RSMEDIC (0x1u << 3) /**< \brief (UOTGHS_HSTICR) Downstream Resume Sent Interrupt Clear */ +#define UOTGHS_HSTICR_RXRSMIC (0x1u << 4) /**< \brief (UOTGHS_HSTICR) Upstream Resume Received Interrupt Clear */ +#define UOTGHS_HSTICR_HSOFIC (0x1u << 5) /**< \brief (UOTGHS_HSTICR) Host Start of Frame Interrupt Clear */ +#define UOTGHS_HSTICR_HWUPIC (0x1u << 6) /**< \brief (UOTGHS_HSTICR) Host Wake-Up Interrupt Clear */ +/* -------- UOTGHS_HSTIFR : (UOTGHS Offset: 0x040C) Host Global Interrupt Set Register -------- */ +#define UOTGHS_HSTIFR_DCONNIS (0x1u << 0) /**< \brief (UOTGHS_HSTIFR) Device Connection Interrupt Set */ +#define UOTGHS_HSTIFR_DDISCIS (0x1u << 1) /**< \brief (UOTGHS_HSTIFR) Device Disconnection Interrupt Set */ +#define UOTGHS_HSTIFR_RSTIS (0x1u << 2) /**< \brief (UOTGHS_HSTIFR) USB Reset Sent Interrupt Set */ +#define UOTGHS_HSTIFR_RSMEDIS (0x1u << 3) /**< \brief (UOTGHS_HSTIFR) Downstream Resume Sent Interrupt Set */ +#define UOTGHS_HSTIFR_RXRSMIS (0x1u << 4) /**< \brief (UOTGHS_HSTIFR) Upstream Resume Received Interrupt Set */ +#define UOTGHS_HSTIFR_HSOFIS (0x1u << 5) /**< \brief (UOTGHS_HSTIFR) Host Start of Frame Interrupt Set */ +#define UOTGHS_HSTIFR_HWUPIS (0x1u << 6) /**< \brief (UOTGHS_HSTIFR) Host Wake-Up Interrupt Set */ +#define UOTGHS_HSTIFR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIFR) DMA Channel 1 Interrupt Set */ +#define UOTGHS_HSTIFR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIFR) DMA Channel 2 Interrupt Set */ +#define UOTGHS_HSTIFR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIFR) DMA Channel 3 Interrupt Set */ +#define UOTGHS_HSTIFR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIFR) DMA Channel 4 Interrupt Set */ +#define UOTGHS_HSTIFR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIFR) DMA Channel 5 Interrupt Set */ +#define UOTGHS_HSTIFR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIFR) DMA Channel 6 Interrupt Set */ +#define UOTGHS_HSTIFR_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_HSTIFR) DMA Channel 7 Interrupt Set */ +/* -------- UOTGHS_HSTIMR : (UOTGHS Offset: 0x0410) Host Global Interrupt Mask Register -------- */ +#define UOTGHS_HSTIMR_DCONNIE (0x1u << 0) /**< \brief (UOTGHS_HSTIMR) Device Connection Interrupt Enable */ +#define UOTGHS_HSTIMR_DDISCIE (0x1u << 1) /**< \brief (UOTGHS_HSTIMR) Device Disconnection Interrupt Enable */ +#define UOTGHS_HSTIMR_RSTIE (0x1u << 2) /**< \brief (UOTGHS_HSTIMR) USB Reset Sent Interrupt Enable */ +#define UOTGHS_HSTIMR_RSMEDIE (0x1u << 3) /**< \brief (UOTGHS_HSTIMR) Downstream Resume Sent Interrupt Enable */ +#define UOTGHS_HSTIMR_RXRSMIE (0x1u << 4) /**< \brief (UOTGHS_HSTIMR) Upstream Resume Received Interrupt Enable */ +#define UOTGHS_HSTIMR_HSOFIE (0x1u << 5) /**< \brief (UOTGHS_HSTIMR) Host Start of Frame Interrupt Enable */ +#define UOTGHS_HSTIMR_HWUPIE (0x1u << 6) /**< \brief (UOTGHS_HSTIMR) Host Wake-Up Interrupt Enable */ +#define UOTGHS_HSTIMR_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTIMR) Pipe 0 Interrupt Enable */ +#define UOTGHS_HSTIMR_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTIMR) Pipe 1 Interrupt Enable */ +#define UOTGHS_HSTIMR_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTIMR) Pipe 2 Interrupt Enable */ +#define UOTGHS_HSTIMR_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTIMR) Pipe 3 Interrupt Enable */ +#define UOTGHS_HSTIMR_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTIMR) Pipe 4 Interrupt Enable */ +#define UOTGHS_HSTIMR_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTIMR) Pipe 5 Interrupt Enable */ +#define UOTGHS_HSTIMR_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTIMR) Pipe 6 Interrupt Enable */ +#define UOTGHS_HSTIMR_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTIMR) Pipe 7 Interrupt Enable */ +#define UOTGHS_HSTIMR_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTIMR) Pipe 8 Interrupt Enable */ +#define UOTGHS_HSTIMR_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTIMR) Pipe 9 Interrupt Enable */ +#define UOTGHS_HSTIMR_PEP_10 (0x1u << 18) /**< \brief (UOTGHS_HSTIMR) Pipe 10 Interrupt Enable */ +#define UOTGHS_HSTIMR_PEP_11 (0x1u << 19) /**< \brief (UOTGHS_HSTIMR) Pipe 11 Interrupt Enable */ +#define UOTGHS_HSTIMR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIMR) DMA Channel 1 Interrupt Enable */ +#define UOTGHS_HSTIMR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIMR) DMA Channel 2 Interrupt Enable */ +#define UOTGHS_HSTIMR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIMR) DMA Channel 3 Interrupt Enable */ +#define UOTGHS_HSTIMR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIMR) DMA Channel 4 Interrupt Enable */ +#define UOTGHS_HSTIMR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIMR) DMA Channel 5 Interrupt Enable */ +#define UOTGHS_HSTIMR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIMR) DMA Channel 6 Interrupt Enable */ +#define UOTGHS_HSTIMR_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_HSTIMR) DMA Channel 7 Interrupt Enable */ +/* -------- UOTGHS_HSTIDR : (UOTGHS Offset: 0x0414) Host Global Interrupt Disable Register -------- */ +#define UOTGHS_HSTIDR_DCONNIEC (0x1u << 0) /**< \brief (UOTGHS_HSTIDR) Device Connection Interrupt Disable */ +#define UOTGHS_HSTIDR_DDISCIEC (0x1u << 1) /**< \brief (UOTGHS_HSTIDR) Device Disconnection Interrupt Disable */ +#define UOTGHS_HSTIDR_RSTIEC (0x1u << 2) /**< \brief (UOTGHS_HSTIDR) USB Reset Sent Interrupt Disable */ +#define UOTGHS_HSTIDR_RSMEDIEC (0x1u << 3) /**< \brief (UOTGHS_HSTIDR) Downstream Resume Sent Interrupt Disable */ +#define UOTGHS_HSTIDR_RXRSMIEC (0x1u << 4) /**< \brief (UOTGHS_HSTIDR) Upstream Resume Received Interrupt Disable */ +#define UOTGHS_HSTIDR_HSOFIEC (0x1u << 5) /**< \brief (UOTGHS_HSTIDR) Host Start of Frame Interrupt Disable */ +#define UOTGHS_HSTIDR_HWUPIEC (0x1u << 6) /**< \brief (UOTGHS_HSTIDR) Host Wake-Up Interrupt Disable */ +#define UOTGHS_HSTIDR_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTIDR) Pipe 0 Interrupt Disable */ +#define UOTGHS_HSTIDR_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTIDR) Pipe 1 Interrupt Disable */ +#define UOTGHS_HSTIDR_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTIDR) Pipe 2 Interrupt Disable */ +#define UOTGHS_HSTIDR_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTIDR) Pipe 3 Interrupt Disable */ +#define UOTGHS_HSTIDR_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTIDR) Pipe 4 Interrupt Disable */ +#define UOTGHS_HSTIDR_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTIDR) Pipe 5 Interrupt Disable */ +#define UOTGHS_HSTIDR_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTIDR) Pipe 6 Interrupt Disable */ +#define UOTGHS_HSTIDR_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTIDR) Pipe 7 Interrupt Disable */ +#define UOTGHS_HSTIDR_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTIDR) Pipe 8 Interrupt Disable */ +#define UOTGHS_HSTIDR_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTIDR) Pipe 9 Interrupt Disable */ +#define UOTGHS_HSTIDR_PEP_10 (0x1u << 18) /**< \brief (UOTGHS_HSTIDR) Pipe 10 Interrupt Disable */ +#define UOTGHS_HSTIDR_PEP_11 (0x1u << 19) /**< \brief (UOTGHS_HSTIDR) Pipe 11 Interrupt Disable */ +#define UOTGHS_HSTIDR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIDR) DMA Channel 1 Interrupt Disable */ +#define UOTGHS_HSTIDR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIDR) DMA Channel 2 Interrupt Disable */ +#define UOTGHS_HSTIDR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIDR) DMA Channel 3 Interrupt Disable */ +#define UOTGHS_HSTIDR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIDR) DMA Channel 4 Interrupt Disable */ +#define UOTGHS_HSTIDR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIDR) DMA Channel 5 Interrupt Disable */ +#define UOTGHS_HSTIDR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIDR) DMA Channel 6 Interrupt Disable */ +#define UOTGHS_HSTIDR_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_HSTIDR) DMA Channel 7 Interrupt Disable */ +/* -------- UOTGHS_HSTIER : (UOTGHS Offset: 0x0418) Host Global Interrupt Enable Register -------- */ +#define UOTGHS_HSTIER_DCONNIES (0x1u << 0) /**< \brief (UOTGHS_HSTIER) Device Connection Interrupt Enable */ +#define UOTGHS_HSTIER_DDISCIES (0x1u << 1) /**< \brief (UOTGHS_HSTIER) Device Disconnection Interrupt Enable */ +#define UOTGHS_HSTIER_RSTIES (0x1u << 2) /**< \brief (UOTGHS_HSTIER) USB Reset Sent Interrupt Enable */ +#define UOTGHS_HSTIER_RSMEDIES (0x1u << 3) /**< \brief (UOTGHS_HSTIER) Downstream Resume Sent Interrupt Enable */ +#define UOTGHS_HSTIER_RXRSMIES (0x1u << 4) /**< \brief (UOTGHS_HSTIER) Upstream Resume Received Interrupt Enable */ +#define UOTGHS_HSTIER_HSOFIES (0x1u << 5) /**< \brief (UOTGHS_HSTIER) Host Start of Frame Interrupt Enable */ +#define UOTGHS_HSTIER_HWUPIES (0x1u << 6) /**< \brief (UOTGHS_HSTIER) Host Wake-Up Interrupt Enable */ +#define UOTGHS_HSTIER_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTIER) Pipe 0 Interrupt Enable */ +#define UOTGHS_HSTIER_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTIER) Pipe 1 Interrupt Enable */ +#define UOTGHS_HSTIER_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTIER) Pipe 2 Interrupt Enable */ +#define UOTGHS_HSTIER_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTIER) Pipe 3 Interrupt Enable */ +#define UOTGHS_HSTIER_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTIER) Pipe 4 Interrupt Enable */ +#define UOTGHS_HSTIER_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTIER) Pipe 5 Interrupt Enable */ +#define UOTGHS_HSTIER_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTIER) Pipe 6 Interrupt Enable */ +#define UOTGHS_HSTIER_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTIER) Pipe 7 Interrupt Enable */ +#define UOTGHS_HSTIER_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTIER) Pipe 8 Interrupt Enable */ +#define UOTGHS_HSTIER_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTIER) Pipe 9 Interrupt Enable */ +#define UOTGHS_HSTIER_PEP_10 (0x1u << 18) /**< \brief (UOTGHS_HSTIER) Pipe 10 Interrupt Enable */ +#define UOTGHS_HSTIER_PEP_11 (0x1u << 19) /**< \brief (UOTGHS_HSTIER) Pipe 11 Interrupt Enable */ +#define UOTGHS_HSTIER_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIER) DMA Channel 1 Interrupt Enable */ +#define UOTGHS_HSTIER_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIER) DMA Channel 2 Interrupt Enable */ +#define UOTGHS_HSTIER_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIER) DMA Channel 3 Interrupt Enable */ +#define UOTGHS_HSTIER_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIER) DMA Channel 4 Interrupt Enable */ +#define UOTGHS_HSTIER_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIER) DMA Channel 5 Interrupt Enable */ +#define UOTGHS_HSTIER_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIER) DMA Channel 6 Interrupt Enable */ +#define UOTGHS_HSTIER_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_HSTIER) DMA Channel 7 Interrupt Enable */ +/* -------- UOTGHS_HSTPIP : (UOTGHS Offset: 0x0041C) Host Pipe Register -------- */ +#define UOTGHS_HSTPIP_PEN0 (0x1u << 0) /**< \brief (UOTGHS_HSTPIP) Pipe 0 Enable */ +#define UOTGHS_HSTPIP_PEN1 (0x1u << 1) /**< \brief (UOTGHS_HSTPIP) Pipe 1 Enable */ +#define UOTGHS_HSTPIP_PEN2 (0x1u << 2) /**< \brief (UOTGHS_HSTPIP) Pipe 2 Enable */ +#define UOTGHS_HSTPIP_PEN3 (0x1u << 3) /**< \brief (UOTGHS_HSTPIP) Pipe 3 Enable */ +#define UOTGHS_HSTPIP_PEN4 (0x1u << 4) /**< \brief (UOTGHS_HSTPIP) Pipe 4 Enable */ +#define UOTGHS_HSTPIP_PEN5 (0x1u << 5) /**< \brief (UOTGHS_HSTPIP) Pipe 5 Enable */ +#define UOTGHS_HSTPIP_PEN6 (0x1u << 6) /**< \brief (UOTGHS_HSTPIP) Pipe 6 Enable */ +#define UOTGHS_HSTPIP_PEN7 (0x1u << 7) /**< \brief (UOTGHS_HSTPIP) Pipe 7 Enable */ +#define UOTGHS_HSTPIP_PEN8 (0x1u << 8) /**< \brief (UOTGHS_HSTPIP) Pipe 8 Enable */ +#define UOTGHS_HSTPIP_PRST0 (0x1u << 16) /**< \brief (UOTGHS_HSTPIP) Pipe 0 Reset */ +#define UOTGHS_HSTPIP_PRST1 (0x1u << 17) /**< \brief (UOTGHS_HSTPIP) Pipe 1 Reset */ +#define UOTGHS_HSTPIP_PRST2 (0x1u << 18) /**< \brief (UOTGHS_HSTPIP) Pipe 2 Reset */ +#define UOTGHS_HSTPIP_PRST3 (0x1u << 19) /**< \brief (UOTGHS_HSTPIP) Pipe 3 Reset */ +#define UOTGHS_HSTPIP_PRST4 (0x1u << 20) /**< \brief (UOTGHS_HSTPIP) Pipe 4 Reset */ +#define UOTGHS_HSTPIP_PRST5 (0x1u << 21) /**< \brief (UOTGHS_HSTPIP) Pipe 5 Reset */ +#define UOTGHS_HSTPIP_PRST6 (0x1u << 22) /**< \brief (UOTGHS_HSTPIP) Pipe 6 Reset */ +#define UOTGHS_HSTPIP_PRST7 (0x1u << 23) /**< \brief (UOTGHS_HSTPIP) Pipe 7 Reset */ +#define UOTGHS_HSTPIP_PRST8 (0x1u << 24) /**< \brief (UOTGHS_HSTPIP) Pipe 8 Reset */ +/* -------- UOTGHS_HSTFNUM : (UOTGHS Offset: 0x0420) Host Frame Number Register -------- */ +#define UOTGHS_HSTFNUM_MFNUM_Pos 0 +#define UOTGHS_HSTFNUM_MFNUM_Msk (0x7u << UOTGHS_HSTFNUM_MFNUM_Pos) /**< \brief (UOTGHS_HSTFNUM) Micro Frame Number */ +#define UOTGHS_HSTFNUM_MFNUM(value) ((UOTGHS_HSTFNUM_MFNUM_Msk & ((value) << UOTGHS_HSTFNUM_MFNUM_Pos))) +#define UOTGHS_HSTFNUM_FNUM_Pos 3 +#define UOTGHS_HSTFNUM_FNUM_Msk (0x7ffu << UOTGHS_HSTFNUM_FNUM_Pos) /**< \brief (UOTGHS_HSTFNUM) Frame Number */ +#define UOTGHS_HSTFNUM_FNUM(value) ((UOTGHS_HSTFNUM_FNUM_Msk & ((value) << UOTGHS_HSTFNUM_FNUM_Pos))) +#define UOTGHS_HSTFNUM_FLENHIGH_Pos 16 +#define UOTGHS_HSTFNUM_FLENHIGH_Msk (0xffu << UOTGHS_HSTFNUM_FLENHIGH_Pos) /**< \brief (UOTGHS_HSTFNUM) Frame Length */ +#define UOTGHS_HSTFNUM_FLENHIGH(value) ((UOTGHS_HSTFNUM_FLENHIGH_Msk & ((value) << UOTGHS_HSTFNUM_FLENHIGH_Pos))) +/* -------- UOTGHS_HSTADDR1 : (UOTGHS Offset: 0x0424) Host Address 1 Register -------- */ +#define UOTGHS_HSTADDR1_HSTADDRP0_Pos 0 +#define UOTGHS_HSTADDR1_HSTADDRP0_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP0_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */ +#define UOTGHS_HSTADDR1_HSTADDRP0(value) ((UOTGHS_HSTADDR1_HSTADDRP0_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP0_Pos))) +#define UOTGHS_HSTADDR1_HSTADDRP1_Pos 8 +#define UOTGHS_HSTADDR1_HSTADDRP1_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP1_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */ +#define UOTGHS_HSTADDR1_HSTADDRP1(value) ((UOTGHS_HSTADDR1_HSTADDRP1_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP1_Pos))) +#define UOTGHS_HSTADDR1_HSTADDRP2_Pos 16 +#define UOTGHS_HSTADDR1_HSTADDRP2_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP2_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */ +#define UOTGHS_HSTADDR1_HSTADDRP2(value) ((UOTGHS_HSTADDR1_HSTADDRP2_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP2_Pos))) +#define UOTGHS_HSTADDR1_HSTADDRP3_Pos 24 +#define UOTGHS_HSTADDR1_HSTADDRP3_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP3_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */ +#define UOTGHS_HSTADDR1_HSTADDRP3(value) ((UOTGHS_HSTADDR1_HSTADDRP3_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP3_Pos))) +/* -------- UOTGHS_HSTADDR2 : (UOTGHS Offset: 0x0428) Host Address 2 Register -------- */ +#define UOTGHS_HSTADDR2_HSTADDRP4_Pos 0 +#define UOTGHS_HSTADDR2_HSTADDRP4_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP4_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */ +#define UOTGHS_HSTADDR2_HSTADDRP4(value) ((UOTGHS_HSTADDR2_HSTADDRP4_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP4_Pos))) +#define UOTGHS_HSTADDR2_HSTADDRP5_Pos 8 +#define UOTGHS_HSTADDR2_HSTADDRP5_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP5_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */ +#define UOTGHS_HSTADDR2_HSTADDRP5(value) ((UOTGHS_HSTADDR2_HSTADDRP5_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP5_Pos))) +#define UOTGHS_HSTADDR2_HSTADDRP6_Pos 16 +#define UOTGHS_HSTADDR2_HSTADDRP6_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP6_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */ +#define UOTGHS_HSTADDR2_HSTADDRP6(value) ((UOTGHS_HSTADDR2_HSTADDRP6_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP6_Pos))) +#define UOTGHS_HSTADDR2_HSTADDRP7_Pos 24 +#define UOTGHS_HSTADDR2_HSTADDRP7_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP7_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */ +#define UOTGHS_HSTADDR2_HSTADDRP7(value) ((UOTGHS_HSTADDR2_HSTADDRP7_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP7_Pos))) +/* -------- UOTGHS_HSTADDR3 : (UOTGHS Offset: 0x042C) Host Address 3 Register -------- */ +#define UOTGHS_HSTADDR3_HSTADDRP8_Pos 0 +#define UOTGHS_HSTADDR3_HSTADDRP8_Msk (0x7fu << UOTGHS_HSTADDR3_HSTADDRP8_Pos) /**< \brief (UOTGHS_HSTADDR3) USB Host Address */ +#define UOTGHS_HSTADDR3_HSTADDRP8(value) ((UOTGHS_HSTADDR3_HSTADDRP8_Msk & ((value) << UOTGHS_HSTADDR3_HSTADDRP8_Pos))) +#define UOTGHS_HSTADDR3_HSTADDRP9_Pos 8 +#define UOTGHS_HSTADDR3_HSTADDRP9_Msk (0x7fu << UOTGHS_HSTADDR3_HSTADDRP9_Pos) /**< \brief (UOTGHS_HSTADDR3) USB Host Address */ +#define UOTGHS_HSTADDR3_HSTADDRP9(value) ((UOTGHS_HSTADDR3_HSTADDRP9_Msk & ((value) << UOTGHS_HSTADDR3_HSTADDRP9_Pos))) +/* -------- UOTGHS_HSTPIPCFG[12] : (UOTGHS Offset: 0x500) Host Pipe Configuration Register (n = 0) -------- */ +#define UOTGHS_HSTPIPCFG_ALLOC (0x1u << 1) /**< \brief (UOTGHS_HSTPIPCFG[12]) Pipe Memory Allocate */ +#define UOTGHS_HSTPIPCFG_PBK_Pos 2 +#define UOTGHS_HSTPIPCFG_PBK_Msk (0x3u << UOTGHS_HSTPIPCFG_PBK_Pos) /**< \brief (UOTGHS_HSTPIPCFG[12]) Pipe Banks */ +#define UOTGHS_HSTPIPCFG_PBK_1_BANK (0x0u << 2) /**< \brief (UOTGHS_HSTPIPCFG[12]) Single-bank pipe */ +#define UOTGHS_HSTPIPCFG_PBK_2_BANK (0x1u << 2) /**< \brief (UOTGHS_HSTPIPCFG[12]) Double-bank pipe */ +#define UOTGHS_HSTPIPCFG_PBK_3_BANK (0x2u << 2) /**< \brief (UOTGHS_HSTPIPCFG[12]) Triple-bank pipe */ +#define UOTGHS_HSTPIPCFG_PSIZE_Pos 4 +#define UOTGHS_HSTPIPCFG_PSIZE_Msk (0x7u << UOTGHS_HSTPIPCFG_PSIZE_Pos) /**< \brief (UOTGHS_HSTPIPCFG[12]) Pipe Size */ +#define UOTGHS_HSTPIPCFG_PSIZE_8_BYTE (0x0u << 4) /**< \brief (UOTGHS_HSTPIPCFG[12]) 8 bytes */ +#define UOTGHS_HSTPIPCFG_PSIZE_16_BYTE (0x1u << 4) /**< \brief (UOTGHS_HSTPIPCFG[12]) 16 bytes */ +#define UOTGHS_HSTPIPCFG_PSIZE_32_BYTE (0x2u << 4) /**< \brief (UOTGHS_HSTPIPCFG[12]) 32 bytes */ +#define UOTGHS_HSTPIPCFG_PSIZE_64_BYTE (0x3u << 4) /**< \brief (UOTGHS_HSTPIPCFG[12]) 64 bytes */ +#define UOTGHS_HSTPIPCFG_PSIZE_128_BYTE (0x4u << 4) /**< \brief (UOTGHS_HSTPIPCFG[12]) 128 bytes */ +#define UOTGHS_HSTPIPCFG_PSIZE_256_BYTE (0x5u << 4) /**< \brief (UOTGHS_HSTPIPCFG[12]) 256 bytes */ +#define UOTGHS_HSTPIPCFG_PSIZE_512_BYTE (0x6u << 4) /**< \brief (UOTGHS_HSTPIPCFG[12]) 512 bytes */ +#define UOTGHS_HSTPIPCFG_PSIZE_1024_BYTE (0x7u << 4) /**< \brief (UOTGHS_HSTPIPCFG[12]) 1024 bytes */ +#define UOTGHS_HSTPIPCFG_PTOKEN_Pos 8 +#define UOTGHS_HSTPIPCFG_PTOKEN_Msk (0x3u << UOTGHS_HSTPIPCFG_PTOKEN_Pos) /**< \brief (UOTGHS_HSTPIPCFG[12]) Pipe Token */ +#define UOTGHS_HSTPIPCFG_PTOKEN_SETUP (0x0u << 8) /**< \brief (UOTGHS_HSTPIPCFG[12]) SETUP */ +#define UOTGHS_HSTPIPCFG_PTOKEN_IN (0x1u << 8) /**< \brief (UOTGHS_HSTPIPCFG[12]) IN */ +#define UOTGHS_HSTPIPCFG_PTOKEN_OUT (0x2u << 8) /**< \brief (UOTGHS_HSTPIPCFG[12]) OUT */ +#define UOTGHS_HSTPIPCFG_AUTOSW (0x1u << 10) /**< \brief (UOTGHS_HSTPIPCFG[12]) Automatic Switch */ +#define UOTGHS_HSTPIPCFG_PTYPE_Pos 12 +#define UOTGHS_HSTPIPCFG_PTYPE_Msk (0x3u << UOTGHS_HSTPIPCFG_PTYPE_Pos) /**< \brief (UOTGHS_HSTPIPCFG[12]) Pipe Type */ +#define UOTGHS_HSTPIPCFG_PTYPE_CTRL (0x0u << 12) /**< \brief (UOTGHS_HSTPIPCFG[12]) Control */ +#define UOTGHS_HSTPIPCFG_PTYPE_ISO (0x1u << 12) /**< \brief (UOTGHS_HSTPIPCFG[12]) Isochronous */ +#define UOTGHS_HSTPIPCFG_PTYPE_BLK (0x2u << 12) /**< \brief (UOTGHS_HSTPIPCFG[12]) Bulk */ +#define UOTGHS_HSTPIPCFG_PTYPE_INTRPT (0x3u << 12) /**< \brief (UOTGHS_HSTPIPCFG[12]) Interrupt */ +#define UOTGHS_HSTPIPCFG_PEPNUM_Pos 16 +#define UOTGHS_HSTPIPCFG_PEPNUM_Msk (0xfu << UOTGHS_HSTPIPCFG_PEPNUM_Pos) /**< \brief (UOTGHS_HSTPIPCFG[12]) Pipe Endpoint Number */ +#define UOTGHS_HSTPIPCFG_PEPNUM(value) ((UOTGHS_HSTPIPCFG_PEPNUM_Msk & ((value) << UOTGHS_HSTPIPCFG_PEPNUM_Pos))) +#define UOTGHS_HSTPIPCFG_INTFRQ_Pos 24 +#define UOTGHS_HSTPIPCFG_INTFRQ_Msk (0xffu << UOTGHS_HSTPIPCFG_INTFRQ_Pos) /**< \brief (UOTGHS_HSTPIPCFG[12]) Pipe Interrupt Request Frequency */ +#define UOTGHS_HSTPIPCFG_INTFRQ(value) ((UOTGHS_HSTPIPCFG_INTFRQ_Msk & ((value) << UOTGHS_HSTPIPCFG_INTFRQ_Pos))) +#define UOTGHS_HSTPIPCFG_PINGEN (0x1u << 20) /**< \brief (UOTGHS_HSTPIPCFG[12]) Ping Enable */ +#define UOTGHS_HSTPIPCFG_BINTERVAL_Pos 24 +#define UOTGHS_HSTPIPCFG_BINTERVAL_Msk (0xffu << UOTGHS_HSTPIPCFG_BINTERVAL_Pos) /**< \brief (UOTGHS_HSTPIPCFG[12]) Binterval Parameter for the Bulk-Out/Ping Transaction */ +#define UOTGHS_HSTPIPCFG_BINTERVAL(value) ((UOTGHS_HSTPIPCFG_BINTERVAL_Msk & ((value) << UOTGHS_HSTPIPCFG_BINTERVAL_Pos))) +/* -------- UOTGHS_HSTPIPISR[12] : (UOTGHS Offset: 0x530) Host Pipe Status Register (n = 0) -------- */ +#define UOTGHS_HSTPIPISR_RXINI (0x1u << 0) /**< \brief (UOTGHS_HSTPIPISR[12]) Received IN Data Interrupt */ +#define UOTGHS_HSTPIPISR_TXOUTI (0x1u << 1) /**< \brief (UOTGHS_HSTPIPISR[12]) Transmitted OUT Data Interrupt */ +#define UOTGHS_HSTPIPISR_TXSTPI (0x1u << 2) /**< \brief (UOTGHS_HSTPIPISR[12]) Transmitted SETUP Interrupt */ +#define UOTGHS_HSTPIPISR_PERRI (0x1u << 3) /**< \brief (UOTGHS_HSTPIPISR[12]) Pipe Error Interrupt */ +#define UOTGHS_HSTPIPISR_NAKEDI (0x1u << 4) /**< \brief (UOTGHS_HSTPIPISR[12]) NAKed Interrupt */ +#define UOTGHS_HSTPIPISR_OVERFI (0x1u << 5) /**< \brief (UOTGHS_HSTPIPISR[12]) Overflow Interrupt */ +#define UOTGHS_HSTPIPISR_RXSTALLDI (0x1u << 6) /**< \brief (UOTGHS_HSTPIPISR[12]) Received STALLed Interrupt */ +#define UOTGHS_HSTPIPISR_SHORTPACKETI (0x1u << 7) /**< \brief (UOTGHS_HSTPIPISR[12]) Short Packet Interrupt */ +#define UOTGHS_HSTPIPISR_DTSEQ_Pos 8 +#define UOTGHS_HSTPIPISR_DTSEQ_Msk (0x3u << UOTGHS_HSTPIPISR_DTSEQ_Pos) /**< \brief (UOTGHS_HSTPIPISR[12]) Data Toggle Sequence */ +#define UOTGHS_HSTPIPISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (UOTGHS_HSTPIPISR[12]) Data0 toggle sequence */ +#define UOTGHS_HSTPIPISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (UOTGHS_HSTPIPISR[12]) Data1 toggle sequence */ +#define UOTGHS_HSTPIPISR_NBUSYBK_Pos 12 +#define UOTGHS_HSTPIPISR_NBUSYBK_Msk (0x3u << UOTGHS_HSTPIPISR_NBUSYBK_Pos) /**< \brief (UOTGHS_HSTPIPISR[12]) Number of Busy Banks */ +#define UOTGHS_HSTPIPISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (UOTGHS_HSTPIPISR[12]) 0 busy bank (all banks free) */ +#define UOTGHS_HSTPIPISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (UOTGHS_HSTPIPISR[12]) 1 busy bank */ +#define UOTGHS_HSTPIPISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (UOTGHS_HSTPIPISR[12]) 2 busy banks */ +#define UOTGHS_HSTPIPISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (UOTGHS_HSTPIPISR[12]) 3 busy banks */ +#define UOTGHS_HSTPIPISR_CURRBK_Pos 14 +#define UOTGHS_HSTPIPISR_CURRBK_Msk (0x3u << UOTGHS_HSTPIPISR_CURRBK_Pos) /**< \brief (UOTGHS_HSTPIPISR[12]) Current Bank */ +#define UOTGHS_HSTPIPISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (UOTGHS_HSTPIPISR[12]) Current bank is bank0 */ +#define UOTGHS_HSTPIPISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (UOTGHS_HSTPIPISR[12]) Current bank is bank1 */ +#define UOTGHS_HSTPIPISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (UOTGHS_HSTPIPISR[12]) Current bank is bank2 */ +#define UOTGHS_HSTPIPISR_RWALL (0x1u << 16) /**< \brief (UOTGHS_HSTPIPISR[12]) Read-write Allowed */ +#define UOTGHS_HSTPIPISR_CFGOK (0x1u << 18) /**< \brief (UOTGHS_HSTPIPISR[12]) Configuration OK Status */ +#define UOTGHS_HSTPIPISR_PBYCT_Pos 20 +#define UOTGHS_HSTPIPISR_PBYCT_Msk (0x7ffu << UOTGHS_HSTPIPISR_PBYCT_Pos) /**< \brief (UOTGHS_HSTPIPISR[12]) Pipe Byte Count */ +#define UOTGHS_HSTPIPISR_UNDERFI (0x1u << 2) /**< \brief (UOTGHS_HSTPIPISR[12]) Underflow Interrupt */ +#define UOTGHS_HSTPIPISR_CRCERRI (0x1u << 6) /**< \brief (UOTGHS_HSTPIPISR[12]) CRC Error Interrupt */ +/* -------- UOTGHS_HSTPIPICR[12] : (UOTGHS Offset: 0x560) Host Pipe Clear Register (n = 0) -------- */ +#define UOTGHS_HSTPIPICR_RXINIC (0x1u << 0) /**< \brief (UOTGHS_HSTPIPICR[12]) Received IN Data Interrupt Clear */ +#define UOTGHS_HSTPIPICR_TXOUTIC (0x1u << 1) /**< \brief (UOTGHS_HSTPIPICR[12]) Transmitted OUT Data Interrupt Clear */ +#define UOTGHS_HSTPIPICR_TXSTPIC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPICR[12]) Transmitted SETUP Interrupt Clear */ +#define UOTGHS_HSTPIPICR_NAKEDIC (0x1u << 4) /**< \brief (UOTGHS_HSTPIPICR[12]) NAKed Interrupt Clear */ +#define UOTGHS_HSTPIPICR_OVERFIC (0x1u << 5) /**< \brief (UOTGHS_HSTPIPICR[12]) Overflow Interrupt Clear */ +#define UOTGHS_HSTPIPICR_RXSTALLDIC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPICR[12]) Received STALLed Interrupt Clear */ +#define UOTGHS_HSTPIPICR_SHORTPACKETIC (0x1u << 7) /**< \brief (UOTGHS_HSTPIPICR[12]) Short Packet Interrupt Clear */ +#define UOTGHS_HSTPIPICR_UNDERFIC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPICR[12]) Underflow Interrupt Clear */ +#define UOTGHS_HSTPIPICR_CRCERRIC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPICR[12]) CRC Error Interrupt Clear */ +/* -------- UOTGHS_HSTPIPIFR[12] : (UOTGHS Offset: 0x590) Host Pipe Set Register (n = 0) -------- */ +#define UOTGHS_HSTPIPIFR_RXINIS (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIFR[12]) Received IN Data Interrupt Set */ +#define UOTGHS_HSTPIPIFR_TXOUTIS (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIFR[12]) Transmitted OUT Data Interrupt Set */ +#define UOTGHS_HSTPIPIFR_TXSTPIS (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIFR[12]) Transmitted SETUP Interrupt Set */ +#define UOTGHS_HSTPIPIFR_PERRIS (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIFR[12]) Pipe Error Interrupt Set */ +#define UOTGHS_HSTPIPIFR_NAKEDIS (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIFR[12]) NAKed Interrupt Set */ +#define UOTGHS_HSTPIPIFR_OVERFIS (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIFR[12]) Overflow Interrupt Set */ +#define UOTGHS_HSTPIPIFR_RXSTALLDIS (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIFR[12]) Received STALLed Interrupt Set */ +#define UOTGHS_HSTPIPIFR_SHORTPACKETIS (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIFR[12]) Short Packet Interrupt Set */ +#define UOTGHS_HSTPIPIFR_NBUSYBKS (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIFR[12]) Number of Busy Banks Set */ +#define UOTGHS_HSTPIPIFR_UNDERFIS (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIFR[12]) Underflow Interrupt Set */ +#define UOTGHS_HSTPIPIFR_CRCERRIS (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIFR[12]) CRC Error Interrupt Set */ +/* -------- UOTGHS_HSTPIPIMR[12] : (UOTGHS Offset: 0x5C0) Host Pipe Mask Register (n = 0) -------- */ +#define UOTGHS_HSTPIPIMR_RXINE (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIMR[12]) Received IN Data Interrupt Enable */ +#define UOTGHS_HSTPIPIMR_TXOUTE (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIMR[12]) Transmitted OUT Data Interrupt Enable */ +#define UOTGHS_HSTPIPIMR_TXSTPE (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIMR[12]) Transmitted SETUP Interrupt Enable */ +#define UOTGHS_HSTPIPIMR_PERRE (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIMR[12]) Pipe Error Interrupt Enable */ +#define UOTGHS_HSTPIPIMR_NAKEDE (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIMR[12]) NAKed Interrupt Enable */ +#define UOTGHS_HSTPIPIMR_OVERFIE (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIMR[12]) Overflow Interrupt Enable */ +#define UOTGHS_HSTPIPIMR_RXSTALLDE (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIMR[12]) Received STALLed Interrupt Enable */ +#define UOTGHS_HSTPIPIMR_SHORTPACKETIE (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIMR[12]) Short Packet Interrupt Enable */ +#define UOTGHS_HSTPIPIMR_NBUSYBKE (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIMR[12]) Number of Busy Banks Interrupt Enable */ +#define UOTGHS_HSTPIPIMR_FIFOCON (0x1u << 14) /**< \brief (UOTGHS_HSTPIPIMR[12]) FIFO Control */ +#define UOTGHS_HSTPIPIMR_PDISHDMA (0x1u << 16) /**< \brief (UOTGHS_HSTPIPIMR[12]) Pipe Interrupts Disable HDMA Request Enable */ +#define UOTGHS_HSTPIPIMR_PFREEZE (0x1u << 17) /**< \brief (UOTGHS_HSTPIPIMR[12]) Pipe Freeze */ +#define UOTGHS_HSTPIPIMR_RSTDT (0x1u << 18) /**< \brief (UOTGHS_HSTPIPIMR[12]) Reset Data Toggle */ +#define UOTGHS_HSTPIPIMR_UNDERFIE (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIMR[12]) Underflow Interrupt Enable */ +#define UOTGHS_HSTPIPIMR_CRCERRE (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIMR[12]) CRC Error Interrupt Enable */ +/* -------- UOTGHS_HSTPIPIER[12] : (UOTGHS Offset: 0x5F0) Host Pipe Enable Register (n = 0) -------- */ +#define UOTGHS_HSTPIPIER_RXINES (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIER[12]) Received IN Data Interrupt Enable */ +#define UOTGHS_HSTPIPIER_TXOUTES (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIER[12]) Transmitted OUT Data Interrupt Enable */ +#define UOTGHS_HSTPIPIER_TXSTPES (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIER[12]) Transmitted SETUP Interrupt Enable */ +#define UOTGHS_HSTPIPIER_PERRES (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIER[12]) Pipe Error Interrupt Enable */ +#define UOTGHS_HSTPIPIER_NAKEDES (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIER[12]) NAKed Interrupt Enable */ +#define UOTGHS_HSTPIPIER_OVERFIES (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIER[12]) Overflow Interrupt Enable */ +#define UOTGHS_HSTPIPIER_RXSTALLDES (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIER[12]) Received STALLed Interrupt Enable */ +#define UOTGHS_HSTPIPIER_SHORTPACKETIES (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIER[12]) Short Packet Interrupt Enable */ +#define UOTGHS_HSTPIPIER_NBUSYBKES (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIER[12]) Number of Busy Banks Enable */ +#define UOTGHS_HSTPIPIER_PDISHDMAS (0x1u << 16) /**< \brief (UOTGHS_HSTPIPIER[12]) Pipe Interrupts Disable HDMA Request Enable */ +#define UOTGHS_HSTPIPIER_PFREEZES (0x1u << 17) /**< \brief (UOTGHS_HSTPIPIER[12]) Pipe Freeze Enable */ +#define UOTGHS_HSTPIPIER_RSTDTS (0x1u << 18) /**< \brief (UOTGHS_HSTPIPIER[12]) Reset Data Toggle Enable */ +#define UOTGHS_HSTPIPIER_UNDERFIES (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIER[12]) Underflow Interrupt Enable */ +#define UOTGHS_HSTPIPIER_CRCERRES (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIER[12]) CRC Error Interrupt Enable */ +/* -------- UOTGHS_HSTPIPIDR[12] : (UOTGHS Offset: 0x620) Host Pipe Disable Register (n = 0) -------- */ +#define UOTGHS_HSTPIPIDR_RXINEC (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIDR[12]) Received IN Data Interrupt Disable */ +#define UOTGHS_HSTPIPIDR_TXOUTEC (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIDR[12]) Transmitted OUT Data Interrupt Disable */ +#define UOTGHS_HSTPIPIDR_TXSTPEC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIDR[12]) Transmitted SETUP Interrupt Disable */ +#define UOTGHS_HSTPIPIDR_PERREC (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIDR[12]) Pipe Error Interrupt Disable */ +#define UOTGHS_HSTPIPIDR_NAKEDEC (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIDR[12]) NAKed Interrupt Disable */ +#define UOTGHS_HSTPIPIDR_OVERFIEC (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIDR[12]) Overflow Interrupt Disable */ +#define UOTGHS_HSTPIPIDR_RXSTALLDEC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIDR[12]) Received STALLed Interrupt Disable */ +#define UOTGHS_HSTPIPIDR_SHORTPACKETIEC (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIDR[12]) Short Packet Interrupt Disable */ +#define UOTGHS_HSTPIPIDR_NBUSYBKEC (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIDR[12]) Number of Busy Banks Disable */ +#define UOTGHS_HSTPIPIDR_FIFOCONC (0x1u << 14) /**< \brief (UOTGHS_HSTPIPIDR[12]) FIFO Control Disable */ +#define UOTGHS_HSTPIPIDR_PDISHDMAC (0x1u << 16) /**< \brief (UOTGHS_HSTPIPIDR[12]) Pipe Interrupts Disable HDMA Request Disable */ +#define UOTGHS_HSTPIPIDR_PFREEZEC (0x1u << 17) /**< \brief (UOTGHS_HSTPIPIDR[12]) Pipe Freeze Disable */ +#define UOTGHS_HSTPIPIDR_UNDERFIEC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIDR[12]) Underflow Interrupt Disable */ +#define UOTGHS_HSTPIPIDR_CRCERREC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIDR[12]) CRC Error Interrupt Disable */ +/* -------- UOTGHS_HSTPIPINRQ[12] : (UOTGHS Offset: 0x650) Host Pipe IN Request Register (n = 0) -------- */ +#define UOTGHS_HSTPIPINRQ_INRQ_Pos 0 +#define UOTGHS_HSTPIPINRQ_INRQ_Msk (0xffu << UOTGHS_HSTPIPINRQ_INRQ_Pos) /**< \brief (UOTGHS_HSTPIPINRQ[12]) IN Request Number before Freeze */ +#define UOTGHS_HSTPIPINRQ_INRQ(value) ((UOTGHS_HSTPIPINRQ_INRQ_Msk & ((value) << UOTGHS_HSTPIPINRQ_INRQ_Pos))) +#define UOTGHS_HSTPIPINRQ_INMODE (0x1u << 8) /**< \brief (UOTGHS_HSTPIPINRQ[12]) IN Request Mode */ +/* -------- UOTGHS_HSTPIPERR[12] : (UOTGHS Offset: 0x680) Host Pipe Error Register (n = 0) -------- */ +#define UOTGHS_HSTPIPERR_DATATGL (0x1u << 0) /**< \brief (UOTGHS_HSTPIPERR[12]) Data Toggle Error */ +#define UOTGHS_HSTPIPERR_DATAPID (0x1u << 1) /**< \brief (UOTGHS_HSTPIPERR[12]) Data PID Error */ +#define UOTGHS_HSTPIPERR_PID (0x1u << 2) /**< \brief (UOTGHS_HSTPIPERR[12]) PID Error */ +#define UOTGHS_HSTPIPERR_TIMEOUT (0x1u << 3) /**< \brief (UOTGHS_HSTPIPERR[12]) Time-Out Error */ +#define UOTGHS_HSTPIPERR_CRC16 (0x1u << 4) /**< \brief (UOTGHS_HSTPIPERR[12]) CRC16 Error */ +#define UOTGHS_HSTPIPERR_COUNTER_Pos 5 +#define UOTGHS_HSTPIPERR_COUNTER_Msk (0x3u << UOTGHS_HSTPIPERR_COUNTER_Pos) /**< \brief (UOTGHS_HSTPIPERR[12]) Error Counter */ +#define UOTGHS_HSTPIPERR_COUNTER(value) ((UOTGHS_HSTPIPERR_COUNTER_Msk & ((value) << UOTGHS_HSTPIPERR_COUNTER_Pos))) +/* -------- UOTGHS_HSTDMANXTDSC : (UOTGHS Offset: N/A) Host DMA Channel Next Descriptor Address Register -------- */ +#define UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos 0 +#define UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (UOTGHS_HSTDMANXTDSC) Next Descriptor Address */ +#define UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD(value) ((UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos))) +/* -------- UOTGHS_HSTDMAADDRESS : (UOTGHS Offset: N/A) Host DMA Channel Address Register -------- */ +#define UOTGHS_HSTDMAADDRESS_BUFF_ADD_Pos 0 +#define UOTGHS_HSTDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << UOTGHS_HSTDMAADDRESS_BUFF_ADD_Pos) /**< \brief (UOTGHS_HSTDMAADDRESS) Buffer Address */ +#define UOTGHS_HSTDMAADDRESS_BUFF_ADD(value) ((UOTGHS_HSTDMAADDRESS_BUFF_ADD_Msk & ((value) << UOTGHS_HSTDMAADDRESS_BUFF_ADD_Pos))) +/* -------- UOTGHS_HSTDMACONTROL : (UOTGHS Offset: N/A) Host DMA Channel Control Register -------- */ +#define UOTGHS_HSTDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_HSTDMACONTROL) Channel Enable Command */ +#define UOTGHS_HSTDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (UOTGHS_HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */ +#define UOTGHS_HSTDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (UOTGHS_HSTDMACONTROL) End of Transfer Enable (Control) */ +#define UOTGHS_HSTDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (UOTGHS_HSTDMACONTROL) End of Buffer Enable Control */ +#define UOTGHS_HSTDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (UOTGHS_HSTDMACONTROL) End of Transfer Interrupt Enable */ +#define UOTGHS_HSTDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (UOTGHS_HSTDMACONTROL) End of Buffer Interrupt Enable */ +#define UOTGHS_HSTDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (UOTGHS_HSTDMACONTROL) Descriptor Loaded Interrupt Enable */ +#define UOTGHS_HSTDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (UOTGHS_HSTDMACONTROL) Burst Lock Enable */ +#define UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Pos 16 +#define UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Msk (0xffffu << UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (UOTGHS_HSTDMACONTROL) Buffer Byte Length (Write-only) */ +#define UOTGHS_HSTDMACONTROL_BUFF_LENGTH(value) ((UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Msk & ((value) << UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Pos))) +/* -------- UOTGHS_HSTDMASTATUS : (UOTGHS Offset: N/A) Host DMA Channel Status Register -------- */ +#define UOTGHS_HSTDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_HSTDMASTATUS) Channel Enable Status */ +#define UOTGHS_HSTDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (UOTGHS_HSTDMASTATUS) Channel Active Status */ +#define UOTGHS_HSTDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (UOTGHS_HSTDMASTATUS) End of Channel Transfer Status */ +#define UOTGHS_HSTDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (UOTGHS_HSTDMASTATUS) End of Channel Buffer Status */ +#define UOTGHS_HSTDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (UOTGHS_HSTDMASTATUS) Descriptor Loaded Status */ +#define UOTGHS_HSTDMASTATUS_BUFF_COUNT_Pos 16 +#define UOTGHS_HSTDMASTATUS_BUFF_COUNT_Msk (0xffffu << UOTGHS_HSTDMASTATUS_BUFF_COUNT_Pos) /**< \brief (UOTGHS_HSTDMASTATUS) Buffer Byte Count */ +#define UOTGHS_HSTDMASTATUS_BUFF_COUNT(value) ((UOTGHS_HSTDMASTATUS_BUFF_COUNT_Msk & ((value) << UOTGHS_HSTDMASTATUS_BUFF_COUNT_Pos))) +/* -------- UOTGHS_CTRL : (UOTGHS Offset: 0x0800) General Control Register -------- */ +#define UOTGHS_CTRL_IDTE (0x1u << 0) /**< \brief (UOTGHS_CTRL) ID Transition Interrupt Enable */ +#define UOTGHS_CTRL_VBUSTE (0x1u << 1) /**< \brief (UOTGHS_CTRL) VBus Transition Interrupt Enable */ +#define UOTGHS_CTRL_SRPE (0x1u << 2) /**< \brief (UOTGHS_CTRL) SRP Interrupt Enable */ +#define UOTGHS_CTRL_VBERRE (0x1u << 3) /**< \brief (UOTGHS_CTRL) VBus Error Interrupt Enable */ +#define UOTGHS_CTRL_BCERRE (0x1u << 4) /**< \brief (UOTGHS_CTRL) B-Connection Error Interrupt Enable */ +#define UOTGHS_CTRL_ROLEEXE (0x1u << 5) /**< \brief (UOTGHS_CTRL) Role Exchange Interrupt Enable */ +#define UOTGHS_CTRL_HNPERRE (0x1u << 6) /**< \brief (UOTGHS_CTRL) HNP Error Interrupt Enable */ +#define UOTGHS_CTRL_STOE (0x1u << 7) /**< \brief (UOTGHS_CTRL) Suspend Time-Out Interrupt Enable */ +#define UOTGHS_CTRL_VBUSHWC (0x1u << 8) /**< \brief (UOTGHS_CTRL) VBus Hardware Control */ +#define UOTGHS_CTRL_SRPSEL (0x1u << 9) /**< \brief (UOTGHS_CTRL) SRP Selection */ +#define UOTGHS_CTRL_SRPREQ (0x1u << 10) /**< \brief (UOTGHS_CTRL) SRP Request */ +#define UOTGHS_CTRL_HNPREQ (0x1u << 11) /**< \brief (UOTGHS_CTRL) HNP Request */ +#define UOTGHS_CTRL_OTGPADE (0x1u << 12) /**< \brief (UOTGHS_CTRL) OTG Pad Enable */ +#define UOTGHS_CTRL_VBUSPO (0x1u << 13) /**< \brief (UOTGHS_CTRL) VBus Polarity Off */ +#define UOTGHS_CTRL_FRZCLK (0x1u << 14) /**< \brief (UOTGHS_CTRL) Freeze USB Clock */ +#define UOTGHS_CTRL_USBE (0x1u << 15) /**< \brief (UOTGHS_CTRL) UOTGHS Enable */ +#define UOTGHS_CTRL_TIMVALUE_Pos 16 +#define UOTGHS_CTRL_TIMVALUE_Msk (0x3u << UOTGHS_CTRL_TIMVALUE_Pos) /**< \brief (UOTGHS_CTRL) Timer Value */ +#define UOTGHS_CTRL_TIMVALUE(value) ((UOTGHS_CTRL_TIMVALUE_Msk & ((value) << UOTGHS_CTRL_TIMVALUE_Pos))) +#define UOTGHS_CTRL_TIMPAGE_Pos 20 +#define UOTGHS_CTRL_TIMPAGE_Msk (0x3u << UOTGHS_CTRL_TIMPAGE_Pos) /**< \brief (UOTGHS_CTRL) Timer Page */ +#define UOTGHS_CTRL_TIMPAGE(value) ((UOTGHS_CTRL_TIMPAGE_Msk & ((value) << UOTGHS_CTRL_TIMPAGE_Pos))) +#define UOTGHS_CTRL_UNLOCK (0x1u << 22) /**< \brief (UOTGHS_CTRL) Timer Access Unlock */ +#define UOTGHS_CTRL_UIDE (0x1u << 24) /**< \brief (UOTGHS_CTRL) UOTGID Pin Enable */ +#define UOTGHS_CTRL_UIDE_UIMOD (0x0u << 24) /**< \brief (UOTGHS_CTRL) The USB mode (device/host) is selected from the UIMOD bit. */ +#define UOTGHS_CTRL_UIDE_UOTGID (0x1u << 24) /**< \brief (UOTGHS_CTRL) The USB mode (device/host) is selected from the UOTGID input pin. */ +#define UOTGHS_CTRL_UIMOD (0x1u << 25) /**< \brief (UOTGHS_CTRL) UOTGHS Mode */ +#define UOTGHS_CTRL_UIMOD_HOST (0x0u << 25) /**< \brief (UOTGHS_CTRL) The module is in USB host mode. */ +#define UOTGHS_CTRL_UIMOD_DEVICE (0x1u << 25) /**< \brief (UOTGHS_CTRL) The module is in USB device mode. */ +/* -------- UOTGHS_SR : (UOTGHS Offset: 0x0804) General Status Register -------- */ +#define UOTGHS_SR_IDTI (0x1u << 0) /**< \brief (UOTGHS_SR) ID Transition Interrupt */ +#define UOTGHS_SR_VBUSTI (0x1u << 1) /**< \brief (UOTGHS_SR) VBus Transition Interrupt */ +#define UOTGHS_SR_SRPI (0x1u << 2) /**< \brief (UOTGHS_SR) SRP Interrupt */ +#define UOTGHS_SR_VBERRI (0x1u << 3) /**< \brief (UOTGHS_SR) VBus Error Interrupt */ +#define UOTGHS_SR_BCERRI (0x1u << 4) /**< \brief (UOTGHS_SR) B-Connection Error Interrupt */ +#define UOTGHS_SR_ROLEEXI (0x1u << 5) /**< \brief (UOTGHS_SR) Role Exchange Interrupt */ +#define UOTGHS_SR_HNPERRI (0x1u << 6) /**< \brief (UOTGHS_SR) HNP Error Interrupt */ +#define UOTGHS_SR_STOI (0x1u << 7) /**< \brief (UOTGHS_SR) Suspend Time-Out Interrupt */ +#define UOTGHS_SR_VBUSRQ (0x1u << 9) /**< \brief (UOTGHS_SR) VBus Request */ +#define UOTGHS_SR_ID (0x1u << 10) /**< \brief (UOTGHS_SR) UOTGID Pin State */ +#define UOTGHS_SR_VBUS (0x1u << 11) /**< \brief (UOTGHS_SR) VBus Level */ +#define UOTGHS_SR_SPEED_Pos 12 +#define UOTGHS_SR_SPEED_Msk (0x3u << UOTGHS_SR_SPEED_Pos) /**< \brief (UOTGHS_SR) Speed Status */ +#define UOTGHS_SR_SPEED_FULL_SPEED (0x0u << 12) /**< \brief (UOTGHS_SR) Full-Speed mode */ +#define UOTGHS_SR_SPEED_HIGH_SPEED (0x1u << 12) /**< \brief (UOTGHS_SR) High-Speed mode */ +#define UOTGHS_SR_SPEED_LOW_SPEED (0x2u << 12) /**< \brief (UOTGHS_SR) Low-Speed mode */ +#define UOTGHS_SR_CLKUSABLE (0x1u << 14) /**< \brief (UOTGHS_SR) UTMI Clock Usable */ +/* -------- UOTGHS_SCR : (UOTGHS Offset: 0x0808) General Status Clear Register -------- */ +#define UOTGHS_SCR_IDTIC (0x1u << 0) /**< \brief (UOTGHS_SCR) ID Transition Interrupt Clear */ +#define UOTGHS_SCR_VBUSTIC (0x1u << 1) /**< \brief (UOTGHS_SCR) VBus Transition Interrupt Clear */ +#define UOTGHS_SCR_SRPIC (0x1u << 2) /**< \brief (UOTGHS_SCR) SRP Interrupt Clear */ +#define UOTGHS_SCR_VBERRIC (0x1u << 3) /**< \brief (UOTGHS_SCR) VBus Error Interrupt Clear */ +#define UOTGHS_SCR_BCERRIC (0x1u << 4) /**< \brief (UOTGHS_SCR) B-Connection Error Interrupt Clear */ +#define UOTGHS_SCR_ROLEEXIC (0x1u << 5) /**< \brief (UOTGHS_SCR) Role Exchange Interrupt Clear */ +#define UOTGHS_SCR_HNPERRIC (0x1u << 6) /**< \brief (UOTGHS_SCR) HNP Error Interrupt Clear */ +#define UOTGHS_SCR_STOIC (0x1u << 7) /**< \brief (UOTGHS_SCR) Suspend Time-Out Interrupt Clear */ +#define UOTGHS_SCR_VBUSRQC (0x1u << 9) /**< \brief (UOTGHS_SCR) VBus Request Clear */ +/* -------- UOTGHS_SFR : (UOTGHS Offset: 0x080C) General Status Set Register -------- */ +#define UOTGHS_SFR_IDTIS (0x1u << 0) /**< \brief (UOTGHS_SFR) ID Transition Interrupt Set */ +#define UOTGHS_SFR_VBUSTIS (0x1u << 1) /**< \brief (UOTGHS_SFR) VBus Transition Interrupt Set */ +#define UOTGHS_SFR_SRPIS (0x1u << 2) /**< \brief (UOTGHS_SFR) SRP Interrupt Set */ +#define UOTGHS_SFR_VBERRIS (0x1u << 3) /**< \brief (UOTGHS_SFR) VBus Error Interrupt Set */ +#define UOTGHS_SFR_BCERRIS (0x1u << 4) /**< \brief (UOTGHS_SFR) B-Connection Error Interrupt Set */ +#define UOTGHS_SFR_ROLEEXIS (0x1u << 5) /**< \brief (UOTGHS_SFR) Role Exchange Interrupt Set */ +#define UOTGHS_SFR_HNPERRIS (0x1u << 6) /**< \brief (UOTGHS_SFR) HNP Error Interrupt Set */ +#define UOTGHS_SFR_STOIS (0x1u << 7) /**< \brief (UOTGHS_SFR) Suspend Time-Out Interrupt Set */ +#define UOTGHS_SFR_VBUSRQS (0x1u << 9) /**< \brief (UOTGHS_SFR) VBus Request Set */ +/* -------- UOTGHS_TSTA1 : (UOTGHS Offset: 0x0810) General Test A1 Register -------- */ +#define UOTGHS_TSTA1_CounterA_Pos 0 +#define UOTGHS_TSTA1_CounterA_Msk (0x7fffu << UOTGHS_TSTA1_CounterA_Pos) /**< \brief (UOTGHS_TSTA1) Load CounterA */ +#define UOTGHS_TSTA1_CounterA(value) ((UOTGHS_TSTA1_CounterA_Msk & ((value) << UOTGHS_TSTA1_CounterA_Pos))) +#define UOTGHS_TSTA1_LoadCntA (0x1u << 15) /**< \brief (UOTGHS_TSTA1) Load CounterA */ +#define UOTGHS_TSTA1_CounterB_Pos 16 +#define UOTGHS_TSTA1_CounterB_Msk (0x3fu << UOTGHS_TSTA1_CounterB_Pos) /**< \brief (UOTGHS_TSTA1) Load CounterB */ +#define UOTGHS_TSTA1_CounterB(value) ((UOTGHS_TSTA1_CounterB_Msk & ((value) << UOTGHS_TSTA1_CounterB_Pos))) +#define UOTGHS_TSTA1_LoadCntB (0x1u << 23) /**< \brief (UOTGHS_TSTA1) Load CounterB */ +#define UOTGHS_TSTA1_SOFCntMa1_Pos 24 +#define UOTGHS_TSTA1_SOFCntMa1_Msk (0x7fu << UOTGHS_TSTA1_SOFCntMa1_Pos) /**< \brief (UOTGHS_TSTA1) SOF Counter Max */ +#define UOTGHS_TSTA1_SOFCntMa1(value) ((UOTGHS_TSTA1_SOFCntMa1_Msk & ((value) << UOTGHS_TSTA1_SOFCntMa1_Pos))) +#define UOTGHS_TSTA1_LoadSOFCnt (0x1u << 31) /**< \brief (UOTGHS_TSTA1) Load SOF Counter */ +/* -------- UOTGHS_TSTA2 : (UOTGHS Offset: 0x0814) General Test A2 Register -------- */ +#define UOTGHS_TSTA2_FullDetachEn (0x1u << 0) /**< \brief (UOTGHS_TSTA2) Full Detach Enable */ +#define UOTGHS_TSTA2_HSSerialMode (0x1u << 1) /**< \brief (UOTGHS_TSTA2) HS Serial Mode */ +#define UOTGHS_TSTA2_LoopBackMode (0x1u << 2) /**< \brief (UOTGHS_TSTA2) Loop-back Mode */ +#define UOTGHS_TSTA2_DisableGatedClock (0x1u << 3) /**< \brief (UOTGHS_TSTA2) Disable Gated Clock */ +#define UOTGHS_TSTA2_ForceSuspendMTo1 (0x1u << 4) /**< \brief (UOTGHS_TSTA2) Force SuspendM to 1 */ +#define UOTGHS_TSTA2_ByPassDpll (0x1u << 5) /**< \brief (UOTGHS_TSTA2) Bypass DPLL */ +#define UOTGHS_TSTA2_HostHSDisconnectDisable (0x1u << 6) /**< \brief (UOTGHS_TSTA2) Host HS Disconnect Disable */ +#define UOTGHS_TSTA2_ForceHSRst_50ms (0x1u << 7) /**< \brief (UOTGHS_TSTA2) Force HS Reset to 50 ms */ +#define UOTGHS_TSTA2_UTMIReset (0x1u << 8) /**< \brief (UOTGHS_TSTA2) UTMI Reset */ +#define UOTGHS_TSTA2_RemovePUWhenTX (0x1u << 9) /**< \brief (UOTGHS_TSTA2) Remove Pull-up When TX */ +/* -------- UOTGHS_VERSION : (UOTGHS Offset: 0x0818) General Version Register -------- */ +#define UOTGHS_VERSION_VERSION_Pos 0 +#define UOTGHS_VERSION_VERSION_Msk (0xfffu << UOTGHS_VERSION_VERSION_Pos) /**< \brief (UOTGHS_VERSION) Version Number */ +#define UOTGHS_VERSION_VARIANT_Pos 16 +#define UOTGHS_VERSION_VARIANT_Msk (0xfu << UOTGHS_VERSION_VARIANT_Pos) /**< \brief (UOTGHS_VERSION) Variant Number */ +/* -------- UOTGHS_FEATURES : (UOTGHS Offset: 0x081C) General Features Register -------- */ +#define UOTGHS_FEATURES_EPTNBRMAX_Pos 0 +#define UOTGHS_FEATURES_EPTNBRMAX_Msk (0xfu << UOTGHS_FEATURES_EPTNBRMAX_Pos) /**< \brief (UOTGHS_FEATURES) Maximal Number of Pipes/Endpoints */ +#define UOTGHS_FEATURES_EPTNBRMAX_16_P_E (0x0u << 0) /**< \brief (UOTGHS_FEATURES) 16 pipes/endpoints */ +#define UOTGHS_FEATURES_EPTNBRMAX_1_P_E (0x1u << 0) /**< \brief (UOTGHS_FEATURES) 1 pipe/endpoint */ +#define UOTGHS_FEATURES_EPTNBRMAX_2_P_E (0x2u << 0) /**< \brief (UOTGHS_FEATURES) 2 pipes/endpoints */ +#define UOTGHS_FEATURES_EPTNBRMAX_15_P_E (0xFu << 0) /**< \brief (UOTGHS_FEATURES) 15 pipes/endpoints */ +#define UOTGHS_FEATURES_DMACHANNELNBR_Pos 4 +#define UOTGHS_FEATURES_DMACHANNELNBR_Msk (0x7u << UOTGHS_FEATURES_DMACHANNELNBR_Pos) /**< \brief (UOTGHS_FEATURES) Number of DMA Channels */ +#define UOTGHS_FEATURES_DMACHANNELNBR_1_DMA_CH (0x1u << 4) /**< \brief (UOTGHS_FEATURES) 1 DMA channel */ +#define UOTGHS_FEATURES_DMACHANNELNBR_2_DMA_CH (0x2u << 4) /**< \brief (UOTGHS_FEATURES) 2 DMA channels */ +#define UOTGHS_FEATURES_DMACHANNELNBR_7_DMA_CH (0x7u << 4) /**< \brief (UOTGHS_FEATURES) 7 DMA channels */ +#define UOTGHS_FEATURES_DMABUFFERSIZE (0x1u << 7) /**< \brief (UOTGHS_FEATURES) DMA Buffer Size */ +#define UOTGHS_FEATURES_DMAFIFOWORDDEPTH_Pos 8 +#define UOTGHS_FEATURES_DMAFIFOWORDDEPTH_Msk (0xfu << UOTGHS_FEATURES_DMAFIFOWORDDEPTH_Pos) /**< \brief (UOTGHS_FEATURES) DMA FIFO Depth in Words */ +#define UOTGHS_FEATURES_DMAFIFOWORDDEPTH_16_DMA_F_D (0x0u << 8) /**< \brief (UOTGHS_FEATURES) 16 DMA FIFO depth */ +#define UOTGHS_FEATURES_DMAFIFOWORDDEPTH_1_DMA_F_D (0x1u << 8) /**< \brief (UOTGHS_FEATURES) 1 DMA FIFO depth */ +#define UOTGHS_FEATURES_DMAFIFOWORDDEPTH_2_DMA_F_D (0x2u << 8) /**< \brief (UOTGHS_FEATURES) 2 DMA FIFO depth */ +#define UOTGHS_FEATURES_DMAFIFOWORDDEPTH_15_DMA_F_D (0xFu << 8) /**< \brief (UOTGHS_FEATURES) 15 DMA FIFO depth */ +#define UOTGHS_FEATURES_FIFOMAXSIZE_Pos 12 +#define UOTGHS_FEATURES_FIFOMAXSIZE_Msk (0x7u << UOTGHS_FEATURES_FIFOMAXSIZE_Pos) /**< \brief (UOTGHS_FEATURES) Maximal FIFO Size */ +#define UOTGHS_FEATURES_FIFOMAXSIZE_256_BYTE (0x0u << 12) /**< \brief (UOTGHS_FEATURES) < 256 bytes */ +#define UOTGHS_FEATURES_FIFOMAXSIZE_512_BYTE (0x1u << 12) /**< \brief (UOTGHS_FEATURES) < 512 bytes */ +#define UOTGHS_FEATURES_FIFOMAXSIZE_1024_BYTE (0x2u << 12) /**< \brief (UOTGHS_FEATURES) < 1024 bytes */ +#define UOTGHS_FEATURES_FIFOMAXSIZE_2048_BYTE (0x3u << 12) /**< \brief (UOTGHS_FEATURES) < 2048 bytes */ +#define UOTGHS_FEATURES_FIFOMAXSIZE_4096_BYTE (0x4u << 12) /**< \brief (UOTGHS_FEATURES) < 4096 bytes */ +#define UOTGHS_FEATURES_FIFOMAXSIZE_8192_BYTE (0x5u << 12) /**< \brief (UOTGHS_FEATURES) < 8192 bytes */ +#define UOTGHS_FEATURES_FIFOMAXSIZE_16384_BYTE (0x6u << 12) /**< \brief (UOTGHS_FEATURES) < 16384 bytes */ +#define UOTGHS_FEATURES_FIFOMAXSIZE_P16384_BYTE (0x7u << 12) /**< \brief (UOTGHS_FEATURES) >= 16384 bytes */ +#define UOTGHS_FEATURES_BYTEWRITEDPRAM (0x1u << 15) /**< \brief (UOTGHS_FEATURES) DPRAM Byte-Write Capability */ +#define UOTGHS_FEATURES_DATABUS (0x1u << 16) /**< \brief (UOTGHS_FEATURES) Data Bus 16-8 */ +#define UOTGHS_FEATURES_ENHBISO1 (0x1u << 17) /**< \brief (UOTGHS_FEATURES) High Bandwidth Isochronous Feature for Endpoint 1 */ +#define UOTGHS_FEATURES_ENHBISO2 (0x1u << 18) /**< \brief (UOTGHS_FEATURES) High Bandwidth Isochronous Feature for Endpoint 2 */ +#define UOTGHS_FEATURES_ENHBISO3 (0x1u << 19) /**< \brief (UOTGHS_FEATURES) High Bandwidth Isochronous Feature for Endpoint 3 */ +#define UOTGHS_FEATURES_ENHBISO4 (0x1u << 20) /**< \brief (UOTGHS_FEATURES) High Bandwidth Isochronous Feature for Endpoint 4 */ +#define UOTGHS_FEATURES_ENHBISO5 (0x1u << 21) /**< \brief (UOTGHS_FEATURES) High Bandwidth Isochronous Feature for Endpoint 5 */ +#define UOTGHS_FEATURES_ENHBISO6 (0x1u << 22) /**< \brief (UOTGHS_FEATURES) High Bandwidth Isochronous Feature for Endpoint 6 */ +#define UOTGHS_FEATURES_ENHBISO7 (0x1u << 23) /**< \brief (UOTGHS_FEATURES) High Bandwidth Isochronous Feature for Endpoint 7 */ +/* -------- UOTGHS_ADDRSIZE : (UOTGHS Offset: 0x0820) General APB Address Size Register -------- */ +#define UOTGHS_ADDRSIZE_UOTGHS_ADDRSIZE_Pos 0 +#define UOTGHS_ADDRSIZE_UOTGHS_ADDRSIZE_Msk (0xffffffffu << UOTGHS_ADDRSIZE_UOTGHS_ADDRSIZE_Pos) /**< \brief (UOTGHS_ADDRSIZE) IP APB Address Size */ +/* -------- UOTGHS_IPNAME1 : (UOTGHS Offset: 0x0824) General Name Register 1 -------- */ +#define UOTGHS_IPNAME1_UOTGHS_IPNAME1_Pos 0 +#define UOTGHS_IPNAME1_UOTGHS_IPNAME1_Msk (0xffffffffu << UOTGHS_IPNAME1_UOTGHS_IPNAME1_Pos) /**< \brief (UOTGHS_IPNAME1) IP Name Part One */ +/* -------- UOTGHS_IPNAME2 : (UOTGHS Offset: 0x0828) General Name Register 2 -------- */ +#define UOTGHS_IPNAME2_UOTGHS_IPNAME2_Pos 0 +#define UOTGHS_IPNAME2_UOTGHS_IPNAME2_Msk (0xffffffffu << UOTGHS_IPNAME2_UOTGHS_IPNAME2_Pos) /**< \brief (UOTGHS_IPNAME2) IP Name Part Two */ +/* -------- UOTGHS_FSM : (UOTGHS Offset: 0x082C) General Finite State Machine Register -------- */ +#define UOTGHS_FSM_DRDSTATE_Pos 0 +#define UOTGHS_FSM_DRDSTATE_Msk (0xfu << UOTGHS_FSM_DRDSTATE_Pos) /**< \brief (UOTGHS_FSM) Dual Role Device State */ +#define UOTGHS_FSM_DRDSTATE_A_IDLESTATE (0x0u << 0) /**< \brief (UOTGHS_FSM) This is the start state for A-devices (when the ID pin is 0) */ +#define UOTGHS_FSM_DRDSTATE_A_WAIT_VRISE (0x1u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the voltage on VBus to rise above the A-device VBus Valid threshold (4.4 V). */ +#define UOTGHS_FSM_DRDSTATE_A_WAIT_BCON (0x2u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the B-device to signal a connection. */ +#define UOTGHS_FSM_DRDSTATE_A_HOST (0x3u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device that operates in Host mode is operational. */ +#define UOTGHS_FSM_DRDSTATE_A_SUSPEND (0x4u << 0) /**< \brief (UOTGHS_FSM) The A-device operating as a host is in the suspend mode. */ +#define UOTGHS_FSM_DRDSTATE_A_PERIPHERAL (0x5u << 0) /**< \brief (UOTGHS_FSM) The A-device operates as a peripheral. */ +#define UOTGHS_FSM_DRDSTATE_A_WAIT_VFALL (0x6u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the voltage on VBus to drop below the A-device Session Valid threshold (1.4 V). */ +#define UOTGHS_FSM_DRDSTATE_A_VBUS_ERR (0x7u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for recovery of the over-current condition that caused it to enter this state. */ +#define UOTGHS_FSM_DRDSTATE_A_WAIT_DISCHARGE (0x8u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the data USB line to discharge (100 us). */ +#define UOTGHS_FSM_DRDSTATE_B_IDLE (0x9u << 0) /**< \brief (UOTGHS_FSM) This is the start state for B-device (when the ID pin is 1). */ +#define UOTGHS_FSM_DRDSTATE_B_PERIPHERAL (0xAu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device acts as the peripheral. */ +#define UOTGHS_FSM_DRDSTATE_B_WAIT_BEGIN_HNP (0xBu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device is in suspend mode and waits until 3 ms before initiating the HNP protocol if requested. */ +#define UOTGHS_FSM_DRDSTATE_B_WAIT_DISCHARGE (0xCu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device waits for the data USB line to discharge (100 us) before becoming Host. */ +#define UOTGHS_FSM_DRDSTATE_B_WAIT_ACON (0xDu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device waits for the A-device to signal a connect before becoming B-Host. */ +#define UOTGHS_FSM_DRDSTATE_B_HOST (0xEu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device acts as the Host. */ +#define UOTGHS_FSM_DRDSTATE_B_SRP_INIT (0xFu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device attempts to start a session using the SRP protocol. */ + +/*@}*/ + + +#endif /* _SAM_UOTGHS_COMPONENT_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_usart.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_usart.h new file mode 100644 index 00000000..00a4564d --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_usart.h @@ -0,0 +1,425 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_USART_COMPONENT_ +#define _SAMV71_USART_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */ +/* ============================================================================= */ +/** \addtogroup SAMV71_USART Universal Synchronous Asynchronous Receiver Transmitter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Usart hardware registers */ +typedef struct { + __O uint32_t US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */ + __IO uint32_t US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */ + __O uint32_t US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */ + __O uint32_t US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */ + __I uint32_t US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */ + __I uint32_t US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */ + __I uint32_t US_RHR; /**< \brief (Usart Offset: 0x0018) Receive Holding Register */ + __O uint32_t US_THR; /**< \brief (Usart Offset: 0x001C) Transmit Holding Register */ + __IO uint32_t US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */ + __IO uint32_t US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */ + __IO uint32_t US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */ + __I uint32_t Reserved1[5]; + __IO uint32_t US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */ + __I uint32_t US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */ + __I uint32_t Reserved2[2]; + __IO uint32_t US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Configuration Register */ + __IO uint32_t US_LINMR; /**< \brief (Usart Offset: 0x0054) LIN Mode Register */ + __IO uint32_t US_LINIR; /**< \brief (Usart Offset: 0x0058) LIN Identifier Register */ + __I uint32_t US_LINBRR; /**< \brief (Usart Offset: 0x005C) LIN Baud Rate Register */ + __IO uint32_t US_LONMR; /**< \brief (Usart Offset: 0x0060) LON Mode Register */ + __IO uint32_t US_LONPR; /**< \brief (Usart Offset: 0x0064) LON Preamble Register */ + __IO uint32_t US_LONDL; /**< \brief (Usart Offset: 0x0068) LON Data Length Register */ + __IO uint32_t US_LONL2HDR; /**< \brief (Usart Offset: 0x006C) LON L2HDR Register */ + __I uint32_t US_LONBL; /**< \brief (Usart Offset: 0x0070) LON Backlog Register */ + __IO uint32_t US_LONB1TX; /**< \brief (Usart Offset: 0x0074) LON Beta1 Tx Register */ + __IO uint32_t US_LONB1RX; /**< \brief (Usart Offset: 0x0078) LON Beta1 Rx Register */ + __IO uint32_t US_LONPRIO; /**< \brief (Usart Offset: 0x007C) LON Priority Register */ + __IO uint32_t US_IDTTX; /**< \brief (Usart Offset: 0x0080) LON IDT Tx Register */ + __IO uint32_t US_IDTRX; /**< \brief (Usart Offset: 0x0084) LON IDT Rx Register */ + __IO uint32_t US_ICDIFF; /**< \brief (Usart Offset: 0x0088) IC DIFF Register */ + __I uint32_t Reserved3[22]; + __IO uint32_t US_WPMR; /**< \brief (Usart Offset: 0x00E4) Write Protection Mode Register */ + __I uint32_t US_WPSR; /**< \brief (Usart Offset: 0x00E8) Write Protection Status Register */ +} Usart; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */ +#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */ +#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */ +#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */ +#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */ +#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */ +#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */ +#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */ +#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */ +#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */ +#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Clear TIMEOUT Flag and Start Time-out After Next Character Received */ +#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */ +#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */ +#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */ +#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Start Time-out Immediately */ +#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Pin Control */ +#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Pin Control */ +#define US_CR_LINABT (0x1u << 20) /**< \brief (US_CR) Abort LIN Transmission */ +#define US_CR_LINWKUP (0x1u << 21) /**< \brief (US_CR) Send LIN Wakeup Signal */ +#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */ +#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */ +/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */ +#define US_MR_USART_MODE_Pos 0 +#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR) USART Mode of Operation */ +#define US_MR_USART_MODE(value) ((US_MR_USART_MODE_Msk & ((value) << US_MR_USART_MODE_Pos))) +#define US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */ +#define US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */ +#define US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */ +#define US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */ +#define US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */ +#define US_MR_USART_MODE_LON (0x9u << 0) /**< \brief (US_MR) LON */ +#define US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI master */ +#define US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */ +#define US_MR_USCLKS_Pos 4 +#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */ +#define US_MR_USCLKS(value) ((US_MR_USCLKS_Msk & ((value) << US_MR_USCLKS_Pos))) +#define US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Peripheral clock is selected */ +#define US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Peripheral clock divided (DIV=DIV=8) is selected */ +#define US_MR_USCLKS_PCK (0x2u << 4) /**< \brief (US_MR) PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1. */ +#define US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial clock (SCK) is selected */ +#define US_MR_CHRL_Pos 6 +#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length */ +#define US_MR_CHRL(value) ((US_MR_CHRL_Msk & ((value) << US_MR_CHRL_Pos))) +#define US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */ +#define US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */ +#define US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */ +#define US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */ +#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */ +#define US_MR_PAR_Pos 9 +#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */ +#define US_MR_PAR(value) ((US_MR_PAR_Msk & ((value) << US_MR_PAR_Pos))) +#define US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */ +#define US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */ +#define US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */ +#define US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */ +#define US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */ +#define US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */ +#define US_MR_NBSTOP_Pos 12 +#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */ +#define US_MR_NBSTOP(value) ((US_MR_NBSTOP_Msk & ((value) << US_MR_NBSTOP_Pos))) +#define US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */ +#define US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */ +#define US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */ +#define US_MR_CHMODE_Pos 14 +#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */ +#define US_MR_CHMODE(value) ((US_MR_CHMODE_Msk & ((value) << US_MR_CHMODE_Pos))) +#define US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal mode */ +#define US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */ +#define US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */ +#define US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */ +#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */ +#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */ +#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */ +#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */ +#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Receive Line Filter */ +#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */ +#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */ +#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */ +#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */ +#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */ +#define US_MR_WRDBT (0x1u << 20) /**< \brief (US_MR) Wait Read Data Before Transfer */ +/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */ +#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */ +#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */ +#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */ +#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */ +#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */ +#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */ +#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */ +#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */ +#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */ +#define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */ +#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error Interrupt Enable */ +#define US_IER_LINBK (0x1u << 13) /**< \brief (US_IER) LIN Break Sent or LIN Break Received Interrupt Enable */ +#define US_IER_LINID (0x1u << 14) /**< \brief (US_IER) LIN Identifier Sent or LIN Identifier Received Interrupt Enable */ +#define US_IER_LINTC (0x1u << 15) /**< \brief (US_IER) LIN Transfer Completed Interrupt Enable */ +#define US_IER_LINBE (0x1u << 25) /**< \brief (US_IER) LIN Bus Error Interrupt Enable */ +#define US_IER_LINISFE (0x1u << 26) /**< \brief (US_IER) LIN Inconsistent Synch Field Error Interrupt Enable */ +#define US_IER_LINIPE (0x1u << 27) /**< \brief (US_IER) LIN Identifier Parity Interrupt Enable */ +#define US_IER_LINCE (0x1u << 28) /**< \brief (US_IER) LIN Checksum Error Interrupt Enable */ +#define US_IER_LINSNRE (0x1u << 29) /**< \brief (US_IER) LIN Slave Not Responding Error Interrupt Enable */ +#define US_IER_LINSTE (0x1u << 30) /**< \brief (US_IER) LIN Synch Tolerance Error Interrupt Enable */ +#define US_IER_LINHTE (0x1u << 31) /**< \brief (US_IER) LIN Header Timeout Error Interrupt Enable */ +#define US_IER_LSFE (0x1u << 6) /**< \brief (US_IER) LON Short Frame Error Interrupt Enable */ +#define US_IER_LCRCE (0x1u << 7) /**< \brief (US_IER) LON CRC Error Interrupt Enable */ +#define US_IER_LTXD (0x1u << 24) /**< \brief (US_IER) LON Transmission Done Interrupt Enable */ +#define US_IER_LCOL (0x1u << 25) /**< \brief (US_IER) LON Collision Interrupt Enable */ +#define US_IER_LFET (0x1u << 26) /**< \brief (US_IER) LON Frame Early Termination Interrupt Enable */ +#define US_IER_LRXD (0x1u << 27) /**< \brief (US_IER) LON Reception Done Interrupt Enable */ +#define US_IER_LBLOVFE (0x1u << 28) /**< \brief (US_IER) LON Backlog Overflow Error Interrupt Enable */ +/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */ +#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */ +#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */ +#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */ +#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Enable */ +#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */ +#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */ +#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */ +#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */ +#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */ +#define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */ +#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Interrupt Disable */ +#define US_IDR_LINBK (0x1u << 13) /**< \brief (US_IDR) LIN Break Sent or LIN Break Received Interrupt Disable */ +#define US_IDR_LINID (0x1u << 14) /**< \brief (US_IDR) LIN Identifier Sent or LIN Identifier Received Interrupt Disable */ +#define US_IDR_LINTC (0x1u << 15) /**< \brief (US_IDR) LIN Transfer Completed Interrupt Disable */ +#define US_IDR_LINBE (0x1u << 25) /**< \brief (US_IDR) LIN Bus Error Interrupt Disable */ +#define US_IDR_LINISFE (0x1u << 26) /**< \brief (US_IDR) LIN Inconsistent Synch Field Error Interrupt Disable */ +#define US_IDR_LINIPE (0x1u << 27) /**< \brief (US_IDR) LIN Identifier Parity Interrupt Disable */ +#define US_IDR_LINCE (0x1u << 28) /**< \brief (US_IDR) LIN Checksum Error Interrupt Disable */ +#define US_IDR_LINSNRE (0x1u << 29) /**< \brief (US_IDR) LIN Slave Not Responding Error Interrupt Disable */ +#define US_IDR_LINSTE (0x1u << 30) /**< \brief (US_IDR) LIN Synch Tolerance Error Interrupt Disable */ +#define US_IDR_LINHTE (0x1u << 31) /**< \brief (US_IDR) LIN Header Timeout Error Interrupt Disable */ +#define US_IDR_LSFE (0x1u << 6) /**< \brief (US_IDR) LON Short Frame Error Interrupt Disable */ +#define US_IDR_LCRCE (0x1u << 7) /**< \brief (US_IDR) LON CRC Error Interrupt Disable */ +#define US_IDR_LTXD (0x1u << 24) /**< \brief (US_IDR) LON Transmission Done Interrupt Disable */ +#define US_IDR_LCOL (0x1u << 25) /**< \brief (US_IDR) LON Collision Interrupt Disable */ +#define US_IDR_LFET (0x1u << 26) /**< \brief (US_IDR) LON Frame Early Termination Interrupt Disable */ +#define US_IDR_LRXD (0x1u << 27) /**< \brief (US_IDR) LON Reception Done Interrupt Disable */ +#define US_IDR_LBLOVFE (0x1u << 28) /**< \brief (US_IDR) LON Backlog Overflow Error Interrupt Disable */ +/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */ +#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */ +#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */ +#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */ +#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */ +#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */ +#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */ +#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */ +#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */ +#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */ +#define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */ +#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Interrupt Mask */ +#define US_IMR_LINBK (0x1u << 13) /**< \brief (US_IMR) LIN Break Sent or LIN Break Received Interrupt Mask */ +#define US_IMR_LINID (0x1u << 14) /**< \brief (US_IMR) LIN Identifier Sent or LIN Identifier Received Interrupt Mask */ +#define US_IMR_LINTC (0x1u << 15) /**< \brief (US_IMR) LIN Transfer Completed Interrupt Mask */ +#define US_IMR_LINBE (0x1u << 25) /**< \brief (US_IMR) LIN Bus Error Interrupt Mask */ +#define US_IMR_LINISFE (0x1u << 26) /**< \brief (US_IMR) LIN Inconsistent Synch Field Error Interrupt Mask */ +#define US_IMR_LINIPE (0x1u << 27) /**< \brief (US_IMR) LIN Identifier Parity Interrupt Mask */ +#define US_IMR_LINCE (0x1u << 28) /**< \brief (US_IMR) LIN Checksum Error Interrupt Mask */ +#define US_IMR_LINSNRE (0x1u << 29) /**< \brief (US_IMR) LIN Slave Not Responding Error Interrupt Mask */ +#define US_IMR_LINSTE (0x1u << 30) /**< \brief (US_IMR) LIN Synch Tolerance Error Interrupt Mask */ +#define US_IMR_LINHTE (0x1u << 31) /**< \brief (US_IMR) LIN Header Timeout Error Interrupt Mask */ +#define US_IMR_LSFE (0x1u << 6) /**< \brief (US_IMR) LON Short Frame Error Interrupt Mask */ +#define US_IMR_LCRCE (0x1u << 7) /**< \brief (US_IMR) LON CRC Error Interrupt Mask */ +#define US_IMR_LTXD (0x1u << 24) /**< \brief (US_IMR) LON Transmission Done Interrupt Mask */ +#define US_IMR_LCOL (0x1u << 25) /**< \brief (US_IMR) LON Collision Interrupt Mask */ +#define US_IMR_LFET (0x1u << 26) /**< \brief (US_IMR) LON Frame Early Termination Interrupt Mask */ +#define US_IMR_LRXD (0x1u << 27) /**< \brief (US_IMR) LON Reception Done Interrupt Mask */ +#define US_IMR_LBLOVFE (0x1u << 28) /**< \brief (US_IMR) LON Backlog Overflow Error Interrupt Mask */ +/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */ +#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready (cleared by reading US_RHR) */ +#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready (cleared by writing US_THR) */ +#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out (cleared by writing a one to bit US_CR.STTTO) */ +#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty (cleared by writing US_THR) */ +#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non AcknowledgeInterrupt */ +#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag (cleared on read) */ +#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */ +#define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) */ +#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) Underrun Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINBK (0x1u << 13) /**< \brief (US_CSR) LIN Break Sent or LIN Break Received (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINID (0x1u << 14) /**< \brief (US_CSR) LIN Identifier Sent or LIN Identifier Received (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINTC (0x1u << 15) /**< \brief (US_CSR) LIN Transfer Completed (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINBLS (0x1u << 23) /**< \brief (US_CSR) LIN Bus Line Status */ +#define US_CSR_LINBE (0x1u << 25) /**< \brief (US_CSR) LIN Bit Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINISFE (0x1u << 26) /**< \brief (US_CSR) LIN Inconsistent Synch Field Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINIPE (0x1u << 27) /**< \brief (US_CSR) LIN Identifier Parity Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINCE (0x1u << 28) /**< \brief (US_CSR) LIN Checksum Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINSNRE (0x1u << 29) /**< \brief (US_CSR) LIN Slave Not Responding Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINSTE (0x1u << 30) /**< \brief (US_CSR) LIN Synch Tolerance Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINHTE (0x1u << 31) /**< \brief (US_CSR) LIN Header Timeout Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LSFE (0x1u << 6) /**< \brief (US_CSR) LON Short Frame Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LCRCE (0x1u << 7) /**< \brief (US_CSR) LON CRC Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LTXD (0x1u << 24) /**< \brief (US_CSR) LON Transmission End Flag (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LCOL (0x1u << 25) /**< \brief (US_CSR) LON Collision Detected Flag (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LFET (0x1u << 26) /**< \brief (US_CSR) LON Frame Early Termination (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LRXD (0x1u << 27) /**< \brief (US_CSR) LON Reception End Flag (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LBLOVFE (0x1u << 28) /**< \brief (US_CSR) LON Backlog Overflow Error (cleared by writing a one to bit US_CR.RSTSTA) */ +/* -------- US_RHR : (USART Offset: 0x0018) Receive Holding Register -------- */ +#define US_RHR_RXCHR_Pos 0 +#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */ +#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */ +/* -------- US_THR : (USART Offset: 0x001C) Transmit Holding Register -------- */ +#define US_THR_TXCHR_Pos 0 +#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */ +#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos))) +#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be Transmitted */ +/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */ +#define US_BRGR_CD_Pos 0 +#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */ +#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos))) +#define US_BRGR_FP_Pos 16 +#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */ +#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos))) +/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */ +#define US_RTOR_TO_Pos 0 +#define US_RTOR_TO_Msk (0x1ffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */ +#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos))) +/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */ +#define US_TTGR_TG_Pos 0 +#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */ +#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos))) +#define US_TTGR_PCYCLE_Pos 0 +#define US_TTGR_PCYCLE_Msk (0xffffffu << US_TTGR_PCYCLE_Pos) /**< \brief (US_TTGR) LON PCYCLE Length */ +#define US_TTGR_PCYCLE(value) ((US_TTGR_PCYCLE_Msk & ((value) << US_TTGR_PCYCLE_Pos))) +/* -------- US_MAN : (USART Offset: 0x0050) Manchester Configuration Register -------- */ +#define US_MAN_TX_PL_Pos 0 +#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */ +#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos))) +#define US_MAN_TX_PP_Pos 8 +#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */ +#define US_MAN_TX_PP(value) ((US_MAN_TX_PP_Msk & ((value) << US_MAN_TX_PP_Pos))) +#define US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */ +#define US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */ +#define US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */ +#define US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */ +#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */ +#define US_MAN_RX_PL_Pos 16 +#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */ +#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos))) +#define US_MAN_RX_PP_Pos 24 +#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */ +#define US_MAN_RX_PP(value) ((US_MAN_RX_PP_Msk & ((value) << US_MAN_RX_PP_Pos))) +#define US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */ +#define US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */ +#define US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */ +#define US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */ +#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */ +#define US_MAN_ONE (0x1u << 29) /**< \brief (US_MAN) Must Be Set to 1 */ +#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift Compensation */ +#define US_MAN_RXIDLEV (0x1u << 31) /**< \brief (US_MAN) */ +/* -------- US_LINMR : (USART Offset: 0x0054) LIN Mode Register -------- */ +#define US_LINMR_NACT_Pos 0 +#define US_LINMR_NACT_Msk (0x3u << US_LINMR_NACT_Pos) /**< \brief (US_LINMR) LIN Node Action */ +#define US_LINMR_NACT(value) ((US_LINMR_NACT_Msk & ((value) << US_LINMR_NACT_Pos))) +#define US_LINMR_NACT_PUBLISH (0x0u << 0) /**< \brief (US_LINMR) The USART transmits the response. */ +#define US_LINMR_NACT_SUBSCRIBE (0x1u << 0) /**< \brief (US_LINMR) The USART receives the response. */ +#define US_LINMR_NACT_IGNORE (0x2u << 0) /**< \brief (US_LINMR) The USART does not transmit and does not receive the response. */ +#define US_LINMR_PARDIS (0x1u << 2) /**< \brief (US_LINMR) Parity Disable */ +#define US_LINMR_CHKDIS (0x1u << 3) /**< \brief (US_LINMR) Checksum Disable */ +#define US_LINMR_CHKTYP (0x1u << 4) /**< \brief (US_LINMR) Checksum Type */ +#define US_LINMR_DLM (0x1u << 5) /**< \brief (US_LINMR) Data Length Mode */ +#define US_LINMR_FSDIS (0x1u << 6) /**< \brief (US_LINMR) Frame Slot Mode Disable */ +#define US_LINMR_WKUPTYP (0x1u << 7) /**< \brief (US_LINMR) Wakeup Signal Type */ +#define US_LINMR_DLC_Pos 8 +#define US_LINMR_DLC_Msk (0xffu << US_LINMR_DLC_Pos) /**< \brief (US_LINMR) Data Length Control */ +#define US_LINMR_DLC(value) ((US_LINMR_DLC_Msk & ((value) << US_LINMR_DLC_Pos))) +#define US_LINMR_PDCM (0x1u << 16) /**< \brief (US_LINMR) DMAC Mode */ +#define US_LINMR_SYNCDIS (0x1u << 17) /**< \brief (US_LINMR) Synchronization Disable */ +/* -------- US_LINIR : (USART Offset: 0x0058) LIN Identifier Register -------- */ +#define US_LINIR_IDCHR_Pos 0 +#define US_LINIR_IDCHR_Msk (0xffu << US_LINIR_IDCHR_Pos) /**< \brief (US_LINIR) Identifier Character */ +#define US_LINIR_IDCHR(value) ((US_LINIR_IDCHR_Msk & ((value) << US_LINIR_IDCHR_Pos))) +/* -------- US_LINBRR : (USART Offset: 0x005C) LIN Baud Rate Register -------- */ +#define US_LINBRR_LINCD_Pos 0 +#define US_LINBRR_LINCD_Msk (0xffffu << US_LINBRR_LINCD_Pos) /**< \brief (US_LINBRR) Clock Divider after Synchronization */ +#define US_LINBRR_LINFP_Pos 16 +#define US_LINBRR_LINFP_Msk (0x7u << US_LINBRR_LINFP_Pos) /**< \brief (US_LINBRR) Fractional Part after Synchronization */ +/* -------- US_LONMR : (USART Offset: 0x0060) LON Mode Register -------- */ +#define US_LONMR_COMMT (0x1u << 0) /**< \brief (US_LONMR) LON comm_type Parameter Value */ +#define US_LONMR_COLDET (0x1u << 1) /**< \brief (US_LONMR) LON Collision Detection Feature */ +#define US_LONMR_TCOL (0x1u << 2) /**< \brief (US_LONMR) Terminate Frame upon Collision Notification */ +#define US_LONMR_CDTAIL (0x1u << 3) /**< \brief (US_LONMR) LON Collision Detection on Frame Tail */ +#define US_LONMR_DMAM (0x1u << 4) /**< \brief (US_LONMR) LON DMA Mode */ +#define US_LONMR_LCDS (0x1u << 5) /**< \brief (US_LONMR) LON Collision Detection Source */ +#define US_LONMR_EOFS_Pos 16 +#define US_LONMR_EOFS_Msk (0xffu << US_LONMR_EOFS_Pos) /**< \brief (US_LONMR) End of Frame Condition Size */ +#define US_LONMR_EOFS(value) ((US_LONMR_EOFS_Msk & ((value) << US_LONMR_EOFS_Pos))) +/* -------- US_LONPR : (USART Offset: 0x0064) LON Preamble Register -------- */ +#define US_LONPR_LONPL_Pos 0 +#define US_LONPR_LONPL_Msk (0x3fffu << US_LONPR_LONPL_Pos) /**< \brief (US_LONPR) LON Preamble Length */ +#define US_LONPR_LONPL(value) ((US_LONPR_LONPL_Msk & ((value) << US_LONPR_LONPL_Pos))) +/* -------- US_LONDL : (USART Offset: 0x0068) LON Data Length Register -------- */ +#define US_LONDL_LONDL_Pos 0 +#define US_LONDL_LONDL_Msk (0xffu << US_LONDL_LONDL_Pos) /**< \brief (US_LONDL) LON Data Length */ +#define US_LONDL_LONDL(value) ((US_LONDL_LONDL_Msk & ((value) << US_LONDL_LONDL_Pos))) +/* -------- US_LONL2HDR : (USART Offset: 0x006C) LON L2HDR Register -------- */ +#define US_LONL2HDR_BLI_Pos 0 +#define US_LONL2HDR_BLI_Msk (0x3fu << US_LONL2HDR_BLI_Pos) /**< \brief (US_LONL2HDR) LON Backlog Increment */ +#define US_LONL2HDR_BLI(value) ((US_LONL2HDR_BLI_Msk & ((value) << US_LONL2HDR_BLI_Pos))) +#define US_LONL2HDR_ALTP (0x1u << 6) /**< \brief (US_LONL2HDR) LON Alternate Path Bit */ +#define US_LONL2HDR_PB (0x1u << 7) /**< \brief (US_LONL2HDR) LON Priority Bit */ +/* -------- US_LONBL : (USART Offset: 0x0070) LON Backlog Register -------- */ +#define US_LONBL_LONBL_Pos 0 +#define US_LONBL_LONBL_Msk (0x3fu << US_LONBL_LONBL_Pos) /**< \brief (US_LONBL) LON Node Backlog Value */ +/* -------- US_LONB1TX : (USART Offset: 0x0074) LON Beta1 Tx Register -------- */ +#define US_LONB1TX_BETA1TX_Pos 0 +#define US_LONB1TX_BETA1TX_Msk (0xffffffu << US_LONB1TX_BETA1TX_Pos) /**< \brief (US_LONB1TX) LON Beta1 Length after Transmission */ +#define US_LONB1TX_BETA1TX(value) ((US_LONB1TX_BETA1TX_Msk & ((value) << US_LONB1TX_BETA1TX_Pos))) +/* -------- US_LONB1RX : (USART Offset: 0x0078) LON Beta1 Rx Register -------- */ +#define US_LONB1RX_BETA1RX_Pos 0 +#define US_LONB1RX_BETA1RX_Msk (0xffffffu << US_LONB1RX_BETA1RX_Pos) /**< \brief (US_LONB1RX) LON Beta1 Length after Reception */ +#define US_LONB1RX_BETA1RX(value) ((US_LONB1RX_BETA1RX_Msk & ((value) << US_LONB1RX_BETA1RX_Pos))) +/* -------- US_LONPRIO : (USART Offset: 0x007C) LON Priority Register -------- */ +#define US_LONPRIO_PSNB_Pos 0 +#define US_LONPRIO_PSNB_Msk (0x7fu << US_LONPRIO_PSNB_Pos) /**< \brief (US_LONPRIO) LON Priority Slot Number */ +#define US_LONPRIO_PSNB(value) ((US_LONPRIO_PSNB_Msk & ((value) << US_LONPRIO_PSNB_Pos))) +#define US_LONPRIO_NPS_Pos 8 +#define US_LONPRIO_NPS_Msk (0x7fu << US_LONPRIO_NPS_Pos) /**< \brief (US_LONPRIO) LON Node Priority Slot */ +#define US_LONPRIO_NPS(value) ((US_LONPRIO_NPS_Msk & ((value) << US_LONPRIO_NPS_Pos))) +/* -------- US_IDTTX : (USART Offset: 0x0080) LON IDT Tx Register -------- */ +#define US_IDTTX_IDTTX_Pos 0 +#define US_IDTTX_IDTTX_Msk (0xffffffu << US_IDTTX_IDTTX_Pos) /**< \brief (US_IDTTX) LON Indeterminate Time after Transmission (comm_type = 1 mode only) */ +#define US_IDTTX_IDTTX(value) ((US_IDTTX_IDTTX_Msk & ((value) << US_IDTTX_IDTTX_Pos))) +/* -------- US_IDTRX : (USART Offset: 0x0084) LON IDT Rx Register -------- */ +#define US_IDTRX_IDTRX_Pos 0 +#define US_IDTRX_IDTRX_Msk (0xffffffu << US_IDTRX_IDTRX_Pos) /**< \brief (US_IDTRX) LON Indeterminate Time after Reception (comm_type = 1 mode only) */ +#define US_IDTRX_IDTRX(value) ((US_IDTRX_IDTRX_Msk & ((value) << US_IDTRX_IDTRX_Pos))) +/* -------- US_ICDIFF : (USART Offset: 0x0088) IC DIFF Register -------- */ +#define US_ICDIFF_ICDIFF_Pos 0 +#define US_ICDIFF_ICDIFF_Msk (0xfu << US_ICDIFF_ICDIFF_Pos) /**< \brief (US_ICDIFF) IC Differentiator Number */ +#define US_ICDIFF_ICDIFF(value) ((US_ICDIFF_ICDIFF_Msk & ((value) << US_ICDIFF_ICDIFF_Pos))) +/* -------- US_WPMR : (USART Offset: 0x00E4) Write Protection Mode Register -------- */ +#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protection Enable */ +#define US_WPMR_WPKEY_Pos 8 +#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protection Key */ +#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos))) +#define US_WPMR_WPKEY_PASSWD (0x555341u << 8) /**< \brief (US_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- US_WPSR : (USART Offset: 0x00E8) Write Protection Status Register -------- */ +#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protection Violation Status */ +#define US_WPSR_WPVSRC_Pos 8 +#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAMV71_USART_COMPONENT_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_usbhs.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_usbhs.h new file mode 100644 index 00000000..c3aac2d5 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_usbhs.h @@ -0,0 +1,960 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_USBHS_COMPONENT_ +#define _SAMV71_USBHS_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR USB High-Speed Interface */ +/* ============================================================================= */ +/** \addtogroup SAMV71_USBHS USB High-Speed Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief UsbhsDevdma hardware registers */ +typedef struct { + __IO uint32_t USBHS_DEVDMANXTDSC; /**< \brief (UsbhsDevdma Offset: 0x0) Device DMA Channel Next Descriptor Address Register */ + __IO uint32_t USBHS_DEVDMAADDRESS; /**< \brief (UsbhsDevdma Offset: 0x4) Device DMA Channel Address Register */ + __IO uint32_t USBHS_DEVDMACONTROL; /**< \brief (UsbhsDevdma Offset: 0x8) Device DMA Channel Control Register */ + __IO uint32_t USBHS_DEVDMASTATUS; /**< \brief (UsbhsDevdma Offset: 0xC) Device DMA Channel Status Register */ +} UsbhsDevdma; +/** \brief UsbhsHstdma hardware registers */ +typedef struct { + __IO uint32_t USBHS_HSTDMANXTDSC; /**< \brief (UsbhsHstdma Offset: 0x0) Host DMA Channel Next Descriptor Address Register */ + __IO uint32_t USBHS_HSTDMAADDRESS; /**< \brief (UsbhsHstdma Offset: 0x4) Host DMA Channel Address Register */ + __IO uint32_t USBHS_HSTDMACONTROL; /**< \brief (UsbhsHstdma Offset: 0x8) Host DMA Channel Control Register */ + __IO uint32_t USBHS_HSTDMASTATUS; /**< \brief (UsbhsHstdma Offset: 0xC) Host DMA Channel Status Register */ +} UsbhsHstdma; +/** \brief Usbhs hardware registers */ +#define USBHSDEVDMA_NUMBER 7 +#define USBHSHSTDMA_NUMBER 7 +typedef struct { + __IO uint32_t USBHS_DEVCTRL; /**< \brief (Usbhs Offset: 0x0000) Device General Control Register */ + __I uint32_t USBHS_DEVISR; /**< \brief (Usbhs Offset: 0x0004) Device Global Interrupt Status Register */ + __O uint32_t USBHS_DEVICR; /**< \brief (Usbhs Offset: 0x0008) Device Global Interrupt Clear Register */ + __O uint32_t USBHS_DEVIFR; /**< \brief (Usbhs Offset: 0x000C) Device Global Interrupt Set Register */ + __I uint32_t USBHS_DEVIMR; /**< \brief (Usbhs Offset: 0x0010) Device Global Interrupt Mask Register */ + __O uint32_t USBHS_DEVIDR; /**< \brief (Usbhs Offset: 0x0014) Device Global Interrupt Disable Register */ + __O uint32_t USBHS_DEVIER; /**< \brief (Usbhs Offset: 0x0018) Device Global Interrupt Enable Register */ + __IO uint32_t USBHS_DEVEPT; /**< \brief (Usbhs Offset: 0x001C) Device Endpoint Register */ + __I uint32_t USBHS_DEVFNUM; /**< \brief (Usbhs Offset: 0x0020) Device Frame Number Register */ + __I uint32_t Reserved1[55]; + __IO uint32_t USBHS_DEVEPTCFG[10]; /**< \brief (Usbhs Offset: 0x100) Device Endpoint Configuration Register (n = 0) */ + __I uint32_t Reserved2[2]; + __I uint32_t USBHS_DEVEPTISR[10]; /**< \brief (Usbhs Offset: 0x130) Device Endpoint Status Register (n = 0) */ + __I uint32_t Reserved3[2]; + __O uint32_t USBHS_DEVEPTICR[10]; /**< \brief (Usbhs Offset: 0x160) Device Endpoint Clear Register (n = 0) */ + __I uint32_t Reserved4[2]; + __O uint32_t USBHS_DEVEPTIFR[10]; /**< \brief (Usbhs Offset: 0x190) Device Endpoint Set Register (n = 0) */ + __I uint32_t Reserved5[2]; + __I uint32_t USBHS_DEVEPTIMR[10]; /**< \brief (Usbhs Offset: 0x1C0) Device Endpoint Mask Register (n = 0) */ + __I uint32_t Reserved6[2]; + __O uint32_t USBHS_DEVEPTIER[10]; /**< \brief (Usbhs Offset: 0x1F0) Device Endpoint Enable Register (n = 0) */ + __I uint32_t Reserved7[2]; + __O uint32_t USBHS_DEVEPTIDR[10]; /**< \brief (Usbhs Offset: 0x220) Device Endpoint Disable Register (n = 0) */ + __I uint32_t Reserved8[50]; + UsbhsDevdma USBHS_DEVDMA[USBHSDEVDMA_NUMBER]; /**< \brief (Usbhs Offset: 0x310) n = 1 .. 7 */ + __I uint32_t Reserved9[32]; + __IO uint32_t USBHS_HSTCTRL; /**< \brief (Usbhs Offset: 0x0400) Host General Control Register */ + __I uint32_t USBHS_HSTISR; /**< \brief (Usbhs Offset: 0x0404) Host Global Interrupt Status Register */ + __O uint32_t USBHS_HSTICR; /**< \brief (Usbhs Offset: 0x0408) Host Global Interrupt Clear Register */ + __O uint32_t USBHS_HSTIFR; /**< \brief (Usbhs Offset: 0x040C) Host Global Interrupt Set Register */ + __I uint32_t USBHS_HSTIMR; /**< \brief (Usbhs Offset: 0x0410) Host Global Interrupt Mask Register */ + __O uint32_t USBHS_HSTIDR; /**< \brief (Usbhs Offset: 0x0414) Host Global Interrupt Disable Register */ + __O uint32_t USBHS_HSTIER; /**< \brief (Usbhs Offset: 0x0418) Host Global Interrupt Enable Register */ + __IO uint32_t USBHS_HSTPIP; /**< \brief (Usbhs Offset: 0x0041C) Host Pipe Register */ + __IO uint32_t USBHS_HSTFNUM; /**< \brief (Usbhs Offset: 0x0420) Host Frame Number Register */ + __IO uint32_t USBHS_HSTADDR1; /**< \brief (Usbhs Offset: 0x0424) Host Address 1 Register */ + __IO uint32_t USBHS_HSTADDR2; /**< \brief (Usbhs Offset: 0x0428) Host Address 2 Register */ + __IO uint32_t USBHS_HSTADDR3; /**< \brief (Usbhs Offset: 0x042C) Host Address 3 Register */ + __I uint32_t Reserved10[52]; + __IO uint32_t USBHS_HSTPIPCFG[10]; /**< \brief (Usbhs Offset: 0x500) Host Pipe Configuration Register (n = 0) */ + __I uint32_t Reserved11[2]; + __I uint32_t USBHS_HSTPIPISR[10]; /**< \brief (Usbhs Offset: 0x530) Host Pipe Status Register (n = 0) */ + __I uint32_t Reserved12[2]; + __O uint32_t USBHS_HSTPIPICR[10]; /**< \brief (Usbhs Offset: 0x560) Host Pipe Clear Register (n = 0) */ + __I uint32_t Reserved13[2]; + __O uint32_t USBHS_HSTPIPIFR[10]; /**< \brief (Usbhs Offset: 0x590) Host Pipe Set Register (n = 0) */ + __I uint32_t Reserved14[2]; + __I uint32_t USBHS_HSTPIPIMR[10]; /**< \brief (Usbhs Offset: 0x5C0) Host Pipe Mask Register (n = 0) */ + __I uint32_t Reserved15[2]; + __O uint32_t USBHS_HSTPIPIER[10]; /**< \brief (Usbhs Offset: 0x5F0) Host Pipe Enable Register (n = 0) */ + __I uint32_t Reserved16[2]; + __O uint32_t USBHS_HSTPIPIDR[10]; /**< \brief (Usbhs Offset: 0x620) Host Pipe Disable Register (n = 0) */ + __I uint32_t Reserved17[2]; + __IO uint32_t USBHS_HSTPIPINRQ[10]; /**< \brief (Usbhs Offset: 0x650) Host Pipe IN Request Register (n = 0) */ + __I uint32_t Reserved18[2]; + __IO uint32_t USBHS_HSTPIPERR[10]; /**< \brief (Usbhs Offset: 0x680) Host Pipe Error Register (n = 0) */ + __I uint32_t Reserved19[26]; + UsbhsHstdma USBHS_HSTDMA[USBHSHSTDMA_NUMBER]; /**< \brief (Usbhs Offset: 0x710) n = 1 .. 7 */ + __I uint32_t Reserved20[32]; + __IO uint32_t USBHS_CTRL; /**< \brief (Usbhs Offset: 0x0800) General Control Register */ + __I uint32_t USBHS_SR; /**< \brief (Usbhs Offset: 0x0804) General Status Register */ + __O uint32_t USBHS_SCR; /**< \brief (Usbhs Offset: 0x0808) General Status Clear Register */ + __O uint32_t USBHS_SFR; /**< \brief (Usbhs Offset: 0x080C) General Status Set Register */ + __IO uint32_t USBHS_TSTA1; /**< \brief (Usbhs Offset: 0x0810) General Test A1 Register */ + __IO uint32_t USBHS_TSTA2; /**< \brief (Usbhs Offset: 0x0814) General Test A2 Register */ + __I uint32_t USBHS_VERSION; /**< \brief (Usbhs Offset: 0x0818) General Version Register */ + __I uint32_t Reserved21[4]; + __I uint32_t USBHS_FSM; /**< \brief (Usbhs Offset: 0x082C) General Finite State Machine Register */ +} Usbhs; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- USBHS_DEVCTRL : (USBHS Offset: 0x0000) Device General Control Register -------- */ +#define USBHS_DEVCTRL_UADD_Pos 0 +#define USBHS_DEVCTRL_UADD_Msk (0x7fu << USBHS_DEVCTRL_UADD_Pos) /**< \brief (USBHS_DEVCTRL) USB Address */ +#define USBHS_DEVCTRL_UADD(value) ((USBHS_DEVCTRL_UADD_Msk & ((value) << USBHS_DEVCTRL_UADD_Pos))) +#define USBHS_DEVCTRL_ADDEN (0x1u << 7) /**< \brief (USBHS_DEVCTRL) Address Enable */ +#define USBHS_DEVCTRL_DETACH (0x1u << 8) /**< \brief (USBHS_DEVCTRL) Detach */ +#define USBHS_DEVCTRL_RMWKUP (0x1u << 9) /**< \brief (USBHS_DEVCTRL) Remote Wake-Up */ +#define USBHS_DEVCTRL_SPDCONF_Pos 10 +#define USBHS_DEVCTRL_SPDCONF_Msk (0x3u << USBHS_DEVCTRL_SPDCONF_Pos) /**< \brief (USBHS_DEVCTRL) Mode Configuration */ +#define USBHS_DEVCTRL_SPDCONF(value) ((USBHS_DEVCTRL_SPDCONF_Msk & ((value) << USBHS_DEVCTRL_SPDCONF_Pos))) +#define USBHS_DEVCTRL_SPDCONF_NORMAL (0x0u << 10) /**< \brief (USBHS_DEVCTRL) The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable. */ +#define USBHS_DEVCTRL_SPDCONF_LOW_POWER (0x1u << 10) /**< \brief (USBHS_DEVCTRL) For a better consumption, if high speed is not needed. */ +#define USBHS_DEVCTRL_SPDCONF_HIGH_SPEED (0x2u << 10) /**< \brief (USBHS_DEVCTRL) Forced high speed. */ +#define USBHS_DEVCTRL_SPDCONF_FORCED_FS (0x3u << 10) /**< \brief (USBHS_DEVCTRL) The peripheral remains in Full-speed mode whatever the host speed capability. */ +#define USBHS_DEVCTRL_LS (0x1u << 12) /**< \brief (USBHS_DEVCTRL) Low-Speed Mode Force */ +#define USBHS_DEVCTRL_TSTJ (0x1u << 13) /**< \brief (USBHS_DEVCTRL) Test mode J */ +#define USBHS_DEVCTRL_TSTK (0x1u << 14) /**< \brief (USBHS_DEVCTRL) Test mode K */ +#define USBHS_DEVCTRL_TSTPCKT (0x1u << 15) /**< \brief (USBHS_DEVCTRL) Test packet mode */ +#define USBHS_DEVCTRL_OPMODE2 (0x1u << 16) /**< \brief (USBHS_DEVCTRL) Specific Operational mode */ +/* -------- USBHS_DEVISR : (USBHS Offset: 0x0004) Device Global Interrupt Status Register -------- */ +#define USBHS_DEVISR_SUSP (0x1u << 0) /**< \brief (USBHS_DEVISR) Suspend Interrupt */ +#define USBHS_DEVISR_MSOF (0x1u << 1) /**< \brief (USBHS_DEVISR) Micro Start of Frame Interrupt */ +#define USBHS_DEVISR_SOF (0x1u << 2) /**< \brief (USBHS_DEVISR) Start of Frame Interrupt */ +#define USBHS_DEVISR_EORST (0x1u << 3) /**< \brief (USBHS_DEVISR) End of Reset Interrupt */ +#define USBHS_DEVISR_WAKEUP (0x1u << 4) /**< \brief (USBHS_DEVISR) Wake-Up Interrupt */ +#define USBHS_DEVISR_EORSM (0x1u << 5) /**< \brief (USBHS_DEVISR) End of Resume Interrupt */ +#define USBHS_DEVISR_UPRSM (0x1u << 6) /**< \brief (USBHS_DEVISR) Upstream Resume Interrupt */ +#define USBHS_DEVISR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVISR) Endpoint 0 Interrupt */ +#define USBHS_DEVISR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVISR) Endpoint 1 Interrupt */ +#define USBHS_DEVISR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVISR) Endpoint 2 Interrupt */ +#define USBHS_DEVISR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVISR) Endpoint 3 Interrupt */ +#define USBHS_DEVISR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVISR) Endpoint 4 Interrupt */ +#define USBHS_DEVISR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVISR) Endpoint 5 Interrupt */ +#define USBHS_DEVISR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVISR) Endpoint 6 Interrupt */ +#define USBHS_DEVISR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVISR) Endpoint 7 Interrupt */ +#define USBHS_DEVISR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVISR) Endpoint 8 Interrupt */ +#define USBHS_DEVISR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVISR) Endpoint 9 Interrupt */ +#define USBHS_DEVISR_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVISR) Endpoint 10 Interrupt */ +#define USBHS_DEVISR_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVISR) Endpoint 11 Interrupt */ +#define USBHS_DEVISR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVISR) DMA Channel 1 Interrupt */ +#define USBHS_DEVISR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVISR) DMA Channel 2 Interrupt */ +#define USBHS_DEVISR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVISR) DMA Channel 3 Interrupt */ +#define USBHS_DEVISR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVISR) DMA Channel 4 Interrupt */ +#define USBHS_DEVISR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVISR) DMA Channel 5 Interrupt */ +#define USBHS_DEVISR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVISR) DMA Channel 6 Interrupt */ +#define USBHS_DEVISR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVISR) DMA Channel 7 Interrupt */ +/* -------- USBHS_DEVICR : (USBHS Offset: 0x0008) Device Global Interrupt Clear Register -------- */ +#define USBHS_DEVICR_SUSPC (0x1u << 0) /**< \brief (USBHS_DEVICR) Suspend Interrupt Clear */ +#define USBHS_DEVICR_MSOFC (0x1u << 1) /**< \brief (USBHS_DEVICR) Micro Start of Frame Interrupt Clear */ +#define USBHS_DEVICR_SOFC (0x1u << 2) /**< \brief (USBHS_DEVICR) Start of Frame Interrupt Clear */ +#define USBHS_DEVICR_EORSTC (0x1u << 3) /**< \brief (USBHS_DEVICR) End of Reset Interrupt Clear */ +#define USBHS_DEVICR_WAKEUPC (0x1u << 4) /**< \brief (USBHS_DEVICR) Wake-Up Interrupt Clear */ +#define USBHS_DEVICR_EORSMC (0x1u << 5) /**< \brief (USBHS_DEVICR) End of Resume Interrupt Clear */ +#define USBHS_DEVICR_UPRSMC (0x1u << 6) /**< \brief (USBHS_DEVICR) Upstream Resume Interrupt Clear */ +/* -------- USBHS_DEVIFR : (USBHS Offset: 0x000C) Device Global Interrupt Set Register -------- */ +#define USBHS_DEVIFR_SUSPS (0x1u << 0) /**< \brief (USBHS_DEVIFR) Suspend Interrupt Set */ +#define USBHS_DEVIFR_MSOFS (0x1u << 1) /**< \brief (USBHS_DEVIFR) Micro Start of Frame Interrupt Set */ +#define USBHS_DEVIFR_SOFS (0x1u << 2) /**< \brief (USBHS_DEVIFR) Start of Frame Interrupt Set */ +#define USBHS_DEVIFR_EORSTS (0x1u << 3) /**< \brief (USBHS_DEVIFR) End of Reset Interrupt Set */ +#define USBHS_DEVIFR_WAKEUPS (0x1u << 4) /**< \brief (USBHS_DEVIFR) Wake-Up Interrupt Set */ +#define USBHS_DEVIFR_EORSMS (0x1u << 5) /**< \brief (USBHS_DEVIFR) End of Resume Interrupt Set */ +#define USBHS_DEVIFR_UPRSMS (0x1u << 6) /**< \brief (USBHS_DEVIFR) Upstream Resume Interrupt Set */ +#define USBHS_DEVIFR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIFR) DMA Channel 1 Interrupt Set */ +#define USBHS_DEVIFR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIFR) DMA Channel 2 Interrupt Set */ +#define USBHS_DEVIFR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIFR) DMA Channel 3 Interrupt Set */ +#define USBHS_DEVIFR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIFR) DMA Channel 4 Interrupt Set */ +#define USBHS_DEVIFR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIFR) DMA Channel 5 Interrupt Set */ +#define USBHS_DEVIFR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIFR) DMA Channel 6 Interrupt Set */ +#define USBHS_DEVIFR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIFR) DMA Channel 7 Interrupt Set */ +/* -------- USBHS_DEVIMR : (USBHS Offset: 0x0010) Device Global Interrupt Mask Register -------- */ +#define USBHS_DEVIMR_SUSPE (0x1u << 0) /**< \brief (USBHS_DEVIMR) Suspend Interrupt Mask */ +#define USBHS_DEVIMR_MSOFE (0x1u << 1) /**< \brief (USBHS_DEVIMR) Micro Start of Frame Interrupt Mask */ +#define USBHS_DEVIMR_SOFE (0x1u << 2) /**< \brief (USBHS_DEVIMR) Start of Frame Interrupt Mask */ +#define USBHS_DEVIMR_EORSTE (0x1u << 3) /**< \brief (USBHS_DEVIMR) End of Reset Interrupt Mask */ +#define USBHS_DEVIMR_WAKEUPE (0x1u << 4) /**< \brief (USBHS_DEVIMR) Wake-Up Interrupt Mask */ +#define USBHS_DEVIMR_EORSME (0x1u << 5) /**< \brief (USBHS_DEVIMR) End of Resume Interrupt Mask */ +#define USBHS_DEVIMR_UPRSME (0x1u << 6) /**< \brief (USBHS_DEVIMR) Upstream Resume Interrupt Mask */ +#define USBHS_DEVIMR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIMR) Endpoint 0 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIMR) Endpoint 1 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIMR) Endpoint 2 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIMR) Endpoint 3 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIMR) Endpoint 4 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIMR) Endpoint 5 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIMR) Endpoint 6 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIMR) Endpoint 7 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIMR) Endpoint 8 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIMR) Endpoint 9 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVIMR) Endpoint 10 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVIMR) Endpoint 11 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIMR) DMA Channel 1 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIMR) DMA Channel 2 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIMR) DMA Channel 3 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIMR) DMA Channel 4 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIMR) DMA Channel 5 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIMR) DMA Channel 6 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIMR) DMA Channel 7 Interrupt Mask */ +/* -------- USBHS_DEVIDR : (USBHS Offset: 0x0014) Device Global Interrupt Disable Register -------- */ +#define USBHS_DEVIDR_SUSPEC (0x1u << 0) /**< \brief (USBHS_DEVIDR) Suspend Interrupt Disable */ +#define USBHS_DEVIDR_MSOFEC (0x1u << 1) /**< \brief (USBHS_DEVIDR) Micro Start of Frame Interrupt Disable */ +#define USBHS_DEVIDR_SOFEC (0x1u << 2) /**< \brief (USBHS_DEVIDR) Start of Frame Interrupt Disable */ +#define USBHS_DEVIDR_EORSTEC (0x1u << 3) /**< \brief (USBHS_DEVIDR) End of Reset Interrupt Disable */ +#define USBHS_DEVIDR_WAKEUPEC (0x1u << 4) /**< \brief (USBHS_DEVIDR) Wake-Up Interrupt Disable */ +#define USBHS_DEVIDR_EORSMEC (0x1u << 5) /**< \brief (USBHS_DEVIDR) End of Resume Interrupt Disable */ +#define USBHS_DEVIDR_UPRSMEC (0x1u << 6) /**< \brief (USBHS_DEVIDR) Upstream Resume Interrupt Disable */ +#define USBHS_DEVIDR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIDR) Endpoint 0 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIDR) Endpoint 1 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIDR) Endpoint 2 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIDR) Endpoint 3 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIDR) Endpoint 4 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIDR) Endpoint 5 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIDR) Endpoint 6 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIDR) Endpoint 7 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIDR) Endpoint 8 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIDR) Endpoint 9 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVIDR) Endpoint 10 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVIDR) Endpoint 11 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIDR) DMA Channel 1 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIDR) DMA Channel 2 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIDR) DMA Channel 3 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIDR) DMA Channel 4 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIDR) DMA Channel 5 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIDR) DMA Channel 6 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIDR) DMA Channel 7 Interrupt Disable */ +/* -------- USBHS_DEVIER : (USBHS Offset: 0x0018) Device Global Interrupt Enable Register -------- */ +#define USBHS_DEVIER_SUSPES (0x1u << 0) /**< \brief (USBHS_DEVIER) Suspend Interrupt Enable */ +#define USBHS_DEVIER_MSOFES (0x1u << 1) /**< \brief (USBHS_DEVIER) Micro Start of Frame Interrupt Enable */ +#define USBHS_DEVIER_SOFES (0x1u << 2) /**< \brief (USBHS_DEVIER) Start of Frame Interrupt Enable */ +#define USBHS_DEVIER_EORSTES (0x1u << 3) /**< \brief (USBHS_DEVIER) End of Reset Interrupt Enable */ +#define USBHS_DEVIER_WAKEUPES (0x1u << 4) /**< \brief (USBHS_DEVIER) Wake-Up Interrupt Enable */ +#define USBHS_DEVIER_EORSMES (0x1u << 5) /**< \brief (USBHS_DEVIER) End of Resume Interrupt Enable */ +#define USBHS_DEVIER_UPRSMES (0x1u << 6) /**< \brief (USBHS_DEVIER) Upstream Resume Interrupt Enable */ +#define USBHS_DEVIER_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIER) Endpoint 0 Interrupt Enable */ +#define USBHS_DEVIER_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIER) Endpoint 1 Interrupt Enable */ +#define USBHS_DEVIER_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIER) Endpoint 2 Interrupt Enable */ +#define USBHS_DEVIER_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIER) Endpoint 3 Interrupt Enable */ +#define USBHS_DEVIER_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIER) Endpoint 4 Interrupt Enable */ +#define USBHS_DEVIER_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIER) Endpoint 5 Interrupt Enable */ +#define USBHS_DEVIER_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIER) Endpoint 6 Interrupt Enable */ +#define USBHS_DEVIER_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIER) Endpoint 7 Interrupt Enable */ +#define USBHS_DEVIER_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIER) Endpoint 8 Interrupt Enable */ +#define USBHS_DEVIER_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIER) Endpoint 9 Interrupt Enable */ +#define USBHS_DEVIER_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVIER) Endpoint 10 Interrupt Enable */ +#define USBHS_DEVIER_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVIER) Endpoint 11 Interrupt Enable */ +#define USBHS_DEVIER_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIER) DMA Channel 1 Interrupt Enable */ +#define USBHS_DEVIER_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIER) DMA Channel 2 Interrupt Enable */ +#define USBHS_DEVIER_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIER) DMA Channel 3 Interrupt Enable */ +#define USBHS_DEVIER_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIER) DMA Channel 4 Interrupt Enable */ +#define USBHS_DEVIER_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIER) DMA Channel 5 Interrupt Enable */ +#define USBHS_DEVIER_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIER) DMA Channel 6 Interrupt Enable */ +#define USBHS_DEVIER_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIER) DMA Channel 7 Interrupt Enable */ +/* -------- USBHS_DEVEPT : (USBHS Offset: 0x001C) Device Endpoint Register -------- */ +#define USBHS_DEVEPT_EPEN0 (0x1u << 0) /**< \brief (USBHS_DEVEPT) Endpoint 0 Enable */ +#define USBHS_DEVEPT_EPEN1 (0x1u << 1) /**< \brief (USBHS_DEVEPT) Endpoint 1 Enable */ +#define USBHS_DEVEPT_EPEN2 (0x1u << 2) /**< \brief (USBHS_DEVEPT) Endpoint 2 Enable */ +#define USBHS_DEVEPT_EPEN3 (0x1u << 3) /**< \brief (USBHS_DEVEPT) Endpoint 3 Enable */ +#define USBHS_DEVEPT_EPEN4 (0x1u << 4) /**< \brief (USBHS_DEVEPT) Endpoint 4 Enable */ +#define USBHS_DEVEPT_EPEN5 (0x1u << 5) /**< \brief (USBHS_DEVEPT) Endpoint 5 Enable */ +#define USBHS_DEVEPT_EPEN6 (0x1u << 6) /**< \brief (USBHS_DEVEPT) Endpoint 6 Enable */ +#define USBHS_DEVEPT_EPEN7 (0x1u << 7) /**< \brief (USBHS_DEVEPT) Endpoint 7 Enable */ +#define USBHS_DEVEPT_EPEN8 (0x1u << 8) /**< \brief (USBHS_DEVEPT) Endpoint 8 Enable */ +#define USBHS_DEVEPT_EPRST0 (0x1u << 16) /**< \brief (USBHS_DEVEPT) Endpoint 0 Reset */ +#define USBHS_DEVEPT_EPRST1 (0x1u << 17) /**< \brief (USBHS_DEVEPT) Endpoint 1 Reset */ +#define USBHS_DEVEPT_EPRST2 (0x1u << 18) /**< \brief (USBHS_DEVEPT) Endpoint 2 Reset */ +#define USBHS_DEVEPT_EPRST3 (0x1u << 19) /**< \brief (USBHS_DEVEPT) Endpoint 3 Reset */ +#define USBHS_DEVEPT_EPRST4 (0x1u << 20) /**< \brief (USBHS_DEVEPT) Endpoint 4 Reset */ +#define USBHS_DEVEPT_EPRST5 (0x1u << 21) /**< \brief (USBHS_DEVEPT) Endpoint 5 Reset */ +#define USBHS_DEVEPT_EPRST6 (0x1u << 22) /**< \brief (USBHS_DEVEPT) Endpoint 6 Reset */ +#define USBHS_DEVEPT_EPRST7 (0x1u << 23) /**< \brief (USBHS_DEVEPT) Endpoint 7 Reset */ +#define USBHS_DEVEPT_EPRST8 (0x1u << 24) /**< \brief (USBHS_DEVEPT) Endpoint 8 Reset */ +/* -------- USBHS_DEVFNUM : (USBHS Offset: 0x0020) Device Frame Number Register -------- */ +#define USBHS_DEVFNUM_MFNUM_Pos 0 +#define USBHS_DEVFNUM_MFNUM_Msk (0x7u << USBHS_DEVFNUM_MFNUM_Pos) /**< \brief (USBHS_DEVFNUM) Micro Frame Number */ +#define USBHS_DEVFNUM_FNUM_Pos 3 +#define USBHS_DEVFNUM_FNUM_Msk (0x7ffu << USBHS_DEVFNUM_FNUM_Pos) /**< \brief (USBHS_DEVFNUM) Frame Number */ +#define USBHS_DEVFNUM_FNCERR (0x1u << 15) /**< \brief (USBHS_DEVFNUM) Frame Number CRC Error */ +/* -------- USBHS_DEVEPTCFG[10] : (USBHS Offset: 0x100) Device Endpoint Configuration Register (n = 0) -------- */ +#define USBHS_DEVEPTCFG_ALLOC (0x1u << 1) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Memory Allocate */ +#define USBHS_DEVEPTCFG_EPBK_Pos 2 +#define USBHS_DEVEPTCFG_EPBK_Msk (0x3u << USBHS_DEVEPTCFG_EPBK_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Banks */ +#define USBHS_DEVEPTCFG_EPBK(value) ((USBHS_DEVEPTCFG_EPBK_Msk & ((value) << USBHS_DEVEPTCFG_EPBK_Pos))) +#define USBHS_DEVEPTCFG_EPBK_1_BANK (0x0u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Single-bank endpoint */ +#define USBHS_DEVEPTCFG_EPBK_2_BANK (0x1u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Double-bank endpoint */ +#define USBHS_DEVEPTCFG_EPBK_3_BANK (0x2u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Triple-bank endpoint */ +#define USBHS_DEVEPTCFG_EPSIZE_Pos 4 +#define USBHS_DEVEPTCFG_EPSIZE_Msk (0x7u << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Size */ +#define USBHS_DEVEPTCFG_EPSIZE(value) ((USBHS_DEVEPTCFG_EPSIZE_Msk & ((value) << USBHS_DEVEPTCFG_EPSIZE_Pos))) +#define USBHS_DEVEPTCFG_EPSIZE_8_BYTE (0x0u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 8 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_16_BYTE (0x1u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 16 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_32_BYTE (0x2u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 32 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_64_BYTE (0x3u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 64 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_128_BYTE (0x4u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 128 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_256_BYTE (0x5u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 256 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_512_BYTE (0x6u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 512 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_1024_BYTE (0x7u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 1024 bytes */ +#define USBHS_DEVEPTCFG_EPDIR (0x1u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Direction */ +#define USBHS_DEVEPTCFG_EPDIR_OUT (0x0u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) The endpoint direction is OUT. */ +#define USBHS_DEVEPTCFG_EPDIR_IN (0x1u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) The endpoint direction is IN (nor for control endpoints). */ +#define USBHS_DEVEPTCFG_AUTOSW (0x1u << 9) /**< \brief (USBHS_DEVEPTCFG[10]) Automatic Switch */ +#define USBHS_DEVEPTCFG_EPTYPE_Pos 11 +#define USBHS_DEVEPTCFG_EPTYPE_Msk (0x3u << USBHS_DEVEPTCFG_EPTYPE_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Type */ +#define USBHS_DEVEPTCFG_EPTYPE(value) ((USBHS_DEVEPTCFG_EPTYPE_Msk & ((value) << USBHS_DEVEPTCFG_EPTYPE_Pos))) +#define USBHS_DEVEPTCFG_EPTYPE_CTRL (0x0u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Control */ +#define USBHS_DEVEPTCFG_EPTYPE_ISO (0x1u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Isochronous */ +#define USBHS_DEVEPTCFG_EPTYPE_BLK (0x2u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Bulk */ +#define USBHS_DEVEPTCFG_EPTYPE_INTRPT (0x3u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Interrupt */ +#define USBHS_DEVEPTCFG_NBTRANS_Pos 13 +#define USBHS_DEVEPTCFG_NBTRANS_Msk (0x3u << USBHS_DEVEPTCFG_NBTRANS_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Number of transactions per microframe for isochronous endpoint */ +#define USBHS_DEVEPTCFG_NBTRANS(value) ((USBHS_DEVEPTCFG_NBTRANS_Msk & ((value) << USBHS_DEVEPTCFG_NBTRANS_Pos))) +#define USBHS_DEVEPTCFG_NBTRANS_0_TRANS (0x0u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Reserved to endpoint that does not have the high-bandwidth isochronous capability. */ +#define USBHS_DEVEPTCFG_NBTRANS_1_TRANS (0x1u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Default value: one transaction per microframe. */ +#define USBHS_DEVEPTCFG_NBTRANS_2_TRANS (0x2u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Two transactions per microframe. This endpoint should be configured as double-bank. */ +#define USBHS_DEVEPTCFG_NBTRANS_3_TRANS (0x3u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Three transactions per microframe. This endpoint should be configured as triple-bank. */ +/* -------- USBHS_DEVEPTISR[10] : (USBHS Offset: 0x130) Device Endpoint Status Register (n = 0) -------- */ +#define USBHS_DEVEPTISR_TXINI (0x1u << 0) /**< \brief (USBHS_DEVEPTISR[10]) Transmitted IN Data Interrupt */ +#define USBHS_DEVEPTISR_RXOUTI (0x1u << 1) /**< \brief (USBHS_DEVEPTISR[10]) Received OUT Data Interrupt */ +#define USBHS_DEVEPTISR_RXSTPI (0x1u << 2) /**< \brief (USBHS_DEVEPTISR[10]) Received SETUP Interrupt */ +#define USBHS_DEVEPTISR_NAKOUTI (0x1u << 3) /**< \brief (USBHS_DEVEPTISR[10]) NAKed OUT Interrupt */ +#define USBHS_DEVEPTISR_NAKINI (0x1u << 4) /**< \brief (USBHS_DEVEPTISR[10]) NAKed IN Interrupt */ +#define USBHS_DEVEPTISR_OVERFI (0x1u << 5) /**< \brief (USBHS_DEVEPTISR[10]) Overflow Interrupt */ +#define USBHS_DEVEPTISR_STALLEDI (0x1u << 6) /**< \brief (USBHS_DEVEPTISR[10]) STALLed Interrupt */ +#define USBHS_DEVEPTISR_SHORTPACKET (0x1u << 7) /**< \brief (USBHS_DEVEPTISR[10]) Short Packet Interrupt */ +#define USBHS_DEVEPTISR_DTSEQ_Pos 8 +#define USBHS_DEVEPTISR_DTSEQ_Msk (0x3u << USBHS_DEVEPTISR_DTSEQ_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Data Toggle Sequence */ +#define USBHS_DEVEPTISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Data0 toggle sequence */ +#define USBHS_DEVEPTISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Data1 toggle sequence */ +#define USBHS_DEVEPTISR_DTSEQ_DATA2 (0x2u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Reserved for high-bandwidth isochronous endpoint */ +#define USBHS_DEVEPTISR_DTSEQ_MDATA (0x3u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Reserved for high-bandwidth isochronous endpoint */ +#define USBHS_DEVEPTISR_NBUSYBK_Pos 12 +#define USBHS_DEVEPTISR_NBUSYBK_Msk (0x3u << USBHS_DEVEPTISR_NBUSYBK_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Number of Busy Banks */ +#define USBHS_DEVEPTISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 0 busy bank (all banks free) */ +#define USBHS_DEVEPTISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 1 busy bank */ +#define USBHS_DEVEPTISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 2 busy banks */ +#define USBHS_DEVEPTISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 3 busy banks */ +#define USBHS_DEVEPTISR_CURRBK_Pos 14 +#define USBHS_DEVEPTISR_CURRBK_Msk (0x3u << USBHS_DEVEPTISR_CURRBK_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Current Bank */ +#define USBHS_DEVEPTISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank0 */ +#define USBHS_DEVEPTISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank1 */ +#define USBHS_DEVEPTISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank2 */ +#define USBHS_DEVEPTISR_RWALL (0x1u << 16) /**< \brief (USBHS_DEVEPTISR[10]) Read/Write Allowed */ +#define USBHS_DEVEPTISR_CTRLDIR (0x1u << 17) /**< \brief (USBHS_DEVEPTISR[10]) Control Direction */ +#define USBHS_DEVEPTISR_CFGOK (0x1u << 18) /**< \brief (USBHS_DEVEPTISR[10]) Configuration OK Status */ +#define USBHS_DEVEPTISR_BYCT_Pos 20 +#define USBHS_DEVEPTISR_BYCT_Msk (0x7ffu << USBHS_DEVEPTISR_BYCT_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Byte Count */ +#define USBHS_DEVEPTISR_UNDERFI (0x1u << 2) /**< \brief (USBHS_DEVEPTISR[10]) Underflow Interrupt */ +#define USBHS_DEVEPTISR_HBISOINERRI (0x1u << 3) /**< \brief (USBHS_DEVEPTISR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt */ +#define USBHS_DEVEPTISR_HBISOFLUSHI (0x1u << 4) /**< \brief (USBHS_DEVEPTISR[10]) High Bandwidth Isochronous IN Flush Interrupt */ +#define USBHS_DEVEPTISR_CRCERRI (0x1u << 6) /**< \brief (USBHS_DEVEPTISR[10]) CRC Error Interrupt */ +#define USBHS_DEVEPTISR_ERRORTRANS (0x1u << 10) /**< \brief (USBHS_DEVEPTISR[10]) High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt */ +/* -------- USBHS_DEVEPTICR[10] : (USBHS Offset: 0x160) Device Endpoint Clear Register (n = 0) -------- */ +#define USBHS_DEVEPTICR_TXINIC (0x1u << 0) /**< \brief (USBHS_DEVEPTICR[10]) Transmitted IN Data Interrupt Clear */ +#define USBHS_DEVEPTICR_RXOUTIC (0x1u << 1) /**< \brief (USBHS_DEVEPTICR[10]) Received OUT Data Interrupt Clear */ +#define USBHS_DEVEPTICR_RXSTPIC (0x1u << 2) /**< \brief (USBHS_DEVEPTICR[10]) Received SETUP Interrupt Clear */ +#define USBHS_DEVEPTICR_NAKOUTIC (0x1u << 3) /**< \brief (USBHS_DEVEPTICR[10]) NAKed OUT Interrupt Clear */ +#define USBHS_DEVEPTICR_NAKINIC (0x1u << 4) /**< \brief (USBHS_DEVEPTICR[10]) NAKed IN Interrupt Clear */ +#define USBHS_DEVEPTICR_OVERFIC (0x1u << 5) /**< \brief (USBHS_DEVEPTICR[10]) Overflow Interrupt Clear */ +#define USBHS_DEVEPTICR_STALLEDIC (0x1u << 6) /**< \brief (USBHS_DEVEPTICR[10]) STALLed Interrupt Clear */ +#define USBHS_DEVEPTICR_SHORTPACKETC (0x1u << 7) /**< \brief (USBHS_DEVEPTICR[10]) Short Packet Interrupt Clear */ +#define USBHS_DEVEPTICR_UNDERFIC (0x1u << 2) /**< \brief (USBHS_DEVEPTICR[10]) Underflow Interrupt Clear */ +#define USBHS_DEVEPTICR_HBISOINERRIC (0x1u << 3) /**< \brief (USBHS_DEVEPTICR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt Clear */ +#define USBHS_DEVEPTICR_HBISOFLUSHIC (0x1u << 4) /**< \brief (USBHS_DEVEPTICR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear */ +#define USBHS_DEVEPTICR_CRCERRIC (0x1u << 6) /**< \brief (USBHS_DEVEPTICR[10]) CRC Error Interrupt Clear */ +/* -------- USBHS_DEVEPTIFR[10] : (USBHS Offset: 0x190) Device Endpoint Set Register (n = 0) -------- */ +#define USBHS_DEVEPTIFR_TXINIS (0x1u << 0) /**< \brief (USBHS_DEVEPTIFR[10]) Transmitted IN Data Interrupt Set */ +#define USBHS_DEVEPTIFR_RXOUTIS (0x1u << 1) /**< \brief (USBHS_DEVEPTIFR[10]) Received OUT Data Interrupt Set */ +#define USBHS_DEVEPTIFR_RXSTPIS (0x1u << 2) /**< \brief (USBHS_DEVEPTIFR[10]) Received SETUP Interrupt Set */ +#define USBHS_DEVEPTIFR_NAKOUTIS (0x1u << 3) /**< \brief (USBHS_DEVEPTIFR[10]) NAKed OUT Interrupt Set */ +#define USBHS_DEVEPTIFR_NAKINIS (0x1u << 4) /**< \brief (USBHS_DEVEPTIFR[10]) NAKed IN Interrupt Set */ +#define USBHS_DEVEPTIFR_OVERFIS (0x1u << 5) /**< \brief (USBHS_DEVEPTIFR[10]) Overflow Interrupt Set */ +#define USBHS_DEVEPTIFR_STALLEDIS (0x1u << 6) /**< \brief (USBHS_DEVEPTIFR[10]) STALLed Interrupt Set */ +#define USBHS_DEVEPTIFR_SHORTPACKETS (0x1u << 7) /**< \brief (USBHS_DEVEPTIFR[10]) Short Packet Interrupt Set */ +#define USBHS_DEVEPTIFR_NBUSYBKS (0x1u << 12) /**< \brief (USBHS_DEVEPTIFR[10]) Number of Busy Banks Interrupt Set */ +#define USBHS_DEVEPTIFR_UNDERFIS (0x1u << 2) /**< \brief (USBHS_DEVEPTIFR[10]) Underflow Interrupt Set */ +#define USBHS_DEVEPTIFR_HBISOINERRIS (0x1u << 3) /**< \brief (USBHS_DEVEPTIFR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt Set */ +#define USBHS_DEVEPTIFR_HBISOFLUSHIS (0x1u << 4) /**< \brief (USBHS_DEVEPTIFR[10]) High Bandwidth Isochronous IN Flush Interrupt Set */ +#define USBHS_DEVEPTIFR_CRCERRIS (0x1u << 6) /**< \brief (USBHS_DEVEPTIFR[10]) CRC Error Interrupt Set */ +/* -------- USBHS_DEVEPTIMR[10] : (USBHS Offset: 0x1C0) Device Endpoint Mask Register (n = 0) -------- */ +#define USBHS_DEVEPTIMR_TXINE (0x1u << 0) /**< \brief (USBHS_DEVEPTIMR[10]) Transmitted IN Data Interrupt */ +#define USBHS_DEVEPTIMR_RXOUTE (0x1u << 1) /**< \brief (USBHS_DEVEPTIMR[10]) Received OUT Data Interrupt */ +#define USBHS_DEVEPTIMR_RXSTPE (0x1u << 2) /**< \brief (USBHS_DEVEPTIMR[10]) Received SETUP Interrupt */ +#define USBHS_DEVEPTIMR_NAKOUTE (0x1u << 3) /**< \brief (USBHS_DEVEPTIMR[10]) NAKed OUT Interrupt */ +#define USBHS_DEVEPTIMR_NAKINE (0x1u << 4) /**< \brief (USBHS_DEVEPTIMR[10]) NAKed IN Interrupt */ +#define USBHS_DEVEPTIMR_OVERFE (0x1u << 5) /**< \brief (USBHS_DEVEPTIMR[10]) Overflow Interrupt */ +#define USBHS_DEVEPTIMR_STALLEDE (0x1u << 6) /**< \brief (USBHS_DEVEPTIMR[10]) STALLed Interrupt */ +#define USBHS_DEVEPTIMR_SHORTPACKETE (0x1u << 7) /**< \brief (USBHS_DEVEPTIMR[10]) Short Packet Interrupt */ +#define USBHS_DEVEPTIMR_NBUSYBKE (0x1u << 12) /**< \brief (USBHS_DEVEPTIMR[10]) Number of Busy Banks Interrupt */ +#define USBHS_DEVEPTIMR_KILLBK (0x1u << 13) /**< \brief (USBHS_DEVEPTIMR[10]) Kill IN Bank */ +#define USBHS_DEVEPTIMR_FIFOCON (0x1u << 14) /**< \brief (USBHS_DEVEPTIMR[10]) FIFO Control */ +#define USBHS_DEVEPTIMR_EPDISHDMA (0x1u << 16) /**< \brief (USBHS_DEVEPTIMR[10]) Endpoint Interrupts Disable HDMA Request */ +#define USBHS_DEVEPTIMR_NYETDIS (0x1u << 17) /**< \brief (USBHS_DEVEPTIMR[10]) NYET Token Disable */ +#define USBHS_DEVEPTIMR_RSTDT (0x1u << 18) /**< \brief (USBHS_DEVEPTIMR[10]) Reset Data Toggle */ +#define USBHS_DEVEPTIMR_STALLRQ (0x1u << 19) /**< \brief (USBHS_DEVEPTIMR[10]) STALL Request */ +#define USBHS_DEVEPTIMR_UNDERFE (0x1u << 2) /**< \brief (USBHS_DEVEPTIMR[10]) Underflow Interrupt */ +#define USBHS_DEVEPTIMR_HBISOINERRE (0x1u << 3) /**< \brief (USBHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Error Interrupt */ +#define USBHS_DEVEPTIMR_HBISOFLUSHE (0x1u << 4) /**< \brief (USBHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Flush Interrupt */ +#define USBHS_DEVEPTIMR_CRCERRE (0x1u << 6) /**< \brief (USBHS_DEVEPTIMR[10]) CRC Error Interrupt */ +#define USBHS_DEVEPTIMR_MDATAE (0x1u << 8) /**< \brief (USBHS_DEVEPTIMR[10]) MData Interrupt */ +#define USBHS_DEVEPTIMR_DATAXE (0x1u << 9) /**< \brief (USBHS_DEVEPTIMR[10]) DataX Interrupt */ +#define USBHS_DEVEPTIMR_ERRORTRANSE (0x1u << 10) /**< \brief (USBHS_DEVEPTIMR[10]) Transaction Error Interrupt */ +/* -------- USBHS_DEVEPTIER[10] : (USBHS Offset: 0x1F0) Device Endpoint Enable Register (n = 0) -------- */ +#define USBHS_DEVEPTIER_TXINES (0x1u << 0) /**< \brief (USBHS_DEVEPTIER[10]) Transmitted IN Data Interrupt Enable */ +#define USBHS_DEVEPTIER_RXOUTES (0x1u << 1) /**< \brief (USBHS_DEVEPTIER[10]) Received OUT Data Interrupt Enable */ +#define USBHS_DEVEPTIER_RXSTPES (0x1u << 2) /**< \brief (USBHS_DEVEPTIER[10]) Received SETUP Interrupt Enable */ +#define USBHS_DEVEPTIER_NAKOUTES (0x1u << 3) /**< \brief (USBHS_DEVEPTIER[10]) NAKed OUT Interrupt Enable */ +#define USBHS_DEVEPTIER_NAKINES (0x1u << 4) /**< \brief (USBHS_DEVEPTIER[10]) NAKed IN Interrupt Enable */ +#define USBHS_DEVEPTIER_OVERFES (0x1u << 5) /**< \brief (USBHS_DEVEPTIER[10]) Overflow Interrupt Enable */ +#define USBHS_DEVEPTIER_STALLEDES (0x1u << 6) /**< \brief (USBHS_DEVEPTIER[10]) STALLed Interrupt Enable */ +#define USBHS_DEVEPTIER_SHORTPACKETES (0x1u << 7) /**< \brief (USBHS_DEVEPTIER[10]) Short Packet Interrupt Enable */ +#define USBHS_DEVEPTIER_NBUSYBKES (0x1u << 12) /**< \brief (USBHS_DEVEPTIER[10]) Number of Busy Banks Interrupt Enable */ +#define USBHS_DEVEPTIER_KILLBKS (0x1u << 13) /**< \brief (USBHS_DEVEPTIER[10]) Kill IN Bank */ +#define USBHS_DEVEPTIER_FIFOCONS (0x1u << 14) /**< \brief (USBHS_DEVEPTIER[10]) FIFO Control */ +#define USBHS_DEVEPTIER_EPDISHDMAS (0x1u << 16) /**< \brief (USBHS_DEVEPTIER[10]) Endpoint Interrupts Disable HDMA Request Enable */ +#define USBHS_DEVEPTIER_NYETDISS (0x1u << 17) /**< \brief (USBHS_DEVEPTIER[10]) NYET Token Disable Enable */ +#define USBHS_DEVEPTIER_RSTDTS (0x1u << 18) /**< \brief (USBHS_DEVEPTIER[10]) Reset Data Toggle Enable */ +#define USBHS_DEVEPTIER_STALLRQS (0x1u << 19) /**< \brief (USBHS_DEVEPTIER[10]) STALL Request Enable */ +#define USBHS_DEVEPTIER_UNDERFES (0x1u << 2) /**< \brief (USBHS_DEVEPTIER[10]) Underflow Interrupt Enable */ +#define USBHS_DEVEPTIER_HBISOINERRES (0x1u << 3) /**< \brief (USBHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Error Interrupt Enable */ +#define USBHS_DEVEPTIER_HBISOFLUSHES (0x1u << 4) /**< \brief (USBHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Flush Interrupt Enable */ +#define USBHS_DEVEPTIER_CRCERRES (0x1u << 6) /**< \brief (USBHS_DEVEPTIER[10]) CRC Error Interrupt Enable */ +#define USBHS_DEVEPTIER_MDATAES (0x1u << 8) /**< \brief (USBHS_DEVEPTIER[10]) MData Interrupt Enable */ +#define USBHS_DEVEPTIER_DATAXES (0x1u << 9) /**< \brief (USBHS_DEVEPTIER[10]) DataX Interrupt Enable */ +#define USBHS_DEVEPTIER_ERRORTRANSES (0x1u << 10) /**< \brief (USBHS_DEVEPTIER[10]) Transaction Error Interrupt Enable */ +/* -------- USBHS_DEVEPTIDR[10] : (USBHS Offset: 0x220) Device Endpoint Disable Register (n = 0) -------- */ +#define USBHS_DEVEPTIDR_TXINEC (0x1u << 0) /**< \brief (USBHS_DEVEPTIDR[10]) Transmitted IN Interrupt Clear */ +#define USBHS_DEVEPTIDR_RXOUTEC (0x1u << 1) /**< \brief (USBHS_DEVEPTIDR[10]) Received OUT Data Interrupt Clear */ +#define USBHS_DEVEPTIDR_RXSTPEC (0x1u << 2) /**< \brief (USBHS_DEVEPTIDR[10]) Received SETUP Interrupt Clear */ +#define USBHS_DEVEPTIDR_NAKOUTEC (0x1u << 3) /**< \brief (USBHS_DEVEPTIDR[10]) NAKed OUT Interrupt Clear */ +#define USBHS_DEVEPTIDR_NAKINEC (0x1u << 4) /**< \brief (USBHS_DEVEPTIDR[10]) NAKed IN Interrupt Clear */ +#define USBHS_DEVEPTIDR_OVERFEC (0x1u << 5) /**< \brief (USBHS_DEVEPTIDR[10]) Overflow Interrupt Clear */ +#define USBHS_DEVEPTIDR_STALLEDEC (0x1u << 6) /**< \brief (USBHS_DEVEPTIDR[10]) STALLed Interrupt Clear */ +#define USBHS_DEVEPTIDR_SHORTPACKETEC (0x1u << 7) /**< \brief (USBHS_DEVEPTIDR[10]) Shortpacket Interrupt Clear */ +#define USBHS_DEVEPTIDR_NBUSYBKEC (0x1u << 12) /**< \brief (USBHS_DEVEPTIDR[10]) Number of Busy Banks Interrupt Clear */ +#define USBHS_DEVEPTIDR_FIFOCONC (0x1u << 14) /**< \brief (USBHS_DEVEPTIDR[10]) FIFO Control Clear */ +#define USBHS_DEVEPTIDR_EPDISHDMAC (0x1u << 16) /**< \brief (USBHS_DEVEPTIDR[10]) Endpoint Interrupts Disable HDMA Request Clear */ +#define USBHS_DEVEPTIDR_NYETDISC (0x1u << 17) /**< \brief (USBHS_DEVEPTIDR[10]) NYET Token Disable Clear */ +#define USBHS_DEVEPTIDR_STALLRQC (0x1u << 19) /**< \brief (USBHS_DEVEPTIDR[10]) STALL Request Clear */ +#define USBHS_DEVEPTIDR_UNDERFEC (0x1u << 2) /**< \brief (USBHS_DEVEPTIDR[10]) Underflow Interrupt Clear */ +#define USBHS_DEVEPTIDR_HBISOINERREC (0x1u << 3) /**< \brief (USBHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Error Interrupt Clear */ +#define USBHS_DEVEPTIDR_HBISOFLUSHEC (0x1u << 4) /**< \brief (USBHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear */ +#define USBHS_DEVEPTIDR_CRCERREC (0x1u << 6) /**< \brief (USBHS_DEVEPTIDR[10]) CRC Error Interrupt Clear */ +#define USBHS_DEVEPTIDR_MDATEC (0x1u << 8) /**< \brief (USBHS_DEVEPTIDR[10]) MData Interrupt Clear */ +#define USBHS_DEVEPTIDR_DATAXEC (0x1u << 9) /**< \brief (USBHS_DEVEPTIDR[10]) DataX Interrupt Clear */ +#define USBHS_DEVEPTIDR_ERRORTRANSEC (0x1u << 10) /**< \brief (USBHS_DEVEPTIDR[10]) Transaction Error Interrupt Clear */ +/* -------- USBHS_DEVDMANXTDSC : (USBHS Offset: N/A) Device DMA Channel Next Descriptor Address Register -------- */ +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos 0 +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (USBHS_DEVDMANXTDSC) Next Descriptor Address */ +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD(value) ((USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos))) +/* -------- USBHS_DEVDMAADDRESS : (USBHS Offset: N/A) Device DMA Channel Address Register -------- */ +#define USBHS_DEVDMAADDRESS_BUFF_ADD_Pos 0 +#define USBHS_DEVDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos) /**< \brief (USBHS_DEVDMAADDRESS) Buffer Address */ +#define USBHS_DEVDMAADDRESS_BUFF_ADD(value) ((USBHS_DEVDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos))) +/* -------- USBHS_DEVDMACONTROL : (USBHS Offset: N/A) Device DMA Channel Control Register -------- */ +#define USBHS_DEVDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_DEVDMACONTROL) Channel Enable Command */ +#define USBHS_DEVDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (USBHS_DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */ +#define USBHS_DEVDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (USBHS_DEVDMACONTROL) End of Transfer Enable Control (OUT transfers only) */ +#define USBHS_DEVDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (USBHS_DEVDMACONTROL) End of Buffer Enable Control */ +#define USBHS_DEVDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (USBHS_DEVDMACONTROL) End of Transfer Interrupt Enable */ +#define USBHS_DEVDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (USBHS_DEVDMACONTROL) End of Buffer Interrupt Enable */ +#define USBHS_DEVDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (USBHS_DEVDMACONTROL) Descriptor Loaded Interrupt Enable */ +#define USBHS_DEVDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (USBHS_DEVDMACONTROL) Burst Lock Enable */ +#define USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos 16 +#define USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk (0xffffu << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (USBHS_DEVDMACONTROL) Buffer Byte Length (Write-only) */ +#define USBHS_DEVDMACONTROL_BUFF_LENGTH(value) ((USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos))) +/* -------- USBHS_DEVDMASTATUS : (USBHS Offset: N/A) Device DMA Channel Status Register -------- */ +#define USBHS_DEVDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_DEVDMASTATUS) Channel Enable Status */ +#define USBHS_DEVDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (USBHS_DEVDMASTATUS) Channel Active Status */ +#define USBHS_DEVDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (USBHS_DEVDMASTATUS) End of Channel Transfer Status */ +#define USBHS_DEVDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (USBHS_DEVDMASTATUS) End of Channel Buffer Status */ +#define USBHS_DEVDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (USBHS_DEVDMASTATUS) Descriptor Loaded Status */ +#define USBHS_DEVDMASTATUS_BUFF_COUNT_Pos 16 +#define USBHS_DEVDMASTATUS_BUFF_COUNT_Msk (0xffffu << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos) /**< \brief (USBHS_DEVDMASTATUS) Buffer Byte Count */ +#define USBHS_DEVDMASTATUS_BUFF_COUNT(value) ((USBHS_DEVDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos))) +/* -------- USBHS_HSTCTRL : (USBHS Offset: 0x0400) Host General Control Register -------- */ +#define USBHS_HSTCTRL_SOFE (0x1u << 8) /**< \brief (USBHS_HSTCTRL) Start of Frame Generation Enable */ +#define USBHS_HSTCTRL_RESET (0x1u << 9) /**< \brief (USBHS_HSTCTRL) Send USB Reset */ +#define USBHS_HSTCTRL_RESUME (0x1u << 10) /**< \brief (USBHS_HSTCTRL) Send USB Resume */ +#define USBHS_HSTCTRL_SPDCONF_Pos 12 +#define USBHS_HSTCTRL_SPDCONF_Msk (0x3u << USBHS_HSTCTRL_SPDCONF_Pos) /**< \brief (USBHS_HSTCTRL) Mode Configuration */ +#define USBHS_HSTCTRL_SPDCONF(value) ((USBHS_HSTCTRL_SPDCONF_Msk & ((value) << USBHS_HSTCTRL_SPDCONF_Pos))) +#define USBHS_HSTCTRL_SPDCONF_NORMAL (0x0u << 12) /**< \brief (USBHS_HSTCTRL) The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable. */ +#define USBHS_HSTCTRL_SPDCONF_LOW_POWER (0x1u << 12) /**< \brief (USBHS_HSTCTRL) For a better consumption, if high speed is not needed. */ +#define USBHS_HSTCTRL_SPDCONF_HIGH_SPEED (0x2u << 12) /**< \brief (USBHS_HSTCTRL) Forced high speed. */ +#define USBHS_HSTCTRL_SPDCONF_FORCED_FS (0x3u << 12) /**< \brief (USBHS_HSTCTRL) The host remains in Full-speed mode whatever the peripheral speed capability. */ +/* -------- USBHS_HSTISR : (USBHS Offset: 0x0404) Host Global Interrupt Status Register -------- */ +#define USBHS_HSTISR_DCONNI (0x1u << 0) /**< \brief (USBHS_HSTISR) Device Connection Interrupt */ +#define USBHS_HSTISR_DDISCI (0x1u << 1) /**< \brief (USBHS_HSTISR) Device Disconnection Interrupt */ +#define USBHS_HSTISR_RSTI (0x1u << 2) /**< \brief (USBHS_HSTISR) USB Reset Sent Interrupt */ +#define USBHS_HSTISR_RSMEDI (0x1u << 3) /**< \brief (USBHS_HSTISR) Downstream Resume Sent Interrupt */ +#define USBHS_HSTISR_RXRSMI (0x1u << 4) /**< \brief (USBHS_HSTISR) Upstream Resume Received Interrupt */ +#define USBHS_HSTISR_HSOFI (0x1u << 5) /**< \brief (USBHS_HSTISR) Host Start of Frame Interrupt */ +#define USBHS_HSTISR_HWUPI (0x1u << 6) /**< \brief (USBHS_HSTISR) Host Wake-Up Interrupt */ +#define USBHS_HSTISR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTISR) Pipe 0 Interrupt */ +#define USBHS_HSTISR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTISR) Pipe 1 Interrupt */ +#define USBHS_HSTISR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTISR) Pipe 2 Interrupt */ +#define USBHS_HSTISR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTISR) Pipe 3 Interrupt */ +#define USBHS_HSTISR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTISR) Pipe 4 Interrupt */ +#define USBHS_HSTISR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTISR) Pipe 5 Interrupt */ +#define USBHS_HSTISR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTISR) Pipe 6 Interrupt */ +#define USBHS_HSTISR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTISR) Pipe 7 Interrupt */ +#define USBHS_HSTISR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTISR) Pipe 8 Interrupt */ +#define USBHS_HSTISR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTISR) Pipe 9 Interrupt */ +#define USBHS_HSTISR_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTISR) Pipe 10 Interrupt */ +#define USBHS_HSTISR_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTISR) Pipe 11 Interrupt */ +#define USBHS_HSTISR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTISR) DMA Channel 1 Interrupt */ +#define USBHS_HSTISR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTISR) DMA Channel 2 Interrupt */ +#define USBHS_HSTISR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTISR) DMA Channel 3 Interrupt */ +#define USBHS_HSTISR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTISR) DMA Channel 4 Interrupt */ +#define USBHS_HSTISR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTISR) DMA Channel 5 Interrupt */ +#define USBHS_HSTISR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTISR) DMA Channel 6 Interrupt */ +#define USBHS_HSTISR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTISR) DMA Channel 7 Interrupt */ +/* -------- USBHS_HSTICR : (USBHS Offset: 0x0408) Host Global Interrupt Clear Register -------- */ +#define USBHS_HSTICR_DCONNIC (0x1u << 0) /**< \brief (USBHS_HSTICR) Device Connection Interrupt Clear */ +#define USBHS_HSTICR_DDISCIC (0x1u << 1) /**< \brief (USBHS_HSTICR) Device Disconnection Interrupt Clear */ +#define USBHS_HSTICR_RSTIC (0x1u << 2) /**< \brief (USBHS_HSTICR) USB Reset Sent Interrupt Clear */ +#define USBHS_HSTICR_RSMEDIC (0x1u << 3) /**< \brief (USBHS_HSTICR) Downstream Resume Sent Interrupt Clear */ +#define USBHS_HSTICR_RXRSMIC (0x1u << 4) /**< \brief (USBHS_HSTICR) Upstream Resume Received Interrupt Clear */ +#define USBHS_HSTICR_HSOFIC (0x1u << 5) /**< \brief (USBHS_HSTICR) Host Start of Frame Interrupt Clear */ +#define USBHS_HSTICR_HWUPIC (0x1u << 6) /**< \brief (USBHS_HSTICR) Host Wake-Up Interrupt Clear */ +/* -------- USBHS_HSTIFR : (USBHS Offset: 0x040C) Host Global Interrupt Set Register -------- */ +#define USBHS_HSTIFR_DCONNIS (0x1u << 0) /**< \brief (USBHS_HSTIFR) Device Connection Interrupt Set */ +#define USBHS_HSTIFR_DDISCIS (0x1u << 1) /**< \brief (USBHS_HSTIFR) Device Disconnection Interrupt Set */ +#define USBHS_HSTIFR_RSTIS (0x1u << 2) /**< \brief (USBHS_HSTIFR) USB Reset Sent Interrupt Set */ +#define USBHS_HSTIFR_RSMEDIS (0x1u << 3) /**< \brief (USBHS_HSTIFR) Downstream Resume Sent Interrupt Set */ +#define USBHS_HSTIFR_RXRSMIS (0x1u << 4) /**< \brief (USBHS_HSTIFR) Upstream Resume Received Interrupt Set */ +#define USBHS_HSTIFR_HSOFIS (0x1u << 5) /**< \brief (USBHS_HSTIFR) Host Start of Frame Interrupt Set */ +#define USBHS_HSTIFR_HWUPIS (0x1u << 6) /**< \brief (USBHS_HSTIFR) Host Wake-Up Interrupt Set */ +#define USBHS_HSTIFR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIFR) DMA Channel 1 Interrupt Set */ +#define USBHS_HSTIFR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIFR) DMA Channel 2 Interrupt Set */ +#define USBHS_HSTIFR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIFR) DMA Channel 3 Interrupt Set */ +#define USBHS_HSTIFR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIFR) DMA Channel 4 Interrupt Set */ +#define USBHS_HSTIFR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIFR) DMA Channel 5 Interrupt Set */ +#define USBHS_HSTIFR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIFR) DMA Channel 6 Interrupt Set */ +#define USBHS_HSTIFR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIFR) DMA Channel 7 Interrupt Set */ +/* -------- USBHS_HSTIMR : (USBHS Offset: 0x0410) Host Global Interrupt Mask Register -------- */ +#define USBHS_HSTIMR_DCONNIE (0x1u << 0) /**< \brief (USBHS_HSTIMR) Device Connection Interrupt Enable */ +#define USBHS_HSTIMR_DDISCIE (0x1u << 1) /**< \brief (USBHS_HSTIMR) Device Disconnection Interrupt Enable */ +#define USBHS_HSTIMR_RSTIE (0x1u << 2) /**< \brief (USBHS_HSTIMR) USB Reset Sent Interrupt Enable */ +#define USBHS_HSTIMR_RSMEDIE (0x1u << 3) /**< \brief (USBHS_HSTIMR) Downstream Resume Sent Interrupt Enable */ +#define USBHS_HSTIMR_RXRSMIE (0x1u << 4) /**< \brief (USBHS_HSTIMR) Upstream Resume Received Interrupt Enable */ +#define USBHS_HSTIMR_HSOFIE (0x1u << 5) /**< \brief (USBHS_HSTIMR) Host Start of Frame Interrupt Enable */ +#define USBHS_HSTIMR_HWUPIE (0x1u << 6) /**< \brief (USBHS_HSTIMR) Host Wake-Up Interrupt Enable */ +#define USBHS_HSTIMR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIMR) Pipe 0 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIMR) Pipe 1 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIMR) Pipe 2 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIMR) Pipe 3 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIMR) Pipe 4 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIMR) Pipe 5 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIMR) Pipe 6 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIMR) Pipe 7 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIMR) Pipe 8 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIMR) Pipe 9 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTIMR) Pipe 10 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTIMR) Pipe 11 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIMR) DMA Channel 1 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIMR) DMA Channel 2 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIMR) DMA Channel 3 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIMR) DMA Channel 4 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIMR) DMA Channel 5 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIMR) DMA Channel 6 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIMR) DMA Channel 7 Interrupt Enable */ +/* -------- USBHS_HSTIDR : (USBHS Offset: 0x0414) Host Global Interrupt Disable Register -------- */ +#define USBHS_HSTIDR_DCONNIEC (0x1u << 0) /**< \brief (USBHS_HSTIDR) Device Connection Interrupt Disable */ +#define USBHS_HSTIDR_DDISCIEC (0x1u << 1) /**< \brief (USBHS_HSTIDR) Device Disconnection Interrupt Disable */ +#define USBHS_HSTIDR_RSTIEC (0x1u << 2) /**< \brief (USBHS_HSTIDR) USB Reset Sent Interrupt Disable */ +#define USBHS_HSTIDR_RSMEDIEC (0x1u << 3) /**< \brief (USBHS_HSTIDR) Downstream Resume Sent Interrupt Disable */ +#define USBHS_HSTIDR_RXRSMIEC (0x1u << 4) /**< \brief (USBHS_HSTIDR) Upstream Resume Received Interrupt Disable */ +#define USBHS_HSTIDR_HSOFIEC (0x1u << 5) /**< \brief (USBHS_HSTIDR) Host Start of Frame Interrupt Disable */ +#define USBHS_HSTIDR_HWUPIEC (0x1u << 6) /**< \brief (USBHS_HSTIDR) Host Wake-Up Interrupt Disable */ +#define USBHS_HSTIDR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIDR) Pipe 0 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIDR) Pipe 1 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIDR) Pipe 2 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIDR) Pipe 3 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIDR) Pipe 4 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIDR) Pipe 5 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIDR) Pipe 6 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIDR) Pipe 7 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIDR) Pipe 8 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIDR) Pipe 9 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTIDR) Pipe 10 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTIDR) Pipe 11 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIDR) DMA Channel 1 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIDR) DMA Channel 2 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIDR) DMA Channel 3 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIDR) DMA Channel 4 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIDR) DMA Channel 5 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIDR) DMA Channel 6 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIDR) DMA Channel 7 Interrupt Disable */ +/* -------- USBHS_HSTIER : (USBHS Offset: 0x0418) Host Global Interrupt Enable Register -------- */ +#define USBHS_HSTIER_DCONNIES (0x1u << 0) /**< \brief (USBHS_HSTIER) Device Connection Interrupt Enable */ +#define USBHS_HSTIER_DDISCIES (0x1u << 1) /**< \brief (USBHS_HSTIER) Device Disconnection Interrupt Enable */ +#define USBHS_HSTIER_RSTIES (0x1u << 2) /**< \brief (USBHS_HSTIER) USB Reset Sent Interrupt Enable */ +#define USBHS_HSTIER_RSMEDIES (0x1u << 3) /**< \brief (USBHS_HSTIER) Downstream Resume Sent Interrupt Enable */ +#define USBHS_HSTIER_RXRSMIES (0x1u << 4) /**< \brief (USBHS_HSTIER) Upstream Resume Received Interrupt Enable */ +#define USBHS_HSTIER_HSOFIES (0x1u << 5) /**< \brief (USBHS_HSTIER) Host Start of Frame Interrupt Enable */ +#define USBHS_HSTIER_HWUPIES (0x1u << 6) /**< \brief (USBHS_HSTIER) Host Wake-Up Interrupt Enable */ +#define USBHS_HSTIER_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIER) Pipe 0 Interrupt Enable */ +#define USBHS_HSTIER_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIER) Pipe 1 Interrupt Enable */ +#define USBHS_HSTIER_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIER) Pipe 2 Interrupt Enable */ +#define USBHS_HSTIER_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIER) Pipe 3 Interrupt Enable */ +#define USBHS_HSTIER_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIER) Pipe 4 Interrupt Enable */ +#define USBHS_HSTIER_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIER) Pipe 5 Interrupt Enable */ +#define USBHS_HSTIER_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIER) Pipe 6 Interrupt Enable */ +#define USBHS_HSTIER_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIER) Pipe 7 Interrupt Enable */ +#define USBHS_HSTIER_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIER) Pipe 8 Interrupt Enable */ +#define USBHS_HSTIER_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIER) Pipe 9 Interrupt Enable */ +#define USBHS_HSTIER_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTIER) Pipe 10 Interrupt Enable */ +#define USBHS_HSTIER_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTIER) Pipe 11 Interrupt Enable */ +#define USBHS_HSTIER_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIER) DMA Channel 1 Interrupt Enable */ +#define USBHS_HSTIER_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIER) DMA Channel 2 Interrupt Enable */ +#define USBHS_HSTIER_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIER) DMA Channel 3 Interrupt Enable */ +#define USBHS_HSTIER_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIER) DMA Channel 4 Interrupt Enable */ +#define USBHS_HSTIER_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIER) DMA Channel 5 Interrupt Enable */ +#define USBHS_HSTIER_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIER) DMA Channel 6 Interrupt Enable */ +#define USBHS_HSTIER_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIER) DMA Channel 7 Interrupt Enable */ +/* -------- USBHS_HSTPIP : (USBHS Offset: 0x0041C) Host Pipe Register -------- */ +#define USBHS_HSTPIP_PEN0 (0x1u << 0) /**< \brief (USBHS_HSTPIP) Pipe 0 Enable */ +#define USBHS_HSTPIP_PEN1 (0x1u << 1) /**< \brief (USBHS_HSTPIP) Pipe 1 Enable */ +#define USBHS_HSTPIP_PEN2 (0x1u << 2) /**< \brief (USBHS_HSTPIP) Pipe 2 Enable */ +#define USBHS_HSTPIP_PEN3 (0x1u << 3) /**< \brief (USBHS_HSTPIP) Pipe 3 Enable */ +#define USBHS_HSTPIP_PEN4 (0x1u << 4) /**< \brief (USBHS_HSTPIP) Pipe 4 Enable */ +#define USBHS_HSTPIP_PEN5 (0x1u << 5) /**< \brief (USBHS_HSTPIP) Pipe 5 Enable */ +#define USBHS_HSTPIP_PEN6 (0x1u << 6) /**< \brief (USBHS_HSTPIP) Pipe 6 Enable */ +#define USBHS_HSTPIP_PEN7 (0x1u << 7) /**< \brief (USBHS_HSTPIP) Pipe 7 Enable */ +#define USBHS_HSTPIP_PEN8 (0x1u << 8) /**< \brief (USBHS_HSTPIP) Pipe 8 Enable */ +#define USBHS_HSTPIP_PRST0 (0x1u << 16) /**< \brief (USBHS_HSTPIP) Pipe 0 Reset */ +#define USBHS_HSTPIP_PRST1 (0x1u << 17) /**< \brief (USBHS_HSTPIP) Pipe 1 Reset */ +#define USBHS_HSTPIP_PRST2 (0x1u << 18) /**< \brief (USBHS_HSTPIP) Pipe 2 Reset */ +#define USBHS_HSTPIP_PRST3 (0x1u << 19) /**< \brief (USBHS_HSTPIP) Pipe 3 Reset */ +#define USBHS_HSTPIP_PRST4 (0x1u << 20) /**< \brief (USBHS_HSTPIP) Pipe 4 Reset */ +#define USBHS_HSTPIP_PRST5 (0x1u << 21) /**< \brief (USBHS_HSTPIP) Pipe 5 Reset */ +#define USBHS_HSTPIP_PRST6 (0x1u << 22) /**< \brief (USBHS_HSTPIP) Pipe 6 Reset */ +#define USBHS_HSTPIP_PRST7 (0x1u << 23) /**< \brief (USBHS_HSTPIP) Pipe 7 Reset */ +#define USBHS_HSTPIP_PRST8 (0x1u << 24) /**< \brief (USBHS_HSTPIP) Pipe 8 Reset */ +/* -------- USBHS_HSTFNUM : (USBHS Offset: 0x0420) Host Frame Number Register -------- */ +#define USBHS_HSTFNUM_MFNUM_Pos 0 +#define USBHS_HSTFNUM_MFNUM_Msk (0x7u << USBHS_HSTFNUM_MFNUM_Pos) /**< \brief (USBHS_HSTFNUM) Micro Frame Number */ +#define USBHS_HSTFNUM_MFNUM(value) ((USBHS_HSTFNUM_MFNUM_Msk & ((value) << USBHS_HSTFNUM_MFNUM_Pos))) +#define USBHS_HSTFNUM_FNUM_Pos 3 +#define USBHS_HSTFNUM_FNUM_Msk (0x7ffu << USBHS_HSTFNUM_FNUM_Pos) /**< \brief (USBHS_HSTFNUM) Frame Number */ +#define USBHS_HSTFNUM_FNUM(value) ((USBHS_HSTFNUM_FNUM_Msk & ((value) << USBHS_HSTFNUM_FNUM_Pos))) +#define USBHS_HSTFNUM_FLENHIGH_Pos 16 +#define USBHS_HSTFNUM_FLENHIGH_Msk (0xffu << USBHS_HSTFNUM_FLENHIGH_Pos) /**< \brief (USBHS_HSTFNUM) Frame Length */ +#define USBHS_HSTFNUM_FLENHIGH(value) ((USBHS_HSTFNUM_FLENHIGH_Msk & ((value) << USBHS_HSTFNUM_FLENHIGH_Pos))) +/* -------- USBHS_HSTADDR1 : (USBHS Offset: 0x0424) Host Address 1 Register -------- */ +#define USBHS_HSTADDR1_HSTADDRP0_Pos 0 +#define USBHS_HSTADDR1_HSTADDRP0_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP0_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP0(value) ((USBHS_HSTADDR1_HSTADDRP0_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP0_Pos))) +#define USBHS_HSTADDR1_HSTADDRP1_Pos 8 +#define USBHS_HSTADDR1_HSTADDRP1_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP1_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP1(value) ((USBHS_HSTADDR1_HSTADDRP1_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP1_Pos))) +#define USBHS_HSTADDR1_HSTADDRP2_Pos 16 +#define USBHS_HSTADDR1_HSTADDRP2_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP2_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP2(value) ((USBHS_HSTADDR1_HSTADDRP2_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP2_Pos))) +#define USBHS_HSTADDR1_HSTADDRP3_Pos 24 +#define USBHS_HSTADDR1_HSTADDRP3_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP3_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP3(value) ((USBHS_HSTADDR1_HSTADDRP3_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP3_Pos))) +/* -------- USBHS_HSTADDR2 : (USBHS Offset: 0x0428) Host Address 2 Register -------- */ +#define USBHS_HSTADDR2_HSTADDRP4_Pos 0 +#define USBHS_HSTADDR2_HSTADDRP4_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP4_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP4(value) ((USBHS_HSTADDR2_HSTADDRP4_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP4_Pos))) +#define USBHS_HSTADDR2_HSTADDRP5_Pos 8 +#define USBHS_HSTADDR2_HSTADDRP5_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP5_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP5(value) ((USBHS_HSTADDR2_HSTADDRP5_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP5_Pos))) +#define USBHS_HSTADDR2_HSTADDRP6_Pos 16 +#define USBHS_HSTADDR2_HSTADDRP6_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP6_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP6(value) ((USBHS_HSTADDR2_HSTADDRP6_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP6_Pos))) +#define USBHS_HSTADDR2_HSTADDRP7_Pos 24 +#define USBHS_HSTADDR2_HSTADDRP7_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP7_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP7(value) ((USBHS_HSTADDR2_HSTADDRP7_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP7_Pos))) +/* -------- USBHS_HSTADDR3 : (USBHS Offset: 0x042C) Host Address 3 Register -------- */ +#define USBHS_HSTADDR3_HSTADDRP8_Pos 0 +#define USBHS_HSTADDR3_HSTADDRP8_Msk (0x7fu << USBHS_HSTADDR3_HSTADDRP8_Pos) /**< \brief (USBHS_HSTADDR3) USB Host Address */ +#define USBHS_HSTADDR3_HSTADDRP8(value) ((USBHS_HSTADDR3_HSTADDRP8_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP8_Pos))) +#define USBHS_HSTADDR3_HSTADDRP9_Pos 8 +#define USBHS_HSTADDR3_HSTADDRP9_Msk (0x7fu << USBHS_HSTADDR3_HSTADDRP9_Pos) /**< \brief (USBHS_HSTADDR3) USB Host Address */ +#define USBHS_HSTADDR3_HSTADDRP9(value) ((USBHS_HSTADDR3_HSTADDRP9_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP9_Pos))) +/* -------- USBHS_HSTPIPCFG[10] : (USBHS Offset: 0x500) Host Pipe Configuration Register (n = 0) -------- */ +#define USBHS_HSTPIPCFG_ALLOC (0x1u << 1) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Memory Allocate */ +#define USBHS_HSTPIPCFG_PBK_Pos 2 +#define USBHS_HSTPIPCFG_PBK_Msk (0x3u << USBHS_HSTPIPCFG_PBK_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Banks */ +#define USBHS_HSTPIPCFG_PBK(value) ((USBHS_HSTPIPCFG_PBK_Msk & ((value) << USBHS_HSTPIPCFG_PBK_Pos))) +#define USBHS_HSTPIPCFG_PBK_1_BANK (0x0u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Single-bank pipe */ +#define USBHS_HSTPIPCFG_PBK_2_BANK (0x1u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Double-bank pipe */ +#define USBHS_HSTPIPCFG_PBK_3_BANK (0x2u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Triple-bank pipe */ +#define USBHS_HSTPIPCFG_PSIZE_Pos 4 +#define USBHS_HSTPIPCFG_PSIZE_Msk (0x7u << USBHS_HSTPIPCFG_PSIZE_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Size */ +#define USBHS_HSTPIPCFG_PSIZE(value) ((USBHS_HSTPIPCFG_PSIZE_Msk & ((value) << USBHS_HSTPIPCFG_PSIZE_Pos))) +#define USBHS_HSTPIPCFG_PSIZE_8_BYTE (0x0u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 8 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_16_BYTE (0x1u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 16 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_32_BYTE (0x2u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 32 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_64_BYTE (0x3u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 64 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_128_BYTE (0x4u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 128 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_256_BYTE (0x5u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 256 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_512_BYTE (0x6u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 512 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_1024_BYTE (0x7u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 1024 bytes */ +#define USBHS_HSTPIPCFG_PTOKEN_Pos 8 +#define USBHS_HSTPIPCFG_PTOKEN_Msk (0x3u << USBHS_HSTPIPCFG_PTOKEN_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Token */ +#define USBHS_HSTPIPCFG_PTOKEN(value) ((USBHS_HSTPIPCFG_PTOKEN_Msk & ((value) << USBHS_HSTPIPCFG_PTOKEN_Pos))) +#define USBHS_HSTPIPCFG_PTOKEN_SETUP (0x0u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) SETUP */ +#define USBHS_HSTPIPCFG_PTOKEN_IN (0x1u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) IN */ +#define USBHS_HSTPIPCFG_PTOKEN_OUT (0x2u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) OUT */ +#define USBHS_HSTPIPCFG_AUTOSW (0x1u << 10) /**< \brief (USBHS_HSTPIPCFG[10]) Automatic Switch */ +#define USBHS_HSTPIPCFG_PTYPE_Pos 12 +#define USBHS_HSTPIPCFG_PTYPE_Msk (0x3u << USBHS_HSTPIPCFG_PTYPE_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Type */ +#define USBHS_HSTPIPCFG_PTYPE(value) ((USBHS_HSTPIPCFG_PTYPE_Msk & ((value) << USBHS_HSTPIPCFG_PTYPE_Pos))) +#define USBHS_HSTPIPCFG_PTYPE_CTRL (0x0u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Control */ +#define USBHS_HSTPIPCFG_PTYPE_ISO (0x1u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Isochronous */ +#define USBHS_HSTPIPCFG_PTYPE_BLK (0x2u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Bulk */ +#define USBHS_HSTPIPCFG_PTYPE_INTRPT (0x3u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Interrupt */ +#define USBHS_HSTPIPCFG_PEPNUM_Pos 16 +#define USBHS_HSTPIPCFG_PEPNUM_Msk (0xfu << USBHS_HSTPIPCFG_PEPNUM_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Endpoint Number */ +#define USBHS_HSTPIPCFG_PEPNUM(value) ((USBHS_HSTPIPCFG_PEPNUM_Msk & ((value) << USBHS_HSTPIPCFG_PEPNUM_Pos))) +#define USBHS_HSTPIPCFG_INTFRQ_Pos 24 +#define USBHS_HSTPIPCFG_INTFRQ_Msk (0xffu << USBHS_HSTPIPCFG_INTFRQ_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Interrupt Request Frequency */ +#define USBHS_HSTPIPCFG_INTFRQ(value) ((USBHS_HSTPIPCFG_INTFRQ_Msk & ((value) << USBHS_HSTPIPCFG_INTFRQ_Pos))) +#define USBHS_HSTPIPCFG_PINGEN (0x1u << 20) /**< \brief (USBHS_HSTPIPCFG[10]) Ping Enable */ +#define USBHS_HSTPIPCFG_BINTERVAL_Pos 24 +#define USBHS_HSTPIPCFG_BINTERVAL_Msk (0xffu << USBHS_HSTPIPCFG_BINTERVAL_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Binterval Parameter for the Bulk-Out/Ping Transaction */ +#define USBHS_HSTPIPCFG_BINTERVAL(value) ((USBHS_HSTPIPCFG_BINTERVAL_Msk & ((value) << USBHS_HSTPIPCFG_BINTERVAL_Pos))) +/* -------- USBHS_HSTPIPISR[10] : (USBHS Offset: 0x530) Host Pipe Status Register (n = 0) -------- */ +#define USBHS_HSTPIPISR_RXINI (0x1u << 0) /**< \brief (USBHS_HSTPIPISR[10]) Received IN Data Interrupt */ +#define USBHS_HSTPIPISR_TXOUTI (0x1u << 1) /**< \brief (USBHS_HSTPIPISR[10]) Transmitted OUT Data Interrupt */ +#define USBHS_HSTPIPISR_TXSTPI (0x1u << 2) /**< \brief (USBHS_HSTPIPISR[10]) Transmitted SETUP Interrupt */ +#define USBHS_HSTPIPISR_PERRI (0x1u << 3) /**< \brief (USBHS_HSTPIPISR[10]) Pipe Error Interrupt */ +#define USBHS_HSTPIPISR_NAKEDI (0x1u << 4) /**< \brief (USBHS_HSTPIPISR[10]) NAKed Interrupt */ +#define USBHS_HSTPIPISR_OVERFI (0x1u << 5) /**< \brief (USBHS_HSTPIPISR[10]) Overflow Interrupt */ +#define USBHS_HSTPIPISR_RXSTALLDI (0x1u << 6) /**< \brief (USBHS_HSTPIPISR[10]) Received STALLed Interrupt */ +#define USBHS_HSTPIPISR_SHORTPACKETI (0x1u << 7) /**< \brief (USBHS_HSTPIPISR[10]) Short Packet Interrupt */ +#define USBHS_HSTPIPISR_DTSEQ_Pos 8 +#define USBHS_HSTPIPISR_DTSEQ_Msk (0x3u << USBHS_HSTPIPISR_DTSEQ_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Data Toggle Sequence */ +#define USBHS_HSTPIPISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (USBHS_HSTPIPISR[10]) Data0 toggle sequence */ +#define USBHS_HSTPIPISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (USBHS_HSTPIPISR[10]) Data1 toggle sequence */ +#define USBHS_HSTPIPISR_NBUSYBK_Pos 12 +#define USBHS_HSTPIPISR_NBUSYBK_Msk (0x3u << USBHS_HSTPIPISR_NBUSYBK_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Number of Busy Banks */ +#define USBHS_HSTPIPISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 0 busy bank (all banks free) */ +#define USBHS_HSTPIPISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 1 busy bank */ +#define USBHS_HSTPIPISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 2 busy banks */ +#define USBHS_HSTPIPISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 3 busy banks */ +#define USBHS_HSTPIPISR_CURRBK_Pos 14 +#define USBHS_HSTPIPISR_CURRBK_Msk (0x3u << USBHS_HSTPIPISR_CURRBK_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Current Bank */ +#define USBHS_HSTPIPISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank0 */ +#define USBHS_HSTPIPISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank1 */ +#define USBHS_HSTPIPISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank2 */ +#define USBHS_HSTPIPISR_RWALL (0x1u << 16) /**< \brief (USBHS_HSTPIPISR[10]) Read/Write Allowed */ +#define USBHS_HSTPIPISR_CFGOK (0x1u << 18) /**< \brief (USBHS_HSTPIPISR[10]) Configuration OK Status */ +#define USBHS_HSTPIPISR_PBYCT_Pos 20 +#define USBHS_HSTPIPISR_PBYCT_Msk (0x7ffu << USBHS_HSTPIPISR_PBYCT_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Pipe Byte Count */ +#define USBHS_HSTPIPISR_UNDERFI (0x1u << 2) /**< \brief (USBHS_HSTPIPISR[10]) Underflow Interrupt */ +#define USBHS_HSTPIPISR_CRCERRI (0x1u << 6) /**< \brief (USBHS_HSTPIPISR[10]) CRC Error Interrupt */ +/* -------- USBHS_HSTPIPICR[10] : (USBHS Offset: 0x560) Host Pipe Clear Register (n = 0) -------- */ +#define USBHS_HSTPIPICR_RXINIC (0x1u << 0) /**< \brief (USBHS_HSTPIPICR[10]) Received IN Data Interrupt Clear */ +#define USBHS_HSTPIPICR_TXOUTIC (0x1u << 1) /**< \brief (USBHS_HSTPIPICR[10]) Transmitted OUT Data Interrupt Clear */ +#define USBHS_HSTPIPICR_TXSTPIC (0x1u << 2) /**< \brief (USBHS_HSTPIPICR[10]) Transmitted SETUP Interrupt Clear */ +#define USBHS_HSTPIPICR_NAKEDIC (0x1u << 4) /**< \brief (USBHS_HSTPIPICR[10]) NAKed Interrupt Clear */ +#define USBHS_HSTPIPICR_OVERFIC (0x1u << 5) /**< \brief (USBHS_HSTPIPICR[10]) Overflow Interrupt Clear */ +#define USBHS_HSTPIPICR_RXSTALLDIC (0x1u << 6) /**< \brief (USBHS_HSTPIPICR[10]) Received STALLed Interrupt Clear */ +#define USBHS_HSTPIPICR_SHORTPACKETIC (0x1u << 7) /**< \brief (USBHS_HSTPIPICR[10]) Short Packet Interrupt Clear */ +#define USBHS_HSTPIPICR_UNDERFIC (0x1u << 2) /**< \brief (USBHS_HSTPIPICR[10]) Underflow Interrupt Clear */ +#define USBHS_HSTPIPICR_CRCERRIC (0x1u << 6) /**< \brief (USBHS_HSTPIPICR[10]) CRC Error Interrupt Clear */ +/* -------- USBHS_HSTPIPIFR[10] : (USBHS Offset: 0x590) Host Pipe Set Register (n = 0) -------- */ +#define USBHS_HSTPIPIFR_RXINIS (0x1u << 0) /**< \brief (USBHS_HSTPIPIFR[10]) Received IN Data Interrupt Set */ +#define USBHS_HSTPIPIFR_TXOUTIS (0x1u << 1) /**< \brief (USBHS_HSTPIPIFR[10]) Transmitted OUT Data Interrupt Set */ +#define USBHS_HSTPIPIFR_TXSTPIS (0x1u << 2) /**< \brief (USBHS_HSTPIPIFR[10]) Transmitted SETUP Interrupt Set */ +#define USBHS_HSTPIPIFR_PERRIS (0x1u << 3) /**< \brief (USBHS_HSTPIPIFR[10]) Pipe Error Interrupt Set */ +#define USBHS_HSTPIPIFR_NAKEDIS (0x1u << 4) /**< \brief (USBHS_HSTPIPIFR[10]) NAKed Interrupt Set */ +#define USBHS_HSTPIPIFR_OVERFIS (0x1u << 5) /**< \brief (USBHS_HSTPIPIFR[10]) Overflow Interrupt Set */ +#define USBHS_HSTPIPIFR_RXSTALLDIS (0x1u << 6) /**< \brief (USBHS_HSTPIPIFR[10]) Received STALLed Interrupt Set */ +#define USBHS_HSTPIPIFR_SHORTPACKETIS (0x1u << 7) /**< \brief (USBHS_HSTPIPIFR[10]) Short Packet Interrupt Set */ +#define USBHS_HSTPIPIFR_NBUSYBKS (0x1u << 12) /**< \brief (USBHS_HSTPIPIFR[10]) Number of Busy Banks Set */ +#define USBHS_HSTPIPIFR_UNDERFIS (0x1u << 2) /**< \brief (USBHS_HSTPIPIFR[10]) Underflow Interrupt Set */ +#define USBHS_HSTPIPIFR_CRCERRIS (0x1u << 6) /**< \brief (USBHS_HSTPIPIFR[10]) CRC Error Interrupt Set */ +/* -------- USBHS_HSTPIPIMR[10] : (USBHS Offset: 0x5C0) Host Pipe Mask Register (n = 0) -------- */ +#define USBHS_HSTPIPIMR_RXINE (0x1u << 0) /**< \brief (USBHS_HSTPIPIMR[10]) Received IN Data Interrupt Enable */ +#define USBHS_HSTPIPIMR_TXOUTE (0x1u << 1) /**< \brief (USBHS_HSTPIPIMR[10]) Transmitted OUT Data Interrupt Enable */ +#define USBHS_HSTPIPIMR_TXSTPE (0x1u << 2) /**< \brief (USBHS_HSTPIPIMR[10]) Transmitted SETUP Interrupt Enable */ +#define USBHS_HSTPIPIMR_PERRE (0x1u << 3) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Error Interrupt Enable */ +#define USBHS_HSTPIPIMR_NAKEDE (0x1u << 4) /**< \brief (USBHS_HSTPIPIMR[10]) NAKed Interrupt Enable */ +#define USBHS_HSTPIPIMR_OVERFIE (0x1u << 5) /**< \brief (USBHS_HSTPIPIMR[10]) Overflow Interrupt Enable */ +#define USBHS_HSTPIPIMR_RXSTALLDE (0x1u << 6) /**< \brief (USBHS_HSTPIPIMR[10]) Received STALLed Interrupt Enable */ +#define USBHS_HSTPIPIMR_SHORTPACKETIE (0x1u << 7) /**< \brief (USBHS_HSTPIPIMR[10]) Short Packet Interrupt Enable */ +#define USBHS_HSTPIPIMR_NBUSYBKE (0x1u << 12) /**< \brief (USBHS_HSTPIPIMR[10]) Number of Busy Banks Interrupt Enable */ +#define USBHS_HSTPIPIMR_FIFOCON (0x1u << 14) /**< \brief (USBHS_HSTPIPIMR[10]) FIFO Control */ +#define USBHS_HSTPIPIMR_PDISHDMA (0x1u << 16) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Interrupts Disable HDMA Request Enable */ +#define USBHS_HSTPIPIMR_PFREEZE (0x1u << 17) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Freeze */ +#define USBHS_HSTPIPIMR_RSTDT (0x1u << 18) /**< \brief (USBHS_HSTPIPIMR[10]) Reset Data Toggle */ +#define USBHS_HSTPIPIMR_UNDERFIE (0x1u << 2) /**< \brief (USBHS_HSTPIPIMR[10]) Underflow Interrupt Enable */ +#define USBHS_HSTPIPIMR_CRCERRE (0x1u << 6) /**< \brief (USBHS_HSTPIPIMR[10]) CRC Error Interrupt Enable */ +/* -------- USBHS_HSTPIPIER[10] : (USBHS Offset: 0x5F0) Host Pipe Enable Register (n = 0) -------- */ +#define USBHS_HSTPIPIER_RXINES (0x1u << 0) /**< \brief (USBHS_HSTPIPIER[10]) Received IN Data Interrupt Enable */ +#define USBHS_HSTPIPIER_TXOUTES (0x1u << 1) /**< \brief (USBHS_HSTPIPIER[10]) Transmitted OUT Data Interrupt Enable */ +#define USBHS_HSTPIPIER_TXSTPES (0x1u << 2) /**< \brief (USBHS_HSTPIPIER[10]) Transmitted SETUP Interrupt Enable */ +#define USBHS_HSTPIPIER_PERRES (0x1u << 3) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Error Interrupt Enable */ +#define USBHS_HSTPIPIER_NAKEDES (0x1u << 4) /**< \brief (USBHS_HSTPIPIER[10]) NAKed Interrupt Enable */ +#define USBHS_HSTPIPIER_OVERFIES (0x1u << 5) /**< \brief (USBHS_HSTPIPIER[10]) Overflow Interrupt Enable */ +#define USBHS_HSTPIPIER_RXSTALLDES (0x1u << 6) /**< \brief (USBHS_HSTPIPIER[10]) Received STALLed Interrupt Enable */ +#define USBHS_HSTPIPIER_SHORTPACKETIES (0x1u << 7) /**< \brief (USBHS_HSTPIPIER[10]) Short Packet Interrupt Enable */ +#define USBHS_HSTPIPIER_NBUSYBKES (0x1u << 12) /**< \brief (USBHS_HSTPIPIER[10]) Number of Busy Banks Enable */ +#define USBHS_HSTPIPIER_PDISHDMAS (0x1u << 16) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Interrupts Disable HDMA Request Enable */ +#define USBHS_HSTPIPIER_PFREEZES (0x1u << 17) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Freeze Enable */ +#define USBHS_HSTPIPIER_RSTDTS (0x1u << 18) /**< \brief (USBHS_HSTPIPIER[10]) Reset Data Toggle Enable */ +#define USBHS_HSTPIPIER_UNDERFIES (0x1u << 2) /**< \brief (USBHS_HSTPIPIER[10]) Underflow Interrupt Enable */ +#define USBHS_HSTPIPIER_CRCERRES (0x1u << 6) /**< \brief (USBHS_HSTPIPIER[10]) CRC Error Interrupt Enable */ +/* -------- USBHS_HSTPIPIDR[10] : (USBHS Offset: 0x620) Host Pipe Disable Register (n = 0) -------- */ +#define USBHS_HSTPIPIDR_RXINEC (0x1u << 0) /**< \brief (USBHS_HSTPIPIDR[10]) Received IN Data Interrupt Disable */ +#define USBHS_HSTPIPIDR_TXOUTEC (0x1u << 1) /**< \brief (USBHS_HSTPIPIDR[10]) Transmitted OUT Data Interrupt Disable */ +#define USBHS_HSTPIPIDR_TXSTPEC (0x1u << 2) /**< \brief (USBHS_HSTPIPIDR[10]) Transmitted SETUP Interrupt Disable */ +#define USBHS_HSTPIPIDR_PERREC (0x1u << 3) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Error Interrupt Disable */ +#define USBHS_HSTPIPIDR_NAKEDEC (0x1u << 4) /**< \brief (USBHS_HSTPIPIDR[10]) NAKed Interrupt Disable */ +#define USBHS_HSTPIPIDR_OVERFIEC (0x1u << 5) /**< \brief (USBHS_HSTPIPIDR[10]) Overflow Interrupt Disable */ +#define USBHS_HSTPIPIDR_RXSTALLDEC (0x1u << 6) /**< \brief (USBHS_HSTPIPIDR[10]) Received STALLed Interrupt Disable */ +#define USBHS_HSTPIPIDR_SHORTPACKETIEC (0x1u << 7) /**< \brief (USBHS_HSTPIPIDR[10]) Short Packet Interrupt Disable */ +#define USBHS_HSTPIPIDR_NBUSYBKEC (0x1u << 12) /**< \brief (USBHS_HSTPIPIDR[10]) Number of Busy Banks Disable */ +#define USBHS_HSTPIPIDR_FIFOCONC (0x1u << 14) /**< \brief (USBHS_HSTPIPIDR[10]) FIFO Control Disable */ +#define USBHS_HSTPIPIDR_PDISHDMAC (0x1u << 16) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Interrupts Disable HDMA Request Disable */ +#define USBHS_HSTPIPIDR_PFREEZEC (0x1u << 17) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Freeze Disable */ +#define USBHS_HSTPIPIDR_UNDERFIEC (0x1u << 2) /**< \brief (USBHS_HSTPIPIDR[10]) Underflow Interrupt Disable */ +#define USBHS_HSTPIPIDR_CRCERREC (0x1u << 6) /**< \brief (USBHS_HSTPIPIDR[10]) CRC Error Interrupt Disable */ +/* -------- USBHS_HSTPIPINRQ[10] : (USBHS Offset: 0x650) Host Pipe IN Request Register (n = 0) -------- */ +#define USBHS_HSTPIPINRQ_INRQ_Pos 0 +#define USBHS_HSTPIPINRQ_INRQ_Msk (0xffu << USBHS_HSTPIPINRQ_INRQ_Pos) /**< \brief (USBHS_HSTPIPINRQ[10]) IN Request Number before Freeze */ +#define USBHS_HSTPIPINRQ_INRQ(value) ((USBHS_HSTPIPINRQ_INRQ_Msk & ((value) << USBHS_HSTPIPINRQ_INRQ_Pos))) +#define USBHS_HSTPIPINRQ_INMODE (0x1u << 8) /**< \brief (USBHS_HSTPIPINRQ[10]) IN Request Mode */ +/* -------- USBHS_HSTPIPERR[10] : (USBHS Offset: 0x680) Host Pipe Error Register (n = 0) -------- */ +#define USBHS_HSTPIPERR_DATATGL (0x1u << 0) /**< \brief (USBHS_HSTPIPERR[10]) Data Toggle Error */ +#define USBHS_HSTPIPERR_DATAPID (0x1u << 1) /**< \brief (USBHS_HSTPIPERR[10]) Data PID Error */ +#define USBHS_HSTPIPERR_PID (0x1u << 2) /**< \brief (USBHS_HSTPIPERR[10]) Data PID Error */ +#define USBHS_HSTPIPERR_TIMEOUT (0x1u << 3) /**< \brief (USBHS_HSTPIPERR[10]) Time-Out Error */ +#define USBHS_HSTPIPERR_CRC16 (0x1u << 4) /**< \brief (USBHS_HSTPIPERR[10]) CRC16 Error */ +#define USBHS_HSTPIPERR_COUNTER_Pos 5 +#define USBHS_HSTPIPERR_COUNTER_Msk (0x3u << USBHS_HSTPIPERR_COUNTER_Pos) /**< \brief (USBHS_HSTPIPERR[10]) Error Counter */ +#define USBHS_HSTPIPERR_COUNTER(value) ((USBHS_HSTPIPERR_COUNTER_Msk & ((value) << USBHS_HSTPIPERR_COUNTER_Pos))) +/* -------- USBHS_HSTDMANXTDSC : (USBHS Offset: N/A) Host DMA Channel Next Descriptor Address Register -------- */ +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos 0 +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (USBHS_HSTDMANXTDSC) Next Descriptor Address */ +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD(value) ((USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos))) +/* -------- USBHS_HSTDMAADDRESS : (USBHS Offset: N/A) Host DMA Channel Address Register -------- */ +#define USBHS_HSTDMAADDRESS_BUFF_ADD_Pos 0 +#define USBHS_HSTDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos) /**< \brief (USBHS_HSTDMAADDRESS) Buffer Address */ +#define USBHS_HSTDMAADDRESS_BUFF_ADD(value) ((USBHS_HSTDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos))) +/* -------- USBHS_HSTDMACONTROL : (USBHS Offset: N/A) Host DMA Channel Control Register -------- */ +#define USBHS_HSTDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_HSTDMACONTROL) Channel Enable Command */ +#define USBHS_HSTDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (USBHS_HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */ +#define USBHS_HSTDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (USBHS_HSTDMACONTROL) End of Transfer Enable Control (OUT transfers only) */ +#define USBHS_HSTDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (USBHS_HSTDMACONTROL) End of Buffer Enable Control */ +#define USBHS_HSTDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (USBHS_HSTDMACONTROL) End of Transfer Interrupt Enable */ +#define USBHS_HSTDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (USBHS_HSTDMACONTROL) End of Buffer Interrupt Enable */ +#define USBHS_HSTDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (USBHS_HSTDMACONTROL) Descriptor Loaded Interrupt Enable */ +#define USBHS_HSTDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (USBHS_HSTDMACONTROL) Burst Lock Enable */ +#define USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos 16 +#define USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk (0xffffu << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (USBHS_HSTDMACONTROL) Buffer Byte Length (Write-only) */ +#define USBHS_HSTDMACONTROL_BUFF_LENGTH(value) ((USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos))) +/* -------- USBHS_HSTDMASTATUS : (USBHS Offset: N/A) Host DMA Channel Status Register -------- */ +#define USBHS_HSTDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_HSTDMASTATUS) Channel Enable Status */ +#define USBHS_HSTDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (USBHS_HSTDMASTATUS) Channel Active Status */ +#define USBHS_HSTDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (USBHS_HSTDMASTATUS) End of Channel Transfer Status */ +#define USBHS_HSTDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (USBHS_HSTDMASTATUS) End of Channel Buffer Status */ +#define USBHS_HSTDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (USBHS_HSTDMASTATUS) Descriptor Loaded Status */ +#define USBHS_HSTDMASTATUS_BUFF_COUNT_Pos 16 +#define USBHS_HSTDMASTATUS_BUFF_COUNT_Msk (0xffffu << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos) /**< \brief (USBHS_HSTDMASTATUS) Buffer Byte Count */ +#define USBHS_HSTDMASTATUS_BUFF_COUNT(value) ((USBHS_HSTDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos))) +/* -------- USBHS_CTRL : (USBHS Offset: 0x0800) General Control Register -------- */ +#define USBHS_CTRL_RDERRE (0x1u << 4) /**< \brief (USBHS_CTRL) Remote Device Connection Error Interrupt Enable */ +#define USBHS_CTRL_FRZCLK (0x1u << 14) /**< \brief (USBHS_CTRL) Freeze USB Clock */ +#define USBHS_CTRL_USBE (0x1u << 15) /**< \brief (USBHS_CTRL) USBHS Enable */ +#define USBHS_CTRL_UIMOD (0x1u << 25) /**< \brief (USBHS_CTRL) USBHS Mode */ +#define USBHS_CTRL_UIMOD_HOST (0x0u << 25) /**< \brief (USBHS_CTRL) The module is in USB Host mode. */ +#define USBHS_CTRL_UIMOD_DEVICE (0x1u << 25) /**< \brief (USBHS_CTRL) The module is in USB Device mode. */ +/* -------- USBHS_SR : (USBHS Offset: 0x0804) General Status Register -------- */ +#define USBHS_SR_RDERRI (0x1u << 4) /**< \brief (USBHS_SR) Remote Device Connection Error Interrupt (Host mode only) */ +#define USBHS_SR_VBUSRQ (0x1u << 9) /**< \brief (USBHS_SR) VBus Request (Host mode only) */ +#define USBHS_SR_SPEED_Pos 12 +#define USBHS_SR_SPEED_Msk (0x3u << USBHS_SR_SPEED_Pos) /**< \brief (USBHS_SR) Speed Status (Device mode only) */ +#define USBHS_SR_SPEED_FULL_SPEED (0x0u << 12) /**< \brief (USBHS_SR) Full-Speed mode */ +#define USBHS_SR_SPEED_HIGH_SPEED (0x1u << 12) /**< \brief (USBHS_SR) High-Speed mode */ +#define USBHS_SR_SPEED_LOW_SPEED (0x2u << 12) /**< \brief (USBHS_SR) Low-Speed mode */ +#define USBHS_SR_CLKUSABLE (0x1u << 14) /**< \brief (USBHS_SR) UTMI Clock Usable */ +/* -------- USBHS_SCR : (USBHS Offset: 0x0808) General Status Clear Register -------- */ +#define USBHS_SCR_RDERRIC (0x1u << 4) /**< \brief (USBHS_SCR) Remote Device Connection Error Interrupt Clear */ +#define USBHS_SCR_VBUSRQC (0x1u << 9) /**< \brief (USBHS_SCR) VBus Request Clear */ +/* -------- USBHS_SFR : (USBHS Offset: 0x080C) General Status Set Register -------- */ +#define USBHS_SFR_RDERRIS (0x1u << 4) /**< \brief (USBHS_SFR) Remote Device Connection Error Interrupt Set */ +#define USBHS_SFR_VBUSRQS (0x1u << 9) /**< \brief (USBHS_SFR) VBus Request Set */ +/* -------- USBHS_TSTA1 : (USBHS Offset: 0x0810) General Test A1 Register -------- */ +#define USBHS_TSTA1_CounterA_Pos 0 +#define USBHS_TSTA1_CounterA_Msk (0x7fffu << USBHS_TSTA1_CounterA_Pos) /**< \brief (USBHS_TSTA1) Counter A */ +#define USBHS_TSTA1_CounterA(value) ((USBHS_TSTA1_CounterA_Msk & ((value) << USBHS_TSTA1_CounterA_Pos))) +#define USBHS_TSTA1_LoadCntA (0x1u << 15) /**< \brief (USBHS_TSTA1) Load CounterA */ +#define USBHS_TSTA1_CounterB_Pos 16 +#define USBHS_TSTA1_CounterB_Msk (0x3fu << USBHS_TSTA1_CounterB_Pos) /**< \brief (USBHS_TSTA1) Counter B */ +#define USBHS_TSTA1_CounterB(value) ((USBHS_TSTA1_CounterB_Msk & ((value) << USBHS_TSTA1_CounterB_Pos))) +#define USBHS_TSTA1_LoadCntB (0x1u << 23) /**< \brief (USBHS_TSTA1) Load CounterB */ +#define USBHS_TSTA1_SOFCntMa1_Pos 24 +#define USBHS_TSTA1_SOFCntMa1_Msk (0x7fu << USBHS_TSTA1_SOFCntMa1_Pos) /**< \brief (USBHS_TSTA1) SOF Counter Max */ +#define USBHS_TSTA1_SOFCntMa1(value) ((USBHS_TSTA1_SOFCntMa1_Msk & ((value) << USBHS_TSTA1_SOFCntMa1_Pos))) +#define USBHS_TSTA1_LoadSOFCnt (0x1u << 31) /**< \brief (USBHS_TSTA1) Load SOF Counter */ +/* -------- USBHS_TSTA2 : (USBHS Offset: 0x0814) General Test A2 Register -------- */ +#define USBHS_TSTA2_FullDetachEn (0x1u << 0) /**< \brief (USBHS_TSTA2) Full Detach Enable */ +#define USBHS_TSTA2_HSSerialMode (0x1u << 1) /**< \brief (USBHS_TSTA2) HS Serial Mode */ +#define USBHS_TSTA2_LoopBackMode (0x1u << 2) /**< \brief (USBHS_TSTA2) Loop-back Mode */ +#define USBHS_TSTA2_DisableGatedClock (0x1u << 3) /**< \brief (USBHS_TSTA2) Disable Gated Clock */ +#define USBHS_TSTA2_ForceSuspendMTo1 (0x1u << 4) /**< \brief (USBHS_TSTA2) Force SuspendM to 1 */ +#define USBHS_TSTA2_ByPassDpll (0x1u << 5) /**< \brief (USBHS_TSTA2) Bypass DPLL */ +#define USBHS_TSTA2_HostHSDisconnectDisable (0x1u << 6) /**< \brief (USBHS_TSTA2) Host HS Disconnect Disable */ +#define USBHS_TSTA2_ForceHSRst_50ms (0x1u << 7) /**< \brief (USBHS_TSTA2) Force HS Reset to 50 ms */ +#define USBHS_TSTA2_RemovePUWhenTX (0x1u << 9) /**< \brief (USBHS_TSTA2) Remove Pull-up When TX */ +/* -------- USBHS_VERSION : (USBHS Offset: 0x0818) General Version Register -------- */ +#define USBHS_VERSION_VERSION_Pos 0 +#define USBHS_VERSION_VERSION_Msk (0xfffu << USBHS_VERSION_VERSION_Pos) /**< \brief (USBHS_VERSION) Version Number */ +#define USBHS_VERSION_MFN_Pos 16 +#define USBHS_VERSION_MFN_Msk (0xfu << USBHS_VERSION_MFN_Pos) /**< \brief (USBHS_VERSION) Metal Fix Number */ +/* -------- USBHS_FSM : (USBHS Offset: 0x082C) General Finite State Machine Register -------- */ +#define USBHS_FSM_DRDSTATE_Pos 0 +#define USBHS_FSM_DRDSTATE_Msk (0xfu << USBHS_FSM_DRDSTATE_Pos) /**< \brief (USBHS_FSM) Dual Role Device State */ +#define USBHS_FSM_DRDSTATE_A_IDLESTATE (0x0u << 0) /**< \brief (USBHS_FSM) This is the start state for A-devices (when the ID pin is 0) */ +#define USBHS_FSM_DRDSTATE_A_WAIT_VRISE (0x1u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for the voltage on VBus to rise above the A-device VBus Valid threshold (4.4 V). */ +#define USBHS_FSM_DRDSTATE_A_WAIT_BCON (0x2u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for the B-device to signal a connection. */ +#define USBHS_FSM_DRDSTATE_A_HOST (0x3u << 0) /**< \brief (USBHS_FSM) In this state, the A-device that operates in Host mode is operational. */ +#define USBHS_FSM_DRDSTATE_A_SUSPEND (0x4u << 0) /**< \brief (USBHS_FSM) The A-device operating as a host is in the Suspend mode. */ +#define USBHS_FSM_DRDSTATE_A_PERIPHERAL (0x5u << 0) /**< \brief (USBHS_FSM) The A-device operates as a peripheral. */ +#define USBHS_FSM_DRDSTATE_A_WAIT_VFALL (0x6u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for the voltage on VBus to drop below the A-device Session Valid threshold (1.4 V). */ +#define USBHS_FSM_DRDSTATE_A_VBUS_ERR (0x7u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for recovery of the over-current condition that caused it to enter this state. */ +#define USBHS_FSM_DRDSTATE_A_WAIT_DISCHARGE (0x8u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for the data USB line to discharge (100 us). */ +#define USBHS_FSM_DRDSTATE_B_IDLE (0x9u << 0) /**< \brief (USBHS_FSM) This is the start state for B-device (when the ID pin is 1). */ +#define USBHS_FSM_DRDSTATE_B_PERIPHERAL (0xAu << 0) /**< \brief (USBHS_FSM) In this state, the B-device acts as the peripheral. */ +#define USBHS_FSM_DRDSTATE_B_WAIT_BEGIN_HNP (0xBu << 0) /**< \brief (USBHS_FSM) In this state, the B-device is in Suspend mode and waits until 3 ms before initiating the HNP protocol if requested. */ +#define USBHS_FSM_DRDSTATE_B_WAIT_DISCHARGE (0xCu << 0) /**< \brief (USBHS_FSM) In this state, the B-device waits for the data USB line to discharge (100 us)) before becoming Host. */ +#define USBHS_FSM_DRDSTATE_B_WAIT_ACON (0xDu << 0) /**< \brief (USBHS_FSM) In this state, the B-device waits for the A-device to signal a connect before becoming B-Host. */ +#define USBHS_FSM_DRDSTATE_B_HOST (0xEu << 0) /**< \brief (USBHS_FSM) In this state, the B-device acts as the Host. */ +#define USBHS_FSM_DRDSTATE_B_SRP_INIT (0xFu << 0) /**< \brief (USBHS_FSM) In this state, the B-device attempts to start a session using the SRP protocol. */ + +/*@}*/ + + +#endif /* _SAMV71_USBHS_COMPONENT_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_utmi.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_utmi.h new file mode 100644 index 00000000..682c48d3 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_utmi.h @@ -0,0 +1,63 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_UTMI_COMPONENT_ +#define _SAMV71_UTMI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR USB Transmitter Interface Macrocell */ +/* ============================================================================= */ +/** \addtogroup SAMV71_UTMI USB Transmitter Interface Macrocell */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Utmi hardware registers */ +typedef struct { + __I uint32_t Reserved1[4]; + __IO uint32_t UTMI_OHCIICR; /**< \brief (Utmi Offset: 0x10) OHCI Interrupt Configuration Register */ + __I uint32_t Reserved2[7]; + __IO uint32_t UTMI_CKTRIM; /**< \brief (Utmi Offset: 0x30) UTMI Clock Trimming Register */ +} Utmi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- UTMI_OHCIICR : (UTMI Offset: 0x10) OHCI Interrupt Configuration Register -------- */ +#define UTMI_OHCIICR_RES0 (0x1u << 0) /**< \brief (UTMI_OHCIICR) USB PORTx Reset */ +#define UTMI_OHCIICR_ARIE (0x1u << 4) /**< \brief (UTMI_OHCIICR) OHCI Asynchronous Resume Interrupt Enable */ +#define UTMI_OHCIICR_APPSTART (0x1u << 5) /**< \brief (UTMI_OHCIICR) Reserved */ +#define UTMI_OHCIICR_UDPPUDIS (0x1u << 23) /**< \brief (UTMI_OHCIICR) USB Device Pull-up Disable */ +/* -------- UTMI_CKTRIM : (UTMI Offset: 0x30) UTMI Clock Trimming Register -------- */ +#define UTMI_CKTRIM_FREQ_Pos 0 +#define UTMI_CKTRIM_FREQ_Msk (0x3u << UTMI_CKTRIM_FREQ_Pos) /**< \brief (UTMI_CKTRIM) UTMI Reference Clock Frequency */ +#define UTMI_CKTRIM_FREQ(value) ((UTMI_CKTRIM_FREQ_Msk & ((value) << UTMI_CKTRIM_FREQ_Pos))) +#define UTMI_CKTRIM_FREQ_XTAL12 (0x0u << 0) /**< \brief (UTMI_CKTRIM) 12 MHz reference clock */ +#define UTMI_CKTRIM_FREQ_XTAL16 (0x1u << 0) /**< \brief (UTMI_CKTRIM) 16 MHz reference clock */ + +/*@}*/ + + +#endif /* _SAMV71_UTMI_COMPONENT_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_wdt.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_wdt.h new file mode 100644 index 00000000..1e2ac187 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_wdt.h @@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_WDT_COMPONENT_ +#define _SAMV71_WDT_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Watchdog Timer */ +/* ============================================================================= */ +/** \addtogroup SAMV71_WDT Watchdog Timer */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Wdt hardware registers */ +typedef struct { + __O uint32_t WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */ + __IO uint32_t WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */ + __I uint32_t WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */ +} Wdt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */ +#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */ +#define WDT_CR_KEY_Pos 24 +#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */ +#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos))) +#define WDT_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (WDT_CR) Writing any other value in this field aborts the write operation. */ +/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */ +#define WDT_MR_WDV_Pos 0 +#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */ +#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos))) +#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */ +#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */ +#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */ +#define WDT_MR_WDD_Pos 16 +#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */ +#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos))) +#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */ +#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */ +/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */ +#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow (cleared on read) */ +#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error (cleared on read) */ + +/*@}*/ + + +#endif /* _SAMV71_WDT_COMPONENT_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_xdmac.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_xdmac.h new file mode 100644 index 00000000..4e23710a --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/component/component_xdmac.h @@ -0,0 +1,619 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_XDMAC_COMPONENT_ +#define _SAMV71_XDMAC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Extensible DMA Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_XDMAC Extensible DMA Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief XdmacChid hardware registers */ +typedef struct { + __O uint32_t XDMAC_CIE; /**< \brief (XdmacChid Offset: 0x0) Channel Interrupt Enable Register */ + __O uint32_t XDMAC_CID; /**< \brief (XdmacChid Offset: 0x4) Channel Interrupt Disable Register */ + __O uint32_t XDMAC_CIM; /**< \brief (XdmacChid Offset: 0x8) Channel Interrupt Mask Register */ + __I uint32_t XDMAC_CIS; /**< \brief (XdmacChid Offset: 0xC) Channel Interrupt Status Register */ + __IO uint32_t XDMAC_CSA; /**< \brief (XdmacChid Offset: 0x10) Channel Source Address Register */ + __IO uint32_t XDMAC_CDA; /**< \brief (XdmacChid Offset: 0x14) Channel Destination Address Register */ + __IO uint32_t XDMAC_CNDA; /**< \brief (XdmacChid Offset: 0x18) Channel Next Descriptor Address Register */ + __IO uint32_t XDMAC_CNDC; /**< \brief (XdmacChid Offset: 0x1C) Channel Next Descriptor Control Register */ + __IO uint32_t XDMAC_CUBC; /**< \brief (XdmacChid Offset: 0x20) Channel Microblock Control Register */ + __IO uint32_t XDMAC_CBC; /**< \brief (XdmacChid Offset: 0x24) Channel Block Control Register */ + __IO uint32_t XDMAC_CC; /**< \brief (XdmacChid Offset: 0x28) Channel Configuration Register */ + __IO uint32_t XDMAC_CDS_MSP; /**< \brief (XdmacChid Offset: 0x2C) Channel Data Stride Memory Set Pattern */ + __IO uint32_t XDMAC_CSUS; /**< \brief (XdmacChid Offset: 0x30) Channel Source Microblock Stride */ + __IO uint32_t XDMAC_CDUS; /**< \brief (XdmacChid Offset: 0x34) Channel Destination Microblock Stride */ + __I uint32_t Reserved1[2]; +} XdmacChid; +/** \brief Xdmac hardware registers */ +#define XDMACCHID_NUMBER 24 +typedef struct { + __IO uint32_t XDMAC_GTYPE; /**< \brief (Xdmac Offset: 0x00) Global Type Register */ + __I uint32_t XDMAC_GCFG; /**< \brief (Xdmac Offset: 0x04) Global Configuration Register */ + __IO uint32_t XDMAC_GWAC; /**< \brief (Xdmac Offset: 0x08) Global Weighted Arbiter Configuration Register */ + __O uint32_t XDMAC_GIE; /**< \brief (Xdmac Offset: 0x0C) Global Interrupt Enable Register */ + __O uint32_t XDMAC_GID; /**< \brief (Xdmac Offset: 0x10) Global Interrupt Disable Register */ + __I uint32_t XDMAC_GIM; /**< \brief (Xdmac Offset: 0x14) Global Interrupt Mask Register */ + __I uint32_t XDMAC_GIS; /**< \brief (Xdmac Offset: 0x18) Global Interrupt Status Register */ + __O uint32_t XDMAC_GE; /**< \brief (Xdmac Offset: 0x1C) Global Channel Enable Register */ + __O uint32_t XDMAC_GD; /**< \brief (Xdmac Offset: 0x20) Global Channel Disable Register */ + __I uint32_t XDMAC_GS; /**< \brief (Xdmac Offset: 0x24) Global Channel Status Register */ + __IO uint32_t XDMAC_GRS; /**< \brief (Xdmac Offset: 0x28) Global Channel Read Suspend Register */ + __IO uint32_t XDMAC_GWS; /**< \brief (Xdmac Offset: 0x2C) Global Channel Write Suspend Register */ + __O uint32_t XDMAC_GRWS; /**< \brief (Xdmac Offset: 0x30) Global Channel Read Write Suspend Register */ + __O uint32_t XDMAC_GRWR; /**< \brief (Xdmac Offset: 0x34) Global Channel Read Write Resume Register */ + __O uint32_t XDMAC_GSWR; /**< \brief (Xdmac Offset: 0x38) Global Channel Software Request Register */ + __I uint32_t XDMAC_GSWS; /**< \brief (Xdmac Offset: 0x3C) Global Channel Software Request Status Register */ + __O uint32_t XDMAC_GSWF; /**< \brief (Xdmac Offset: 0x40) Global Channel Software Flush Request Register */ + __I uint32_t Reserved1[3]; + XdmacChid XDMAC_CHID[XDMACCHID_NUMBER]; /**< \brief (Xdmac Offset: 0x50) chid = 0 .. 23 */ +} Xdmac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- XDMAC_GTYPE : (XDMAC Offset: 0x00) Global Type Register -------- */ +#define XDMAC_GTYPE_NB_CH_Pos 0 +#define XDMAC_GTYPE_NB_CH_Msk (0x1fu << XDMAC_GTYPE_NB_CH_Pos) /**< \brief (XDMAC_GTYPE) Number of Channels Minus One */ +#define XDMAC_GTYPE_NB_CH(value) ((XDMAC_GTYPE_NB_CH_Msk & ((value) << XDMAC_GTYPE_NB_CH_Pos))) +#define XDMAC_GTYPE_FIFO_SZ_Pos 5 +#define XDMAC_GTYPE_FIFO_SZ_Msk (0x7ffu << XDMAC_GTYPE_FIFO_SZ_Pos) /**< \brief (XDMAC_GTYPE) Number of Bytes */ +#define XDMAC_GTYPE_FIFO_SZ(value) ((XDMAC_GTYPE_FIFO_SZ_Msk & ((value) << XDMAC_GTYPE_FIFO_SZ_Pos))) +#define XDMAC_GTYPE_NB_REQ_Pos 16 +#define XDMAC_GTYPE_NB_REQ_Msk (0x7fu << XDMAC_GTYPE_NB_REQ_Pos) /**< \brief (XDMAC_GTYPE) Number of Peripheral Requests Minus One */ +#define XDMAC_GTYPE_NB_REQ(value) ((XDMAC_GTYPE_NB_REQ_Msk & ((value) << XDMAC_GTYPE_NB_REQ_Pos))) +/* -------- XDMAC_GCFG : (XDMAC Offset: 0x04) Global Configuration Register -------- */ +#define XDMAC_GCFG_CGDISREG (0x1u << 0) /**< \brief (XDMAC_GCFG) Configuration Registers Clock Gating Disable */ +#define XDMAC_GCFG_CGDISPIPE (0x1u << 1) /**< \brief (XDMAC_GCFG) Pipeline Clock Gating Disable */ +#define XDMAC_GCFG_CGDISFIFO (0x1u << 2) /**< \brief (XDMAC_GCFG) FIFO Clock Gating Disable */ +#define XDMAC_GCFG_CGDISIF (0x1u << 3) /**< \brief (XDMAC_GCFG) Bus Interface Clock Gating Disable */ +#define XDMAC_GCFG_BXKBEN (0x1u << 8) /**< \brief (XDMAC_GCFG) Boundary X Kilo byte Enable */ +/* -------- XDMAC_GWAC : (XDMAC Offset: 0x08) Global Weighted Arbiter Configuration Register -------- */ +#define XDMAC_GWAC_PW0_Pos 0 +#define XDMAC_GWAC_PW0_Msk (0xfu << XDMAC_GWAC_PW0_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 0 */ +#define XDMAC_GWAC_PW0(value) ((XDMAC_GWAC_PW0_Msk & ((value) << XDMAC_GWAC_PW0_Pos))) +#define XDMAC_GWAC_PW1_Pos 4 +#define XDMAC_GWAC_PW1_Msk (0xfu << XDMAC_GWAC_PW1_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 1 */ +#define XDMAC_GWAC_PW1(value) ((XDMAC_GWAC_PW1_Msk & ((value) << XDMAC_GWAC_PW1_Pos))) +#define XDMAC_GWAC_PW2_Pos 8 +#define XDMAC_GWAC_PW2_Msk (0xfu << XDMAC_GWAC_PW2_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 2 */ +#define XDMAC_GWAC_PW2(value) ((XDMAC_GWAC_PW2_Msk & ((value) << XDMAC_GWAC_PW2_Pos))) +#define XDMAC_GWAC_PW3_Pos 12 +#define XDMAC_GWAC_PW3_Msk (0xfu << XDMAC_GWAC_PW3_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 3 */ +#define XDMAC_GWAC_PW3(value) ((XDMAC_GWAC_PW3_Msk & ((value) << XDMAC_GWAC_PW3_Pos))) +/* -------- XDMAC_GIE : (XDMAC Offset: 0x0C) Global Interrupt Enable Register -------- */ +#define XDMAC_GIE_IE0 (0x1u << 0) /**< \brief (XDMAC_GIE) XDMAC Channel 0 Interrupt Enable Bit */ +#define XDMAC_GIE_IE1 (0x1u << 1) /**< \brief (XDMAC_GIE) XDMAC Channel 1 Interrupt Enable Bit */ +#define XDMAC_GIE_IE2 (0x1u << 2) /**< \brief (XDMAC_GIE) XDMAC Channel 2 Interrupt Enable Bit */ +#define XDMAC_GIE_IE3 (0x1u << 3) /**< \brief (XDMAC_GIE) XDMAC Channel 3 Interrupt Enable Bit */ +#define XDMAC_GIE_IE4 (0x1u << 4) /**< \brief (XDMAC_GIE) XDMAC Channel 4 Interrupt Enable Bit */ +#define XDMAC_GIE_IE5 (0x1u << 5) /**< \brief (XDMAC_GIE) XDMAC Channel 5 Interrupt Enable Bit */ +#define XDMAC_GIE_IE6 (0x1u << 6) /**< \brief (XDMAC_GIE) XDMAC Channel 6 Interrupt Enable Bit */ +#define XDMAC_GIE_IE7 (0x1u << 7) /**< \brief (XDMAC_GIE) XDMAC Channel 7 Interrupt Enable Bit */ +#define XDMAC_GIE_IE8 (0x1u << 8) /**< \brief (XDMAC_GIE) XDMAC Channel 8 Interrupt Enable Bit */ +#define XDMAC_GIE_IE9 (0x1u << 9) /**< \brief (XDMAC_GIE) XDMAC Channel 9 Interrupt Enable Bit */ +#define XDMAC_GIE_IE10 (0x1u << 10) /**< \brief (XDMAC_GIE) XDMAC Channel 10 Interrupt Enable Bit */ +#define XDMAC_GIE_IE11 (0x1u << 11) /**< \brief (XDMAC_GIE) XDMAC Channel 11 Interrupt Enable Bit */ +#define XDMAC_GIE_IE12 (0x1u << 12) /**< \brief (XDMAC_GIE) XDMAC Channel 12 Interrupt Enable Bit */ +#define XDMAC_GIE_IE13 (0x1u << 13) /**< \brief (XDMAC_GIE) XDMAC Channel 13 Interrupt Enable Bit */ +#define XDMAC_GIE_IE14 (0x1u << 14) /**< \brief (XDMAC_GIE) XDMAC Channel 14 Interrupt Enable Bit */ +#define XDMAC_GIE_IE15 (0x1u << 15) /**< \brief (XDMAC_GIE) XDMAC Channel 15 Interrupt Enable Bit */ +#define XDMAC_GIE_IE16 (0x1u << 16) /**< \brief (XDMAC_GIE) XDMAC Channel 16 Interrupt Enable Bit */ +#define XDMAC_GIE_IE17 (0x1u << 17) /**< \brief (XDMAC_GIE) XDMAC Channel 17 Interrupt Enable Bit */ +#define XDMAC_GIE_IE18 (0x1u << 18) /**< \brief (XDMAC_GIE) XDMAC Channel 18 Interrupt Enable Bit */ +#define XDMAC_GIE_IE19 (0x1u << 19) /**< \brief (XDMAC_GIE) XDMAC Channel 19 Interrupt Enable Bit */ +#define XDMAC_GIE_IE20 (0x1u << 20) /**< \brief (XDMAC_GIE) XDMAC Channel 20 Interrupt Enable Bit */ +#define XDMAC_GIE_IE21 (0x1u << 21) /**< \brief (XDMAC_GIE) XDMAC Channel 21 Interrupt Enable Bit */ +#define XDMAC_GIE_IE22 (0x1u << 22) /**< \brief (XDMAC_GIE) XDMAC Channel 22 Interrupt Enable Bit */ +#define XDMAC_GIE_IE23 (0x1u << 23) /**< \brief (XDMAC_GIE) XDMAC Channel 23 Interrupt Enable Bit */ +/* -------- XDMAC_GID : (XDMAC Offset: 0x10) Global Interrupt Disable Register -------- */ +#define XDMAC_GID_ID0 (0x1u << 0) /**< \brief (XDMAC_GID) XDMAC Channel 0 Interrupt Disable Bit */ +#define XDMAC_GID_ID1 (0x1u << 1) /**< \brief (XDMAC_GID) XDMAC Channel 1 Interrupt Disable Bit */ +#define XDMAC_GID_ID2 (0x1u << 2) /**< \brief (XDMAC_GID) XDMAC Channel 2 Interrupt Disable Bit */ +#define XDMAC_GID_ID3 (0x1u << 3) /**< \brief (XDMAC_GID) XDMAC Channel 3 Interrupt Disable Bit */ +#define XDMAC_GID_ID4 (0x1u << 4) /**< \brief (XDMAC_GID) XDMAC Channel 4 Interrupt Disable Bit */ +#define XDMAC_GID_ID5 (0x1u << 5) /**< \brief (XDMAC_GID) XDMAC Channel 5 Interrupt Disable Bit */ +#define XDMAC_GID_ID6 (0x1u << 6) /**< \brief (XDMAC_GID) XDMAC Channel 6 Interrupt Disable Bit */ +#define XDMAC_GID_ID7 (0x1u << 7) /**< \brief (XDMAC_GID) XDMAC Channel 7 Interrupt Disable Bit */ +#define XDMAC_GID_ID8 (0x1u << 8) /**< \brief (XDMAC_GID) XDMAC Channel 8 Interrupt Disable Bit */ +#define XDMAC_GID_ID9 (0x1u << 9) /**< \brief (XDMAC_GID) XDMAC Channel 9 Interrupt Disable Bit */ +#define XDMAC_GID_ID10 (0x1u << 10) /**< \brief (XDMAC_GID) XDMAC Channel 10 Interrupt Disable Bit */ +#define XDMAC_GID_ID11 (0x1u << 11) /**< \brief (XDMAC_GID) XDMAC Channel 11 Interrupt Disable Bit */ +#define XDMAC_GID_ID12 (0x1u << 12) /**< \brief (XDMAC_GID) XDMAC Channel 12 Interrupt Disable Bit */ +#define XDMAC_GID_ID13 (0x1u << 13) /**< \brief (XDMAC_GID) XDMAC Channel 13 Interrupt Disable Bit */ +#define XDMAC_GID_ID14 (0x1u << 14) /**< \brief (XDMAC_GID) XDMAC Channel 14 Interrupt Disable Bit */ +#define XDMAC_GID_ID15 (0x1u << 15) /**< \brief (XDMAC_GID) XDMAC Channel 15 Interrupt Disable Bit */ +#define XDMAC_GID_ID16 (0x1u << 16) /**< \brief (XDMAC_GID) XDMAC Channel 16 Interrupt Disable Bit */ +#define XDMAC_GID_ID17 (0x1u << 17) /**< \brief (XDMAC_GID) XDMAC Channel 17 Interrupt Disable Bit */ +#define XDMAC_GID_ID18 (0x1u << 18) /**< \brief (XDMAC_GID) XDMAC Channel 18 Interrupt Disable Bit */ +#define XDMAC_GID_ID19 (0x1u << 19) /**< \brief (XDMAC_GID) XDMAC Channel 19 Interrupt Disable Bit */ +#define XDMAC_GID_ID20 (0x1u << 20) /**< \brief (XDMAC_GID) XDMAC Channel 20 Interrupt Disable Bit */ +#define XDMAC_GID_ID21 (0x1u << 21) /**< \brief (XDMAC_GID) XDMAC Channel 21 Interrupt Disable Bit */ +#define XDMAC_GID_ID22 (0x1u << 22) /**< \brief (XDMAC_GID) XDMAC Channel 22 Interrupt Disable Bit */ +#define XDMAC_GID_ID23 (0x1u << 23) /**< \brief (XDMAC_GID) XDMAC Channel 23 Interrupt Disable Bit */ +/* -------- XDMAC_GIM : (XDMAC Offset: 0x14) Global Interrupt Mask Register -------- */ +#define XDMAC_GIM_IM0 (0x1u << 0) /**< \brief (XDMAC_GIM) XDMAC Channel 0 Interrupt Mask Bit */ +#define XDMAC_GIM_IM1 (0x1u << 1) /**< \brief (XDMAC_GIM) XDMAC Channel 1 Interrupt Mask Bit */ +#define XDMAC_GIM_IM2 (0x1u << 2) /**< \brief (XDMAC_GIM) XDMAC Channel 2 Interrupt Mask Bit */ +#define XDMAC_GIM_IM3 (0x1u << 3) /**< \brief (XDMAC_GIM) XDMAC Channel 3 Interrupt Mask Bit */ +#define XDMAC_GIM_IM4 (0x1u << 4) /**< \brief (XDMAC_GIM) XDMAC Channel 4 Interrupt Mask Bit */ +#define XDMAC_GIM_IM5 (0x1u << 5) /**< \brief (XDMAC_GIM) XDMAC Channel 5 Interrupt Mask Bit */ +#define XDMAC_GIM_IM6 (0x1u << 6) /**< \brief (XDMAC_GIM) XDMAC Channel 6 Interrupt Mask Bit */ +#define XDMAC_GIM_IM7 (0x1u << 7) /**< \brief (XDMAC_GIM) XDMAC Channel 7 Interrupt Mask Bit */ +#define XDMAC_GIM_IM8 (0x1u << 8) /**< \brief (XDMAC_GIM) XDMAC Channel 8 Interrupt Mask Bit */ +#define XDMAC_GIM_IM9 (0x1u << 9) /**< \brief (XDMAC_GIM) XDMAC Channel 9 Interrupt Mask Bit */ +#define XDMAC_GIM_IM10 (0x1u << 10) /**< \brief (XDMAC_GIM) XDMAC Channel 10 Interrupt Mask Bit */ +#define XDMAC_GIM_IM11 (0x1u << 11) /**< \brief (XDMAC_GIM) XDMAC Channel 11 Interrupt Mask Bit */ +#define XDMAC_GIM_IM12 (0x1u << 12) /**< \brief (XDMAC_GIM) XDMAC Channel 12 Interrupt Mask Bit */ +#define XDMAC_GIM_IM13 (0x1u << 13) /**< \brief (XDMAC_GIM) XDMAC Channel 13 Interrupt Mask Bit */ +#define XDMAC_GIM_IM14 (0x1u << 14) /**< \brief (XDMAC_GIM) XDMAC Channel 14 Interrupt Mask Bit */ +#define XDMAC_GIM_IM15 (0x1u << 15) /**< \brief (XDMAC_GIM) XDMAC Channel 15 Interrupt Mask Bit */ +#define XDMAC_GIM_IM16 (0x1u << 16) /**< \brief (XDMAC_GIM) XDMAC Channel 16 Interrupt Mask Bit */ +#define XDMAC_GIM_IM17 (0x1u << 17) /**< \brief (XDMAC_GIM) XDMAC Channel 17 Interrupt Mask Bit */ +#define XDMAC_GIM_IM18 (0x1u << 18) /**< \brief (XDMAC_GIM) XDMAC Channel 18 Interrupt Mask Bit */ +#define XDMAC_GIM_IM19 (0x1u << 19) /**< \brief (XDMAC_GIM) XDMAC Channel 19 Interrupt Mask Bit */ +#define XDMAC_GIM_IM20 (0x1u << 20) /**< \brief (XDMAC_GIM) XDMAC Channel 20 Interrupt Mask Bit */ +#define XDMAC_GIM_IM21 (0x1u << 21) /**< \brief (XDMAC_GIM) XDMAC Channel 21 Interrupt Mask Bit */ +#define XDMAC_GIM_IM22 (0x1u << 22) /**< \brief (XDMAC_GIM) XDMAC Channel 22 Interrupt Mask Bit */ +#define XDMAC_GIM_IM23 (0x1u << 23) /**< \brief (XDMAC_GIM) XDMAC Channel 23 Interrupt Mask Bit */ +/* -------- XDMAC_GIS : (XDMAC Offset: 0x18) Global Interrupt Status Register -------- */ +#define XDMAC_GIS_IS0 (0x1u << 0) /**< \brief (XDMAC_GIS) XDMAC Channel 0 Interrupt Status Bit */ +#define XDMAC_GIS_IS1 (0x1u << 1) /**< \brief (XDMAC_GIS) XDMAC Channel 1 Interrupt Status Bit */ +#define XDMAC_GIS_IS2 (0x1u << 2) /**< \brief (XDMAC_GIS) XDMAC Channel 2 Interrupt Status Bit */ +#define XDMAC_GIS_IS3 (0x1u << 3) /**< \brief (XDMAC_GIS) XDMAC Channel 3 Interrupt Status Bit */ +#define XDMAC_GIS_IS4 (0x1u << 4) /**< \brief (XDMAC_GIS) XDMAC Channel 4 Interrupt Status Bit */ +#define XDMAC_GIS_IS5 (0x1u << 5) /**< \brief (XDMAC_GIS) XDMAC Channel 5 Interrupt Status Bit */ +#define XDMAC_GIS_IS6 (0x1u << 6) /**< \brief (XDMAC_GIS) XDMAC Channel 6 Interrupt Status Bit */ +#define XDMAC_GIS_IS7 (0x1u << 7) /**< \brief (XDMAC_GIS) XDMAC Channel 7 Interrupt Status Bit */ +#define XDMAC_GIS_IS8 (0x1u << 8) /**< \brief (XDMAC_GIS) XDMAC Channel 8 Interrupt Status Bit */ +#define XDMAC_GIS_IS9 (0x1u << 9) /**< \brief (XDMAC_GIS) XDMAC Channel 9 Interrupt Status Bit */ +#define XDMAC_GIS_IS10 (0x1u << 10) /**< \brief (XDMAC_GIS) XDMAC Channel 10 Interrupt Status Bit */ +#define XDMAC_GIS_IS11 (0x1u << 11) /**< \brief (XDMAC_GIS) XDMAC Channel 11 Interrupt Status Bit */ +#define XDMAC_GIS_IS12 (0x1u << 12) /**< \brief (XDMAC_GIS) XDMAC Channel 12 Interrupt Status Bit */ +#define XDMAC_GIS_IS13 (0x1u << 13) /**< \brief (XDMAC_GIS) XDMAC Channel 13 Interrupt Status Bit */ +#define XDMAC_GIS_IS14 (0x1u << 14) /**< \brief (XDMAC_GIS) XDMAC Channel 14 Interrupt Status Bit */ +#define XDMAC_GIS_IS15 (0x1u << 15) /**< \brief (XDMAC_GIS) XDMAC Channel 15 Interrupt Status Bit */ +#define XDMAC_GIS_IS16 (0x1u << 16) /**< \brief (XDMAC_GIS) XDMAC Channel 16 Interrupt Status Bit */ +#define XDMAC_GIS_IS17 (0x1u << 17) /**< \brief (XDMAC_GIS) XDMAC Channel 17 Interrupt Status Bit */ +#define XDMAC_GIS_IS18 (0x1u << 18) /**< \brief (XDMAC_GIS) XDMAC Channel 18 Interrupt Status Bit */ +#define XDMAC_GIS_IS19 (0x1u << 19) /**< \brief (XDMAC_GIS) XDMAC Channel 19 Interrupt Status Bit */ +#define XDMAC_GIS_IS20 (0x1u << 20) /**< \brief (XDMAC_GIS) XDMAC Channel 20 Interrupt Status Bit */ +#define XDMAC_GIS_IS21 (0x1u << 21) /**< \brief (XDMAC_GIS) XDMAC Channel 21 Interrupt Status Bit */ +#define XDMAC_GIS_IS22 (0x1u << 22) /**< \brief (XDMAC_GIS) XDMAC Channel 22 Interrupt Status Bit */ +#define XDMAC_GIS_IS23 (0x1u << 23) /**< \brief (XDMAC_GIS) XDMAC Channel 23 Interrupt Status Bit */ +/* -------- XDMAC_GE : (XDMAC Offset: 0x1C) Global Channel Enable Register -------- */ +#define XDMAC_GE_EN0 (0x1u << 0) /**< \brief (XDMAC_GE) XDMAC Channel 0 Enable Bit */ +#define XDMAC_GE_EN1 (0x1u << 1) /**< \brief (XDMAC_GE) XDMAC Channel 1 Enable Bit */ +#define XDMAC_GE_EN2 (0x1u << 2) /**< \brief (XDMAC_GE) XDMAC Channel 2 Enable Bit */ +#define XDMAC_GE_EN3 (0x1u << 3) /**< \brief (XDMAC_GE) XDMAC Channel 3 Enable Bit */ +#define XDMAC_GE_EN4 (0x1u << 4) /**< \brief (XDMAC_GE) XDMAC Channel 4 Enable Bit */ +#define XDMAC_GE_EN5 (0x1u << 5) /**< \brief (XDMAC_GE) XDMAC Channel 5 Enable Bit */ +#define XDMAC_GE_EN6 (0x1u << 6) /**< \brief (XDMAC_GE) XDMAC Channel 6 Enable Bit */ +#define XDMAC_GE_EN7 (0x1u << 7) /**< \brief (XDMAC_GE) XDMAC Channel 7 Enable Bit */ +#define XDMAC_GE_EN8 (0x1u << 8) /**< \brief (XDMAC_GE) XDMAC Channel 8 Enable Bit */ +#define XDMAC_GE_EN9 (0x1u << 9) /**< \brief (XDMAC_GE) XDMAC Channel 9 Enable Bit */ +#define XDMAC_GE_EN10 (0x1u << 10) /**< \brief (XDMAC_GE) XDMAC Channel 10 Enable Bit */ +#define XDMAC_GE_EN11 (0x1u << 11) /**< \brief (XDMAC_GE) XDMAC Channel 11 Enable Bit */ +#define XDMAC_GE_EN12 (0x1u << 12) /**< \brief (XDMAC_GE) XDMAC Channel 12 Enable Bit */ +#define XDMAC_GE_EN13 (0x1u << 13) /**< \brief (XDMAC_GE) XDMAC Channel 13 Enable Bit */ +#define XDMAC_GE_EN14 (0x1u << 14) /**< \brief (XDMAC_GE) XDMAC Channel 14 Enable Bit */ +#define XDMAC_GE_EN15 (0x1u << 15) /**< \brief (XDMAC_GE) XDMAC Channel 15 Enable Bit */ +#define XDMAC_GE_EN16 (0x1u << 16) /**< \brief (XDMAC_GE) XDMAC Channel 16 Enable Bit */ +#define XDMAC_GE_EN17 (0x1u << 17) /**< \brief (XDMAC_GE) XDMAC Channel 17 Enable Bit */ +#define XDMAC_GE_EN18 (0x1u << 18) /**< \brief (XDMAC_GE) XDMAC Channel 18 Enable Bit */ +#define XDMAC_GE_EN19 (0x1u << 19) /**< \brief (XDMAC_GE) XDMAC Channel 19 Enable Bit */ +#define XDMAC_GE_EN20 (0x1u << 20) /**< \brief (XDMAC_GE) XDMAC Channel 20 Enable Bit */ +#define XDMAC_GE_EN21 (0x1u << 21) /**< \brief (XDMAC_GE) XDMAC Channel 21 Enable Bit */ +#define XDMAC_GE_EN22 (0x1u << 22) /**< \brief (XDMAC_GE) XDMAC Channel 22 Enable Bit */ +#define XDMAC_GE_EN23 (0x1u << 23) /**< \brief (XDMAC_GE) XDMAC Channel 23 Enable Bit */ +/* -------- XDMAC_GD : (XDMAC Offset: 0x20) Global Channel Disable Register -------- */ +#define XDMAC_GD_DI0 (0x1u << 0) /**< \brief (XDMAC_GD) XDMAC Channel 0 Disable Bit */ +#define XDMAC_GD_DI1 (0x1u << 1) /**< \brief (XDMAC_GD) XDMAC Channel 1 Disable Bit */ +#define XDMAC_GD_DI2 (0x1u << 2) /**< \brief (XDMAC_GD) XDMAC Channel 2 Disable Bit */ +#define XDMAC_GD_DI3 (0x1u << 3) /**< \brief (XDMAC_GD) XDMAC Channel 3 Disable Bit */ +#define XDMAC_GD_DI4 (0x1u << 4) /**< \brief (XDMAC_GD) XDMAC Channel 4 Disable Bit */ +#define XDMAC_GD_DI5 (0x1u << 5) /**< \brief (XDMAC_GD) XDMAC Channel 5 Disable Bit */ +#define XDMAC_GD_DI6 (0x1u << 6) /**< \brief (XDMAC_GD) XDMAC Channel 6 Disable Bit */ +#define XDMAC_GD_DI7 (0x1u << 7) /**< \brief (XDMAC_GD) XDMAC Channel 7 Disable Bit */ +#define XDMAC_GD_DI8 (0x1u << 8) /**< \brief (XDMAC_GD) XDMAC Channel 8 Disable Bit */ +#define XDMAC_GD_DI9 (0x1u << 9) /**< \brief (XDMAC_GD) XDMAC Channel 9 Disable Bit */ +#define XDMAC_GD_DI10 (0x1u << 10) /**< \brief (XDMAC_GD) XDMAC Channel 10 Disable Bit */ +#define XDMAC_GD_DI11 (0x1u << 11) /**< \brief (XDMAC_GD) XDMAC Channel 11 Disable Bit */ +#define XDMAC_GD_DI12 (0x1u << 12) /**< \brief (XDMAC_GD) XDMAC Channel 12 Disable Bit */ +#define XDMAC_GD_DI13 (0x1u << 13) /**< \brief (XDMAC_GD) XDMAC Channel 13 Disable Bit */ +#define XDMAC_GD_DI14 (0x1u << 14) /**< \brief (XDMAC_GD) XDMAC Channel 14 Disable Bit */ +#define XDMAC_GD_DI15 (0x1u << 15) /**< \brief (XDMAC_GD) XDMAC Channel 15 Disable Bit */ +#define XDMAC_GD_DI16 (0x1u << 16) /**< \brief (XDMAC_GD) XDMAC Channel 16 Disable Bit */ +#define XDMAC_GD_DI17 (0x1u << 17) /**< \brief (XDMAC_GD) XDMAC Channel 17 Disable Bit */ +#define XDMAC_GD_DI18 (0x1u << 18) /**< \brief (XDMAC_GD) XDMAC Channel 18 Disable Bit */ +#define XDMAC_GD_DI19 (0x1u << 19) /**< \brief (XDMAC_GD) XDMAC Channel 19 Disable Bit */ +#define XDMAC_GD_DI20 (0x1u << 20) /**< \brief (XDMAC_GD) XDMAC Channel 20 Disable Bit */ +#define XDMAC_GD_DI21 (0x1u << 21) /**< \brief (XDMAC_GD) XDMAC Channel 21 Disable Bit */ +#define XDMAC_GD_DI22 (0x1u << 22) /**< \brief (XDMAC_GD) XDMAC Channel 22 Disable Bit */ +#define XDMAC_GD_DI23 (0x1u << 23) /**< \brief (XDMAC_GD) XDMAC Channel 23 Disable Bit */ +/* -------- XDMAC_GS : (XDMAC Offset: 0x24) Global Channel Status Register -------- */ +#define XDMAC_GS_ST0 (0x1u << 0) /**< \brief (XDMAC_GS) XDMAC Channel 0 Status Bit */ +#define XDMAC_GS_ST1 (0x1u << 1) /**< \brief (XDMAC_GS) XDMAC Channel 1 Status Bit */ +#define XDMAC_GS_ST2 (0x1u << 2) /**< \brief (XDMAC_GS) XDMAC Channel 2 Status Bit */ +#define XDMAC_GS_ST3 (0x1u << 3) /**< \brief (XDMAC_GS) XDMAC Channel 3 Status Bit */ +#define XDMAC_GS_ST4 (0x1u << 4) /**< \brief (XDMAC_GS) XDMAC Channel 4 Status Bit */ +#define XDMAC_GS_ST5 (0x1u << 5) /**< \brief (XDMAC_GS) XDMAC Channel 5 Status Bit */ +#define XDMAC_GS_ST6 (0x1u << 6) /**< \brief (XDMAC_GS) XDMAC Channel 6 Status Bit */ +#define XDMAC_GS_ST7 (0x1u << 7) /**< \brief (XDMAC_GS) XDMAC Channel 7 Status Bit */ +#define XDMAC_GS_ST8 (0x1u << 8) /**< \brief (XDMAC_GS) XDMAC Channel 8 Status Bit */ +#define XDMAC_GS_ST9 (0x1u << 9) /**< \brief (XDMAC_GS) XDMAC Channel 9 Status Bit */ +#define XDMAC_GS_ST10 (0x1u << 10) /**< \brief (XDMAC_GS) XDMAC Channel 10 Status Bit */ +#define XDMAC_GS_ST11 (0x1u << 11) /**< \brief (XDMAC_GS) XDMAC Channel 11 Status Bit */ +#define XDMAC_GS_ST12 (0x1u << 12) /**< \brief (XDMAC_GS) XDMAC Channel 12 Status Bit */ +#define XDMAC_GS_ST13 (0x1u << 13) /**< \brief (XDMAC_GS) XDMAC Channel 13 Status Bit */ +#define XDMAC_GS_ST14 (0x1u << 14) /**< \brief (XDMAC_GS) XDMAC Channel 14 Status Bit */ +#define XDMAC_GS_ST15 (0x1u << 15) /**< \brief (XDMAC_GS) XDMAC Channel 15 Status Bit */ +#define XDMAC_GS_ST16 (0x1u << 16) /**< \brief (XDMAC_GS) XDMAC Channel 16 Status Bit */ +#define XDMAC_GS_ST17 (0x1u << 17) /**< \brief (XDMAC_GS) XDMAC Channel 17 Status Bit */ +#define XDMAC_GS_ST18 (0x1u << 18) /**< \brief (XDMAC_GS) XDMAC Channel 18 Status Bit */ +#define XDMAC_GS_ST19 (0x1u << 19) /**< \brief (XDMAC_GS) XDMAC Channel 19 Status Bit */ +#define XDMAC_GS_ST20 (0x1u << 20) /**< \brief (XDMAC_GS) XDMAC Channel 20 Status Bit */ +#define XDMAC_GS_ST21 (0x1u << 21) /**< \brief (XDMAC_GS) XDMAC Channel 21 Status Bit */ +#define XDMAC_GS_ST22 (0x1u << 22) /**< \brief (XDMAC_GS) XDMAC Channel 22 Status Bit */ +#define XDMAC_GS_ST23 (0x1u << 23) /**< \brief (XDMAC_GS) XDMAC Channel 23 Status Bit */ +/* -------- XDMAC_GRS : (XDMAC Offset: 0x28) Global Channel Read Suspend Register -------- */ +#define XDMAC_GRS_RS0 (0x1u << 0) /**< \brief (XDMAC_GRS) XDMAC Channel 0 Read Suspend Bit */ +#define XDMAC_GRS_RS1 (0x1u << 1) /**< \brief (XDMAC_GRS) XDMAC Channel 1 Read Suspend Bit */ +#define XDMAC_GRS_RS2 (0x1u << 2) /**< \brief (XDMAC_GRS) XDMAC Channel 2 Read Suspend Bit */ +#define XDMAC_GRS_RS3 (0x1u << 3) /**< \brief (XDMAC_GRS) XDMAC Channel 3 Read Suspend Bit */ +#define XDMAC_GRS_RS4 (0x1u << 4) /**< \brief (XDMAC_GRS) XDMAC Channel 4 Read Suspend Bit */ +#define XDMAC_GRS_RS5 (0x1u << 5) /**< \brief (XDMAC_GRS) XDMAC Channel 5 Read Suspend Bit */ +#define XDMAC_GRS_RS6 (0x1u << 6) /**< \brief (XDMAC_GRS) XDMAC Channel 6 Read Suspend Bit */ +#define XDMAC_GRS_RS7 (0x1u << 7) /**< \brief (XDMAC_GRS) XDMAC Channel 7 Read Suspend Bit */ +#define XDMAC_GRS_RS8 (0x1u << 8) /**< \brief (XDMAC_GRS) XDMAC Channel 8 Read Suspend Bit */ +#define XDMAC_GRS_RS9 (0x1u << 9) /**< \brief (XDMAC_GRS) XDMAC Channel 9 Read Suspend Bit */ +#define XDMAC_GRS_RS10 (0x1u << 10) /**< \brief (XDMAC_GRS) XDMAC Channel 10 Read Suspend Bit */ +#define XDMAC_GRS_RS11 (0x1u << 11) /**< \brief (XDMAC_GRS) XDMAC Channel 11 Read Suspend Bit */ +#define XDMAC_GRS_RS12 (0x1u << 12) /**< \brief (XDMAC_GRS) XDMAC Channel 12 Read Suspend Bit */ +#define XDMAC_GRS_RS13 (0x1u << 13) /**< \brief (XDMAC_GRS) XDMAC Channel 13 Read Suspend Bit */ +#define XDMAC_GRS_RS14 (0x1u << 14) /**< \brief (XDMAC_GRS) XDMAC Channel 14 Read Suspend Bit */ +#define XDMAC_GRS_RS15 (0x1u << 15) /**< \brief (XDMAC_GRS) XDMAC Channel 15 Read Suspend Bit */ +#define XDMAC_GRS_RS16 (0x1u << 16) /**< \brief (XDMAC_GRS) XDMAC Channel 16 Read Suspend Bit */ +#define XDMAC_GRS_RS17 (0x1u << 17) /**< \brief (XDMAC_GRS) XDMAC Channel 17 Read Suspend Bit */ +#define XDMAC_GRS_RS18 (0x1u << 18) /**< \brief (XDMAC_GRS) XDMAC Channel 18 Read Suspend Bit */ +#define XDMAC_GRS_RS19 (0x1u << 19) /**< \brief (XDMAC_GRS) XDMAC Channel 19 Read Suspend Bit */ +#define XDMAC_GRS_RS20 (0x1u << 20) /**< \brief (XDMAC_GRS) XDMAC Channel 20 Read Suspend Bit */ +#define XDMAC_GRS_RS21 (0x1u << 21) /**< \brief (XDMAC_GRS) XDMAC Channel 21 Read Suspend Bit */ +#define XDMAC_GRS_RS22 (0x1u << 22) /**< \brief (XDMAC_GRS) XDMAC Channel 22 Read Suspend Bit */ +#define XDMAC_GRS_RS23 (0x1u << 23) /**< \brief (XDMAC_GRS) XDMAC Channel 23 Read Suspend Bit */ +/* -------- XDMAC_GWS : (XDMAC Offset: 0x2C) Global Channel Write Suspend Register -------- */ +#define XDMAC_GWS_WS0 (0x1u << 0) /**< \brief (XDMAC_GWS) XDMAC Channel 0 Write Suspend Bit */ +#define XDMAC_GWS_WS1 (0x1u << 1) /**< \brief (XDMAC_GWS) XDMAC Channel 1 Write Suspend Bit */ +#define XDMAC_GWS_WS2 (0x1u << 2) /**< \brief (XDMAC_GWS) XDMAC Channel 2 Write Suspend Bit */ +#define XDMAC_GWS_WS3 (0x1u << 3) /**< \brief (XDMAC_GWS) XDMAC Channel 3 Write Suspend Bit */ +#define XDMAC_GWS_WS4 (0x1u << 4) /**< \brief (XDMAC_GWS) XDMAC Channel 4 Write Suspend Bit */ +#define XDMAC_GWS_WS5 (0x1u << 5) /**< \brief (XDMAC_GWS) XDMAC Channel 5 Write Suspend Bit */ +#define XDMAC_GWS_WS6 (0x1u << 6) /**< \brief (XDMAC_GWS) XDMAC Channel 6 Write Suspend Bit */ +#define XDMAC_GWS_WS7 (0x1u << 7) /**< \brief (XDMAC_GWS) XDMAC Channel 7 Write Suspend Bit */ +#define XDMAC_GWS_WS8 (0x1u << 8) /**< \brief (XDMAC_GWS) XDMAC Channel 8 Write Suspend Bit */ +#define XDMAC_GWS_WS9 (0x1u << 9) /**< \brief (XDMAC_GWS) XDMAC Channel 9 Write Suspend Bit */ +#define XDMAC_GWS_WS10 (0x1u << 10) /**< \brief (XDMAC_GWS) XDMAC Channel 10 Write Suspend Bit */ +#define XDMAC_GWS_WS11 (0x1u << 11) /**< \brief (XDMAC_GWS) XDMAC Channel 11 Write Suspend Bit */ +#define XDMAC_GWS_WS12 (0x1u << 12) /**< \brief (XDMAC_GWS) XDMAC Channel 12 Write Suspend Bit */ +#define XDMAC_GWS_WS13 (0x1u << 13) /**< \brief (XDMAC_GWS) XDMAC Channel 13 Write Suspend Bit */ +#define XDMAC_GWS_WS14 (0x1u << 14) /**< \brief (XDMAC_GWS) XDMAC Channel 14 Write Suspend Bit */ +#define XDMAC_GWS_WS15 (0x1u << 15) /**< \brief (XDMAC_GWS) XDMAC Channel 15 Write Suspend Bit */ +#define XDMAC_GWS_WS16 (0x1u << 16) /**< \brief (XDMAC_GWS) XDMAC Channel 16 Write Suspend Bit */ +#define XDMAC_GWS_WS17 (0x1u << 17) /**< \brief (XDMAC_GWS) XDMAC Channel 17 Write Suspend Bit */ +#define XDMAC_GWS_WS18 (0x1u << 18) /**< \brief (XDMAC_GWS) XDMAC Channel 18 Write Suspend Bit */ +#define XDMAC_GWS_WS19 (0x1u << 19) /**< \brief (XDMAC_GWS) XDMAC Channel 19 Write Suspend Bit */ +#define XDMAC_GWS_WS20 (0x1u << 20) /**< \brief (XDMAC_GWS) XDMAC Channel 20 Write Suspend Bit */ +#define XDMAC_GWS_WS21 (0x1u << 21) /**< \brief (XDMAC_GWS) XDMAC Channel 21 Write Suspend Bit */ +#define XDMAC_GWS_WS22 (0x1u << 22) /**< \brief (XDMAC_GWS) XDMAC Channel 22 Write Suspend Bit */ +#define XDMAC_GWS_WS23 (0x1u << 23) /**< \brief (XDMAC_GWS) XDMAC Channel 23 Write Suspend Bit */ +/* -------- XDMAC_GRWS : (XDMAC Offset: 0x30) Global Channel Read Write Suspend Register -------- */ +#define XDMAC_GRWS_RWS0 (0x1u << 0) /**< \brief (XDMAC_GRWS) XDMAC Channel 0 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS1 (0x1u << 1) /**< \brief (XDMAC_GRWS) XDMAC Channel 1 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS2 (0x1u << 2) /**< \brief (XDMAC_GRWS) XDMAC Channel 2 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS3 (0x1u << 3) /**< \brief (XDMAC_GRWS) XDMAC Channel 3 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS4 (0x1u << 4) /**< \brief (XDMAC_GRWS) XDMAC Channel 4 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS5 (0x1u << 5) /**< \brief (XDMAC_GRWS) XDMAC Channel 5 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS6 (0x1u << 6) /**< \brief (XDMAC_GRWS) XDMAC Channel 6 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS7 (0x1u << 7) /**< \brief (XDMAC_GRWS) XDMAC Channel 7 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS8 (0x1u << 8) /**< \brief (XDMAC_GRWS) XDMAC Channel 8 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS9 (0x1u << 9) /**< \brief (XDMAC_GRWS) XDMAC Channel 9 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS10 (0x1u << 10) /**< \brief (XDMAC_GRWS) XDMAC Channel 10 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS11 (0x1u << 11) /**< \brief (XDMAC_GRWS) XDMAC Channel 11 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS12 (0x1u << 12) /**< \brief (XDMAC_GRWS) XDMAC Channel 12 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS13 (0x1u << 13) /**< \brief (XDMAC_GRWS) XDMAC Channel 13 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS14 (0x1u << 14) /**< \brief (XDMAC_GRWS) XDMAC Channel 14 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS15 (0x1u << 15) /**< \brief (XDMAC_GRWS) XDMAC Channel 15 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS16 (0x1u << 16) /**< \brief (XDMAC_GRWS) XDMAC Channel 16 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS17 (0x1u << 17) /**< \brief (XDMAC_GRWS) XDMAC Channel 17 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS18 (0x1u << 18) /**< \brief (XDMAC_GRWS) XDMAC Channel 18 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS19 (0x1u << 19) /**< \brief (XDMAC_GRWS) XDMAC Channel 19 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS20 (0x1u << 20) /**< \brief (XDMAC_GRWS) XDMAC Channel 20 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS21 (0x1u << 21) /**< \brief (XDMAC_GRWS) XDMAC Channel 21 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS22 (0x1u << 22) /**< \brief (XDMAC_GRWS) XDMAC Channel 22 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS23 (0x1u << 23) /**< \brief (XDMAC_GRWS) XDMAC Channel 23 Read Write Suspend Bit */ +/* -------- XDMAC_GRWR : (XDMAC Offset: 0x34) Global Channel Read Write Resume Register -------- */ +#define XDMAC_GRWR_RWR0 (0x1u << 0) /**< \brief (XDMAC_GRWR) XDMAC Channel 0 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR1 (0x1u << 1) /**< \brief (XDMAC_GRWR) XDMAC Channel 1 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR2 (0x1u << 2) /**< \brief (XDMAC_GRWR) XDMAC Channel 2 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR3 (0x1u << 3) /**< \brief (XDMAC_GRWR) XDMAC Channel 3 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR4 (0x1u << 4) /**< \brief (XDMAC_GRWR) XDMAC Channel 4 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR5 (0x1u << 5) /**< \brief (XDMAC_GRWR) XDMAC Channel 5 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR6 (0x1u << 6) /**< \brief (XDMAC_GRWR) XDMAC Channel 6 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR7 (0x1u << 7) /**< \brief (XDMAC_GRWR) XDMAC Channel 7 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR8 (0x1u << 8) /**< \brief (XDMAC_GRWR) XDMAC Channel 8 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR9 (0x1u << 9) /**< \brief (XDMAC_GRWR) XDMAC Channel 9 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR10 (0x1u << 10) /**< \brief (XDMAC_GRWR) XDMAC Channel 10 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR11 (0x1u << 11) /**< \brief (XDMAC_GRWR) XDMAC Channel 11 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR12 (0x1u << 12) /**< \brief (XDMAC_GRWR) XDMAC Channel 12 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR13 (0x1u << 13) /**< \brief (XDMAC_GRWR) XDMAC Channel 13 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR14 (0x1u << 14) /**< \brief (XDMAC_GRWR) XDMAC Channel 14 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR15 (0x1u << 15) /**< \brief (XDMAC_GRWR) XDMAC Channel 15 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR16 (0x1u << 16) /**< \brief (XDMAC_GRWR) XDMAC Channel 16 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR17 (0x1u << 17) /**< \brief (XDMAC_GRWR) XDMAC Channel 17 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR18 (0x1u << 18) /**< \brief (XDMAC_GRWR) XDMAC Channel 18 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR19 (0x1u << 19) /**< \brief (XDMAC_GRWR) XDMAC Channel 19 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR20 (0x1u << 20) /**< \brief (XDMAC_GRWR) XDMAC Channel 20 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR21 (0x1u << 21) /**< \brief (XDMAC_GRWR) XDMAC Channel 21 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR22 (0x1u << 22) /**< \brief (XDMAC_GRWR) XDMAC Channel 22 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR23 (0x1u << 23) /**< \brief (XDMAC_GRWR) XDMAC Channel 23 Read Write Resume Bit */ +/* -------- XDMAC_GSWR : (XDMAC Offset: 0x38) Global Channel Software Request Register -------- */ +#define XDMAC_GSWR_SWREQ0 (0x1u << 0) /**< \brief (XDMAC_GSWR) XDMAC Channel 0 Software Request Bit */ +#define XDMAC_GSWR_SWREQ1 (0x1u << 1) /**< \brief (XDMAC_GSWR) XDMAC Channel 1 Software Request Bit */ +#define XDMAC_GSWR_SWREQ2 (0x1u << 2) /**< \brief (XDMAC_GSWR) XDMAC Channel 2 Software Request Bit */ +#define XDMAC_GSWR_SWREQ3 (0x1u << 3) /**< \brief (XDMAC_GSWR) XDMAC Channel 3 Software Request Bit */ +#define XDMAC_GSWR_SWREQ4 (0x1u << 4) /**< \brief (XDMAC_GSWR) XDMAC Channel 4 Software Request Bit */ +#define XDMAC_GSWR_SWREQ5 (0x1u << 5) /**< \brief (XDMAC_GSWR) XDMAC Channel 5 Software Request Bit */ +#define XDMAC_GSWR_SWREQ6 (0x1u << 6) /**< \brief (XDMAC_GSWR) XDMAC Channel 6 Software Request Bit */ +#define XDMAC_GSWR_SWREQ7 (0x1u << 7) /**< \brief (XDMAC_GSWR) XDMAC Channel 7 Software Request Bit */ +#define XDMAC_GSWR_SWREQ8 (0x1u << 8) /**< \brief (XDMAC_GSWR) XDMAC Channel 8 Software Request Bit */ +#define XDMAC_GSWR_SWREQ9 (0x1u << 9) /**< \brief (XDMAC_GSWR) XDMAC Channel 9 Software Request Bit */ +#define XDMAC_GSWR_SWREQ10 (0x1u << 10) /**< \brief (XDMAC_GSWR) XDMAC Channel 10 Software Request Bit */ +#define XDMAC_GSWR_SWREQ11 (0x1u << 11) /**< \brief (XDMAC_GSWR) XDMAC Channel 11 Software Request Bit */ +#define XDMAC_GSWR_SWREQ12 (0x1u << 12) /**< \brief (XDMAC_GSWR) XDMAC Channel 12 Software Request Bit */ +#define XDMAC_GSWR_SWREQ13 (0x1u << 13) /**< \brief (XDMAC_GSWR) XDMAC Channel 13 Software Request Bit */ +#define XDMAC_GSWR_SWREQ14 (0x1u << 14) /**< \brief (XDMAC_GSWR) XDMAC Channel 14 Software Request Bit */ +#define XDMAC_GSWR_SWREQ15 (0x1u << 15) /**< \brief (XDMAC_GSWR) XDMAC Channel 15 Software Request Bit */ +#define XDMAC_GSWR_SWREQ16 (0x1u << 16) /**< \brief (XDMAC_GSWR) XDMAC Channel 16 Software Request Bit */ +#define XDMAC_GSWR_SWREQ17 (0x1u << 17) /**< \brief (XDMAC_GSWR) XDMAC Channel 17 Software Request Bit */ +#define XDMAC_GSWR_SWREQ18 (0x1u << 18) /**< \brief (XDMAC_GSWR) XDMAC Channel 18 Software Request Bit */ +#define XDMAC_GSWR_SWREQ19 (0x1u << 19) /**< \brief (XDMAC_GSWR) XDMAC Channel 19 Software Request Bit */ +#define XDMAC_GSWR_SWREQ20 (0x1u << 20) /**< \brief (XDMAC_GSWR) XDMAC Channel 20 Software Request Bit */ +#define XDMAC_GSWR_SWREQ21 (0x1u << 21) /**< \brief (XDMAC_GSWR) XDMAC Channel 21 Software Request Bit */ +#define XDMAC_GSWR_SWREQ22 (0x1u << 22) /**< \brief (XDMAC_GSWR) XDMAC Channel 22 Software Request Bit */ +#define XDMAC_GSWR_SWREQ23 (0x1u << 23) /**< \brief (XDMAC_GSWR) XDMAC Channel 23 Software Request Bit */ +/* -------- XDMAC_GSWS : (XDMAC Offset: 0x3C) Global Channel Software Request Status Register -------- */ +#define XDMAC_GSWS_SWRS0 (0x1u << 0) /**< \brief (XDMAC_GSWS) XDMAC Channel 0 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS1 (0x1u << 1) /**< \brief (XDMAC_GSWS) XDMAC Channel 1 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS2 (0x1u << 2) /**< \brief (XDMAC_GSWS) XDMAC Channel 2 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS3 (0x1u << 3) /**< \brief (XDMAC_GSWS) XDMAC Channel 3 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS4 (0x1u << 4) /**< \brief (XDMAC_GSWS) XDMAC Channel 4 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS5 (0x1u << 5) /**< \brief (XDMAC_GSWS) XDMAC Channel 5 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS6 (0x1u << 6) /**< \brief (XDMAC_GSWS) XDMAC Channel 6 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS7 (0x1u << 7) /**< \brief (XDMAC_GSWS) XDMAC Channel 7 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS8 (0x1u << 8) /**< \brief (XDMAC_GSWS) XDMAC Channel 8 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS9 (0x1u << 9) /**< \brief (XDMAC_GSWS) XDMAC Channel 9 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS10 (0x1u << 10) /**< \brief (XDMAC_GSWS) XDMAC Channel 10 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS11 (0x1u << 11) /**< \brief (XDMAC_GSWS) XDMAC Channel 11 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS12 (0x1u << 12) /**< \brief (XDMAC_GSWS) XDMAC Channel 12 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS13 (0x1u << 13) /**< \brief (XDMAC_GSWS) XDMAC Channel 13 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS14 (0x1u << 14) /**< \brief (XDMAC_GSWS) XDMAC Channel 14 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS15 (0x1u << 15) /**< \brief (XDMAC_GSWS) XDMAC Channel 15 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS16 (0x1u << 16) /**< \brief (XDMAC_GSWS) XDMAC Channel 16 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS17 (0x1u << 17) /**< \brief (XDMAC_GSWS) XDMAC Channel 17 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS18 (0x1u << 18) /**< \brief (XDMAC_GSWS) XDMAC Channel 18 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS19 (0x1u << 19) /**< \brief (XDMAC_GSWS) XDMAC Channel 19 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS20 (0x1u << 20) /**< \brief (XDMAC_GSWS) XDMAC Channel 20 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS21 (0x1u << 21) /**< \brief (XDMAC_GSWS) XDMAC Channel 21 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS22 (0x1u << 22) /**< \brief (XDMAC_GSWS) XDMAC Channel 22 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS23 (0x1u << 23) /**< \brief (XDMAC_GSWS) XDMAC Channel 23 Software Request Status Bit */ +/* -------- XDMAC_GSWF : (XDMAC Offset: 0x40) Global Channel Software Flush Request Register -------- */ +#define XDMAC_GSWF_SWF0 (0x1u << 0) /**< \brief (XDMAC_GSWF) XDMAC Channel 0 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF1 (0x1u << 1) /**< \brief (XDMAC_GSWF) XDMAC Channel 1 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF2 (0x1u << 2) /**< \brief (XDMAC_GSWF) XDMAC Channel 2 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF3 (0x1u << 3) /**< \brief (XDMAC_GSWF) XDMAC Channel 3 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF4 (0x1u << 4) /**< \brief (XDMAC_GSWF) XDMAC Channel 4 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF5 (0x1u << 5) /**< \brief (XDMAC_GSWF) XDMAC Channel 5 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF6 (0x1u << 6) /**< \brief (XDMAC_GSWF) XDMAC Channel 6 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF7 (0x1u << 7) /**< \brief (XDMAC_GSWF) XDMAC Channel 7 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF8 (0x1u << 8) /**< \brief (XDMAC_GSWF) XDMAC Channel 8 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF9 (0x1u << 9) /**< \brief (XDMAC_GSWF) XDMAC Channel 9 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF10 (0x1u << 10) /**< \brief (XDMAC_GSWF) XDMAC Channel 10 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF11 (0x1u << 11) /**< \brief (XDMAC_GSWF) XDMAC Channel 11 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF12 (0x1u << 12) /**< \brief (XDMAC_GSWF) XDMAC Channel 12 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF13 (0x1u << 13) /**< \brief (XDMAC_GSWF) XDMAC Channel 13 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF14 (0x1u << 14) /**< \brief (XDMAC_GSWF) XDMAC Channel 14 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF15 (0x1u << 15) /**< \brief (XDMAC_GSWF) XDMAC Channel 15 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF16 (0x1u << 16) /**< \brief (XDMAC_GSWF) XDMAC Channel 16 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF17 (0x1u << 17) /**< \brief (XDMAC_GSWF) XDMAC Channel 17 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF18 (0x1u << 18) /**< \brief (XDMAC_GSWF) XDMAC Channel 18 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF19 (0x1u << 19) /**< \brief (XDMAC_GSWF) XDMAC Channel 19 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF20 (0x1u << 20) /**< \brief (XDMAC_GSWF) XDMAC Channel 20 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF21 (0x1u << 21) /**< \brief (XDMAC_GSWF) XDMAC Channel 21 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF22 (0x1u << 22) /**< \brief (XDMAC_GSWF) XDMAC Channel 22 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF23 (0x1u << 23) /**< \brief (XDMAC_GSWF) XDMAC Channel 23 Software Flush Request Bit */ +/* -------- XDMAC_CIE : (XDMAC Offset: N/A) Channel Interrupt Enable Register -------- */ +#define XDMAC_CIE_BIE (0x1u << 0) /**< \brief (XDMAC_CIE) End of Block Interrupt Enable Bit */ +#define XDMAC_CIE_LIE (0x1u << 1) /**< \brief (XDMAC_CIE) End of Linked List Interrupt Enable Bit */ +#define XDMAC_CIE_DIE (0x1u << 2) /**< \brief (XDMAC_CIE) End of Disable Interrupt Enable Bit */ +#define XDMAC_CIE_FIE (0x1u << 3) /**< \brief (XDMAC_CIE) End of Flush Interrupt Enable Bit */ +#define XDMAC_CIE_RBIE (0x1u << 4) /**< \brief (XDMAC_CIE) Read Bus Error Interrupt Enable Bit */ +#define XDMAC_CIE_WBIE (0x1u << 5) /**< \brief (XDMAC_CIE) Write Bus Error Interrupt Enable Bit */ +#define XDMAC_CIE_ROIE (0x1u << 6) /**< \brief (XDMAC_CIE) Request Overflow Error Interrupt Enable Bit */ +/* -------- XDMAC_CID : (XDMAC Offset: N/A) Channel Interrupt Disable Register -------- */ +#define XDMAC_CID_BID (0x1u << 0) /**< \brief (XDMAC_CID) End of Block Interrupt Disable Bit */ +#define XDMAC_CID_LID (0x1u << 1) /**< \brief (XDMAC_CID) End of Linked List Interrupt Disable Bit */ +#define XDMAC_CID_DID (0x1u << 2) /**< \brief (XDMAC_CID) End of Disable Interrupt Disable Bit */ +#define XDMAC_CID_FID (0x1u << 3) /**< \brief (XDMAC_CID) End of Flush Interrupt Disable Bit */ +#define XDMAC_CID_RBEID (0x1u << 4) /**< \brief (XDMAC_CID) Read Bus Error Interrupt Disable Bit */ +#define XDMAC_CID_WBEID (0x1u << 5) /**< \brief (XDMAC_CID) Write Bus Error Interrupt Disable Bit */ +#define XDMAC_CID_ROID (0x1u << 6) /**< \brief (XDMAC_CID) Request Overflow Error Interrupt Disable Bit */ +/* -------- XDMAC_CIM : (XDMAC Offset: N/A) Channel Interrupt Mask Register -------- */ +#define XDMAC_CIM_BIM (0x1u << 0) /**< \brief (XDMAC_CIM) End of Block Interrupt Mask Bit */ +#define XDMAC_CIM_LIM (0x1u << 1) /**< \brief (XDMAC_CIM) End of Linked List Interrupt Mask Bit */ +#define XDMAC_CIM_DIM (0x1u << 2) /**< \brief (XDMAC_CIM) End of Disable Interrupt Mask Bit */ +#define XDMAC_CIM_FIM (0x1u << 3) /**< \brief (XDMAC_CIM) End of Flush Interrupt Mask Bit */ +#define XDMAC_CIM_RBEIM (0x1u << 4) /**< \brief (XDMAC_CIM) Read Bus Error Interrupt Mask Bit */ +#define XDMAC_CIM_WBEIM (0x1u << 5) /**< \brief (XDMAC_CIM) Write Bus Error Interrupt Mask Bit */ +#define XDMAC_CIM_ROIM (0x1u << 6) /**< \brief (XDMAC_CIM) Request Overflow Error Interrupt Mask Bit */ +/* -------- XDMAC_CIS : (XDMAC Offset: N/A) Channel Interrupt Status Register -------- */ +#define XDMAC_CIS_BIS (0x1u << 0) /**< \brief (XDMAC_CIS) End of Block Interrupt Status Bit */ +#define XDMAC_CIS_LIS (0x1u << 1) /**< \brief (XDMAC_CIS) End of Linked List Interrupt Status Bit */ +#define XDMAC_CIS_DIS (0x1u << 2) /**< \brief (XDMAC_CIS) End of Disable Interrupt Status Bit */ +#define XDMAC_CIS_FIS (0x1u << 3) /**< \brief (XDMAC_CIS) End of Flush Interrupt Status Bit */ +#define XDMAC_CIS_RBEIS (0x1u << 4) /**< \brief (XDMAC_CIS) Read Bus Error Interrupt Status Bit */ +#define XDMAC_CIS_WBEIS (0x1u << 5) /**< \brief (XDMAC_CIS) Write Bus Error Interrupt Status Bit */ +#define XDMAC_CIS_ROIS (0x1u << 6) /**< \brief (XDMAC_CIS) Request Overflow Error Interrupt Status Bit */ +/* -------- XDMAC_CSA : (XDMAC Offset: N/A) Channel Source Address Register -------- */ +#define XDMAC_CSA_SA_Pos 0 +#define XDMAC_CSA_SA_Msk (0xffffffffu << XDMAC_CSA_SA_Pos) /**< \brief (XDMAC_CSA) Channel x Source Address */ +#define XDMAC_CSA_SA(value) ((XDMAC_CSA_SA_Msk & ((value) << XDMAC_CSA_SA_Pos))) +/* -------- XDMAC_CDA : (XDMAC Offset: N/A) Channel Destination Address Register -------- */ +#define XDMAC_CDA_DA_Pos 0 +#define XDMAC_CDA_DA_Msk (0xffffffffu << XDMAC_CDA_DA_Pos) /**< \brief (XDMAC_CDA) Channel x Destination Address */ +#define XDMAC_CDA_DA(value) ((XDMAC_CDA_DA_Msk & ((value) << XDMAC_CDA_DA_Pos))) +/* -------- XDMAC_CNDA : (XDMAC Offset: N/A) Channel Next Descriptor Address Register -------- */ +#define XDMAC_CNDA_NDAIF (0x1u << 0) /**< \brief (XDMAC_CNDA) Channel x Next Descriptor Interface */ +#define XDMAC_CNDA_NDA_Pos 2 +#define XDMAC_CNDA_NDA_Msk (0x3fffffffu << XDMAC_CNDA_NDA_Pos) /**< \brief (XDMAC_CNDA) Channel x Next Descriptor Address */ +#define XDMAC_CNDA_NDA(value) ((XDMAC_CNDA_NDA_Msk & ((value) << XDMAC_CNDA_NDA_Pos))) +/* -------- XDMAC_CNDC : (XDMAC Offset: N/A) Channel Next Descriptor Control Register -------- */ +#define XDMAC_CNDC_NDE (0x1u << 0) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Enable */ +#define XDMAC_CNDC_NDE_DSCR_FETCH_DIS (0x0u << 0) /**< \brief (XDMAC_CNDC) Descriptor fetch is disabled */ +#define XDMAC_CNDC_NDE_DSCR_FETCH_EN (0x1u << 0) /**< \brief (XDMAC_CNDC) Descriptor fetch is enabled */ +#define XDMAC_CNDC_NDSUP (0x1u << 1) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Source Update */ +#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UNCHANGED (0x0u << 1) /**< \brief (XDMAC_CNDC) Source parameters remain unchanged. */ +#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED (0x1u << 1) /**< \brief (XDMAC_CNDC) Source parameters are updated when the descriptor is retrieved. */ +#define XDMAC_CNDC_NDDUP (0x1u << 2) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Destination Update */ +#define XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED (0x0u << 2) /**< \brief (XDMAC_CNDC) Destination parameters remain unchanged. */ +#define XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED (0x1u << 2) /**< \brief (XDMAC_CNDC) Destination parameters are updated when the descriptor is retrieved. */ +#define XDMAC_CNDC_NDVIEW_Pos 3 +#define XDMAC_CNDC_NDVIEW_Msk (0x3u << XDMAC_CNDC_NDVIEW_Pos) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor View */ +#define XDMAC_CNDC_NDVIEW(value) ((XDMAC_CNDC_NDVIEW_Msk & ((value) << XDMAC_CNDC_NDVIEW_Pos))) +#define XDMAC_CNDC_NDVIEW_NDV0 (0x0u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 0 */ +#define XDMAC_CNDC_NDVIEW_NDV1 (0x1u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 1 */ +#define XDMAC_CNDC_NDVIEW_NDV2 (0x2u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 2 */ +#define XDMAC_CNDC_NDVIEW_NDV3 (0x3u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 3 */ +/* -------- XDMAC_CUBC : (XDMAC Offset: N/A) Channel Microblock Control Register -------- */ +#define XDMAC_CUBC_UBLEN_Pos 0 +#define XDMAC_CUBC_UBLEN_Msk (0xffffffu << XDMAC_CUBC_UBLEN_Pos) /**< \brief (XDMAC_CUBC) Channel x Microblock Length */ +#define XDMAC_CUBC_UBLEN(value) ((XDMAC_CUBC_UBLEN_Msk & ((value) << XDMAC_CUBC_UBLEN_Pos))) +/* -------- XDMAC_CBC : (XDMAC Offset: N/A) Channel Block Control Register -------- */ +#define XDMAC_CBC_BLEN_Pos 0 +#define XDMAC_CBC_BLEN_Msk (0xfffu << XDMAC_CBC_BLEN_Pos) /**< \brief (XDMAC_CBC) Channel x Block Length */ +#define XDMAC_CBC_BLEN(value) ((XDMAC_CBC_BLEN_Msk & ((value) << XDMAC_CBC_BLEN_Pos))) +/* -------- XDMAC_CC : (XDMAC Offset: N/A) Channel Configuration Register -------- */ +#define XDMAC_CC_TYPE (0x1u << 0) /**< \brief (XDMAC_CC) Channel x Transfer Type */ +#define XDMAC_CC_TYPE_MEM_TRAN (0x0u << 0) /**< \brief (XDMAC_CC) Self triggered mode (Memory to Memory Transfer). */ +#define XDMAC_CC_TYPE_PER_TRAN (0x1u << 0) /**< \brief (XDMAC_CC) Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). */ +#define XDMAC_CC_MBSIZE_Pos 1 +#define XDMAC_CC_MBSIZE_Msk (0x3u << XDMAC_CC_MBSIZE_Pos) /**< \brief (XDMAC_CC) Channel x Memory Burst Size */ +#define XDMAC_CC_MBSIZE(value) ((XDMAC_CC_MBSIZE_Msk & ((value) << XDMAC_CC_MBSIZE_Pos))) +#define XDMAC_CC_MBSIZE_SINGLE (0x0u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to one. */ +#define XDMAC_CC_MBSIZE_FOUR (0x1u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to four. */ +#define XDMAC_CC_MBSIZE_EIGHT (0x2u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to eight. */ +#define XDMAC_CC_MBSIZE_SIXTEEN (0x3u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to sixteen. */ +#define XDMAC_CC_DSYNC (0x1u << 4) /**< \brief (XDMAC_CC) Channel x Synchronization */ +#define XDMAC_CC_DSYNC_PER2MEM (0x0u << 4) /**< \brief (XDMAC_CC) Peripheral to Memory transfer */ +#define XDMAC_CC_DSYNC_MEM2PER (0x1u << 4) /**< \brief (XDMAC_CC) Memory to Peripheral transfer */ +#define XDMAC_CC_PROT (0x1u << 5) /**< \brief (XDMAC_CC) Channel x Protection */ +#define XDMAC_CC_PROT_SEC (0x0u << 5) /**< \brief (XDMAC_CC) Channel is secured */ +#define XDMAC_CC_PROT_UNSEC (0x1u << 5) /**< \brief (XDMAC_CC) Channel is unsecured */ +#define XDMAC_CC_SWREQ (0x1u << 6) /**< \brief (XDMAC_CC) Channel x Software Request Trigger */ +#define XDMAC_CC_SWREQ_HWR_CONNECTED (0x0u << 6) /**< \brief (XDMAC_CC) Hardware request line is connected to the peripheral request line. */ +#define XDMAC_CC_SWREQ_SWR_CONNECTED (0x1u << 6) /**< \brief (XDMAC_CC) Software request is connected to the peripheral request line. */ +#define XDMAC_CC_MEMSET (0x1u << 7) /**< \brief (XDMAC_CC) Channel x Fill Block of memory */ +#define XDMAC_CC_MEMSET_NORMAL_MODE (0x0u << 7) /**< \brief (XDMAC_CC) Memset is not activated */ +#define XDMAC_CC_MEMSET_HW_MODE (0x1u << 7) /**< \brief (XDMAC_CC) Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. */ +#define XDMAC_CC_CSIZE_Pos 8 +#define XDMAC_CC_CSIZE_Msk (0x7u << XDMAC_CC_CSIZE_Pos) /**< \brief (XDMAC_CC) Channel x Chunk Size */ +#define XDMAC_CC_CSIZE(value) ((XDMAC_CC_CSIZE_Msk & ((value) << XDMAC_CC_CSIZE_Pos))) +#define XDMAC_CC_CSIZE_CHK_1 (0x0u << 8) /**< \brief (XDMAC_CC) 1 data transferred */ +#define XDMAC_CC_CSIZE_CHK_2 (0x1u << 8) /**< \brief (XDMAC_CC) 2 data transferred */ +#define XDMAC_CC_CSIZE_CHK_4 (0x2u << 8) /**< \brief (XDMAC_CC) 4 data transferred */ +#define XDMAC_CC_CSIZE_CHK_8 (0x3u << 8) /**< \brief (XDMAC_CC) 8 data transferred */ +#define XDMAC_CC_CSIZE_CHK_16 (0x4u << 8) /**< \brief (XDMAC_CC) 16 data transferred */ +#define XDMAC_CC_DWIDTH_Pos 11 +#define XDMAC_CC_DWIDTH_Msk (0x3u << XDMAC_CC_DWIDTH_Pos) /**< \brief (XDMAC_CC) Channel x Data Width */ +#define XDMAC_CC_DWIDTH(value) ((XDMAC_CC_DWIDTH_Msk & ((value) << XDMAC_CC_DWIDTH_Pos))) +#define XDMAC_CC_DWIDTH_BYTE (0x0u << 11) /**< \brief (XDMAC_CC) The data size is set to 8 bits */ +#define XDMAC_CC_DWIDTH_HALFWORD (0x1u << 11) /**< \brief (XDMAC_CC) The data size is set to 16 bits */ +#define XDMAC_CC_DWIDTH_WORD (0x2u << 11) /**< \brief (XDMAC_CC) The data size is set to 32 bits */ +#define XDMAC_CC_SIF (0x1u << 13) /**< \brief (XDMAC_CC) Channel x Source Interface Identifier */ +#define XDMAC_CC_SIF_AHB_IF0 (0x0u << 13) /**< \brief (XDMAC_CC) The data is read through the system bus interface 0 */ +#define XDMAC_CC_SIF_AHB_IF1 (0x1u << 13) /**< \brief (XDMAC_CC) The data is read through the system bus interface 1 */ +#define XDMAC_CC_DIF (0x1u << 14) /**< \brief (XDMAC_CC) Channel x Destination Interface Identifier */ +#define XDMAC_CC_DIF_AHB_IF0 (0x0u << 14) /**< \brief (XDMAC_CC) The data is written through the system bus interface 0 */ +#define XDMAC_CC_DIF_AHB_IF1 (0x1u << 14) /**< \brief (XDMAC_CC) The data is written though the system bus interface 1 */ +#define XDMAC_CC_SAM_Pos 16 +#define XDMAC_CC_SAM_Msk (0x3u << XDMAC_CC_SAM_Pos) /**< \brief (XDMAC_CC) Channel x Source Addressing Mode */ +#define XDMAC_CC_SAM(value) ((XDMAC_CC_SAM_Msk & ((value) << XDMAC_CC_SAM_Pos))) +#define XDMAC_CC_SAM_FIXED_AM (0x0u << 16) /**< \brief (XDMAC_CC) The address remains unchanged. */ +#define XDMAC_CC_SAM_INCREMENTED_AM (0x1u << 16) /**< \brief (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */ +#define XDMAC_CC_SAM_UBS_AM (0x2u << 16) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary. */ +#define XDMAC_CC_SAM_UBS_DS_AM (0x3u << 16) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. */ +#define XDMAC_CC_DAM_Pos 18 +#define XDMAC_CC_DAM_Msk (0x3u << XDMAC_CC_DAM_Pos) /**< \brief (XDMAC_CC) Channel x Destination Addressing Mode */ +#define XDMAC_CC_DAM(value) ((XDMAC_CC_DAM_Msk & ((value) << XDMAC_CC_DAM_Pos))) +#define XDMAC_CC_DAM_FIXED_AM (0x0u << 18) /**< \brief (XDMAC_CC) The address remains unchanged. */ +#define XDMAC_CC_DAM_INCREMENTED_AM (0x1u << 18) /**< \brief (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */ +#define XDMAC_CC_DAM_UBS_AM (0x2u << 18) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary. */ +#define XDMAC_CC_DAM_UBS_DS_AM (0x3u << 18) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. */ +#define XDMAC_CC_INITD (0x1u << 21) /**< \brief (XDMAC_CC) Channel Initialization Terminated (this bit is read-only) */ +#define XDMAC_CC_INITD_TERMINATED (0x0u << 21) /**< \brief (XDMAC_CC) Channel initialization is in progress. */ +#define XDMAC_CC_INITD_IN_PROGRESS (0x1u << 21) /**< \brief (XDMAC_CC) Channel initialization is completed. */ +#define XDMAC_CC_RDIP (0x1u << 22) /**< \brief (XDMAC_CC) Read in Progress (this bit is read-only) */ +#define XDMAC_CC_RDIP_DONE (0x0u << 22) /**< \brief (XDMAC_CC) No Active read transaction on the bus. */ +#define XDMAC_CC_RDIP_IN_PROGRESS (0x1u << 22) /**< \brief (XDMAC_CC) A read transaction is in progress. */ +#define XDMAC_CC_WRIP (0x1u << 23) /**< \brief (XDMAC_CC) Write in Progress (this bit is read-only) */ +#define XDMAC_CC_WRIP_DONE (0x0u << 23) /**< \brief (XDMAC_CC) No Active write transaction on the bus. */ +#define XDMAC_CC_WRIP_IN_PROGRESS (0x1u << 23) /**< \brief (XDMAC_CC) A Write transaction is in progress. */ +#define XDMAC_CC_PERID_Pos 24 +#define XDMAC_CC_PERID_Msk (0x7fu << XDMAC_CC_PERID_Pos) /**< \brief (XDMAC_CC) Channel x Peripheral Identifier */ +#define XDMAC_CC_PERID(value) ((XDMAC_CC_PERID_Msk & ((value) << XDMAC_CC_PERID_Pos))) +/* -------- XDMAC_CDS_MSP : (XDMAC Offset: N/A) Channel Data Stride Memory Set Pattern -------- */ +#define XDMAC_CDS_MSP_SDS_MSP_Pos 0 +#define XDMAC_CDS_MSP_SDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_SDS_MSP_Pos) /**< \brief (XDMAC_CDS_MSP) Channel x Source Data stride or Memory Set Pattern */ +#define XDMAC_CDS_MSP_SDS_MSP(value) ((XDMAC_CDS_MSP_SDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_SDS_MSP_Pos))) +#define XDMAC_CDS_MSP_DDS_MSP_Pos 16 +#define XDMAC_CDS_MSP_DDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_DDS_MSP_Pos) /**< \brief (XDMAC_CDS_MSP) Channel x Destination Data Stride or Memory Set Pattern */ +#define XDMAC_CDS_MSP_DDS_MSP(value) ((XDMAC_CDS_MSP_DDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_DDS_MSP_Pos))) +/* -------- XDMAC_CSUS : (XDMAC Offset: N/A) Channel Source Microblock Stride -------- */ +#define XDMAC_CSUS_SUBS_Pos 0 +#define XDMAC_CSUS_SUBS_Msk (0xffffffu << XDMAC_CSUS_SUBS_Pos) /**< \brief (XDMAC_CSUS) Channel x Source Microblock Stride */ +#define XDMAC_CSUS_SUBS(value) ((XDMAC_CSUS_SUBS_Msk & ((value) << XDMAC_CSUS_SUBS_Pos))) +/* -------- XDMAC_CDUS : (XDMAC Offset: N/A) Channel Destination Microblock Stride -------- */ +#define XDMAC_CDUS_DUBS_Pos 0 +#define XDMAC_CDUS_DUBS_Msk (0xffffffu << XDMAC_CDUS_DUBS_Pos) /**< \brief (XDMAC_CDUS) Channel x Destination Microblock Stride */ +#define XDMAC_CDUS_DUBS(value) ((XDMAC_CDUS_DUBS_Msk & ((value) << XDMAC_CDUS_DUBS_Pos))) + +/*@}*/ + + +#endif /* _SAMV71_XDMAC_COMPONENT_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_acc.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_acc.h new file mode 100644 index 00000000..4521d7e9 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_acc.h @@ -0,0 +1,56 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_ACC_INSTANCE_ +#define _SAMV71_ACC_INSTANCE_ + +/* ========== Register definition for ACC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_ACC_CR (0x40044000U) /**< \brief (ACC) Control Register */ + #define REG_ACC_MR (0x40044004U) /**< \brief (ACC) Mode Register */ + #define REG_ACC_IER (0x40044024U) /**< \brief (ACC) Interrupt Enable Register */ + #define REG_ACC_IDR (0x40044028U) /**< \brief (ACC) Interrupt Disable Register */ + #define REG_ACC_IMR (0x4004402CU) /**< \brief (ACC) Interrupt Mask Register */ + #define REG_ACC_ISR (0x40044030U) /**< \brief (ACC) Interrupt Status Register */ + #define REG_ACC_ACR (0x40044094U) /**< \brief (ACC) Analog Control Register */ + #define REG_ACC_WPMR (0x400440E4U) /**< \brief (ACC) Write Protection Mode Register */ + #define REG_ACC_WPSR (0x400440E8U) /**< \brief (ACC) Write Protection Status Register */ +#else + #define REG_ACC_CR (*(__O uint32_t*)0x40044000U) /**< \brief (ACC) Control Register */ + #define REG_ACC_MR (*(__IO uint32_t*)0x40044004U) /**< \brief (ACC) Mode Register */ + #define REG_ACC_IER (*(__O uint32_t*)0x40044024U) /**< \brief (ACC) Interrupt Enable Register */ + #define REG_ACC_IDR (*(__O uint32_t*)0x40044028U) /**< \brief (ACC) Interrupt Disable Register */ + #define REG_ACC_IMR (*(__I uint32_t*)0x4004402CU) /**< \brief (ACC) Interrupt Mask Register */ + #define REG_ACC_ISR (*(__I uint32_t*)0x40044030U) /**< \brief (ACC) Interrupt Status Register */ + #define REG_ACC_ACR (*(__IO uint32_t*)0x40044094U) /**< \brief (ACC) Analog Control Register */ + #define REG_ACC_WPMR (*(__IO uint32_t*)0x400440E4U) /**< \brief (ACC) Write Protection Mode Register */ + #define REG_ACC_WPSR (*(__I uint32_t*)0x400440E8U) /**< \brief (ACC) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_ACC_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_aes.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_aes.h new file mode 100644 index 00000000..cb822a7d --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_aes.h @@ -0,0 +1,70 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_AES_INSTANCE_ +#define _SAMV71_AES_INSTANCE_ + +/* ========== Register definition for AES peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_AES_CR (0x4006C000U) /**< \brief (AES) Control Register */ + #define REG_AES_MR (0x4006C004U) /**< \brief (AES) Mode Register */ + #define REG_AES_IER (0x4006C010U) /**< \brief (AES) Interrupt Enable Register */ + #define REG_AES_IDR (0x4006C014U) /**< \brief (AES) Interrupt Disable Register */ + #define REG_AES_IMR (0x4006C018U) /**< \brief (AES) Interrupt Mask Register */ + #define REG_AES_ISR (0x4006C01CU) /**< \brief (AES) Interrupt Status Register */ + #define REG_AES_KEYWR (0x4006C020U) /**< \brief (AES) Key Word Register */ + #define REG_AES_IDATAR (0x4006C040U) /**< \brief (AES) Input Data Register */ + #define REG_AES_ODATAR (0x4006C050U) /**< \brief (AES) Output Data Register */ + #define REG_AES_IVR (0x4006C060U) /**< \brief (AES) Initialization Vector Register */ + #define REG_AES_AADLENR (0x4006C070U) /**< \brief (AES) Additional Authenticated Data Length Register */ + #define REG_AES_CLENR (0x4006C074U) /**< \brief (AES) Plaintext/Ciphertext Length Register */ + #define REG_AES_GHASHR (0x4006C078U) /**< \brief (AES) GCM Intermediate Hash Word Register */ + #define REG_AES_TAGR (0x4006C088U) /**< \brief (AES) GCM Authentication Tag Word Register */ + #define REG_AES_CTRR (0x4006C098U) /**< \brief (AES) GCM Encryption Counter Value Register */ + #define REG_AES_GCMHR (0x4006C09CU) /**< \brief (AES) GCM H Word Register */ +#else + #define REG_AES_CR (*(__O uint32_t*)0x4006C000U) /**< \brief (AES) Control Register */ + #define REG_AES_MR (*(__IO uint32_t*)0x4006C004U) /**< \brief (AES) Mode Register */ + #define REG_AES_IER (*(__O uint32_t*)0x4006C010U) /**< \brief (AES) Interrupt Enable Register */ + #define REG_AES_IDR (*(__O uint32_t*)0x4006C014U) /**< \brief (AES) Interrupt Disable Register */ + #define REG_AES_IMR (*(__I uint32_t*)0x4006C018U) /**< \brief (AES) Interrupt Mask Register */ + #define REG_AES_ISR (*(__I uint32_t*)0x4006C01CU) /**< \brief (AES) Interrupt Status Register */ + #define REG_AES_KEYWR (*(__O uint32_t*)0x4006C020U) /**< \brief (AES) Key Word Register */ + #define REG_AES_IDATAR (*(__O uint32_t*)0x4006C040U) /**< \brief (AES) Input Data Register */ + #define REG_AES_ODATAR (*(__I uint32_t*)0x4006C050U) /**< \brief (AES) Output Data Register */ + #define REG_AES_IVR (*(__O uint32_t*)0x4006C060U) /**< \brief (AES) Initialization Vector Register */ + #define REG_AES_AADLENR (*(__IO uint32_t*)0x4006C070U) /**< \brief (AES) Additional Authenticated Data Length Register */ + #define REG_AES_CLENR (*(__IO uint32_t*)0x4006C074U) /**< \brief (AES) Plaintext/Ciphertext Length Register */ + #define REG_AES_GHASHR (*(__IO uint32_t*)0x4006C078U) /**< \brief (AES) GCM Intermediate Hash Word Register */ + #define REG_AES_TAGR (*(__I uint32_t*)0x4006C088U) /**< \brief (AES) GCM Authentication Tag Word Register */ + #define REG_AES_CTRR (*(__I uint32_t*)0x4006C098U) /**< \brief (AES) GCM Encryption Counter Value Register */ + #define REG_AES_GCMHR (*(__IO uint32_t*)0x4006C09CU) /**< \brief (AES) GCM H Word Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_AES_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_afec0.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_afec0.h new file mode 100644 index 00000000..e168aee0 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_afec0.h @@ -0,0 +1,96 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_AFEC0_INSTANCE_ +#define _SAMV71_AFEC0_INSTANCE_ + +/* ========== Register definition for AFEC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_AFEC0_CR (0x4003C000U) /**< \brief (AFEC0) AFEC Control Register */ + #define REG_AFEC0_MR (0x4003C004U) /**< \brief (AFEC0) AFEC Mode Register */ + #define REG_AFEC0_EMR (0x4003C008U) /**< \brief (AFEC0) AFEC Extended Mode Register */ + #define REG_AFEC0_SEQ1R (0x4003C00CU) /**< \brief (AFEC0) AFEC Channel Sequence 1 Register */ + #define REG_AFEC0_SEQ2R (0x4003C010U) /**< \brief (AFEC0) AFEC Channel Sequence 2 Register */ + #define REG_AFEC0_CHER (0x4003C014U) /**< \brief (AFEC0) AFEC Channel Enable Register */ + #define REG_AFEC0_CHDR (0x4003C018U) /**< \brief (AFEC0) AFEC Channel Disable Register */ + #define REG_AFEC0_CHSR (0x4003C01CU) /**< \brief (AFEC0) AFEC Channel Status Register */ + #define REG_AFEC0_LCDR (0x4003C020U) /**< \brief (AFEC0) AFEC Last Converted Data Register */ + #define REG_AFEC0_IER (0x4003C024U) /**< \brief (AFEC0) AFEC Interrupt Enable Register */ + #define REG_AFEC0_IDR (0x4003C028U) /**< \brief (AFEC0) AFEC Interrupt Disable Register */ + #define REG_AFEC0_IMR (0x4003C02CU) /**< \brief (AFEC0) AFEC Interrupt Mask Register */ + #define REG_AFEC0_ISR (0x4003C030U) /**< \brief (AFEC0) AFEC Interrupt Status Register */ + #define REG_AFEC0_OVER (0x4003C04CU) /**< \brief (AFEC0) AFEC Overrun Status Register */ + #define REG_AFEC0_CWR (0x4003C050U) /**< \brief (AFEC0) AFEC Compare Window Register */ + #define REG_AFEC0_CGR (0x4003C054U) /**< \brief (AFEC0) AFEC Channel Gain Register */ + #define REG_AFEC0_DIFFR (0x4003C060U) /**< \brief (AFEC0) AFEC Channel Differential Register */ + #define REG_AFEC0_CSELR (0x4003C064U) /**< \brief (AFEC0) AFEC Channel Selection Register */ + #define REG_AFEC0_CDR (0x4003C068U) /**< \brief (AFEC0) AFEC Channel Data Register */ + #define REG_AFEC0_COCR (0x4003C06CU) /**< \brief (AFEC0) AFEC Channel Offset Compensation Register */ + #define REG_AFEC0_TEMPMR (0x4003C070U) /**< \brief (AFEC0) AFEC Temperature Sensor Mode Register */ + #define REG_AFEC0_TEMPCWR (0x4003C074U) /**< \brief (AFEC0) AFEC Temperature Compare Window Register */ + #define REG_AFEC0_ACR (0x4003C094U) /**< \brief (AFEC0) AFEC Analog Control Register */ + #define REG_AFEC0_SHMR (0x4003C0A0U) /**< \brief (AFEC0) AFEC Sample & Hold Mode Register */ + #define REG_AFEC0_COSR (0x4003C0D0U) /**< \brief (AFEC0) AFEC Correction Select Register */ + #define REG_AFEC0_CVR (0x4003C0D4U) /**< \brief (AFEC0) AFEC Correction Values Register */ + #define REG_AFEC0_CECR (0x4003C0D8U) /**< \brief (AFEC0) AFEC Channel Error Correction Register */ + #define REG_AFEC0_WPMR (0x4003C0E4U) /**< \brief (AFEC0) AFEC Write Protection Mode Register */ + #define REG_AFEC0_WPSR (0x4003C0E8U) /**< \brief (AFEC0) AFEC Write Protection Status Register */ +#else + #define REG_AFEC0_CR (*(__O uint32_t*)0x4003C000U) /**< \brief (AFEC0) AFEC Control Register */ + #define REG_AFEC0_MR (*(__IO uint32_t*)0x4003C004U) /**< \brief (AFEC0) AFEC Mode Register */ + #define REG_AFEC0_EMR (*(__IO uint32_t*)0x4003C008U) /**< \brief (AFEC0) AFEC Extended Mode Register */ + #define REG_AFEC0_SEQ1R (*(__IO uint32_t*)0x4003C00CU) /**< \brief (AFEC0) AFEC Channel Sequence 1 Register */ + #define REG_AFEC0_SEQ2R (*(__IO uint32_t*)0x4003C010U) /**< \brief (AFEC0) AFEC Channel Sequence 2 Register */ + #define REG_AFEC0_CHER (*(__O uint32_t*)0x4003C014U) /**< \brief (AFEC0) AFEC Channel Enable Register */ + #define REG_AFEC0_CHDR (*(__O uint32_t*)0x4003C018U) /**< \brief (AFEC0) AFEC Channel Disable Register */ + #define REG_AFEC0_CHSR (*(__I uint32_t*)0x4003C01CU) /**< \brief (AFEC0) AFEC Channel Status Register */ + #define REG_AFEC0_LCDR (*(__I uint32_t*)0x4003C020U) /**< \brief (AFEC0) AFEC Last Converted Data Register */ + #define REG_AFEC0_IER (*(__O uint32_t*)0x4003C024U) /**< \brief (AFEC0) AFEC Interrupt Enable Register */ + #define REG_AFEC0_IDR (*(__O uint32_t*)0x4003C028U) /**< \brief (AFEC0) AFEC Interrupt Disable Register */ + #define REG_AFEC0_IMR (*(__I uint32_t*)0x4003C02CU) /**< \brief (AFEC0) AFEC Interrupt Mask Register */ + #define REG_AFEC0_ISR (*(__I uint32_t*)0x4003C030U) /**< \brief (AFEC0) AFEC Interrupt Status Register */ + #define REG_AFEC0_OVER (*(__I uint32_t*)0x4003C04CU) /**< \brief (AFEC0) AFEC Overrun Status Register */ + #define REG_AFEC0_CWR (*(__IO uint32_t*)0x4003C050U) /**< \brief (AFEC0) AFEC Compare Window Register */ + #define REG_AFEC0_CGR (*(__IO uint32_t*)0x4003C054U) /**< \brief (AFEC0) AFEC Channel Gain Register */ + #define REG_AFEC0_DIFFR (*(__IO uint32_t*)0x4003C060U) /**< \brief (AFEC0) AFEC Channel Differential Register */ + #define REG_AFEC0_CSELR (*(__IO uint32_t*)0x4003C064U) /**< \brief (AFEC0) AFEC Channel Selection Register */ + #define REG_AFEC0_CDR (*(__I uint32_t*)0x4003C068U) /**< \brief (AFEC0) AFEC Channel Data Register */ + #define REG_AFEC0_COCR (*(__IO uint32_t*)0x4003C06CU) /**< \brief (AFEC0) AFEC Channel Offset Compensation Register */ + #define REG_AFEC0_TEMPMR (*(__IO uint32_t*)0x4003C070U) /**< \brief (AFEC0) AFEC Temperature Sensor Mode Register */ + #define REG_AFEC0_TEMPCWR (*(__IO uint32_t*)0x4003C074U) /**< \brief (AFEC0) AFEC Temperature Compare Window Register */ + #define REG_AFEC0_ACR (*(__IO uint32_t*)0x4003C094U) /**< \brief (AFEC0) AFEC Analog Control Register */ + #define REG_AFEC0_SHMR (*(__IO uint32_t*)0x4003C0A0U) /**< \brief (AFEC0) AFEC Sample & Hold Mode Register */ + #define REG_AFEC0_COSR (*(__IO uint32_t*)0x4003C0D0U) /**< \brief (AFEC0) AFEC Correction Select Register */ + #define REG_AFEC0_CVR (*(__IO uint32_t*)0x4003C0D4U) /**< \brief (AFEC0) AFEC Correction Values Register */ + #define REG_AFEC0_CECR (*(__IO uint32_t*)0x4003C0D8U) /**< \brief (AFEC0) AFEC Channel Error Correction Register */ + #define REG_AFEC0_WPMR (*(__IO uint32_t*)0x4003C0E4U) /**< \brief (AFEC0) AFEC Write Protection Mode Register */ + #define REG_AFEC0_WPSR (*(__I uint32_t*)0x4003C0E8U) /**< \brief (AFEC0) AFEC Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_AFEC0_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_afec1.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_afec1.h new file mode 100644 index 00000000..1816ad5d --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_afec1.h @@ -0,0 +1,96 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_AFEC1_INSTANCE_ +#define _SAMV71_AFEC1_INSTANCE_ + +/* ========== Register definition for AFEC1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_AFEC1_CR (0x40064000U) /**< \brief (AFEC1) AFEC Control Register */ + #define REG_AFEC1_MR (0x40064004U) /**< \brief (AFEC1) AFEC Mode Register */ + #define REG_AFEC1_EMR (0x40064008U) /**< \brief (AFEC1) AFEC Extended Mode Register */ + #define REG_AFEC1_SEQ1R (0x4006400CU) /**< \brief (AFEC1) AFEC Channel Sequence 1 Register */ + #define REG_AFEC1_SEQ2R (0x40064010U) /**< \brief (AFEC1) AFEC Channel Sequence 2 Register */ + #define REG_AFEC1_CHER (0x40064014U) /**< \brief (AFEC1) AFEC Channel Enable Register */ + #define REG_AFEC1_CHDR (0x40064018U) /**< \brief (AFEC1) AFEC Channel Disable Register */ + #define REG_AFEC1_CHSR (0x4006401CU) /**< \brief (AFEC1) AFEC Channel Status Register */ + #define REG_AFEC1_LCDR (0x40064020U) /**< \brief (AFEC1) AFEC Last Converted Data Register */ + #define REG_AFEC1_IER (0x40064024U) /**< \brief (AFEC1) AFEC Interrupt Enable Register */ + #define REG_AFEC1_IDR (0x40064028U) /**< \brief (AFEC1) AFEC Interrupt Disable Register */ + #define REG_AFEC1_IMR (0x4006402CU) /**< \brief (AFEC1) AFEC Interrupt Mask Register */ + #define REG_AFEC1_ISR (0x40064030U) /**< \brief (AFEC1) AFEC Interrupt Status Register */ + #define REG_AFEC1_OVER (0x4006404CU) /**< \brief (AFEC1) AFEC Overrun Status Register */ + #define REG_AFEC1_CWR (0x40064050U) /**< \brief (AFEC1) AFEC Compare Window Register */ + #define REG_AFEC1_CGR (0x40064054U) /**< \brief (AFEC1) AFEC Channel Gain Register */ + #define REG_AFEC1_DIFFR (0x40064060U) /**< \brief (AFEC1) AFEC Channel Differential Register */ + #define REG_AFEC1_CSELR (0x40064064U) /**< \brief (AFEC1) AFEC Channel Selection Register */ + #define REG_AFEC1_CDR (0x40064068U) /**< \brief (AFEC1) AFEC Channel Data Register */ + #define REG_AFEC1_COCR (0x4006406CU) /**< \brief (AFEC1) AFEC Channel Offset Compensation Register */ + #define REG_AFEC1_TEMPMR (0x40064070U) /**< \brief (AFEC1) AFEC Temperature Sensor Mode Register */ + #define REG_AFEC1_TEMPCWR (0x40064074U) /**< \brief (AFEC1) AFEC Temperature Compare Window Register */ + #define REG_AFEC1_ACR (0x40064094U) /**< \brief (AFEC1) AFEC Analog Control Register */ + #define REG_AFEC1_SHMR (0x400640A0U) /**< \brief (AFEC1) AFEC Sample & Hold Mode Register */ + #define REG_AFEC1_COSR (0x400640D0U) /**< \brief (AFEC1) AFEC Correction Select Register */ + #define REG_AFEC1_CVR (0x400640D4U) /**< \brief (AFEC1) AFEC Correction Values Register */ + #define REG_AFEC1_CECR (0x400640D8U) /**< \brief (AFEC1) AFEC Channel Error Correction Register */ + #define REG_AFEC1_WPMR (0x400640E4U) /**< \brief (AFEC1) AFEC Write Protection Mode Register */ + #define REG_AFEC1_WPSR (0x400640E8U) /**< \brief (AFEC1) AFEC Write Protection Status Register */ +#else + #define REG_AFEC1_CR (*(__O uint32_t*)0x40064000U) /**< \brief (AFEC1) AFEC Control Register */ + #define REG_AFEC1_MR (*(__IO uint32_t*)0x40064004U) /**< \brief (AFEC1) AFEC Mode Register */ + #define REG_AFEC1_EMR (*(__IO uint32_t*)0x40064008U) /**< \brief (AFEC1) AFEC Extended Mode Register */ + #define REG_AFEC1_SEQ1R (*(__IO uint32_t*)0x4006400CU) /**< \brief (AFEC1) AFEC Channel Sequence 1 Register */ + #define REG_AFEC1_SEQ2R (*(__IO uint32_t*)0x40064010U) /**< \brief (AFEC1) AFEC Channel Sequence 2 Register */ + #define REG_AFEC1_CHER (*(__O uint32_t*)0x40064014U) /**< \brief (AFEC1) AFEC Channel Enable Register */ + #define REG_AFEC1_CHDR (*(__O uint32_t*)0x40064018U) /**< \brief (AFEC1) AFEC Channel Disable Register */ + #define REG_AFEC1_CHSR (*(__I uint32_t*)0x4006401CU) /**< \brief (AFEC1) AFEC Channel Status Register */ + #define REG_AFEC1_LCDR (*(__I uint32_t*)0x40064020U) /**< \brief (AFEC1) AFEC Last Converted Data Register */ + #define REG_AFEC1_IER (*(__O uint32_t*)0x40064024U) /**< \brief (AFEC1) AFEC Interrupt Enable Register */ + #define REG_AFEC1_IDR (*(__O uint32_t*)0x40064028U) /**< \brief (AFEC1) AFEC Interrupt Disable Register */ + #define REG_AFEC1_IMR (*(__I uint32_t*)0x4006402CU) /**< \brief (AFEC1) AFEC Interrupt Mask Register */ + #define REG_AFEC1_ISR (*(__I uint32_t*)0x40064030U) /**< \brief (AFEC1) AFEC Interrupt Status Register */ + #define REG_AFEC1_OVER (*(__I uint32_t*)0x4006404CU) /**< \brief (AFEC1) AFEC Overrun Status Register */ + #define REG_AFEC1_CWR (*(__IO uint32_t*)0x40064050U) /**< \brief (AFEC1) AFEC Compare Window Register */ + #define REG_AFEC1_CGR (*(__IO uint32_t*)0x40064054U) /**< \brief (AFEC1) AFEC Channel Gain Register */ + #define REG_AFEC1_DIFFR (*(__IO uint32_t*)0x40064060U) /**< \brief (AFEC1) AFEC Channel Differential Register */ + #define REG_AFEC1_CSELR (*(__IO uint32_t*)0x40064064U) /**< \brief (AFEC1) AFEC Channel Selection Register */ + #define REG_AFEC1_CDR (*(__I uint32_t*)0x40064068U) /**< \brief (AFEC1) AFEC Channel Data Register */ + #define REG_AFEC1_COCR (*(__IO uint32_t*)0x4006406CU) /**< \brief (AFEC1) AFEC Channel Offset Compensation Register */ + #define REG_AFEC1_TEMPMR (*(__IO uint32_t*)0x40064070U) /**< \brief (AFEC1) AFEC Temperature Sensor Mode Register */ + #define REG_AFEC1_TEMPCWR (*(__IO uint32_t*)0x40064074U) /**< \brief (AFEC1) AFEC Temperature Compare Window Register */ + #define REG_AFEC1_ACR (*(__IO uint32_t*)0x40064094U) /**< \brief (AFEC1) AFEC Analog Control Register */ + #define REG_AFEC1_SHMR (*(__IO uint32_t*)0x400640A0U) /**< \brief (AFEC1) AFEC Sample & Hold Mode Register */ + #define REG_AFEC1_COSR (*(__IO uint32_t*)0x400640D0U) /**< \brief (AFEC1) AFEC Correction Select Register */ + #define REG_AFEC1_CVR (*(__IO uint32_t*)0x400640D4U) /**< \brief (AFEC1) AFEC Correction Values Register */ + #define REG_AFEC1_CECR (*(__IO uint32_t*)0x400640D8U) /**< \brief (AFEC1) AFEC Channel Error Correction Register */ + #define REG_AFEC1_WPMR (*(__IO uint32_t*)0x400640E4U) /**< \brief (AFEC1) AFEC Write Protection Mode Register */ + #define REG_AFEC1_WPSR (*(__I uint32_t*)0x400640E8U) /**< \brief (AFEC1) AFEC Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_AFEC1_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_chipid.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_chipid.h new file mode 100644 index 00000000..8c297de9 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_chipid.h @@ -0,0 +1,42 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_CHIPID_INSTANCE_ +#define _SAMV71_CHIPID_INSTANCE_ + +/* ========== Register definition for CHIPID peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_CHIPID_CIDR (0x400E0940U) /**< \brief (CHIPID) Chip ID Register */ + #define REG_CHIPID_EXID (0x400E0944U) /**< \brief (CHIPID) Chip ID Extension Register */ +#else + #define REG_CHIPID_CIDR (*(__I uint32_t*)0x400E0940U) /**< \brief (CHIPID) Chip ID Register */ + #define REG_CHIPID_EXID (*(__I uint32_t*)0x400E0944U) /**< \brief (CHIPID) Chip ID Extension Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_CHIPID_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_dacc.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_dacc.h new file mode 100644 index 00000000..31a5a4a7 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_dacc.h @@ -0,0 +1,66 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_DACC_INSTANCE_ +#define _SAMV71_DACC_INSTANCE_ + +/* ========== Register definition for DACC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_DACC_CR (0x40040000U) /**< \brief (DACC) Control Register */ + #define REG_DACC_MR (0x40040004U) /**< \brief (DACC) Mode Register */ + #define REG_DACC_TRIGR (0x40040008U) /**< \brief (DACC) Trigger Register */ + #define REG_DACC_CHER (0x40040010U) /**< \brief (DACC) Channel Enable Register */ + #define REG_DACC_CHDR (0x40040014U) /**< \brief (DACC) Channel Disable Register */ + #define REG_DACC_CHSR (0x40040018U) /**< \brief (DACC) Channel Status Register */ + #define REG_DACC_CDR (0x4004001CU) /**< \brief (DACC) Conversion Data Register */ + #define REG_DACC_IER (0x40040024U) /**< \brief (DACC) Interrupt Enable Register */ + #define REG_DACC_IDR (0x40040028U) /**< \brief (DACC) Interrupt Disable Register */ + #define REG_DACC_IMR (0x4004002CU) /**< \brief (DACC) Interrupt Mask Register */ + #define REG_DACC_ISR (0x40040030U) /**< \brief (DACC) Interrupt Status Register */ + #define REG_DACC_ACR (0x40040094U) /**< \brief (DACC) Analog Current Register */ + #define REG_DACC_WPMR (0x400400E4U) /**< \brief (DACC) Write Protection Mode register */ + #define REG_DACC_WPSR (0x400400E8U) /**< \brief (DACC) Write Protection Status register */ +#else + #define REG_DACC_CR (*(__O uint32_t*)0x40040000U) /**< \brief (DACC) Control Register */ + #define REG_DACC_MR (*(__IO uint32_t*)0x40040004U) /**< \brief (DACC) Mode Register */ + #define REG_DACC_TRIGR (*(__IO uint32_t*)0x40040008U) /**< \brief (DACC) Trigger Register */ + #define REG_DACC_CHER (*(__O uint32_t*)0x40040010U) /**< \brief (DACC) Channel Enable Register */ + #define REG_DACC_CHDR (*(__O uint32_t*)0x40040014U) /**< \brief (DACC) Channel Disable Register */ + #define REG_DACC_CHSR (*(__I uint32_t*)0x40040018U) /**< \brief (DACC) Channel Status Register */ + #define REG_DACC_CDR (*(__O uint32_t*)0x4004001CU) /**< \brief (DACC) Conversion Data Register */ + #define REG_DACC_IER (*(__O uint32_t*)0x40040024U) /**< \brief (DACC) Interrupt Enable Register */ + #define REG_DACC_IDR (*(__O uint32_t*)0x40040028U) /**< \brief (DACC) Interrupt Disable Register */ + #define REG_DACC_IMR (*(__I uint32_t*)0x4004002CU) /**< \brief (DACC) Interrupt Mask Register */ + #define REG_DACC_ISR (*(__I uint32_t*)0x40040030U) /**< \brief (DACC) Interrupt Status Register */ + #define REG_DACC_ACR (*(__IO uint32_t*)0x40040094U) /**< \brief (DACC) Analog Current Register */ + #define REG_DACC_WPMR (*(__IO uint32_t*)0x400400E4U) /**< \brief (DACC) Write Protection Mode register */ + #define REG_DACC_WPSR (*(__I uint32_t*)0x400400E8U) /**< \brief (DACC) Write Protection Status register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_DACC_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_efc.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_efc.h new file mode 100644 index 00000000..92ac20d4 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_efc.h @@ -0,0 +1,50 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_EFC_INSTANCE_ +#define _SAMV71_EFC_INSTANCE_ + +/* ========== Register definition for EFC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_EFC_FMR (0x400E0C00U) /**< \brief (EFC) EEFC Flash Mode Register */ + #define REG_EFC_FCR (0x400E0C04U) /**< \brief (EFC) EEFC Flash Command Register */ + #define REG_EFC_FSR (0x400E0C08U) /**< \brief (EFC) EEFC Flash Status Register */ + #define REG_EFC_FRR (0x400E0C0CU) /**< \brief (EFC) EEFC Flash Result Register */ + #define REG_EFC_VERSION (0x400E0C14U) /**< \brief (EFC) EEFC Version Register */ + #define REG_EFC_WPMR (0x400E0CE4U) /**< \brief (EFC) Write Protection Mode Register */ +#else + #define REG_EFC_FMR (*(__IO uint32_t*)0x400E0C00U) /**< \brief (EFC) EEFC Flash Mode Register */ + #define REG_EFC_FCR (*(__O uint32_t*)0x400E0C04U) /**< \brief (EFC) EEFC Flash Command Register */ + #define REG_EFC_FSR (*(__I uint32_t*)0x400E0C08U) /**< \brief (EFC) EEFC Flash Status Register */ + #define REG_EFC_FRR (*(__I uint32_t*)0x400E0C0CU) /**< \brief (EFC) EEFC Flash Result Register */ + #define REG_EFC_VERSION (*(__I uint32_t*)0x400E0C14U) /**< \brief (EFC) EEFC Version Register */ + #define REG_EFC_WPMR (*(__IO uint32_t*)0x400E0CE4U) /**< \brief (EFC) Write Protection Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_EFC_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_gmac.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_gmac.h new file mode 100644 index 00000000..378eb146 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_gmac.h @@ -0,0 +1,370 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_GMAC_INSTANCE_ +#define _SAMV71_GMAC_INSTANCE_ + +/* ========== Register definition for GMAC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_GMAC_NCR (0x40050000U) /**< \brief (GMAC) Network Control Register */ + #define REG_GMAC_NCFGR (0x40050004U) /**< \brief (GMAC) Network Configuration Register */ + #define REG_GMAC_NSR (0x40050008U) /**< \brief (GMAC) Network Status Register */ + #define REG_GMAC_UR (0x4005000CU) /**< \brief (GMAC) User Register */ + #define REG_GMAC_DCFGR (0x40050010U) /**< \brief (GMAC) DMA Configuration Register */ + #define REG_GMAC_TSR (0x40050014U) /**< \brief (GMAC) Transmit Status Register */ + #define REG_GMAC_RBQB (0x40050018U) /**< \brief (GMAC) Receive Buffer Queue Base Address Register */ + #define REG_GMAC_TBQB (0x4005001CU) /**< \brief (GMAC) Transmit Buffer Queue Base Address Register */ + #define REG_GMAC_RSR (0x40050020U) /**< \brief (GMAC) Receive Status Register */ + #define REG_GMAC_ISR (0x40050024U) /**< \brief (GMAC) Interrupt Status Register */ + #define REG_GMAC_IER (0x40050028U) /**< \brief (GMAC) Interrupt Enable Register */ + #define REG_GMAC_IDR (0x4005002CU) /**< \brief (GMAC) Interrupt Disable Register */ + #define REG_GMAC_IMR (0x40050030U) /**< \brief (GMAC) Interrupt Mask Register */ + #define REG_GMAC_MAN (0x40050034U) /**< \brief (GMAC) PHY Maintenance Register */ + #define REG_GMAC_RPQ (0x40050038U) /**< \brief (GMAC) Received Pause Quantum Register */ + #define REG_GMAC_TPQ (0x4005003CU) /**< \brief (GMAC) Transmit Pause Quantum Register */ + #define REG_GMAC_TPSF (0x40050040U) /**< \brief (GMAC) TX Partial Store and Forward Register */ + #define REG_GMAC_RPSF (0x40050044U) /**< \brief (GMAC) RX Partial Store and Forward Register */ + #define REG_GMAC_RJFML (0x40050048U) /**< \brief (GMAC) RX Jumbo Frame Max Length Register */ + #define REG_GMAC_HRB (0x40050080U) /**< \brief (GMAC) Hash Register Bottom */ + #define REG_GMAC_HRT (0x40050084U) /**< \brief (GMAC) Hash Register Top */ + #define REG_GMAC_SAB1 (0x40050088U) /**< \brief (GMAC) Specific Address 1 Bottom Register */ + #define REG_GMAC_SAT1 (0x4005008CU) /**< \brief (GMAC) Specific Address 1 Top Register */ + #define REG_GMAC_SAB2 (0x40050090U) /**< \brief (GMAC) Specific Address 2 Bottom Register */ + #define REG_GMAC_SAT2 (0x40050094U) /**< \brief (GMAC) Specific Address 2 Top Register */ + #define REG_GMAC_SAB3 (0x40050098U) /**< \brief (GMAC) Specific Address 3 Bottom Register */ + #define REG_GMAC_SAT3 (0x4005009CU) /**< \brief (GMAC) Specific Address 3 Top Register */ + #define REG_GMAC_SAB4 (0x400500A0U) /**< \brief (GMAC) Specific Address 4 Bottom Register */ + #define REG_GMAC_SAT4 (0x400500A4U) /**< \brief (GMAC) Specific Address 4 Top Register */ + #define REG_GMAC_TIDM1 (0x400500A8U) /**< \brief (GMAC) Type ID Match 1 Register */ + #define REG_GMAC_TIDM2 (0x400500ACU) /**< \brief (GMAC) Type ID Match 2 Register */ + #define REG_GMAC_TIDM3 (0x400500B0U) /**< \brief (GMAC) Type ID Match 3 Register */ + #define REG_GMAC_TIDM4 (0x400500B4U) /**< \brief (GMAC) Type ID Match 4 Register */ + #define REG_GMAC_WOL (0x400500B8U) /**< \brief (GMAC) Wake on LAN Register */ + #define REG_GMAC_IPGS (0x400500BCU) /**< \brief (GMAC) IPG Stretch Register */ + #define REG_GMAC_SVLAN (0x400500C0U) /**< \brief (GMAC) Stacked VLAN Register */ + #define REG_GMAC_TPFCP (0x400500C4U) /**< \brief (GMAC) Transmit PFC Pause Register */ + #define REG_GMAC_SAMB1 (0x400500C8U) /**< \brief (GMAC) Specific Address 1 Mask Bottom Register */ + #define REG_GMAC_SAMT1 (0x400500CCU) /**< \brief (GMAC) Specific Address 1 Mask Top Register */ + #define REG_GMAC_NSC (0x400500DCU) /**< \brief (GMAC) 1588 Timer Nanosecond Comparison Register */ + #define REG_GMAC_SCL (0x400500E0U) /**< \brief (GMAC) 1588 Timer Second Comparison Low Register */ + #define REG_GMAC_SCH (0x400500E4U) /**< \brief (GMAC) 1588 Timer Second Comparison High Register */ + #define REG_GMAC_EFTSH (0x400500E8U) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds High Register */ + #define REG_GMAC_EFRSH (0x400500ECU) /**< \brief (GMAC) PTP Event Frame Received Seconds High Register */ + #define REG_GMAC_PEFTSH (0x400500F0U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds High Register */ + #define REG_GMAC_PEFRSH (0x400500F4U) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds High Register */ + #define REG_GMAC_OTLO (0x40050100U) /**< \brief (GMAC) Octets Transmitted Low Register */ + #define REG_GMAC_OTHI (0x40050104U) /**< \brief (GMAC) Octets Transmitted High Register */ + #define REG_GMAC_FT (0x40050108U) /**< \brief (GMAC) Frames Transmitted Register */ + #define REG_GMAC_BCFT (0x4005010CU) /**< \brief (GMAC) Broadcast Frames Transmitted Register */ + #define REG_GMAC_MFT (0x40050110U) /**< \brief (GMAC) Multicast Frames Transmitted Register */ + #define REG_GMAC_PFT (0x40050114U) /**< \brief (GMAC) Pause Frames Transmitted Register */ + #define REG_GMAC_BFT64 (0x40050118U) /**< \brief (GMAC) 64 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT127 (0x4005011CU) /**< \brief (GMAC) 65 to 127 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT255 (0x40050120U) /**< \brief (GMAC) 128 to 255 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT511 (0x40050124U) /**< \brief (GMAC) 256 to 511 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT1023 (0x40050128U) /**< \brief (GMAC) 512 to 1023 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT1518 (0x4005012CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Transmitted Register */ + #define REG_GMAC_GTBFT1518 (0x40050130U) /**< \brief (GMAC) Greater Than 1518 Byte Frames Transmitted Register */ + #define REG_GMAC_TUR (0x40050134U) /**< \brief (GMAC) Transmit Underruns Register */ + #define REG_GMAC_SCF (0x40050138U) /**< \brief (GMAC) Single Collision Frames Register */ + #define REG_GMAC_MCF (0x4005013CU) /**< \brief (GMAC) Multiple Collision Frames Register */ + #define REG_GMAC_EC (0x40050140U) /**< \brief (GMAC) Excessive Collisions Register */ + #define REG_GMAC_LC (0x40050144U) /**< \brief (GMAC) Late Collisions Register */ + #define REG_GMAC_DTF (0x40050148U) /**< \brief (GMAC) Deferred Transmission Frames Register */ + #define REG_GMAC_CSE (0x4005014CU) /**< \brief (GMAC) Carrier Sense Errors Register Register */ + #define REG_GMAC_ORLO (0x40050150U) /**< \brief (GMAC) Octets Received Low Received Register */ + #define REG_GMAC_ORHI (0x40050154U) /**< \brief (GMAC) Octets Received High Received Register */ + #define REG_GMAC_FR (0x40050158U) /**< \brief (GMAC) Frames Received Register */ + #define REG_GMAC_BCFR (0x4005015CU) /**< \brief (GMAC) Broadcast Frames Received Register */ + #define REG_GMAC_MFR (0x40050160U) /**< \brief (GMAC) Multicast Frames Received Register */ + #define REG_GMAC_PFR (0x40050164U) /**< \brief (GMAC) Pause Frames Received Register */ + #define REG_GMAC_BFR64 (0x40050168U) /**< \brief (GMAC) 64 Byte Frames Received Register */ + #define REG_GMAC_TBFR127 (0x4005016CU) /**< \brief (GMAC) 65 to 127 Byte Frames Received Register */ + #define REG_GMAC_TBFR255 (0x40050170U) /**< \brief (GMAC) 128 to 255 Byte Frames Received Register */ + #define REG_GMAC_TBFR511 (0x40050174U) /**< \brief (GMAC) 256 to 511 Byte Frames Received Register */ + #define REG_GMAC_TBFR1023 (0x40050178U) /**< \brief (GMAC) 512 to 1023 Byte Frames Received Register */ + #define REG_GMAC_TBFR1518 (0x4005017CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Received Register */ + #define REG_GMAC_TMXBFR (0x40050180U) /**< \brief (GMAC) 1519 to Maximum Byte Frames Received Register */ + #define REG_GMAC_UFR (0x40050184U) /**< \brief (GMAC) Undersize Frames Received Register */ + #define REG_GMAC_OFR (0x40050188U) /**< \brief (GMAC) Oversize Frames Received Register */ + #define REG_GMAC_JR (0x4005018CU) /**< \brief (GMAC) Jabbers Received Register */ + #define REG_GMAC_FCSE (0x40050190U) /**< \brief (GMAC) Frame Check Sequence Errors Register */ + #define REG_GMAC_LFFE (0x40050194U) /**< \brief (GMAC) Length Field Frame Errors Register */ + #define REG_GMAC_RSE (0x40050198U) /**< \brief (GMAC) Receive Symbol Errors Register */ + #define REG_GMAC_AE (0x4005019CU) /**< \brief (GMAC) Alignment Errors Register */ + #define REG_GMAC_RRE (0x400501A0U) /**< \brief (GMAC) Receive Resource Errors Register */ + #define REG_GMAC_ROE (0x400501A4U) /**< \brief (GMAC) Receive Overrun Register */ + #define REG_GMAC_IHCE (0x400501A8U) /**< \brief (GMAC) IP Header Checksum Errors Register */ + #define REG_GMAC_TCE (0x400501ACU) /**< \brief (GMAC) TCP Checksum Errors Register */ + #define REG_GMAC_UCE (0x400501B0U) /**< \brief (GMAC) UDP Checksum Errors Register */ + #define REG_GMAC_TISUBN (0x400501BCU) /**< \brief (GMAC) 1588 Timer Increment Sub-nanoseconds Register */ + #define REG_GMAC_TSH (0x400501C0U) /**< \brief (GMAC) 1588 Timer Seconds High Register */ + #define REG_GMAC_TSL (0x400501D0U) /**< \brief (GMAC) 1588 Timer Seconds Low Register */ + #define REG_GMAC_TN (0x400501D4U) /**< \brief (GMAC) 1588 Timer Nanoseconds Register */ + #define REG_GMAC_TA (0x400501D8U) /**< \brief (GMAC) 1588 Timer Adjust Register */ + #define REG_GMAC_TI (0x400501DCU) /**< \brief (GMAC) 1588 Timer Increment Register */ + #define REG_GMAC_EFTSL (0x400501E0U) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds Low Register */ + #define REG_GMAC_EFTN (0x400501E4U) /**< \brief (GMAC) PTP Event Frame Transmitted Nanoseconds Register */ + #define REG_GMAC_EFRSL (0x400501E8U) /**< \brief (GMAC) PTP Event Frame Received Seconds Low Register */ + #define REG_GMAC_EFRN (0x400501ECU) /**< \brief (GMAC) PTP Event Frame Received Nanoseconds Register */ + #define REG_GMAC_PEFTSL (0x400501F0U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds Low Register */ + #define REG_GMAC_PEFTN (0x400501F4U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Nanoseconds Register */ + #define REG_GMAC_PEFRSL (0x400501F8U) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds Low Register */ + #define REG_GMAC_PEFRN (0x400501FCU) /**< \brief (GMAC) PTP Peer Event Frame Received Nanoseconds Register */ + #define REG_GMAC_ISRPQ (0x40050400U) /**< \brief (GMAC) Interrupt Status Register Priority Queue (index = 1) */ + #define REG_GMAC_TBQBAPQ (0x40050440U) /**< \brief (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) */ + #define REG_GMAC_RBQBAPQ (0x40050480U) /**< \brief (GMAC) Receive Buffer Queue Base Address Register Priority Queue (index = 1) */ + #define REG_GMAC_RBSRPQ (0x400504A0U) /**< \brief (GMAC) Receive Buffer Size Register Priority Queue (index = 1) */ + #define REG_GMAC_CBSCR (0x400504BCU) /**< \brief (GMAC) Credit-Based Shaping Control Register */ + #define REG_GMAC_CBSISQA (0x400504C0U) /**< \brief (GMAC) Credit-Based Shaping IdleSlope Register for Queue A */ + #define REG_GMAC_CBSISQB (0x400504C4U) /**< \brief (GMAC) Credit-Based Shaping IdleSlope Register for Queue B */ + #define REG_GMAC_ST1RPQ (0x40050500U) /**< \brief (GMAC) Screening Type 1 Register Priority Queue (index = 0) */ + #define REG_GMAC_ST2RPQ (0x40050540U) /**< \brief (GMAC) Screening Type 2 Register Priority Queue (index = 0) */ + #define REG_GMAC_IERPQ (0x40050600U) /**< \brief (GMAC) Interrupt Enable Register Priority Queue (index = 1) */ + #define REG_GMAC_IDRPQ (0x40050620U) /**< \brief (GMAC) Interrupt Disable Register Priority Queue (index = 1) */ + #define REG_GMAC_IMRPQ (0x40050640U) /**< \brief (GMAC) Interrupt Mask Register Priority Queue (index = 1) */ + #define REG_GMAC_ST2ER (0x400506E0U) /**< \brief (GMAC) Screening Type 2 Ethertype Register (index = 0) */ + #define REG_GMAC_ST2CW00 (0x40050700U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 0) */ + #define REG_GMAC_ST2CW10 (0x40050704U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 0) */ + #define REG_GMAC_ST2CW01 (0x40050708U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 1) */ + #define REG_GMAC_ST2CW11 (0x4005070CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 1) */ + #define REG_GMAC_ST2CW02 (0x40050710U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 2) */ + #define REG_GMAC_ST2CW12 (0x40050714U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 2) */ + #define REG_GMAC_ST2CW03 (0x40050718U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 3) */ + #define REG_GMAC_ST2CW13 (0x4005071CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 3) */ + #define REG_GMAC_ST2CW04 (0x40050720U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 4) */ + #define REG_GMAC_ST2CW14 (0x40050724U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 4) */ + #define REG_GMAC_ST2CW05 (0x40050728U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 5) */ + #define REG_GMAC_ST2CW15 (0x4005072CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 5) */ + #define REG_GMAC_ST2CW06 (0x40050730U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 6) */ + #define REG_GMAC_ST2CW16 (0x40050734U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 6) */ + #define REG_GMAC_ST2CW07 (0x40050738U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 7) */ + #define REG_GMAC_ST2CW17 (0x4005073CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 7) */ + #define REG_GMAC_ST2CW08 (0x40050740U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 8) */ + #define REG_GMAC_ST2CW18 (0x40050744U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 8) */ + #define REG_GMAC_ST2CW09 (0x40050748U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 9) */ + #define REG_GMAC_ST2CW19 (0x4005074CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 9) */ + #define REG_GMAC_ST2CW010 (0x40050750U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 10) */ + #define REG_GMAC_ST2CW110 (0x40050754U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 10) */ + #define REG_GMAC_ST2CW011 (0x40050758U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 11) */ + #define REG_GMAC_ST2CW111 (0x4005075CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 11) */ + #define REG_GMAC_ST2CW012 (0x40050760U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 12) */ + #define REG_GMAC_ST2CW112 (0x40050764U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 12) */ + #define REG_GMAC_ST2CW013 (0x40050768U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 13) */ + #define REG_GMAC_ST2CW113 (0x4005076CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 13) */ + #define REG_GMAC_ST2CW014 (0x40050770U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 14) */ + #define REG_GMAC_ST2CW114 (0x40050774U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 14) */ + #define REG_GMAC_ST2CW015 (0x40050778U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 15) */ + #define REG_GMAC_ST2CW115 (0x4005077CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 15) */ + #define REG_GMAC_ST2CW016 (0x40050780U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 16) */ + #define REG_GMAC_ST2CW116 (0x40050784U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 16) */ + #define REG_GMAC_ST2CW017 (0x40050788U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 17) */ + #define REG_GMAC_ST2CW117 (0x4005078CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 17) */ + #define REG_GMAC_ST2CW018 (0x40050790U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 18) */ + #define REG_GMAC_ST2CW118 (0x40050794U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 18) */ + #define REG_GMAC_ST2CW019 (0x40050798U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 19) */ + #define REG_GMAC_ST2CW119 (0x4005079CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 19) */ + #define REG_GMAC_ST2CW020 (0x400507A0U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 20) */ + #define REG_GMAC_ST2CW120 (0x400507A4U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 20) */ + #define REG_GMAC_ST2CW021 (0x400507A8U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 21) */ + #define REG_GMAC_ST2CW121 (0x400507ACU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 21) */ + #define REG_GMAC_ST2CW022 (0x400507B0U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 22) */ + #define REG_GMAC_ST2CW122 (0x400507B4U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 22) */ + #define REG_GMAC_ST2CW023 (0x400507B8U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 23) */ + #define REG_GMAC_ST2CW123 (0x400507BCU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 23) */ +#else + #define REG_GMAC_NCR (*(__IO uint32_t*)0x40050000U) /**< \brief (GMAC) Network Control Register */ + #define REG_GMAC_NCFGR (*(__IO uint32_t*)0x40050004U) /**< \brief (GMAC) Network Configuration Register */ + #define REG_GMAC_NSR (*(__I uint32_t*)0x40050008U) /**< \brief (GMAC) Network Status Register */ + #define REG_GMAC_UR (*(__IO uint32_t*)0x4005000CU) /**< \brief (GMAC) User Register */ + #define REG_GMAC_DCFGR (*(__IO uint32_t*)0x40050010U) /**< \brief (GMAC) DMA Configuration Register */ + #define REG_GMAC_TSR (*(__IO uint32_t*)0x40050014U) /**< \brief (GMAC) Transmit Status Register */ + #define REG_GMAC_RBQB (*(__IO uint32_t*)0x40050018U) /**< \brief (GMAC) Receive Buffer Queue Base Address Register */ + #define REG_GMAC_TBQB (*(__IO uint32_t*)0x4005001CU) /**< \brief (GMAC) Transmit Buffer Queue Base Address Register */ + #define REG_GMAC_RSR (*(__IO uint32_t*)0x40050020U) /**< \brief (GMAC) Receive Status Register */ + #define REG_GMAC_ISR (*(__I uint32_t*)0x40050024U) /**< \brief (GMAC) Interrupt Status Register */ + #define REG_GMAC_IER (*(__O uint32_t*)0x40050028U) /**< \brief (GMAC) Interrupt Enable Register */ + #define REG_GMAC_IDR (*(__O uint32_t*)0x4005002CU) /**< \brief (GMAC) Interrupt Disable Register */ + #define REG_GMAC_IMR (*(__IO uint32_t*)0x40050030U) /**< \brief (GMAC) Interrupt Mask Register */ + #define REG_GMAC_MAN (*(__IO uint32_t*)0x40050034U) /**< \brief (GMAC) PHY Maintenance Register */ + #define REG_GMAC_RPQ (*(__I uint32_t*)0x40050038U) /**< \brief (GMAC) Received Pause Quantum Register */ + #define REG_GMAC_TPQ (*(__IO uint32_t*)0x4005003CU) /**< \brief (GMAC) Transmit Pause Quantum Register */ + #define REG_GMAC_TPSF (*(__IO uint32_t*)0x40050040U) /**< \brief (GMAC) TX Partial Store and Forward Register */ + #define REG_GMAC_RPSF (*(__IO uint32_t*)0x40050044U) /**< \brief (GMAC) RX Partial Store and Forward Register */ + #define REG_GMAC_RJFML (*(__IO uint32_t*)0x40050048U) /**< \brief (GMAC) RX Jumbo Frame Max Length Register */ + #define REG_GMAC_HRB (*(__IO uint32_t*)0x40050080U) /**< \brief (GMAC) Hash Register Bottom */ + #define REG_GMAC_HRT (*(__IO uint32_t*)0x40050084U) /**< \brief (GMAC) Hash Register Top */ + #define REG_GMAC_SAB1 (*(__IO uint32_t*)0x40050088U) /**< \brief (GMAC) Specific Address 1 Bottom Register */ + #define REG_GMAC_SAT1 (*(__IO uint32_t*)0x4005008CU) /**< \brief (GMAC) Specific Address 1 Top Register */ + #define REG_GMAC_SAB2 (*(__IO uint32_t*)0x40050090U) /**< \brief (GMAC) Specific Address 2 Bottom Register */ + #define REG_GMAC_SAT2 (*(__IO uint32_t*)0x40050094U) /**< \brief (GMAC) Specific Address 2 Top Register */ + #define REG_GMAC_SAB3 (*(__IO uint32_t*)0x40050098U) /**< \brief (GMAC) Specific Address 3 Bottom Register */ + #define REG_GMAC_SAT3 (*(__IO uint32_t*)0x4005009CU) /**< \brief (GMAC) Specific Address 3 Top Register */ + #define REG_GMAC_SAB4 (*(__IO uint32_t*)0x400500A0U) /**< \brief (GMAC) Specific Address 4 Bottom Register */ + #define REG_GMAC_SAT4 (*(__IO uint32_t*)0x400500A4U) /**< \brief (GMAC) Specific Address 4 Top Register */ + #define REG_GMAC_TIDM1 (*(__IO uint32_t*)0x400500A8U) /**< \brief (GMAC) Type ID Match 1 Register */ + #define REG_GMAC_TIDM2 (*(__IO uint32_t*)0x400500ACU) /**< \brief (GMAC) Type ID Match 2 Register */ + #define REG_GMAC_TIDM3 (*(__IO uint32_t*)0x400500B0U) /**< \brief (GMAC) Type ID Match 3 Register */ + #define REG_GMAC_TIDM4 (*(__IO uint32_t*)0x400500B4U) /**< \brief (GMAC) Type ID Match 4 Register */ + #define REG_GMAC_WOL (*(__IO uint32_t*)0x400500B8U) /**< \brief (GMAC) Wake on LAN Register */ + #define REG_GMAC_IPGS (*(__IO uint32_t*)0x400500BCU) /**< \brief (GMAC) IPG Stretch Register */ + #define REG_GMAC_SVLAN (*(__IO uint32_t*)0x400500C0U) /**< \brief (GMAC) Stacked VLAN Register */ + #define REG_GMAC_TPFCP (*(__IO uint32_t*)0x400500C4U) /**< \brief (GMAC) Transmit PFC Pause Register */ + #define REG_GMAC_SAMB1 (*(__IO uint32_t*)0x400500C8U) /**< \brief (GMAC) Specific Address 1 Mask Bottom Register */ + #define REG_GMAC_SAMT1 (*(__IO uint32_t*)0x400500CCU) /**< \brief (GMAC) Specific Address 1 Mask Top Register */ + #define REG_GMAC_NSC (*(__IO uint32_t*)0x400500DCU) /**< \brief (GMAC) 1588 Timer Nanosecond Comparison Register */ + #define REG_GMAC_SCL (*(__IO uint32_t*)0x400500E0U) /**< \brief (GMAC) 1588 Timer Second Comparison Low Register */ + #define REG_GMAC_SCH (*(__IO uint32_t*)0x400500E4U) /**< \brief (GMAC) 1588 Timer Second Comparison High Register */ + #define REG_GMAC_EFTSH (*(__I uint32_t*)0x400500E8U) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds High Register */ + #define REG_GMAC_EFRSH (*(__I uint32_t*)0x400500ECU) /**< \brief (GMAC) PTP Event Frame Received Seconds High Register */ + #define REG_GMAC_PEFTSH (*(__I uint32_t*)0x400500F0U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds High Register */ + #define REG_GMAC_PEFRSH (*(__I uint32_t*)0x400500F4U) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds High Register */ + #define REG_GMAC_OTLO (*(__I uint32_t*)0x40050100U) /**< \brief (GMAC) Octets Transmitted Low Register */ + #define REG_GMAC_OTHI (*(__I uint32_t*)0x40050104U) /**< \brief (GMAC) Octets Transmitted High Register */ + #define REG_GMAC_FT (*(__I uint32_t*)0x40050108U) /**< \brief (GMAC) Frames Transmitted Register */ + #define REG_GMAC_BCFT (*(__I uint32_t*)0x4005010CU) /**< \brief (GMAC) Broadcast Frames Transmitted Register */ + #define REG_GMAC_MFT (*(__I uint32_t*)0x40050110U) /**< \brief (GMAC) Multicast Frames Transmitted Register */ + #define REG_GMAC_PFT (*(__I uint32_t*)0x40050114U) /**< \brief (GMAC) Pause Frames Transmitted Register */ + #define REG_GMAC_BFT64 (*(__I uint32_t*)0x40050118U) /**< \brief (GMAC) 64 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT127 (*(__I uint32_t*)0x4005011CU) /**< \brief (GMAC) 65 to 127 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT255 (*(__I uint32_t*)0x40050120U) /**< \brief (GMAC) 128 to 255 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT511 (*(__I uint32_t*)0x40050124U) /**< \brief (GMAC) 256 to 511 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT1023 (*(__I uint32_t*)0x40050128U) /**< \brief (GMAC) 512 to 1023 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT1518 (*(__I uint32_t*)0x4005012CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Transmitted Register */ + #define REG_GMAC_GTBFT1518 (*(__I uint32_t*)0x40050130U) /**< \brief (GMAC) Greater Than 1518 Byte Frames Transmitted Register */ + #define REG_GMAC_TUR (*(__I uint32_t*)0x40050134U) /**< \brief (GMAC) Transmit Underruns Register */ + #define REG_GMAC_SCF (*(__I uint32_t*)0x40050138U) /**< \brief (GMAC) Single Collision Frames Register */ + #define REG_GMAC_MCF (*(__I uint32_t*)0x4005013CU) /**< \brief (GMAC) Multiple Collision Frames Register */ + #define REG_GMAC_EC (*(__I uint32_t*)0x40050140U) /**< \brief (GMAC) Excessive Collisions Register */ + #define REG_GMAC_LC (*(__I uint32_t*)0x40050144U) /**< \brief (GMAC) Late Collisions Register */ + #define REG_GMAC_DTF (*(__I uint32_t*)0x40050148U) /**< \brief (GMAC) Deferred Transmission Frames Register */ + #define REG_GMAC_CSE (*(__I uint32_t*)0x4005014CU) /**< \brief (GMAC) Carrier Sense Errors Register Register */ + #define REG_GMAC_ORLO (*(__I uint32_t*)0x40050150U) /**< \brief (GMAC) Octets Received Low Received Register */ + #define REG_GMAC_ORHI (*(__I uint32_t*)0x40050154U) /**< \brief (GMAC) Octets Received High Received Register */ + #define REG_GMAC_FR (*(__I uint32_t*)0x40050158U) /**< \brief (GMAC) Frames Received Register */ + #define REG_GMAC_BCFR (*(__I uint32_t*)0x4005015CU) /**< \brief (GMAC) Broadcast Frames Received Register */ + #define REG_GMAC_MFR (*(__I uint32_t*)0x40050160U) /**< \brief (GMAC) Multicast Frames Received Register */ + #define REG_GMAC_PFR (*(__I uint32_t*)0x40050164U) /**< \brief (GMAC) Pause Frames Received Register */ + #define REG_GMAC_BFR64 (*(__I uint32_t*)0x40050168U) /**< \brief (GMAC) 64 Byte Frames Received Register */ + #define REG_GMAC_TBFR127 (*(__I uint32_t*)0x4005016CU) /**< \brief (GMAC) 65 to 127 Byte Frames Received Register */ + #define REG_GMAC_TBFR255 (*(__I uint32_t*)0x40050170U) /**< \brief (GMAC) 128 to 255 Byte Frames Received Register */ + #define REG_GMAC_TBFR511 (*(__I uint32_t*)0x40050174U) /**< \brief (GMAC) 256 to 511 Byte Frames Received Register */ + #define REG_GMAC_TBFR1023 (*(__I uint32_t*)0x40050178U) /**< \brief (GMAC) 512 to 1023 Byte Frames Received Register */ + #define REG_GMAC_TBFR1518 (*(__I uint32_t*)0x4005017CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Received Register */ + #define REG_GMAC_TMXBFR (*(__I uint32_t*)0x40050180U) /**< \brief (GMAC) 1519 to Maximum Byte Frames Received Register */ + #define REG_GMAC_UFR (*(__I uint32_t*)0x40050184U) /**< \brief (GMAC) Undersize Frames Received Register */ + #define REG_GMAC_OFR (*(__I uint32_t*)0x40050188U) /**< \brief (GMAC) Oversize Frames Received Register */ + #define REG_GMAC_JR (*(__I uint32_t*)0x4005018CU) /**< \brief (GMAC) Jabbers Received Register */ + #define REG_GMAC_FCSE (*(__I uint32_t*)0x40050190U) /**< \brief (GMAC) Frame Check Sequence Errors Register */ + #define REG_GMAC_LFFE (*(__I uint32_t*)0x40050194U) /**< \brief (GMAC) Length Field Frame Errors Register */ + #define REG_GMAC_RSE (*(__I uint32_t*)0x40050198U) /**< \brief (GMAC) Receive Symbol Errors Register */ + #define REG_GMAC_AE (*(__I uint32_t*)0x4005019CU) /**< \brief (GMAC) Alignment Errors Register */ + #define REG_GMAC_RRE (*(__I uint32_t*)0x400501A0U) /**< \brief (GMAC) Receive Resource Errors Register */ + #define REG_GMAC_ROE (*(__I uint32_t*)0x400501A4U) /**< \brief (GMAC) Receive Overrun Register */ + #define REG_GMAC_IHCE (*(__I uint32_t*)0x400501A8U) /**< \brief (GMAC) IP Header Checksum Errors Register */ + #define REG_GMAC_TCE (*(__I uint32_t*)0x400501ACU) /**< \brief (GMAC) TCP Checksum Errors Register */ + #define REG_GMAC_UCE (*(__I uint32_t*)0x400501B0U) /**< \brief (GMAC) UDP Checksum Errors Register */ + #define REG_GMAC_TISUBN (*(__IO uint32_t*)0x400501BCU) /**< \brief (GMAC) 1588 Timer Increment Sub-nanoseconds Register */ + #define REG_GMAC_TSH (*(__IO uint32_t*)0x400501C0U) /**< \brief (GMAC) 1588 Timer Seconds High Register */ + #define REG_GMAC_TSL (*(__IO uint32_t*)0x400501D0U) /**< \brief (GMAC) 1588 Timer Seconds Low Register */ + #define REG_GMAC_TN (*(__IO uint32_t*)0x400501D4U) /**< \brief (GMAC) 1588 Timer Nanoseconds Register */ + #define REG_GMAC_TA (*(__O uint32_t*)0x400501D8U) /**< \brief (GMAC) 1588 Timer Adjust Register */ + #define REG_GMAC_TI (*(__IO uint32_t*)0x400501DCU) /**< \brief (GMAC) 1588 Timer Increment Register */ + #define REG_GMAC_EFTSL (*(__I uint32_t*)0x400501E0U) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds Low Register */ + #define REG_GMAC_EFTN (*(__I uint32_t*)0x400501E4U) /**< \brief (GMAC) PTP Event Frame Transmitted Nanoseconds Register */ + #define REG_GMAC_EFRSL (*(__I uint32_t*)0x400501E8U) /**< \brief (GMAC) PTP Event Frame Received Seconds Low Register */ + #define REG_GMAC_EFRN (*(__I uint32_t*)0x400501ECU) /**< \brief (GMAC) PTP Event Frame Received Nanoseconds Register */ + #define REG_GMAC_PEFTSL (*(__I uint32_t*)0x400501F0U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds Low Register */ + #define REG_GMAC_PEFTN (*(__I uint32_t*)0x400501F4U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Nanoseconds Register */ + #define REG_GMAC_PEFRSL (*(__I uint32_t*)0x400501F8U) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds Low Register */ + #define REG_GMAC_PEFRN (*(__I uint32_t*)0x400501FCU) /**< \brief (GMAC) PTP Peer Event Frame Received Nanoseconds Register */ + #define REG_GMAC_ISRPQ (*(__I uint32_t*)0x40050400U) /**< \brief (GMAC) Interrupt Status Register Priority Queue (index = 1) */ + #define REG_GMAC_TBQBAPQ (*(__IO uint32_t*)0x40050440U) /**< \brief (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) */ + #define REG_GMAC_RBQBAPQ (*(__IO uint32_t*)0x40050480U) /**< \brief (GMAC) Receive Buffer Queue Base Address Register Priority Queue (index = 1) */ + #define REG_GMAC_RBSRPQ (*(__IO uint32_t*)0x400504A0U) /**< \brief (GMAC) Receive Buffer Size Register Priority Queue (index = 1) */ + #define REG_GMAC_CBSCR (*(__IO uint32_t*)0x400504BCU) /**< \brief (GMAC) Credit-Based Shaping Control Register */ + #define REG_GMAC_CBSISQA (*(__IO uint32_t*)0x400504C0U) /**< \brief (GMAC) Credit-Based Shaping IdleSlope Register for Queue A */ + #define REG_GMAC_CBSISQB (*(__IO uint32_t*)0x400504C4U) /**< \brief (GMAC) Credit-Based Shaping IdleSlope Register for Queue B */ + #define REG_GMAC_ST1RPQ (*(__IO uint32_t*)0x40050500U) /**< \brief (GMAC) Screening Type 1 Register Priority Queue (index = 0) */ + #define REG_GMAC_ST2RPQ (*(__IO uint32_t*)0x40050540U) /**< \brief (GMAC) Screening Type 2 Register Priority Queue (index = 0) */ + #define REG_GMAC_IERPQ (*(__O uint32_t*)0x40050600U) /**< \brief (GMAC) Interrupt Enable Register Priority Queue (index = 1) */ + #define REG_GMAC_IDRPQ (*(__O uint32_t*)0x40050620U) /**< \brief (GMAC) Interrupt Disable Register Priority Queue (index = 1) */ + #define REG_GMAC_IMRPQ (*(__IO uint32_t*)0x40050640U) /**< \brief (GMAC) Interrupt Mask Register Priority Queue (index = 1) */ + #define REG_GMAC_ST2ER (*(__IO uint32_t*)0x400506E0U) /**< \brief (GMAC) Screening Type 2 Ethertype Register (index = 0) */ + #define REG_GMAC_ST2CW00 (*(__IO uint32_t*)0x40050700U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 0) */ + #define REG_GMAC_ST2CW10 (*(__IO uint32_t*)0x40050704U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 0) */ + #define REG_GMAC_ST2CW01 (*(__IO uint32_t*)0x40050708U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 1) */ + #define REG_GMAC_ST2CW11 (*(__IO uint32_t*)0x4005070CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 1) */ + #define REG_GMAC_ST2CW02 (*(__IO uint32_t*)0x40050710U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 2) */ + #define REG_GMAC_ST2CW12 (*(__IO uint32_t*)0x40050714U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 2) */ + #define REG_GMAC_ST2CW03 (*(__IO uint32_t*)0x40050718U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 3) */ + #define REG_GMAC_ST2CW13 (*(__IO uint32_t*)0x4005071CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 3) */ + #define REG_GMAC_ST2CW04 (*(__IO uint32_t*)0x40050720U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 4) */ + #define REG_GMAC_ST2CW14 (*(__IO uint32_t*)0x40050724U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 4) */ + #define REG_GMAC_ST2CW05 (*(__IO uint32_t*)0x40050728U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 5) */ + #define REG_GMAC_ST2CW15 (*(__IO uint32_t*)0x4005072CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 5) */ + #define REG_GMAC_ST2CW06 (*(__IO uint32_t*)0x40050730U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 6) */ + #define REG_GMAC_ST2CW16 (*(__IO uint32_t*)0x40050734U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 6) */ + #define REG_GMAC_ST2CW07 (*(__IO uint32_t*)0x40050738U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 7) */ + #define REG_GMAC_ST2CW17 (*(__IO uint32_t*)0x4005073CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 7) */ + #define REG_GMAC_ST2CW08 (*(__IO uint32_t*)0x40050740U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 8) */ + #define REG_GMAC_ST2CW18 (*(__IO uint32_t*)0x40050744U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 8) */ + #define REG_GMAC_ST2CW09 (*(__IO uint32_t*)0x40050748U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 9) */ + #define REG_GMAC_ST2CW19 (*(__IO uint32_t*)0x4005074CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 9) */ + #define REG_GMAC_ST2CW010 (*(__IO uint32_t*)0x40050750U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 10) */ + #define REG_GMAC_ST2CW110 (*(__IO uint32_t*)0x40050754U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 10) */ + #define REG_GMAC_ST2CW011 (*(__IO uint32_t*)0x40050758U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 11) */ + #define REG_GMAC_ST2CW111 (*(__IO uint32_t*)0x4005075CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 11) */ + #define REG_GMAC_ST2CW012 (*(__IO uint32_t*)0x40050760U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 12) */ + #define REG_GMAC_ST2CW112 (*(__IO uint32_t*)0x40050764U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 12) */ + #define REG_GMAC_ST2CW013 (*(__IO uint32_t*)0x40050768U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 13) */ + #define REG_GMAC_ST2CW113 (*(__IO uint32_t*)0x4005076CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 13) */ + #define REG_GMAC_ST2CW014 (*(__IO uint32_t*)0x40050770U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 14) */ + #define REG_GMAC_ST2CW114 (*(__IO uint32_t*)0x40050774U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 14) */ + #define REG_GMAC_ST2CW015 (*(__IO uint32_t*)0x40050778U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 15) */ + #define REG_GMAC_ST2CW115 (*(__IO uint32_t*)0x4005077CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 15) */ + #define REG_GMAC_ST2CW016 (*(__IO uint32_t*)0x40050780U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 16) */ + #define REG_GMAC_ST2CW116 (*(__IO uint32_t*)0x40050784U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 16) */ + #define REG_GMAC_ST2CW017 (*(__IO uint32_t*)0x40050788U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 17) */ + #define REG_GMAC_ST2CW117 (*(__IO uint32_t*)0x4005078CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 17) */ + #define REG_GMAC_ST2CW018 (*(__IO uint32_t*)0x40050790U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 18) */ + #define REG_GMAC_ST2CW118 (*(__IO uint32_t*)0x40050794U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 18) */ + #define REG_GMAC_ST2CW019 (*(__IO uint32_t*)0x40050798U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 19) */ + #define REG_GMAC_ST2CW119 (*(__IO uint32_t*)0x4005079CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 19) */ + #define REG_GMAC_ST2CW020 (*(__IO uint32_t*)0x400507A0U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 20) */ + #define REG_GMAC_ST2CW120 (*(__IO uint32_t*)0x400507A4U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 20) */ + #define REG_GMAC_ST2CW021 (*(__IO uint32_t*)0x400507A8U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 21) */ + #define REG_GMAC_ST2CW121 (*(__IO uint32_t*)0x400507ACU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 21) */ + #define REG_GMAC_ST2CW022 (*(__IO uint32_t*)0x400507B0U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 22) */ + #define REG_GMAC_ST2CW122 (*(__IO uint32_t*)0x400507B4U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 22) */ + #define REG_GMAC_ST2CW023 (*(__IO uint32_t*)0x400507B8U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 23) */ + #define REG_GMAC_ST2CW123 (*(__IO uint32_t*)0x400507BCU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 23) */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_GMAC_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_gpbr.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_gpbr.h new file mode 100644 index 00000000..7ecd31e3 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_gpbr.h @@ -0,0 +1,40 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_GPBR_INSTANCE_ +#define _SAMV71_GPBR_INSTANCE_ + +/* ========== Register definition for GPBR peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_GPBR_GPBR (0x400E1890U) /**< \brief (GPBR) General Purpose Backup Register */ +#else + #define REG_GPBR_GPBR (*(__IO uint32_t*)0x400E1890U) /**< \brief (GPBR) General Purpose Backup Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_GPBR_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_hsmci.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_hsmci.h new file mode 100644 index 00000000..8caf067c --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_hsmci.h @@ -0,0 +1,78 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_HSMCI_INSTANCE_ +#define _SAMV71_HSMCI_INSTANCE_ + +/* ========== Register definition for HSMCI peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_HSMCI_CR (0x40000000U) /**< \brief (HSMCI) Control Register */ + #define REG_HSMCI_MR (0x40000004U) /**< \brief (HSMCI) Mode Register */ + #define REG_HSMCI_DTOR (0x40000008U) /**< \brief (HSMCI) Data Timeout Register */ + #define REG_HSMCI_SDCR (0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */ + #define REG_HSMCI_ARGR (0x40000010U) /**< \brief (HSMCI) Argument Register */ + #define REG_HSMCI_CMDR (0x40000014U) /**< \brief (HSMCI) Command Register */ + #define REG_HSMCI_BLKR (0x40000018U) /**< \brief (HSMCI) Block Register */ + #define REG_HSMCI_CSTOR (0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */ + #define REG_HSMCI_RSPR (0x40000020U) /**< \brief (HSMCI) Response Register */ + #define REG_HSMCI_RDR (0x40000030U) /**< \brief (HSMCI) Receive Data Register */ + #define REG_HSMCI_TDR (0x40000034U) /**< \brief (HSMCI) Transmit Data Register */ + #define REG_HSMCI_SR (0x40000040U) /**< \brief (HSMCI) Status Register */ + #define REG_HSMCI_IER (0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */ + #define REG_HSMCI_IDR (0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */ + #define REG_HSMCI_IMR (0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */ + #define REG_HSMCI_DMA (0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */ + #define REG_HSMCI_CFG (0x40000054U) /**< \brief (HSMCI) Configuration Register */ + #define REG_HSMCI_WPMR (0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */ + #define REG_HSMCI_WPSR (0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */ + #define REG_HSMCI_FIFO (0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */ +#else + #define REG_HSMCI_CR (*(__O uint32_t*)0x40000000U) /**< \brief (HSMCI) Control Register */ + #define REG_HSMCI_MR (*(__IO uint32_t*)0x40000004U) /**< \brief (HSMCI) Mode Register */ + #define REG_HSMCI_DTOR (*(__IO uint32_t*)0x40000008U) /**< \brief (HSMCI) Data Timeout Register */ + #define REG_HSMCI_SDCR (*(__IO uint32_t*)0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */ + #define REG_HSMCI_ARGR (*(__IO uint32_t*)0x40000010U) /**< \brief (HSMCI) Argument Register */ + #define REG_HSMCI_CMDR (*(__O uint32_t*)0x40000014U) /**< \brief (HSMCI) Command Register */ + #define REG_HSMCI_BLKR (*(__IO uint32_t*)0x40000018U) /**< \brief (HSMCI) Block Register */ + #define REG_HSMCI_CSTOR (*(__IO uint32_t*)0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */ + #define REG_HSMCI_RSPR (*(__I uint32_t*)0x40000020U) /**< \brief (HSMCI) Response Register */ + #define REG_HSMCI_RDR (*(__I uint32_t*)0x40000030U) /**< \brief (HSMCI) Receive Data Register */ + #define REG_HSMCI_TDR (*(__O uint32_t*)0x40000034U) /**< \brief (HSMCI) Transmit Data Register */ + #define REG_HSMCI_SR (*(__I uint32_t*)0x40000040U) /**< \brief (HSMCI) Status Register */ + #define REG_HSMCI_IER (*(__O uint32_t*)0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */ + #define REG_HSMCI_IDR (*(__O uint32_t*)0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */ + #define REG_HSMCI_IMR (*(__I uint32_t*)0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */ + #define REG_HSMCI_DMA (*(__IO uint32_t*)0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */ + #define REG_HSMCI_CFG (*(__IO uint32_t*)0x40000054U) /**< \brief (HSMCI) Configuration Register */ + #define REG_HSMCI_WPMR (*(__IO uint32_t*)0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */ + #define REG_HSMCI_WPSR (*(__I uint32_t*)0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */ + #define REG_HSMCI_FIFO (*(__IO uint32_t*)0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_HSMCI_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_icm.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_icm.h new file mode 100644 index 00000000..c5ea9bdb --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_icm.h @@ -0,0 +1,60 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_ICM_INSTANCE_ +#define _SAMV71_ICM_INSTANCE_ + +/* ========== Register definition for ICM peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_ICM_CFG (0x40048000U) /**< \brief (ICM) Configuration Register */ + #define REG_ICM_CTRL (0x40048004U) /**< \brief (ICM) Control Register */ + #define REG_ICM_SR (0x40048008U) /**< \brief (ICM) Status Register */ + #define REG_ICM_IER (0x40048010U) /**< \brief (ICM) Interrupt Enable Register */ + #define REG_ICM_IDR (0x40048014U) /**< \brief (ICM) Interrupt Disable Register */ + #define REG_ICM_IMR (0x40048018U) /**< \brief (ICM) Interrupt Mask Register */ + #define REG_ICM_ISR (0x4004801CU) /**< \brief (ICM) Interrupt Status Register */ + #define REG_ICM_UASR (0x40048020U) /**< \brief (ICM) Undefined Access Status Register */ + #define REG_ICM_DSCR (0x40048030U) /**< \brief (ICM) Region Descriptor Area Start Address Register */ + #define REG_ICM_HASH (0x40048034U) /**< \brief (ICM) Region Hash Area Start Address Register */ + #define REG_ICM_UIHVAL (0x40048038U) /**< \brief (ICM) User Initial Hash Value 0 Register */ +#else + #define REG_ICM_CFG (*(__IO uint32_t*)0x40048000U) /**< \brief (ICM) Configuration Register */ + #define REG_ICM_CTRL (*(__O uint32_t*)0x40048004U) /**< \brief (ICM) Control Register */ + #define REG_ICM_SR (*(__O uint32_t*)0x40048008U) /**< \brief (ICM) Status Register */ + #define REG_ICM_IER (*(__O uint32_t*)0x40048010U) /**< \brief (ICM) Interrupt Enable Register */ + #define REG_ICM_IDR (*(__O uint32_t*)0x40048014U) /**< \brief (ICM) Interrupt Disable Register */ + #define REG_ICM_IMR (*(__I uint32_t*)0x40048018U) /**< \brief (ICM) Interrupt Mask Register */ + #define REG_ICM_ISR (*(__I uint32_t*)0x4004801CU) /**< \brief (ICM) Interrupt Status Register */ + #define REG_ICM_UASR (*(__I uint32_t*)0x40048020U) /**< \brief (ICM) Undefined Access Status Register */ + #define REG_ICM_DSCR (*(__IO uint32_t*)0x40048030U) /**< \brief (ICM) Region Descriptor Area Start Address Register */ + #define REG_ICM_HASH (*(__IO uint32_t*)0x40048034U) /**< \brief (ICM) Region Hash Area Start Address Register */ + #define REG_ICM_UIHVAL (*(__O uint32_t*)0x40048038U) /**< \brief (ICM) User Initial Hash Value 0 Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_ICM_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_isi.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_isi.h new file mode 100644 index 00000000..10f75b0d --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_isi.h @@ -0,0 +1,88 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_ISI_INSTANCE_ +#define _SAMV71_ISI_INSTANCE_ + +/* ========== Register definition for ISI peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_ISI_CFG1 (0x4004C000U) /**< \brief (ISI) ISI Configuration 1 Register */ + #define REG_ISI_CFG2 (0x4004C004U) /**< \brief (ISI) ISI Configuration 2 Register */ + #define REG_ISI_PSIZE (0x4004C008U) /**< \brief (ISI) ISI Preview Size Register */ + #define REG_ISI_PDECF (0x4004C00CU) /**< \brief (ISI) ISI Preview Decimation Factor Register */ + #define REG_ISI_Y2R_SET0 (0x4004C010U) /**< \brief (ISI) ISI Color Space Conversion YCrCb To RGB Set 0 Register */ + #define REG_ISI_Y2R_SET1 (0x4004C014U) /**< \brief (ISI) ISI Color Space Conversion YCrCb To RGB Set 1 Register */ + #define REG_ISI_R2Y_SET0 (0x4004C018U) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 0 Register */ + #define REG_ISI_R2Y_SET1 (0x4004C01CU) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 1 Register */ + #define REG_ISI_R2Y_SET2 (0x4004C020U) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 2 Register */ + #define REG_ISI_CR (0x4004C024U) /**< \brief (ISI) ISI Control Register */ + #define REG_ISI_SR (0x4004C028U) /**< \brief (ISI) ISI Status Register */ + #define REG_ISI_IER (0x4004C02CU) /**< \brief (ISI) ISI Interrupt Enable Register */ + #define REG_ISI_IDR (0x4004C030U) /**< \brief (ISI) ISI Interrupt Disable Register */ + #define REG_ISI_IMR (0x4004C034U) /**< \brief (ISI) ISI Interrupt Mask Register */ + #define REG_ISI_DMA_CHER (0x4004C038U) /**< \brief (ISI) DMA Channel Enable Register */ + #define REG_ISI_DMA_CHDR (0x4004C03CU) /**< \brief (ISI) DMA Channel Disable Register */ + #define REG_ISI_DMA_CHSR (0x4004C040U) /**< \brief (ISI) DMA Channel Status Register */ + #define REG_ISI_DMA_P_ADDR (0x4004C044U) /**< \brief (ISI) DMA Preview Base Address Register */ + #define REG_ISI_DMA_P_CTRL (0x4004C048U) /**< \brief (ISI) DMA Preview Control Register */ + #define REG_ISI_DMA_P_DSCR (0x4004C04CU) /**< \brief (ISI) DMA Preview Descriptor Address Register */ + #define REG_ISI_DMA_C_ADDR (0x4004C050U) /**< \brief (ISI) DMA Codec Base Address Register */ + #define REG_ISI_DMA_C_CTRL (0x4004C054U) /**< \brief (ISI) DMA Codec Control Register */ + #define REG_ISI_DMA_C_DSCR (0x4004C058U) /**< \brief (ISI) DMA Codec Descriptor Address Register */ + #define REG_ISI_WPMR (0x4004C0E4U) /**< \brief (ISI) Write Protection Mode Register */ + #define REG_ISI_WPSR (0x4004C0E8U) /**< \brief (ISI) Write Protection Status Register */ +#else + #define REG_ISI_CFG1 (*(__IO uint32_t*)0x4004C000U) /**< \brief (ISI) ISI Configuration 1 Register */ + #define REG_ISI_CFG2 (*(__IO uint32_t*)0x4004C004U) /**< \brief (ISI) ISI Configuration 2 Register */ + #define REG_ISI_PSIZE (*(__IO uint32_t*)0x4004C008U) /**< \brief (ISI) ISI Preview Size Register */ + #define REG_ISI_PDECF (*(__IO uint32_t*)0x4004C00CU) /**< \brief (ISI) ISI Preview Decimation Factor Register */ + #define REG_ISI_Y2R_SET0 (*(__IO uint32_t*)0x4004C010U) /**< \brief (ISI) ISI Color Space Conversion YCrCb To RGB Set 0 Register */ + #define REG_ISI_Y2R_SET1 (*(__IO uint32_t*)0x4004C014U) /**< \brief (ISI) ISI Color Space Conversion YCrCb To RGB Set 1 Register */ + #define REG_ISI_R2Y_SET0 (*(__IO uint32_t*)0x4004C018U) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 0 Register */ + #define REG_ISI_R2Y_SET1 (*(__IO uint32_t*)0x4004C01CU) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 1 Register */ + #define REG_ISI_R2Y_SET2 (*(__IO uint32_t*)0x4004C020U) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 2 Register */ + #define REG_ISI_CR (*(__O uint32_t*)0x4004C024U) /**< \brief (ISI) ISI Control Register */ + #define REG_ISI_SR (*(__I uint32_t*)0x4004C028U) /**< \brief (ISI) ISI Status Register */ + #define REG_ISI_IER (*(__O uint32_t*)0x4004C02CU) /**< \brief (ISI) ISI Interrupt Enable Register */ + #define REG_ISI_IDR (*(__O uint32_t*)0x4004C030U) /**< \brief (ISI) ISI Interrupt Disable Register */ + #define REG_ISI_IMR (*(__I uint32_t*)0x4004C034U) /**< \brief (ISI) ISI Interrupt Mask Register */ + #define REG_ISI_DMA_CHER (*(__O uint32_t*)0x4004C038U) /**< \brief (ISI) DMA Channel Enable Register */ + #define REG_ISI_DMA_CHDR (*(__O uint32_t*)0x4004C03CU) /**< \brief (ISI) DMA Channel Disable Register */ + #define REG_ISI_DMA_CHSR (*(__I uint32_t*)0x4004C040U) /**< \brief (ISI) DMA Channel Status Register */ + #define REG_ISI_DMA_P_ADDR (*(__IO uint32_t*)0x4004C044U) /**< \brief (ISI) DMA Preview Base Address Register */ + #define REG_ISI_DMA_P_CTRL (*(__IO uint32_t*)0x4004C048U) /**< \brief (ISI) DMA Preview Control Register */ + #define REG_ISI_DMA_P_DSCR (*(__IO uint32_t*)0x4004C04CU) /**< \brief (ISI) DMA Preview Descriptor Address Register */ + #define REG_ISI_DMA_C_ADDR (*(__IO uint32_t*)0x4004C050U) /**< \brief (ISI) DMA Codec Base Address Register */ + #define REG_ISI_DMA_C_CTRL (*(__IO uint32_t*)0x4004C054U) /**< \brief (ISI) DMA Codec Control Register */ + #define REG_ISI_DMA_C_DSCR (*(__IO uint32_t*)0x4004C058U) /**< \brief (ISI) DMA Codec Descriptor Address Register */ + #define REG_ISI_WPMR (*(__IO uint32_t*)0x4004C0E4U) /**< \brief (ISI) Write Protection Mode Register */ + #define REG_ISI_WPSR (*(__I uint32_t*)0x4004C0E8U) /**< \brief (ISI) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_ISI_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_matrix.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_matrix.h new file mode 100644 index 00000000..5e35df82 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_matrix.h @@ -0,0 +1,90 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_MATRIX_INSTANCE_ +#define _SAMV71_MATRIX_INSTANCE_ + +/* ========== Register definition for MATRIX peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_MATRIX_MCFG (0x40088000U) /**< \brief (MATRIX) Master Configuration Register */ + #define REG_MATRIX_SCFG (0x40088040U) /**< \brief (MATRIX) Slave Configuration Register */ + #define REG_MATRIX_PRAS0 (0x40088080U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ + #define REG_MATRIX_PRBS0 (0x40088084U) /**< \brief (MATRIX) Priority Register B for Slave 0 */ + #define REG_MATRIX_PRAS1 (0x40088088U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ + #define REG_MATRIX_PRBS1 (0x4008808CU) /**< \brief (MATRIX) Priority Register B for Slave 1 */ + #define REG_MATRIX_PRAS2 (0x40088090U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ + #define REG_MATRIX_PRBS2 (0x40088094U) /**< \brief (MATRIX) Priority Register B for Slave 2 */ + #define REG_MATRIX_PRAS3 (0x40088098U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ + #define REG_MATRIX_PRBS3 (0x4008809CU) /**< \brief (MATRIX) Priority Register B for Slave 3 */ + #define REG_MATRIX_PRAS4 (0x400880A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ + #define REG_MATRIX_PRBS4 (0x400880A4U) /**< \brief (MATRIX) Priority Register B for Slave 4 */ + #define REG_MATRIX_PRAS5 (0x400880A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */ + #define REG_MATRIX_PRBS5 (0x400880ACU) /**< \brief (MATRIX) Priority Register B for Slave 5 */ + #define REG_MATRIX_PRAS6 (0x400880B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */ + #define REG_MATRIX_PRBS6 (0x400880B4U) /**< \brief (MATRIX) Priority Register B for Slave 6 */ + #define REG_MATRIX_PRAS7 (0x400880B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */ + #define REG_MATRIX_PRBS7 (0x400880BCU) /**< \brief (MATRIX) Priority Register B for Slave 7 */ + #define REG_MATRIX_PRAS8 (0x400880C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */ + #define REG_MATRIX_PRBS8 (0x400880C4U) /**< \brief (MATRIX) Priority Register B for Slave 8 */ + #define REG_MATRIX_MRCR (0x40088100U) /**< \brief (MATRIX) Master Remap Control Register */ + #define REG_CCFG_CAN0 (0x40088110U) /**< \brief (MATRIX) CAN0 Configuration Register */ + #define REG_CCFG_SYSIO (0x40088114U) /**< \brief (MATRIX) System I/O and CAN1 Configuration Register */ + #define REG_CCFG_SMCNFCS (0x40088124U) /**< \brief (MATRIX) SMC NAND Flash Chip Select Configuration Register */ + #define REG_MATRIX_WPMR (0x400881E4U) /**< \brief (MATRIX) Write Protection Mode Register */ + #define REG_MATRIX_WPSR (0x400881E8U) /**< \brief (MATRIX) Write Protection Status Register */ +#else + #define REG_MATRIX_MCFG (*(__IO uint32_t*)0x40088000U) /**< \brief (MATRIX) Master Configuration Register */ + #define REG_MATRIX_SCFG (*(__IO uint32_t*)0x40088040U) /**< \brief (MATRIX) Slave Configuration Register */ + #define REG_MATRIX_PRAS0 (*(__IO uint32_t*)0x40088080U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ + #define REG_MATRIX_PRBS0 (*(__IO uint32_t*)0x40088084U) /**< \brief (MATRIX) Priority Register B for Slave 0 */ + #define REG_MATRIX_PRAS1 (*(__IO uint32_t*)0x40088088U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ + #define REG_MATRIX_PRBS1 (*(__IO uint32_t*)0x4008808CU) /**< \brief (MATRIX) Priority Register B for Slave 1 */ + #define REG_MATRIX_PRAS2 (*(__IO uint32_t*)0x40088090U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ + #define REG_MATRIX_PRBS2 (*(__IO uint32_t*)0x40088094U) /**< \brief (MATRIX) Priority Register B for Slave 2 */ + #define REG_MATRIX_PRAS3 (*(__IO uint32_t*)0x40088098U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ + #define REG_MATRIX_PRBS3 (*(__IO uint32_t*)0x4008809CU) /**< \brief (MATRIX) Priority Register B for Slave 3 */ + #define REG_MATRIX_PRAS4 (*(__IO uint32_t*)0x400880A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ + #define REG_MATRIX_PRBS4 (*(__IO uint32_t*)0x400880A4U) /**< \brief (MATRIX) Priority Register B for Slave 4 */ + #define REG_MATRIX_PRAS5 (*(__IO uint32_t*)0x400880A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */ + #define REG_MATRIX_PRBS5 (*(__IO uint32_t*)0x400880ACU) /**< \brief (MATRIX) Priority Register B for Slave 5 */ + #define REG_MATRIX_PRAS6 (*(__IO uint32_t*)0x400880B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */ + #define REG_MATRIX_PRBS6 (*(__IO uint32_t*)0x400880B4U) /**< \brief (MATRIX) Priority Register B for Slave 6 */ + #define REG_MATRIX_PRAS7 (*(__IO uint32_t*)0x400880B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */ + #define REG_MATRIX_PRBS7 (*(__IO uint32_t*)0x400880BCU) /**< \brief (MATRIX) Priority Register B for Slave 7 */ + #define REG_MATRIX_PRAS8 (*(__IO uint32_t*)0x400880C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */ + #define REG_MATRIX_PRBS8 (*(__IO uint32_t*)0x400880C4U) /**< \brief (MATRIX) Priority Register B for Slave 8 */ + #define REG_MATRIX_MRCR (*(__IO uint32_t*)0x40088100U) /**< \brief (MATRIX) Master Remap Control Register */ + #define REG_CCFG_CAN0 (*(__IO uint32_t*)0x40088110U) /**< \brief (MATRIX) CAN0 Configuration Register */ + #define REG_CCFG_SYSIO (*(__IO uint32_t*)0x40088114U) /**< \brief (MATRIX) System I/O and CAN1 Configuration Register */ + #define REG_CCFG_SMCNFCS (*(__IO uint32_t*)0x40088124U) /**< \brief (MATRIX) SMC NAND Flash Chip Select Configuration Register */ + #define REG_MATRIX_WPMR (*(__IO uint32_t*)0x400881E4U) /**< \brief (MATRIX) Write Protection Mode Register */ + #define REG_MATRIX_WPSR (*(__I uint32_t*)0x400881E8U) /**< \brief (MATRIX) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_MATRIX_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_mcan0.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_mcan0.h new file mode 100644 index 00000000..480ee3ab --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_mcan0.h @@ -0,0 +1,126 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_MCAN0_INSTANCE_ +#define _SAMV71_MCAN0_INSTANCE_ + +/* ========== Register definition for MCAN0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_MCAN0_CUST (0x40030008U) /**< \brief (MCAN0) Customer Register */ + #define REG_MCAN0_FBTP (0x4003000CU) /**< \brief (MCAN0) Fast Bit Timing and Prescaler Register */ + #define REG_MCAN0_TEST (0x40030010U) /**< \brief (MCAN0) Test Register */ + #define REG_MCAN0_RWD (0x40030014U) /**< \brief (MCAN0) RAM Watchdog Register */ + #define REG_MCAN0_CCCR (0x40030018U) /**< \brief (MCAN0) CC Control Register */ + #define REG_MCAN0_BTP (0x4003001CU) /**< \brief (MCAN0) Bit Timing and Prescaler Register */ + #define REG_MCAN0_TSCC (0x40030020U) /**< \brief (MCAN0) Timestamp Counter Configuration Register */ + #define REG_MCAN0_TSCV (0x40030024U) /**< \brief (MCAN0) Timestamp Counter Value Register */ + #define REG_MCAN0_TOCC (0x40030028U) /**< \brief (MCAN0) Timeout Counter Configuration Register */ + #define REG_MCAN0_TOCV (0x4003002CU) /**< \brief (MCAN0) Timeout Counter Value Register */ + #define REG_MCAN0_ECR (0x40030040U) /**< \brief (MCAN0) Error Counter Register */ + #define REG_MCAN0_PSR (0x40030044U) /**< \brief (MCAN0) Protocol Status Register */ + #define REG_MCAN0_IR (0x40030050U) /**< \brief (MCAN0) Interrupt Register */ + #define REG_MCAN0_IE (0x40030054U) /**< \brief (MCAN0) Interrupt Enable Register */ + #define REG_MCAN0_ILS (0x40030058U) /**< \brief (MCAN0) Interrupt Line Select Register */ + #define REG_MCAN0_ILE (0x4003005CU) /**< \brief (MCAN0) Interrupt Line Enable Register */ + #define REG_MCAN0_GFC (0x40030080U) /**< \brief (MCAN0) Global Filter Configuration Register */ + #define REG_MCAN0_SIDFC (0x40030084U) /**< \brief (MCAN0) Standard ID Filter Configuration Register */ + #define REG_MCAN0_XIDFC (0x40030088U) /**< \brief (MCAN0) Extended ID Filter Configuration Register */ + #define REG_MCAN0_XIDAM (0x40030090U) /**< \brief (MCAN0) Extended ID AND Mask Register */ + #define REG_MCAN0_HPMS (0x40030094U) /**< \brief (MCAN0) High Priority Message Status Register */ + #define REG_MCAN0_NDAT1 (0x40030098U) /**< \brief (MCAN0) New Data 1 Register */ + #define REG_MCAN0_NDAT2 (0x4003009CU) /**< \brief (MCAN0) New Data 2 Register */ + #define REG_MCAN0_RXF0C (0x400300A0U) /**< \brief (MCAN0) Receive FIFO 0 Configuration Register */ + #define REG_MCAN0_RXF0S (0x400300A4U) /**< \brief (MCAN0) Receive FIFO 0 Status Register */ + #define REG_MCAN0_RXF0A (0x400300A8U) /**< \brief (MCAN0) Receive FIFO 0 Acknowledge Register */ + #define REG_MCAN0_RXBC (0x400300ACU) /**< \brief (MCAN0) Receive Rx Buffer Configuration Register */ + #define REG_MCAN0_RXF1C (0x400300B0U) /**< \brief (MCAN0) Receive FIFO 1 Configuration Register */ + #define REG_MCAN0_RXF1S (0x400300B4U) /**< \brief (MCAN0) Receive FIFO 1 Status Register */ + #define REG_MCAN0_RXF1A (0x400300B8U) /**< \brief (MCAN0) Receive FIFO 1 Acknowledge Register */ + #define REG_MCAN0_RXESC (0x400300BCU) /**< \brief (MCAN0) Receive Buffer / FIFO Element Size Configuration Register */ + #define REG_MCAN0_TXBC (0x400300C0U) /**< \brief (MCAN0) Transmit Buffer Configuration Register */ + #define REG_MCAN0_TXFQS (0x400300C4U) /**< \brief (MCAN0) Transmit FIFO/Queue Status Register */ + #define REG_MCAN0_TXESC (0x400300C8U) /**< \brief (MCAN0) Transmit Buffer Element Size Configuration Register */ + #define REG_MCAN0_TXBRP (0x400300CCU) /**< \brief (MCAN0) Transmit Buffer Request Pending Register */ + #define REG_MCAN0_TXBAR (0x400300D0U) /**< \brief (MCAN0) Transmit Buffer Add Request Register */ + #define REG_MCAN0_TXBCR (0x400300D4U) /**< \brief (MCAN0) Transmit Buffer Cancellation Request Register */ + #define REG_MCAN0_TXBTO (0x400300D8U) /**< \brief (MCAN0) Transmit Buffer Transmission Occurred Register */ + #define REG_MCAN0_TXBCF (0x400300DCU) /**< \brief (MCAN0) Transmit Buffer Cancellation Finished Register */ + #define REG_MCAN0_TXBTIE (0x400300E0U) /**< \brief (MCAN0) Transmit Buffer Transmission Interrupt Enable Register */ + #define REG_MCAN0_TXBCIE (0x400300E4U) /**< \brief (MCAN0) Transmit Buffer Cancellation Finished Interrupt Enable Register */ + #define REG_MCAN0_TXEFC (0x400300F0U) /**< \brief (MCAN0) Transmit Event FIFO Configuration Register */ + #define REG_MCAN0_TXEFS (0x400300F4U) /**< \brief (MCAN0) Transmit Event FIFO Status Register */ + #define REG_MCAN0_TXEFA (0x400300F8U) /**< \brief (MCAN0) Transmit Event FIFO Acknowledge Register */ +#else + #define REG_MCAN0_CUST (*(__IO uint32_t*)0x40030008U) /**< \brief (MCAN0) Customer Register */ + #define REG_MCAN0_FBTP (*(__IO uint32_t*)0x4003000CU) /**< \brief (MCAN0) Fast Bit Timing and Prescaler Register */ + #define REG_MCAN0_TEST (*(__IO uint32_t*)0x40030010U) /**< \brief (MCAN0) Test Register */ + #define REG_MCAN0_RWD (*(__IO uint32_t*)0x40030014U) /**< \brief (MCAN0) RAM Watchdog Register */ + #define REG_MCAN0_CCCR (*(__IO uint32_t*)0x40030018U) /**< \brief (MCAN0) CC Control Register */ + #define REG_MCAN0_BTP (*(__IO uint32_t*)0x4003001CU) /**< \brief (MCAN0) Bit Timing and Prescaler Register */ + #define REG_MCAN0_TSCC (*(__IO uint32_t*)0x40030020U) /**< \brief (MCAN0) Timestamp Counter Configuration Register */ + #define REG_MCAN0_TSCV (*(__IO uint32_t*)0x40030024U) /**< \brief (MCAN0) Timestamp Counter Value Register */ + #define REG_MCAN0_TOCC (*(__IO uint32_t*)0x40030028U) /**< \brief (MCAN0) Timeout Counter Configuration Register */ + #define REG_MCAN0_TOCV (*(__IO uint32_t*)0x4003002CU) /**< \brief (MCAN0) Timeout Counter Value Register */ + #define REG_MCAN0_ECR (*(__I uint32_t*)0x40030040U) /**< \brief (MCAN0) Error Counter Register */ + #define REG_MCAN0_PSR (*(__I uint32_t*)0x40030044U) /**< \brief (MCAN0) Protocol Status Register */ + #define REG_MCAN0_IR (*(__IO uint32_t*)0x40030050U) /**< \brief (MCAN0) Interrupt Register */ + #define REG_MCAN0_IE (*(__IO uint32_t*)0x40030054U) /**< \brief (MCAN0) Interrupt Enable Register */ + #define REG_MCAN0_ILS (*(__IO uint32_t*)0x40030058U) /**< \brief (MCAN0) Interrupt Line Select Register */ + #define REG_MCAN0_ILE (*(__IO uint32_t*)0x4003005CU) /**< \brief (MCAN0) Interrupt Line Enable Register */ + #define REG_MCAN0_GFC (*(__IO uint32_t*)0x40030080U) /**< \brief (MCAN0) Global Filter Configuration Register */ + #define REG_MCAN0_SIDFC (*(__IO uint32_t*)0x40030084U) /**< \brief (MCAN0) Standard ID Filter Configuration Register */ + #define REG_MCAN0_XIDFC (*(__IO uint32_t*)0x40030088U) /**< \brief (MCAN0) Extended ID Filter Configuration Register */ + #define REG_MCAN0_XIDAM (*(__IO uint32_t*)0x40030090U) /**< \brief (MCAN0) Extended ID AND Mask Register */ + #define REG_MCAN0_HPMS (*(__I uint32_t*)0x40030094U) /**< \brief (MCAN0) High Priority Message Status Register */ + #define REG_MCAN0_NDAT1 (*(__IO uint32_t*)0x40030098U) /**< \brief (MCAN0) New Data 1 Register */ + #define REG_MCAN0_NDAT2 (*(__IO uint32_t*)0x4003009CU) /**< \brief (MCAN0) New Data 2 Register */ + #define REG_MCAN0_RXF0C (*(__IO uint32_t*)0x400300A0U) /**< \brief (MCAN0) Receive FIFO 0 Configuration Register */ + #define REG_MCAN0_RXF0S (*(__I uint32_t*)0x400300A4U) /**< \brief (MCAN0) Receive FIFO 0 Status Register */ + #define REG_MCAN0_RXF0A (*(__IO uint32_t*)0x400300A8U) /**< \brief (MCAN0) Receive FIFO 0 Acknowledge Register */ + #define REG_MCAN0_RXBC (*(__IO uint32_t*)0x400300ACU) /**< \brief (MCAN0) Receive Rx Buffer Configuration Register */ + #define REG_MCAN0_RXF1C (*(__IO uint32_t*)0x400300B0U) /**< \brief (MCAN0) Receive FIFO 1 Configuration Register */ + #define REG_MCAN0_RXF1S (*(__I uint32_t*)0x400300B4U) /**< \brief (MCAN0) Receive FIFO 1 Status Register */ + #define REG_MCAN0_RXF1A (*(__IO uint32_t*)0x400300B8U) /**< \brief (MCAN0) Receive FIFO 1 Acknowledge Register */ + #define REG_MCAN0_RXESC (*(__IO uint32_t*)0x400300BCU) /**< \brief (MCAN0) Receive Buffer / FIFO Element Size Configuration Register */ + #define REG_MCAN0_TXBC (*(__IO uint32_t*)0x400300C0U) /**< \brief (MCAN0) Transmit Buffer Configuration Register */ + #define REG_MCAN0_TXFQS (*(__I uint32_t*)0x400300C4U) /**< \brief (MCAN0) Transmit FIFO/Queue Status Register */ + #define REG_MCAN0_TXESC (*(__IO uint32_t*)0x400300C8U) /**< \brief (MCAN0) Transmit Buffer Element Size Configuration Register */ + #define REG_MCAN0_TXBRP (*(__I uint32_t*)0x400300CCU) /**< \brief (MCAN0) Transmit Buffer Request Pending Register */ + #define REG_MCAN0_TXBAR (*(__IO uint32_t*)0x400300D0U) /**< \brief (MCAN0) Transmit Buffer Add Request Register */ + #define REG_MCAN0_TXBCR (*(__IO uint32_t*)0x400300D4U) /**< \brief (MCAN0) Transmit Buffer Cancellation Request Register */ + #define REG_MCAN0_TXBTO (*(__I uint32_t*)0x400300D8U) /**< \brief (MCAN0) Transmit Buffer Transmission Occurred Register */ + #define REG_MCAN0_TXBCF (*(__I uint32_t*)0x400300DCU) /**< \brief (MCAN0) Transmit Buffer Cancellation Finished Register */ + #define REG_MCAN0_TXBTIE (*(__IO uint32_t*)0x400300E0U) /**< \brief (MCAN0) Transmit Buffer Transmission Interrupt Enable Register */ + #define REG_MCAN0_TXBCIE (*(__IO uint32_t*)0x400300E4U) /**< \brief (MCAN0) Transmit Buffer Cancellation Finished Interrupt Enable Register */ + #define REG_MCAN0_TXEFC (*(__IO uint32_t*)0x400300F0U) /**< \brief (MCAN0) Transmit Event FIFO Configuration Register */ + #define REG_MCAN0_TXEFS (*(__I uint32_t*)0x400300F4U) /**< \brief (MCAN0) Transmit Event FIFO Status Register */ + #define REG_MCAN0_TXEFA (*(__IO uint32_t*)0x400300F8U) /**< \brief (MCAN0) Transmit Event FIFO Acknowledge Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_MCAN0_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_mcan1.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_mcan1.h new file mode 100644 index 00000000..6cac21c2 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_mcan1.h @@ -0,0 +1,126 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_MCAN1_INSTANCE_ +#define _SAMV71_MCAN1_INSTANCE_ + +/* ========== Register definition for MCAN1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_MCAN1_CUST (0x40034008U) /**< \brief (MCAN1) Customer Register */ + #define REG_MCAN1_FBTP (0x4003400CU) /**< \brief (MCAN1) Fast Bit Timing and Prescaler Register */ + #define REG_MCAN1_TEST (0x40034010U) /**< \brief (MCAN1) Test Register */ + #define REG_MCAN1_RWD (0x40034014U) /**< \brief (MCAN1) RAM Watchdog Register */ + #define REG_MCAN1_CCCR (0x40034018U) /**< \brief (MCAN1) CC Control Register */ + #define REG_MCAN1_BTP (0x4003401CU) /**< \brief (MCAN1) Bit Timing and Prescaler Register */ + #define REG_MCAN1_TSCC (0x40034020U) /**< \brief (MCAN1) Timestamp Counter Configuration Register */ + #define REG_MCAN1_TSCV (0x40034024U) /**< \brief (MCAN1) Timestamp Counter Value Register */ + #define REG_MCAN1_TOCC (0x40034028U) /**< \brief (MCAN1) Timeout Counter Configuration Register */ + #define REG_MCAN1_TOCV (0x4003402CU) /**< \brief (MCAN1) Timeout Counter Value Register */ + #define REG_MCAN1_ECR (0x40034040U) /**< \brief (MCAN1) Error Counter Register */ + #define REG_MCAN1_PSR (0x40034044U) /**< \brief (MCAN1) Protocol Status Register */ + #define REG_MCAN1_IR (0x40034050U) /**< \brief (MCAN1) Interrupt Register */ + #define REG_MCAN1_IE (0x40034054U) /**< \brief (MCAN1) Interrupt Enable Register */ + #define REG_MCAN1_ILS (0x40034058U) /**< \brief (MCAN1) Interrupt Line Select Register */ + #define REG_MCAN1_ILE (0x4003405CU) /**< \brief (MCAN1) Interrupt Line Enable Register */ + #define REG_MCAN1_GFC (0x40034080U) /**< \brief (MCAN1) Global Filter Configuration Register */ + #define REG_MCAN1_SIDFC (0x40034084U) /**< \brief (MCAN1) Standard ID Filter Configuration Register */ + #define REG_MCAN1_XIDFC (0x40034088U) /**< \brief (MCAN1) Extended ID Filter Configuration Register */ + #define REG_MCAN1_XIDAM (0x40034090U) /**< \brief (MCAN1) Extended ID AND Mask Register */ + #define REG_MCAN1_HPMS (0x40034094U) /**< \brief (MCAN1) High Priority Message Status Register */ + #define REG_MCAN1_NDAT1 (0x40034098U) /**< \brief (MCAN1) New Data 1 Register */ + #define REG_MCAN1_NDAT2 (0x4003409CU) /**< \brief (MCAN1) New Data 2 Register */ + #define REG_MCAN1_RXF0C (0x400340A0U) /**< \brief (MCAN1) Receive FIFO 0 Configuration Register */ + #define REG_MCAN1_RXF0S (0x400340A4U) /**< \brief (MCAN1) Receive FIFO 0 Status Register */ + #define REG_MCAN1_RXF0A (0x400340A8U) /**< \brief (MCAN1) Receive FIFO 0 Acknowledge Register */ + #define REG_MCAN1_RXBC (0x400340ACU) /**< \brief (MCAN1) Receive Rx Buffer Configuration Register */ + #define REG_MCAN1_RXF1C (0x400340B0U) /**< \brief (MCAN1) Receive FIFO 1 Configuration Register */ + #define REG_MCAN1_RXF1S (0x400340B4U) /**< \brief (MCAN1) Receive FIFO 1 Status Register */ + #define REG_MCAN1_RXF1A (0x400340B8U) /**< \brief (MCAN1) Receive FIFO 1 Acknowledge Register */ + #define REG_MCAN1_RXESC (0x400340BCU) /**< \brief (MCAN1) Receive Buffer / FIFO Element Size Configuration Register */ + #define REG_MCAN1_TXBC (0x400340C0U) /**< \brief (MCAN1) Transmit Buffer Configuration Register */ + #define REG_MCAN1_TXFQS (0x400340C4U) /**< \brief (MCAN1) Transmit FIFO/Queue Status Register */ + #define REG_MCAN1_TXESC (0x400340C8U) /**< \brief (MCAN1) Transmit Buffer Element Size Configuration Register */ + #define REG_MCAN1_TXBRP (0x400340CCU) /**< \brief (MCAN1) Transmit Buffer Request Pending Register */ + #define REG_MCAN1_TXBAR (0x400340D0U) /**< \brief (MCAN1) Transmit Buffer Add Request Register */ + #define REG_MCAN1_TXBCR (0x400340D4U) /**< \brief (MCAN1) Transmit Buffer Cancellation Request Register */ + #define REG_MCAN1_TXBTO (0x400340D8U) /**< \brief (MCAN1) Transmit Buffer Transmission Occurred Register */ + #define REG_MCAN1_TXBCF (0x400340DCU) /**< \brief (MCAN1) Transmit Buffer Cancellation Finished Register */ + #define REG_MCAN1_TXBTIE (0x400340E0U) /**< \brief (MCAN1) Transmit Buffer Transmission Interrupt Enable Register */ + #define REG_MCAN1_TXBCIE (0x400340E4U) /**< \brief (MCAN1) Transmit Buffer Cancellation Finished Interrupt Enable Register */ + #define REG_MCAN1_TXEFC (0x400340F0U) /**< \brief (MCAN1) Transmit Event FIFO Configuration Register */ + #define REG_MCAN1_TXEFS (0x400340F4U) /**< \brief (MCAN1) Transmit Event FIFO Status Register */ + #define REG_MCAN1_TXEFA (0x400340F8U) /**< \brief (MCAN1) Transmit Event FIFO Acknowledge Register */ +#else + #define REG_MCAN1_CUST (*(__IO uint32_t*)0x40034008U) /**< \brief (MCAN1) Customer Register */ + #define REG_MCAN1_FBTP (*(__IO uint32_t*)0x4003400CU) /**< \brief (MCAN1) Fast Bit Timing and Prescaler Register */ + #define REG_MCAN1_TEST (*(__IO uint32_t*)0x40034010U) /**< \brief (MCAN1) Test Register */ + #define REG_MCAN1_RWD (*(__IO uint32_t*)0x40034014U) /**< \brief (MCAN1) RAM Watchdog Register */ + #define REG_MCAN1_CCCR (*(__IO uint32_t*)0x40034018U) /**< \brief (MCAN1) CC Control Register */ + #define REG_MCAN1_BTP (*(__IO uint32_t*)0x4003401CU) /**< \brief (MCAN1) Bit Timing and Prescaler Register */ + #define REG_MCAN1_TSCC (*(__IO uint32_t*)0x40034020U) /**< \brief (MCAN1) Timestamp Counter Configuration Register */ + #define REG_MCAN1_TSCV (*(__IO uint32_t*)0x40034024U) /**< \brief (MCAN1) Timestamp Counter Value Register */ + #define REG_MCAN1_TOCC (*(__IO uint32_t*)0x40034028U) /**< \brief (MCAN1) Timeout Counter Configuration Register */ + #define REG_MCAN1_TOCV (*(__IO uint32_t*)0x4003402CU) /**< \brief (MCAN1) Timeout Counter Value Register */ + #define REG_MCAN1_ECR (*(__I uint32_t*)0x40034040U) /**< \brief (MCAN1) Error Counter Register */ + #define REG_MCAN1_PSR (*(__I uint32_t*)0x40034044U) /**< \brief (MCAN1) Protocol Status Register */ + #define REG_MCAN1_IR (*(__IO uint32_t*)0x40034050U) /**< \brief (MCAN1) Interrupt Register */ + #define REG_MCAN1_IE (*(__IO uint32_t*)0x40034054U) /**< \brief (MCAN1) Interrupt Enable Register */ + #define REG_MCAN1_ILS (*(__IO uint32_t*)0x40034058U) /**< \brief (MCAN1) Interrupt Line Select Register */ + #define REG_MCAN1_ILE (*(__IO uint32_t*)0x4003405CU) /**< \brief (MCAN1) Interrupt Line Enable Register */ + #define REG_MCAN1_GFC (*(__IO uint32_t*)0x40034080U) /**< \brief (MCAN1) Global Filter Configuration Register */ + #define REG_MCAN1_SIDFC (*(__IO uint32_t*)0x40034084U) /**< \brief (MCAN1) Standard ID Filter Configuration Register */ + #define REG_MCAN1_XIDFC (*(__IO uint32_t*)0x40034088U) /**< \brief (MCAN1) Extended ID Filter Configuration Register */ + #define REG_MCAN1_XIDAM (*(__IO uint32_t*)0x40034090U) /**< \brief (MCAN1) Extended ID AND Mask Register */ + #define REG_MCAN1_HPMS (*(__I uint32_t*)0x40034094U) /**< \brief (MCAN1) High Priority Message Status Register */ + #define REG_MCAN1_NDAT1 (*(__IO uint32_t*)0x40034098U) /**< \brief (MCAN1) New Data 1 Register */ + #define REG_MCAN1_NDAT2 (*(__IO uint32_t*)0x4003409CU) /**< \brief (MCAN1) New Data 2 Register */ + #define REG_MCAN1_RXF0C (*(__IO uint32_t*)0x400340A0U) /**< \brief (MCAN1) Receive FIFO 0 Configuration Register */ + #define REG_MCAN1_RXF0S (*(__I uint32_t*)0x400340A4U) /**< \brief (MCAN1) Receive FIFO 0 Status Register */ + #define REG_MCAN1_RXF0A (*(__IO uint32_t*)0x400340A8U) /**< \brief (MCAN1) Receive FIFO 0 Acknowledge Register */ + #define REG_MCAN1_RXBC (*(__IO uint32_t*)0x400340ACU) /**< \brief (MCAN1) Receive Rx Buffer Configuration Register */ + #define REG_MCAN1_RXF1C (*(__IO uint32_t*)0x400340B0U) /**< \brief (MCAN1) Receive FIFO 1 Configuration Register */ + #define REG_MCAN1_RXF1S (*(__I uint32_t*)0x400340B4U) /**< \brief (MCAN1) Receive FIFO 1 Status Register */ + #define REG_MCAN1_RXF1A (*(__IO uint32_t*)0x400340B8U) /**< \brief (MCAN1) Receive FIFO 1 Acknowledge Register */ + #define REG_MCAN1_RXESC (*(__IO uint32_t*)0x400340BCU) /**< \brief (MCAN1) Receive Buffer / FIFO Element Size Configuration Register */ + #define REG_MCAN1_TXBC (*(__IO uint32_t*)0x400340C0U) /**< \brief (MCAN1) Transmit Buffer Configuration Register */ + #define REG_MCAN1_TXFQS (*(__I uint32_t*)0x400340C4U) /**< \brief (MCAN1) Transmit FIFO/Queue Status Register */ + #define REG_MCAN1_TXESC (*(__IO uint32_t*)0x400340C8U) /**< \brief (MCAN1) Transmit Buffer Element Size Configuration Register */ + #define REG_MCAN1_TXBRP (*(__I uint32_t*)0x400340CCU) /**< \brief (MCAN1) Transmit Buffer Request Pending Register */ + #define REG_MCAN1_TXBAR (*(__IO uint32_t*)0x400340D0U) /**< \brief (MCAN1) Transmit Buffer Add Request Register */ + #define REG_MCAN1_TXBCR (*(__IO uint32_t*)0x400340D4U) /**< \brief (MCAN1) Transmit Buffer Cancellation Request Register */ + #define REG_MCAN1_TXBTO (*(__I uint32_t*)0x400340D8U) /**< \brief (MCAN1) Transmit Buffer Transmission Occurred Register */ + #define REG_MCAN1_TXBCF (*(__I uint32_t*)0x400340DCU) /**< \brief (MCAN1) Transmit Buffer Cancellation Finished Register */ + #define REG_MCAN1_TXBTIE (*(__IO uint32_t*)0x400340E0U) /**< \brief (MCAN1) Transmit Buffer Transmission Interrupt Enable Register */ + #define REG_MCAN1_TXBCIE (*(__IO uint32_t*)0x400340E4U) /**< \brief (MCAN1) Transmit Buffer Cancellation Finished Interrupt Enable Register */ + #define REG_MCAN1_TXEFC (*(__IO uint32_t*)0x400340F0U) /**< \brief (MCAN1) Transmit Event FIFO Configuration Register */ + #define REG_MCAN1_TXEFS (*(__I uint32_t*)0x400340F4U) /**< \brief (MCAN1) Transmit Event FIFO Status Register */ + #define REG_MCAN1_TXEFA (*(__IO uint32_t*)0x400340F8U) /**< \brief (MCAN1) Transmit Event FIFO Acknowledge Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_MCAN1_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_mlb.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_mlb.h new file mode 100644 index 00000000..81e506db --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_mlb.h @@ -0,0 +1,74 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_MLB_INSTANCE_ +#define _SAMV71_MLB_INSTANCE_ + +/* ========== Register definition for MLB peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_MLB_MLBC0 (0x40068000U) /**< \brief (MLB) MediaLB Control 0 Register */ + #define REG_MLB_MS0 (0x4006800CU) /**< \brief (MLB) MediaLB Channel Status 0 Register */ + #define REG_MLB_MS1 (0x40068014U) /**< \brief (MLB) MediaLB Channel Status1 Register */ + #define REG_MLB_MSS (0x40068020U) /**< \brief (MLB) MediaLB System Status Register */ + #define REG_MLB_MSD (0x40068024U) /**< \brief (MLB) MediaLB System Data Register */ + #define REG_MLB_MIEN (0x4006802CU) /**< \brief (MLB) MediaLB Interrupt Enable Register */ + #define REG_MLB_MLBC1 (0x4006803CU) /**< \brief (MLB) MediaLB Control 1 Register */ + #define REG_MLB_HCTL (0x40068080U) /**< \brief (MLB) HBI Control Register */ + #define REG_MLB_HCMR (0x40068088U) /**< \brief (MLB) HBI Channel Mask 0 Register */ + #define REG_MLB_HCER (0x40068090U) /**< \brief (MLB) HBI Channel Error 0 Register */ + #define REG_MLB_HCBR (0x40068098U) /**< \brief (MLB) HBI Channel Busy 0 Register */ + #define REG_MLB_MDAT (0x400680C0U) /**< \brief (MLB) MIF Data 0 Register */ + #define REG_MLB_MDWE (0x400680D0U) /**< \brief (MLB) MIF Data Write Enable 0 Register */ + #define REG_MLB_MCTL (0x400680E0U) /**< \brief (MLB) MIF Control Register */ + #define REG_MLB_MADR (0x400680E4U) /**< \brief (MLB) MIF Address Register */ + #define REG_MLB_ACTL (0x400683C0U) /**< \brief (MLB) AHB Control Register */ + #define REG_MLB_ACSR (0x400683D0U) /**< \brief (MLB) AHB Channel Status 0 Register */ + #define REG_MLB_ACMR (0x400683D8U) /**< \brief (MLB) AHB Channel Mask 0 Register */ +#else + #define REG_MLB_MLBC0 (*(__IO uint32_t*)0x40068000U) /**< \brief (MLB) MediaLB Control 0 Register */ + #define REG_MLB_MS0 (*(__IO uint32_t*)0x4006800CU) /**< \brief (MLB) MediaLB Channel Status 0 Register */ + #define REG_MLB_MS1 (*(__IO uint32_t*)0x40068014U) /**< \brief (MLB) MediaLB Channel Status1 Register */ + #define REG_MLB_MSS (*(__IO uint32_t*)0x40068020U) /**< \brief (MLB) MediaLB System Status Register */ + #define REG_MLB_MSD (*(__I uint32_t*)0x40068024U) /**< \brief (MLB) MediaLB System Data Register */ + #define REG_MLB_MIEN (*(__IO uint32_t*)0x4006802CU) /**< \brief (MLB) MediaLB Interrupt Enable Register */ + #define REG_MLB_MLBC1 (*(__IO uint32_t*)0x4006803CU) /**< \brief (MLB) MediaLB Control 1 Register */ + #define REG_MLB_HCTL (*(__IO uint32_t*)0x40068080U) /**< \brief (MLB) HBI Control Register */ + #define REG_MLB_HCMR (*(__IO uint32_t*)0x40068088U) /**< \brief (MLB) HBI Channel Mask 0 Register */ + #define REG_MLB_HCER (*(__I uint32_t*)0x40068090U) /**< \brief (MLB) HBI Channel Error 0 Register */ + #define REG_MLB_HCBR (*(__I uint32_t*)0x40068098U) /**< \brief (MLB) HBI Channel Busy 0 Register */ + #define REG_MLB_MDAT (*(__IO uint32_t*)0x400680C0U) /**< \brief (MLB) MIF Data 0 Register */ + #define REG_MLB_MDWE (*(__IO uint32_t*)0x400680D0U) /**< \brief (MLB) MIF Data Write Enable 0 Register */ + #define REG_MLB_MCTL (*(__IO uint32_t*)0x400680E0U) /**< \brief (MLB) MIF Control Register */ + #define REG_MLB_MADR (*(__IO uint32_t*)0x400680E4U) /**< \brief (MLB) MIF Address Register */ + #define REG_MLB_ACTL (*(__IO uint32_t*)0x400683C0U) /**< \brief (MLB) AHB Control Register */ + #define REG_MLB_ACSR (*(__IO uint32_t*)0x400683D0U) /**< \brief (MLB) AHB Channel Status 0 Register */ + #define REG_MLB_ACMR (*(__IO uint32_t*)0x400683D8U) /**< \brief (MLB) AHB Channel Mask 0 Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_MLB_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_pioa.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_pioa.h new file mode 100644 index 00000000..d7a1cd26 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_pioa.h @@ -0,0 +1,162 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_PIOA_INSTANCE_ +#define _SAMV71_PIOA_INSTANCE_ + +/* ========== Register definition for PIOA peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PIOA_PER (0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */ + #define REG_PIOA_PDR (0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */ + #define REG_PIOA_PSR (0x400E0E08U) /**< \brief (PIOA) PIO Status Register */ + #define REG_PIOA_OER (0x400E0E10U) /**< \brief (PIOA) Output Enable Register */ + #define REG_PIOA_ODR (0x400E0E14U) /**< \brief (PIOA) Output Disable Register */ + #define REG_PIOA_OSR (0x400E0E18U) /**< \brief (PIOA) Output Status Register */ + #define REG_PIOA_IFER (0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ + #define REG_PIOA_IFDR (0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ + #define REG_PIOA_IFSR (0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ + #define REG_PIOA_SODR (0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */ + #define REG_PIOA_CODR (0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */ + #define REG_PIOA_ODSR (0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */ + #define REG_PIOA_PDSR (0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */ + #define REG_PIOA_IER (0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */ + #define REG_PIOA_IDR (0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */ + #define REG_PIOA_IMR (0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */ + #define REG_PIOA_ISR (0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */ + #define REG_PIOA_MDER (0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */ + #define REG_PIOA_MDDR (0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */ + #define REG_PIOA_MDSR (0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */ + #define REG_PIOA_PUDR (0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */ + #define REG_PIOA_PUER (0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */ + #define REG_PIOA_PUSR (0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */ + #define REG_PIOA_ABCDSR (0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */ + #define REG_PIOA_IFSCDR (0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */ + #define REG_PIOA_IFSCER (0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */ + #define REG_PIOA_IFSCSR (0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */ + #define REG_PIOA_SCDR (0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ + #define REG_PIOA_PPDDR (0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */ + #define REG_PIOA_PPDER (0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */ + #define REG_PIOA_PPDSR (0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */ + #define REG_PIOA_OWER (0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */ + #define REG_PIOA_OWDR (0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */ + #define REG_PIOA_OWSR (0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */ + #define REG_PIOA_AIMER (0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ + #define REG_PIOA_AIMDR (0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disable Register */ + #define REG_PIOA_AIMMR (0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ + #define REG_PIOA_ESR (0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */ + #define REG_PIOA_LSR (0x400E0EC4U) /**< \brief (PIOA) Level Select Register */ + #define REG_PIOA_ELSR (0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */ + #define REG_PIOA_FELLSR (0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low-Level Select Register */ + #define REG_PIOA_REHLSR (0x400E0ED4U) /**< \brief (PIOA) Rising Edge/High-Level Select Register */ + #define REG_PIOA_FRLHSR (0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ + #define REG_PIOA_LOCKSR (0x400E0EE0U) /**< \brief (PIOA) Lock Status */ + #define REG_PIOA_WPMR (0x400E0EE4U) /**< \brief (PIOA) Write Protection Mode Register */ + #define REG_PIOA_WPSR (0x400E0EE8U) /**< \brief (PIOA) Write Protection Status Register */ + #define REG_PIOA_SCHMITT (0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */ + #define REG_PIOA_KER (0x400E0F20U) /**< \brief (PIOA) Keypad Controller Enable Register */ + #define REG_PIOA_KRCR (0x400E0F24U) /**< \brief (PIOA) Keypad Controller Row Column Register */ + #define REG_PIOA_KDR (0x400E0F28U) /**< \brief (PIOA) Keypad Controller Debouncing Register */ + #define REG_PIOA_KIER (0x400E0F30U) /**< \brief (PIOA) Keypad Controller Interrupt Enable Register */ + #define REG_PIOA_KIDR (0x400E0F34U) /**< \brief (PIOA) Keypad Controller Interrupt Disable Register */ + #define REG_PIOA_KIMR (0x400E0F38U) /**< \brief (PIOA) Keypad Controller Interrupt Mask Register */ + #define REG_PIOA_KSR (0x400E0F3CU) /**< \brief (PIOA) Keypad Controller Status Register */ + #define REG_PIOA_KKPR (0x400E0F40U) /**< \brief (PIOA) Keypad Controller Key Press Register */ + #define REG_PIOA_KKRR (0x400E0F44U) /**< \brief (PIOA) Keypad Controller Key Release Register */ + #define REG_PIOA_PCMR (0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */ + #define REG_PIOA_PCIER (0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */ + #define REG_PIOA_PCIDR (0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */ + #define REG_PIOA_PCIMR (0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */ + #define REG_PIOA_PCISR (0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */ + #define REG_PIOA_PCRHR (0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */ +#else + #define REG_PIOA_PER (*(__O uint32_t*)0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */ + #define REG_PIOA_PDR (*(__O uint32_t*)0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */ + #define REG_PIOA_PSR (*(__I uint32_t*)0x400E0E08U) /**< \brief (PIOA) PIO Status Register */ + #define REG_PIOA_OER (*(__O uint32_t*)0x400E0E10U) /**< \brief (PIOA) Output Enable Register */ + #define REG_PIOA_ODR (*(__O uint32_t*)0x400E0E14U) /**< \brief (PIOA) Output Disable Register */ + #define REG_PIOA_OSR (*(__I uint32_t*)0x400E0E18U) /**< \brief (PIOA) Output Status Register */ + #define REG_PIOA_IFER (*(__O uint32_t*)0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ + #define REG_PIOA_IFDR (*(__O uint32_t*)0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ + #define REG_PIOA_IFSR (*(__I uint32_t*)0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ + #define REG_PIOA_SODR (*(__O uint32_t*)0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */ + #define REG_PIOA_CODR (*(__O uint32_t*)0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */ + #define REG_PIOA_ODSR (*(__IO uint32_t*)0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */ + #define REG_PIOA_PDSR (*(__I uint32_t*)0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */ + #define REG_PIOA_IER (*(__O uint32_t*)0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */ + #define REG_PIOA_IDR (*(__O uint32_t*)0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */ + #define REG_PIOA_IMR (*(__I uint32_t*)0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */ + #define REG_PIOA_ISR (*(__I uint32_t*)0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */ + #define REG_PIOA_MDER (*(__O uint32_t*)0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */ + #define REG_PIOA_MDDR (*(__O uint32_t*)0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */ + #define REG_PIOA_MDSR (*(__I uint32_t*)0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */ + #define REG_PIOA_PUDR (*(__O uint32_t*)0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */ + #define REG_PIOA_PUER (*(__O uint32_t*)0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */ + #define REG_PIOA_PUSR (*(__I uint32_t*)0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */ + #define REG_PIOA_ABCDSR (*(__IO uint32_t*)0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */ + #define REG_PIOA_IFSCDR (*(__O uint32_t*)0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */ + #define REG_PIOA_IFSCER (*(__O uint32_t*)0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */ + #define REG_PIOA_IFSCSR (*(__I uint32_t*)0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */ + #define REG_PIOA_SCDR (*(__IO uint32_t*)0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ + #define REG_PIOA_PPDDR (*(__O uint32_t*)0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */ + #define REG_PIOA_PPDER (*(__O uint32_t*)0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */ + #define REG_PIOA_PPDSR (*(__I uint32_t*)0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */ + #define REG_PIOA_OWER (*(__O uint32_t*)0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */ + #define REG_PIOA_OWDR (*(__O uint32_t*)0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */ + #define REG_PIOA_OWSR (*(__I uint32_t*)0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */ + #define REG_PIOA_AIMER (*(__O uint32_t*)0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ + #define REG_PIOA_AIMDR (*(__O uint32_t*)0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disable Register */ + #define REG_PIOA_AIMMR (*(__I uint32_t*)0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ + #define REG_PIOA_ESR (*(__O uint32_t*)0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */ + #define REG_PIOA_LSR (*(__O uint32_t*)0x400E0EC4U) /**< \brief (PIOA) Level Select Register */ + #define REG_PIOA_ELSR (*(__I uint32_t*)0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */ + #define REG_PIOA_FELLSR (*(__O uint32_t*)0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low-Level Select Register */ + #define REG_PIOA_REHLSR (*(__O uint32_t*)0x400E0ED4U) /**< \brief (PIOA) Rising Edge/High-Level Select Register */ + #define REG_PIOA_FRLHSR (*(__I uint32_t*)0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ + #define REG_PIOA_LOCKSR (*(__I uint32_t*)0x400E0EE0U) /**< \brief (PIOA) Lock Status */ + #define REG_PIOA_WPMR (*(__IO uint32_t*)0x400E0EE4U) /**< \brief (PIOA) Write Protection Mode Register */ + #define REG_PIOA_WPSR (*(__I uint32_t*)0x400E0EE8U) /**< \brief (PIOA) Write Protection Status Register */ + #define REG_PIOA_SCHMITT (*(__IO uint32_t*)0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */ + #define REG_PIOA_KER (*(__IO uint32_t*)0x400E0F20U) /**< \brief (PIOA) Keypad Controller Enable Register */ + #define REG_PIOA_KRCR (*(__IO uint32_t*)0x400E0F24U) /**< \brief (PIOA) Keypad Controller Row Column Register */ + #define REG_PIOA_KDR (*(__IO uint32_t*)0x400E0F28U) /**< \brief (PIOA) Keypad Controller Debouncing Register */ + #define REG_PIOA_KIER (*(__O uint32_t*)0x400E0F30U) /**< \brief (PIOA) Keypad Controller Interrupt Enable Register */ + #define REG_PIOA_KIDR (*(__O uint32_t*)0x400E0F34U) /**< \brief (PIOA) Keypad Controller Interrupt Disable Register */ + #define REG_PIOA_KIMR (*(__I uint32_t*)0x400E0F38U) /**< \brief (PIOA) Keypad Controller Interrupt Mask Register */ + #define REG_PIOA_KSR (*(__I uint32_t*)0x400E0F3CU) /**< \brief (PIOA) Keypad Controller Status Register */ + #define REG_PIOA_KKPR (*(__I uint32_t*)0x400E0F40U) /**< \brief (PIOA) Keypad Controller Key Press Register */ + #define REG_PIOA_KKRR (*(__I uint32_t*)0x400E0F44U) /**< \brief (PIOA) Keypad Controller Key Release Register */ + #define REG_PIOA_PCMR (*(__IO uint32_t*)0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */ + #define REG_PIOA_PCIER (*(__O uint32_t*)0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */ + #define REG_PIOA_PCIDR (*(__O uint32_t*)0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */ + #define REG_PIOA_PCIMR (*(__I uint32_t*)0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */ + #define REG_PIOA_PCISR (*(__I uint32_t*)0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */ + #define REG_PIOA_PCRHR (*(__I uint32_t*)0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_PIOA_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_piob.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_piob.h new file mode 100644 index 00000000..71787615 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_piob.h @@ -0,0 +1,162 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_PIOB_INSTANCE_ +#define _SAMV71_PIOB_INSTANCE_ + +/* ========== Register definition for PIOB peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PIOB_PER (0x400E1000U) /**< \brief (PIOB) PIO Enable Register */ + #define REG_PIOB_PDR (0x400E1004U) /**< \brief (PIOB) PIO Disable Register */ + #define REG_PIOB_PSR (0x400E1008U) /**< \brief (PIOB) PIO Status Register */ + #define REG_PIOB_OER (0x400E1010U) /**< \brief (PIOB) Output Enable Register */ + #define REG_PIOB_ODR (0x400E1014U) /**< \brief (PIOB) Output Disable Register */ + #define REG_PIOB_OSR (0x400E1018U) /**< \brief (PIOB) Output Status Register */ + #define REG_PIOB_IFER (0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ + #define REG_PIOB_IFDR (0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ + #define REG_PIOB_IFSR (0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */ + #define REG_PIOB_SODR (0x400E1030U) /**< \brief (PIOB) Set Output Data Register */ + #define REG_PIOB_CODR (0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */ + #define REG_PIOB_ODSR (0x400E1038U) /**< \brief (PIOB) Output Data Status Register */ + #define REG_PIOB_PDSR (0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */ + #define REG_PIOB_IER (0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */ + #define REG_PIOB_IDR (0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */ + #define REG_PIOB_IMR (0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */ + #define REG_PIOB_ISR (0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */ + #define REG_PIOB_MDER (0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */ + #define REG_PIOB_MDDR (0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */ + #define REG_PIOB_MDSR (0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */ + #define REG_PIOB_PUDR (0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */ + #define REG_PIOB_PUER (0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */ + #define REG_PIOB_PUSR (0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */ + #define REG_PIOB_ABCDSR (0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */ + #define REG_PIOB_IFSCDR (0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */ + #define REG_PIOB_IFSCER (0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */ + #define REG_PIOB_IFSCSR (0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */ + #define REG_PIOB_SCDR (0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ + #define REG_PIOB_PPDDR (0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */ + #define REG_PIOB_PPDER (0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */ + #define REG_PIOB_PPDSR (0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */ + #define REG_PIOB_OWER (0x400E10A0U) /**< \brief (PIOB) Output Write Enable */ + #define REG_PIOB_OWDR (0x400E10A4U) /**< \brief (PIOB) Output Write Disable */ + #define REG_PIOB_OWSR (0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */ + #define REG_PIOB_AIMER (0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ + #define REG_PIOB_AIMDR (0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disable Register */ + #define REG_PIOB_AIMMR (0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ + #define REG_PIOB_ESR (0x400E10C0U) /**< \brief (PIOB) Edge Select Register */ + #define REG_PIOB_LSR (0x400E10C4U) /**< \brief (PIOB) Level Select Register */ + #define REG_PIOB_ELSR (0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */ + #define REG_PIOB_FELLSR (0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low-Level Select Register */ + #define REG_PIOB_REHLSR (0x400E10D4U) /**< \brief (PIOB) Rising Edge/High-Level Select Register */ + #define REG_PIOB_FRLHSR (0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ + #define REG_PIOB_LOCKSR (0x400E10E0U) /**< \brief (PIOB) Lock Status */ + #define REG_PIOB_WPMR (0x400E10E4U) /**< \brief (PIOB) Write Protection Mode Register */ + #define REG_PIOB_WPSR (0x400E10E8U) /**< \brief (PIOB) Write Protection Status Register */ + #define REG_PIOB_SCHMITT (0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */ + #define REG_PIOB_KER (0x400E1120U) /**< \brief (PIOB) Keypad Controller Enable Register */ + #define REG_PIOB_KRCR (0x400E1124U) /**< \brief (PIOB) Keypad Controller Row Column Register */ + #define REG_PIOB_KDR (0x400E1128U) /**< \brief (PIOB) Keypad Controller Debouncing Register */ + #define REG_PIOB_KIER (0x400E1130U) /**< \brief (PIOB) Keypad Controller Interrupt Enable Register */ + #define REG_PIOB_KIDR (0x400E1134U) /**< \brief (PIOB) Keypad Controller Interrupt Disable Register */ + #define REG_PIOB_KIMR (0x400E1138U) /**< \brief (PIOB) Keypad Controller Interrupt Mask Register */ + #define REG_PIOB_KSR (0x400E113CU) /**< \brief (PIOB) Keypad Controller Status Register */ + #define REG_PIOB_KKPR (0x400E1140U) /**< \brief (PIOB) Keypad Controller Key Press Register */ + #define REG_PIOB_KKRR (0x400E1144U) /**< \brief (PIOB) Keypad Controller Key Release Register */ + #define REG_PIOB_PCMR (0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */ + #define REG_PIOB_PCIER (0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */ + #define REG_PIOB_PCIDR (0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */ + #define REG_PIOB_PCIMR (0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */ + #define REG_PIOB_PCISR (0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */ + #define REG_PIOB_PCRHR (0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */ +#else + #define REG_PIOB_PER (*(__O uint32_t*)0x400E1000U) /**< \brief (PIOB) PIO Enable Register */ + #define REG_PIOB_PDR (*(__O uint32_t*)0x400E1004U) /**< \brief (PIOB) PIO Disable Register */ + #define REG_PIOB_PSR (*(__I uint32_t*)0x400E1008U) /**< \brief (PIOB) PIO Status Register */ + #define REG_PIOB_OER (*(__O uint32_t*)0x400E1010U) /**< \brief (PIOB) Output Enable Register */ + #define REG_PIOB_ODR (*(__O uint32_t*)0x400E1014U) /**< \brief (PIOB) Output Disable Register */ + #define REG_PIOB_OSR (*(__I uint32_t*)0x400E1018U) /**< \brief (PIOB) Output Status Register */ + #define REG_PIOB_IFER (*(__O uint32_t*)0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ + #define REG_PIOB_IFDR (*(__O uint32_t*)0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ + #define REG_PIOB_IFSR (*(__I uint32_t*)0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */ + #define REG_PIOB_SODR (*(__O uint32_t*)0x400E1030U) /**< \brief (PIOB) Set Output Data Register */ + #define REG_PIOB_CODR (*(__O uint32_t*)0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */ + #define REG_PIOB_ODSR (*(__IO uint32_t*)0x400E1038U) /**< \brief (PIOB) Output Data Status Register */ + #define REG_PIOB_PDSR (*(__I uint32_t*)0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */ + #define REG_PIOB_IER (*(__O uint32_t*)0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */ + #define REG_PIOB_IDR (*(__O uint32_t*)0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */ + #define REG_PIOB_IMR (*(__I uint32_t*)0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */ + #define REG_PIOB_ISR (*(__I uint32_t*)0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */ + #define REG_PIOB_MDER (*(__O uint32_t*)0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */ + #define REG_PIOB_MDDR (*(__O uint32_t*)0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */ + #define REG_PIOB_MDSR (*(__I uint32_t*)0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */ + #define REG_PIOB_PUDR (*(__O uint32_t*)0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */ + #define REG_PIOB_PUER (*(__O uint32_t*)0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */ + #define REG_PIOB_PUSR (*(__I uint32_t*)0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */ + #define REG_PIOB_ABCDSR (*(__IO uint32_t*)0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */ + #define REG_PIOB_IFSCDR (*(__O uint32_t*)0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */ + #define REG_PIOB_IFSCER (*(__O uint32_t*)0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */ + #define REG_PIOB_IFSCSR (*(__I uint32_t*)0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */ + #define REG_PIOB_SCDR (*(__IO uint32_t*)0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ + #define REG_PIOB_PPDDR (*(__O uint32_t*)0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */ + #define REG_PIOB_PPDER (*(__O uint32_t*)0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */ + #define REG_PIOB_PPDSR (*(__I uint32_t*)0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */ + #define REG_PIOB_OWER (*(__O uint32_t*)0x400E10A0U) /**< \brief (PIOB) Output Write Enable */ + #define REG_PIOB_OWDR (*(__O uint32_t*)0x400E10A4U) /**< \brief (PIOB) Output Write Disable */ + #define REG_PIOB_OWSR (*(__I uint32_t*)0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */ + #define REG_PIOB_AIMER (*(__O uint32_t*)0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ + #define REG_PIOB_AIMDR (*(__O uint32_t*)0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disable Register */ + #define REG_PIOB_AIMMR (*(__I uint32_t*)0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ + #define REG_PIOB_ESR (*(__O uint32_t*)0x400E10C0U) /**< \brief (PIOB) Edge Select Register */ + #define REG_PIOB_LSR (*(__O uint32_t*)0x400E10C4U) /**< \brief (PIOB) Level Select Register */ + #define REG_PIOB_ELSR (*(__I uint32_t*)0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */ + #define REG_PIOB_FELLSR (*(__O uint32_t*)0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low-Level Select Register */ + #define REG_PIOB_REHLSR (*(__O uint32_t*)0x400E10D4U) /**< \brief (PIOB) Rising Edge/High-Level Select Register */ + #define REG_PIOB_FRLHSR (*(__I uint32_t*)0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ + #define REG_PIOB_LOCKSR (*(__I uint32_t*)0x400E10E0U) /**< \brief (PIOB) Lock Status */ + #define REG_PIOB_WPMR (*(__IO uint32_t*)0x400E10E4U) /**< \brief (PIOB) Write Protection Mode Register */ + #define REG_PIOB_WPSR (*(__I uint32_t*)0x400E10E8U) /**< \brief (PIOB) Write Protection Status Register */ + #define REG_PIOB_SCHMITT (*(__IO uint32_t*)0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */ + #define REG_PIOB_KER (*(__IO uint32_t*)0x400E1120U) /**< \brief (PIOB) Keypad Controller Enable Register */ + #define REG_PIOB_KRCR (*(__IO uint32_t*)0x400E1124U) /**< \brief (PIOB) Keypad Controller Row Column Register */ + #define REG_PIOB_KDR (*(__IO uint32_t*)0x400E1128U) /**< \brief (PIOB) Keypad Controller Debouncing Register */ + #define REG_PIOB_KIER (*(__O uint32_t*)0x400E1130U) /**< \brief (PIOB) Keypad Controller Interrupt Enable Register */ + #define REG_PIOB_KIDR (*(__O uint32_t*)0x400E1134U) /**< \brief (PIOB) Keypad Controller Interrupt Disable Register */ + #define REG_PIOB_KIMR (*(__I uint32_t*)0x400E1138U) /**< \brief (PIOB) Keypad Controller Interrupt Mask Register */ + #define REG_PIOB_KSR (*(__I uint32_t*)0x400E113CU) /**< \brief (PIOB) Keypad Controller Status Register */ + #define REG_PIOB_KKPR (*(__I uint32_t*)0x400E1140U) /**< \brief (PIOB) Keypad Controller Key Press Register */ + #define REG_PIOB_KKRR (*(__I uint32_t*)0x400E1144U) /**< \brief (PIOB) Keypad Controller Key Release Register */ + #define REG_PIOB_PCMR (*(__IO uint32_t*)0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */ + #define REG_PIOB_PCIER (*(__O uint32_t*)0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */ + #define REG_PIOB_PCIDR (*(__O uint32_t*)0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */ + #define REG_PIOB_PCIMR (*(__I uint32_t*)0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */ + #define REG_PIOB_PCISR (*(__I uint32_t*)0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */ + #define REG_PIOB_PCRHR (*(__I uint32_t*)0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_PIOB_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_pioc.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_pioc.h new file mode 100644 index 00000000..5e9129dd --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_pioc.h @@ -0,0 +1,162 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_PIOC_INSTANCE_ +#define _SAMV71_PIOC_INSTANCE_ + +/* ========== Register definition for PIOC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PIOC_PER (0x400E1200U) /**< \brief (PIOC) PIO Enable Register */ + #define REG_PIOC_PDR (0x400E1204U) /**< \brief (PIOC) PIO Disable Register */ + #define REG_PIOC_PSR (0x400E1208U) /**< \brief (PIOC) PIO Status Register */ + #define REG_PIOC_OER (0x400E1210U) /**< \brief (PIOC) Output Enable Register */ + #define REG_PIOC_ODR (0x400E1214U) /**< \brief (PIOC) Output Disable Register */ + #define REG_PIOC_OSR (0x400E1218U) /**< \brief (PIOC) Output Status Register */ + #define REG_PIOC_IFER (0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */ + #define REG_PIOC_IFDR (0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */ + #define REG_PIOC_IFSR (0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */ + #define REG_PIOC_SODR (0x400E1230U) /**< \brief (PIOC) Set Output Data Register */ + #define REG_PIOC_CODR (0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */ + #define REG_PIOC_ODSR (0x400E1238U) /**< \brief (PIOC) Output Data Status Register */ + #define REG_PIOC_PDSR (0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */ + #define REG_PIOC_IER (0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */ + #define REG_PIOC_IDR (0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */ + #define REG_PIOC_IMR (0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */ + #define REG_PIOC_ISR (0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */ + #define REG_PIOC_MDER (0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */ + #define REG_PIOC_MDDR (0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */ + #define REG_PIOC_MDSR (0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */ + #define REG_PIOC_PUDR (0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */ + #define REG_PIOC_PUER (0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */ + #define REG_PIOC_PUSR (0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */ + #define REG_PIOC_ABCDSR (0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */ + #define REG_PIOC_IFSCDR (0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */ + #define REG_PIOC_IFSCER (0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */ + #define REG_PIOC_IFSCSR (0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */ + #define REG_PIOC_SCDR (0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */ + #define REG_PIOC_PPDDR (0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */ + #define REG_PIOC_PPDER (0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */ + #define REG_PIOC_PPDSR (0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */ + #define REG_PIOC_OWER (0x400E12A0U) /**< \brief (PIOC) Output Write Enable */ + #define REG_PIOC_OWDR (0x400E12A4U) /**< \brief (PIOC) Output Write Disable */ + #define REG_PIOC_OWSR (0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */ + #define REG_PIOC_AIMER (0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */ + #define REG_PIOC_AIMDR (0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disable Register */ + #define REG_PIOC_AIMMR (0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */ + #define REG_PIOC_ESR (0x400E12C0U) /**< \brief (PIOC) Edge Select Register */ + #define REG_PIOC_LSR (0x400E12C4U) /**< \brief (PIOC) Level Select Register */ + #define REG_PIOC_ELSR (0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */ + #define REG_PIOC_FELLSR (0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low-Level Select Register */ + #define REG_PIOC_REHLSR (0x400E12D4U) /**< \brief (PIOC) Rising Edge/High-Level Select Register */ + #define REG_PIOC_FRLHSR (0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */ + #define REG_PIOC_LOCKSR (0x400E12E0U) /**< \brief (PIOC) Lock Status */ + #define REG_PIOC_WPMR (0x400E12E4U) /**< \brief (PIOC) Write Protection Mode Register */ + #define REG_PIOC_WPSR (0x400E12E8U) /**< \brief (PIOC) Write Protection Status Register */ + #define REG_PIOC_SCHMITT (0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */ + #define REG_PIOC_KER (0x400E1320U) /**< \brief (PIOC) Keypad Controller Enable Register */ + #define REG_PIOC_KRCR (0x400E1324U) /**< \brief (PIOC) Keypad Controller Row Column Register */ + #define REG_PIOC_KDR (0x400E1328U) /**< \brief (PIOC) Keypad Controller Debouncing Register */ + #define REG_PIOC_KIER (0x400E1330U) /**< \brief (PIOC) Keypad Controller Interrupt Enable Register */ + #define REG_PIOC_KIDR (0x400E1334U) /**< \brief (PIOC) Keypad Controller Interrupt Disable Register */ + #define REG_PIOC_KIMR (0x400E1338U) /**< \brief (PIOC) Keypad Controller Interrupt Mask Register */ + #define REG_PIOC_KSR (0x400E133CU) /**< \brief (PIOC) Keypad Controller Status Register */ + #define REG_PIOC_KKPR (0x400E1340U) /**< \brief (PIOC) Keypad Controller Key Press Register */ + #define REG_PIOC_KKRR (0x400E1344U) /**< \brief (PIOC) Keypad Controller Key Release Register */ + #define REG_PIOC_PCMR (0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */ + #define REG_PIOC_PCIER (0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */ + #define REG_PIOC_PCIDR (0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */ + #define REG_PIOC_PCIMR (0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */ + #define REG_PIOC_PCISR (0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */ + #define REG_PIOC_PCRHR (0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */ +#else + #define REG_PIOC_PER (*(__O uint32_t*)0x400E1200U) /**< \brief (PIOC) PIO Enable Register */ + #define REG_PIOC_PDR (*(__O uint32_t*)0x400E1204U) /**< \brief (PIOC) PIO Disable Register */ + #define REG_PIOC_PSR (*(__I uint32_t*)0x400E1208U) /**< \brief (PIOC) PIO Status Register */ + #define REG_PIOC_OER (*(__O uint32_t*)0x400E1210U) /**< \brief (PIOC) Output Enable Register */ + #define REG_PIOC_ODR (*(__O uint32_t*)0x400E1214U) /**< \brief (PIOC) Output Disable Register */ + #define REG_PIOC_OSR (*(__I uint32_t*)0x400E1218U) /**< \brief (PIOC) Output Status Register */ + #define REG_PIOC_IFER (*(__O uint32_t*)0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */ + #define REG_PIOC_IFDR (*(__O uint32_t*)0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */ + #define REG_PIOC_IFSR (*(__I uint32_t*)0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */ + #define REG_PIOC_SODR (*(__O uint32_t*)0x400E1230U) /**< \brief (PIOC) Set Output Data Register */ + #define REG_PIOC_CODR (*(__O uint32_t*)0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */ + #define REG_PIOC_ODSR (*(__IO uint32_t*)0x400E1238U) /**< \brief (PIOC) Output Data Status Register */ + #define REG_PIOC_PDSR (*(__I uint32_t*)0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */ + #define REG_PIOC_IER (*(__O uint32_t*)0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */ + #define REG_PIOC_IDR (*(__O uint32_t*)0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */ + #define REG_PIOC_IMR (*(__I uint32_t*)0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */ + #define REG_PIOC_ISR (*(__I uint32_t*)0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */ + #define REG_PIOC_MDER (*(__O uint32_t*)0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */ + #define REG_PIOC_MDDR (*(__O uint32_t*)0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */ + #define REG_PIOC_MDSR (*(__I uint32_t*)0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */ + #define REG_PIOC_PUDR (*(__O uint32_t*)0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */ + #define REG_PIOC_PUER (*(__O uint32_t*)0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */ + #define REG_PIOC_PUSR (*(__I uint32_t*)0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */ + #define REG_PIOC_ABCDSR (*(__IO uint32_t*)0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */ + #define REG_PIOC_IFSCDR (*(__O uint32_t*)0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */ + #define REG_PIOC_IFSCER (*(__O uint32_t*)0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */ + #define REG_PIOC_IFSCSR (*(__I uint32_t*)0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */ + #define REG_PIOC_SCDR (*(__IO uint32_t*)0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */ + #define REG_PIOC_PPDDR (*(__O uint32_t*)0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */ + #define REG_PIOC_PPDER (*(__O uint32_t*)0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */ + #define REG_PIOC_PPDSR (*(__I uint32_t*)0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */ + #define REG_PIOC_OWER (*(__O uint32_t*)0x400E12A0U) /**< \brief (PIOC) Output Write Enable */ + #define REG_PIOC_OWDR (*(__O uint32_t*)0x400E12A4U) /**< \brief (PIOC) Output Write Disable */ + #define REG_PIOC_OWSR (*(__I uint32_t*)0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */ + #define REG_PIOC_AIMER (*(__O uint32_t*)0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */ + #define REG_PIOC_AIMDR (*(__O uint32_t*)0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disable Register */ + #define REG_PIOC_AIMMR (*(__I uint32_t*)0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */ + #define REG_PIOC_ESR (*(__O uint32_t*)0x400E12C0U) /**< \brief (PIOC) Edge Select Register */ + #define REG_PIOC_LSR (*(__O uint32_t*)0x400E12C4U) /**< \brief (PIOC) Level Select Register */ + #define REG_PIOC_ELSR (*(__I uint32_t*)0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */ + #define REG_PIOC_FELLSR (*(__O uint32_t*)0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low-Level Select Register */ + #define REG_PIOC_REHLSR (*(__O uint32_t*)0x400E12D4U) /**< \brief (PIOC) Rising Edge/High-Level Select Register */ + #define REG_PIOC_FRLHSR (*(__I uint32_t*)0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */ + #define REG_PIOC_LOCKSR (*(__I uint32_t*)0x400E12E0U) /**< \brief (PIOC) Lock Status */ + #define REG_PIOC_WPMR (*(__IO uint32_t*)0x400E12E4U) /**< \brief (PIOC) Write Protection Mode Register */ + #define REG_PIOC_WPSR (*(__I uint32_t*)0x400E12E8U) /**< \brief (PIOC) Write Protection Status Register */ + #define REG_PIOC_SCHMITT (*(__IO uint32_t*)0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */ + #define REG_PIOC_KER (*(__IO uint32_t*)0x400E1320U) /**< \brief (PIOC) Keypad Controller Enable Register */ + #define REG_PIOC_KRCR (*(__IO uint32_t*)0x400E1324U) /**< \brief (PIOC) Keypad Controller Row Column Register */ + #define REG_PIOC_KDR (*(__IO uint32_t*)0x400E1328U) /**< \brief (PIOC) Keypad Controller Debouncing Register */ + #define REG_PIOC_KIER (*(__O uint32_t*)0x400E1330U) /**< \brief (PIOC) Keypad Controller Interrupt Enable Register */ + #define REG_PIOC_KIDR (*(__O uint32_t*)0x400E1334U) /**< \brief (PIOC) Keypad Controller Interrupt Disable Register */ + #define REG_PIOC_KIMR (*(__I uint32_t*)0x400E1338U) /**< \brief (PIOC) Keypad Controller Interrupt Mask Register */ + #define REG_PIOC_KSR (*(__I uint32_t*)0x400E133CU) /**< \brief (PIOC) Keypad Controller Status Register */ + #define REG_PIOC_KKPR (*(__I uint32_t*)0x400E1340U) /**< \brief (PIOC) Keypad Controller Key Press Register */ + #define REG_PIOC_KKRR (*(__I uint32_t*)0x400E1344U) /**< \brief (PIOC) Keypad Controller Key Release Register */ + #define REG_PIOC_PCMR (*(__IO uint32_t*)0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */ + #define REG_PIOC_PCIER (*(__O uint32_t*)0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */ + #define REG_PIOC_PCIDR (*(__O uint32_t*)0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */ + #define REG_PIOC_PCIMR (*(__I uint32_t*)0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */ + #define REG_PIOC_PCISR (*(__I uint32_t*)0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */ + #define REG_PIOC_PCRHR (*(__I uint32_t*)0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_PIOC_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_piod.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_piod.h new file mode 100644 index 00000000..7726c792 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_piod.h @@ -0,0 +1,162 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_PIOD_INSTANCE_ +#define _SAMV71_PIOD_INSTANCE_ + +/* ========== Register definition for PIOD peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PIOD_PER (0x400E1400U) /**< \brief (PIOD) PIO Enable Register */ + #define REG_PIOD_PDR (0x400E1404U) /**< \brief (PIOD) PIO Disable Register */ + #define REG_PIOD_PSR (0x400E1408U) /**< \brief (PIOD) PIO Status Register */ + #define REG_PIOD_OER (0x400E1410U) /**< \brief (PIOD) Output Enable Register */ + #define REG_PIOD_ODR (0x400E1414U) /**< \brief (PIOD) Output Disable Register */ + #define REG_PIOD_OSR (0x400E1418U) /**< \brief (PIOD) Output Status Register */ + #define REG_PIOD_IFER (0x400E1420U) /**< \brief (PIOD) Glitch Input Filter Enable Register */ + #define REG_PIOD_IFDR (0x400E1424U) /**< \brief (PIOD) Glitch Input Filter Disable Register */ + #define REG_PIOD_IFSR (0x400E1428U) /**< \brief (PIOD) Glitch Input Filter Status Register */ + #define REG_PIOD_SODR (0x400E1430U) /**< \brief (PIOD) Set Output Data Register */ + #define REG_PIOD_CODR (0x400E1434U) /**< \brief (PIOD) Clear Output Data Register */ + #define REG_PIOD_ODSR (0x400E1438U) /**< \brief (PIOD) Output Data Status Register */ + #define REG_PIOD_PDSR (0x400E143CU) /**< \brief (PIOD) Pin Data Status Register */ + #define REG_PIOD_IER (0x400E1440U) /**< \brief (PIOD) Interrupt Enable Register */ + #define REG_PIOD_IDR (0x400E1444U) /**< \brief (PIOD) Interrupt Disable Register */ + #define REG_PIOD_IMR (0x400E1448U) /**< \brief (PIOD) Interrupt Mask Register */ + #define REG_PIOD_ISR (0x400E144CU) /**< \brief (PIOD) Interrupt Status Register */ + #define REG_PIOD_MDER (0x400E1450U) /**< \brief (PIOD) Multi-driver Enable Register */ + #define REG_PIOD_MDDR (0x400E1454U) /**< \brief (PIOD) Multi-driver Disable Register */ + #define REG_PIOD_MDSR (0x400E1458U) /**< \brief (PIOD) Multi-driver Status Register */ + #define REG_PIOD_PUDR (0x400E1460U) /**< \brief (PIOD) Pull-up Disable Register */ + #define REG_PIOD_PUER (0x400E1464U) /**< \brief (PIOD) Pull-up Enable Register */ + #define REG_PIOD_PUSR (0x400E1468U) /**< \brief (PIOD) Pad Pull-up Status Register */ + #define REG_PIOD_ABCDSR (0x400E1470U) /**< \brief (PIOD) Peripheral Select Register */ + #define REG_PIOD_IFSCDR (0x400E1480U) /**< \brief (PIOD) Input Filter Slow Clock Disable Register */ + #define REG_PIOD_IFSCER (0x400E1484U) /**< \brief (PIOD) Input Filter Slow Clock Enable Register */ + #define REG_PIOD_IFSCSR (0x400E1488U) /**< \brief (PIOD) Input Filter Slow Clock Status Register */ + #define REG_PIOD_SCDR (0x400E148CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */ + #define REG_PIOD_PPDDR (0x400E1490U) /**< \brief (PIOD) Pad Pull-down Disable Register */ + #define REG_PIOD_PPDER (0x400E1494U) /**< \brief (PIOD) Pad Pull-down Enable Register */ + #define REG_PIOD_PPDSR (0x400E1498U) /**< \brief (PIOD) Pad Pull-down Status Register */ + #define REG_PIOD_OWER (0x400E14A0U) /**< \brief (PIOD) Output Write Enable */ + #define REG_PIOD_OWDR (0x400E14A4U) /**< \brief (PIOD) Output Write Disable */ + #define REG_PIOD_OWSR (0x400E14A8U) /**< \brief (PIOD) Output Write Status Register */ + #define REG_PIOD_AIMER (0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */ + #define REG_PIOD_AIMDR (0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Modes Disable Register */ + #define REG_PIOD_AIMMR (0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */ + #define REG_PIOD_ESR (0x400E14C0U) /**< \brief (PIOD) Edge Select Register */ + #define REG_PIOD_LSR (0x400E14C4U) /**< \brief (PIOD) Level Select Register */ + #define REG_PIOD_ELSR (0x400E14C8U) /**< \brief (PIOD) Edge/Level Status Register */ + #define REG_PIOD_FELLSR (0x400E14D0U) /**< \brief (PIOD) Falling Edge/Low-Level Select Register */ + #define REG_PIOD_REHLSR (0x400E14D4U) /**< \brief (PIOD) Rising Edge/High-Level Select Register */ + #define REG_PIOD_FRLHSR (0x400E14D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */ + #define REG_PIOD_LOCKSR (0x400E14E0U) /**< \brief (PIOD) Lock Status */ + #define REG_PIOD_WPMR (0x400E14E4U) /**< \brief (PIOD) Write Protection Mode Register */ + #define REG_PIOD_WPSR (0x400E14E8U) /**< \brief (PIOD) Write Protection Status Register */ + #define REG_PIOD_SCHMITT (0x400E1500U) /**< \brief (PIOD) Schmitt Trigger Register */ + #define REG_PIOD_KER (0x400E1520U) /**< \brief (PIOD) Keypad Controller Enable Register */ + #define REG_PIOD_KRCR (0x400E1524U) /**< \brief (PIOD) Keypad Controller Row Column Register */ + #define REG_PIOD_KDR (0x400E1528U) /**< \brief (PIOD) Keypad Controller Debouncing Register */ + #define REG_PIOD_KIER (0x400E1530U) /**< \brief (PIOD) Keypad Controller Interrupt Enable Register */ + #define REG_PIOD_KIDR (0x400E1534U) /**< \brief (PIOD) Keypad Controller Interrupt Disable Register */ + #define REG_PIOD_KIMR (0x400E1538U) /**< \brief (PIOD) Keypad Controller Interrupt Mask Register */ + #define REG_PIOD_KSR (0x400E153CU) /**< \brief (PIOD) Keypad Controller Status Register */ + #define REG_PIOD_KKPR (0x400E1540U) /**< \brief (PIOD) Keypad Controller Key Press Register */ + #define REG_PIOD_KKRR (0x400E1544U) /**< \brief (PIOD) Keypad Controller Key Release Register */ + #define REG_PIOD_PCMR (0x400E1550U) /**< \brief (PIOD) Parallel Capture Mode Register */ + #define REG_PIOD_PCIER (0x400E1554U) /**< \brief (PIOD) Parallel Capture Interrupt Enable Register */ + #define REG_PIOD_PCIDR (0x400E1558U) /**< \brief (PIOD) Parallel Capture Interrupt Disable Register */ + #define REG_PIOD_PCIMR (0x400E155CU) /**< \brief (PIOD) Parallel Capture Interrupt Mask Register */ + #define REG_PIOD_PCISR (0x400E1560U) /**< \brief (PIOD) Parallel Capture Interrupt Status Register */ + #define REG_PIOD_PCRHR (0x400E1564U) /**< \brief (PIOD) Parallel Capture Reception Holding Register */ +#else + #define REG_PIOD_PER (*(__O uint32_t*)0x400E1400U) /**< \brief (PIOD) PIO Enable Register */ + #define REG_PIOD_PDR (*(__O uint32_t*)0x400E1404U) /**< \brief (PIOD) PIO Disable Register */ + #define REG_PIOD_PSR (*(__I uint32_t*)0x400E1408U) /**< \brief (PIOD) PIO Status Register */ + #define REG_PIOD_OER (*(__O uint32_t*)0x400E1410U) /**< \brief (PIOD) Output Enable Register */ + #define REG_PIOD_ODR (*(__O uint32_t*)0x400E1414U) /**< \brief (PIOD) Output Disable Register */ + #define REG_PIOD_OSR (*(__I uint32_t*)0x400E1418U) /**< \brief (PIOD) Output Status Register */ + #define REG_PIOD_IFER (*(__O uint32_t*)0x400E1420U) /**< \brief (PIOD) Glitch Input Filter Enable Register */ + #define REG_PIOD_IFDR (*(__O uint32_t*)0x400E1424U) /**< \brief (PIOD) Glitch Input Filter Disable Register */ + #define REG_PIOD_IFSR (*(__I uint32_t*)0x400E1428U) /**< \brief (PIOD) Glitch Input Filter Status Register */ + #define REG_PIOD_SODR (*(__O uint32_t*)0x400E1430U) /**< \brief (PIOD) Set Output Data Register */ + #define REG_PIOD_CODR (*(__O uint32_t*)0x400E1434U) /**< \brief (PIOD) Clear Output Data Register */ + #define REG_PIOD_ODSR (*(__IO uint32_t*)0x400E1438U) /**< \brief (PIOD) Output Data Status Register */ + #define REG_PIOD_PDSR (*(__I uint32_t*)0x400E143CU) /**< \brief (PIOD) Pin Data Status Register */ + #define REG_PIOD_IER (*(__O uint32_t*)0x400E1440U) /**< \brief (PIOD) Interrupt Enable Register */ + #define REG_PIOD_IDR (*(__O uint32_t*)0x400E1444U) /**< \brief (PIOD) Interrupt Disable Register */ + #define REG_PIOD_IMR (*(__I uint32_t*)0x400E1448U) /**< \brief (PIOD) Interrupt Mask Register */ + #define REG_PIOD_ISR (*(__I uint32_t*)0x400E144CU) /**< \brief (PIOD) Interrupt Status Register */ + #define REG_PIOD_MDER (*(__O uint32_t*)0x400E1450U) /**< \brief (PIOD) Multi-driver Enable Register */ + #define REG_PIOD_MDDR (*(__O uint32_t*)0x400E1454U) /**< \brief (PIOD) Multi-driver Disable Register */ + #define REG_PIOD_MDSR (*(__I uint32_t*)0x400E1458U) /**< \brief (PIOD) Multi-driver Status Register */ + #define REG_PIOD_PUDR (*(__O uint32_t*)0x400E1460U) /**< \brief (PIOD) Pull-up Disable Register */ + #define REG_PIOD_PUER (*(__O uint32_t*)0x400E1464U) /**< \brief (PIOD) Pull-up Enable Register */ + #define REG_PIOD_PUSR (*(__I uint32_t*)0x400E1468U) /**< \brief (PIOD) Pad Pull-up Status Register */ + #define REG_PIOD_ABCDSR (*(__IO uint32_t*)0x400E1470U) /**< \brief (PIOD) Peripheral Select Register */ + #define REG_PIOD_IFSCDR (*(__O uint32_t*)0x400E1480U) /**< \brief (PIOD) Input Filter Slow Clock Disable Register */ + #define REG_PIOD_IFSCER (*(__O uint32_t*)0x400E1484U) /**< \brief (PIOD) Input Filter Slow Clock Enable Register */ + #define REG_PIOD_IFSCSR (*(__I uint32_t*)0x400E1488U) /**< \brief (PIOD) Input Filter Slow Clock Status Register */ + #define REG_PIOD_SCDR (*(__IO uint32_t*)0x400E148CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */ + #define REG_PIOD_PPDDR (*(__O uint32_t*)0x400E1490U) /**< \brief (PIOD) Pad Pull-down Disable Register */ + #define REG_PIOD_PPDER (*(__O uint32_t*)0x400E1494U) /**< \brief (PIOD) Pad Pull-down Enable Register */ + #define REG_PIOD_PPDSR (*(__I uint32_t*)0x400E1498U) /**< \brief (PIOD) Pad Pull-down Status Register */ + #define REG_PIOD_OWER (*(__O uint32_t*)0x400E14A0U) /**< \brief (PIOD) Output Write Enable */ + #define REG_PIOD_OWDR (*(__O uint32_t*)0x400E14A4U) /**< \brief (PIOD) Output Write Disable */ + #define REG_PIOD_OWSR (*(__I uint32_t*)0x400E14A8U) /**< \brief (PIOD) Output Write Status Register */ + #define REG_PIOD_AIMER (*(__O uint32_t*)0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */ + #define REG_PIOD_AIMDR (*(__O uint32_t*)0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Modes Disable Register */ + #define REG_PIOD_AIMMR (*(__I uint32_t*)0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */ + #define REG_PIOD_ESR (*(__O uint32_t*)0x400E14C0U) /**< \brief (PIOD) Edge Select Register */ + #define REG_PIOD_LSR (*(__O uint32_t*)0x400E14C4U) /**< \brief (PIOD) Level Select Register */ + #define REG_PIOD_ELSR (*(__I uint32_t*)0x400E14C8U) /**< \brief (PIOD) Edge/Level Status Register */ + #define REG_PIOD_FELLSR (*(__O uint32_t*)0x400E14D0U) /**< \brief (PIOD) Falling Edge/Low-Level Select Register */ + #define REG_PIOD_REHLSR (*(__O uint32_t*)0x400E14D4U) /**< \brief (PIOD) Rising Edge/High-Level Select Register */ + #define REG_PIOD_FRLHSR (*(__I uint32_t*)0x400E14D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */ + #define REG_PIOD_LOCKSR (*(__I uint32_t*)0x400E14E0U) /**< \brief (PIOD) Lock Status */ + #define REG_PIOD_WPMR (*(__IO uint32_t*)0x400E14E4U) /**< \brief (PIOD) Write Protection Mode Register */ + #define REG_PIOD_WPSR (*(__I uint32_t*)0x400E14E8U) /**< \brief (PIOD) Write Protection Status Register */ + #define REG_PIOD_SCHMITT (*(__IO uint32_t*)0x400E1500U) /**< \brief (PIOD) Schmitt Trigger Register */ + #define REG_PIOD_KER (*(__IO uint32_t*)0x400E1520U) /**< \brief (PIOD) Keypad Controller Enable Register */ + #define REG_PIOD_KRCR (*(__IO uint32_t*)0x400E1524U) /**< \brief (PIOD) Keypad Controller Row Column Register */ + #define REG_PIOD_KDR (*(__IO uint32_t*)0x400E1528U) /**< \brief (PIOD) Keypad Controller Debouncing Register */ + #define REG_PIOD_KIER (*(__O uint32_t*)0x400E1530U) /**< \brief (PIOD) Keypad Controller Interrupt Enable Register */ + #define REG_PIOD_KIDR (*(__O uint32_t*)0x400E1534U) /**< \brief (PIOD) Keypad Controller Interrupt Disable Register */ + #define REG_PIOD_KIMR (*(__I uint32_t*)0x400E1538U) /**< \brief (PIOD) Keypad Controller Interrupt Mask Register */ + #define REG_PIOD_KSR (*(__I uint32_t*)0x400E153CU) /**< \brief (PIOD) Keypad Controller Status Register */ + #define REG_PIOD_KKPR (*(__I uint32_t*)0x400E1540U) /**< \brief (PIOD) Keypad Controller Key Press Register */ + #define REG_PIOD_KKRR (*(__I uint32_t*)0x400E1544U) /**< \brief (PIOD) Keypad Controller Key Release Register */ + #define REG_PIOD_PCMR (*(__IO uint32_t*)0x400E1550U) /**< \brief (PIOD) Parallel Capture Mode Register */ + #define REG_PIOD_PCIER (*(__O uint32_t*)0x400E1554U) /**< \brief (PIOD) Parallel Capture Interrupt Enable Register */ + #define REG_PIOD_PCIDR (*(__O uint32_t*)0x400E1558U) /**< \brief (PIOD) Parallel Capture Interrupt Disable Register */ + #define REG_PIOD_PCIMR (*(__I uint32_t*)0x400E155CU) /**< \brief (PIOD) Parallel Capture Interrupt Mask Register */ + #define REG_PIOD_PCISR (*(__I uint32_t*)0x400E1560U) /**< \brief (PIOD) Parallel Capture Interrupt Status Register */ + #define REG_PIOD_PCRHR (*(__I uint32_t*)0x400E1564U) /**< \brief (PIOD) Parallel Capture Reception Holding Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_PIOD_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_pioe.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_pioe.h new file mode 100644 index 00000000..c0162332 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_pioe.h @@ -0,0 +1,162 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_PIOE_INSTANCE_ +#define _SAMV71_PIOE_INSTANCE_ + +/* ========== Register definition for PIOE peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PIOE_PER (0x400E1600U) /**< \brief (PIOE) PIO Enable Register */ + #define REG_PIOE_PDR (0x400E1604U) /**< \brief (PIOE) PIO Disable Register */ + #define REG_PIOE_PSR (0x400E1608U) /**< \brief (PIOE) PIO Status Register */ + #define REG_PIOE_OER (0x400E1610U) /**< \brief (PIOE) Output Enable Register */ + #define REG_PIOE_ODR (0x400E1614U) /**< \brief (PIOE) Output Disable Register */ + #define REG_PIOE_OSR (0x400E1618U) /**< \brief (PIOE) Output Status Register */ + #define REG_PIOE_IFER (0x400E1620U) /**< \brief (PIOE) Glitch Input Filter Enable Register */ + #define REG_PIOE_IFDR (0x400E1624U) /**< \brief (PIOE) Glitch Input Filter Disable Register */ + #define REG_PIOE_IFSR (0x400E1628U) /**< \brief (PIOE) Glitch Input Filter Status Register */ + #define REG_PIOE_SODR (0x400E1630U) /**< \brief (PIOE) Set Output Data Register */ + #define REG_PIOE_CODR (0x400E1634U) /**< \brief (PIOE) Clear Output Data Register */ + #define REG_PIOE_ODSR (0x400E1638U) /**< \brief (PIOE) Output Data Status Register */ + #define REG_PIOE_PDSR (0x400E163CU) /**< \brief (PIOE) Pin Data Status Register */ + #define REG_PIOE_IER (0x400E1640U) /**< \brief (PIOE) Interrupt Enable Register */ + #define REG_PIOE_IDR (0x400E1644U) /**< \brief (PIOE) Interrupt Disable Register */ + #define REG_PIOE_IMR (0x400E1648U) /**< \brief (PIOE) Interrupt Mask Register */ + #define REG_PIOE_ISR (0x400E164CU) /**< \brief (PIOE) Interrupt Status Register */ + #define REG_PIOE_MDER (0x400E1650U) /**< \brief (PIOE) Multi-driver Enable Register */ + #define REG_PIOE_MDDR (0x400E1654U) /**< \brief (PIOE) Multi-driver Disable Register */ + #define REG_PIOE_MDSR (0x400E1658U) /**< \brief (PIOE) Multi-driver Status Register */ + #define REG_PIOE_PUDR (0x400E1660U) /**< \brief (PIOE) Pull-up Disable Register */ + #define REG_PIOE_PUER (0x400E1664U) /**< \brief (PIOE) Pull-up Enable Register */ + #define REG_PIOE_PUSR (0x400E1668U) /**< \brief (PIOE) Pad Pull-up Status Register */ + #define REG_PIOE_ABCDSR (0x400E1670U) /**< \brief (PIOE) Peripheral Select Register */ + #define REG_PIOE_IFSCDR (0x400E1680U) /**< \brief (PIOE) Input Filter Slow Clock Disable Register */ + #define REG_PIOE_IFSCER (0x400E1684U) /**< \brief (PIOE) Input Filter Slow Clock Enable Register */ + #define REG_PIOE_IFSCSR (0x400E1688U) /**< \brief (PIOE) Input Filter Slow Clock Status Register */ + #define REG_PIOE_SCDR (0x400E168CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */ + #define REG_PIOE_PPDDR (0x400E1690U) /**< \brief (PIOE) Pad Pull-down Disable Register */ + #define REG_PIOE_PPDER (0x400E1694U) /**< \brief (PIOE) Pad Pull-down Enable Register */ + #define REG_PIOE_PPDSR (0x400E1698U) /**< \brief (PIOE) Pad Pull-down Status Register */ + #define REG_PIOE_OWER (0x400E16A0U) /**< \brief (PIOE) Output Write Enable */ + #define REG_PIOE_OWDR (0x400E16A4U) /**< \brief (PIOE) Output Write Disable */ + #define REG_PIOE_OWSR (0x400E16A8U) /**< \brief (PIOE) Output Write Status Register */ + #define REG_PIOE_AIMER (0x400E16B0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */ + #define REG_PIOE_AIMDR (0x400E16B4U) /**< \brief (PIOE) Additional Interrupt Modes Disable Register */ + #define REG_PIOE_AIMMR (0x400E16B8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */ + #define REG_PIOE_ESR (0x400E16C0U) /**< \brief (PIOE) Edge Select Register */ + #define REG_PIOE_LSR (0x400E16C4U) /**< \brief (PIOE) Level Select Register */ + #define REG_PIOE_ELSR (0x400E16C8U) /**< \brief (PIOE) Edge/Level Status Register */ + #define REG_PIOE_FELLSR (0x400E16D0U) /**< \brief (PIOE) Falling Edge/Low-Level Select Register */ + #define REG_PIOE_REHLSR (0x400E16D4U) /**< \brief (PIOE) Rising Edge/High-Level Select Register */ + #define REG_PIOE_FRLHSR (0x400E16D8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */ + #define REG_PIOE_LOCKSR (0x400E16E0U) /**< \brief (PIOE) Lock Status */ + #define REG_PIOE_WPMR (0x400E16E4U) /**< \brief (PIOE) Write Protection Mode Register */ + #define REG_PIOE_WPSR (0x400E16E8U) /**< \brief (PIOE) Write Protection Status Register */ + #define REG_PIOE_SCHMITT (0x400E1700U) /**< \brief (PIOE) Schmitt Trigger Register */ + #define REG_PIOE_KER (0x400E1720U) /**< \brief (PIOE) Keypad Controller Enable Register */ + #define REG_PIOE_KRCR (0x400E1724U) /**< \brief (PIOE) Keypad Controller Row Column Register */ + #define REG_PIOE_KDR (0x400E1728U) /**< \brief (PIOE) Keypad Controller Debouncing Register */ + #define REG_PIOE_KIER (0x400E1730U) /**< \brief (PIOE) Keypad Controller Interrupt Enable Register */ + #define REG_PIOE_KIDR (0x400E1734U) /**< \brief (PIOE) Keypad Controller Interrupt Disable Register */ + #define REG_PIOE_KIMR (0x400E1738U) /**< \brief (PIOE) Keypad Controller Interrupt Mask Register */ + #define REG_PIOE_KSR (0x400E173CU) /**< \brief (PIOE) Keypad Controller Status Register */ + #define REG_PIOE_KKPR (0x400E1740U) /**< \brief (PIOE) Keypad Controller Key Press Register */ + #define REG_PIOE_KKRR (0x400E1744U) /**< \brief (PIOE) Keypad Controller Key Release Register */ + #define REG_PIOE_PCMR (0x400E1750U) /**< \brief (PIOE) Parallel Capture Mode Register */ + #define REG_PIOE_PCIER (0x400E1754U) /**< \brief (PIOE) Parallel Capture Interrupt Enable Register */ + #define REG_PIOE_PCIDR (0x400E1758U) /**< \brief (PIOE) Parallel Capture Interrupt Disable Register */ + #define REG_PIOE_PCIMR (0x400E175CU) /**< \brief (PIOE) Parallel Capture Interrupt Mask Register */ + #define REG_PIOE_PCISR (0x400E1760U) /**< \brief (PIOE) Parallel Capture Interrupt Status Register */ + #define REG_PIOE_PCRHR (0x400E1764U) /**< \brief (PIOE) Parallel Capture Reception Holding Register */ +#else + #define REG_PIOE_PER (*(__O uint32_t*)0x400E1600U) /**< \brief (PIOE) PIO Enable Register */ + #define REG_PIOE_PDR (*(__O uint32_t*)0x400E1604U) /**< \brief (PIOE) PIO Disable Register */ + #define REG_PIOE_PSR (*(__I uint32_t*)0x400E1608U) /**< \brief (PIOE) PIO Status Register */ + #define REG_PIOE_OER (*(__O uint32_t*)0x400E1610U) /**< \brief (PIOE) Output Enable Register */ + #define REG_PIOE_ODR (*(__O uint32_t*)0x400E1614U) /**< \brief (PIOE) Output Disable Register */ + #define REG_PIOE_OSR (*(__I uint32_t*)0x400E1618U) /**< \brief (PIOE) Output Status Register */ + #define REG_PIOE_IFER (*(__O uint32_t*)0x400E1620U) /**< \brief (PIOE) Glitch Input Filter Enable Register */ + #define REG_PIOE_IFDR (*(__O uint32_t*)0x400E1624U) /**< \brief (PIOE) Glitch Input Filter Disable Register */ + #define REG_PIOE_IFSR (*(__I uint32_t*)0x400E1628U) /**< \brief (PIOE) Glitch Input Filter Status Register */ + #define REG_PIOE_SODR (*(__O uint32_t*)0x400E1630U) /**< \brief (PIOE) Set Output Data Register */ + #define REG_PIOE_CODR (*(__O uint32_t*)0x400E1634U) /**< \brief (PIOE) Clear Output Data Register */ + #define REG_PIOE_ODSR (*(__IO uint32_t*)0x400E1638U) /**< \brief (PIOE) Output Data Status Register */ + #define REG_PIOE_PDSR (*(__I uint32_t*)0x400E163CU) /**< \brief (PIOE) Pin Data Status Register */ + #define REG_PIOE_IER (*(__O uint32_t*)0x400E1640U) /**< \brief (PIOE) Interrupt Enable Register */ + #define REG_PIOE_IDR (*(__O uint32_t*)0x400E1644U) /**< \brief (PIOE) Interrupt Disable Register */ + #define REG_PIOE_IMR (*(__I uint32_t*)0x400E1648U) /**< \brief (PIOE) Interrupt Mask Register */ + #define REG_PIOE_ISR (*(__I uint32_t*)0x400E164CU) /**< \brief (PIOE) Interrupt Status Register */ + #define REG_PIOE_MDER (*(__O uint32_t*)0x400E1650U) /**< \brief (PIOE) Multi-driver Enable Register */ + #define REG_PIOE_MDDR (*(__O uint32_t*)0x400E1654U) /**< \brief (PIOE) Multi-driver Disable Register */ + #define REG_PIOE_MDSR (*(__I uint32_t*)0x400E1658U) /**< \brief (PIOE) Multi-driver Status Register */ + #define REG_PIOE_PUDR (*(__O uint32_t*)0x400E1660U) /**< \brief (PIOE) Pull-up Disable Register */ + #define REG_PIOE_PUER (*(__O uint32_t*)0x400E1664U) /**< \brief (PIOE) Pull-up Enable Register */ + #define REG_PIOE_PUSR (*(__I uint32_t*)0x400E1668U) /**< \brief (PIOE) Pad Pull-up Status Register */ + #define REG_PIOE_ABCDSR (*(__IO uint32_t*)0x400E1670U) /**< \brief (PIOE) Peripheral Select Register */ + #define REG_PIOE_IFSCDR (*(__O uint32_t*)0x400E1680U) /**< \brief (PIOE) Input Filter Slow Clock Disable Register */ + #define REG_PIOE_IFSCER (*(__O uint32_t*)0x400E1684U) /**< \brief (PIOE) Input Filter Slow Clock Enable Register */ + #define REG_PIOE_IFSCSR (*(__I uint32_t*)0x400E1688U) /**< \brief (PIOE) Input Filter Slow Clock Status Register */ + #define REG_PIOE_SCDR (*(__IO uint32_t*)0x400E168CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */ + #define REG_PIOE_PPDDR (*(__O uint32_t*)0x400E1690U) /**< \brief (PIOE) Pad Pull-down Disable Register */ + #define REG_PIOE_PPDER (*(__O uint32_t*)0x400E1694U) /**< \brief (PIOE) Pad Pull-down Enable Register */ + #define REG_PIOE_PPDSR (*(__I uint32_t*)0x400E1698U) /**< \brief (PIOE) Pad Pull-down Status Register */ + #define REG_PIOE_OWER (*(__O uint32_t*)0x400E16A0U) /**< \brief (PIOE) Output Write Enable */ + #define REG_PIOE_OWDR (*(__O uint32_t*)0x400E16A4U) /**< \brief (PIOE) Output Write Disable */ + #define REG_PIOE_OWSR (*(__I uint32_t*)0x400E16A8U) /**< \brief (PIOE) Output Write Status Register */ + #define REG_PIOE_AIMER (*(__O uint32_t*)0x400E16B0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */ + #define REG_PIOE_AIMDR (*(__O uint32_t*)0x400E16B4U) /**< \brief (PIOE) Additional Interrupt Modes Disable Register */ + #define REG_PIOE_AIMMR (*(__I uint32_t*)0x400E16B8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */ + #define REG_PIOE_ESR (*(__O uint32_t*)0x400E16C0U) /**< \brief (PIOE) Edge Select Register */ + #define REG_PIOE_LSR (*(__O uint32_t*)0x400E16C4U) /**< \brief (PIOE) Level Select Register */ + #define REG_PIOE_ELSR (*(__I uint32_t*)0x400E16C8U) /**< \brief (PIOE) Edge/Level Status Register */ + #define REG_PIOE_FELLSR (*(__O uint32_t*)0x400E16D0U) /**< \brief (PIOE) Falling Edge/Low-Level Select Register */ + #define REG_PIOE_REHLSR (*(__O uint32_t*)0x400E16D4U) /**< \brief (PIOE) Rising Edge/High-Level Select Register */ + #define REG_PIOE_FRLHSR (*(__I uint32_t*)0x400E16D8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */ + #define REG_PIOE_LOCKSR (*(__I uint32_t*)0x400E16E0U) /**< \brief (PIOE) Lock Status */ + #define REG_PIOE_WPMR (*(__IO uint32_t*)0x400E16E4U) /**< \brief (PIOE) Write Protection Mode Register */ + #define REG_PIOE_WPSR (*(__I uint32_t*)0x400E16E8U) /**< \brief (PIOE) Write Protection Status Register */ + #define REG_PIOE_SCHMITT (*(__IO uint32_t*)0x400E1700U) /**< \brief (PIOE) Schmitt Trigger Register */ + #define REG_PIOE_KER (*(__IO uint32_t*)0x400E1720U) /**< \brief (PIOE) Keypad Controller Enable Register */ + #define REG_PIOE_KRCR (*(__IO uint32_t*)0x400E1724U) /**< \brief (PIOE) Keypad Controller Row Column Register */ + #define REG_PIOE_KDR (*(__IO uint32_t*)0x400E1728U) /**< \brief (PIOE) Keypad Controller Debouncing Register */ + #define REG_PIOE_KIER (*(__O uint32_t*)0x400E1730U) /**< \brief (PIOE) Keypad Controller Interrupt Enable Register */ + #define REG_PIOE_KIDR (*(__O uint32_t*)0x400E1734U) /**< \brief (PIOE) Keypad Controller Interrupt Disable Register */ + #define REG_PIOE_KIMR (*(__I uint32_t*)0x400E1738U) /**< \brief (PIOE) Keypad Controller Interrupt Mask Register */ + #define REG_PIOE_KSR (*(__I uint32_t*)0x400E173CU) /**< \brief (PIOE) Keypad Controller Status Register */ + #define REG_PIOE_KKPR (*(__I uint32_t*)0x400E1740U) /**< \brief (PIOE) Keypad Controller Key Press Register */ + #define REG_PIOE_KKRR (*(__I uint32_t*)0x400E1744U) /**< \brief (PIOE) Keypad Controller Key Release Register */ + #define REG_PIOE_PCMR (*(__IO uint32_t*)0x400E1750U) /**< \brief (PIOE) Parallel Capture Mode Register */ + #define REG_PIOE_PCIER (*(__O uint32_t*)0x400E1754U) /**< \brief (PIOE) Parallel Capture Interrupt Enable Register */ + #define REG_PIOE_PCIDR (*(__O uint32_t*)0x400E1758U) /**< \brief (PIOE) Parallel Capture Interrupt Disable Register */ + #define REG_PIOE_PCIMR (*(__I uint32_t*)0x400E175CU) /**< \brief (PIOE) Parallel Capture Interrupt Mask Register */ + #define REG_PIOE_PCISR (*(__I uint32_t*)0x400E1760U) /**< \brief (PIOE) Parallel Capture Interrupt Status Register */ + #define REG_PIOE_PCRHR (*(__I uint32_t*)0x400E1764U) /**< \brief (PIOE) Parallel Capture Reception Holding Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_PIOE_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_pmc.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_pmc.h new file mode 100644 index 00000000..56723b35 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_pmc.h @@ -0,0 +1,110 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_PMC_INSTANCE_ +#define _SAMV71_PMC_INSTANCE_ + +/* ========== Register definition for PMC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PMC_SCER (0x400E0600U) /**< \brief (PMC) System Clock Enable Register */ + #define REG_PMC_SCDR (0x400E0604U) /**< \brief (PMC) System Clock Disable Register */ + #define REG_PMC_SCSR (0x400E0608U) /**< \brief (PMC) System Clock Status Register */ + #define REG_PMC_PCER0 (0x400E0610U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ + #define REG_PMC_PCDR0 (0x400E0614U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ + #define REG_PMC_PCSR0 (0x400E0618U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ + #define REG_CKGR_UCKR (0x400E061CU) /**< \brief (PMC) UTMI Clock Register */ + #define REG_CKGR_MOR (0x400E0620U) /**< \brief (PMC) Main Oscillator Register */ + #define REG_CKGR_MCFR (0x400E0624U) /**< \brief (PMC) Main Clock Frequency Register */ + #define REG_CKGR_PLLAR (0x400E0628U) /**< \brief (PMC) PLLA Register */ + #define REG_PMC_MCKR (0x400E0630U) /**< \brief (PMC) Master Clock Register */ + #define REG_PMC_USB (0x400E0638U) /**< \brief (PMC) USB Clock Register */ + #define REG_PMC_PCK (0x400E0640U) /**< \brief (PMC) Programmable Clock 0 Register */ + #define REG_PMC_IER (0x400E0660U) /**< \brief (PMC) Interrupt Enable Register */ + #define REG_PMC_IDR (0x400E0664U) /**< \brief (PMC) Interrupt Disable Register */ + #define REG_PMC_SR (0x400E0668U) /**< \brief (PMC) Status Register */ + #define REG_PMC_IMR (0x400E066CU) /**< \brief (PMC) Interrupt Mask Register */ + #define REG_PMC_FSMR (0x400E0670U) /**< \brief (PMC) Fast Startup Mode Register */ + #define REG_PMC_FSPR (0x400E0674U) /**< \brief (PMC) Fast Startup Polarity Register */ + #define REG_PMC_FOCR (0x400E0678U) /**< \brief (PMC) Fault Output Clear Register */ + #define REG_PMC_WPMR (0x400E06E4U) /**< \brief (PMC) Write Protection Mode Register */ + #define REG_PMC_WPSR (0x400E06E8U) /**< \brief (PMC) Write Protection Status Register */ + #define REG_PMC_PCER1 (0x400E0700U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */ + #define REG_PMC_PCDR1 (0x400E0704U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ + #define REG_PMC_PCSR1 (0x400E0708U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ + #define REG_PMC_PCR (0x400E070CU) /**< \brief (PMC) Peripheral Control Register */ + #define REG_PMC_OCR (0x400E0710U) /**< \brief (PMC) Oscillator Calibration Register */ + #define REG_PMC_SLPWK_ER0 (0x400E0714U) /**< \brief (PMC) SleepWalking Enable Register 0 */ + #define REG_PMC_SLPWK_DR0 (0x400E0718U) /**< \brief (PMC) SleepWalking Disable Register 0 */ + #define REG_PMC_SLPWK_SR0 (0x400E071CU) /**< \brief (PMC) SleepWalking Status Register 0 */ + #define REG_PMC_SLPWK_ASR0 (0x400E0720U) /**< \brief (PMC) SleepWalking Activity Status Register 0 */ + #define REG_PMC_SLPWK_ER1 (0x400E0734U) /**< \brief (PMC) SleepWalking Enable Register 1 */ + #define REG_PMC_SLPWK_DR1 (0x400E0738U) /**< \brief (PMC) SleepWalking Disable Register 1 */ + #define REG_PMC_SLPWK_SR1 (0x400E073CU) /**< \brief (PMC) SleepWalking Status Register 1 */ + #define REG_PMC_SLPWK_ASR1 (0x400E0740U) /**< \brief (PMC) SleepWalking Activity Status Register 1 */ + #define REG_PMC_SLPWK_AIPR (0x400E0744U) /**< \brief (PMC) SleepWalking Activity In Progress Register */ +#else + #define REG_PMC_SCER (*(__O uint32_t*)0x400E0600U) /**< \brief (PMC) System Clock Enable Register */ + #define REG_PMC_SCDR (*(__O uint32_t*)0x400E0604U) /**< \brief (PMC) System Clock Disable Register */ + #define REG_PMC_SCSR (*(__I uint32_t*)0x400E0608U) /**< \brief (PMC) System Clock Status Register */ + #define REG_PMC_PCER0 (*(__O uint32_t*)0x400E0610U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ + #define REG_PMC_PCDR0 (*(__O uint32_t*)0x400E0614U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ + #define REG_PMC_PCSR0 (*(__I uint32_t*)0x400E0618U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ + #define REG_CKGR_UCKR (*(__IO uint32_t*)0x400E061CU) /**< \brief (PMC) UTMI Clock Register */ + #define REG_CKGR_MOR (*(__IO uint32_t*)0x400E0620U) /**< \brief (PMC) Main Oscillator Register */ + #define REG_CKGR_MCFR (*(__IO uint32_t*)0x400E0624U) /**< \brief (PMC) Main Clock Frequency Register */ + #define REG_CKGR_PLLAR (*(__IO uint32_t*)0x400E0628U) /**< \brief (PMC) PLLA Register */ + #define REG_PMC_MCKR (*(__IO uint32_t*)0x400E0630U) /**< \brief (PMC) Master Clock Register */ + #define REG_PMC_USB (*(__IO uint32_t*)0x400E0638U) /**< \brief (PMC) USB Clock Register */ + #define REG_PMC_PCK (*(__IO uint32_t*)0x400E0640U) /**< \brief (PMC) Programmable Clock 0 Register */ + #define REG_PMC_IER (*(__O uint32_t*)0x400E0660U) /**< \brief (PMC) Interrupt Enable Register */ + #define REG_PMC_IDR (*(__O uint32_t*)0x400E0664U) /**< \brief (PMC) Interrupt Disable Register */ + #define REG_PMC_SR (*(__I uint32_t*)0x400E0668U) /**< \brief (PMC) Status Register */ + #define REG_PMC_IMR (*(__I uint32_t*)0x400E066CU) /**< \brief (PMC) Interrupt Mask Register */ + #define REG_PMC_FSMR (*(__IO uint32_t*)0x400E0670U) /**< \brief (PMC) Fast Startup Mode Register */ + #define REG_PMC_FSPR (*(__IO uint32_t*)0x400E0674U) /**< \brief (PMC) Fast Startup Polarity Register */ + #define REG_PMC_FOCR (*(__O uint32_t*)0x400E0678U) /**< \brief (PMC) Fault Output Clear Register */ + #define REG_PMC_WPMR (*(__IO uint32_t*)0x400E06E4U) /**< \brief (PMC) Write Protection Mode Register */ + #define REG_PMC_WPSR (*(__I uint32_t*)0x400E06E8U) /**< \brief (PMC) Write Protection Status Register */ + #define REG_PMC_PCER1 (*(__O uint32_t*)0x400E0700U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */ + #define REG_PMC_PCDR1 (*(__O uint32_t*)0x400E0704U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ + #define REG_PMC_PCSR1 (*(__I uint32_t*)0x400E0708U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ + #define REG_PMC_PCR (*(__IO uint32_t*)0x400E070CU) /**< \brief (PMC) Peripheral Control Register */ + #define REG_PMC_OCR (*(__IO uint32_t*)0x400E0710U) /**< \brief (PMC) Oscillator Calibration Register */ + #define REG_PMC_SLPWK_ER0 (*(__O uint32_t*)0x400E0714U) /**< \brief (PMC) SleepWalking Enable Register 0 */ + #define REG_PMC_SLPWK_DR0 (*(__O uint32_t*)0x400E0718U) /**< \brief (PMC) SleepWalking Disable Register 0 */ + #define REG_PMC_SLPWK_SR0 (*(__I uint32_t*)0x400E071CU) /**< \brief (PMC) SleepWalking Status Register 0 */ + #define REG_PMC_SLPWK_ASR0 (*(__I uint32_t*)0x400E0720U) /**< \brief (PMC) SleepWalking Activity Status Register 0 */ + #define REG_PMC_SLPWK_ER1 (*(__O uint32_t*)0x400E0734U) /**< \brief (PMC) SleepWalking Enable Register 1 */ + #define REG_PMC_SLPWK_DR1 (*(__O uint32_t*)0x400E0738U) /**< \brief (PMC) SleepWalking Disable Register 1 */ + #define REG_PMC_SLPWK_SR1 (*(__I uint32_t*)0x400E073CU) /**< \brief (PMC) SleepWalking Status Register 1 */ + #define REG_PMC_SLPWK_ASR1 (*(__I uint32_t*)0x400E0740U) /**< \brief (PMC) SleepWalking Activity Status Register 1 */ + #define REG_PMC_SLPWK_AIPR (*(__I uint32_t*)0x400E0744U) /**< \brief (PMC) SleepWalking Activity In Progress Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_PMC_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_pwm0.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_pwm0.h new file mode 100644 index 00000000..a0e6ee19 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_pwm0.h @@ -0,0 +1,260 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_PWM0_INSTANCE_ +#define _SAMV71_PWM0_INSTANCE_ + +/* ========== Register definition for PWM0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PWM0_CLK (0x40020000U) /**< \brief (PWM0) PWM Clock Register */ + #define REG_PWM0_ENA (0x40020004U) /**< \brief (PWM0) PWM Enable Register */ + #define REG_PWM0_DIS (0x40020008U) /**< \brief (PWM0) PWM Disable Register */ + #define REG_PWM0_SR (0x4002000CU) /**< \brief (PWM0) PWM Status Register */ + #define REG_PWM0_IER1 (0x40020010U) /**< \brief (PWM0) PWM Interrupt Enable Register 1 */ + #define REG_PWM0_IDR1 (0x40020014U) /**< \brief (PWM0) PWM Interrupt Disable Register 1 */ + #define REG_PWM0_IMR1 (0x40020018U) /**< \brief (PWM0) PWM Interrupt Mask Register 1 */ + #define REG_PWM0_ISR1 (0x4002001CU) /**< \brief (PWM0) PWM Interrupt Status Register 1 */ + #define REG_PWM0_SCM (0x40020020U) /**< \brief (PWM0) PWM Sync Channels Mode Register */ + #define REG_PWM0_DMAR (0x40020024U) /**< \brief (PWM0) PWM DMA Register */ + #define REG_PWM0_SCUC (0x40020028U) /**< \brief (PWM0) PWM Sync Channels Update Control Register */ + #define REG_PWM0_SCUP (0x4002002CU) /**< \brief (PWM0) PWM Sync Channels Update Period Register */ + #define REG_PWM0_SCUPUPD (0x40020030U) /**< \brief (PWM0) PWM Sync Channels Update Period Update Register */ + #define REG_PWM0_IER2 (0x40020034U) /**< \brief (PWM0) PWM Interrupt Enable Register 2 */ + #define REG_PWM0_IDR2 (0x40020038U) /**< \brief (PWM0) PWM Interrupt Disable Register 2 */ + #define REG_PWM0_IMR2 (0x4002003CU) /**< \brief (PWM0) PWM Interrupt Mask Register 2 */ + #define REG_PWM0_ISR2 (0x40020040U) /**< \brief (PWM0) PWM Interrupt Status Register 2 */ + #define REG_PWM0_OOV (0x40020044U) /**< \brief (PWM0) PWM Output Override Value Register */ + #define REG_PWM0_OS (0x40020048U) /**< \brief (PWM0) PWM Output Selection Register */ + #define REG_PWM0_OSS (0x4002004CU) /**< \brief (PWM0) PWM Output Selection Set Register */ + #define REG_PWM0_OSC (0x40020050U) /**< \brief (PWM0) PWM Output Selection Clear Register */ + #define REG_PWM0_OSSUPD (0x40020054U) /**< \brief (PWM0) PWM Output Selection Set Update Register */ + #define REG_PWM0_OSCUPD (0x40020058U) /**< \brief (PWM0) PWM Output Selection Clear Update Register */ + #define REG_PWM0_FMR (0x4002005CU) /**< \brief (PWM0) PWM Fault Mode Register */ + #define REG_PWM0_FSR (0x40020060U) /**< \brief (PWM0) PWM Fault Status Register */ + #define REG_PWM0_FCR (0x40020064U) /**< \brief (PWM0) PWM Fault Clear Register */ + #define REG_PWM0_FPV1 (0x40020068U) /**< \brief (PWM0) PWM Fault Protection Value Register 1 */ + #define REG_PWM0_FPE (0x4002006CU) /**< \brief (PWM0) PWM Fault Protection Enable Register */ + #define REG_PWM0_ELMR (0x4002007CU) /**< \brief (PWM0) PWM Event Line 0 Mode Register */ + #define REG_PWM0_SSPR (0x400200A0U) /**< \brief (PWM0) PWM Spread Spectrum Register */ + #define REG_PWM0_SSPUP (0x400200A4U) /**< \brief (PWM0) PWM Spread Spectrum Update Register */ + #define REG_PWM0_SMMR (0x400200B0U) /**< \brief (PWM0) PWM Stepper Motor Mode Register */ + #define REG_PWM0_FPV2 (0x400200C0U) /**< \brief (PWM0) PWM Fault Protection Value 2 Register */ + #define REG_PWM0_WPCR (0x400200E4U) /**< \brief (PWM0) PWM Write Protection Control Register */ + #define REG_PWM0_WPSR (0x400200E8U) /**< \brief (PWM0) PWM Write Protection Status Register */ + #define REG_PWM0_CMPV0 (0x40020130U) /**< \brief (PWM0) PWM Comparison 0 Value Register */ + #define REG_PWM0_CMPVUPD0 (0x40020134U) /**< \brief (PWM0) PWM Comparison 0 Value Update Register */ + #define REG_PWM0_CMPM0 (0x40020138U) /**< \brief (PWM0) PWM Comparison 0 Mode Register */ + #define REG_PWM0_CMPMUPD0 (0x4002013CU) /**< \brief (PWM0) PWM Comparison 0 Mode Update Register */ + #define REG_PWM0_CMPV1 (0x40020140U) /**< \brief (PWM0) PWM Comparison 1 Value Register */ + #define REG_PWM0_CMPVUPD1 (0x40020144U) /**< \brief (PWM0) PWM Comparison 1 Value Update Register */ + #define REG_PWM0_CMPM1 (0x40020148U) /**< \brief (PWM0) PWM Comparison 1 Mode Register */ + #define REG_PWM0_CMPMUPD1 (0x4002014CU) /**< \brief (PWM0) PWM Comparison 1 Mode Update Register */ + #define REG_PWM0_CMPV2 (0x40020150U) /**< \brief (PWM0) PWM Comparison 2 Value Register */ + #define REG_PWM0_CMPVUPD2 (0x40020154U) /**< \brief (PWM0) PWM Comparison 2 Value Update Register */ + #define REG_PWM0_CMPM2 (0x40020158U) /**< \brief (PWM0) PWM Comparison 2 Mode Register */ + #define REG_PWM0_CMPMUPD2 (0x4002015CU) /**< \brief (PWM0) PWM Comparison 2 Mode Update Register */ + #define REG_PWM0_CMPV3 (0x40020160U) /**< \brief (PWM0) PWM Comparison 3 Value Register */ + #define REG_PWM0_CMPVUPD3 (0x40020164U) /**< \brief (PWM0) PWM Comparison 3 Value Update Register */ + #define REG_PWM0_CMPM3 (0x40020168U) /**< \brief (PWM0) PWM Comparison 3 Mode Register */ + #define REG_PWM0_CMPMUPD3 (0x4002016CU) /**< \brief (PWM0) PWM Comparison 3 Mode Update Register */ + #define REG_PWM0_CMPV4 (0x40020170U) /**< \brief (PWM0) PWM Comparison 4 Value Register */ + #define REG_PWM0_CMPVUPD4 (0x40020174U) /**< \brief (PWM0) PWM Comparison 4 Value Update Register */ + #define REG_PWM0_CMPM4 (0x40020178U) /**< \brief (PWM0) PWM Comparison 4 Mode Register */ + #define REG_PWM0_CMPMUPD4 (0x4002017CU) /**< \brief (PWM0) PWM Comparison 4 Mode Update Register */ + #define REG_PWM0_CMPV5 (0x40020180U) /**< \brief (PWM0) PWM Comparison 5 Value Register */ + #define REG_PWM0_CMPVUPD5 (0x40020184U) /**< \brief (PWM0) PWM Comparison 5 Value Update Register */ + #define REG_PWM0_CMPM5 (0x40020188U) /**< \brief (PWM0) PWM Comparison 5 Mode Register */ + #define REG_PWM0_CMPMUPD5 (0x4002018CU) /**< \brief (PWM0) PWM Comparison 5 Mode Update Register */ + #define REG_PWM0_CMPV6 (0x40020190U) /**< \brief (PWM0) PWM Comparison 6 Value Register */ + #define REG_PWM0_CMPVUPD6 (0x40020194U) /**< \brief (PWM0) PWM Comparison 6 Value Update Register */ + #define REG_PWM0_CMPM6 (0x40020198U) /**< \brief (PWM0) PWM Comparison 6 Mode Register */ + #define REG_PWM0_CMPMUPD6 (0x4002019CU) /**< \brief (PWM0) PWM Comparison 6 Mode Update Register */ + #define REG_PWM0_CMPV7 (0x400201A0U) /**< \brief (PWM0) PWM Comparison 7 Value Register */ + #define REG_PWM0_CMPVUPD7 (0x400201A4U) /**< \brief (PWM0) PWM Comparison 7 Value Update Register */ + #define REG_PWM0_CMPM7 (0x400201A8U) /**< \brief (PWM0) PWM Comparison 7 Mode Register */ + #define REG_PWM0_CMPMUPD7 (0x400201ACU) /**< \brief (PWM0) PWM Comparison 7 Mode Update Register */ + #define REG_PWM0_CMR0 (0x40020200U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 0) */ + #define REG_PWM0_CDTY0 (0x40020204U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 0) */ + #define REG_PWM0_CDTYUPD0 (0x40020208U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 0) */ + #define REG_PWM0_CPRD0 (0x4002020CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 0) */ + #define REG_PWM0_CPRDUPD0 (0x40020210U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 0) */ + #define REG_PWM0_CCNT0 (0x40020214U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 0) */ + #define REG_PWM0_DT0 (0x40020218U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 0) */ + #define REG_PWM0_DTUPD0 (0x4002021CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 0) */ + #define REG_PWM0_CMR1 (0x40020220U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 1) */ + #define REG_PWM0_CDTY1 (0x40020224U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 1) */ + #define REG_PWM0_CDTYUPD1 (0x40020228U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 1) */ + #define REG_PWM0_CPRD1 (0x4002022CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 1) */ + #define REG_PWM0_CPRDUPD1 (0x40020230U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 1) */ + #define REG_PWM0_CCNT1 (0x40020234U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 1) */ + #define REG_PWM0_DT1 (0x40020238U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 1) */ + #define REG_PWM0_DTUPD1 (0x4002023CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 1) */ + #define REG_PWM0_CMR2 (0x40020240U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 2) */ + #define REG_PWM0_CDTY2 (0x40020244U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 2) */ + #define REG_PWM0_CDTYUPD2 (0x40020248U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 2) */ + #define REG_PWM0_CPRD2 (0x4002024CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 2) */ + #define REG_PWM0_CPRDUPD2 (0x40020250U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 2) */ + #define REG_PWM0_CCNT2 (0x40020254U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 2) */ + #define REG_PWM0_DT2 (0x40020258U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 2) */ + #define REG_PWM0_DTUPD2 (0x4002025CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 2) */ + #define REG_PWM0_CMR3 (0x40020260U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 3) */ + #define REG_PWM0_CDTY3 (0x40020264U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 3) */ + #define REG_PWM0_CDTYUPD3 (0x40020268U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 3) */ + #define REG_PWM0_CPRD3 (0x4002026CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 3) */ + #define REG_PWM0_CPRDUPD3 (0x40020270U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 3) */ + #define REG_PWM0_CCNT3 (0x40020274U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 3) */ + #define REG_PWM0_DT3 (0x40020278U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 3) */ + #define REG_PWM0_DTUPD3 (0x4002027CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 3) */ + #define REG_PWM0_CMUPD0 (0x40020400U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 0) */ + #define REG_PWM0_CMUPD1 (0x40020420U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 1) */ + #define REG_PWM0_ETRG1 (0x4002042CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 1) */ + #define REG_PWM0_LEBR1 (0x40020430U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 1) */ + #define REG_PWM0_CMUPD2 (0x40020440U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 2) */ + #define REG_PWM0_ETRG2 (0x4002044CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 2) */ + #define REG_PWM0_LEBR2 (0x40020450U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 2) */ + #define REG_PWM0_CMUPD3 (0x40020460U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 3) */ + #define REG_PWM0_ETRG3 (0x4002046CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 3) */ + #define REG_PWM0_LEBR3 (0x40020470U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 3) */ + #define REG_PWM0_ETRG4 (0x4002048CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 4) */ + #define REG_PWM0_LEBR4 (0x40020490U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 4) */ +#else + #define REG_PWM0_CLK (*(__IO uint32_t*)0x40020000U) /**< \brief (PWM0) PWM Clock Register */ + #define REG_PWM0_ENA (*(__O uint32_t*)0x40020004U) /**< \brief (PWM0) PWM Enable Register */ + #define REG_PWM0_DIS (*(__O uint32_t*)0x40020008U) /**< \brief (PWM0) PWM Disable Register */ + #define REG_PWM0_SR (*(__I uint32_t*)0x4002000CU) /**< \brief (PWM0) PWM Status Register */ + #define REG_PWM0_IER1 (*(__O uint32_t*)0x40020010U) /**< \brief (PWM0) PWM Interrupt Enable Register 1 */ + #define REG_PWM0_IDR1 (*(__O uint32_t*)0x40020014U) /**< \brief (PWM0) PWM Interrupt Disable Register 1 */ + #define REG_PWM0_IMR1 (*(__I uint32_t*)0x40020018U) /**< \brief (PWM0) PWM Interrupt Mask Register 1 */ + #define REG_PWM0_ISR1 (*(__I uint32_t*)0x4002001CU) /**< \brief (PWM0) PWM Interrupt Status Register 1 */ + #define REG_PWM0_SCM (*(__IO uint32_t*)0x40020020U) /**< \brief (PWM0) PWM Sync Channels Mode Register */ + #define REG_PWM0_DMAR (*(__O uint32_t*)0x40020024U) /**< \brief (PWM0) PWM DMA Register */ + #define REG_PWM0_SCUC (*(__IO uint32_t*)0x40020028U) /**< \brief (PWM0) PWM Sync Channels Update Control Register */ + #define REG_PWM0_SCUP (*(__IO uint32_t*)0x4002002CU) /**< \brief (PWM0) PWM Sync Channels Update Period Register */ + #define REG_PWM0_SCUPUPD (*(__O uint32_t*)0x40020030U) /**< \brief (PWM0) PWM Sync Channels Update Period Update Register */ + #define REG_PWM0_IER2 (*(__O uint32_t*)0x40020034U) /**< \brief (PWM0) PWM Interrupt Enable Register 2 */ + #define REG_PWM0_IDR2 (*(__O uint32_t*)0x40020038U) /**< \brief (PWM0) PWM Interrupt Disable Register 2 */ + #define REG_PWM0_IMR2 (*(__I uint32_t*)0x4002003CU) /**< \brief (PWM0) PWM Interrupt Mask Register 2 */ + #define REG_PWM0_ISR2 (*(__I uint32_t*)0x40020040U) /**< \brief (PWM0) PWM Interrupt Status Register 2 */ + #define REG_PWM0_OOV (*(__IO uint32_t*)0x40020044U) /**< \brief (PWM0) PWM Output Override Value Register */ + #define REG_PWM0_OS (*(__IO uint32_t*)0x40020048U) /**< \brief (PWM0) PWM Output Selection Register */ + #define REG_PWM0_OSS (*(__O uint32_t*)0x4002004CU) /**< \brief (PWM0) PWM Output Selection Set Register */ + #define REG_PWM0_OSC (*(__O uint32_t*)0x40020050U) /**< \brief (PWM0) PWM Output Selection Clear Register */ + #define REG_PWM0_OSSUPD (*(__O uint32_t*)0x40020054U) /**< \brief (PWM0) PWM Output Selection Set Update Register */ + #define REG_PWM0_OSCUPD (*(__O uint32_t*)0x40020058U) /**< \brief (PWM0) PWM Output Selection Clear Update Register */ + #define REG_PWM0_FMR (*(__IO uint32_t*)0x4002005CU) /**< \brief (PWM0) PWM Fault Mode Register */ + #define REG_PWM0_FSR (*(__I uint32_t*)0x40020060U) /**< \brief (PWM0) PWM Fault Status Register */ + #define REG_PWM0_FCR (*(__O uint32_t*)0x40020064U) /**< \brief (PWM0) PWM Fault Clear Register */ + #define REG_PWM0_FPV1 (*(__IO uint32_t*)0x40020068U) /**< \brief (PWM0) PWM Fault Protection Value Register 1 */ + #define REG_PWM0_FPE (*(__IO uint32_t*)0x4002006CU) /**< \brief (PWM0) PWM Fault Protection Enable Register */ + #define REG_PWM0_ELMR (*(__IO uint32_t*)0x4002007CU) /**< \brief (PWM0) PWM Event Line 0 Mode Register */ + #define REG_PWM0_SSPR (*(__IO uint32_t*)0x400200A0U) /**< \brief (PWM0) PWM Spread Spectrum Register */ + #define REG_PWM0_SSPUP (*(__O uint32_t*)0x400200A4U) /**< \brief (PWM0) PWM Spread Spectrum Update Register */ + #define REG_PWM0_SMMR (*(__IO uint32_t*)0x400200B0U) /**< \brief (PWM0) PWM Stepper Motor Mode Register */ + #define REG_PWM0_FPV2 (*(__IO uint32_t*)0x400200C0U) /**< \brief (PWM0) PWM Fault Protection Value 2 Register */ + #define REG_PWM0_WPCR (*(__O uint32_t*)0x400200E4U) /**< \brief (PWM0) PWM Write Protection Control Register */ + #define REG_PWM0_WPSR (*(__I uint32_t*)0x400200E8U) /**< \brief (PWM0) PWM Write Protection Status Register */ + #define REG_PWM0_CMPV0 (*(__IO uint32_t*)0x40020130U) /**< \brief (PWM0) PWM Comparison 0 Value Register */ + #define REG_PWM0_CMPVUPD0 (*(__O uint32_t*)0x40020134U) /**< \brief (PWM0) PWM Comparison 0 Value Update Register */ + #define REG_PWM0_CMPM0 (*(__IO uint32_t*)0x40020138U) /**< \brief (PWM0) PWM Comparison 0 Mode Register */ + #define REG_PWM0_CMPMUPD0 (*(__O uint32_t*)0x4002013CU) /**< \brief (PWM0) PWM Comparison 0 Mode Update Register */ + #define REG_PWM0_CMPV1 (*(__IO uint32_t*)0x40020140U) /**< \brief (PWM0) PWM Comparison 1 Value Register */ + #define REG_PWM0_CMPVUPD1 (*(__O uint32_t*)0x40020144U) /**< \brief (PWM0) PWM Comparison 1 Value Update Register */ + #define REG_PWM0_CMPM1 (*(__IO uint32_t*)0x40020148U) /**< \brief (PWM0) PWM Comparison 1 Mode Register */ + #define REG_PWM0_CMPMUPD1 (*(__O uint32_t*)0x4002014CU) /**< \brief (PWM0) PWM Comparison 1 Mode Update Register */ + #define REG_PWM0_CMPV2 (*(__IO uint32_t*)0x40020150U) /**< \brief (PWM0) PWM Comparison 2 Value Register */ + #define REG_PWM0_CMPVUPD2 (*(__O uint32_t*)0x40020154U) /**< \brief (PWM0) PWM Comparison 2 Value Update Register */ + #define REG_PWM0_CMPM2 (*(__IO uint32_t*)0x40020158U) /**< \brief (PWM0) PWM Comparison 2 Mode Register */ + #define REG_PWM0_CMPMUPD2 (*(__O uint32_t*)0x4002015CU) /**< \brief (PWM0) PWM Comparison 2 Mode Update Register */ + #define REG_PWM0_CMPV3 (*(__IO uint32_t*)0x40020160U) /**< \brief (PWM0) PWM Comparison 3 Value Register */ + #define REG_PWM0_CMPVUPD3 (*(__O uint32_t*)0x40020164U) /**< \brief (PWM0) PWM Comparison 3 Value Update Register */ + #define REG_PWM0_CMPM3 (*(__IO uint32_t*)0x40020168U) /**< \brief (PWM0) PWM Comparison 3 Mode Register */ + #define REG_PWM0_CMPMUPD3 (*(__O uint32_t*)0x4002016CU) /**< \brief (PWM0) PWM Comparison 3 Mode Update Register */ + #define REG_PWM0_CMPV4 (*(__IO uint32_t*)0x40020170U) /**< \brief (PWM0) PWM Comparison 4 Value Register */ + #define REG_PWM0_CMPVUPD4 (*(__O uint32_t*)0x40020174U) /**< \brief (PWM0) PWM Comparison 4 Value Update Register */ + #define REG_PWM0_CMPM4 (*(__IO uint32_t*)0x40020178U) /**< \brief (PWM0) PWM Comparison 4 Mode Register */ + #define REG_PWM0_CMPMUPD4 (*(__O uint32_t*)0x4002017CU) /**< \brief (PWM0) PWM Comparison 4 Mode Update Register */ + #define REG_PWM0_CMPV5 (*(__IO uint32_t*)0x40020180U) /**< \brief (PWM0) PWM Comparison 5 Value Register */ + #define REG_PWM0_CMPVUPD5 (*(__O uint32_t*)0x40020184U) /**< \brief (PWM0) PWM Comparison 5 Value Update Register */ + #define REG_PWM0_CMPM5 (*(__IO uint32_t*)0x40020188U) /**< \brief (PWM0) PWM Comparison 5 Mode Register */ + #define REG_PWM0_CMPMUPD5 (*(__O uint32_t*)0x4002018CU) /**< \brief (PWM0) PWM Comparison 5 Mode Update Register */ + #define REG_PWM0_CMPV6 (*(__IO uint32_t*)0x40020190U) /**< \brief (PWM0) PWM Comparison 6 Value Register */ + #define REG_PWM0_CMPVUPD6 (*(__O uint32_t*)0x40020194U) /**< \brief (PWM0) PWM Comparison 6 Value Update Register */ + #define REG_PWM0_CMPM6 (*(__IO uint32_t*)0x40020198U) /**< \brief (PWM0) PWM Comparison 6 Mode Register */ + #define REG_PWM0_CMPMUPD6 (*(__O uint32_t*)0x4002019CU) /**< \brief (PWM0) PWM Comparison 6 Mode Update Register */ + #define REG_PWM0_CMPV7 (*(__IO uint32_t*)0x400201A0U) /**< \brief (PWM0) PWM Comparison 7 Value Register */ + #define REG_PWM0_CMPVUPD7 (*(__O uint32_t*)0x400201A4U) /**< \brief (PWM0) PWM Comparison 7 Value Update Register */ + #define REG_PWM0_CMPM7 (*(__IO uint32_t*)0x400201A8U) /**< \brief (PWM0) PWM Comparison 7 Mode Register */ + #define REG_PWM0_CMPMUPD7 (*(__O uint32_t*)0x400201ACU) /**< \brief (PWM0) PWM Comparison 7 Mode Update Register */ + #define REG_PWM0_CMR0 (*(__IO uint32_t*)0x40020200U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 0) */ + #define REG_PWM0_CDTY0 (*(__IO uint32_t*)0x40020204U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 0) */ + #define REG_PWM0_CDTYUPD0 (*(__O uint32_t*)0x40020208U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 0) */ + #define REG_PWM0_CPRD0 (*(__IO uint32_t*)0x4002020CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 0) */ + #define REG_PWM0_CPRDUPD0 (*(__O uint32_t*)0x40020210U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 0) */ + #define REG_PWM0_CCNT0 (*(__I uint32_t*)0x40020214U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 0) */ + #define REG_PWM0_DT0 (*(__IO uint32_t*)0x40020218U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 0) */ + #define REG_PWM0_DTUPD0 (*(__O uint32_t*)0x4002021CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 0) */ + #define REG_PWM0_CMR1 (*(__IO uint32_t*)0x40020220U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 1) */ + #define REG_PWM0_CDTY1 (*(__IO uint32_t*)0x40020224U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 1) */ + #define REG_PWM0_CDTYUPD1 (*(__O uint32_t*)0x40020228U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 1) */ + #define REG_PWM0_CPRD1 (*(__IO uint32_t*)0x4002022CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 1) */ + #define REG_PWM0_CPRDUPD1 (*(__O uint32_t*)0x40020230U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 1) */ + #define REG_PWM0_CCNT1 (*(__I uint32_t*)0x40020234U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 1) */ + #define REG_PWM0_DT1 (*(__IO uint32_t*)0x40020238U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 1) */ + #define REG_PWM0_DTUPD1 (*(__O uint32_t*)0x4002023CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 1) */ + #define REG_PWM0_CMR2 (*(__IO uint32_t*)0x40020240U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 2) */ + #define REG_PWM0_CDTY2 (*(__IO uint32_t*)0x40020244U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 2) */ + #define REG_PWM0_CDTYUPD2 (*(__O uint32_t*)0x40020248U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 2) */ + #define REG_PWM0_CPRD2 (*(__IO uint32_t*)0x4002024CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 2) */ + #define REG_PWM0_CPRDUPD2 (*(__O uint32_t*)0x40020250U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 2) */ + #define REG_PWM0_CCNT2 (*(__I uint32_t*)0x40020254U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 2) */ + #define REG_PWM0_DT2 (*(__IO uint32_t*)0x40020258U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 2) */ + #define REG_PWM0_DTUPD2 (*(__O uint32_t*)0x4002025CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 2) */ + #define REG_PWM0_CMR3 (*(__IO uint32_t*)0x40020260U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 3) */ + #define REG_PWM0_CDTY3 (*(__IO uint32_t*)0x40020264U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 3) */ + #define REG_PWM0_CDTYUPD3 (*(__O uint32_t*)0x40020268U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 3) */ + #define REG_PWM0_CPRD3 (*(__IO uint32_t*)0x4002026CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 3) */ + #define REG_PWM0_CPRDUPD3 (*(__O uint32_t*)0x40020270U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 3) */ + #define REG_PWM0_CCNT3 (*(__I uint32_t*)0x40020274U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 3) */ + #define REG_PWM0_DT3 (*(__IO uint32_t*)0x40020278U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 3) */ + #define REG_PWM0_DTUPD3 (*(__O uint32_t*)0x4002027CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 3) */ + #define REG_PWM0_CMUPD0 (*(__O uint32_t*)0x40020400U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 0) */ + #define REG_PWM0_CMUPD1 (*(__O uint32_t*)0x40020420U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 1) */ + #define REG_PWM0_ETRG1 (*(__IO uint32_t*)0x4002042CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 1) */ + #define REG_PWM0_LEBR1 (*(__IO uint32_t*)0x40020430U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 1) */ + #define REG_PWM0_CMUPD2 (*(__O uint32_t*)0x40020440U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 2) */ + #define REG_PWM0_ETRG2 (*(__IO uint32_t*)0x4002044CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 2) */ + #define REG_PWM0_LEBR2 (*(__IO uint32_t*)0x40020450U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 2) */ + #define REG_PWM0_CMUPD3 (*(__O uint32_t*)0x40020460U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 3) */ + #define REG_PWM0_ETRG3 (*(__IO uint32_t*)0x4002046CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 3) */ + #define REG_PWM0_LEBR3 (*(__IO uint32_t*)0x40020470U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 3) */ + #define REG_PWM0_ETRG4 (*(__IO uint32_t*)0x4002048CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 4) */ + #define REG_PWM0_LEBR4 (*(__IO uint32_t*)0x40020490U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 4) */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_PWM0_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_pwm1.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_pwm1.h new file mode 100644 index 00000000..4350bf16 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_pwm1.h @@ -0,0 +1,260 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_PWM1_INSTANCE_ +#define _SAMV71_PWM1_INSTANCE_ + +/* ========== Register definition for PWM1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PWM1_CLK (0x4005C000U) /**< \brief (PWM1) PWM Clock Register */ + #define REG_PWM1_ENA (0x4005C004U) /**< \brief (PWM1) PWM Enable Register */ + #define REG_PWM1_DIS (0x4005C008U) /**< \brief (PWM1) PWM Disable Register */ + #define REG_PWM1_SR (0x4005C00CU) /**< \brief (PWM1) PWM Status Register */ + #define REG_PWM1_IER1 (0x4005C010U) /**< \brief (PWM1) PWM Interrupt Enable Register 1 */ + #define REG_PWM1_IDR1 (0x4005C014U) /**< \brief (PWM1) PWM Interrupt Disable Register 1 */ + #define REG_PWM1_IMR1 (0x4005C018U) /**< \brief (PWM1) PWM Interrupt Mask Register 1 */ + #define REG_PWM1_ISR1 (0x4005C01CU) /**< \brief (PWM1) PWM Interrupt Status Register 1 */ + #define REG_PWM1_SCM (0x4005C020U) /**< \brief (PWM1) PWM Sync Channels Mode Register */ + #define REG_PWM1_DMAR (0x4005C024U) /**< \brief (PWM1) PWM DMA Register */ + #define REG_PWM1_SCUC (0x4005C028U) /**< \brief (PWM1) PWM Sync Channels Update Control Register */ + #define REG_PWM1_SCUP (0x4005C02CU) /**< \brief (PWM1) PWM Sync Channels Update Period Register */ + #define REG_PWM1_SCUPUPD (0x4005C030U) /**< \brief (PWM1) PWM Sync Channels Update Period Update Register */ + #define REG_PWM1_IER2 (0x4005C034U) /**< \brief (PWM1) PWM Interrupt Enable Register 2 */ + #define REG_PWM1_IDR2 (0x4005C038U) /**< \brief (PWM1) PWM Interrupt Disable Register 2 */ + #define REG_PWM1_IMR2 (0x4005C03CU) /**< \brief (PWM1) PWM Interrupt Mask Register 2 */ + #define REG_PWM1_ISR2 (0x4005C040U) /**< \brief (PWM1) PWM Interrupt Status Register 2 */ + #define REG_PWM1_OOV (0x4005C044U) /**< \brief (PWM1) PWM Output Override Value Register */ + #define REG_PWM1_OS (0x4005C048U) /**< \brief (PWM1) PWM Output Selection Register */ + #define REG_PWM1_OSS (0x4005C04CU) /**< \brief (PWM1) PWM Output Selection Set Register */ + #define REG_PWM1_OSC (0x4005C050U) /**< \brief (PWM1) PWM Output Selection Clear Register */ + #define REG_PWM1_OSSUPD (0x4005C054U) /**< \brief (PWM1) PWM Output Selection Set Update Register */ + #define REG_PWM1_OSCUPD (0x4005C058U) /**< \brief (PWM1) PWM Output Selection Clear Update Register */ + #define REG_PWM1_FMR (0x4005C05CU) /**< \brief (PWM1) PWM Fault Mode Register */ + #define REG_PWM1_FSR (0x4005C060U) /**< \brief (PWM1) PWM Fault Status Register */ + #define REG_PWM1_FCR (0x4005C064U) /**< \brief (PWM1) PWM Fault Clear Register */ + #define REG_PWM1_FPV1 (0x4005C068U) /**< \brief (PWM1) PWM Fault Protection Value Register 1 */ + #define REG_PWM1_FPE (0x4005C06CU) /**< \brief (PWM1) PWM Fault Protection Enable Register */ + #define REG_PWM1_ELMR (0x4005C07CU) /**< \brief (PWM1) PWM Event Line 0 Mode Register */ + #define REG_PWM1_SSPR (0x4005C0A0U) /**< \brief (PWM1) PWM Spread Spectrum Register */ + #define REG_PWM1_SSPUP (0x4005C0A4U) /**< \brief (PWM1) PWM Spread Spectrum Update Register */ + #define REG_PWM1_SMMR (0x4005C0B0U) /**< \brief (PWM1) PWM Stepper Motor Mode Register */ + #define REG_PWM1_FPV2 (0x4005C0C0U) /**< \brief (PWM1) PWM Fault Protection Value 2 Register */ + #define REG_PWM1_WPCR (0x4005C0E4U) /**< \brief (PWM1) PWM Write Protection Control Register */ + #define REG_PWM1_WPSR (0x4005C0E8U) /**< \brief (PWM1) PWM Write Protection Status Register */ + #define REG_PWM1_CMPV0 (0x4005C130U) /**< \brief (PWM1) PWM Comparison 0 Value Register */ + #define REG_PWM1_CMPVUPD0 (0x4005C134U) /**< \brief (PWM1) PWM Comparison 0 Value Update Register */ + #define REG_PWM1_CMPM0 (0x4005C138U) /**< \brief (PWM1) PWM Comparison 0 Mode Register */ + #define REG_PWM1_CMPMUPD0 (0x4005C13CU) /**< \brief (PWM1) PWM Comparison 0 Mode Update Register */ + #define REG_PWM1_CMPV1 (0x4005C140U) /**< \brief (PWM1) PWM Comparison 1 Value Register */ + #define REG_PWM1_CMPVUPD1 (0x4005C144U) /**< \brief (PWM1) PWM Comparison 1 Value Update Register */ + #define REG_PWM1_CMPM1 (0x4005C148U) /**< \brief (PWM1) PWM Comparison 1 Mode Register */ + #define REG_PWM1_CMPMUPD1 (0x4005C14CU) /**< \brief (PWM1) PWM Comparison 1 Mode Update Register */ + #define REG_PWM1_CMPV2 (0x4005C150U) /**< \brief (PWM1) PWM Comparison 2 Value Register */ + #define REG_PWM1_CMPVUPD2 (0x4005C154U) /**< \brief (PWM1) PWM Comparison 2 Value Update Register */ + #define REG_PWM1_CMPM2 (0x4005C158U) /**< \brief (PWM1) PWM Comparison 2 Mode Register */ + #define REG_PWM1_CMPMUPD2 (0x4005C15CU) /**< \brief (PWM1) PWM Comparison 2 Mode Update Register */ + #define REG_PWM1_CMPV3 (0x4005C160U) /**< \brief (PWM1) PWM Comparison 3 Value Register */ + #define REG_PWM1_CMPVUPD3 (0x4005C164U) /**< \brief (PWM1) PWM Comparison 3 Value Update Register */ + #define REG_PWM1_CMPM3 (0x4005C168U) /**< \brief (PWM1) PWM Comparison 3 Mode Register */ + #define REG_PWM1_CMPMUPD3 (0x4005C16CU) /**< \brief (PWM1) PWM Comparison 3 Mode Update Register */ + #define REG_PWM1_CMPV4 (0x4005C170U) /**< \brief (PWM1) PWM Comparison 4 Value Register */ + #define REG_PWM1_CMPVUPD4 (0x4005C174U) /**< \brief (PWM1) PWM Comparison 4 Value Update Register */ + #define REG_PWM1_CMPM4 (0x4005C178U) /**< \brief (PWM1) PWM Comparison 4 Mode Register */ + #define REG_PWM1_CMPMUPD4 (0x4005C17CU) /**< \brief (PWM1) PWM Comparison 4 Mode Update Register */ + #define REG_PWM1_CMPV5 (0x4005C180U) /**< \brief (PWM1) PWM Comparison 5 Value Register */ + #define REG_PWM1_CMPVUPD5 (0x4005C184U) /**< \brief (PWM1) PWM Comparison 5 Value Update Register */ + #define REG_PWM1_CMPM5 (0x4005C188U) /**< \brief (PWM1) PWM Comparison 5 Mode Register */ + #define REG_PWM1_CMPMUPD5 (0x4005C18CU) /**< \brief (PWM1) PWM Comparison 5 Mode Update Register */ + #define REG_PWM1_CMPV6 (0x4005C190U) /**< \brief (PWM1) PWM Comparison 6 Value Register */ + #define REG_PWM1_CMPVUPD6 (0x4005C194U) /**< \brief (PWM1) PWM Comparison 6 Value Update Register */ + #define REG_PWM1_CMPM6 (0x4005C198U) /**< \brief (PWM1) PWM Comparison 6 Mode Register */ + #define REG_PWM1_CMPMUPD6 (0x4005C19CU) /**< \brief (PWM1) PWM Comparison 6 Mode Update Register */ + #define REG_PWM1_CMPV7 (0x4005C1A0U) /**< \brief (PWM1) PWM Comparison 7 Value Register */ + #define REG_PWM1_CMPVUPD7 (0x4005C1A4U) /**< \brief (PWM1) PWM Comparison 7 Value Update Register */ + #define REG_PWM1_CMPM7 (0x4005C1A8U) /**< \brief (PWM1) PWM Comparison 7 Mode Register */ + #define REG_PWM1_CMPMUPD7 (0x4005C1ACU) /**< \brief (PWM1) PWM Comparison 7 Mode Update Register */ + #define REG_PWM1_CMR0 (0x4005C200U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 0) */ + #define REG_PWM1_CDTY0 (0x4005C204U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 0) */ + #define REG_PWM1_CDTYUPD0 (0x4005C208U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 0) */ + #define REG_PWM1_CPRD0 (0x4005C20CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 0) */ + #define REG_PWM1_CPRDUPD0 (0x4005C210U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 0) */ + #define REG_PWM1_CCNT0 (0x4005C214U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 0) */ + #define REG_PWM1_DT0 (0x4005C218U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 0) */ + #define REG_PWM1_DTUPD0 (0x4005C21CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 0) */ + #define REG_PWM1_CMR1 (0x4005C220U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 1) */ + #define REG_PWM1_CDTY1 (0x4005C224U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 1) */ + #define REG_PWM1_CDTYUPD1 (0x4005C228U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 1) */ + #define REG_PWM1_CPRD1 (0x4005C22CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 1) */ + #define REG_PWM1_CPRDUPD1 (0x4005C230U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 1) */ + #define REG_PWM1_CCNT1 (0x4005C234U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 1) */ + #define REG_PWM1_DT1 (0x4005C238U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 1) */ + #define REG_PWM1_DTUPD1 (0x4005C23CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 1) */ + #define REG_PWM1_CMR2 (0x4005C240U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 2) */ + #define REG_PWM1_CDTY2 (0x4005C244U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 2) */ + #define REG_PWM1_CDTYUPD2 (0x4005C248U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 2) */ + #define REG_PWM1_CPRD2 (0x4005C24CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 2) */ + #define REG_PWM1_CPRDUPD2 (0x4005C250U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 2) */ + #define REG_PWM1_CCNT2 (0x4005C254U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 2) */ + #define REG_PWM1_DT2 (0x4005C258U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 2) */ + #define REG_PWM1_DTUPD2 (0x4005C25CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 2) */ + #define REG_PWM1_CMR3 (0x4005C260U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 3) */ + #define REG_PWM1_CDTY3 (0x4005C264U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 3) */ + #define REG_PWM1_CDTYUPD3 (0x4005C268U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 3) */ + #define REG_PWM1_CPRD3 (0x4005C26CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 3) */ + #define REG_PWM1_CPRDUPD3 (0x4005C270U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 3) */ + #define REG_PWM1_CCNT3 (0x4005C274U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 3) */ + #define REG_PWM1_DT3 (0x4005C278U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 3) */ + #define REG_PWM1_DTUPD3 (0x4005C27CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 3) */ + #define REG_PWM1_CMUPD0 (0x4005C400U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 0) */ + #define REG_PWM1_CMUPD1 (0x4005C420U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 1) */ + #define REG_PWM1_ETRG1 (0x4005C42CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 1) */ + #define REG_PWM1_LEBR1 (0x4005C430U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 1) */ + #define REG_PWM1_CMUPD2 (0x4005C440U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 2) */ + #define REG_PWM1_ETRG2 (0x4005C44CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 2) */ + #define REG_PWM1_LEBR2 (0x4005C450U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 2) */ + #define REG_PWM1_CMUPD3 (0x4005C460U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 3) */ + #define REG_PWM1_ETRG3 (0x4005C46CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 3) */ + #define REG_PWM1_LEBR3 (0x4005C470U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 3) */ + #define REG_PWM1_ETRG4 (0x4005C48CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 4) */ + #define REG_PWM1_LEBR4 (0x4005C490U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 4) */ +#else + #define REG_PWM1_CLK (*(__IO uint32_t*)0x4005C000U) /**< \brief (PWM1) PWM Clock Register */ + #define REG_PWM1_ENA (*(__O uint32_t*)0x4005C004U) /**< \brief (PWM1) PWM Enable Register */ + #define REG_PWM1_DIS (*(__O uint32_t*)0x4005C008U) /**< \brief (PWM1) PWM Disable Register */ + #define REG_PWM1_SR (*(__I uint32_t*)0x4005C00CU) /**< \brief (PWM1) PWM Status Register */ + #define REG_PWM1_IER1 (*(__O uint32_t*)0x4005C010U) /**< \brief (PWM1) PWM Interrupt Enable Register 1 */ + #define REG_PWM1_IDR1 (*(__O uint32_t*)0x4005C014U) /**< \brief (PWM1) PWM Interrupt Disable Register 1 */ + #define REG_PWM1_IMR1 (*(__I uint32_t*)0x4005C018U) /**< \brief (PWM1) PWM Interrupt Mask Register 1 */ + #define REG_PWM1_ISR1 (*(__I uint32_t*)0x4005C01CU) /**< \brief (PWM1) PWM Interrupt Status Register 1 */ + #define REG_PWM1_SCM (*(__IO uint32_t*)0x4005C020U) /**< \brief (PWM1) PWM Sync Channels Mode Register */ + #define REG_PWM1_DMAR (*(__O uint32_t*)0x4005C024U) /**< \brief (PWM1) PWM DMA Register */ + #define REG_PWM1_SCUC (*(__IO uint32_t*)0x4005C028U) /**< \brief (PWM1) PWM Sync Channels Update Control Register */ + #define REG_PWM1_SCUP (*(__IO uint32_t*)0x4005C02CU) /**< \brief (PWM1) PWM Sync Channels Update Period Register */ + #define REG_PWM1_SCUPUPD (*(__O uint32_t*)0x4005C030U) /**< \brief (PWM1) PWM Sync Channels Update Period Update Register */ + #define REG_PWM1_IER2 (*(__O uint32_t*)0x4005C034U) /**< \brief (PWM1) PWM Interrupt Enable Register 2 */ + #define REG_PWM1_IDR2 (*(__O uint32_t*)0x4005C038U) /**< \brief (PWM1) PWM Interrupt Disable Register 2 */ + #define REG_PWM1_IMR2 (*(__I uint32_t*)0x4005C03CU) /**< \brief (PWM1) PWM Interrupt Mask Register 2 */ + #define REG_PWM1_ISR2 (*(__I uint32_t*)0x4005C040U) /**< \brief (PWM1) PWM Interrupt Status Register 2 */ + #define REG_PWM1_OOV (*(__IO uint32_t*)0x4005C044U) /**< \brief (PWM1) PWM Output Override Value Register */ + #define REG_PWM1_OS (*(__IO uint32_t*)0x4005C048U) /**< \brief (PWM1) PWM Output Selection Register */ + #define REG_PWM1_OSS (*(__O uint32_t*)0x4005C04CU) /**< \brief (PWM1) PWM Output Selection Set Register */ + #define REG_PWM1_OSC (*(__O uint32_t*)0x4005C050U) /**< \brief (PWM1) PWM Output Selection Clear Register */ + #define REG_PWM1_OSSUPD (*(__O uint32_t*)0x4005C054U) /**< \brief (PWM1) PWM Output Selection Set Update Register */ + #define REG_PWM1_OSCUPD (*(__O uint32_t*)0x4005C058U) /**< \brief (PWM1) PWM Output Selection Clear Update Register */ + #define REG_PWM1_FMR (*(__IO uint32_t*)0x4005C05CU) /**< \brief (PWM1) PWM Fault Mode Register */ + #define REG_PWM1_FSR (*(__I uint32_t*)0x4005C060U) /**< \brief (PWM1) PWM Fault Status Register */ + #define REG_PWM1_FCR (*(__O uint32_t*)0x4005C064U) /**< \brief (PWM1) PWM Fault Clear Register */ + #define REG_PWM1_FPV1 (*(__IO uint32_t*)0x4005C068U) /**< \brief (PWM1) PWM Fault Protection Value Register 1 */ + #define REG_PWM1_FPE (*(__IO uint32_t*)0x4005C06CU) /**< \brief (PWM1) PWM Fault Protection Enable Register */ + #define REG_PWM1_ELMR (*(__IO uint32_t*)0x4005C07CU) /**< \brief (PWM1) PWM Event Line 0 Mode Register */ + #define REG_PWM1_SSPR (*(__IO uint32_t*)0x4005C0A0U) /**< \brief (PWM1) PWM Spread Spectrum Register */ + #define REG_PWM1_SSPUP (*(__O uint32_t*)0x4005C0A4U) /**< \brief (PWM1) PWM Spread Spectrum Update Register */ + #define REG_PWM1_SMMR (*(__IO uint32_t*)0x4005C0B0U) /**< \brief (PWM1) PWM Stepper Motor Mode Register */ + #define REG_PWM1_FPV2 (*(__IO uint32_t*)0x4005C0C0U) /**< \brief (PWM1) PWM Fault Protection Value 2 Register */ + #define REG_PWM1_WPCR (*(__O uint32_t*)0x4005C0E4U) /**< \brief (PWM1) PWM Write Protection Control Register */ + #define REG_PWM1_WPSR (*(__I uint32_t*)0x4005C0E8U) /**< \brief (PWM1) PWM Write Protection Status Register */ + #define REG_PWM1_CMPV0 (*(__IO uint32_t*)0x4005C130U) /**< \brief (PWM1) PWM Comparison 0 Value Register */ + #define REG_PWM1_CMPVUPD0 (*(__O uint32_t*)0x4005C134U) /**< \brief (PWM1) PWM Comparison 0 Value Update Register */ + #define REG_PWM1_CMPM0 (*(__IO uint32_t*)0x4005C138U) /**< \brief (PWM1) PWM Comparison 0 Mode Register */ + #define REG_PWM1_CMPMUPD0 (*(__O uint32_t*)0x4005C13CU) /**< \brief (PWM1) PWM Comparison 0 Mode Update Register */ + #define REG_PWM1_CMPV1 (*(__IO uint32_t*)0x4005C140U) /**< \brief (PWM1) PWM Comparison 1 Value Register */ + #define REG_PWM1_CMPVUPD1 (*(__O uint32_t*)0x4005C144U) /**< \brief (PWM1) PWM Comparison 1 Value Update Register */ + #define REG_PWM1_CMPM1 (*(__IO uint32_t*)0x4005C148U) /**< \brief (PWM1) PWM Comparison 1 Mode Register */ + #define REG_PWM1_CMPMUPD1 (*(__O uint32_t*)0x4005C14CU) /**< \brief (PWM1) PWM Comparison 1 Mode Update Register */ + #define REG_PWM1_CMPV2 (*(__IO uint32_t*)0x4005C150U) /**< \brief (PWM1) PWM Comparison 2 Value Register */ + #define REG_PWM1_CMPVUPD2 (*(__O uint32_t*)0x4005C154U) /**< \brief (PWM1) PWM Comparison 2 Value Update Register */ + #define REG_PWM1_CMPM2 (*(__IO uint32_t*)0x4005C158U) /**< \brief (PWM1) PWM Comparison 2 Mode Register */ + #define REG_PWM1_CMPMUPD2 (*(__O uint32_t*)0x4005C15CU) /**< \brief (PWM1) PWM Comparison 2 Mode Update Register */ + #define REG_PWM1_CMPV3 (*(__IO uint32_t*)0x4005C160U) /**< \brief (PWM1) PWM Comparison 3 Value Register */ + #define REG_PWM1_CMPVUPD3 (*(__O uint32_t*)0x4005C164U) /**< \brief (PWM1) PWM Comparison 3 Value Update Register */ + #define REG_PWM1_CMPM3 (*(__IO uint32_t*)0x4005C168U) /**< \brief (PWM1) PWM Comparison 3 Mode Register */ + #define REG_PWM1_CMPMUPD3 (*(__O uint32_t*)0x4005C16CU) /**< \brief (PWM1) PWM Comparison 3 Mode Update Register */ + #define REG_PWM1_CMPV4 (*(__IO uint32_t*)0x4005C170U) /**< \brief (PWM1) PWM Comparison 4 Value Register */ + #define REG_PWM1_CMPVUPD4 (*(__O uint32_t*)0x4005C174U) /**< \brief (PWM1) PWM Comparison 4 Value Update Register */ + #define REG_PWM1_CMPM4 (*(__IO uint32_t*)0x4005C178U) /**< \brief (PWM1) PWM Comparison 4 Mode Register */ + #define REG_PWM1_CMPMUPD4 (*(__O uint32_t*)0x4005C17CU) /**< \brief (PWM1) PWM Comparison 4 Mode Update Register */ + #define REG_PWM1_CMPV5 (*(__IO uint32_t*)0x4005C180U) /**< \brief (PWM1) PWM Comparison 5 Value Register */ + #define REG_PWM1_CMPVUPD5 (*(__O uint32_t*)0x4005C184U) /**< \brief (PWM1) PWM Comparison 5 Value Update Register */ + #define REG_PWM1_CMPM5 (*(__IO uint32_t*)0x4005C188U) /**< \brief (PWM1) PWM Comparison 5 Mode Register */ + #define REG_PWM1_CMPMUPD5 (*(__O uint32_t*)0x4005C18CU) /**< \brief (PWM1) PWM Comparison 5 Mode Update Register */ + #define REG_PWM1_CMPV6 (*(__IO uint32_t*)0x4005C190U) /**< \brief (PWM1) PWM Comparison 6 Value Register */ + #define REG_PWM1_CMPVUPD6 (*(__O uint32_t*)0x4005C194U) /**< \brief (PWM1) PWM Comparison 6 Value Update Register */ + #define REG_PWM1_CMPM6 (*(__IO uint32_t*)0x4005C198U) /**< \brief (PWM1) PWM Comparison 6 Mode Register */ + #define REG_PWM1_CMPMUPD6 (*(__O uint32_t*)0x4005C19CU) /**< \brief (PWM1) PWM Comparison 6 Mode Update Register */ + #define REG_PWM1_CMPV7 (*(__IO uint32_t*)0x4005C1A0U) /**< \brief (PWM1) PWM Comparison 7 Value Register */ + #define REG_PWM1_CMPVUPD7 (*(__O uint32_t*)0x4005C1A4U) /**< \brief (PWM1) PWM Comparison 7 Value Update Register */ + #define REG_PWM1_CMPM7 (*(__IO uint32_t*)0x4005C1A8U) /**< \brief (PWM1) PWM Comparison 7 Mode Register */ + #define REG_PWM1_CMPMUPD7 (*(__O uint32_t*)0x4005C1ACU) /**< \brief (PWM1) PWM Comparison 7 Mode Update Register */ + #define REG_PWM1_CMR0 (*(__IO uint32_t*)0x4005C200U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 0) */ + #define REG_PWM1_CDTY0 (*(__IO uint32_t*)0x4005C204U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 0) */ + #define REG_PWM1_CDTYUPD0 (*(__O uint32_t*)0x4005C208U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 0) */ + #define REG_PWM1_CPRD0 (*(__IO uint32_t*)0x4005C20CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 0) */ + #define REG_PWM1_CPRDUPD0 (*(__O uint32_t*)0x4005C210U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 0) */ + #define REG_PWM1_CCNT0 (*(__I uint32_t*)0x4005C214U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 0) */ + #define REG_PWM1_DT0 (*(__IO uint32_t*)0x4005C218U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 0) */ + #define REG_PWM1_DTUPD0 (*(__O uint32_t*)0x4005C21CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 0) */ + #define REG_PWM1_CMR1 (*(__IO uint32_t*)0x4005C220U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 1) */ + #define REG_PWM1_CDTY1 (*(__IO uint32_t*)0x4005C224U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 1) */ + #define REG_PWM1_CDTYUPD1 (*(__O uint32_t*)0x4005C228U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 1) */ + #define REG_PWM1_CPRD1 (*(__IO uint32_t*)0x4005C22CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 1) */ + #define REG_PWM1_CPRDUPD1 (*(__O uint32_t*)0x4005C230U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 1) */ + #define REG_PWM1_CCNT1 (*(__I uint32_t*)0x4005C234U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 1) */ + #define REG_PWM1_DT1 (*(__IO uint32_t*)0x4005C238U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 1) */ + #define REG_PWM1_DTUPD1 (*(__O uint32_t*)0x4005C23CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 1) */ + #define REG_PWM1_CMR2 (*(__IO uint32_t*)0x4005C240U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 2) */ + #define REG_PWM1_CDTY2 (*(__IO uint32_t*)0x4005C244U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 2) */ + #define REG_PWM1_CDTYUPD2 (*(__O uint32_t*)0x4005C248U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 2) */ + #define REG_PWM1_CPRD2 (*(__IO uint32_t*)0x4005C24CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 2) */ + #define REG_PWM1_CPRDUPD2 (*(__O uint32_t*)0x4005C250U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 2) */ + #define REG_PWM1_CCNT2 (*(__I uint32_t*)0x4005C254U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 2) */ + #define REG_PWM1_DT2 (*(__IO uint32_t*)0x4005C258U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 2) */ + #define REG_PWM1_DTUPD2 (*(__O uint32_t*)0x4005C25CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 2) */ + #define REG_PWM1_CMR3 (*(__IO uint32_t*)0x4005C260U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 3) */ + #define REG_PWM1_CDTY3 (*(__IO uint32_t*)0x4005C264U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 3) */ + #define REG_PWM1_CDTYUPD3 (*(__O uint32_t*)0x4005C268U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 3) */ + #define REG_PWM1_CPRD3 (*(__IO uint32_t*)0x4005C26CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 3) */ + #define REG_PWM1_CPRDUPD3 (*(__O uint32_t*)0x4005C270U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 3) */ + #define REG_PWM1_CCNT3 (*(__I uint32_t*)0x4005C274U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 3) */ + #define REG_PWM1_DT3 (*(__IO uint32_t*)0x4005C278U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 3) */ + #define REG_PWM1_DTUPD3 (*(__O uint32_t*)0x4005C27CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 3) */ + #define REG_PWM1_CMUPD0 (*(__O uint32_t*)0x4005C400U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 0) */ + #define REG_PWM1_CMUPD1 (*(__O uint32_t*)0x4005C420U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 1) */ + #define REG_PWM1_ETRG1 (*(__IO uint32_t*)0x4005C42CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 1) */ + #define REG_PWM1_LEBR1 (*(__IO uint32_t*)0x4005C430U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 1) */ + #define REG_PWM1_CMUPD2 (*(__O uint32_t*)0x4005C440U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 2) */ + #define REG_PWM1_ETRG2 (*(__IO uint32_t*)0x4005C44CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 2) */ + #define REG_PWM1_LEBR2 (*(__IO uint32_t*)0x4005C450U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 2) */ + #define REG_PWM1_CMUPD3 (*(__O uint32_t*)0x4005C460U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 3) */ + #define REG_PWM1_ETRG3 (*(__IO uint32_t*)0x4005C46CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 3) */ + #define REG_PWM1_LEBR3 (*(__IO uint32_t*)0x4005C470U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 3) */ + #define REG_PWM1_ETRG4 (*(__IO uint32_t*)0x4005C48CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 4) */ + #define REG_PWM1_LEBR4 (*(__IO uint32_t*)0x4005C490U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 4) */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_PWM1_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_qspi.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_qspi.h new file mode 100644 index 00000000..30aae74c --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_qspi.h @@ -0,0 +1,70 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_QSPI_INSTANCE_ +#define _SAMV71_QSPI_INSTANCE_ + +/* ========== Register definition for QSPI peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_QSPI_CR (0x4007C000U) /**< \brief (QSPI) Control Register */ + #define REG_QSPI_MR (0x4007C004U) /**< \brief (QSPI) Mode Register */ + #define REG_QSPI_RDR (0x4007C008U) /**< \brief (QSPI) Receive Data Register */ + #define REG_QSPI_TDR (0x4007C00CU) /**< \brief (QSPI) Transmit Data Register */ + #define REG_QSPI_SR (0x4007C010U) /**< \brief (QSPI) Status Register */ + #define REG_QSPI_IER (0x4007C014U) /**< \brief (QSPI) Interrupt Enable Register */ + #define REG_QSPI_IDR (0x4007C018U) /**< \brief (QSPI) Interrupt Disable Register */ + #define REG_QSPI_IMR (0x4007C01CU) /**< \brief (QSPI) Interrupt Mask Register */ + #define REG_QSPI_SCR (0x4007C020U) /**< \brief (QSPI) Serial Clock Register */ + #define REG_QSPI_IAR (0x4007C030U) /**< \brief (QSPI) Instruction Address Register */ + #define REG_QSPI_ICR (0x4007C034U) /**< \brief (QSPI) Instruction Code Register */ + #define REG_QSPI_IFR (0x4007C038U) /**< \brief (QSPI) Instruction Frame Register */ + #define REG_QSPI_SMR (0x4007C040U) /**< \brief (QSPI) Scrambling Mode Register */ + #define REG_QSPI_SKR (0x4007C044U) /**< \brief (QSPI) Scrambling Key Register */ + #define REG_QSPI_WPMR (0x4007C0E4U) /**< \brief (QSPI) Write Protection Mode Register */ + #define REG_QSPI_WPSR (0x4007C0E8U) /**< \brief (QSPI) Write Protection Status Register */ +#else + #define REG_QSPI_CR (*(__O uint32_t*)0x4007C000U) /**< \brief (QSPI) Control Register */ + #define REG_QSPI_MR (*(__IO uint32_t*)0x4007C004U) /**< \brief (QSPI) Mode Register */ + #define REG_QSPI_RDR (*(__I uint32_t*)0x4007C008U) /**< \brief (QSPI) Receive Data Register */ + #define REG_QSPI_TDR (*(__O uint32_t*)0x4007C00CU) /**< \brief (QSPI) Transmit Data Register */ + #define REG_QSPI_SR (*(__I uint32_t*)0x4007C010U) /**< \brief (QSPI) Status Register */ + #define REG_QSPI_IER (*(__O uint32_t*)0x4007C014U) /**< \brief (QSPI) Interrupt Enable Register */ + #define REG_QSPI_IDR (*(__O uint32_t*)0x4007C018U) /**< \brief (QSPI) Interrupt Disable Register */ + #define REG_QSPI_IMR (*(__I uint32_t*)0x4007C01CU) /**< \brief (QSPI) Interrupt Mask Register */ + #define REG_QSPI_SCR (*(__IO uint32_t*)0x4007C020U) /**< \brief (QSPI) Serial Clock Register */ + #define REG_QSPI_IAR (*(__IO uint32_t*)0x4007C030U) /**< \brief (QSPI) Instruction Address Register */ + #define REG_QSPI_ICR (*(__IO uint32_t*)0x4007C034U) /**< \brief (QSPI) Instruction Code Register */ + #define REG_QSPI_IFR (*(__IO uint32_t*)0x4007C038U) /**< \brief (QSPI) Instruction Frame Register */ + #define REG_QSPI_SMR (*(__IO uint32_t*)0x4007C040U) /**< \brief (QSPI) Scrambling Mode Register */ + #define REG_QSPI_SKR (*(__O uint32_t*)0x4007C044U) /**< \brief (QSPI) Scrambling Key Register */ + #define REG_QSPI_WPMR (*(__IO uint32_t*)0x4007C0E4U) /**< \brief (QSPI) Write Protection Mode Register */ + #define REG_QSPI_WPSR (*(__I uint32_t*)0x4007C0E8U) /**< \brief (QSPI) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_QSPI_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_rstc.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_rstc.h new file mode 100644 index 00000000..ab13eb6c --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_rstc.h @@ -0,0 +1,44 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_RSTC_INSTANCE_ +#define _SAMV71_RSTC_INSTANCE_ + +/* ========== Register definition for RSTC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_RSTC_CR (0x400E1800U) /**< \brief (RSTC) Control Register */ + #define REG_RSTC_SR (0x400E1804U) /**< \brief (RSTC) Status Register */ + #define REG_RSTC_MR (0x400E1808U) /**< \brief (RSTC) Mode Register */ +#else + #define REG_RSTC_CR (*(__O uint32_t*)0x400E1800U) /**< \brief (RSTC) Control Register */ + #define REG_RSTC_SR (*(__I uint32_t*)0x400E1804U) /**< \brief (RSTC) Status Register */ + #define REG_RSTC_MR (*(__IO uint32_t*)0x400E1808U) /**< \brief (RSTC) Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_RSTC_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_rswdt.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_rswdt.h new file mode 100644 index 00000000..665ef010 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_rswdt.h @@ -0,0 +1,44 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_RSWDT_INSTANCE_ +#define _SAMV71_RSWDT_INSTANCE_ + +/* ========== Register definition for RSWDT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_RSWDT_CR (0x400E1900U) /**< \brief (RSWDT) Control Register */ + #define REG_RSWDT_MR (0x400E1904U) /**< \brief (RSWDT) Mode Register */ + #define REG_RSWDT_SR (0x400E1908U) /**< \brief (RSWDT) Status Register */ +#else + #define REG_RSWDT_CR (*(__O uint32_t*)0x400E1900U) /**< \brief (RSWDT) Control Register */ + #define REG_RSWDT_MR (*(__IO uint32_t*)0x400E1904U) /**< \brief (RSWDT) Mode Register */ + #define REG_RSWDT_SR (*(__I uint32_t*)0x400E1908U) /**< \brief (RSWDT) Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_RSWDT_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_rtc.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_rtc.h new file mode 100644 index 00000000..2d865f60 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_rtc.h @@ -0,0 +1,62 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_RTC_INSTANCE_ +#define _SAMV71_RTC_INSTANCE_ + +/* ========== Register definition for RTC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_RTC_CR (0x400E1860U) /**< \brief (RTC) Control Register */ + #define REG_RTC_MR (0x400E1864U) /**< \brief (RTC) Mode Register */ + #define REG_RTC_TIMR (0x400E1868U) /**< \brief (RTC) Time Register */ + #define REG_RTC_CALR (0x400E186CU) /**< \brief (RTC) Calendar Register */ + #define REG_RTC_TIMALR (0x400E1870U) /**< \brief (RTC) Time Alarm Register */ + #define REG_RTC_CALALR (0x400E1874U) /**< \brief (RTC) Calendar Alarm Register */ + #define REG_RTC_SR (0x400E1878U) /**< \brief (RTC) Status Register */ + #define REG_RTC_SCCR (0x400E187CU) /**< \brief (RTC) Status Clear Command Register */ + #define REG_RTC_IER (0x400E1880U) /**< \brief (RTC) Interrupt Enable Register */ + #define REG_RTC_IDR (0x400E1884U) /**< \brief (RTC) Interrupt Disable Register */ + #define REG_RTC_IMR (0x400E1888U) /**< \brief (RTC) Interrupt Mask Register */ + #define REG_RTC_VER (0x400E188CU) /**< \brief (RTC) Valid Entry Register */ +#else + #define REG_RTC_CR (*(__IO uint32_t*)0x400E1860U) /**< \brief (RTC) Control Register */ + #define REG_RTC_MR (*(__IO uint32_t*)0x400E1864U) /**< \brief (RTC) Mode Register */ + #define REG_RTC_TIMR (*(__IO uint32_t*)0x400E1868U) /**< \brief (RTC) Time Register */ + #define REG_RTC_CALR (*(__IO uint32_t*)0x400E186CU) /**< \brief (RTC) Calendar Register */ + #define REG_RTC_TIMALR (*(__IO uint32_t*)0x400E1870U) /**< \brief (RTC) Time Alarm Register */ + #define REG_RTC_CALALR (*(__IO uint32_t*)0x400E1874U) /**< \brief (RTC) Calendar Alarm Register */ + #define REG_RTC_SR (*(__I uint32_t*)0x400E1878U) /**< \brief (RTC) Status Register */ + #define REG_RTC_SCCR (*(__O uint32_t*)0x400E187CU) /**< \brief (RTC) Status Clear Command Register */ + #define REG_RTC_IER (*(__O uint32_t*)0x400E1880U) /**< \brief (RTC) Interrupt Enable Register */ + #define REG_RTC_IDR (*(__O uint32_t*)0x400E1884U) /**< \brief (RTC) Interrupt Disable Register */ + #define REG_RTC_IMR (*(__I uint32_t*)0x400E1888U) /**< \brief (RTC) Interrupt Mask Register */ + #define REG_RTC_VER (*(__I uint32_t*)0x400E188CU) /**< \brief (RTC) Valid Entry Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_RTC_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_rtt.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_rtt.h new file mode 100644 index 00000000..0c377a9a --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_rtt.h @@ -0,0 +1,46 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_RTT_INSTANCE_ +#define _SAMV71_RTT_INSTANCE_ + +/* ========== Register definition for RTT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_RTT_MR (0x400E1830U) /**< \brief (RTT) Mode Register */ + #define REG_RTT_AR (0x400E1834U) /**< \brief (RTT) Alarm Register */ + #define REG_RTT_VR (0x400E1838U) /**< \brief (RTT) Value Register */ + #define REG_RTT_SR (0x400E183CU) /**< \brief (RTT) Status Register */ +#else + #define REG_RTT_MR (*(__IO uint32_t*)0x400E1830U) /**< \brief (RTT) Mode Register */ + #define REG_RTT_AR (*(__IO uint32_t*)0x400E1834U) /**< \brief (RTT) Alarm Register */ + #define REG_RTT_VR (*(__I uint32_t*)0x400E1838U) /**< \brief (RTT) Value Register */ + #define REG_RTT_SR (*(__I uint32_t*)0x400E183CU) /**< \brief (RTT) Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_RTT_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_sdramc.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_sdramc.h new file mode 100644 index 00000000..c6c603ef --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_sdramc.h @@ -0,0 +1,64 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_SDRAMC_INSTANCE_ +#define _SAMV71_SDRAMC_INSTANCE_ + +/* ========== Register definition for SDRAMC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_SDRAMC_MR (0x40084000U) /**< \brief (SDRAMC) SDRAMC Mode Register */ + #define REG_SDRAMC_TR (0x40084004U) /**< \brief (SDRAMC) SDRAMC Refresh Timer Register */ + #define REG_SDRAMC_CR (0x40084008U) /**< \brief (SDRAMC) SDRAMC Configuration Register */ + #define REG_SDRAMC_LPR (0x40084010U) /**< \brief (SDRAMC) SDRAMC Low Power Register */ + #define REG_SDRAMC_IER (0x40084014U) /**< \brief (SDRAMC) SDRAMC Interrupt Enable Register */ + #define REG_SDRAMC_IDR (0x40084018U) /**< \brief (SDRAMC) SDRAMC Interrupt Disable Register */ + #define REG_SDRAMC_IMR (0x4008401CU) /**< \brief (SDRAMC) SDRAMC Interrupt Mask Register */ + #define REG_SDRAMC_ISR (0x40084020U) /**< \brief (SDRAMC) SDRAMC Interrupt Status Register */ + #define REG_SDRAMC_MDR (0x40084024U) /**< \brief (SDRAMC) SDRAMC Memory Device Register */ + #define REG_SDRAMC_CFR1 (0x40084028U) /**< \brief (SDRAMC) SDRAMC Configuration Register 1 */ + #define REG_SDRAMC_OCMS (0x4008402CU) /**< \brief (SDRAMC) SDRAMC OCMS Register */ + #define REG_SDRAMC_OCMS_KEY1 (0x40084030U) /**< \brief (SDRAMC) SDRAMC OCMS KEY1 Register */ + #define REG_SDRAMC_OCMS_KEY2 (0x40084034U) /**< \brief (SDRAMC) SDRAMC OCMS KEY2 Register */ +#else + #define REG_SDRAMC_MR (*(__IO uint32_t*)0x40084000U) /**< \brief (SDRAMC) SDRAMC Mode Register */ + #define REG_SDRAMC_TR (*(__IO uint32_t*)0x40084004U) /**< \brief (SDRAMC) SDRAMC Refresh Timer Register */ + #define REG_SDRAMC_CR (*(__IO uint32_t*)0x40084008U) /**< \brief (SDRAMC) SDRAMC Configuration Register */ + #define REG_SDRAMC_LPR (*(__IO uint32_t*)0x40084010U) /**< \brief (SDRAMC) SDRAMC Low Power Register */ + #define REG_SDRAMC_IER (*(__O uint32_t*)0x40084014U) /**< \brief (SDRAMC) SDRAMC Interrupt Enable Register */ + #define REG_SDRAMC_IDR (*(__O uint32_t*)0x40084018U) /**< \brief (SDRAMC) SDRAMC Interrupt Disable Register */ + #define REG_SDRAMC_IMR (*(__I uint32_t*)0x4008401CU) /**< \brief (SDRAMC) SDRAMC Interrupt Mask Register */ + #define REG_SDRAMC_ISR (*(__I uint32_t*)0x40084020U) /**< \brief (SDRAMC) SDRAMC Interrupt Status Register */ + #define REG_SDRAMC_MDR (*(__IO uint32_t*)0x40084024U) /**< \brief (SDRAMC) SDRAMC Memory Device Register */ + #define REG_SDRAMC_CFR1 (*(__IO uint32_t*)0x40084028U) /**< \brief (SDRAMC) SDRAMC Configuration Register 1 */ + #define REG_SDRAMC_OCMS (*(__IO uint32_t*)0x4008402CU) /**< \brief (SDRAMC) SDRAMC OCMS Register */ + #define REG_SDRAMC_OCMS_KEY1 (*(__O uint32_t*)0x40084030U) /**< \brief (SDRAMC) SDRAMC OCMS KEY1 Register */ + #define REG_SDRAMC_OCMS_KEY2 (*(__O uint32_t*)0x40084034U) /**< \brief (SDRAMC) SDRAMC OCMS KEY2 Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_SDRAMC_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_smc.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_smc.h new file mode 100644 index 00000000..cd0b6213 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_smc.h @@ -0,0 +1,80 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_SMC_INSTANCE_ +#define _SAMV71_SMC_INSTANCE_ + +/* ========== Register definition for SMC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_SMC_SETUP0 (0x40080000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */ + #define REG_SMC_PULSE0 (0x40080004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */ + #define REG_SMC_CYCLE0 (0x40080008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */ + #define REG_SMC_MODE0 (0x4008000CU) /**< \brief (SMC) SMC MODE Register (CS_number = 0) */ + #define REG_SMC_SETUP1 (0x40080010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */ + #define REG_SMC_PULSE1 (0x40080014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */ + #define REG_SMC_CYCLE1 (0x40080018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */ + #define REG_SMC_MODE1 (0x4008001CU) /**< \brief (SMC) SMC MODE Register (CS_number = 1) */ + #define REG_SMC_SETUP2 (0x40080020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */ + #define REG_SMC_PULSE2 (0x40080024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */ + #define REG_SMC_CYCLE2 (0x40080028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */ + #define REG_SMC_MODE2 (0x4008002CU) /**< \brief (SMC) SMC MODE Register (CS_number = 2) */ + #define REG_SMC_SETUP3 (0x40080030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */ + #define REG_SMC_PULSE3 (0x40080034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */ + #define REG_SMC_CYCLE3 (0x40080038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */ + #define REG_SMC_MODE3 (0x4008003CU) /**< \brief (SMC) SMC MODE Register (CS_number = 3) */ + #define REG_SMC_OCMS (0x40080080U) /**< \brief (SMC) SMC OCMS MODE Register */ + #define REG_SMC_KEY1 (0x40080084U) /**< \brief (SMC) SMC OCMS KEY1 Register */ + #define REG_SMC_KEY2 (0x40080088U) /**< \brief (SMC) SMC OCMS KEY2 Register */ + #define REG_SMC_WPMR (0x400800E4U) /**< \brief (SMC) SMC Write Protection Mode Register */ + #define REG_SMC_WPSR (0x400800E8U) /**< \brief (SMC) SMC Write Protection Status Register */ +#else + #define REG_SMC_SETUP0 (*(__IO uint32_t*)0x40080000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */ + #define REG_SMC_PULSE0 (*(__IO uint32_t*)0x40080004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */ + #define REG_SMC_CYCLE0 (*(__IO uint32_t*)0x40080008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */ + #define REG_SMC_MODE0 (*(__IO uint32_t*)0x4008000CU) /**< \brief (SMC) SMC MODE Register (CS_number = 0) */ + #define REG_SMC_SETUP1 (*(__IO uint32_t*)0x40080010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */ + #define REG_SMC_PULSE1 (*(__IO uint32_t*)0x40080014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */ + #define REG_SMC_CYCLE1 (*(__IO uint32_t*)0x40080018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */ + #define REG_SMC_MODE1 (*(__IO uint32_t*)0x4008001CU) /**< \brief (SMC) SMC MODE Register (CS_number = 1) */ + #define REG_SMC_SETUP2 (*(__IO uint32_t*)0x40080020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */ + #define REG_SMC_PULSE2 (*(__IO uint32_t*)0x40080024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */ + #define REG_SMC_CYCLE2 (*(__IO uint32_t*)0x40080028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */ + #define REG_SMC_MODE2 (*(__IO uint32_t*)0x4008002CU) /**< \brief (SMC) SMC MODE Register (CS_number = 2) */ + #define REG_SMC_SETUP3 (*(__IO uint32_t*)0x40080030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */ + #define REG_SMC_PULSE3 (*(__IO uint32_t*)0x40080034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */ + #define REG_SMC_CYCLE3 (*(__IO uint32_t*)0x40080038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */ + #define REG_SMC_MODE3 (*(__IO uint32_t*)0x4008003CU) /**< \brief (SMC) SMC MODE Register (CS_number = 3) */ + #define REG_SMC_OCMS (*(__IO uint32_t*)0x40080080U) /**< \brief (SMC) SMC OCMS MODE Register */ + #define REG_SMC_KEY1 (*(__O uint32_t*)0x40080084U) /**< \brief (SMC) SMC OCMS KEY1 Register */ + #define REG_SMC_KEY2 (*(__O uint32_t*)0x40080088U) /**< \brief (SMC) SMC OCMS KEY2 Register */ + #define REG_SMC_WPMR (*(__IO uint32_t*)0x400800E4U) /**< \brief (SMC) SMC Write Protection Mode Register */ + #define REG_SMC_WPSR (*(__I uint32_t*)0x400800E8U) /**< \brief (SMC) SMC Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_SMC_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_spi0.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_spi0.h new file mode 100644 index 00000000..8d7bc3a0 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_spi0.h @@ -0,0 +1,60 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_SPI0_INSTANCE_ +#define _SAMV71_SPI0_INSTANCE_ + +/* ========== Register definition for SPI0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_SPI0_CR (0x40008000U) /**< \brief (SPI0) Control Register */ + #define REG_SPI0_MR (0x40008004U) /**< \brief (SPI0) Mode Register */ + #define REG_SPI0_RDR (0x40008008U) /**< \brief (SPI0) Receive Data Register */ + #define REG_SPI0_TDR (0x4000800CU) /**< \brief (SPI0) Transmit Data Register */ + #define REG_SPI0_SR (0x40008010U) /**< \brief (SPI0) Status Register */ + #define REG_SPI0_IER (0x40008014U) /**< \brief (SPI0) Interrupt Enable Register */ + #define REG_SPI0_IDR (0x40008018U) /**< \brief (SPI0) Interrupt Disable Register */ + #define REG_SPI0_IMR (0x4000801CU) /**< \brief (SPI0) Interrupt Mask Register */ + #define REG_SPI0_CSR (0x40008030U) /**< \brief (SPI0) Chip Select Register */ + #define REG_SPI0_WPMR (0x400080E4U) /**< \brief (SPI0) Write Protection Mode Register */ + #define REG_SPI0_WPSR (0x400080E8U) /**< \brief (SPI0) Write Protection Status Register */ +#else + #define REG_SPI0_CR (*(__O uint32_t*)0x40008000U) /**< \brief (SPI0) Control Register */ + #define REG_SPI0_MR (*(__IO uint32_t*)0x40008004U) /**< \brief (SPI0) Mode Register */ + #define REG_SPI0_RDR (*(__I uint32_t*)0x40008008U) /**< \brief (SPI0) Receive Data Register */ + #define REG_SPI0_TDR (*(__O uint32_t*)0x4000800CU) /**< \brief (SPI0) Transmit Data Register */ + #define REG_SPI0_SR (*(__I uint32_t*)0x40008010U) /**< \brief (SPI0) Status Register */ + #define REG_SPI0_IER (*(__O uint32_t*)0x40008014U) /**< \brief (SPI0) Interrupt Enable Register */ + #define REG_SPI0_IDR (*(__O uint32_t*)0x40008018U) /**< \brief (SPI0) Interrupt Disable Register */ + #define REG_SPI0_IMR (*(__I uint32_t*)0x4000801CU) /**< \brief (SPI0) Interrupt Mask Register */ + #define REG_SPI0_CSR (*(__IO uint32_t*)0x40008030U) /**< \brief (SPI0) Chip Select Register */ + #define REG_SPI0_WPMR (*(__IO uint32_t*)0x400080E4U) /**< \brief (SPI0) Write Protection Mode Register */ + #define REG_SPI0_WPSR (*(__I uint32_t*)0x400080E8U) /**< \brief (SPI0) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_SPI0_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_spi1.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_spi1.h new file mode 100644 index 00000000..2b8443fb --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_spi1.h @@ -0,0 +1,60 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_SPI1_INSTANCE_ +#define _SAMV71_SPI1_INSTANCE_ + +/* ========== Register definition for SPI1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_SPI1_CR (0x40058000U) /**< \brief (SPI1) Control Register */ + #define REG_SPI1_MR (0x40058004U) /**< \brief (SPI1) Mode Register */ + #define REG_SPI1_RDR (0x40058008U) /**< \brief (SPI1) Receive Data Register */ + #define REG_SPI1_TDR (0x4005800CU) /**< \brief (SPI1) Transmit Data Register */ + #define REG_SPI1_SR (0x40058010U) /**< \brief (SPI1) Status Register */ + #define REG_SPI1_IER (0x40058014U) /**< \brief (SPI1) Interrupt Enable Register */ + #define REG_SPI1_IDR (0x40058018U) /**< \brief (SPI1) Interrupt Disable Register */ + #define REG_SPI1_IMR (0x4005801CU) /**< \brief (SPI1) Interrupt Mask Register */ + #define REG_SPI1_CSR (0x40058030U) /**< \brief (SPI1) Chip Select Register */ + #define REG_SPI1_WPMR (0x400580E4U) /**< \brief (SPI1) Write Protection Mode Register */ + #define REG_SPI1_WPSR (0x400580E8U) /**< \brief (SPI1) Write Protection Status Register */ +#else + #define REG_SPI1_CR (*(__O uint32_t*)0x40058000U) /**< \brief (SPI1) Control Register */ + #define REG_SPI1_MR (*(__IO uint32_t*)0x40058004U) /**< \brief (SPI1) Mode Register */ + #define REG_SPI1_RDR (*(__I uint32_t*)0x40058008U) /**< \brief (SPI1) Receive Data Register */ + #define REG_SPI1_TDR (*(__O uint32_t*)0x4005800CU) /**< \brief (SPI1) Transmit Data Register */ + #define REG_SPI1_SR (*(__I uint32_t*)0x40058010U) /**< \brief (SPI1) Status Register */ + #define REG_SPI1_IER (*(__O uint32_t*)0x40058014U) /**< \brief (SPI1) Interrupt Enable Register */ + #define REG_SPI1_IDR (*(__O uint32_t*)0x40058018U) /**< \brief (SPI1) Interrupt Disable Register */ + #define REG_SPI1_IMR (*(__I uint32_t*)0x4005801CU) /**< \brief (SPI1) Interrupt Mask Register */ + #define REG_SPI1_CSR (*(__IO uint32_t*)0x40058030U) /**< \brief (SPI1) Chip Select Register */ + #define REG_SPI1_WPMR (*(__IO uint32_t*)0x400580E4U) /**< \brief (SPI1) Write Protection Mode Register */ + #define REG_SPI1_WPSR (*(__I uint32_t*)0x400580E8U) /**< \brief (SPI1) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_SPI1_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_ssc.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_ssc.h new file mode 100644 index 00000000..5522d2f8 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_ssc.h @@ -0,0 +1,74 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_SSC_INSTANCE_ +#define _SAMV71_SSC_INSTANCE_ + +/* ========== Register definition for SSC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_SSC_CR (0x40004000U) /**< \brief (SSC) Control Register */ + #define REG_SSC_CMR (0x40004004U) /**< \brief (SSC) Clock Mode Register */ + #define REG_SSC_RCMR (0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */ + #define REG_SSC_RFMR (0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */ + #define REG_SSC_TCMR (0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */ + #define REG_SSC_TFMR (0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */ + #define REG_SSC_RHR (0x40004020U) /**< \brief (SSC) Receive Holding Register */ + #define REG_SSC_THR (0x40004024U) /**< \brief (SSC) Transmit Holding Register */ + #define REG_SSC_RSHR (0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */ + #define REG_SSC_TSHR (0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */ + #define REG_SSC_RC0R (0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */ + #define REG_SSC_RC1R (0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */ + #define REG_SSC_SR (0x40004040U) /**< \brief (SSC) Status Register */ + #define REG_SSC_IER (0x40004044U) /**< \brief (SSC) Interrupt Enable Register */ + #define REG_SSC_IDR (0x40004048U) /**< \brief (SSC) Interrupt Disable Register */ + #define REG_SSC_IMR (0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */ + #define REG_SSC_WPMR (0x400040E4U) /**< \brief (SSC) Write Protection Mode Register */ + #define REG_SSC_WPSR (0x400040E8U) /**< \brief (SSC) Write Protection Status Register */ +#else + #define REG_SSC_CR (*(__O uint32_t*)0x40004000U) /**< \brief (SSC) Control Register */ + #define REG_SSC_CMR (*(__IO uint32_t*)0x40004004U) /**< \brief (SSC) Clock Mode Register */ + #define REG_SSC_RCMR (*(__IO uint32_t*)0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */ + #define REG_SSC_RFMR (*(__IO uint32_t*)0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */ + #define REG_SSC_TCMR (*(__IO uint32_t*)0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */ + #define REG_SSC_TFMR (*(__IO uint32_t*)0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */ + #define REG_SSC_RHR (*(__I uint32_t*)0x40004020U) /**< \brief (SSC) Receive Holding Register */ + #define REG_SSC_THR (*(__O uint32_t*)0x40004024U) /**< \brief (SSC) Transmit Holding Register */ + #define REG_SSC_RSHR (*(__I uint32_t*)0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */ + #define REG_SSC_TSHR (*(__IO uint32_t*)0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */ + #define REG_SSC_RC0R (*(__IO uint32_t*)0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */ + #define REG_SSC_RC1R (*(__IO uint32_t*)0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */ + #define REG_SSC_SR (*(__I uint32_t*)0x40004040U) /**< \brief (SSC) Status Register */ + #define REG_SSC_IER (*(__O uint32_t*)0x40004044U) /**< \brief (SSC) Interrupt Enable Register */ + #define REG_SSC_IDR (*(__O uint32_t*)0x40004048U) /**< \brief (SSC) Interrupt Disable Register */ + #define REG_SSC_IMR (*(__I uint32_t*)0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */ + #define REG_SSC_WPMR (*(__IO uint32_t*)0x400040E4U) /**< \brief (SSC) Write Protection Mode Register */ + #define REG_SSC_WPSR (*(__I uint32_t*)0x400040E8U) /**< \brief (SSC) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_SSC_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_supc.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_supc.h new file mode 100644 index 00000000..88c0f49d --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_supc.h @@ -0,0 +1,50 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_SUPC_INSTANCE_ +#define _SAMV71_SUPC_INSTANCE_ + +/* ========== Register definition for SUPC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_SUPC_CR (0x400E1810U) /**< \brief (SUPC) Supply Controller Control Register */ + #define REG_SUPC_SMMR (0x400E1814U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */ + #define REG_SUPC_MR (0x400E1818U) /**< \brief (SUPC) Supply Controller Mode Register */ + #define REG_SUPC_WUMR (0x400E181CU) /**< \brief (SUPC) Supply Controller Wake-up Mode Register */ + #define REG_SUPC_WUIR (0x400E1820U) /**< \brief (SUPC) Supply Controller Wake-up Inputs Register */ + #define REG_SUPC_SR (0x400E1824U) /**< \brief (SUPC) Supply Controller Status Register */ +#else + #define REG_SUPC_CR (*(__O uint32_t*)0x400E1810U) /**< \brief (SUPC) Supply Controller Control Register */ + #define REG_SUPC_SMMR (*(__IO uint32_t*)0x400E1814U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */ + #define REG_SUPC_MR (*(__IO uint32_t*)0x400E1818U) /**< \brief (SUPC) Supply Controller Mode Register */ + #define REG_SUPC_WUMR (*(__IO uint32_t*)0x400E181CU) /**< \brief (SUPC) Supply Controller Wake-up Mode Register */ + #define REG_SUPC_WUIR (*(__IO uint32_t*)0x400E1820U) /**< \brief (SUPC) Supply Controller Wake-up Inputs Register */ + #define REG_SUPC_SR (*(__I uint32_t*)0x400E1824U) /**< \brief (SUPC) Supply Controller Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_SUPC_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_tc0.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_tc0.h new file mode 100644 index 00000000..23cb2b94 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_tc0.h @@ -0,0 +1,132 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_TC0_INSTANCE_ +#define _SAMV71_TC0_INSTANCE_ + +/* ========== Register definition for TC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TC0_CCR0 (0x4000C000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ + #define REG_TC0_CMR0 (0x4000C004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ + #define REG_TC0_SMMR0 (0x4000C008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC0_RAB0 (0x4000C00CU) /**< \brief (TC0) Register AB (channel = 0) */ + #define REG_TC0_CV0 (0x4000C010U) /**< \brief (TC0) Counter Value (channel = 0) */ + #define REG_TC0_RA0 (0x4000C014U) /**< \brief (TC0) Register A (channel = 0) */ + #define REG_TC0_RB0 (0x4000C018U) /**< \brief (TC0) Register B (channel = 0) */ + #define REG_TC0_RC0 (0x4000C01CU) /**< \brief (TC0) Register C (channel = 0) */ + #define REG_TC0_SR0 (0x4000C020U) /**< \brief (TC0) Status Register (channel = 0) */ + #define REG_TC0_IER0 (0x4000C024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ + #define REG_TC0_IDR0 (0x4000C028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ + #define REG_TC0_IMR0 (0x4000C02CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ + #define REG_TC0_EMR0 (0x4000C030U) /**< \brief (TC0) Extended Mode Register (channel = 0) */ + #define REG_TC0_CCR1 (0x4000C040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ + #define REG_TC0_CMR1 (0x4000C044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ + #define REG_TC0_SMMR1 (0x4000C048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC0_RAB1 (0x4000C04CU) /**< \brief (TC0) Register AB (channel = 1) */ + #define REG_TC0_CV1 (0x4000C050U) /**< \brief (TC0) Counter Value (channel = 1) */ + #define REG_TC0_RA1 (0x4000C054U) /**< \brief (TC0) Register A (channel = 1) */ + #define REG_TC0_RB1 (0x4000C058U) /**< \brief (TC0) Register B (channel = 1) */ + #define REG_TC0_RC1 (0x4000C05CU) /**< \brief (TC0) Register C (channel = 1) */ + #define REG_TC0_SR1 (0x4000C060U) /**< \brief (TC0) Status Register (channel = 1) */ + #define REG_TC0_IER1 (0x4000C064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ + #define REG_TC0_IDR1 (0x4000C068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ + #define REG_TC0_IMR1 (0x4000C06CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ + #define REG_TC0_EMR1 (0x4000C070U) /**< \brief (TC0) Extended Mode Register (channel = 1) */ + #define REG_TC0_CCR2 (0x4000C080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ + #define REG_TC0_CMR2 (0x4000C084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ + #define REG_TC0_SMMR2 (0x4000C088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC0_RAB2 (0x4000C08CU) /**< \brief (TC0) Register AB (channel = 2) */ + #define REG_TC0_CV2 (0x4000C090U) /**< \brief (TC0) Counter Value (channel = 2) */ + #define REG_TC0_RA2 (0x4000C094U) /**< \brief (TC0) Register A (channel = 2) */ + #define REG_TC0_RB2 (0x4000C098U) /**< \brief (TC0) Register B (channel = 2) */ + #define REG_TC0_RC2 (0x4000C09CU) /**< \brief (TC0) Register C (channel = 2) */ + #define REG_TC0_SR2 (0x4000C0A0U) /**< \brief (TC0) Status Register (channel = 2) */ + #define REG_TC0_IER2 (0x4000C0A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ + #define REG_TC0_IDR2 (0x4000C0A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ + #define REG_TC0_IMR2 (0x4000C0ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ + #define REG_TC0_EMR2 (0x4000C0B0U) /**< \brief (TC0) Extended Mode Register (channel = 2) */ + #define REG_TC0_BCR (0x4000C0C0U) /**< \brief (TC0) Block Control Register */ + #define REG_TC0_BMR (0x4000C0C4U) /**< \brief (TC0) Block Mode Register */ + #define REG_TC0_QIER (0x4000C0C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */ + #define REG_TC0_QIDR (0x4000C0CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */ + #define REG_TC0_QIMR (0x4000C0D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */ + #define REG_TC0_QISR (0x4000C0D4U) /**< \brief (TC0) QDEC Interrupt Status Register */ + #define REG_TC0_FMR (0x4000C0D8U) /**< \brief (TC0) Fault Mode Register */ + #define REG_TC0_WPMR (0x4000C0E4U) /**< \brief (TC0) Write Protection Mode Register */ +#else + #define REG_TC0_CCR0 (*(__O uint32_t*)0x4000C000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ + #define REG_TC0_CMR0 (*(__IO uint32_t*)0x4000C004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ + #define REG_TC0_SMMR0 (*(__IO uint32_t*)0x4000C008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC0_RAB0 (*(__I uint32_t*)0x4000C00CU) /**< \brief (TC0) Register AB (channel = 0) */ + #define REG_TC0_CV0 (*(__I uint32_t*)0x4000C010U) /**< \brief (TC0) Counter Value (channel = 0) */ + #define REG_TC0_RA0 (*(__IO uint32_t*)0x4000C014U) /**< \brief (TC0) Register A (channel = 0) */ + #define REG_TC0_RB0 (*(__IO uint32_t*)0x4000C018U) /**< \brief (TC0) Register B (channel = 0) */ + #define REG_TC0_RC0 (*(__IO uint32_t*)0x4000C01CU) /**< \brief (TC0) Register C (channel = 0) */ + #define REG_TC0_SR0 (*(__I uint32_t*)0x4000C020U) /**< \brief (TC0) Status Register (channel = 0) */ + #define REG_TC0_IER0 (*(__O uint32_t*)0x4000C024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ + #define REG_TC0_IDR0 (*(__O uint32_t*)0x4000C028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ + #define REG_TC0_IMR0 (*(__I uint32_t*)0x4000C02CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ + #define REG_TC0_EMR0 (*(__IO uint32_t*)0x4000C030U) /**< \brief (TC0) Extended Mode Register (channel = 0) */ + #define REG_TC0_CCR1 (*(__O uint32_t*)0x4000C040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ + #define REG_TC0_CMR1 (*(__IO uint32_t*)0x4000C044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ + #define REG_TC0_SMMR1 (*(__IO uint32_t*)0x4000C048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC0_RAB1 (*(__I uint32_t*)0x4000C04CU) /**< \brief (TC0) Register AB (channel = 1) */ + #define REG_TC0_CV1 (*(__I uint32_t*)0x4000C050U) /**< \brief (TC0) Counter Value (channel = 1) */ + #define REG_TC0_RA1 (*(__IO uint32_t*)0x4000C054U) /**< \brief (TC0) Register A (channel = 1) */ + #define REG_TC0_RB1 (*(__IO uint32_t*)0x4000C058U) /**< \brief (TC0) Register B (channel = 1) */ + #define REG_TC0_RC1 (*(__IO uint32_t*)0x4000C05CU) /**< \brief (TC0) Register C (channel = 1) */ + #define REG_TC0_SR1 (*(__I uint32_t*)0x4000C060U) /**< \brief (TC0) Status Register (channel = 1) */ + #define REG_TC0_IER1 (*(__O uint32_t*)0x4000C064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ + #define REG_TC0_IDR1 (*(__O uint32_t*)0x4000C068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ + #define REG_TC0_IMR1 (*(__I uint32_t*)0x4000C06CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ + #define REG_TC0_EMR1 (*(__IO uint32_t*)0x4000C070U) /**< \brief (TC0) Extended Mode Register (channel = 1) */ + #define REG_TC0_CCR2 (*(__O uint32_t*)0x4000C080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ + #define REG_TC0_CMR2 (*(__IO uint32_t*)0x4000C084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ + #define REG_TC0_SMMR2 (*(__IO uint32_t*)0x4000C088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC0_RAB2 (*(__I uint32_t*)0x4000C08CU) /**< \brief (TC0) Register AB (channel = 2) */ + #define REG_TC0_CV2 (*(__I uint32_t*)0x4000C090U) /**< \brief (TC0) Counter Value (channel = 2) */ + #define REG_TC0_RA2 (*(__IO uint32_t*)0x4000C094U) /**< \brief (TC0) Register A (channel = 2) */ + #define REG_TC0_RB2 (*(__IO uint32_t*)0x4000C098U) /**< \brief (TC0) Register B (channel = 2) */ + #define REG_TC0_RC2 (*(__IO uint32_t*)0x4000C09CU) /**< \brief (TC0) Register C (channel = 2) */ + #define REG_TC0_SR2 (*(__I uint32_t*)0x4000C0A0U) /**< \brief (TC0) Status Register (channel = 2) */ + #define REG_TC0_IER2 (*(__O uint32_t*)0x4000C0A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ + #define REG_TC0_IDR2 (*(__O uint32_t*)0x4000C0A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ + #define REG_TC0_IMR2 (*(__I uint32_t*)0x4000C0ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ + #define REG_TC0_EMR2 (*(__IO uint32_t*)0x4000C0B0U) /**< \brief (TC0) Extended Mode Register (channel = 2) */ + #define REG_TC0_BCR (*(__O uint32_t*)0x4000C0C0U) /**< \brief (TC0) Block Control Register */ + #define REG_TC0_BMR (*(__IO uint32_t*)0x4000C0C4U) /**< \brief (TC0) Block Mode Register */ + #define REG_TC0_QIER (*(__O uint32_t*)0x4000C0C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */ + #define REG_TC0_QIDR (*(__O uint32_t*)0x4000C0CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */ + #define REG_TC0_QIMR (*(__I uint32_t*)0x4000C0D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */ + #define REG_TC0_QISR (*(__I uint32_t*)0x4000C0D4U) /**< \brief (TC0) QDEC Interrupt Status Register */ + #define REG_TC0_FMR (*(__IO uint32_t*)0x4000C0D8U) /**< \brief (TC0) Fault Mode Register */ + #define REG_TC0_WPMR (*(__IO uint32_t*)0x4000C0E4U) /**< \brief (TC0) Write Protection Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_TC0_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_tc1.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_tc1.h new file mode 100644 index 00000000..059c8d50 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_tc1.h @@ -0,0 +1,132 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_TC1_INSTANCE_ +#define _SAMV71_TC1_INSTANCE_ + +/* ========== Register definition for TC1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TC1_CCR0 (0x40010000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ + #define REG_TC1_CMR0 (0x40010004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ + #define REG_TC1_SMMR0 (0x40010008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC1_RAB0 (0x4001000CU) /**< \brief (TC1) Register AB (channel = 0) */ + #define REG_TC1_CV0 (0x40010010U) /**< \brief (TC1) Counter Value (channel = 0) */ + #define REG_TC1_RA0 (0x40010014U) /**< \brief (TC1) Register A (channel = 0) */ + #define REG_TC1_RB0 (0x40010018U) /**< \brief (TC1) Register B (channel = 0) */ + #define REG_TC1_RC0 (0x4001001CU) /**< \brief (TC1) Register C (channel = 0) */ + #define REG_TC1_SR0 (0x40010020U) /**< \brief (TC1) Status Register (channel = 0) */ + #define REG_TC1_IER0 (0x40010024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ + #define REG_TC1_IDR0 (0x40010028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ + #define REG_TC1_IMR0 (0x4001002CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ + #define REG_TC1_EMR0 (0x40010030U) /**< \brief (TC1) Extended Mode Register (channel = 0) */ + #define REG_TC1_CCR1 (0x40010040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ + #define REG_TC1_CMR1 (0x40010044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ + #define REG_TC1_SMMR1 (0x40010048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC1_RAB1 (0x4001004CU) /**< \brief (TC1) Register AB (channel = 1) */ + #define REG_TC1_CV1 (0x40010050U) /**< \brief (TC1) Counter Value (channel = 1) */ + #define REG_TC1_RA1 (0x40010054U) /**< \brief (TC1) Register A (channel = 1) */ + #define REG_TC1_RB1 (0x40010058U) /**< \brief (TC1) Register B (channel = 1) */ + #define REG_TC1_RC1 (0x4001005CU) /**< \brief (TC1) Register C (channel = 1) */ + #define REG_TC1_SR1 (0x40010060U) /**< \brief (TC1) Status Register (channel = 1) */ + #define REG_TC1_IER1 (0x40010064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ + #define REG_TC1_IDR1 (0x40010068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ + #define REG_TC1_IMR1 (0x4001006CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ + #define REG_TC1_EMR1 (0x40010070U) /**< \brief (TC1) Extended Mode Register (channel = 1) */ + #define REG_TC1_CCR2 (0x40010080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ + #define REG_TC1_CMR2 (0x40010084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ + #define REG_TC1_SMMR2 (0x40010088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC1_RAB2 (0x4001008CU) /**< \brief (TC1) Register AB (channel = 2) */ + #define REG_TC1_CV2 (0x40010090U) /**< \brief (TC1) Counter Value (channel = 2) */ + #define REG_TC1_RA2 (0x40010094U) /**< \brief (TC1) Register A (channel = 2) */ + #define REG_TC1_RB2 (0x40010098U) /**< \brief (TC1) Register B (channel = 2) */ + #define REG_TC1_RC2 (0x4001009CU) /**< \brief (TC1) Register C (channel = 2) */ + #define REG_TC1_SR2 (0x400100A0U) /**< \brief (TC1) Status Register (channel = 2) */ + #define REG_TC1_IER2 (0x400100A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ + #define REG_TC1_IDR2 (0x400100A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ + #define REG_TC1_IMR2 (0x400100ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ + #define REG_TC1_EMR2 (0x400100B0U) /**< \brief (TC1) Extended Mode Register (channel = 2) */ + #define REG_TC1_BCR (0x400100C0U) /**< \brief (TC1) Block Control Register */ + #define REG_TC1_BMR (0x400100C4U) /**< \brief (TC1) Block Mode Register */ + #define REG_TC1_QIER (0x400100C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */ + #define REG_TC1_QIDR (0x400100CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */ + #define REG_TC1_QIMR (0x400100D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */ + #define REG_TC1_QISR (0x400100D4U) /**< \brief (TC1) QDEC Interrupt Status Register */ + #define REG_TC1_FMR (0x400100D8U) /**< \brief (TC1) Fault Mode Register */ + #define REG_TC1_WPMR (0x400100E4U) /**< \brief (TC1) Write Protection Mode Register */ +#else + #define REG_TC1_CCR0 (*(__O uint32_t*)0x40010000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ + #define REG_TC1_CMR0 (*(__IO uint32_t*)0x40010004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ + #define REG_TC1_SMMR0 (*(__IO uint32_t*)0x40010008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC1_RAB0 (*(__I uint32_t*)0x4001000CU) /**< \brief (TC1) Register AB (channel = 0) */ + #define REG_TC1_CV0 (*(__I uint32_t*)0x40010010U) /**< \brief (TC1) Counter Value (channel = 0) */ + #define REG_TC1_RA0 (*(__IO uint32_t*)0x40010014U) /**< \brief (TC1) Register A (channel = 0) */ + #define REG_TC1_RB0 (*(__IO uint32_t*)0x40010018U) /**< \brief (TC1) Register B (channel = 0) */ + #define REG_TC1_RC0 (*(__IO uint32_t*)0x4001001CU) /**< \brief (TC1) Register C (channel = 0) */ + #define REG_TC1_SR0 (*(__I uint32_t*)0x40010020U) /**< \brief (TC1) Status Register (channel = 0) */ + #define REG_TC1_IER0 (*(__O uint32_t*)0x40010024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ + #define REG_TC1_IDR0 (*(__O uint32_t*)0x40010028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ + #define REG_TC1_IMR0 (*(__I uint32_t*)0x4001002CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ + #define REG_TC1_EMR0 (*(__IO uint32_t*)0x40010030U) /**< \brief (TC1) Extended Mode Register (channel = 0) */ + #define REG_TC1_CCR1 (*(__O uint32_t*)0x40010040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ + #define REG_TC1_CMR1 (*(__IO uint32_t*)0x40010044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ + #define REG_TC1_SMMR1 (*(__IO uint32_t*)0x40010048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC1_RAB1 (*(__I uint32_t*)0x4001004CU) /**< \brief (TC1) Register AB (channel = 1) */ + #define REG_TC1_CV1 (*(__I uint32_t*)0x40010050U) /**< \brief (TC1) Counter Value (channel = 1) */ + #define REG_TC1_RA1 (*(__IO uint32_t*)0x40010054U) /**< \brief (TC1) Register A (channel = 1) */ + #define REG_TC1_RB1 (*(__IO uint32_t*)0x40010058U) /**< \brief (TC1) Register B (channel = 1) */ + #define REG_TC1_RC1 (*(__IO uint32_t*)0x4001005CU) /**< \brief (TC1) Register C (channel = 1) */ + #define REG_TC1_SR1 (*(__I uint32_t*)0x40010060U) /**< \brief (TC1) Status Register (channel = 1) */ + #define REG_TC1_IER1 (*(__O uint32_t*)0x40010064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ + #define REG_TC1_IDR1 (*(__O uint32_t*)0x40010068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ + #define REG_TC1_IMR1 (*(__I uint32_t*)0x4001006CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ + #define REG_TC1_EMR1 (*(__IO uint32_t*)0x40010070U) /**< \brief (TC1) Extended Mode Register (channel = 1) */ + #define REG_TC1_CCR2 (*(__O uint32_t*)0x40010080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ + #define REG_TC1_CMR2 (*(__IO uint32_t*)0x40010084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ + #define REG_TC1_SMMR2 (*(__IO uint32_t*)0x40010088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC1_RAB2 (*(__I uint32_t*)0x4001008CU) /**< \brief (TC1) Register AB (channel = 2) */ + #define REG_TC1_CV2 (*(__I uint32_t*)0x40010090U) /**< \brief (TC1) Counter Value (channel = 2) */ + #define REG_TC1_RA2 (*(__IO uint32_t*)0x40010094U) /**< \brief (TC1) Register A (channel = 2) */ + #define REG_TC1_RB2 (*(__IO uint32_t*)0x40010098U) /**< \brief (TC1) Register B (channel = 2) */ + #define REG_TC1_RC2 (*(__IO uint32_t*)0x4001009CU) /**< \brief (TC1) Register C (channel = 2) */ + #define REG_TC1_SR2 (*(__I uint32_t*)0x400100A0U) /**< \brief (TC1) Status Register (channel = 2) */ + #define REG_TC1_IER2 (*(__O uint32_t*)0x400100A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ + #define REG_TC1_IDR2 (*(__O uint32_t*)0x400100A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ + #define REG_TC1_IMR2 (*(__I uint32_t*)0x400100ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ + #define REG_TC1_EMR2 (*(__IO uint32_t*)0x400100B0U) /**< \brief (TC1) Extended Mode Register (channel = 2) */ + #define REG_TC1_BCR (*(__O uint32_t*)0x400100C0U) /**< \brief (TC1) Block Control Register */ + #define REG_TC1_BMR (*(__IO uint32_t*)0x400100C4U) /**< \brief (TC1) Block Mode Register */ + #define REG_TC1_QIER (*(__O uint32_t*)0x400100C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */ + #define REG_TC1_QIDR (*(__O uint32_t*)0x400100CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */ + #define REG_TC1_QIMR (*(__I uint32_t*)0x400100D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */ + #define REG_TC1_QISR (*(__I uint32_t*)0x400100D4U) /**< \brief (TC1) QDEC Interrupt Status Register */ + #define REG_TC1_FMR (*(__IO uint32_t*)0x400100D8U) /**< \brief (TC1) Fault Mode Register */ + #define REG_TC1_WPMR (*(__IO uint32_t*)0x400100E4U) /**< \brief (TC1) Write Protection Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_TC1_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_tc2.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_tc2.h new file mode 100644 index 00000000..4d8ba52f --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_tc2.h @@ -0,0 +1,132 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_TC2_INSTANCE_ +#define _SAMV71_TC2_INSTANCE_ + +/* ========== Register definition for TC2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TC2_CCR0 (0x40014000U) /**< \brief (TC2) Channel Control Register (channel = 0) */ + #define REG_TC2_CMR0 (0x40014004U) /**< \brief (TC2) Channel Mode Register (channel = 0) */ + #define REG_TC2_SMMR0 (0x40014008U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC2_RAB0 (0x4001400CU) /**< \brief (TC2) Register AB (channel = 0) */ + #define REG_TC2_CV0 (0x40014010U) /**< \brief (TC2) Counter Value (channel = 0) */ + #define REG_TC2_RA0 (0x40014014U) /**< \brief (TC2) Register A (channel = 0) */ + #define REG_TC2_RB0 (0x40014018U) /**< \brief (TC2) Register B (channel = 0) */ + #define REG_TC2_RC0 (0x4001401CU) /**< \brief (TC2) Register C (channel = 0) */ + #define REG_TC2_SR0 (0x40014020U) /**< \brief (TC2) Status Register (channel = 0) */ + #define REG_TC2_IER0 (0x40014024U) /**< \brief (TC2) Interrupt Enable Register (channel = 0) */ + #define REG_TC2_IDR0 (0x40014028U) /**< \brief (TC2) Interrupt Disable Register (channel = 0) */ + #define REG_TC2_IMR0 (0x4001402CU) /**< \brief (TC2) Interrupt Mask Register (channel = 0) */ + #define REG_TC2_EMR0 (0x40014030U) /**< \brief (TC2) Extended Mode Register (channel = 0) */ + #define REG_TC2_CCR1 (0x40014040U) /**< \brief (TC2) Channel Control Register (channel = 1) */ + #define REG_TC2_CMR1 (0x40014044U) /**< \brief (TC2) Channel Mode Register (channel = 1) */ + #define REG_TC2_SMMR1 (0x40014048U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC2_RAB1 (0x4001404CU) /**< \brief (TC2) Register AB (channel = 1) */ + #define REG_TC2_CV1 (0x40014050U) /**< \brief (TC2) Counter Value (channel = 1) */ + #define REG_TC2_RA1 (0x40014054U) /**< \brief (TC2) Register A (channel = 1) */ + #define REG_TC2_RB1 (0x40014058U) /**< \brief (TC2) Register B (channel = 1) */ + #define REG_TC2_RC1 (0x4001405CU) /**< \brief (TC2) Register C (channel = 1) */ + #define REG_TC2_SR1 (0x40014060U) /**< \brief (TC2) Status Register (channel = 1) */ + #define REG_TC2_IER1 (0x40014064U) /**< \brief (TC2) Interrupt Enable Register (channel = 1) */ + #define REG_TC2_IDR1 (0x40014068U) /**< \brief (TC2) Interrupt Disable Register (channel = 1) */ + #define REG_TC2_IMR1 (0x4001406CU) /**< \brief (TC2) Interrupt Mask Register (channel = 1) */ + #define REG_TC2_EMR1 (0x40014070U) /**< \brief (TC2) Extended Mode Register (channel = 1) */ + #define REG_TC2_CCR2 (0x40014080U) /**< \brief (TC2) Channel Control Register (channel = 2) */ + #define REG_TC2_CMR2 (0x40014084U) /**< \brief (TC2) Channel Mode Register (channel = 2) */ + #define REG_TC2_SMMR2 (0x40014088U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC2_RAB2 (0x4001408CU) /**< \brief (TC2) Register AB (channel = 2) */ + #define REG_TC2_CV2 (0x40014090U) /**< \brief (TC2) Counter Value (channel = 2) */ + #define REG_TC2_RA2 (0x40014094U) /**< \brief (TC2) Register A (channel = 2) */ + #define REG_TC2_RB2 (0x40014098U) /**< \brief (TC2) Register B (channel = 2) */ + #define REG_TC2_RC2 (0x4001409CU) /**< \brief (TC2) Register C (channel = 2) */ + #define REG_TC2_SR2 (0x400140A0U) /**< \brief (TC2) Status Register (channel = 2) */ + #define REG_TC2_IER2 (0x400140A4U) /**< \brief (TC2) Interrupt Enable Register (channel = 2) */ + #define REG_TC2_IDR2 (0x400140A8U) /**< \brief (TC2) Interrupt Disable Register (channel = 2) */ + #define REG_TC2_IMR2 (0x400140ACU) /**< \brief (TC2) Interrupt Mask Register (channel = 2) */ + #define REG_TC2_EMR2 (0x400140B0U) /**< \brief (TC2) Extended Mode Register (channel = 2) */ + #define REG_TC2_BCR (0x400140C0U) /**< \brief (TC2) Block Control Register */ + #define REG_TC2_BMR (0x400140C4U) /**< \brief (TC2) Block Mode Register */ + #define REG_TC2_QIER (0x400140C8U) /**< \brief (TC2) QDEC Interrupt Enable Register */ + #define REG_TC2_QIDR (0x400140CCU) /**< \brief (TC2) QDEC Interrupt Disable Register */ + #define REG_TC2_QIMR (0x400140D0U) /**< \brief (TC2) QDEC Interrupt Mask Register */ + #define REG_TC2_QISR (0x400140D4U) /**< \brief (TC2) QDEC Interrupt Status Register */ + #define REG_TC2_FMR (0x400140D8U) /**< \brief (TC2) Fault Mode Register */ + #define REG_TC2_WPMR (0x400140E4U) /**< \brief (TC2) Write Protection Mode Register */ +#else + #define REG_TC2_CCR0 (*(__O uint32_t*)0x40014000U) /**< \brief (TC2) Channel Control Register (channel = 0) */ + #define REG_TC2_CMR0 (*(__IO uint32_t*)0x40014004U) /**< \brief (TC2) Channel Mode Register (channel = 0) */ + #define REG_TC2_SMMR0 (*(__IO uint32_t*)0x40014008U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC2_RAB0 (*(__I uint32_t*)0x4001400CU) /**< \brief (TC2) Register AB (channel = 0) */ + #define REG_TC2_CV0 (*(__I uint32_t*)0x40014010U) /**< \brief (TC2) Counter Value (channel = 0) */ + #define REG_TC2_RA0 (*(__IO uint32_t*)0x40014014U) /**< \brief (TC2) Register A (channel = 0) */ + #define REG_TC2_RB0 (*(__IO uint32_t*)0x40014018U) /**< \brief (TC2) Register B (channel = 0) */ + #define REG_TC2_RC0 (*(__IO uint32_t*)0x4001401CU) /**< \brief (TC2) Register C (channel = 0) */ + #define REG_TC2_SR0 (*(__I uint32_t*)0x40014020U) /**< \brief (TC2) Status Register (channel = 0) */ + #define REG_TC2_IER0 (*(__O uint32_t*)0x40014024U) /**< \brief (TC2) Interrupt Enable Register (channel = 0) */ + #define REG_TC2_IDR0 (*(__O uint32_t*)0x40014028U) /**< \brief (TC2) Interrupt Disable Register (channel = 0) */ + #define REG_TC2_IMR0 (*(__I uint32_t*)0x4001402CU) /**< \brief (TC2) Interrupt Mask Register (channel = 0) */ + #define REG_TC2_EMR0 (*(__IO uint32_t*)0x40014030U) /**< \brief (TC2) Extended Mode Register (channel = 0) */ + #define REG_TC2_CCR1 (*(__O uint32_t*)0x40014040U) /**< \brief (TC2) Channel Control Register (channel = 1) */ + #define REG_TC2_CMR1 (*(__IO uint32_t*)0x40014044U) /**< \brief (TC2) Channel Mode Register (channel = 1) */ + #define REG_TC2_SMMR1 (*(__IO uint32_t*)0x40014048U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC2_RAB1 (*(__I uint32_t*)0x4001404CU) /**< \brief (TC2) Register AB (channel = 1) */ + #define REG_TC2_CV1 (*(__I uint32_t*)0x40014050U) /**< \brief (TC2) Counter Value (channel = 1) */ + #define REG_TC2_RA1 (*(__IO uint32_t*)0x40014054U) /**< \brief (TC2) Register A (channel = 1) */ + #define REG_TC2_RB1 (*(__IO uint32_t*)0x40014058U) /**< \brief (TC2) Register B (channel = 1) */ + #define REG_TC2_RC1 (*(__IO uint32_t*)0x4001405CU) /**< \brief (TC2) Register C (channel = 1) */ + #define REG_TC2_SR1 (*(__I uint32_t*)0x40014060U) /**< \brief (TC2) Status Register (channel = 1) */ + #define REG_TC2_IER1 (*(__O uint32_t*)0x40014064U) /**< \brief (TC2) Interrupt Enable Register (channel = 1) */ + #define REG_TC2_IDR1 (*(__O uint32_t*)0x40014068U) /**< \brief (TC2) Interrupt Disable Register (channel = 1) */ + #define REG_TC2_IMR1 (*(__I uint32_t*)0x4001406CU) /**< \brief (TC2) Interrupt Mask Register (channel = 1) */ + #define REG_TC2_EMR1 (*(__IO uint32_t*)0x40014070U) /**< \brief (TC2) Extended Mode Register (channel = 1) */ + #define REG_TC2_CCR2 (*(__O uint32_t*)0x40014080U) /**< \brief (TC2) Channel Control Register (channel = 2) */ + #define REG_TC2_CMR2 (*(__IO uint32_t*)0x40014084U) /**< \brief (TC2) Channel Mode Register (channel = 2) */ + #define REG_TC2_SMMR2 (*(__IO uint32_t*)0x40014088U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC2_RAB2 (*(__I uint32_t*)0x4001408CU) /**< \brief (TC2) Register AB (channel = 2) */ + #define REG_TC2_CV2 (*(__I uint32_t*)0x40014090U) /**< \brief (TC2) Counter Value (channel = 2) */ + #define REG_TC2_RA2 (*(__IO uint32_t*)0x40014094U) /**< \brief (TC2) Register A (channel = 2) */ + #define REG_TC2_RB2 (*(__IO uint32_t*)0x40014098U) /**< \brief (TC2) Register B (channel = 2) */ + #define REG_TC2_RC2 (*(__IO uint32_t*)0x4001409CU) /**< \brief (TC2) Register C (channel = 2) */ + #define REG_TC2_SR2 (*(__I uint32_t*)0x400140A0U) /**< \brief (TC2) Status Register (channel = 2) */ + #define REG_TC2_IER2 (*(__O uint32_t*)0x400140A4U) /**< \brief (TC2) Interrupt Enable Register (channel = 2) */ + #define REG_TC2_IDR2 (*(__O uint32_t*)0x400140A8U) /**< \brief (TC2) Interrupt Disable Register (channel = 2) */ + #define REG_TC2_IMR2 (*(__I uint32_t*)0x400140ACU) /**< \brief (TC2) Interrupt Mask Register (channel = 2) */ + #define REG_TC2_EMR2 (*(__IO uint32_t*)0x400140B0U) /**< \brief (TC2) Extended Mode Register (channel = 2) */ + #define REG_TC2_BCR (*(__O uint32_t*)0x400140C0U) /**< \brief (TC2) Block Control Register */ + #define REG_TC2_BMR (*(__IO uint32_t*)0x400140C4U) /**< \brief (TC2) Block Mode Register */ + #define REG_TC2_QIER (*(__O uint32_t*)0x400140C8U) /**< \brief (TC2) QDEC Interrupt Enable Register */ + #define REG_TC2_QIDR (*(__O uint32_t*)0x400140CCU) /**< \brief (TC2) QDEC Interrupt Disable Register */ + #define REG_TC2_QIMR (*(__I uint32_t*)0x400140D0U) /**< \brief (TC2) QDEC Interrupt Mask Register */ + #define REG_TC2_QISR (*(__I uint32_t*)0x400140D4U) /**< \brief (TC2) QDEC Interrupt Status Register */ + #define REG_TC2_FMR (*(__IO uint32_t*)0x400140D8U) /**< \brief (TC2) Fault Mode Register */ + #define REG_TC2_WPMR (*(__IO uint32_t*)0x400140E4U) /**< \brief (TC2) Write Protection Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_TC2_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_tc3.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_tc3.h new file mode 100644 index 00000000..20ea7e42 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_tc3.h @@ -0,0 +1,132 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_TC3_INSTANCE_ +#define _SAMV71_TC3_INSTANCE_ + +/* ========== Register definition for TC3 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TC3_CCR0 (0x40054000U) /**< \brief (TC3) Channel Control Register (channel = 0) */ + #define REG_TC3_CMR0 (0x40054004U) /**< \brief (TC3) Channel Mode Register (channel = 0) */ + #define REG_TC3_SMMR0 (0x40054008U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC3_RAB0 (0x4005400CU) /**< \brief (TC3) Register AB (channel = 0) */ + #define REG_TC3_CV0 (0x40054010U) /**< \brief (TC3) Counter Value (channel = 0) */ + #define REG_TC3_RA0 (0x40054014U) /**< \brief (TC3) Register A (channel = 0) */ + #define REG_TC3_RB0 (0x40054018U) /**< \brief (TC3) Register B (channel = 0) */ + #define REG_TC3_RC0 (0x4005401CU) /**< \brief (TC3) Register C (channel = 0) */ + #define REG_TC3_SR0 (0x40054020U) /**< \brief (TC3) Status Register (channel = 0) */ + #define REG_TC3_IER0 (0x40054024U) /**< \brief (TC3) Interrupt Enable Register (channel = 0) */ + #define REG_TC3_IDR0 (0x40054028U) /**< \brief (TC3) Interrupt Disable Register (channel = 0) */ + #define REG_TC3_IMR0 (0x4005402CU) /**< \brief (TC3) Interrupt Mask Register (channel = 0) */ + #define REG_TC3_EMR0 (0x40054030U) /**< \brief (TC3) Extended Mode Register (channel = 0) */ + #define REG_TC3_CCR1 (0x40054040U) /**< \brief (TC3) Channel Control Register (channel = 1) */ + #define REG_TC3_CMR1 (0x40054044U) /**< \brief (TC3) Channel Mode Register (channel = 1) */ + #define REG_TC3_SMMR1 (0x40054048U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC3_RAB1 (0x4005404CU) /**< \brief (TC3) Register AB (channel = 1) */ + #define REG_TC3_CV1 (0x40054050U) /**< \brief (TC3) Counter Value (channel = 1) */ + #define REG_TC3_RA1 (0x40054054U) /**< \brief (TC3) Register A (channel = 1) */ + #define REG_TC3_RB1 (0x40054058U) /**< \brief (TC3) Register B (channel = 1) */ + #define REG_TC3_RC1 (0x4005405CU) /**< \brief (TC3) Register C (channel = 1) */ + #define REG_TC3_SR1 (0x40054060U) /**< \brief (TC3) Status Register (channel = 1) */ + #define REG_TC3_IER1 (0x40054064U) /**< \brief (TC3) Interrupt Enable Register (channel = 1) */ + #define REG_TC3_IDR1 (0x40054068U) /**< \brief (TC3) Interrupt Disable Register (channel = 1) */ + #define REG_TC3_IMR1 (0x4005406CU) /**< \brief (TC3) Interrupt Mask Register (channel = 1) */ + #define REG_TC3_EMR1 (0x40054070U) /**< \brief (TC3) Extended Mode Register (channel = 1) */ + #define REG_TC3_CCR2 (0x40054080U) /**< \brief (TC3) Channel Control Register (channel = 2) */ + #define REG_TC3_CMR2 (0x40054084U) /**< \brief (TC3) Channel Mode Register (channel = 2) */ + #define REG_TC3_SMMR2 (0x40054088U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC3_RAB2 (0x4005408CU) /**< \brief (TC3) Register AB (channel = 2) */ + #define REG_TC3_CV2 (0x40054090U) /**< \brief (TC3) Counter Value (channel = 2) */ + #define REG_TC3_RA2 (0x40054094U) /**< \brief (TC3) Register A (channel = 2) */ + #define REG_TC3_RB2 (0x40054098U) /**< \brief (TC3) Register B (channel = 2) */ + #define REG_TC3_RC2 (0x4005409CU) /**< \brief (TC3) Register C (channel = 2) */ + #define REG_TC3_SR2 (0x400540A0U) /**< \brief (TC3) Status Register (channel = 2) */ + #define REG_TC3_IER2 (0x400540A4U) /**< \brief (TC3) Interrupt Enable Register (channel = 2) */ + #define REG_TC3_IDR2 (0x400540A8U) /**< \brief (TC3) Interrupt Disable Register (channel = 2) */ + #define REG_TC3_IMR2 (0x400540ACU) /**< \brief (TC3) Interrupt Mask Register (channel = 2) */ + #define REG_TC3_EMR2 (0x400540B0U) /**< \brief (TC3) Extended Mode Register (channel = 2) */ + #define REG_TC3_BCR (0x400540C0U) /**< \brief (TC3) Block Control Register */ + #define REG_TC3_BMR (0x400540C4U) /**< \brief (TC3) Block Mode Register */ + #define REG_TC3_QIER (0x400540C8U) /**< \brief (TC3) QDEC Interrupt Enable Register */ + #define REG_TC3_QIDR (0x400540CCU) /**< \brief (TC3) QDEC Interrupt Disable Register */ + #define REG_TC3_QIMR (0x400540D0U) /**< \brief (TC3) QDEC Interrupt Mask Register */ + #define REG_TC3_QISR (0x400540D4U) /**< \brief (TC3) QDEC Interrupt Status Register */ + #define REG_TC3_FMR (0x400540D8U) /**< \brief (TC3) Fault Mode Register */ + #define REG_TC3_WPMR (0x400540E4U) /**< \brief (TC3) Write Protection Mode Register */ +#else + #define REG_TC3_CCR0 (*(__O uint32_t*)0x40054000U) /**< \brief (TC3) Channel Control Register (channel = 0) */ + #define REG_TC3_CMR0 (*(__IO uint32_t*)0x40054004U) /**< \brief (TC3) Channel Mode Register (channel = 0) */ + #define REG_TC3_SMMR0 (*(__IO uint32_t*)0x40054008U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC3_RAB0 (*(__I uint32_t*)0x4005400CU) /**< \brief (TC3) Register AB (channel = 0) */ + #define REG_TC3_CV0 (*(__I uint32_t*)0x40054010U) /**< \brief (TC3) Counter Value (channel = 0) */ + #define REG_TC3_RA0 (*(__IO uint32_t*)0x40054014U) /**< \brief (TC3) Register A (channel = 0) */ + #define REG_TC3_RB0 (*(__IO uint32_t*)0x40054018U) /**< \brief (TC3) Register B (channel = 0) */ + #define REG_TC3_RC0 (*(__IO uint32_t*)0x4005401CU) /**< \brief (TC3) Register C (channel = 0) */ + #define REG_TC3_SR0 (*(__I uint32_t*)0x40054020U) /**< \brief (TC3) Status Register (channel = 0) */ + #define REG_TC3_IER0 (*(__O uint32_t*)0x40054024U) /**< \brief (TC3) Interrupt Enable Register (channel = 0) */ + #define REG_TC3_IDR0 (*(__O uint32_t*)0x40054028U) /**< \brief (TC3) Interrupt Disable Register (channel = 0) */ + #define REG_TC3_IMR0 (*(__I uint32_t*)0x4005402CU) /**< \brief (TC3) Interrupt Mask Register (channel = 0) */ + #define REG_TC3_EMR0 (*(__IO uint32_t*)0x40054030U) /**< \brief (TC3) Extended Mode Register (channel = 0) */ + #define REG_TC3_CCR1 (*(__O uint32_t*)0x40054040U) /**< \brief (TC3) Channel Control Register (channel = 1) */ + #define REG_TC3_CMR1 (*(__IO uint32_t*)0x40054044U) /**< \brief (TC3) Channel Mode Register (channel = 1) */ + #define REG_TC3_SMMR1 (*(__IO uint32_t*)0x40054048U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC3_RAB1 (*(__I uint32_t*)0x4005404CU) /**< \brief (TC3) Register AB (channel = 1) */ + #define REG_TC3_CV1 (*(__I uint32_t*)0x40054050U) /**< \brief (TC3) Counter Value (channel = 1) */ + #define REG_TC3_RA1 (*(__IO uint32_t*)0x40054054U) /**< \brief (TC3) Register A (channel = 1) */ + #define REG_TC3_RB1 (*(__IO uint32_t*)0x40054058U) /**< \brief (TC3) Register B (channel = 1) */ + #define REG_TC3_RC1 (*(__IO uint32_t*)0x4005405CU) /**< \brief (TC3) Register C (channel = 1) */ + #define REG_TC3_SR1 (*(__I uint32_t*)0x40054060U) /**< \brief (TC3) Status Register (channel = 1) */ + #define REG_TC3_IER1 (*(__O uint32_t*)0x40054064U) /**< \brief (TC3) Interrupt Enable Register (channel = 1) */ + #define REG_TC3_IDR1 (*(__O uint32_t*)0x40054068U) /**< \brief (TC3) Interrupt Disable Register (channel = 1) */ + #define REG_TC3_IMR1 (*(__I uint32_t*)0x4005406CU) /**< \brief (TC3) Interrupt Mask Register (channel = 1) */ + #define REG_TC3_EMR1 (*(__IO uint32_t*)0x40054070U) /**< \brief (TC3) Extended Mode Register (channel = 1) */ + #define REG_TC3_CCR2 (*(__O uint32_t*)0x40054080U) /**< \brief (TC3) Channel Control Register (channel = 2) */ + #define REG_TC3_CMR2 (*(__IO uint32_t*)0x40054084U) /**< \brief (TC3) Channel Mode Register (channel = 2) */ + #define REG_TC3_SMMR2 (*(__IO uint32_t*)0x40054088U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC3_RAB2 (*(__I uint32_t*)0x4005408CU) /**< \brief (TC3) Register AB (channel = 2) */ + #define REG_TC3_CV2 (*(__I uint32_t*)0x40054090U) /**< \brief (TC3) Counter Value (channel = 2) */ + #define REG_TC3_RA2 (*(__IO uint32_t*)0x40054094U) /**< \brief (TC3) Register A (channel = 2) */ + #define REG_TC3_RB2 (*(__IO uint32_t*)0x40054098U) /**< \brief (TC3) Register B (channel = 2) */ + #define REG_TC3_RC2 (*(__IO uint32_t*)0x4005409CU) /**< \brief (TC3) Register C (channel = 2) */ + #define REG_TC3_SR2 (*(__I uint32_t*)0x400540A0U) /**< \brief (TC3) Status Register (channel = 2) */ + #define REG_TC3_IER2 (*(__O uint32_t*)0x400540A4U) /**< \brief (TC3) Interrupt Enable Register (channel = 2) */ + #define REG_TC3_IDR2 (*(__O uint32_t*)0x400540A8U) /**< \brief (TC3) Interrupt Disable Register (channel = 2) */ + #define REG_TC3_IMR2 (*(__I uint32_t*)0x400540ACU) /**< \brief (TC3) Interrupt Mask Register (channel = 2) */ + #define REG_TC3_EMR2 (*(__IO uint32_t*)0x400540B0U) /**< \brief (TC3) Extended Mode Register (channel = 2) */ + #define REG_TC3_BCR (*(__O uint32_t*)0x400540C0U) /**< \brief (TC3) Block Control Register */ + #define REG_TC3_BMR (*(__IO uint32_t*)0x400540C4U) /**< \brief (TC3) Block Mode Register */ + #define REG_TC3_QIER (*(__O uint32_t*)0x400540C8U) /**< \brief (TC3) QDEC Interrupt Enable Register */ + #define REG_TC3_QIDR (*(__O uint32_t*)0x400540CCU) /**< \brief (TC3) QDEC Interrupt Disable Register */ + #define REG_TC3_QIMR (*(__I uint32_t*)0x400540D0U) /**< \brief (TC3) QDEC Interrupt Mask Register */ + #define REG_TC3_QISR (*(__I uint32_t*)0x400540D4U) /**< \brief (TC3) QDEC Interrupt Status Register */ + #define REG_TC3_FMR (*(__IO uint32_t*)0x400540D8U) /**< \brief (TC3) Fault Mode Register */ + #define REG_TC3_WPMR (*(__IO uint32_t*)0x400540E4U) /**< \brief (TC3) Write Protection Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_TC3_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_trng.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_trng.h new file mode 100644 index 00000000..ee9b08d7 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_trng.h @@ -0,0 +1,50 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_TRNG_INSTANCE_ +#define _SAMV71_TRNG_INSTANCE_ + +/* ========== Register definition for TRNG peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TRNG_CR (0x40070000U) /**< \brief (TRNG) Control Register */ + #define REG_TRNG_IER (0x40070010U) /**< \brief (TRNG) Interrupt Enable Register */ + #define REG_TRNG_IDR (0x40070014U) /**< \brief (TRNG) Interrupt Disable Register */ + #define REG_TRNG_IMR (0x40070018U) /**< \brief (TRNG) Interrupt Mask Register */ + #define REG_TRNG_ISR (0x4007001CU) /**< \brief (TRNG) Interrupt Status Register */ + #define REG_TRNG_ODATA (0x40070050U) /**< \brief (TRNG) Output Data Register */ +#else + #define REG_TRNG_CR (*(__O uint32_t*)0x40070000U) /**< \brief (TRNG) Control Register */ + #define REG_TRNG_IER (*(__O uint32_t*)0x40070010U) /**< \brief (TRNG) Interrupt Enable Register */ + #define REG_TRNG_IDR (*(__O uint32_t*)0x40070014U) /**< \brief (TRNG) Interrupt Disable Register */ + #define REG_TRNG_IMR (*(__I uint32_t*)0x40070018U) /**< \brief (TRNG) Interrupt Mask Register */ + #define REG_TRNG_ISR (*(__I uint32_t*)0x4007001CU) /**< \brief (TRNG) Interrupt Status Register */ + #define REG_TRNG_ODATA (*(__I uint32_t*)0x40070050U) /**< \brief (TRNG) Output Data Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_TRNG_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_twihs0.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_twihs0.h new file mode 100644 index 00000000..12705822 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_twihs0.h @@ -0,0 +1,70 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_TWIHS0_INSTANCE_ +#define _SAMV71_TWIHS0_INSTANCE_ + +/* ========== Register definition for TWIHS0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TWIHS0_CR (0x40018000U) /**< \brief (TWIHS0) Control Register */ + #define REG_TWIHS0_MMR (0x40018004U) /**< \brief (TWIHS0) Master Mode Register */ + #define REG_TWIHS0_SMR (0x40018008U) /**< \brief (TWIHS0) Slave Mode Register */ + #define REG_TWIHS0_IADR (0x4001800CU) /**< \brief (TWIHS0) Internal Address Register */ + #define REG_TWIHS0_CWGR (0x40018010U) /**< \brief (TWIHS0) Clock Waveform Generator Register */ + #define REG_TWIHS0_SR (0x40018020U) /**< \brief (TWIHS0) Status Register */ + #define REG_TWIHS0_IER (0x40018024U) /**< \brief (TWIHS0) Interrupt Enable Register */ + #define REG_TWIHS0_IDR (0x40018028U) /**< \brief (TWIHS0) Interrupt Disable Register */ + #define REG_TWIHS0_IMR (0x4001802CU) /**< \brief (TWIHS0) Interrupt Mask Register */ + #define REG_TWIHS0_RHR (0x40018030U) /**< \brief (TWIHS0) Receive Holding Register */ + #define REG_TWIHS0_THR (0x40018034U) /**< \brief (TWIHS0) Transmit Holding Register */ + #define REG_TWIHS0_SMBTR (0x40018038U) /**< \brief (TWIHS0) SMBus Timing Register */ + #define REG_TWIHS0_FILTR (0x40018044U) /**< \brief (TWIHS0) Filter Register */ + #define REG_TWIHS0_SWMR (0x4001804CU) /**< \brief (TWIHS0) SleepWalking Matching Register */ + #define REG_TWIHS0_WPMR (0x400180E4U) /**< \brief (TWIHS0) Write Protection Mode Register */ + #define REG_TWIHS0_WPSR (0x400180E8U) /**< \brief (TWIHS0) Write Protection Status Register */ +#else + #define REG_TWIHS0_CR (*(__O uint32_t*)0x40018000U) /**< \brief (TWIHS0) Control Register */ + #define REG_TWIHS0_MMR (*(__IO uint32_t*)0x40018004U) /**< \brief (TWIHS0) Master Mode Register */ + #define REG_TWIHS0_SMR (*(__IO uint32_t*)0x40018008U) /**< \brief (TWIHS0) Slave Mode Register */ + #define REG_TWIHS0_IADR (*(__IO uint32_t*)0x4001800CU) /**< \brief (TWIHS0) Internal Address Register */ + #define REG_TWIHS0_CWGR (*(__IO uint32_t*)0x40018010U) /**< \brief (TWIHS0) Clock Waveform Generator Register */ + #define REG_TWIHS0_SR (*(__I uint32_t*)0x40018020U) /**< \brief (TWIHS0) Status Register */ + #define REG_TWIHS0_IER (*(__O uint32_t*)0x40018024U) /**< \brief (TWIHS0) Interrupt Enable Register */ + #define REG_TWIHS0_IDR (*(__O uint32_t*)0x40018028U) /**< \brief (TWIHS0) Interrupt Disable Register */ + #define REG_TWIHS0_IMR (*(__I uint32_t*)0x4001802CU) /**< \brief (TWIHS0) Interrupt Mask Register */ + #define REG_TWIHS0_RHR (*(__I uint32_t*)0x40018030U) /**< \brief (TWIHS0) Receive Holding Register */ + #define REG_TWIHS0_THR (*(__O uint32_t*)0x40018034U) /**< \brief (TWIHS0) Transmit Holding Register */ + #define REG_TWIHS0_SMBTR (*(__IO uint32_t*)0x40018038U) /**< \brief (TWIHS0) SMBus Timing Register */ + #define REG_TWIHS0_FILTR (*(__IO uint32_t*)0x40018044U) /**< \brief (TWIHS0) Filter Register */ + #define REG_TWIHS0_SWMR (*(__IO uint32_t*)0x4001804CU) /**< \brief (TWIHS0) SleepWalking Matching Register */ + #define REG_TWIHS0_WPMR (*(__IO uint32_t*)0x400180E4U) /**< \brief (TWIHS0) Write Protection Mode Register */ + #define REG_TWIHS0_WPSR (*(__I uint32_t*)0x400180E8U) /**< \brief (TWIHS0) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_TWIHS0_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_twihs1.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_twihs1.h new file mode 100644 index 00000000..11631f74 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_twihs1.h @@ -0,0 +1,70 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_TWIHS1_INSTANCE_ +#define _SAMV71_TWIHS1_INSTANCE_ + +/* ========== Register definition for TWIHS1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TWIHS1_CR (0x4001C000U) /**< \brief (TWIHS1) Control Register */ + #define REG_TWIHS1_MMR (0x4001C004U) /**< \brief (TWIHS1) Master Mode Register */ + #define REG_TWIHS1_SMR (0x4001C008U) /**< \brief (TWIHS1) Slave Mode Register */ + #define REG_TWIHS1_IADR (0x4001C00CU) /**< \brief (TWIHS1) Internal Address Register */ + #define REG_TWIHS1_CWGR (0x4001C010U) /**< \brief (TWIHS1) Clock Waveform Generator Register */ + #define REG_TWIHS1_SR (0x4001C020U) /**< \brief (TWIHS1) Status Register */ + #define REG_TWIHS1_IER (0x4001C024U) /**< \brief (TWIHS1) Interrupt Enable Register */ + #define REG_TWIHS1_IDR (0x4001C028U) /**< \brief (TWIHS1) Interrupt Disable Register */ + #define REG_TWIHS1_IMR (0x4001C02CU) /**< \brief (TWIHS1) Interrupt Mask Register */ + #define REG_TWIHS1_RHR (0x4001C030U) /**< \brief (TWIHS1) Receive Holding Register */ + #define REG_TWIHS1_THR (0x4001C034U) /**< \brief (TWIHS1) Transmit Holding Register */ + #define REG_TWIHS1_SMBTR (0x4001C038U) /**< \brief (TWIHS1) SMBus Timing Register */ + #define REG_TWIHS1_FILTR (0x4001C044U) /**< \brief (TWIHS1) Filter Register */ + #define REG_TWIHS1_SWMR (0x4001C04CU) /**< \brief (TWIHS1) SleepWalking Matching Register */ + #define REG_TWIHS1_WPMR (0x4001C0E4U) /**< \brief (TWIHS1) Write Protection Mode Register */ + #define REG_TWIHS1_WPSR (0x4001C0E8U) /**< \brief (TWIHS1) Write Protection Status Register */ +#else + #define REG_TWIHS1_CR (*(__O uint32_t*)0x4001C000U) /**< \brief (TWIHS1) Control Register */ + #define REG_TWIHS1_MMR (*(__IO uint32_t*)0x4001C004U) /**< \brief (TWIHS1) Master Mode Register */ + #define REG_TWIHS1_SMR (*(__IO uint32_t*)0x4001C008U) /**< \brief (TWIHS1) Slave Mode Register */ + #define REG_TWIHS1_IADR (*(__IO uint32_t*)0x4001C00CU) /**< \brief (TWIHS1) Internal Address Register */ + #define REG_TWIHS1_CWGR (*(__IO uint32_t*)0x4001C010U) /**< \brief (TWIHS1) Clock Waveform Generator Register */ + #define REG_TWIHS1_SR (*(__I uint32_t*)0x4001C020U) /**< \brief (TWIHS1) Status Register */ + #define REG_TWIHS1_IER (*(__O uint32_t*)0x4001C024U) /**< \brief (TWIHS1) Interrupt Enable Register */ + #define REG_TWIHS1_IDR (*(__O uint32_t*)0x4001C028U) /**< \brief (TWIHS1) Interrupt Disable Register */ + #define REG_TWIHS1_IMR (*(__I uint32_t*)0x4001C02CU) /**< \brief (TWIHS1) Interrupt Mask Register */ + #define REG_TWIHS1_RHR (*(__I uint32_t*)0x4001C030U) /**< \brief (TWIHS1) Receive Holding Register */ + #define REG_TWIHS1_THR (*(__O uint32_t*)0x4001C034U) /**< \brief (TWIHS1) Transmit Holding Register */ + #define REG_TWIHS1_SMBTR (*(__IO uint32_t*)0x4001C038U) /**< \brief (TWIHS1) SMBus Timing Register */ + #define REG_TWIHS1_FILTR (*(__IO uint32_t*)0x4001C044U) /**< \brief (TWIHS1) Filter Register */ + #define REG_TWIHS1_SWMR (*(__IO uint32_t*)0x4001C04CU) /**< \brief (TWIHS1) SleepWalking Matching Register */ + #define REG_TWIHS1_WPMR (*(__IO uint32_t*)0x4001C0E4U) /**< \brief (TWIHS1) Write Protection Mode Register */ + #define REG_TWIHS1_WPSR (*(__I uint32_t*)0x4001C0E8U) /**< \brief (TWIHS1) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_TWIHS1_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_twihs2.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_twihs2.h new file mode 100644 index 00000000..90e4ac20 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_twihs2.h @@ -0,0 +1,70 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_TWIHS2_INSTANCE_ +#define _SAMV71_TWIHS2_INSTANCE_ + +/* ========== Register definition for TWIHS2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TWIHS2_CR (0x40060000U) /**< \brief (TWIHS2) Control Register */ + #define REG_TWIHS2_MMR (0x40060004U) /**< \brief (TWIHS2) Master Mode Register */ + #define REG_TWIHS2_SMR (0x40060008U) /**< \brief (TWIHS2) Slave Mode Register */ + #define REG_TWIHS2_IADR (0x4006000CU) /**< \brief (TWIHS2) Internal Address Register */ + #define REG_TWIHS2_CWGR (0x40060010U) /**< \brief (TWIHS2) Clock Waveform Generator Register */ + #define REG_TWIHS2_SR (0x40060020U) /**< \brief (TWIHS2) Status Register */ + #define REG_TWIHS2_IER (0x40060024U) /**< \brief (TWIHS2) Interrupt Enable Register */ + #define REG_TWIHS2_IDR (0x40060028U) /**< \brief (TWIHS2) Interrupt Disable Register */ + #define REG_TWIHS2_IMR (0x4006002CU) /**< \brief (TWIHS2) Interrupt Mask Register */ + #define REG_TWIHS2_RHR (0x40060030U) /**< \brief (TWIHS2) Receive Holding Register */ + #define REG_TWIHS2_THR (0x40060034U) /**< \brief (TWIHS2) Transmit Holding Register */ + #define REG_TWIHS2_SMBTR (0x40060038U) /**< \brief (TWIHS2) SMBus Timing Register */ + #define REG_TWIHS2_FILTR (0x40060044U) /**< \brief (TWIHS2) Filter Register */ + #define REG_TWIHS2_SWMR (0x4006004CU) /**< \brief (TWIHS2) SleepWalking Matching Register */ + #define REG_TWIHS2_WPMR (0x400600E4U) /**< \brief (TWIHS2) Write Protection Mode Register */ + #define REG_TWIHS2_WPSR (0x400600E8U) /**< \brief (TWIHS2) Write Protection Status Register */ +#else + #define REG_TWIHS2_CR (*(__O uint32_t*)0x40060000U) /**< \brief (TWIHS2) Control Register */ + #define REG_TWIHS2_MMR (*(__IO uint32_t*)0x40060004U) /**< \brief (TWIHS2) Master Mode Register */ + #define REG_TWIHS2_SMR (*(__IO uint32_t*)0x40060008U) /**< \brief (TWIHS2) Slave Mode Register */ + #define REG_TWIHS2_IADR (*(__IO uint32_t*)0x4006000CU) /**< \brief (TWIHS2) Internal Address Register */ + #define REG_TWIHS2_CWGR (*(__IO uint32_t*)0x40060010U) /**< \brief (TWIHS2) Clock Waveform Generator Register */ + #define REG_TWIHS2_SR (*(__I uint32_t*)0x40060020U) /**< \brief (TWIHS2) Status Register */ + #define REG_TWIHS2_IER (*(__O uint32_t*)0x40060024U) /**< \brief (TWIHS2) Interrupt Enable Register */ + #define REG_TWIHS2_IDR (*(__O uint32_t*)0x40060028U) /**< \brief (TWIHS2) Interrupt Disable Register */ + #define REG_TWIHS2_IMR (*(__I uint32_t*)0x4006002CU) /**< \brief (TWIHS2) Interrupt Mask Register */ + #define REG_TWIHS2_RHR (*(__I uint32_t*)0x40060030U) /**< \brief (TWIHS2) Receive Holding Register */ + #define REG_TWIHS2_THR (*(__O uint32_t*)0x40060034U) /**< \brief (TWIHS2) Transmit Holding Register */ + #define REG_TWIHS2_SMBTR (*(__IO uint32_t*)0x40060038U) /**< \brief (TWIHS2) SMBus Timing Register */ + #define REG_TWIHS2_FILTR (*(__IO uint32_t*)0x40060044U) /**< \brief (TWIHS2) Filter Register */ + #define REG_TWIHS2_SWMR (*(__IO uint32_t*)0x4006004CU) /**< \brief (TWIHS2) SleepWalking Matching Register */ + #define REG_TWIHS2_WPMR (*(__IO uint32_t*)0x400600E4U) /**< \brief (TWIHS2) Write Protection Mode Register */ + #define REG_TWIHS2_WPSR (*(__I uint32_t*)0x400600E8U) /**< \brief (TWIHS2) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_TWIHS2_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_uart0.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_uart0.h new file mode 100644 index 00000000..3a8fa60b --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_uart0.h @@ -0,0 +1,60 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_UART0_INSTANCE_ +#define _SAMV71_UART0_INSTANCE_ + +/* ========== Register definition for UART0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_UART0_CR (0x400E0800U) /**< \brief (UART0) Control Register */ + #define REG_UART0_MR (0x400E0804U) /**< \brief (UART0) Mode Register */ + #define REG_UART0_IER (0x400E0808U) /**< \brief (UART0) Interrupt Enable Register */ + #define REG_UART0_IDR (0x400E080CU) /**< \brief (UART0) Interrupt Disable Register */ + #define REG_UART0_IMR (0x400E0810U) /**< \brief (UART0) Interrupt Mask Register */ + #define REG_UART0_SR (0x400E0814U) /**< \brief (UART0) Status Register */ + #define REG_UART0_RHR (0x400E0818U) /**< \brief (UART0) Receive Holding Register */ + #define REG_UART0_THR (0x400E081CU) /**< \brief (UART0) Transmit Holding Register */ + #define REG_UART0_BRGR (0x400E0820U) /**< \brief (UART0) Baud Rate Generator Register */ + #define REG_UART0_CMPR (0x400E0824U) /**< \brief (UART0) Comparison Register */ + #define REG_UART0_WPMR (0x400E08E4U) /**< \brief (UART0) Write Protection Mode Register */ +#else + #define REG_UART0_CR (*(__O uint32_t*)0x400E0800U) /**< \brief (UART0) Control Register */ + #define REG_UART0_MR (*(__IO uint32_t*)0x400E0804U) /**< \brief (UART0) Mode Register */ + #define REG_UART0_IER (*(__O uint32_t*)0x400E0808U) /**< \brief (UART0) Interrupt Enable Register */ + #define REG_UART0_IDR (*(__O uint32_t*)0x400E080CU) /**< \brief (UART0) Interrupt Disable Register */ + #define REG_UART0_IMR (*(__I uint32_t*)0x400E0810U) /**< \brief (UART0) Interrupt Mask Register */ + #define REG_UART0_SR (*(__I uint32_t*)0x400E0814U) /**< \brief (UART0) Status Register */ + #define REG_UART0_RHR (*(__I uint32_t*)0x400E0818U) /**< \brief (UART0) Receive Holding Register */ + #define REG_UART0_THR (*(__O uint32_t*)0x400E081CU) /**< \brief (UART0) Transmit Holding Register */ + #define REG_UART0_BRGR (*(__IO uint32_t*)0x400E0820U) /**< \brief (UART0) Baud Rate Generator Register */ + #define REG_UART0_CMPR (*(__IO uint32_t*)0x400E0824U) /**< \brief (UART0) Comparison Register */ + #define REG_UART0_WPMR (*(__IO uint32_t*)0x400E08E4U) /**< \brief (UART0) Write Protection Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_UART0_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_uart1.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_uart1.h new file mode 100644 index 00000000..4c93aa3c --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_uart1.h @@ -0,0 +1,60 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_UART1_INSTANCE_ +#define _SAMV71_UART1_INSTANCE_ + +/* ========== Register definition for UART1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_UART1_CR (0x400E0A00U) /**< \brief (UART1) Control Register */ + #define REG_UART1_MR (0x400E0A04U) /**< \brief (UART1) Mode Register */ + #define REG_UART1_IER (0x400E0A08U) /**< \brief (UART1) Interrupt Enable Register */ + #define REG_UART1_IDR (0x400E0A0CU) /**< \brief (UART1) Interrupt Disable Register */ + #define REG_UART1_IMR (0x400E0A10U) /**< \brief (UART1) Interrupt Mask Register */ + #define REG_UART1_SR (0x400E0A14U) /**< \brief (UART1) Status Register */ + #define REG_UART1_RHR (0x400E0A18U) /**< \brief (UART1) Receive Holding Register */ + #define REG_UART1_THR (0x400E0A1CU) /**< \brief (UART1) Transmit Holding Register */ + #define REG_UART1_BRGR (0x400E0A20U) /**< \brief (UART1) Baud Rate Generator Register */ + #define REG_UART1_CMPR (0x400E0A24U) /**< \brief (UART1) Comparison Register */ + #define REG_UART1_WPMR (0x400E0AE4U) /**< \brief (UART1) Write Protection Mode Register */ +#else + #define REG_UART1_CR (*(__O uint32_t*)0x400E0A00U) /**< \brief (UART1) Control Register */ + #define REG_UART1_MR (*(__IO uint32_t*)0x400E0A04U) /**< \brief (UART1) Mode Register */ + #define REG_UART1_IER (*(__O uint32_t*)0x400E0A08U) /**< \brief (UART1) Interrupt Enable Register */ + #define REG_UART1_IDR (*(__O uint32_t*)0x400E0A0CU) /**< \brief (UART1) Interrupt Disable Register */ + #define REG_UART1_IMR (*(__I uint32_t*)0x400E0A10U) /**< \brief (UART1) Interrupt Mask Register */ + #define REG_UART1_SR (*(__I uint32_t*)0x400E0A14U) /**< \brief (UART1) Status Register */ + #define REG_UART1_RHR (*(__I uint32_t*)0x400E0A18U) /**< \brief (UART1) Receive Holding Register */ + #define REG_UART1_THR (*(__O uint32_t*)0x400E0A1CU) /**< \brief (UART1) Transmit Holding Register */ + #define REG_UART1_BRGR (*(__IO uint32_t*)0x400E0A20U) /**< \brief (UART1) Baud Rate Generator Register */ + #define REG_UART1_CMPR (*(__IO uint32_t*)0x400E0A24U) /**< \brief (UART1) Comparison Register */ + #define REG_UART1_WPMR (*(__IO uint32_t*)0x400E0AE4U) /**< \brief (UART1) Write Protection Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_UART1_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_uart2.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_uart2.h new file mode 100644 index 00000000..78bb4036 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_uart2.h @@ -0,0 +1,60 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_UART2_INSTANCE_ +#define _SAMV71_UART2_INSTANCE_ + +/* ========== Register definition for UART2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_UART2_CR (0x400E1A00U) /**< \brief (UART2) Control Register */ + #define REG_UART2_MR (0x400E1A04U) /**< \brief (UART2) Mode Register */ + #define REG_UART2_IER (0x400E1A08U) /**< \brief (UART2) Interrupt Enable Register */ + #define REG_UART2_IDR (0x400E1A0CU) /**< \brief (UART2) Interrupt Disable Register */ + #define REG_UART2_IMR (0x400E1A10U) /**< \brief (UART2) Interrupt Mask Register */ + #define REG_UART2_SR (0x400E1A14U) /**< \brief (UART2) Status Register */ + #define REG_UART2_RHR (0x400E1A18U) /**< \brief (UART2) Receive Holding Register */ + #define REG_UART2_THR (0x400E1A1CU) /**< \brief (UART2) Transmit Holding Register */ + #define REG_UART2_BRGR (0x400E1A20U) /**< \brief (UART2) Baud Rate Generator Register */ + #define REG_UART2_CMPR (0x400E1A24U) /**< \brief (UART2) Comparison Register */ + #define REG_UART2_WPMR (0x400E1AE4U) /**< \brief (UART2) Write Protection Mode Register */ +#else + #define REG_UART2_CR (*(__O uint32_t*)0x400E1A00U) /**< \brief (UART2) Control Register */ + #define REG_UART2_MR (*(__IO uint32_t*)0x400E1A04U) /**< \brief (UART2) Mode Register */ + #define REG_UART2_IER (*(__O uint32_t*)0x400E1A08U) /**< \brief (UART2) Interrupt Enable Register */ + #define REG_UART2_IDR (*(__O uint32_t*)0x400E1A0CU) /**< \brief (UART2) Interrupt Disable Register */ + #define REG_UART2_IMR (*(__I uint32_t*)0x400E1A10U) /**< \brief (UART2) Interrupt Mask Register */ + #define REG_UART2_SR (*(__I uint32_t*)0x400E1A14U) /**< \brief (UART2) Status Register */ + #define REG_UART2_RHR (*(__I uint32_t*)0x400E1A18U) /**< \brief (UART2) Receive Holding Register */ + #define REG_UART2_THR (*(__O uint32_t*)0x400E1A1CU) /**< \brief (UART2) Transmit Holding Register */ + #define REG_UART2_BRGR (*(__IO uint32_t*)0x400E1A20U) /**< \brief (UART2) Baud Rate Generator Register */ + #define REG_UART2_CMPR (*(__IO uint32_t*)0x400E1A24U) /**< \brief (UART2) Comparison Register */ + #define REG_UART2_WPMR (*(__IO uint32_t*)0x400E1AE4U) /**< \brief (UART2) Write Protection Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_UART2_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_uart3.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_uart3.h new file mode 100644 index 00000000..56c1ffa4 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_uart3.h @@ -0,0 +1,60 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_UART3_INSTANCE_ +#define _SAMV71_UART3_INSTANCE_ + +/* ========== Register definition for UART3 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_UART3_CR (0x400E1C00U) /**< \brief (UART3) Control Register */ + #define REG_UART3_MR (0x400E1C04U) /**< \brief (UART3) Mode Register */ + #define REG_UART3_IER (0x400E1C08U) /**< \brief (UART3) Interrupt Enable Register */ + #define REG_UART3_IDR (0x400E1C0CU) /**< \brief (UART3) Interrupt Disable Register */ + #define REG_UART3_IMR (0x400E1C10U) /**< \brief (UART3) Interrupt Mask Register */ + #define REG_UART3_SR (0x400E1C14U) /**< \brief (UART3) Status Register */ + #define REG_UART3_RHR (0x400E1C18U) /**< \brief (UART3) Receive Holding Register */ + #define REG_UART3_THR (0x400E1C1CU) /**< \brief (UART3) Transmit Holding Register */ + #define REG_UART3_BRGR (0x400E1C20U) /**< \brief (UART3) Baud Rate Generator Register */ + #define REG_UART3_CMPR (0x400E1C24U) /**< \brief (UART3) Comparison Register */ + #define REG_UART3_WPMR (0x400E1CE4U) /**< \brief (UART3) Write Protection Mode Register */ +#else + #define REG_UART3_CR (*(__O uint32_t*)0x400E1C00U) /**< \brief (UART3) Control Register */ + #define REG_UART3_MR (*(__IO uint32_t*)0x400E1C04U) /**< \brief (UART3) Mode Register */ + #define REG_UART3_IER (*(__O uint32_t*)0x400E1C08U) /**< \brief (UART3) Interrupt Enable Register */ + #define REG_UART3_IDR (*(__O uint32_t*)0x400E1C0CU) /**< \brief (UART3) Interrupt Disable Register */ + #define REG_UART3_IMR (*(__I uint32_t*)0x400E1C10U) /**< \brief (UART3) Interrupt Mask Register */ + #define REG_UART3_SR (*(__I uint32_t*)0x400E1C14U) /**< \brief (UART3) Status Register */ + #define REG_UART3_RHR (*(__I uint32_t*)0x400E1C18U) /**< \brief (UART3) Receive Holding Register */ + #define REG_UART3_THR (*(__O uint32_t*)0x400E1C1CU) /**< \brief (UART3) Transmit Holding Register */ + #define REG_UART3_BRGR (*(__IO uint32_t*)0x400E1C20U) /**< \brief (UART3) Baud Rate Generator Register */ + #define REG_UART3_CMPR (*(__IO uint32_t*)0x400E1C24U) /**< \brief (UART3) Comparison Register */ + #define REG_UART3_WPMR (*(__IO uint32_t*)0x400E1CE4U) /**< \brief (UART3) Write Protection Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_UART3_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_uart4.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_uart4.h new file mode 100644 index 00000000..db5ce7ad --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_uart4.h @@ -0,0 +1,60 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_UART4_INSTANCE_ +#define _SAMV71_UART4_INSTANCE_ + +/* ========== Register definition for UART4 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_UART4_CR (0x400E1E00U) /**< \brief (UART4) Control Register */ + #define REG_UART4_MR (0x400E1E04U) /**< \brief (UART4) Mode Register */ + #define REG_UART4_IER (0x400E1E08U) /**< \brief (UART4) Interrupt Enable Register */ + #define REG_UART4_IDR (0x400E1E0CU) /**< \brief (UART4) Interrupt Disable Register */ + #define REG_UART4_IMR (0x400E1E10U) /**< \brief (UART4) Interrupt Mask Register */ + #define REG_UART4_SR (0x400E1E14U) /**< \brief (UART4) Status Register */ + #define REG_UART4_RHR (0x400E1E18U) /**< \brief (UART4) Receive Holding Register */ + #define REG_UART4_THR (0x400E1E1CU) /**< \brief (UART4) Transmit Holding Register */ + #define REG_UART4_BRGR (0x400E1E20U) /**< \brief (UART4) Baud Rate Generator Register */ + #define REG_UART4_CMPR (0x400E1E24U) /**< \brief (UART4) Comparison Register */ + #define REG_UART4_WPMR (0x400E1EE4U) /**< \brief (UART4) Write Protection Mode Register */ +#else + #define REG_UART4_CR (*(__O uint32_t*)0x400E1E00U) /**< \brief (UART4) Control Register */ + #define REG_UART4_MR (*(__IO uint32_t*)0x400E1E04U) /**< \brief (UART4) Mode Register */ + #define REG_UART4_IER (*(__O uint32_t*)0x400E1E08U) /**< \brief (UART4) Interrupt Enable Register */ + #define REG_UART4_IDR (*(__O uint32_t*)0x400E1E0CU) /**< \brief (UART4) Interrupt Disable Register */ + #define REG_UART4_IMR (*(__I uint32_t*)0x400E1E10U) /**< \brief (UART4) Interrupt Mask Register */ + #define REG_UART4_SR (*(__I uint32_t*)0x400E1E14U) /**< \brief (UART4) Status Register */ + #define REG_UART4_RHR (*(__I uint32_t*)0x400E1E18U) /**< \brief (UART4) Receive Holding Register */ + #define REG_UART4_THR (*(__O uint32_t*)0x400E1E1CU) /**< \brief (UART4) Transmit Holding Register */ + #define REG_UART4_BRGR (*(__IO uint32_t*)0x400E1E20U) /**< \brief (UART4) Baud Rate Generator Register */ + #define REG_UART4_CMPR (*(__IO uint32_t*)0x400E1E24U) /**< \brief (UART4) Comparison Register */ + #define REG_UART4_WPMR (*(__IO uint32_t*)0x400E1EE4U) /**< \brief (UART4) Write Protection Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_UART4_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_usart0.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_usart0.h new file mode 100644 index 00000000..742ca1f6 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_usart0.h @@ -0,0 +1,94 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_USART0_INSTANCE_ +#define _SAMV71_USART0_INSTANCE_ + +/* ========== Register definition for USART0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_USART0_CR (0x40024000U) /**< \brief (USART0) Control Register */ + #define REG_USART0_MR (0x40024004U) /**< \brief (USART0) Mode Register */ + #define REG_USART0_IER (0x40024008U) /**< \brief (USART0) Interrupt Enable Register */ + #define REG_USART0_IDR (0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */ + #define REG_USART0_IMR (0x40024010U) /**< \brief (USART0) Interrupt Mask Register */ + #define REG_USART0_CSR (0x40024014U) /**< \brief (USART0) Channel Status Register */ + #define REG_USART0_RHR (0x40024018U) /**< \brief (USART0) Receive Holding Register */ + #define REG_USART0_THR (0x4002401CU) /**< \brief (USART0) Transmit Holding Register */ + #define REG_USART0_BRGR (0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */ + #define REG_USART0_RTOR (0x40024024U) /**< \brief (USART0) Receiver Time-out Register */ + #define REG_USART0_TTGR (0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */ + #define REG_USART0_MAN (0x40024050U) /**< \brief (USART0) Manchester Configuration Register */ + #define REG_USART0_LINMR (0x40024054U) /**< \brief (USART0) LIN Mode Register */ + #define REG_USART0_LINIR (0x40024058U) /**< \brief (USART0) LIN Identifier Register */ + #define REG_USART0_LINBRR (0x4002405CU) /**< \brief (USART0) LIN Baud Rate Register */ + #define REG_USART0_LONMR (0x40024060U) /**< \brief (USART0) LON Mode Register */ + #define REG_USART0_LONPR (0x40024064U) /**< \brief (USART0) LON Preamble Register */ + #define REG_USART0_LONDL (0x40024068U) /**< \brief (USART0) LON Data Length Register */ + #define REG_USART0_LONL2HDR (0x4002406CU) /**< \brief (USART0) LON L2HDR Register */ + #define REG_USART0_LONBL (0x40024070U) /**< \brief (USART0) LON Backlog Register */ + #define REG_USART0_LONB1TX (0x40024074U) /**< \brief (USART0) LON Beta1 Tx Register */ + #define REG_USART0_LONB1RX (0x40024078U) /**< \brief (USART0) LON Beta1 Rx Register */ + #define REG_USART0_LONPRIO (0x4002407CU) /**< \brief (USART0) LON Priority Register */ + #define REG_USART0_IDTTX (0x40024080U) /**< \brief (USART0) LON IDT Tx Register */ + #define REG_USART0_IDTRX (0x40024084U) /**< \brief (USART0) LON IDT Rx Register */ + #define REG_USART0_ICDIFF (0x40024088U) /**< \brief (USART0) IC DIFF Register */ + #define REG_USART0_WPMR (0x400240E4U) /**< \brief (USART0) Write Protection Mode Register */ + #define REG_USART0_WPSR (0x400240E8U) /**< \brief (USART0) Write Protection Status Register */ +#else + #define REG_USART0_CR (*(__O uint32_t*)0x40024000U) /**< \brief (USART0) Control Register */ + #define REG_USART0_MR (*(__IO uint32_t*)0x40024004U) /**< \brief (USART0) Mode Register */ + #define REG_USART0_IER (*(__O uint32_t*)0x40024008U) /**< \brief (USART0) Interrupt Enable Register */ + #define REG_USART0_IDR (*(__O uint32_t*)0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */ + #define REG_USART0_IMR (*(__I uint32_t*)0x40024010U) /**< \brief (USART0) Interrupt Mask Register */ + #define REG_USART0_CSR (*(__I uint32_t*)0x40024014U) /**< \brief (USART0) Channel Status Register */ + #define REG_USART0_RHR (*(__I uint32_t*)0x40024018U) /**< \brief (USART0) Receive Holding Register */ + #define REG_USART0_THR (*(__O uint32_t*)0x4002401CU) /**< \brief (USART0) Transmit Holding Register */ + #define REG_USART0_BRGR (*(__IO uint32_t*)0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */ + #define REG_USART0_RTOR (*(__IO uint32_t*)0x40024024U) /**< \brief (USART0) Receiver Time-out Register */ + #define REG_USART0_TTGR (*(__IO uint32_t*)0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */ + #define REG_USART0_MAN (*(__IO uint32_t*)0x40024050U) /**< \brief (USART0) Manchester Configuration Register */ + #define REG_USART0_LINMR (*(__IO uint32_t*)0x40024054U) /**< \brief (USART0) LIN Mode Register */ + #define REG_USART0_LINIR (*(__IO uint32_t*)0x40024058U) /**< \brief (USART0) LIN Identifier Register */ + #define REG_USART0_LINBRR (*(__I uint32_t*)0x4002405CU) /**< \brief (USART0) LIN Baud Rate Register */ + #define REG_USART0_LONMR (*(__IO uint32_t*)0x40024060U) /**< \brief (USART0) LON Mode Register */ + #define REG_USART0_LONPR (*(__IO uint32_t*)0x40024064U) /**< \brief (USART0) LON Preamble Register */ + #define REG_USART0_LONDL (*(__IO uint32_t*)0x40024068U) /**< \brief (USART0) LON Data Length Register */ + #define REG_USART0_LONL2HDR (*(__IO uint32_t*)0x4002406CU) /**< \brief (USART0) LON L2HDR Register */ + #define REG_USART0_LONBL (*(__I uint32_t*)0x40024070U) /**< \brief (USART0) LON Backlog Register */ + #define REG_USART0_LONB1TX (*(__IO uint32_t*)0x40024074U) /**< \brief (USART0) LON Beta1 Tx Register */ + #define REG_USART0_LONB1RX (*(__IO uint32_t*)0x40024078U) /**< \brief (USART0) LON Beta1 Rx Register */ + #define REG_USART0_LONPRIO (*(__IO uint32_t*)0x4002407CU) /**< \brief (USART0) LON Priority Register */ + #define REG_USART0_IDTTX (*(__IO uint32_t*)0x40024080U) /**< \brief (USART0) LON IDT Tx Register */ + #define REG_USART0_IDTRX (*(__IO uint32_t*)0x40024084U) /**< \brief (USART0) LON IDT Rx Register */ + #define REG_USART0_ICDIFF (*(__IO uint32_t*)0x40024088U) /**< \brief (USART0) IC DIFF Register */ + #define REG_USART0_WPMR (*(__IO uint32_t*)0x400240E4U) /**< \brief (USART0) Write Protection Mode Register */ + #define REG_USART0_WPSR (*(__I uint32_t*)0x400240E8U) /**< \brief (USART0) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_USART0_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_usart1.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_usart1.h new file mode 100644 index 00000000..871f81c5 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_usart1.h @@ -0,0 +1,94 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_USART1_INSTANCE_ +#define _SAMV71_USART1_INSTANCE_ + +/* ========== Register definition for USART1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_USART1_CR (0x40028000U) /**< \brief (USART1) Control Register */ + #define REG_USART1_MR (0x40028004U) /**< \brief (USART1) Mode Register */ + #define REG_USART1_IER (0x40028008U) /**< \brief (USART1) Interrupt Enable Register */ + #define REG_USART1_IDR (0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */ + #define REG_USART1_IMR (0x40028010U) /**< \brief (USART1) Interrupt Mask Register */ + #define REG_USART1_CSR (0x40028014U) /**< \brief (USART1) Channel Status Register */ + #define REG_USART1_RHR (0x40028018U) /**< \brief (USART1) Receive Holding Register */ + #define REG_USART1_THR (0x4002801CU) /**< \brief (USART1) Transmit Holding Register */ + #define REG_USART1_BRGR (0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */ + #define REG_USART1_RTOR (0x40028024U) /**< \brief (USART1) Receiver Time-out Register */ + #define REG_USART1_TTGR (0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */ + #define REG_USART1_MAN (0x40028050U) /**< \brief (USART1) Manchester Configuration Register */ + #define REG_USART1_LINMR (0x40028054U) /**< \brief (USART1) LIN Mode Register */ + #define REG_USART1_LINIR (0x40028058U) /**< \brief (USART1) LIN Identifier Register */ + #define REG_USART1_LINBRR (0x4002805CU) /**< \brief (USART1) LIN Baud Rate Register */ + #define REG_USART1_LONMR (0x40028060U) /**< \brief (USART1) LON Mode Register */ + #define REG_USART1_LONPR (0x40028064U) /**< \brief (USART1) LON Preamble Register */ + #define REG_USART1_LONDL (0x40028068U) /**< \brief (USART1) LON Data Length Register */ + #define REG_USART1_LONL2HDR (0x4002806CU) /**< \brief (USART1) LON L2HDR Register */ + #define REG_USART1_LONBL (0x40028070U) /**< \brief (USART1) LON Backlog Register */ + #define REG_USART1_LONB1TX (0x40028074U) /**< \brief (USART1) LON Beta1 Tx Register */ + #define REG_USART1_LONB1RX (0x40028078U) /**< \brief (USART1) LON Beta1 Rx Register */ + #define REG_USART1_LONPRIO (0x4002807CU) /**< \brief (USART1) LON Priority Register */ + #define REG_USART1_IDTTX (0x40028080U) /**< \brief (USART1) LON IDT Tx Register */ + #define REG_USART1_IDTRX (0x40028084U) /**< \brief (USART1) LON IDT Rx Register */ + #define REG_USART1_ICDIFF (0x40028088U) /**< \brief (USART1) IC DIFF Register */ + #define REG_USART1_WPMR (0x400280E4U) /**< \brief (USART1) Write Protection Mode Register */ + #define REG_USART1_WPSR (0x400280E8U) /**< \brief (USART1) Write Protection Status Register */ +#else + #define REG_USART1_CR (*(__O uint32_t*)0x40028000U) /**< \brief (USART1) Control Register */ + #define REG_USART1_MR (*(__IO uint32_t*)0x40028004U) /**< \brief (USART1) Mode Register */ + #define REG_USART1_IER (*(__O uint32_t*)0x40028008U) /**< \brief (USART1) Interrupt Enable Register */ + #define REG_USART1_IDR (*(__O uint32_t*)0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */ + #define REG_USART1_IMR (*(__I uint32_t*)0x40028010U) /**< \brief (USART1) Interrupt Mask Register */ + #define REG_USART1_CSR (*(__I uint32_t*)0x40028014U) /**< \brief (USART1) Channel Status Register */ + #define REG_USART1_RHR (*(__I uint32_t*)0x40028018U) /**< \brief (USART1) Receive Holding Register */ + #define REG_USART1_THR (*(__O uint32_t*)0x4002801CU) /**< \brief (USART1) Transmit Holding Register */ + #define REG_USART1_BRGR (*(__IO uint32_t*)0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */ + #define REG_USART1_RTOR (*(__IO uint32_t*)0x40028024U) /**< \brief (USART1) Receiver Time-out Register */ + #define REG_USART1_TTGR (*(__IO uint32_t*)0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */ + #define REG_USART1_MAN (*(__IO uint32_t*)0x40028050U) /**< \brief (USART1) Manchester Configuration Register */ + #define REG_USART1_LINMR (*(__IO uint32_t*)0x40028054U) /**< \brief (USART1) LIN Mode Register */ + #define REG_USART1_LINIR (*(__IO uint32_t*)0x40028058U) /**< \brief (USART1) LIN Identifier Register */ + #define REG_USART1_LINBRR (*(__I uint32_t*)0x4002805CU) /**< \brief (USART1) LIN Baud Rate Register */ + #define REG_USART1_LONMR (*(__IO uint32_t*)0x40028060U) /**< \brief (USART1) LON Mode Register */ + #define REG_USART1_LONPR (*(__IO uint32_t*)0x40028064U) /**< \brief (USART1) LON Preamble Register */ + #define REG_USART1_LONDL (*(__IO uint32_t*)0x40028068U) /**< \brief (USART1) LON Data Length Register */ + #define REG_USART1_LONL2HDR (*(__IO uint32_t*)0x4002806CU) /**< \brief (USART1) LON L2HDR Register */ + #define REG_USART1_LONBL (*(__I uint32_t*)0x40028070U) /**< \brief (USART1) LON Backlog Register */ + #define REG_USART1_LONB1TX (*(__IO uint32_t*)0x40028074U) /**< \brief (USART1) LON Beta1 Tx Register */ + #define REG_USART1_LONB1RX (*(__IO uint32_t*)0x40028078U) /**< \brief (USART1) LON Beta1 Rx Register */ + #define REG_USART1_LONPRIO (*(__IO uint32_t*)0x4002807CU) /**< \brief (USART1) LON Priority Register */ + #define REG_USART1_IDTTX (*(__IO uint32_t*)0x40028080U) /**< \brief (USART1) LON IDT Tx Register */ + #define REG_USART1_IDTRX (*(__IO uint32_t*)0x40028084U) /**< \brief (USART1) LON IDT Rx Register */ + #define REG_USART1_ICDIFF (*(__IO uint32_t*)0x40028088U) /**< \brief (USART1) IC DIFF Register */ + #define REG_USART1_WPMR (*(__IO uint32_t*)0x400280E4U) /**< \brief (USART1) Write Protection Mode Register */ + #define REG_USART1_WPSR (*(__I uint32_t*)0x400280E8U) /**< \brief (USART1) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_USART1_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_usart2.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_usart2.h new file mode 100644 index 00000000..c97827e1 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_usart2.h @@ -0,0 +1,94 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_USART2_INSTANCE_ +#define _SAMV71_USART2_INSTANCE_ + +/* ========== Register definition for USART2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_USART2_CR (0x4002C000U) /**< \brief (USART2) Control Register */ + #define REG_USART2_MR (0x4002C004U) /**< \brief (USART2) Mode Register */ + #define REG_USART2_IER (0x4002C008U) /**< \brief (USART2) Interrupt Enable Register */ + #define REG_USART2_IDR (0x4002C00CU) /**< \brief (USART2) Interrupt Disable Register */ + #define REG_USART2_IMR (0x4002C010U) /**< \brief (USART2) Interrupt Mask Register */ + #define REG_USART2_CSR (0x4002C014U) /**< \brief (USART2) Channel Status Register */ + #define REG_USART2_RHR (0x4002C018U) /**< \brief (USART2) Receive Holding Register */ + #define REG_USART2_THR (0x4002C01CU) /**< \brief (USART2) Transmit Holding Register */ + #define REG_USART2_BRGR (0x4002C020U) /**< \brief (USART2) Baud Rate Generator Register */ + #define REG_USART2_RTOR (0x4002C024U) /**< \brief (USART2) Receiver Time-out Register */ + #define REG_USART2_TTGR (0x4002C028U) /**< \brief (USART2) Transmitter Timeguard Register */ + #define REG_USART2_MAN (0x4002C050U) /**< \brief (USART2) Manchester Configuration Register */ + #define REG_USART2_LINMR (0x4002C054U) /**< \brief (USART2) LIN Mode Register */ + #define REG_USART2_LINIR (0x4002C058U) /**< \brief (USART2) LIN Identifier Register */ + #define REG_USART2_LINBRR (0x4002C05CU) /**< \brief (USART2) LIN Baud Rate Register */ + #define REG_USART2_LONMR (0x4002C060U) /**< \brief (USART2) LON Mode Register */ + #define REG_USART2_LONPR (0x4002C064U) /**< \brief (USART2) LON Preamble Register */ + #define REG_USART2_LONDL (0x4002C068U) /**< \brief (USART2) LON Data Length Register */ + #define REG_USART2_LONL2HDR (0x4002C06CU) /**< \brief (USART2) LON L2HDR Register */ + #define REG_USART2_LONBL (0x4002C070U) /**< \brief (USART2) LON Backlog Register */ + #define REG_USART2_LONB1TX (0x4002C074U) /**< \brief (USART2) LON Beta1 Tx Register */ + #define REG_USART2_LONB1RX (0x4002C078U) /**< \brief (USART2) LON Beta1 Rx Register */ + #define REG_USART2_LONPRIO (0x4002C07CU) /**< \brief (USART2) LON Priority Register */ + #define REG_USART2_IDTTX (0x4002C080U) /**< \brief (USART2) LON IDT Tx Register */ + #define REG_USART2_IDTRX (0x4002C084U) /**< \brief (USART2) LON IDT Rx Register */ + #define REG_USART2_ICDIFF (0x4002C088U) /**< \brief (USART2) IC DIFF Register */ + #define REG_USART2_WPMR (0x4002C0E4U) /**< \brief (USART2) Write Protection Mode Register */ + #define REG_USART2_WPSR (0x4002C0E8U) /**< \brief (USART2) Write Protection Status Register */ +#else + #define REG_USART2_CR (*(__O uint32_t*)0x4002C000U) /**< \brief (USART2) Control Register */ + #define REG_USART2_MR (*(__IO uint32_t*)0x4002C004U) /**< \brief (USART2) Mode Register */ + #define REG_USART2_IER (*(__O uint32_t*)0x4002C008U) /**< \brief (USART2) Interrupt Enable Register */ + #define REG_USART2_IDR (*(__O uint32_t*)0x4002C00CU) /**< \brief (USART2) Interrupt Disable Register */ + #define REG_USART2_IMR (*(__I uint32_t*)0x4002C010U) /**< \brief (USART2) Interrupt Mask Register */ + #define REG_USART2_CSR (*(__I uint32_t*)0x4002C014U) /**< \brief (USART2) Channel Status Register */ + #define REG_USART2_RHR (*(__I uint32_t*)0x4002C018U) /**< \brief (USART2) Receive Holding Register */ + #define REG_USART2_THR (*(__O uint32_t*)0x4002C01CU) /**< \brief (USART2) Transmit Holding Register */ + #define REG_USART2_BRGR (*(__IO uint32_t*)0x4002C020U) /**< \brief (USART2) Baud Rate Generator Register */ + #define REG_USART2_RTOR (*(__IO uint32_t*)0x4002C024U) /**< \brief (USART2) Receiver Time-out Register */ + #define REG_USART2_TTGR (*(__IO uint32_t*)0x4002C028U) /**< \brief (USART2) Transmitter Timeguard Register */ + #define REG_USART2_MAN (*(__IO uint32_t*)0x4002C050U) /**< \brief (USART2) Manchester Configuration Register */ + #define REG_USART2_LINMR (*(__IO uint32_t*)0x4002C054U) /**< \brief (USART2) LIN Mode Register */ + #define REG_USART2_LINIR (*(__IO uint32_t*)0x4002C058U) /**< \brief (USART2) LIN Identifier Register */ + #define REG_USART2_LINBRR (*(__I uint32_t*)0x4002C05CU) /**< \brief (USART2) LIN Baud Rate Register */ + #define REG_USART2_LONMR (*(__IO uint32_t*)0x4002C060U) /**< \brief (USART2) LON Mode Register */ + #define REG_USART2_LONPR (*(__IO uint32_t*)0x4002C064U) /**< \brief (USART2) LON Preamble Register */ + #define REG_USART2_LONDL (*(__IO uint32_t*)0x4002C068U) /**< \brief (USART2) LON Data Length Register */ + #define REG_USART2_LONL2HDR (*(__IO uint32_t*)0x4002C06CU) /**< \brief (USART2) LON L2HDR Register */ + #define REG_USART2_LONBL (*(__I uint32_t*)0x4002C070U) /**< \brief (USART2) LON Backlog Register */ + #define REG_USART2_LONB1TX (*(__IO uint32_t*)0x4002C074U) /**< \brief (USART2) LON Beta1 Tx Register */ + #define REG_USART2_LONB1RX (*(__IO uint32_t*)0x4002C078U) /**< \brief (USART2) LON Beta1 Rx Register */ + #define REG_USART2_LONPRIO (*(__IO uint32_t*)0x4002C07CU) /**< \brief (USART2) LON Priority Register */ + #define REG_USART2_IDTTX (*(__IO uint32_t*)0x4002C080U) /**< \brief (USART2) LON IDT Tx Register */ + #define REG_USART2_IDTRX (*(__IO uint32_t*)0x4002C084U) /**< \brief (USART2) LON IDT Rx Register */ + #define REG_USART2_ICDIFF (*(__IO uint32_t*)0x4002C088U) /**< \brief (USART2) IC DIFF Register */ + #define REG_USART2_WPMR (*(__IO uint32_t*)0x4002C0E4U) /**< \brief (USART2) Write Protection Mode Register */ + #define REG_USART2_WPSR (*(__I uint32_t*)0x4002C0E8U) /**< \brief (USART2) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_USART2_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_usbhs.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_usbhs.h new file mode 100644 index 00000000..86a83f05 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_usbhs.h @@ -0,0 +1,240 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_USBHS_INSTANCE_ +#define _SAMV71_USBHS_INSTANCE_ + +/* ========== Register definition for USBHS peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_USBHS_DEVCTRL (0x40038000U) /**< \brief (USBHS) Device General Control Register */ + #define REG_USBHS_DEVISR (0x40038004U) /**< \brief (USBHS) Device Global Interrupt Status Register */ + #define REG_USBHS_DEVICR (0x40038008U) /**< \brief (USBHS) Device Global Interrupt Clear Register */ + #define REG_USBHS_DEVIFR (0x4003800CU) /**< \brief (USBHS) Device Global Interrupt Set Register */ + #define REG_USBHS_DEVIMR (0x40038010U) /**< \brief (USBHS) Device Global Interrupt Mask Register */ + #define REG_USBHS_DEVIDR (0x40038014U) /**< \brief (USBHS) Device Global Interrupt Disable Register */ + #define REG_USBHS_DEVIER (0x40038018U) /**< \brief (USBHS) Device Global Interrupt Enable Register */ + #define REG_USBHS_DEVEPT (0x4003801CU) /**< \brief (USBHS) Device Endpoint Register */ + #define REG_USBHS_DEVFNUM (0x40038020U) /**< \brief (USBHS) Device Frame Number Register */ + #define REG_USBHS_DEVEPTCFG (0x40038100U) /**< \brief (USBHS) Device Endpoint Configuration Register (n = 0) */ + #define REG_USBHS_DEVEPTISR (0x40038130U) /**< \brief (USBHS) Device Endpoint Status Register (n = 0) */ + #define REG_USBHS_DEVEPTICR (0x40038160U) /**< \brief (USBHS) Device Endpoint Clear Register (n = 0) */ + #define REG_USBHS_DEVEPTIFR (0x40038190U) /**< \brief (USBHS) Device Endpoint Set Register (n = 0) */ + #define REG_USBHS_DEVEPTIMR (0x400381C0U) /**< \brief (USBHS) Device Endpoint Mask Register (n = 0) */ + #define REG_USBHS_DEVEPTIER (0x400381F0U) /**< \brief (USBHS) Device Endpoint Enable Register (n = 0) */ + #define REG_USBHS_DEVEPTIDR (0x40038220U) /**< \brief (USBHS) Device Endpoint Disable Register (n = 0) */ + #define REG_USBHS_DEVDMANXTDSC1 (0x40038310U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) */ + #define REG_USBHS_DEVDMAADDRESS1 (0x40038314U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 1) */ + #define REG_USBHS_DEVDMACONTROL1 (0x40038318U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 1) */ + #define REG_USBHS_DEVDMASTATUS1 (0x4003831CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 1) */ + #define REG_USBHS_DEVDMANXTDSC2 (0x40038320U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 2) */ + #define REG_USBHS_DEVDMAADDRESS2 (0x40038324U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 2) */ + #define REG_USBHS_DEVDMACONTROL2 (0x40038328U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 2) */ + #define REG_USBHS_DEVDMASTATUS2 (0x4003832CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 2) */ + #define REG_USBHS_DEVDMANXTDSC3 (0x40038330U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 3) */ + #define REG_USBHS_DEVDMAADDRESS3 (0x40038334U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 3) */ + #define REG_USBHS_DEVDMACONTROL3 (0x40038338U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 3) */ + #define REG_USBHS_DEVDMASTATUS3 (0x4003833CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 3) */ + #define REG_USBHS_DEVDMANXTDSC4 (0x40038340U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 4) */ + #define REG_USBHS_DEVDMAADDRESS4 (0x40038344U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 4) */ + #define REG_USBHS_DEVDMACONTROL4 (0x40038348U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 4) */ + #define REG_USBHS_DEVDMASTATUS4 (0x4003834CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 4) */ + #define REG_USBHS_DEVDMANXTDSC5 (0x40038350U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 5) */ + #define REG_USBHS_DEVDMAADDRESS5 (0x40038354U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 5) */ + #define REG_USBHS_DEVDMACONTROL5 (0x40038358U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 5) */ + #define REG_USBHS_DEVDMASTATUS5 (0x4003835CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 5) */ + #define REG_USBHS_DEVDMANXTDSC6 (0x40038360U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 6) */ + #define REG_USBHS_DEVDMAADDRESS6 (0x40038364U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 6) */ + #define REG_USBHS_DEVDMACONTROL6 (0x40038368U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 6) */ + #define REG_USBHS_DEVDMASTATUS6 (0x4003836CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 6) */ + #define REG_USBHS_DEVDMANXTDSC7 (0x40038370U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 7) */ + #define REG_USBHS_DEVDMAADDRESS7 (0x40038374U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 7) */ + #define REG_USBHS_DEVDMACONTROL7 (0x40038378U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 7) */ + #define REG_USBHS_DEVDMASTATUS7 (0x4003837CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 7) */ + #define REG_USBHS_HSTCTRL (0x40038400U) /**< \brief (USBHS) Host General Control Register */ + #define REG_USBHS_HSTISR (0x40038404U) /**< \brief (USBHS) Host Global Interrupt Status Register */ + #define REG_USBHS_HSTICR (0x40038408U) /**< \brief (USBHS) Host Global Interrupt Clear Register */ + #define REG_USBHS_HSTIFR (0x4003840CU) /**< \brief (USBHS) Host Global Interrupt Set Register */ + #define REG_USBHS_HSTIMR (0x40038410U) /**< \brief (USBHS) Host Global Interrupt Mask Register */ + #define REG_USBHS_HSTIDR (0x40038414U) /**< \brief (USBHS) Host Global Interrupt Disable Register */ + #define REG_USBHS_HSTIER (0x40038418U) /**< \brief (USBHS) Host Global Interrupt Enable Register */ + #define REG_USBHS_HSTPIP (0x4003841CU) /**< \brief (USBHS) Host Pipe Register */ + #define REG_USBHS_HSTFNUM (0x40038420U) /**< \brief (USBHS) Host Frame Number Register */ + #define REG_USBHS_HSTADDR1 (0x40038424U) /**< \brief (USBHS) Host Address 1 Register */ + #define REG_USBHS_HSTADDR2 (0x40038428U) /**< \brief (USBHS) Host Address 2 Register */ + #define REG_USBHS_HSTADDR3 (0x4003842CU) /**< \brief (USBHS) Host Address 3 Register */ + #define REG_USBHS_HSTPIPCFG (0x40038500U) /**< \brief (USBHS) Host Pipe Configuration Register (n = 0) */ + #define REG_USBHS_HSTPIPISR (0x40038530U) /**< \brief (USBHS) Host Pipe Status Register (n = 0) */ + #define REG_USBHS_HSTPIPICR (0x40038560U) /**< \brief (USBHS) Host Pipe Clear Register (n = 0) */ + #define REG_USBHS_HSTPIPIFR (0x40038590U) /**< \brief (USBHS) Host Pipe Set Register (n = 0) */ + #define REG_USBHS_HSTPIPIMR (0x400385C0U) /**< \brief (USBHS) Host Pipe Mask Register (n = 0) */ + #define REG_USBHS_HSTPIPIER (0x400385F0U) /**< \brief (USBHS) Host Pipe Enable Register (n = 0) */ + #define REG_USBHS_HSTPIPIDR (0x40038620U) /**< \brief (USBHS) Host Pipe Disable Register (n = 0) */ + #define REG_USBHS_HSTPIPINRQ (0x40038650U) /**< \brief (USBHS) Host Pipe IN Request Register (n = 0) */ + #define REG_USBHS_HSTPIPERR (0x40038680U) /**< \brief (USBHS) Host Pipe Error Register (n = 0) */ + #define REG_USBHS_HSTDMANXTDSC1 (0x40038710U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) */ + #define REG_USBHS_HSTDMAADDRESS1 (0x40038714U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 1) */ + #define REG_USBHS_HSTDMACONTROL1 (0x40038718U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 1) */ + #define REG_USBHS_HSTDMASTATUS1 (0x4003871CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 1) */ + #define REG_USBHS_HSTDMANXTDSC2 (0x40038720U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 2) */ + #define REG_USBHS_HSTDMAADDRESS2 (0x40038724U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 2) */ + #define REG_USBHS_HSTDMACONTROL2 (0x40038728U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 2) */ + #define REG_USBHS_HSTDMASTATUS2 (0x4003872CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 2) */ + #define REG_USBHS_HSTDMANXTDSC3 (0x40038730U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 3) */ + #define REG_USBHS_HSTDMAADDRESS3 (0x40038734U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 3) */ + #define REG_USBHS_HSTDMACONTROL3 (0x40038738U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 3) */ + #define REG_USBHS_HSTDMASTATUS3 (0x4003873CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 3) */ + #define REG_USBHS_HSTDMANXTDSC4 (0x40038740U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 4) */ + #define REG_USBHS_HSTDMAADDRESS4 (0x40038744U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 4) */ + #define REG_USBHS_HSTDMACONTROL4 (0x40038748U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 4) */ + #define REG_USBHS_HSTDMASTATUS4 (0x4003874CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 4) */ + #define REG_USBHS_HSTDMANXTDSC5 (0x40038750U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 5) */ + #define REG_USBHS_HSTDMAADDRESS5 (0x40038754U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 5) */ + #define REG_USBHS_HSTDMACONTROL5 (0x40038758U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 5) */ + #define REG_USBHS_HSTDMASTATUS5 (0x4003875CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 5) */ + #define REG_USBHS_HSTDMANXTDSC6 (0x40038760U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 6) */ + #define REG_USBHS_HSTDMAADDRESS6 (0x40038764U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 6) */ + #define REG_USBHS_HSTDMACONTROL6 (0x40038768U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 6) */ + #define REG_USBHS_HSTDMASTATUS6 (0x4003876CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 6) */ + #define REG_USBHS_HSTDMANXTDSC7 (0x40038770U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 7) */ + #define REG_USBHS_HSTDMAADDRESS7 (0x40038774U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 7) */ + #define REG_USBHS_HSTDMACONTROL7 (0x40038778U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 7) */ + #define REG_USBHS_HSTDMASTATUS7 (0x4003877CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 7) */ + #define REG_USBHS_CTRL (0x40038800U) /**< \brief (USBHS) General Control Register */ + #define REG_USBHS_SR (0x40038804U) /**< \brief (USBHS) General Status Register */ + #define REG_USBHS_SCR (0x40038808U) /**< \brief (USBHS) General Status Clear Register */ + #define REG_USBHS_SFR (0x4003880CU) /**< \brief (USBHS) General Status Set Register */ + #define REG_USBHS_TSTA1 (0x40038810U) /**< \brief (USBHS) General Test A1 Register */ + #define REG_USBHS_TSTA2 (0x40038814U) /**< \brief (USBHS) General Test A2 Register */ + #define REG_USBHS_VERSION (0x40038818U) /**< \brief (USBHS) General Version Register */ + #define REG_USBHS_FSM (0x4003882CU) /**< \brief (USBHS) General Finite State Machine Register */ +#else + #define REG_USBHS_DEVCTRL (*(__IO uint32_t*)0x40038000U) /**< \brief (USBHS) Device General Control Register */ + #define REG_USBHS_DEVISR (*(__I uint32_t*)0x40038004U) /**< \brief (USBHS) Device Global Interrupt Status Register */ + #define REG_USBHS_DEVICR (*(__O uint32_t*)0x40038008U) /**< \brief (USBHS) Device Global Interrupt Clear Register */ + #define REG_USBHS_DEVIFR (*(__O uint32_t*)0x4003800CU) /**< \brief (USBHS) Device Global Interrupt Set Register */ + #define REG_USBHS_DEVIMR (*(__I uint32_t*)0x40038010U) /**< \brief (USBHS) Device Global Interrupt Mask Register */ + #define REG_USBHS_DEVIDR (*(__O uint32_t*)0x40038014U) /**< \brief (USBHS) Device Global Interrupt Disable Register */ + #define REG_USBHS_DEVIER (*(__O uint32_t*)0x40038018U) /**< \brief (USBHS) Device Global Interrupt Enable Register */ + #define REG_USBHS_DEVEPT (*(__IO uint32_t*)0x4003801CU) /**< \brief (USBHS) Device Endpoint Register */ + #define REG_USBHS_DEVFNUM (*(__I uint32_t*)0x40038020U) /**< \brief (USBHS) Device Frame Number Register */ + #define REG_USBHS_DEVEPTCFG (*(__IO uint32_t*)0x40038100U) /**< \brief (USBHS) Device Endpoint Configuration Register (n = 0) */ + #define REG_USBHS_DEVEPTISR (*(__I uint32_t*)0x40038130U) /**< \brief (USBHS) Device Endpoint Status Register (n = 0) */ + #define REG_USBHS_DEVEPTICR (*(__O uint32_t*)0x40038160U) /**< \brief (USBHS) Device Endpoint Clear Register (n = 0) */ + #define REG_USBHS_DEVEPTIFR (*(__O uint32_t*)0x40038190U) /**< \brief (USBHS) Device Endpoint Set Register (n = 0) */ + #define REG_USBHS_DEVEPTIMR (*(__I uint32_t*)0x400381C0U) /**< \brief (USBHS) Device Endpoint Mask Register (n = 0) */ + #define REG_USBHS_DEVEPTIER (*(__O uint32_t*)0x400381F0U) /**< \brief (USBHS) Device Endpoint Enable Register (n = 0) */ + #define REG_USBHS_DEVEPTIDR (*(__O uint32_t*)0x40038220U) /**< \brief (USBHS) Device Endpoint Disable Register (n = 0) */ + #define REG_USBHS_DEVDMANXTDSC1 (*(__IO uint32_t*)0x40038310U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) */ + #define REG_USBHS_DEVDMAADDRESS1 (*(__IO uint32_t*)0x40038314U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 1) */ + #define REG_USBHS_DEVDMACONTROL1 (*(__IO uint32_t*)0x40038318U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 1) */ + #define REG_USBHS_DEVDMASTATUS1 (*(__IO uint32_t*)0x4003831CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 1) */ + #define REG_USBHS_DEVDMANXTDSC2 (*(__IO uint32_t*)0x40038320U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 2) */ + #define REG_USBHS_DEVDMAADDRESS2 (*(__IO uint32_t*)0x40038324U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 2) */ + #define REG_USBHS_DEVDMACONTROL2 (*(__IO uint32_t*)0x40038328U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 2) */ + #define REG_USBHS_DEVDMASTATUS2 (*(__IO uint32_t*)0x4003832CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 2) */ + #define REG_USBHS_DEVDMANXTDSC3 (*(__IO uint32_t*)0x40038330U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 3) */ + #define REG_USBHS_DEVDMAADDRESS3 (*(__IO uint32_t*)0x40038334U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 3) */ + #define REG_USBHS_DEVDMACONTROL3 (*(__IO uint32_t*)0x40038338U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 3) */ + #define REG_USBHS_DEVDMASTATUS3 (*(__IO uint32_t*)0x4003833CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 3) */ + #define REG_USBHS_DEVDMANXTDSC4 (*(__IO uint32_t*)0x40038340U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 4) */ + #define REG_USBHS_DEVDMAADDRESS4 (*(__IO uint32_t*)0x40038344U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 4) */ + #define REG_USBHS_DEVDMACONTROL4 (*(__IO uint32_t*)0x40038348U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 4) */ + #define REG_USBHS_DEVDMASTATUS4 (*(__IO uint32_t*)0x4003834CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 4) */ + #define REG_USBHS_DEVDMANXTDSC5 (*(__IO uint32_t*)0x40038350U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 5) */ + #define REG_USBHS_DEVDMAADDRESS5 (*(__IO uint32_t*)0x40038354U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 5) */ + #define REG_USBHS_DEVDMACONTROL5 (*(__IO uint32_t*)0x40038358U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 5) */ + #define REG_USBHS_DEVDMASTATUS5 (*(__IO uint32_t*)0x4003835CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 5) */ + #define REG_USBHS_DEVDMANXTDSC6 (*(__IO uint32_t*)0x40038360U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 6) */ + #define REG_USBHS_DEVDMAADDRESS6 (*(__IO uint32_t*)0x40038364U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 6) */ + #define REG_USBHS_DEVDMACONTROL6 (*(__IO uint32_t*)0x40038368U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 6) */ + #define REG_USBHS_DEVDMASTATUS6 (*(__IO uint32_t*)0x4003836CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 6) */ + #define REG_USBHS_DEVDMANXTDSC7 (*(__IO uint32_t*)0x40038370U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 7) */ + #define REG_USBHS_DEVDMAADDRESS7 (*(__IO uint32_t*)0x40038374U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 7) */ + #define REG_USBHS_DEVDMACONTROL7 (*(__IO uint32_t*)0x40038378U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 7) */ + #define REG_USBHS_DEVDMASTATUS7 (*(__IO uint32_t*)0x4003837CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 7) */ + #define REG_USBHS_HSTCTRL (*(__IO uint32_t*)0x40038400U) /**< \brief (USBHS) Host General Control Register */ + #define REG_USBHS_HSTISR (*(__I uint32_t*)0x40038404U) /**< \brief (USBHS) Host Global Interrupt Status Register */ + #define REG_USBHS_HSTICR (*(__O uint32_t*)0x40038408U) /**< \brief (USBHS) Host Global Interrupt Clear Register */ + #define REG_USBHS_HSTIFR (*(__O uint32_t*)0x4003840CU) /**< \brief (USBHS) Host Global Interrupt Set Register */ + #define REG_USBHS_HSTIMR (*(__I uint32_t*)0x40038410U) /**< \brief (USBHS) Host Global Interrupt Mask Register */ + #define REG_USBHS_HSTIDR (*(__O uint32_t*)0x40038414U) /**< \brief (USBHS) Host Global Interrupt Disable Register */ + #define REG_USBHS_HSTIER (*(__O uint32_t*)0x40038418U) /**< \brief (USBHS) Host Global Interrupt Enable Register */ + #define REG_USBHS_HSTPIP (*(__IO uint32_t*)0x4003841CU) /**< \brief (USBHS) Host Pipe Register */ + #define REG_USBHS_HSTFNUM (*(__IO uint32_t*)0x40038420U) /**< \brief (USBHS) Host Frame Number Register */ + #define REG_USBHS_HSTADDR1 (*(__IO uint32_t*)0x40038424U) /**< \brief (USBHS) Host Address 1 Register */ + #define REG_USBHS_HSTADDR2 (*(__IO uint32_t*)0x40038428U) /**< \brief (USBHS) Host Address 2 Register */ + #define REG_USBHS_HSTADDR3 (*(__IO uint32_t*)0x4003842CU) /**< \brief (USBHS) Host Address 3 Register */ + #define REG_USBHS_HSTPIPCFG (*(__IO uint32_t*)0x40038500U) /**< \brief (USBHS) Host Pipe Configuration Register (n = 0) */ + #define REG_USBHS_HSTPIPISR (*(__I uint32_t*)0x40038530U) /**< \brief (USBHS) Host Pipe Status Register (n = 0) */ + #define REG_USBHS_HSTPIPICR (*(__O uint32_t*)0x40038560U) /**< \brief (USBHS) Host Pipe Clear Register (n = 0) */ + #define REG_USBHS_HSTPIPIFR (*(__O uint32_t*)0x40038590U) /**< \brief (USBHS) Host Pipe Set Register (n = 0) */ + #define REG_USBHS_HSTPIPIMR (*(__I uint32_t*)0x400385C0U) /**< \brief (USBHS) Host Pipe Mask Register (n = 0) */ + #define REG_USBHS_HSTPIPIER (*(__O uint32_t*)0x400385F0U) /**< \brief (USBHS) Host Pipe Enable Register (n = 0) */ + #define REG_USBHS_HSTPIPIDR (*(__O uint32_t*)0x40038620U) /**< \brief (USBHS) Host Pipe Disable Register (n = 0) */ + #define REG_USBHS_HSTPIPINRQ (*(__IO uint32_t*)0x40038650U) /**< \brief (USBHS) Host Pipe IN Request Register (n = 0) */ + #define REG_USBHS_HSTPIPERR (*(__IO uint32_t*)0x40038680U) /**< \brief (USBHS) Host Pipe Error Register (n = 0) */ + #define REG_USBHS_HSTDMANXTDSC1 (*(__IO uint32_t*)0x40038710U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) */ + #define REG_USBHS_HSTDMAADDRESS1 (*(__IO uint32_t*)0x40038714U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 1) */ + #define REG_USBHS_HSTDMACONTROL1 (*(__IO uint32_t*)0x40038718U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 1) */ + #define REG_USBHS_HSTDMASTATUS1 (*(__IO uint32_t*)0x4003871CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 1) */ + #define REG_USBHS_HSTDMANXTDSC2 (*(__IO uint32_t*)0x40038720U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 2) */ + #define REG_USBHS_HSTDMAADDRESS2 (*(__IO uint32_t*)0x40038724U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 2) */ + #define REG_USBHS_HSTDMACONTROL2 (*(__IO uint32_t*)0x40038728U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 2) */ + #define REG_USBHS_HSTDMASTATUS2 (*(__IO uint32_t*)0x4003872CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 2) */ + #define REG_USBHS_HSTDMANXTDSC3 (*(__IO uint32_t*)0x40038730U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 3) */ + #define REG_USBHS_HSTDMAADDRESS3 (*(__IO uint32_t*)0x40038734U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 3) */ + #define REG_USBHS_HSTDMACONTROL3 (*(__IO uint32_t*)0x40038738U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 3) */ + #define REG_USBHS_HSTDMASTATUS3 (*(__IO uint32_t*)0x4003873CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 3) */ + #define REG_USBHS_HSTDMANXTDSC4 (*(__IO uint32_t*)0x40038740U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 4) */ + #define REG_USBHS_HSTDMAADDRESS4 (*(__IO uint32_t*)0x40038744U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 4) */ + #define REG_USBHS_HSTDMACONTROL4 (*(__IO uint32_t*)0x40038748U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 4) */ + #define REG_USBHS_HSTDMASTATUS4 (*(__IO uint32_t*)0x4003874CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 4) */ + #define REG_USBHS_HSTDMANXTDSC5 (*(__IO uint32_t*)0x40038750U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 5) */ + #define REG_USBHS_HSTDMAADDRESS5 (*(__IO uint32_t*)0x40038754U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 5) */ + #define REG_USBHS_HSTDMACONTROL5 (*(__IO uint32_t*)0x40038758U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 5) */ + #define REG_USBHS_HSTDMASTATUS5 (*(__IO uint32_t*)0x4003875CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 5) */ + #define REG_USBHS_HSTDMANXTDSC6 (*(__IO uint32_t*)0x40038760U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 6) */ + #define REG_USBHS_HSTDMAADDRESS6 (*(__IO uint32_t*)0x40038764U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 6) */ + #define REG_USBHS_HSTDMACONTROL6 (*(__IO uint32_t*)0x40038768U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 6) */ + #define REG_USBHS_HSTDMASTATUS6 (*(__IO uint32_t*)0x4003876CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 6) */ + #define REG_USBHS_HSTDMANXTDSC7 (*(__IO uint32_t*)0x40038770U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 7) */ + #define REG_USBHS_HSTDMAADDRESS7 (*(__IO uint32_t*)0x40038774U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 7) */ + #define REG_USBHS_HSTDMACONTROL7 (*(__IO uint32_t*)0x40038778U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 7) */ + #define REG_USBHS_HSTDMASTATUS7 (*(__IO uint32_t*)0x4003877CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 7) */ + #define REG_USBHS_CTRL (*(__IO uint32_t*)0x40038800U) /**< \brief (USBHS) General Control Register */ + #define REG_USBHS_SR (*(__I uint32_t*)0x40038804U) /**< \brief (USBHS) General Status Register */ + #define REG_USBHS_SCR (*(__O uint32_t*)0x40038808U) /**< \brief (USBHS) General Status Clear Register */ + #define REG_USBHS_SFR (*(__O uint32_t*)0x4003880CU) /**< \brief (USBHS) General Status Set Register */ + #define REG_USBHS_TSTA1 (*(__IO uint32_t*)0x40038810U) /**< \brief (USBHS) General Test A1 Register */ + #define REG_USBHS_TSTA2 (*(__IO uint32_t*)0x40038814U) /**< \brief (USBHS) General Test A2 Register */ + #define REG_USBHS_VERSION (*(__I uint32_t*)0x40038818U) /**< \brief (USBHS) General Version Register */ + #define REG_USBHS_FSM (*(__I uint32_t*)0x4003882CU) /**< \brief (USBHS) General Finite State Machine Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_USBHS_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_utmi.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_utmi.h new file mode 100644 index 00000000..f5b5af86 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_utmi.h @@ -0,0 +1,42 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_UTMI_INSTANCE_ +#define _SAMV71_UTMI_INSTANCE_ + +/* ========== Register definition for UTMI peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_UTMI_OHCIICR (0x400E0410U) /**< \brief (UTMI) OHCI Interrupt Configuration Register */ + #define REG_UTMI_CKTRIM (0x400E0430U) /**< \brief (UTMI) UTMI Clock Trimming Register */ +#else + #define REG_UTMI_OHCIICR (*(__IO uint32_t*)0x400E0410U) /**< \brief (UTMI) OHCI Interrupt Configuration Register */ + #define REG_UTMI_CKTRIM (*(__IO uint32_t*)0x400E0430U) /**< \brief (UTMI) UTMI Clock Trimming Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_UTMI_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_wdt.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_wdt.h new file mode 100644 index 00000000..4bbc0aae --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_wdt.h @@ -0,0 +1,44 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_WDT_INSTANCE_ +#define _SAMV71_WDT_INSTANCE_ + +/* ========== Register definition for WDT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_WDT_CR (0x400E1850U) /**< \brief (WDT) Control Register */ + #define REG_WDT_MR (0x400E1854U) /**< \brief (WDT) Mode Register */ + #define REG_WDT_SR (0x400E1858U) /**< \brief (WDT) Status Register */ +#else + #define REG_WDT_CR (*(__O uint32_t*)0x400E1850U) /**< \brief (WDT) Control Register */ + #define REG_WDT_MR (*(__IO uint32_t*)0x400E1854U) /**< \brief (WDT) Mode Register */ + #define REG_WDT_SR (*(__I uint32_t*)0x400E1858U) /**< \brief (WDT) Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_WDT_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_xdmac.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_xdmac.h new file mode 100644 index 00000000..65087654 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/instance/instance_xdmac.h @@ -0,0 +1,744 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_XDMAC_INSTANCE_ +#define _SAMV71_XDMAC_INSTANCE_ + +/* ========== Register definition for XDMAC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_XDMAC_GTYPE (0x40078000U) /**< \brief (XDMAC) Global Type Register */ + #define REG_XDMAC_GCFG (0x40078004U) /**< \brief (XDMAC) Global Configuration Register */ + #define REG_XDMAC_GWAC (0x40078008U) /**< \brief (XDMAC) Global Weighted Arbiter Configuration Register */ + #define REG_XDMAC_GIE (0x4007800CU) /**< \brief (XDMAC) Global Interrupt Enable Register */ + #define REG_XDMAC_GID (0x40078010U) /**< \brief (XDMAC) Global Interrupt Disable Register */ + #define REG_XDMAC_GIM (0x40078014U) /**< \brief (XDMAC) Global Interrupt Mask Register */ + #define REG_XDMAC_GIS (0x40078018U) /**< \brief (XDMAC) Global Interrupt Status Register */ + #define REG_XDMAC_GE (0x4007801CU) /**< \brief (XDMAC) Global Channel Enable Register */ + #define REG_XDMAC_GD (0x40078020U) /**< \brief (XDMAC) Global Channel Disable Register */ + #define REG_XDMAC_GS (0x40078024U) /**< \brief (XDMAC) Global Channel Status Register */ + #define REG_XDMAC_GRS (0x40078028U) /**< \brief (XDMAC) Global Channel Read Suspend Register */ + #define REG_XDMAC_GWS (0x4007802CU) /**< \brief (XDMAC) Global Channel Write Suspend Register */ + #define REG_XDMAC_GRWS (0x40078030U) /**< \brief (XDMAC) Global Channel Read Write Suspend Register */ + #define REG_XDMAC_GRWR (0x40078034U) /**< \brief (XDMAC) Global Channel Read Write Resume Register */ + #define REG_XDMAC_GSWR (0x40078038U) /**< \brief (XDMAC) Global Channel Software Request Register */ + #define REG_XDMAC_GSWS (0x4007803CU) /**< \brief (XDMAC) Global Channel Software Request Status Register */ + #define REG_XDMAC_GSWF (0x40078040U) /**< \brief (XDMAC) Global Channel Software Flush Request Register */ + #define REG_XDMAC_CIE0 (0x40078050U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 0) */ + #define REG_XDMAC_CID0 (0x40078054U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 0) */ + #define REG_XDMAC_CIM0 (0x40078058U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 0) */ + #define REG_XDMAC_CIS0 (0x4007805CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 0) */ + #define REG_XDMAC_CSA0 (0x40078060U) /**< \brief (XDMAC) Channel Source Address Register (chid = 0) */ + #define REG_XDMAC_CDA0 (0x40078064U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 0) */ + #define REG_XDMAC_CNDA0 (0x40078068U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 0) */ + #define REG_XDMAC_CNDC0 (0x4007806CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 0) */ + #define REG_XDMAC_CUBC0 (0x40078070U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 0) */ + #define REG_XDMAC_CBC0 (0x40078074U) /**< \brief (XDMAC) Channel Block Control Register (chid = 0) */ + #define REG_XDMAC_CC0 (0x40078078U) /**< \brief (XDMAC) Channel Configuration Register (chid = 0) */ + #define REG_XDMAC_CDS_MSP0 (0x4007807CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) */ + #define REG_XDMAC_CSUS0 (0x40078080U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 0) */ + #define REG_XDMAC_CDUS0 (0x40078084U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 0) */ + #define REG_XDMAC_CIE1 (0x40078090U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 1) */ + #define REG_XDMAC_CID1 (0x40078094U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 1) */ + #define REG_XDMAC_CIM1 (0x40078098U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 1) */ + #define REG_XDMAC_CIS1 (0x4007809CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 1) */ + #define REG_XDMAC_CSA1 (0x400780A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 1) */ + #define REG_XDMAC_CDA1 (0x400780A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 1) */ + #define REG_XDMAC_CNDA1 (0x400780A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 1) */ + #define REG_XDMAC_CNDC1 (0x400780ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 1) */ + #define REG_XDMAC_CUBC1 (0x400780B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 1) */ + #define REG_XDMAC_CBC1 (0x400780B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 1) */ + #define REG_XDMAC_CC1 (0x400780B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 1) */ + #define REG_XDMAC_CDS_MSP1 (0x400780BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 1) */ + #define REG_XDMAC_CSUS1 (0x400780C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 1) */ + #define REG_XDMAC_CDUS1 (0x400780C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 1) */ + #define REG_XDMAC_CIE2 (0x400780D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 2) */ + #define REG_XDMAC_CID2 (0x400780D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 2) */ + #define REG_XDMAC_CIM2 (0x400780D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 2) */ + #define REG_XDMAC_CIS2 (0x400780DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 2) */ + #define REG_XDMAC_CSA2 (0x400780E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 2) */ + #define REG_XDMAC_CDA2 (0x400780E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 2) */ + #define REG_XDMAC_CNDA2 (0x400780E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 2) */ + #define REG_XDMAC_CNDC2 (0x400780ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 2) */ + #define REG_XDMAC_CUBC2 (0x400780F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 2) */ + #define REG_XDMAC_CBC2 (0x400780F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 2) */ + #define REG_XDMAC_CC2 (0x400780F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 2) */ + #define REG_XDMAC_CDS_MSP2 (0x400780FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 2) */ + #define REG_XDMAC_CSUS2 (0x40078100U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 2) */ + #define REG_XDMAC_CDUS2 (0x40078104U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 2) */ + #define REG_XDMAC_CIE3 (0x40078110U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 3) */ + #define REG_XDMAC_CID3 (0x40078114U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 3) */ + #define REG_XDMAC_CIM3 (0x40078118U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 3) */ + #define REG_XDMAC_CIS3 (0x4007811CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 3) */ + #define REG_XDMAC_CSA3 (0x40078120U) /**< \brief (XDMAC) Channel Source Address Register (chid = 3) */ + #define REG_XDMAC_CDA3 (0x40078124U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 3) */ + #define REG_XDMAC_CNDA3 (0x40078128U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 3) */ + #define REG_XDMAC_CNDC3 (0x4007812CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 3) */ + #define REG_XDMAC_CUBC3 (0x40078130U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 3) */ + #define REG_XDMAC_CBC3 (0x40078134U) /**< \brief (XDMAC) Channel Block Control Register (chid = 3) */ + #define REG_XDMAC_CC3 (0x40078138U) /**< \brief (XDMAC) Channel Configuration Register (chid = 3) */ + #define REG_XDMAC_CDS_MSP3 (0x4007813CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 3) */ + #define REG_XDMAC_CSUS3 (0x40078140U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 3) */ + #define REG_XDMAC_CDUS3 (0x40078144U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 3) */ + #define REG_XDMAC_CIE4 (0x40078150U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 4) */ + #define REG_XDMAC_CID4 (0x40078154U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 4) */ + #define REG_XDMAC_CIM4 (0x40078158U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 4) */ + #define REG_XDMAC_CIS4 (0x4007815CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 4) */ + #define REG_XDMAC_CSA4 (0x40078160U) /**< \brief (XDMAC) Channel Source Address Register (chid = 4) */ + #define REG_XDMAC_CDA4 (0x40078164U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 4) */ + #define REG_XDMAC_CNDA4 (0x40078168U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 4) */ + #define REG_XDMAC_CNDC4 (0x4007816CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 4) */ + #define REG_XDMAC_CUBC4 (0x40078170U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 4) */ + #define REG_XDMAC_CBC4 (0x40078174U) /**< \brief (XDMAC) Channel Block Control Register (chid = 4) */ + #define REG_XDMAC_CC4 (0x40078178U) /**< \brief (XDMAC) Channel Configuration Register (chid = 4) */ + #define REG_XDMAC_CDS_MSP4 (0x4007817CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 4) */ + #define REG_XDMAC_CSUS4 (0x40078180U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 4) */ + #define REG_XDMAC_CDUS4 (0x40078184U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 4) */ + #define REG_XDMAC_CIE5 (0x40078190U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 5) */ + #define REG_XDMAC_CID5 (0x40078194U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 5) */ + #define REG_XDMAC_CIM5 (0x40078198U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 5) */ + #define REG_XDMAC_CIS5 (0x4007819CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 5) */ + #define REG_XDMAC_CSA5 (0x400781A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 5) */ + #define REG_XDMAC_CDA5 (0x400781A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 5) */ + #define REG_XDMAC_CNDA5 (0x400781A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 5) */ + #define REG_XDMAC_CNDC5 (0x400781ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 5) */ + #define REG_XDMAC_CUBC5 (0x400781B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 5) */ + #define REG_XDMAC_CBC5 (0x400781B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 5) */ + #define REG_XDMAC_CC5 (0x400781B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 5) */ + #define REG_XDMAC_CDS_MSP5 (0x400781BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 5) */ + #define REG_XDMAC_CSUS5 (0x400781C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 5) */ + #define REG_XDMAC_CDUS5 (0x400781C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 5) */ + #define REG_XDMAC_CIE6 (0x400781D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 6) */ + #define REG_XDMAC_CID6 (0x400781D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 6) */ + #define REG_XDMAC_CIM6 (0x400781D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 6) */ + #define REG_XDMAC_CIS6 (0x400781DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 6) */ + #define REG_XDMAC_CSA6 (0x400781E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 6) */ + #define REG_XDMAC_CDA6 (0x400781E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 6) */ + #define REG_XDMAC_CNDA6 (0x400781E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 6) */ + #define REG_XDMAC_CNDC6 (0x400781ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 6) */ + #define REG_XDMAC_CUBC6 (0x400781F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 6) */ + #define REG_XDMAC_CBC6 (0x400781F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 6) */ + #define REG_XDMAC_CC6 (0x400781F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 6) */ + #define REG_XDMAC_CDS_MSP6 (0x400781FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 6) */ + #define REG_XDMAC_CSUS6 (0x40078200U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 6) */ + #define REG_XDMAC_CDUS6 (0x40078204U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 6) */ + #define REG_XDMAC_CIE7 (0x40078210U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 7) */ + #define REG_XDMAC_CID7 (0x40078214U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 7) */ + #define REG_XDMAC_CIM7 (0x40078218U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 7) */ + #define REG_XDMAC_CIS7 (0x4007821CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 7) */ + #define REG_XDMAC_CSA7 (0x40078220U) /**< \brief (XDMAC) Channel Source Address Register (chid = 7) */ + #define REG_XDMAC_CDA7 (0x40078224U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 7) */ + #define REG_XDMAC_CNDA7 (0x40078228U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 7) */ + #define REG_XDMAC_CNDC7 (0x4007822CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 7) */ + #define REG_XDMAC_CUBC7 (0x40078230U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 7) */ + #define REG_XDMAC_CBC7 (0x40078234U) /**< \brief (XDMAC) Channel Block Control Register (chid = 7) */ + #define REG_XDMAC_CC7 (0x40078238U) /**< \brief (XDMAC) Channel Configuration Register (chid = 7) */ + #define REG_XDMAC_CDS_MSP7 (0x4007823CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 7) */ + #define REG_XDMAC_CSUS7 (0x40078240U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 7) */ + #define REG_XDMAC_CDUS7 (0x40078244U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 7) */ + #define REG_XDMAC_CIE8 (0x40078250U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 8) */ + #define REG_XDMAC_CID8 (0x40078254U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 8) */ + #define REG_XDMAC_CIM8 (0x40078258U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 8) */ + #define REG_XDMAC_CIS8 (0x4007825CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 8) */ + #define REG_XDMAC_CSA8 (0x40078260U) /**< \brief (XDMAC) Channel Source Address Register (chid = 8) */ + #define REG_XDMAC_CDA8 (0x40078264U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 8) */ + #define REG_XDMAC_CNDA8 (0x40078268U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 8) */ + #define REG_XDMAC_CNDC8 (0x4007826CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 8) */ + #define REG_XDMAC_CUBC8 (0x40078270U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 8) */ + #define REG_XDMAC_CBC8 (0x40078274U) /**< \brief (XDMAC) Channel Block Control Register (chid = 8) */ + #define REG_XDMAC_CC8 (0x40078278U) /**< \brief (XDMAC) Channel Configuration Register (chid = 8) */ + #define REG_XDMAC_CDS_MSP8 (0x4007827CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 8) */ + #define REG_XDMAC_CSUS8 (0x40078280U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 8) */ + #define REG_XDMAC_CDUS8 (0x40078284U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 8) */ + #define REG_XDMAC_CIE9 (0x40078290U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 9) */ + #define REG_XDMAC_CID9 (0x40078294U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 9) */ + #define REG_XDMAC_CIM9 (0x40078298U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 9) */ + #define REG_XDMAC_CIS9 (0x4007829CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 9) */ + #define REG_XDMAC_CSA9 (0x400782A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 9) */ + #define REG_XDMAC_CDA9 (0x400782A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 9) */ + #define REG_XDMAC_CNDA9 (0x400782A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 9) */ + #define REG_XDMAC_CNDC9 (0x400782ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 9) */ + #define REG_XDMAC_CUBC9 (0x400782B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 9) */ + #define REG_XDMAC_CBC9 (0x400782B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 9) */ + #define REG_XDMAC_CC9 (0x400782B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 9) */ + #define REG_XDMAC_CDS_MSP9 (0x400782BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 9) */ + #define REG_XDMAC_CSUS9 (0x400782C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 9) */ + #define REG_XDMAC_CDUS9 (0x400782C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 9) */ + #define REG_XDMAC_CIE10 (0x400782D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 10) */ + #define REG_XDMAC_CID10 (0x400782D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 10) */ + #define REG_XDMAC_CIM10 (0x400782D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 10) */ + #define REG_XDMAC_CIS10 (0x400782DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 10) */ + #define REG_XDMAC_CSA10 (0x400782E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 10) */ + #define REG_XDMAC_CDA10 (0x400782E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 10) */ + #define REG_XDMAC_CNDA10 (0x400782E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 10) */ + #define REG_XDMAC_CNDC10 (0x400782ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 10) */ + #define REG_XDMAC_CUBC10 (0x400782F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 10) */ + #define REG_XDMAC_CBC10 (0x400782F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 10) */ + #define REG_XDMAC_CC10 (0x400782F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 10) */ + #define REG_XDMAC_CDS_MSP10 (0x400782FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 10) */ + #define REG_XDMAC_CSUS10 (0x40078300U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 10) */ + #define REG_XDMAC_CDUS10 (0x40078304U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 10) */ + #define REG_XDMAC_CIE11 (0x40078310U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 11) */ + #define REG_XDMAC_CID11 (0x40078314U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 11) */ + #define REG_XDMAC_CIM11 (0x40078318U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 11) */ + #define REG_XDMAC_CIS11 (0x4007831CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 11) */ + #define REG_XDMAC_CSA11 (0x40078320U) /**< \brief (XDMAC) Channel Source Address Register (chid = 11) */ + #define REG_XDMAC_CDA11 (0x40078324U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 11) */ + #define REG_XDMAC_CNDA11 (0x40078328U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 11) */ + #define REG_XDMAC_CNDC11 (0x4007832CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 11) */ + #define REG_XDMAC_CUBC11 (0x40078330U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 11) */ + #define REG_XDMAC_CBC11 (0x40078334U) /**< \brief (XDMAC) Channel Block Control Register (chid = 11) */ + #define REG_XDMAC_CC11 (0x40078338U) /**< \brief (XDMAC) Channel Configuration Register (chid = 11) */ + #define REG_XDMAC_CDS_MSP11 (0x4007833CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 11) */ + #define REG_XDMAC_CSUS11 (0x40078340U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 11) */ + #define REG_XDMAC_CDUS11 (0x40078344U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 11) */ + #define REG_XDMAC_CIE12 (0x40078350U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 12) */ + #define REG_XDMAC_CID12 (0x40078354U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 12) */ + #define REG_XDMAC_CIM12 (0x40078358U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 12) */ + #define REG_XDMAC_CIS12 (0x4007835CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 12) */ + #define REG_XDMAC_CSA12 (0x40078360U) /**< \brief (XDMAC) Channel Source Address Register (chid = 12) */ + #define REG_XDMAC_CDA12 (0x40078364U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 12) */ + #define REG_XDMAC_CNDA12 (0x40078368U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 12) */ + #define REG_XDMAC_CNDC12 (0x4007836CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 12) */ + #define REG_XDMAC_CUBC12 (0x40078370U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 12) */ + #define REG_XDMAC_CBC12 (0x40078374U) /**< \brief (XDMAC) Channel Block Control Register (chid = 12) */ + #define REG_XDMAC_CC12 (0x40078378U) /**< \brief (XDMAC) Channel Configuration Register (chid = 12) */ + #define REG_XDMAC_CDS_MSP12 (0x4007837CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 12) */ + #define REG_XDMAC_CSUS12 (0x40078380U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 12) */ + #define REG_XDMAC_CDUS12 (0x40078384U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 12) */ + #define REG_XDMAC_CIE13 (0x40078390U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 13) */ + #define REG_XDMAC_CID13 (0x40078394U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 13) */ + #define REG_XDMAC_CIM13 (0x40078398U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 13) */ + #define REG_XDMAC_CIS13 (0x4007839CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 13) */ + #define REG_XDMAC_CSA13 (0x400783A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 13) */ + #define REG_XDMAC_CDA13 (0x400783A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 13) */ + #define REG_XDMAC_CNDA13 (0x400783A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 13) */ + #define REG_XDMAC_CNDC13 (0x400783ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 13) */ + #define REG_XDMAC_CUBC13 (0x400783B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 13) */ + #define REG_XDMAC_CBC13 (0x400783B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 13) */ + #define REG_XDMAC_CC13 (0x400783B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 13) */ + #define REG_XDMAC_CDS_MSP13 (0x400783BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 13) */ + #define REG_XDMAC_CSUS13 (0x400783C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 13) */ + #define REG_XDMAC_CDUS13 (0x400783C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 13) */ + #define REG_XDMAC_CIE14 (0x400783D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 14) */ + #define REG_XDMAC_CID14 (0x400783D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 14) */ + #define REG_XDMAC_CIM14 (0x400783D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 14) */ + #define REG_XDMAC_CIS14 (0x400783DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 14) */ + #define REG_XDMAC_CSA14 (0x400783E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 14) */ + #define REG_XDMAC_CDA14 (0x400783E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 14) */ + #define REG_XDMAC_CNDA14 (0x400783E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 14) */ + #define REG_XDMAC_CNDC14 (0x400783ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 14) */ + #define REG_XDMAC_CUBC14 (0x400783F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 14) */ + #define REG_XDMAC_CBC14 (0x400783F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 14) */ + #define REG_XDMAC_CC14 (0x400783F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 14) */ + #define REG_XDMAC_CDS_MSP14 (0x400783FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 14) */ + #define REG_XDMAC_CSUS14 (0x40078400U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 14) */ + #define REG_XDMAC_CDUS14 (0x40078404U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 14) */ + #define REG_XDMAC_CIE15 (0x40078410U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 15) */ + #define REG_XDMAC_CID15 (0x40078414U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 15) */ + #define REG_XDMAC_CIM15 (0x40078418U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 15) */ + #define REG_XDMAC_CIS15 (0x4007841CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 15) */ + #define REG_XDMAC_CSA15 (0x40078420U) /**< \brief (XDMAC) Channel Source Address Register (chid = 15) */ + #define REG_XDMAC_CDA15 (0x40078424U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 15) */ + #define REG_XDMAC_CNDA15 (0x40078428U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 15) */ + #define REG_XDMAC_CNDC15 (0x4007842CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 15) */ + #define REG_XDMAC_CUBC15 (0x40078430U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 15) */ + #define REG_XDMAC_CBC15 (0x40078434U) /**< \brief (XDMAC) Channel Block Control Register (chid = 15) */ + #define REG_XDMAC_CC15 (0x40078438U) /**< \brief (XDMAC) Channel Configuration Register (chid = 15) */ + #define REG_XDMAC_CDS_MSP15 (0x4007843CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 15) */ + #define REG_XDMAC_CSUS15 (0x40078440U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 15) */ + #define REG_XDMAC_CDUS15 (0x40078444U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 15) */ + #define REG_XDMAC_CIE16 (0x40078450U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 16) */ + #define REG_XDMAC_CID16 (0x40078454U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 16) */ + #define REG_XDMAC_CIM16 (0x40078458U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 16) */ + #define REG_XDMAC_CIS16 (0x4007845CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 16) */ + #define REG_XDMAC_CSA16 (0x40078460U) /**< \brief (XDMAC) Channel Source Address Register (chid = 16) */ + #define REG_XDMAC_CDA16 (0x40078464U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 16) */ + #define REG_XDMAC_CNDA16 (0x40078468U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 16) */ + #define REG_XDMAC_CNDC16 (0x4007846CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 16) */ + #define REG_XDMAC_CUBC16 (0x40078470U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 16) */ + #define REG_XDMAC_CBC16 (0x40078474U) /**< \brief (XDMAC) Channel Block Control Register (chid = 16) */ + #define REG_XDMAC_CC16 (0x40078478U) /**< \brief (XDMAC) Channel Configuration Register (chid = 16) */ + #define REG_XDMAC_CDS_MSP16 (0x4007847CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 16) */ + #define REG_XDMAC_CSUS16 (0x40078480U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 16) */ + #define REG_XDMAC_CDUS16 (0x40078484U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 16) */ + #define REG_XDMAC_CIE17 (0x40078490U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 17) */ + #define REG_XDMAC_CID17 (0x40078494U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 17) */ + #define REG_XDMAC_CIM17 (0x40078498U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 17) */ + #define REG_XDMAC_CIS17 (0x4007849CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 17) */ + #define REG_XDMAC_CSA17 (0x400784A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 17) */ + #define REG_XDMAC_CDA17 (0x400784A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 17) */ + #define REG_XDMAC_CNDA17 (0x400784A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 17) */ + #define REG_XDMAC_CNDC17 (0x400784ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 17) */ + #define REG_XDMAC_CUBC17 (0x400784B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 17) */ + #define REG_XDMAC_CBC17 (0x400784B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 17) */ + #define REG_XDMAC_CC17 (0x400784B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 17) */ + #define REG_XDMAC_CDS_MSP17 (0x400784BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 17) */ + #define REG_XDMAC_CSUS17 (0x400784C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 17) */ + #define REG_XDMAC_CDUS17 (0x400784C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 17) */ + #define REG_XDMAC_CIE18 (0x400784D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 18) */ + #define REG_XDMAC_CID18 (0x400784D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 18) */ + #define REG_XDMAC_CIM18 (0x400784D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 18) */ + #define REG_XDMAC_CIS18 (0x400784DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 18) */ + #define REG_XDMAC_CSA18 (0x400784E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 18) */ + #define REG_XDMAC_CDA18 (0x400784E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 18) */ + #define REG_XDMAC_CNDA18 (0x400784E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 18) */ + #define REG_XDMAC_CNDC18 (0x400784ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 18) */ + #define REG_XDMAC_CUBC18 (0x400784F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 18) */ + #define REG_XDMAC_CBC18 (0x400784F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 18) */ + #define REG_XDMAC_CC18 (0x400784F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 18) */ + #define REG_XDMAC_CDS_MSP18 (0x400784FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 18) */ + #define REG_XDMAC_CSUS18 (0x40078500U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 18) */ + #define REG_XDMAC_CDUS18 (0x40078504U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 18) */ + #define REG_XDMAC_CIE19 (0x40078510U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 19) */ + #define REG_XDMAC_CID19 (0x40078514U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 19) */ + #define REG_XDMAC_CIM19 (0x40078518U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 19) */ + #define REG_XDMAC_CIS19 (0x4007851CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 19) */ + #define REG_XDMAC_CSA19 (0x40078520U) /**< \brief (XDMAC) Channel Source Address Register (chid = 19) */ + #define REG_XDMAC_CDA19 (0x40078524U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 19) */ + #define REG_XDMAC_CNDA19 (0x40078528U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 19) */ + #define REG_XDMAC_CNDC19 (0x4007852CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 19) */ + #define REG_XDMAC_CUBC19 (0x40078530U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 19) */ + #define REG_XDMAC_CBC19 (0x40078534U) /**< \brief (XDMAC) Channel Block Control Register (chid = 19) */ + #define REG_XDMAC_CC19 (0x40078538U) /**< \brief (XDMAC) Channel Configuration Register (chid = 19) */ + #define REG_XDMAC_CDS_MSP19 (0x4007853CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 19) */ + #define REG_XDMAC_CSUS19 (0x40078540U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 19) */ + #define REG_XDMAC_CDUS19 (0x40078544U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 19) */ + #define REG_XDMAC_CIE20 (0x40078550U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 20) */ + #define REG_XDMAC_CID20 (0x40078554U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 20) */ + #define REG_XDMAC_CIM20 (0x40078558U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 20) */ + #define REG_XDMAC_CIS20 (0x4007855CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 20) */ + #define REG_XDMAC_CSA20 (0x40078560U) /**< \brief (XDMAC) Channel Source Address Register (chid = 20) */ + #define REG_XDMAC_CDA20 (0x40078564U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 20) */ + #define REG_XDMAC_CNDA20 (0x40078568U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 20) */ + #define REG_XDMAC_CNDC20 (0x4007856CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 20) */ + #define REG_XDMAC_CUBC20 (0x40078570U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 20) */ + #define REG_XDMAC_CBC20 (0x40078574U) /**< \brief (XDMAC) Channel Block Control Register (chid = 20) */ + #define REG_XDMAC_CC20 (0x40078578U) /**< \brief (XDMAC) Channel Configuration Register (chid = 20) */ + #define REG_XDMAC_CDS_MSP20 (0x4007857CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 20) */ + #define REG_XDMAC_CSUS20 (0x40078580U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 20) */ + #define REG_XDMAC_CDUS20 (0x40078584U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 20) */ + #define REG_XDMAC_CIE21 (0x40078590U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 21) */ + #define REG_XDMAC_CID21 (0x40078594U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 21) */ + #define REG_XDMAC_CIM21 (0x40078598U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 21) */ + #define REG_XDMAC_CIS21 (0x4007859CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 21) */ + #define REG_XDMAC_CSA21 (0x400785A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 21) */ + #define REG_XDMAC_CDA21 (0x400785A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 21) */ + #define REG_XDMAC_CNDA21 (0x400785A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 21) */ + #define REG_XDMAC_CNDC21 (0x400785ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 21) */ + #define REG_XDMAC_CUBC21 (0x400785B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 21) */ + #define REG_XDMAC_CBC21 (0x400785B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 21) */ + #define REG_XDMAC_CC21 (0x400785B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 21) */ + #define REG_XDMAC_CDS_MSP21 (0x400785BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 21) */ + #define REG_XDMAC_CSUS21 (0x400785C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 21) */ + #define REG_XDMAC_CDUS21 (0x400785C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 21) */ + #define REG_XDMAC_CIE22 (0x400785D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 22) */ + #define REG_XDMAC_CID22 (0x400785D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 22) */ + #define REG_XDMAC_CIM22 (0x400785D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 22) */ + #define REG_XDMAC_CIS22 (0x400785DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 22) */ + #define REG_XDMAC_CSA22 (0x400785E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 22) */ + #define REG_XDMAC_CDA22 (0x400785E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 22) */ + #define REG_XDMAC_CNDA22 (0x400785E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 22) */ + #define REG_XDMAC_CNDC22 (0x400785ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 22) */ + #define REG_XDMAC_CUBC22 (0x400785F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 22) */ + #define REG_XDMAC_CBC22 (0x400785F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 22) */ + #define REG_XDMAC_CC22 (0x400785F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 22) */ + #define REG_XDMAC_CDS_MSP22 (0x400785FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 22) */ + #define REG_XDMAC_CSUS22 (0x40078600U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 22) */ + #define REG_XDMAC_CDUS22 (0x40078604U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 22) */ + #define REG_XDMAC_CIE23 (0x40078610U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 23) */ + #define REG_XDMAC_CID23 (0x40078614U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 23) */ + #define REG_XDMAC_CIM23 (0x40078618U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 23) */ + #define REG_XDMAC_CIS23 (0x4007861CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 23) */ + #define REG_XDMAC_CSA23 (0x40078620U) /**< \brief (XDMAC) Channel Source Address Register (chid = 23) */ + #define REG_XDMAC_CDA23 (0x40078624U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 23) */ + #define REG_XDMAC_CNDA23 (0x40078628U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 23) */ + #define REG_XDMAC_CNDC23 (0x4007862CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 23) */ + #define REG_XDMAC_CUBC23 (0x40078630U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 23) */ + #define REG_XDMAC_CBC23 (0x40078634U) /**< \brief (XDMAC) Channel Block Control Register (chid = 23) */ + #define REG_XDMAC_CC23 (0x40078638U) /**< \brief (XDMAC) Channel Configuration Register (chid = 23) */ + #define REG_XDMAC_CDS_MSP23 (0x4007863CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 23) */ + #define REG_XDMAC_CSUS23 (0x40078640U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 23) */ + #define REG_XDMAC_CDUS23 (0x40078644U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 23) */ +#else + #define REG_XDMAC_GTYPE (*(__IO uint32_t*)0x40078000U) /**< \brief (XDMAC) Global Type Register */ + #define REG_XDMAC_GCFG (*(__I uint32_t*)0x40078004U) /**< \brief (XDMAC) Global Configuration Register */ + #define REG_XDMAC_GWAC (*(__IO uint32_t*)0x40078008U) /**< \brief (XDMAC) Global Weighted Arbiter Configuration Register */ + #define REG_XDMAC_GIE (*(__O uint32_t*)0x4007800CU) /**< \brief (XDMAC) Global Interrupt Enable Register */ + #define REG_XDMAC_GID (*(__O uint32_t*)0x40078010U) /**< \brief (XDMAC) Global Interrupt Disable Register */ + #define REG_XDMAC_GIM (*(__I uint32_t*)0x40078014U) /**< \brief (XDMAC) Global Interrupt Mask Register */ + #define REG_XDMAC_GIS (*(__I uint32_t*)0x40078018U) /**< \brief (XDMAC) Global Interrupt Status Register */ + #define REG_XDMAC_GE (*(__O uint32_t*)0x4007801CU) /**< \brief (XDMAC) Global Channel Enable Register */ + #define REG_XDMAC_GD (*(__O uint32_t*)0x40078020U) /**< \brief (XDMAC) Global Channel Disable Register */ + #define REG_XDMAC_GS (*(__I uint32_t*)0x40078024U) /**< \brief (XDMAC) Global Channel Status Register */ + #define REG_XDMAC_GRS (*(__IO uint32_t*)0x40078028U) /**< \brief (XDMAC) Global Channel Read Suspend Register */ + #define REG_XDMAC_GWS (*(__IO uint32_t*)0x4007802CU) /**< \brief (XDMAC) Global Channel Write Suspend Register */ + #define REG_XDMAC_GRWS (*(__O uint32_t*)0x40078030U) /**< \brief (XDMAC) Global Channel Read Write Suspend Register */ + #define REG_XDMAC_GRWR (*(__O uint32_t*)0x40078034U) /**< \brief (XDMAC) Global Channel Read Write Resume Register */ + #define REG_XDMAC_GSWR (*(__O uint32_t*)0x40078038U) /**< \brief (XDMAC) Global Channel Software Request Register */ + #define REG_XDMAC_GSWS (*(__I uint32_t*)0x4007803CU) /**< \brief (XDMAC) Global Channel Software Request Status Register */ + #define REG_XDMAC_GSWF (*(__O uint32_t*)0x40078040U) /**< \brief (XDMAC) Global Channel Software Flush Request Register */ + #define REG_XDMAC_CIE0 (*(__O uint32_t*)0x40078050U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 0) */ + #define REG_XDMAC_CID0 (*(__O uint32_t*)0x40078054U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 0) */ + #define REG_XDMAC_CIM0 (*(__O uint32_t*)0x40078058U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 0) */ + #define REG_XDMAC_CIS0 (*(__I uint32_t*)0x4007805CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 0) */ + #define REG_XDMAC_CSA0 (*(__IO uint32_t*)0x40078060U) /**< \brief (XDMAC) Channel Source Address Register (chid = 0) */ + #define REG_XDMAC_CDA0 (*(__IO uint32_t*)0x40078064U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 0) */ + #define REG_XDMAC_CNDA0 (*(__IO uint32_t*)0x40078068U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 0) */ + #define REG_XDMAC_CNDC0 (*(__IO uint32_t*)0x4007806CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 0) */ + #define REG_XDMAC_CUBC0 (*(__IO uint32_t*)0x40078070U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 0) */ + #define REG_XDMAC_CBC0 (*(__IO uint32_t*)0x40078074U) /**< \brief (XDMAC) Channel Block Control Register (chid = 0) */ + #define REG_XDMAC_CC0 (*(__IO uint32_t*)0x40078078U) /**< \brief (XDMAC) Channel Configuration Register (chid = 0) */ + #define REG_XDMAC_CDS_MSP0 (*(__IO uint32_t*)0x4007807CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) */ + #define REG_XDMAC_CSUS0 (*(__IO uint32_t*)0x40078080U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 0) */ + #define REG_XDMAC_CDUS0 (*(__IO uint32_t*)0x40078084U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 0) */ + #define REG_XDMAC_CIE1 (*(__O uint32_t*)0x40078090U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 1) */ + #define REG_XDMAC_CID1 (*(__O uint32_t*)0x40078094U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 1) */ + #define REG_XDMAC_CIM1 (*(__O uint32_t*)0x40078098U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 1) */ + #define REG_XDMAC_CIS1 (*(__I uint32_t*)0x4007809CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 1) */ + #define REG_XDMAC_CSA1 (*(__IO uint32_t*)0x400780A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 1) */ + #define REG_XDMAC_CDA1 (*(__IO uint32_t*)0x400780A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 1) */ + #define REG_XDMAC_CNDA1 (*(__IO uint32_t*)0x400780A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 1) */ + #define REG_XDMAC_CNDC1 (*(__IO uint32_t*)0x400780ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 1) */ + #define REG_XDMAC_CUBC1 (*(__IO uint32_t*)0x400780B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 1) */ + #define REG_XDMAC_CBC1 (*(__IO uint32_t*)0x400780B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 1) */ + #define REG_XDMAC_CC1 (*(__IO uint32_t*)0x400780B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 1) */ + #define REG_XDMAC_CDS_MSP1 (*(__IO uint32_t*)0x400780BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 1) */ + #define REG_XDMAC_CSUS1 (*(__IO uint32_t*)0x400780C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 1) */ + #define REG_XDMAC_CDUS1 (*(__IO uint32_t*)0x400780C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 1) */ + #define REG_XDMAC_CIE2 (*(__O uint32_t*)0x400780D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 2) */ + #define REG_XDMAC_CID2 (*(__O uint32_t*)0x400780D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 2) */ + #define REG_XDMAC_CIM2 (*(__O uint32_t*)0x400780D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 2) */ + #define REG_XDMAC_CIS2 (*(__I uint32_t*)0x400780DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 2) */ + #define REG_XDMAC_CSA2 (*(__IO uint32_t*)0x400780E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 2) */ + #define REG_XDMAC_CDA2 (*(__IO uint32_t*)0x400780E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 2) */ + #define REG_XDMAC_CNDA2 (*(__IO uint32_t*)0x400780E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 2) */ + #define REG_XDMAC_CNDC2 (*(__IO uint32_t*)0x400780ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 2) */ + #define REG_XDMAC_CUBC2 (*(__IO uint32_t*)0x400780F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 2) */ + #define REG_XDMAC_CBC2 (*(__IO uint32_t*)0x400780F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 2) */ + #define REG_XDMAC_CC2 (*(__IO uint32_t*)0x400780F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 2) */ + #define REG_XDMAC_CDS_MSP2 (*(__IO uint32_t*)0x400780FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 2) */ + #define REG_XDMAC_CSUS2 (*(__IO uint32_t*)0x40078100U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 2) */ + #define REG_XDMAC_CDUS2 (*(__IO uint32_t*)0x40078104U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 2) */ + #define REG_XDMAC_CIE3 (*(__O uint32_t*)0x40078110U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 3) */ + #define REG_XDMAC_CID3 (*(__O uint32_t*)0x40078114U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 3) */ + #define REG_XDMAC_CIM3 (*(__O uint32_t*)0x40078118U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 3) */ + #define REG_XDMAC_CIS3 (*(__I uint32_t*)0x4007811CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 3) */ + #define REG_XDMAC_CSA3 (*(__IO uint32_t*)0x40078120U) /**< \brief (XDMAC) Channel Source Address Register (chid = 3) */ + #define REG_XDMAC_CDA3 (*(__IO uint32_t*)0x40078124U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 3) */ + #define REG_XDMAC_CNDA3 (*(__IO uint32_t*)0x40078128U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 3) */ + #define REG_XDMAC_CNDC3 (*(__IO uint32_t*)0x4007812CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 3) */ + #define REG_XDMAC_CUBC3 (*(__IO uint32_t*)0x40078130U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 3) */ + #define REG_XDMAC_CBC3 (*(__IO uint32_t*)0x40078134U) /**< \brief (XDMAC) Channel Block Control Register (chid = 3) */ + #define REG_XDMAC_CC3 (*(__IO uint32_t*)0x40078138U) /**< \brief (XDMAC) Channel Configuration Register (chid = 3) */ + #define REG_XDMAC_CDS_MSP3 (*(__IO uint32_t*)0x4007813CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 3) */ + #define REG_XDMAC_CSUS3 (*(__IO uint32_t*)0x40078140U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 3) */ + #define REG_XDMAC_CDUS3 (*(__IO uint32_t*)0x40078144U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 3) */ + #define REG_XDMAC_CIE4 (*(__O uint32_t*)0x40078150U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 4) */ + #define REG_XDMAC_CID4 (*(__O uint32_t*)0x40078154U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 4) */ + #define REG_XDMAC_CIM4 (*(__O uint32_t*)0x40078158U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 4) */ + #define REG_XDMAC_CIS4 (*(__I uint32_t*)0x4007815CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 4) */ + #define REG_XDMAC_CSA4 (*(__IO uint32_t*)0x40078160U) /**< \brief (XDMAC) Channel Source Address Register (chid = 4) */ + #define REG_XDMAC_CDA4 (*(__IO uint32_t*)0x40078164U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 4) */ + #define REG_XDMAC_CNDA4 (*(__IO uint32_t*)0x40078168U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 4) */ + #define REG_XDMAC_CNDC4 (*(__IO uint32_t*)0x4007816CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 4) */ + #define REG_XDMAC_CUBC4 (*(__IO uint32_t*)0x40078170U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 4) */ + #define REG_XDMAC_CBC4 (*(__IO uint32_t*)0x40078174U) /**< \brief (XDMAC) Channel Block Control Register (chid = 4) */ + #define REG_XDMAC_CC4 (*(__IO uint32_t*)0x40078178U) /**< \brief (XDMAC) Channel Configuration Register (chid = 4) */ + #define REG_XDMAC_CDS_MSP4 (*(__IO uint32_t*)0x4007817CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 4) */ + #define REG_XDMAC_CSUS4 (*(__IO uint32_t*)0x40078180U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 4) */ + #define REG_XDMAC_CDUS4 (*(__IO uint32_t*)0x40078184U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 4) */ + #define REG_XDMAC_CIE5 (*(__O uint32_t*)0x40078190U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 5) */ + #define REG_XDMAC_CID5 (*(__O uint32_t*)0x40078194U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 5) */ + #define REG_XDMAC_CIM5 (*(__O uint32_t*)0x40078198U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 5) */ + #define REG_XDMAC_CIS5 (*(__I uint32_t*)0x4007819CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 5) */ + #define REG_XDMAC_CSA5 (*(__IO uint32_t*)0x400781A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 5) */ + #define REG_XDMAC_CDA5 (*(__IO uint32_t*)0x400781A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 5) */ + #define REG_XDMAC_CNDA5 (*(__IO uint32_t*)0x400781A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 5) */ + #define REG_XDMAC_CNDC5 (*(__IO uint32_t*)0x400781ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 5) */ + #define REG_XDMAC_CUBC5 (*(__IO uint32_t*)0x400781B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 5) */ + #define REG_XDMAC_CBC5 (*(__IO uint32_t*)0x400781B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 5) */ + #define REG_XDMAC_CC5 (*(__IO uint32_t*)0x400781B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 5) */ + #define REG_XDMAC_CDS_MSP5 (*(__IO uint32_t*)0x400781BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 5) */ + #define REG_XDMAC_CSUS5 (*(__IO uint32_t*)0x400781C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 5) */ + #define REG_XDMAC_CDUS5 (*(__IO uint32_t*)0x400781C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 5) */ + #define REG_XDMAC_CIE6 (*(__O uint32_t*)0x400781D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 6) */ + #define REG_XDMAC_CID6 (*(__O uint32_t*)0x400781D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 6) */ + #define REG_XDMAC_CIM6 (*(__O uint32_t*)0x400781D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 6) */ + #define REG_XDMAC_CIS6 (*(__I uint32_t*)0x400781DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 6) */ + #define REG_XDMAC_CSA6 (*(__IO uint32_t*)0x400781E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 6) */ + #define REG_XDMAC_CDA6 (*(__IO uint32_t*)0x400781E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 6) */ + #define REG_XDMAC_CNDA6 (*(__IO uint32_t*)0x400781E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 6) */ + #define REG_XDMAC_CNDC6 (*(__IO uint32_t*)0x400781ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 6) */ + #define REG_XDMAC_CUBC6 (*(__IO uint32_t*)0x400781F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 6) */ + #define REG_XDMAC_CBC6 (*(__IO uint32_t*)0x400781F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 6) */ + #define REG_XDMAC_CC6 (*(__IO uint32_t*)0x400781F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 6) */ + #define REG_XDMAC_CDS_MSP6 (*(__IO uint32_t*)0x400781FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 6) */ + #define REG_XDMAC_CSUS6 (*(__IO uint32_t*)0x40078200U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 6) */ + #define REG_XDMAC_CDUS6 (*(__IO uint32_t*)0x40078204U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 6) */ + #define REG_XDMAC_CIE7 (*(__O uint32_t*)0x40078210U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 7) */ + #define REG_XDMAC_CID7 (*(__O uint32_t*)0x40078214U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 7) */ + #define REG_XDMAC_CIM7 (*(__O uint32_t*)0x40078218U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 7) */ + #define REG_XDMAC_CIS7 (*(__I uint32_t*)0x4007821CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 7) */ + #define REG_XDMAC_CSA7 (*(__IO uint32_t*)0x40078220U) /**< \brief (XDMAC) Channel Source Address Register (chid = 7) */ + #define REG_XDMAC_CDA7 (*(__IO uint32_t*)0x40078224U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 7) */ + #define REG_XDMAC_CNDA7 (*(__IO uint32_t*)0x40078228U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 7) */ + #define REG_XDMAC_CNDC7 (*(__IO uint32_t*)0x4007822CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 7) */ + #define REG_XDMAC_CUBC7 (*(__IO uint32_t*)0x40078230U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 7) */ + #define REG_XDMAC_CBC7 (*(__IO uint32_t*)0x40078234U) /**< \brief (XDMAC) Channel Block Control Register (chid = 7) */ + #define REG_XDMAC_CC7 (*(__IO uint32_t*)0x40078238U) /**< \brief (XDMAC) Channel Configuration Register (chid = 7) */ + #define REG_XDMAC_CDS_MSP7 (*(__IO uint32_t*)0x4007823CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 7) */ + #define REG_XDMAC_CSUS7 (*(__IO uint32_t*)0x40078240U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 7) */ + #define REG_XDMAC_CDUS7 (*(__IO uint32_t*)0x40078244U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 7) */ + #define REG_XDMAC_CIE8 (*(__O uint32_t*)0x40078250U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 8) */ + #define REG_XDMAC_CID8 (*(__O uint32_t*)0x40078254U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 8) */ + #define REG_XDMAC_CIM8 (*(__O uint32_t*)0x40078258U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 8) */ + #define REG_XDMAC_CIS8 (*(__I uint32_t*)0x4007825CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 8) */ + #define REG_XDMAC_CSA8 (*(__IO uint32_t*)0x40078260U) /**< \brief (XDMAC) Channel Source Address Register (chid = 8) */ + #define REG_XDMAC_CDA8 (*(__IO uint32_t*)0x40078264U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 8) */ + #define REG_XDMAC_CNDA8 (*(__IO uint32_t*)0x40078268U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 8) */ + #define REG_XDMAC_CNDC8 (*(__IO uint32_t*)0x4007826CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 8) */ + #define REG_XDMAC_CUBC8 (*(__IO uint32_t*)0x40078270U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 8) */ + #define REG_XDMAC_CBC8 (*(__IO uint32_t*)0x40078274U) /**< \brief (XDMAC) Channel Block Control Register (chid = 8) */ + #define REG_XDMAC_CC8 (*(__IO uint32_t*)0x40078278U) /**< \brief (XDMAC) Channel Configuration Register (chid = 8) */ + #define REG_XDMAC_CDS_MSP8 (*(__IO uint32_t*)0x4007827CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 8) */ + #define REG_XDMAC_CSUS8 (*(__IO uint32_t*)0x40078280U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 8) */ + #define REG_XDMAC_CDUS8 (*(__IO uint32_t*)0x40078284U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 8) */ + #define REG_XDMAC_CIE9 (*(__O uint32_t*)0x40078290U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 9) */ + #define REG_XDMAC_CID9 (*(__O uint32_t*)0x40078294U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 9) */ + #define REG_XDMAC_CIM9 (*(__O uint32_t*)0x40078298U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 9) */ + #define REG_XDMAC_CIS9 (*(__I uint32_t*)0x4007829CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 9) */ + #define REG_XDMAC_CSA9 (*(__IO uint32_t*)0x400782A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 9) */ + #define REG_XDMAC_CDA9 (*(__IO uint32_t*)0x400782A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 9) */ + #define REG_XDMAC_CNDA9 (*(__IO uint32_t*)0x400782A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 9) */ + #define REG_XDMAC_CNDC9 (*(__IO uint32_t*)0x400782ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 9) */ + #define REG_XDMAC_CUBC9 (*(__IO uint32_t*)0x400782B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 9) */ + #define REG_XDMAC_CBC9 (*(__IO uint32_t*)0x400782B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 9) */ + #define REG_XDMAC_CC9 (*(__IO uint32_t*)0x400782B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 9) */ + #define REG_XDMAC_CDS_MSP9 (*(__IO uint32_t*)0x400782BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 9) */ + #define REG_XDMAC_CSUS9 (*(__IO uint32_t*)0x400782C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 9) */ + #define REG_XDMAC_CDUS9 (*(__IO uint32_t*)0x400782C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 9) */ + #define REG_XDMAC_CIE10 (*(__O uint32_t*)0x400782D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 10) */ + #define REG_XDMAC_CID10 (*(__O uint32_t*)0x400782D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 10) */ + #define REG_XDMAC_CIM10 (*(__O uint32_t*)0x400782D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 10) */ + #define REG_XDMAC_CIS10 (*(__I uint32_t*)0x400782DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 10) */ + #define REG_XDMAC_CSA10 (*(__IO uint32_t*)0x400782E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 10) */ + #define REG_XDMAC_CDA10 (*(__IO uint32_t*)0x400782E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 10) */ + #define REG_XDMAC_CNDA10 (*(__IO uint32_t*)0x400782E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 10) */ + #define REG_XDMAC_CNDC10 (*(__IO uint32_t*)0x400782ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 10) */ + #define REG_XDMAC_CUBC10 (*(__IO uint32_t*)0x400782F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 10) */ + #define REG_XDMAC_CBC10 (*(__IO uint32_t*)0x400782F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 10) */ + #define REG_XDMAC_CC10 (*(__IO uint32_t*)0x400782F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 10) */ + #define REG_XDMAC_CDS_MSP10 (*(__IO uint32_t*)0x400782FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 10) */ + #define REG_XDMAC_CSUS10 (*(__IO uint32_t*)0x40078300U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 10) */ + #define REG_XDMAC_CDUS10 (*(__IO uint32_t*)0x40078304U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 10) */ + #define REG_XDMAC_CIE11 (*(__O uint32_t*)0x40078310U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 11) */ + #define REG_XDMAC_CID11 (*(__O uint32_t*)0x40078314U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 11) */ + #define REG_XDMAC_CIM11 (*(__O uint32_t*)0x40078318U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 11) */ + #define REG_XDMAC_CIS11 (*(__I uint32_t*)0x4007831CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 11) */ + #define REG_XDMAC_CSA11 (*(__IO uint32_t*)0x40078320U) /**< \brief (XDMAC) Channel Source Address Register (chid = 11) */ + #define REG_XDMAC_CDA11 (*(__IO uint32_t*)0x40078324U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 11) */ + #define REG_XDMAC_CNDA11 (*(__IO uint32_t*)0x40078328U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 11) */ + #define REG_XDMAC_CNDC11 (*(__IO uint32_t*)0x4007832CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 11) */ + #define REG_XDMAC_CUBC11 (*(__IO uint32_t*)0x40078330U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 11) */ + #define REG_XDMAC_CBC11 (*(__IO uint32_t*)0x40078334U) /**< \brief (XDMAC) Channel Block Control Register (chid = 11) */ + #define REG_XDMAC_CC11 (*(__IO uint32_t*)0x40078338U) /**< \brief (XDMAC) Channel Configuration Register (chid = 11) */ + #define REG_XDMAC_CDS_MSP11 (*(__IO uint32_t*)0x4007833CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 11) */ + #define REG_XDMAC_CSUS11 (*(__IO uint32_t*)0x40078340U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 11) */ + #define REG_XDMAC_CDUS11 (*(__IO uint32_t*)0x40078344U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 11) */ + #define REG_XDMAC_CIE12 (*(__O uint32_t*)0x40078350U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 12) */ + #define REG_XDMAC_CID12 (*(__O uint32_t*)0x40078354U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 12) */ + #define REG_XDMAC_CIM12 (*(__O uint32_t*)0x40078358U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 12) */ + #define REG_XDMAC_CIS12 (*(__I uint32_t*)0x4007835CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 12) */ + #define REG_XDMAC_CSA12 (*(__IO uint32_t*)0x40078360U) /**< \brief (XDMAC) Channel Source Address Register (chid = 12) */ + #define REG_XDMAC_CDA12 (*(__IO uint32_t*)0x40078364U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 12) */ + #define REG_XDMAC_CNDA12 (*(__IO uint32_t*)0x40078368U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 12) */ + #define REG_XDMAC_CNDC12 (*(__IO uint32_t*)0x4007836CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 12) */ + #define REG_XDMAC_CUBC12 (*(__IO uint32_t*)0x40078370U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 12) */ + #define REG_XDMAC_CBC12 (*(__IO uint32_t*)0x40078374U) /**< \brief (XDMAC) Channel Block Control Register (chid = 12) */ + #define REG_XDMAC_CC12 (*(__IO uint32_t*)0x40078378U) /**< \brief (XDMAC) Channel Configuration Register (chid = 12) */ + #define REG_XDMAC_CDS_MSP12 (*(__IO uint32_t*)0x4007837CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 12) */ + #define REG_XDMAC_CSUS12 (*(__IO uint32_t*)0x40078380U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 12) */ + #define REG_XDMAC_CDUS12 (*(__IO uint32_t*)0x40078384U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 12) */ + #define REG_XDMAC_CIE13 (*(__O uint32_t*)0x40078390U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 13) */ + #define REG_XDMAC_CID13 (*(__O uint32_t*)0x40078394U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 13) */ + #define REG_XDMAC_CIM13 (*(__O uint32_t*)0x40078398U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 13) */ + #define REG_XDMAC_CIS13 (*(__I uint32_t*)0x4007839CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 13) */ + #define REG_XDMAC_CSA13 (*(__IO uint32_t*)0x400783A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 13) */ + #define REG_XDMAC_CDA13 (*(__IO uint32_t*)0x400783A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 13) */ + #define REG_XDMAC_CNDA13 (*(__IO uint32_t*)0x400783A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 13) */ + #define REG_XDMAC_CNDC13 (*(__IO uint32_t*)0x400783ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 13) */ + #define REG_XDMAC_CUBC13 (*(__IO uint32_t*)0x400783B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 13) */ + #define REG_XDMAC_CBC13 (*(__IO uint32_t*)0x400783B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 13) */ + #define REG_XDMAC_CC13 (*(__IO uint32_t*)0x400783B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 13) */ + #define REG_XDMAC_CDS_MSP13 (*(__IO uint32_t*)0x400783BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 13) */ + #define REG_XDMAC_CSUS13 (*(__IO uint32_t*)0x400783C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 13) */ + #define REG_XDMAC_CDUS13 (*(__IO uint32_t*)0x400783C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 13) */ + #define REG_XDMAC_CIE14 (*(__O uint32_t*)0x400783D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 14) */ + #define REG_XDMAC_CID14 (*(__O uint32_t*)0x400783D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 14) */ + #define REG_XDMAC_CIM14 (*(__O uint32_t*)0x400783D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 14) */ + #define REG_XDMAC_CIS14 (*(__I uint32_t*)0x400783DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 14) */ + #define REG_XDMAC_CSA14 (*(__IO uint32_t*)0x400783E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 14) */ + #define REG_XDMAC_CDA14 (*(__IO uint32_t*)0x400783E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 14) */ + #define REG_XDMAC_CNDA14 (*(__IO uint32_t*)0x400783E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 14) */ + #define REG_XDMAC_CNDC14 (*(__IO uint32_t*)0x400783ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 14) */ + #define REG_XDMAC_CUBC14 (*(__IO uint32_t*)0x400783F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 14) */ + #define REG_XDMAC_CBC14 (*(__IO uint32_t*)0x400783F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 14) */ + #define REG_XDMAC_CC14 (*(__IO uint32_t*)0x400783F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 14) */ + #define REG_XDMAC_CDS_MSP14 (*(__IO uint32_t*)0x400783FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 14) */ + #define REG_XDMAC_CSUS14 (*(__IO uint32_t*)0x40078400U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 14) */ + #define REG_XDMAC_CDUS14 (*(__IO uint32_t*)0x40078404U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 14) */ + #define REG_XDMAC_CIE15 (*(__O uint32_t*)0x40078410U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 15) */ + #define REG_XDMAC_CID15 (*(__O uint32_t*)0x40078414U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 15) */ + #define REG_XDMAC_CIM15 (*(__O uint32_t*)0x40078418U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 15) */ + #define REG_XDMAC_CIS15 (*(__I uint32_t*)0x4007841CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 15) */ + #define REG_XDMAC_CSA15 (*(__IO uint32_t*)0x40078420U) /**< \brief (XDMAC) Channel Source Address Register (chid = 15) */ + #define REG_XDMAC_CDA15 (*(__IO uint32_t*)0x40078424U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 15) */ + #define REG_XDMAC_CNDA15 (*(__IO uint32_t*)0x40078428U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 15) */ + #define REG_XDMAC_CNDC15 (*(__IO uint32_t*)0x4007842CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 15) */ + #define REG_XDMAC_CUBC15 (*(__IO uint32_t*)0x40078430U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 15) */ + #define REG_XDMAC_CBC15 (*(__IO uint32_t*)0x40078434U) /**< \brief (XDMAC) Channel Block Control Register (chid = 15) */ + #define REG_XDMAC_CC15 (*(__IO uint32_t*)0x40078438U) /**< \brief (XDMAC) Channel Configuration Register (chid = 15) */ + #define REG_XDMAC_CDS_MSP15 (*(__IO uint32_t*)0x4007843CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 15) */ + #define REG_XDMAC_CSUS15 (*(__IO uint32_t*)0x40078440U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 15) */ + #define REG_XDMAC_CDUS15 (*(__IO uint32_t*)0x40078444U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 15) */ + #define REG_XDMAC_CIE16 (*(__O uint32_t*)0x40078450U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 16) */ + #define REG_XDMAC_CID16 (*(__O uint32_t*)0x40078454U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 16) */ + #define REG_XDMAC_CIM16 (*(__O uint32_t*)0x40078458U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 16) */ + #define REG_XDMAC_CIS16 (*(__I uint32_t*)0x4007845CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 16) */ + #define REG_XDMAC_CSA16 (*(__IO uint32_t*)0x40078460U) /**< \brief (XDMAC) Channel Source Address Register (chid = 16) */ + #define REG_XDMAC_CDA16 (*(__IO uint32_t*)0x40078464U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 16) */ + #define REG_XDMAC_CNDA16 (*(__IO uint32_t*)0x40078468U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 16) */ + #define REG_XDMAC_CNDC16 (*(__IO uint32_t*)0x4007846CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 16) */ + #define REG_XDMAC_CUBC16 (*(__IO uint32_t*)0x40078470U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 16) */ + #define REG_XDMAC_CBC16 (*(__IO uint32_t*)0x40078474U) /**< \brief (XDMAC) Channel Block Control Register (chid = 16) */ + #define REG_XDMAC_CC16 (*(__IO uint32_t*)0x40078478U) /**< \brief (XDMAC) Channel Configuration Register (chid = 16) */ + #define REG_XDMAC_CDS_MSP16 (*(__IO uint32_t*)0x4007847CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 16) */ + #define REG_XDMAC_CSUS16 (*(__IO uint32_t*)0x40078480U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 16) */ + #define REG_XDMAC_CDUS16 (*(__IO uint32_t*)0x40078484U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 16) */ + #define REG_XDMAC_CIE17 (*(__O uint32_t*)0x40078490U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 17) */ + #define REG_XDMAC_CID17 (*(__O uint32_t*)0x40078494U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 17) */ + #define REG_XDMAC_CIM17 (*(__O uint32_t*)0x40078498U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 17) */ + #define REG_XDMAC_CIS17 (*(__I uint32_t*)0x4007849CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 17) */ + #define REG_XDMAC_CSA17 (*(__IO uint32_t*)0x400784A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 17) */ + #define REG_XDMAC_CDA17 (*(__IO uint32_t*)0x400784A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 17) */ + #define REG_XDMAC_CNDA17 (*(__IO uint32_t*)0x400784A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 17) */ + #define REG_XDMAC_CNDC17 (*(__IO uint32_t*)0x400784ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 17) */ + #define REG_XDMAC_CUBC17 (*(__IO uint32_t*)0x400784B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 17) */ + #define REG_XDMAC_CBC17 (*(__IO uint32_t*)0x400784B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 17) */ + #define REG_XDMAC_CC17 (*(__IO uint32_t*)0x400784B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 17) */ + #define REG_XDMAC_CDS_MSP17 (*(__IO uint32_t*)0x400784BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 17) */ + #define REG_XDMAC_CSUS17 (*(__IO uint32_t*)0x400784C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 17) */ + #define REG_XDMAC_CDUS17 (*(__IO uint32_t*)0x400784C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 17) */ + #define REG_XDMAC_CIE18 (*(__O uint32_t*)0x400784D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 18) */ + #define REG_XDMAC_CID18 (*(__O uint32_t*)0x400784D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 18) */ + #define REG_XDMAC_CIM18 (*(__O uint32_t*)0x400784D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 18) */ + #define REG_XDMAC_CIS18 (*(__I uint32_t*)0x400784DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 18) */ + #define REG_XDMAC_CSA18 (*(__IO uint32_t*)0x400784E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 18) */ + #define REG_XDMAC_CDA18 (*(__IO uint32_t*)0x400784E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 18) */ + #define REG_XDMAC_CNDA18 (*(__IO uint32_t*)0x400784E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 18) */ + #define REG_XDMAC_CNDC18 (*(__IO uint32_t*)0x400784ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 18) */ + #define REG_XDMAC_CUBC18 (*(__IO uint32_t*)0x400784F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 18) */ + #define REG_XDMAC_CBC18 (*(__IO uint32_t*)0x400784F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 18) */ + #define REG_XDMAC_CC18 (*(__IO uint32_t*)0x400784F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 18) */ + #define REG_XDMAC_CDS_MSP18 (*(__IO uint32_t*)0x400784FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 18) */ + #define REG_XDMAC_CSUS18 (*(__IO uint32_t*)0x40078500U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 18) */ + #define REG_XDMAC_CDUS18 (*(__IO uint32_t*)0x40078504U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 18) */ + #define REG_XDMAC_CIE19 (*(__O uint32_t*)0x40078510U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 19) */ + #define REG_XDMAC_CID19 (*(__O uint32_t*)0x40078514U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 19) */ + #define REG_XDMAC_CIM19 (*(__O uint32_t*)0x40078518U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 19) */ + #define REG_XDMAC_CIS19 (*(__I uint32_t*)0x4007851CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 19) */ + #define REG_XDMAC_CSA19 (*(__IO uint32_t*)0x40078520U) /**< \brief (XDMAC) Channel Source Address Register (chid = 19) */ + #define REG_XDMAC_CDA19 (*(__IO uint32_t*)0x40078524U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 19) */ + #define REG_XDMAC_CNDA19 (*(__IO uint32_t*)0x40078528U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 19) */ + #define REG_XDMAC_CNDC19 (*(__IO uint32_t*)0x4007852CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 19) */ + #define REG_XDMAC_CUBC19 (*(__IO uint32_t*)0x40078530U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 19) */ + #define REG_XDMAC_CBC19 (*(__IO uint32_t*)0x40078534U) /**< \brief (XDMAC) Channel Block Control Register (chid = 19) */ + #define REG_XDMAC_CC19 (*(__IO uint32_t*)0x40078538U) /**< \brief (XDMAC) Channel Configuration Register (chid = 19) */ + #define REG_XDMAC_CDS_MSP19 (*(__IO uint32_t*)0x4007853CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 19) */ + #define REG_XDMAC_CSUS19 (*(__IO uint32_t*)0x40078540U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 19) */ + #define REG_XDMAC_CDUS19 (*(__IO uint32_t*)0x40078544U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 19) */ + #define REG_XDMAC_CIE20 (*(__O uint32_t*)0x40078550U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 20) */ + #define REG_XDMAC_CID20 (*(__O uint32_t*)0x40078554U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 20) */ + #define REG_XDMAC_CIM20 (*(__O uint32_t*)0x40078558U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 20) */ + #define REG_XDMAC_CIS20 (*(__I uint32_t*)0x4007855CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 20) */ + #define REG_XDMAC_CSA20 (*(__IO uint32_t*)0x40078560U) /**< \brief (XDMAC) Channel Source Address Register (chid = 20) */ + #define REG_XDMAC_CDA20 (*(__IO uint32_t*)0x40078564U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 20) */ + #define REG_XDMAC_CNDA20 (*(__IO uint32_t*)0x40078568U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 20) */ + #define REG_XDMAC_CNDC20 (*(__IO uint32_t*)0x4007856CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 20) */ + #define REG_XDMAC_CUBC20 (*(__IO uint32_t*)0x40078570U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 20) */ + #define REG_XDMAC_CBC20 (*(__IO uint32_t*)0x40078574U) /**< \brief (XDMAC) Channel Block Control Register (chid = 20) */ + #define REG_XDMAC_CC20 (*(__IO uint32_t*)0x40078578U) /**< \brief (XDMAC) Channel Configuration Register (chid = 20) */ + #define REG_XDMAC_CDS_MSP20 (*(__IO uint32_t*)0x4007857CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 20) */ + #define REG_XDMAC_CSUS20 (*(__IO uint32_t*)0x40078580U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 20) */ + #define REG_XDMAC_CDUS20 (*(__IO uint32_t*)0x40078584U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 20) */ + #define REG_XDMAC_CIE21 (*(__O uint32_t*)0x40078590U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 21) */ + #define REG_XDMAC_CID21 (*(__O uint32_t*)0x40078594U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 21) */ + #define REG_XDMAC_CIM21 (*(__O uint32_t*)0x40078598U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 21) */ + #define REG_XDMAC_CIS21 (*(__I uint32_t*)0x4007859CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 21) */ + #define REG_XDMAC_CSA21 (*(__IO uint32_t*)0x400785A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 21) */ + #define REG_XDMAC_CDA21 (*(__IO uint32_t*)0x400785A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 21) */ + #define REG_XDMAC_CNDA21 (*(__IO uint32_t*)0x400785A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 21) */ + #define REG_XDMAC_CNDC21 (*(__IO uint32_t*)0x400785ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 21) */ + #define REG_XDMAC_CUBC21 (*(__IO uint32_t*)0x400785B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 21) */ + #define REG_XDMAC_CBC21 (*(__IO uint32_t*)0x400785B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 21) */ + #define REG_XDMAC_CC21 (*(__IO uint32_t*)0x400785B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 21) */ + #define REG_XDMAC_CDS_MSP21 (*(__IO uint32_t*)0x400785BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 21) */ + #define REG_XDMAC_CSUS21 (*(__IO uint32_t*)0x400785C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 21) */ + #define REG_XDMAC_CDUS21 (*(__IO uint32_t*)0x400785C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 21) */ + #define REG_XDMAC_CIE22 (*(__O uint32_t*)0x400785D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 22) */ + #define REG_XDMAC_CID22 (*(__O uint32_t*)0x400785D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 22) */ + #define REG_XDMAC_CIM22 (*(__O uint32_t*)0x400785D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 22) */ + #define REG_XDMAC_CIS22 (*(__I uint32_t*)0x400785DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 22) */ + #define REG_XDMAC_CSA22 (*(__IO uint32_t*)0x400785E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 22) */ + #define REG_XDMAC_CDA22 (*(__IO uint32_t*)0x400785E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 22) */ + #define REG_XDMAC_CNDA22 (*(__IO uint32_t*)0x400785E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 22) */ + #define REG_XDMAC_CNDC22 (*(__IO uint32_t*)0x400785ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 22) */ + #define REG_XDMAC_CUBC22 (*(__IO uint32_t*)0x400785F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 22) */ + #define REG_XDMAC_CBC22 (*(__IO uint32_t*)0x400785F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 22) */ + #define REG_XDMAC_CC22 (*(__IO uint32_t*)0x400785F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 22) */ + #define REG_XDMAC_CDS_MSP22 (*(__IO uint32_t*)0x400785FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 22) */ + #define REG_XDMAC_CSUS22 (*(__IO uint32_t*)0x40078600U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 22) */ + #define REG_XDMAC_CDUS22 (*(__IO uint32_t*)0x40078604U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 22) */ + #define REG_XDMAC_CIE23 (*(__O uint32_t*)0x40078610U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 23) */ + #define REG_XDMAC_CID23 (*(__O uint32_t*)0x40078614U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 23) */ + #define REG_XDMAC_CIM23 (*(__O uint32_t*)0x40078618U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 23) */ + #define REG_XDMAC_CIS23 (*(__I uint32_t*)0x4007861CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 23) */ + #define REG_XDMAC_CSA23 (*(__IO uint32_t*)0x40078620U) /**< \brief (XDMAC) Channel Source Address Register (chid = 23) */ + #define REG_XDMAC_CDA23 (*(__IO uint32_t*)0x40078624U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 23) */ + #define REG_XDMAC_CNDA23 (*(__IO uint32_t*)0x40078628U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 23) */ + #define REG_XDMAC_CNDC23 (*(__IO uint32_t*)0x4007862CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 23) */ + #define REG_XDMAC_CUBC23 (*(__IO uint32_t*)0x40078630U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 23) */ + #define REG_XDMAC_CBC23 (*(__IO uint32_t*)0x40078634U) /**< \brief (XDMAC) Channel Block Control Register (chid = 23) */ + #define REG_XDMAC_CC23 (*(__IO uint32_t*)0x40078638U) /**< \brief (XDMAC) Channel Configuration Register (chid = 23) */ + #define REG_XDMAC_CDS_MSP23 (*(__IO uint32_t*)0x4007863CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 23) */ + #define REG_XDMAC_CSUS23 (*(__IO uint32_t*)0x40078640U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 23) */ + #define REG_XDMAC_CDUS23 (*(__IO uint32_t*)0x40078644U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 23) */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_XDMAC_INSTANCE_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/pio/pio_samv71j19.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/pio/pio_samv71j19.h new file mode 100644 index 00000000..4fba181e --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/pio/pio_samv71j19.h @@ -0,0 +1,438 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71J19_PIO_ +#define _SAMV71J19_PIO_ + +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for MLB peripheral ========== */ +#define PIO_PB4C_MLBCLK (1u << 4) /**< \brief Mlb signal: MLBCLK */ +#define PIO_PB5C_MLBDAT (1u << 5) /**< \brief Mlb signal: MLBDAT */ +#define PIO_PD10D_MLBSIG (1u << 10) /**< \brief Mlb signal: MLBSIG */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA24_IDX 24 +#define PIO_PA27_IDX 27 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD31_IDX 127 + +#endif /* _SAMV71J19_PIO_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/pio/pio_samv71j20.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/pio/pio_samv71j20.h new file mode 100644 index 00000000..a2c87403 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/pio/pio_samv71j20.h @@ -0,0 +1,442 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71J20_PIO_ +#define _SAMV71J20_PIO_ + +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for MLB peripheral ========== */ +#define PIO_PB4C_MLBCLK (1u << 4) /**< \brief Mlb signal: MLBCLK */ +#define PIO_PB5C_MLBDAT (1u << 5) /**< \brief Mlb signal: MLBDAT */ +#define PIO_PD10D_MLBSIG (1u << 10) /**< \brief Mlb signal: MLBSIG */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA24_IDX 24 +#define PIO_PA27_IDX 27 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD31_IDX 127 + +#endif /* _SAMV71J20_PIO_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/pio/pio_samv71j21.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/pio/pio_samv71j21.h new file mode 100644 index 00000000..277e631f --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/pio/pio_samv71j21.h @@ -0,0 +1,442 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71J21_PIO_ +#define _SAMV71J21_PIO_ + +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for MLB peripheral ========== */ +#define PIO_PB4C_MLBCLK (1u << 4) /**< \brief Mlb signal: MLBCLK */ +#define PIO_PB5C_MLBDAT (1u << 5) /**< \brief Mlb signal: MLBDAT */ +#define PIO_PD10D_MLBSIG (1u << 10) /**< \brief Mlb signal: MLBSIG */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA24_IDX 24 +#define PIO_PA27_IDX 27 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD31_IDX 127 + +#endif /* _SAMV71J21_PIO_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/pio/pio_samv71n19.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/pio/pio_samv71n19.h new file mode 100644 index 00000000..52144e7e --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/pio/pio_samv71n19.h @@ -0,0 +1,499 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71N19_PIO_ +#define _SAMV71N19_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for MLB peripheral ========== */ +#define PIO_PB4C_MLBCLK (1u << 4) /**< \brief Mlb signal: MLBCLK */ +#define PIO_PB5C_MLBDAT (1u << 5) /**< \brief Mlb signal: MLBDAT */ +#define PIO_PD10D_MLBSIG (1u << 10) /**< \brief Mlb signal: MLBSIG */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 + +#endif /* _SAMV71N19_PIO_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/pio/pio_samv71n20.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/pio/pio_samv71n20.h new file mode 100644 index 00000000..e0c50bf2 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/pio/pio_samv71n20.h @@ -0,0 +1,495 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71N20_PIO_ +#define _SAMV71N20_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for MLB peripheral ========== */ +#define PIO_PB4C_MLBCLK (1u << 4) /**< \brief Mlb signal: MLBCLK */ +#define PIO_PB5C_MLBDAT (1u << 5) /**< \brief Mlb signal: MLBDAT */ +#define PIO_PD10D_MLBSIG (1u << 10) /**< \brief Mlb signal: MLBSIG */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 + +#endif /* _SAMV71N20_PIO_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/pio/pio_samv71n21.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/pio/pio_samv71n21.h new file mode 100644 index 00000000..58d4e17c --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/pio/pio_samv71n21.h @@ -0,0 +1,495 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71N21_PIO_ +#define _SAMV71N21_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for MLB peripheral ========== */ +#define PIO_PB4C_MLBCLK (1u << 4) /**< \brief Mlb signal: MLBCLK */ +#define PIO_PB5C_MLBDAT (1u << 5) /**< \brief Mlb signal: MLBDAT */ +#define PIO_PD10D_MLBSIG (1u << 10) /**< \brief Mlb signal: MLBSIG */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 + +#endif /* _SAMV71N21_PIO_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/pio/pio_samv71q19.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/pio/pio_samv71q19.h new file mode 100644 index 00000000..5bdec5c8 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/pio/pio_samv71q19.h @@ -0,0 +1,672 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71Q19_PIO_ +#define _SAMV71Q19_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ +#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ +#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ +#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ +#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ +#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ +/* ========== PIO definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== PIO definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== PIO definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== PIO definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== PIO definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */ +#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */ +#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */ +#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */ +#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */ +#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */ +#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */ +#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */ +#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */ +/* ========== PIO definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== PIO definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== PIO definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== PIO definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== PIO definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== PIO definition for MLB peripheral ========== */ +#define PIO_PB4C_MLBCLK (1u << 4) /**< \brief Mlb signal: MLBCLK */ +#define PIO_PB5C_MLBDAT (1u << 5) /**< \brief Mlb signal: MLBDAT */ +#define PIO_PD10D_MLBSIG (1u << 10) /**< \brief Mlb signal: MLBSIG */ +/* ========== PIO definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== PIO definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== PIO definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== PIO definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== PIO definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== PIO definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== PIO definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== PIO definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== PIO definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== PIO definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== PIO definition for TC2 peripheral ========== */ +#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ +#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ +#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ +#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ +/* ========== PIO definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== PIO definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== PIO definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== PIO definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== PIO definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== PIO definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== PIO definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== PIO definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== PIO definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== PIO definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== PIO definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== PIO definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== PIO indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD23_IDX 119 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD29_IDX 125 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 +#define PIO_PE0_IDX 128 +#define PIO_PE1_IDX 129 +#define PIO_PE2_IDX 130 +#define PIO_PE3_IDX 131 +#define PIO_PE4_IDX 132 +#define PIO_PE5_IDX 133 + +#endif /* _SAMV71Q19_PIO_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/pio/pio_samv71q20.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/pio/pio_samv71q20.h new file mode 100644 index 00000000..cd9ea31e --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/pio/pio_samv71q20.h @@ -0,0 +1,672 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71Q20_PIO_ +#define _SAMV71Q20_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ +#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ +#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ +#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ +#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ +#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */ +#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */ +#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */ +#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */ +#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */ +#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */ +#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */ +#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */ +#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for MLB peripheral ========== */ +#define PIO_PB4C_MLBCLK (1u << 4) /**< \brief Mlb signal: MLBCLK */ +#define PIO_PB5C_MLBDAT (1u << 5) /**< \brief Mlb signal: MLBDAT */ +#define PIO_PD10D_MLBSIG (1u << 10) /**< \brief Mlb signal: MLBSIG */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TC2 peripheral ========== */ +#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ +#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ +#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ +#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD23_IDX 119 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD29_IDX 125 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 +#define PIO_PE0_IDX 128 +#define PIO_PE1_IDX 129 +#define PIO_PE2_IDX 130 +#define PIO_PE3_IDX 131 +#define PIO_PE4_IDX 132 +#define PIO_PE5_IDX 133 + +#endif /* _SAMV71Q20_PIO_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/pio/pio_samv71q21.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/pio/pio_samv71q21.h new file mode 100644 index 00000000..7a221e63 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/pio/pio_samv71q21.h @@ -0,0 +1,672 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71Q21_PIO_ +#define _SAMV71Q21_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ +#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ +#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ +#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ +#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ +#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */ +#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */ +#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */ +#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */ +#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */ +#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */ +#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */ +#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */ +#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for MLB peripheral ========== */ +#define PIO_PB4C_MLBCLK (1u << 4) /**< \brief Mlb signal: MLBCLK */ +#define PIO_PB5C_MLBDAT (1u << 5) /**< \brief Mlb signal: MLBDAT */ +#define PIO_PD10D_MLBSIG (1u << 10) /**< \brief Mlb signal: MLBSIG */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TC2 peripheral ========== */ +#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ +#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ +#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ +#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD23_IDX 119 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD29_IDX 125 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 +#define PIO_PE0_IDX 128 +#define PIO_PE1_IDX 129 +#define PIO_PE2_IDX 130 +#define PIO_PE3_IDX 131 +#define PIO_PE4_IDX 132 +#define PIO_PE5_IDX 133 + +#endif /* _SAMV71Q21_PIO_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/samv71.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/samv71.h new file mode 100644 index 00000000..91f3699b --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/samv71.h @@ -0,0 +1,55 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_ +#define _SAMV71_ + +#if defined __SAMV71J19__ + #include "samv71j19.h" +#elif defined __SAMV71J20__ + #include "samv71j20.h" +#elif defined __SAMV71J21__ + #include "samv71j21.h" +#elif defined __SAMV71N19__ + #include "samv71n19.h" +#elif defined __SAMV71N20__ + #include "samv71n20.h" +#elif defined __SAMV71N21__ + #include "samv71n21.h" +#elif defined __SAMV71Q19__ + #include "samv71q19.h" +#elif defined __SAMV71Q20__ + #include "samv71q20.h" +#elif defined __SAMV71Q21__ + #include "samv71q21.h" +#else + #error Library does not support the specified device. +#endif + +#endif /* _SAMV71_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/samv71j19.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/samv71j19.h new file mode 100644 index 00000000..aa09324f --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/samv71j19.h @@ -0,0 +1,633 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71J19_ +#define _SAMV71J19_ + +/** \addtogroup SAMV71J19_definitions SAMV71J19 definitions + This file defines all structures and symbols for SAMV71J19: + - registers and bit-fields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMV71J19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J19_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMV71J19 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMV71J19 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMV71J19 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMV71J19 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMV71J19 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMV71J19 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMV71J19 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMV71J19 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMV71J19 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMV71J19 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMV71J19 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMV71J19 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAMV71J19 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMV71J19 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMV71J19 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMV71J19 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAMV71J19 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMV71J19 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMV71J19 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMV71J19 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMV71J19 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMV71J19 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMV71J19 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMV71J19 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAMV71J19 Analog Front End 0 (AFEC0) */ + PWM0_IRQn = 31, /**< 31 SAMV71J19 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMV71J19 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMV71J19 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMV71J19 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAMV71J19 MCAN Controller 0 (MCAN0) */ + MCAN0_LINE1_IRQn = 36, /**< 36 SAMV71Q21 MCAN Controller 0 LINE1 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAMV71J19 MCAN Controller 1 (MCAN1) */ + MCAN1_LINE1_IRQn = 38, /**< 38 SAMV71Q21 MCAN Controller 1 LINE1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAMV71J19 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAMV71J19 Analog Front End 1 (AFEC1) */ + SPI1_IRQn = 42, /**< 42 SAMV71J19 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMV71J19 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMV71J19 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMV71J19 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMV71J19 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAMV71J19 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMV71J19 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMV71J19 Timer/Counter 11 (TC11) */ + MLB_IRQn = 53, /**< 53 SAMV71J19 MediaLB (MLB) */ + AES_IRQn = 56, /**< 56 SAMV71J19 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMV71J19 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMV71J19 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMV71J19 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMV71J19 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAMV71J19 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pvReserved30; + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pfnMCAN0_Line1_Handler; /* 36 MCAN Controller 0 */ + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pfnMCAN1_Line1_Handler; /* 38 MCAN Controller 1 */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pvReserved41; + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pfnMLB_Handler; /* 53 MediaLB */ + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN0_Line1_Handler( void ); +void MCAN1_Handler ( void ); +void MCAN1_Line1_Handler( void ); +void MLB_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMV71J19 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMV71J19 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMV71J19 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMV71J19 does provide a FPU */ +#define __FPU_DP 1 /**< SAMV71J19 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMV71J19 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMV71J19 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMV71J19 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMV71J19 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samv71.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71J19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J19_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_mlb.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMV71J19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J19_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_afec1.h" +#include "instance/instance_mlb.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMV71J19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J19_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_MLB (53) /**< \brief MediaLB (MLB) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMV71J19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J19_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB (0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMV71J19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J19_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_samv71j19.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMV71J19 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x80000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (32u) +#define IRAM_SIZE (0x40000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMV71J19 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA12D0A00UL) +#define CHIP_EXID (0x00000000UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMV71J19 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (26000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (52000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (78000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (104000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (131000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (150000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMV71J19_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/samv71j20.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/samv71j20.h new file mode 100644 index 00000000..8dbcc41c --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/samv71j20.h @@ -0,0 +1,640 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71J20_ +#define _SAMV71J20_ + +/** \addtogroup SAMV71J20_definitions SAMV71J20 definitions + This file defines all structures and symbols for SAMV71J20: + - registers and bit-fields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMV71J20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J20_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMV71J20 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMV71J20 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMV71J20 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMV71J20 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMV71J20 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMV71J20 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMV71J20 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMV71J20 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMV71J20 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMV71J20 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMV71J20 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMV71J20 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAMV71J20 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMV71J20 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMV71J20 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMV71J20 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAMV71J20 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMV71J20 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMV71J20 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMV71J20 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMV71J20 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMV71J20 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMV71J20 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMV71J20 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAMV71J20 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMV71J20 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMV71J20 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMV71J20 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMV71J20 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMV71J20 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAMV71J20 MCAN Controller 0 (MCAN0) */ + MCAN0_LINE1_IRQn = 36, /**< 36 SAMV71Q21 MCAN Controller 0 LINE1 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAMV71J20 MCAN Controller 1 (MCAN1) */ + MCAN1_LINE1_IRQn = 38, /**< 38 SAMV71Q21 MCAN Controller 1 LINE1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAMV71J20 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAMV71J20 Analog Front End 1 (AFEC1) */ + SPI1_IRQn = 42, /**< 42 SAMV71J20 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMV71J20 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMV71J20 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMV71J20 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMV71J20 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAMV71J20 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMV71J20 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMV71J20 Timer/Counter 11 (TC11) */ + MLB_IRQn = 53, /**< 53 SAMV71J20 MediaLB (MLB) */ + AES_IRQn = 56, /**< 56 SAMV71J20 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMV71J20 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMV71J20 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMV71J20 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMV71J20 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAMV71J20 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pfnMCAN0_Line1_Handler; /* 36 MCAN Controller 0 */ + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pfnMCAN1_Line1_Handler; /* 38 MCAN Controller 1 */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pvReserved41; + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pfnMLB_Handler; /* 53 MediaLB */ + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN0_Line1_Handler( void ); +void MCAN1_Handler ( void ); +void MCAN1_Line1_Handler( void ); +void MLB_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMV71J20 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMV71J20 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMV71J20 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMV71J20 does provide a FPU */ +#define __FPU_DP 1 /**< SAMV71J20 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMV71J20 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMV71J20 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMV71J20 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMV71J20 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samv71.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71J20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J20_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_mlb.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMV71J20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J20_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_afec1.h" +#include "instance/instance_mlb.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMV71J20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J20_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_MLB (53) /**< \brief MediaLB (MLB) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMV71J20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J20_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB (0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMV71J20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J20_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_samv71j20.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMV71J20 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x100000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (2048u) +#define IFLASH_NB_OF_LOCK_BITS (64u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMV71J20 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1220C00UL) +#define CHIP_EXID (0x00000000UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMV71J20 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (26000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (52000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (78000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (104000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (131000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (150000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMV71J20_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/samv71j21.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/samv71j21.h new file mode 100644 index 00000000..4d5c946a --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/samv71j21.h @@ -0,0 +1,639 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71J21_ +#define _SAMV71J21_ + +/** \addtogroup SAMV71J21_definitions SAMV71J21 definitions + This file defines all structures and symbols for SAMV71J21: + - registers and bit-fields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMV71J21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J21_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMV71J21 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMV71J21 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMV71J21 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMV71J21 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMV71J21 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMV71J21 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMV71J21 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMV71J21 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMV71J21 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMV71J21 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMV71J21 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMV71J21 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAMV71J21 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMV71J21 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMV71J21 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMV71J21 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAMV71J21 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMV71J21 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMV71J21 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMV71J21 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMV71J21 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMV71J21 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMV71J21 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMV71J21 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAMV71J21 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMV71J21 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMV71J21 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMV71J21 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMV71J21 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMV71J21 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAMV71J21 MCAN Controller 0 (MCAN0) */ + MCAN0_LINE1_IRQn = 36, /**< 36 SAMV71Q21 MCAN Controller 0 LINE1 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAMV71J21 MCAN Controller 1 (MCAN1) */ + MCAN1_LINE1_IRQn = 38, /**< 38 SAMV71Q21 MCAN Controller 1 LINE1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAMV71J21 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAMV71J21 Analog Front End 1 (AFEC1) */ + SPI1_IRQn = 42, /**< 42 SAMV71J21 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMV71J21 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMV71J21 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMV71J21 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMV71J21 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAMV71J21 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMV71J21 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMV71J21 Timer/Counter 11 (TC11) */ + MLB_IRQn = 53, /**< 53 SAMV71J21 MediaLB (MLB) */ + AES_IRQn = 56, /**< 56 SAMV71J21 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMV71J21 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMV71J21 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMV71J21 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMV71J21 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAMV71J21 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pfnMCAN0_Line1_Handler; /* 36 MCAN Controller 0 */ + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pfnMCAN1_Line1_Handler; /* 38 MCAN Controller 1 */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pvReserved41; + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pfnMLB_Handler; /* 53 MediaLB */ + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN0_Line1_Handler( void ); +void MCAN1_Handler ( void ); +void MCAN1_Line1_Handler( void ); +void MLB_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMV71J21 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMV71J21 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMV71J21 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMV71J21 does provide a FPU */ +#define __FPU_DP 1 /**< SAMV71J21 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMV71J21 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMV71J21 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMV71J21 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMV71J21 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samv71.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71J21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J21_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_mlb.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMV71J21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J21_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_afec1.h" +#include "instance/instance_mlb.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMV71J21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J21_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_MLB (53) /**< \brief MediaLB (MLB) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMV71J21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J21_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB (0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMV71J21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J21_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_samv71j21.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMV71J21 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x200000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (4096u) +#define IFLASH_NB_OF_LOCK_BITS (128u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMV71J21 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1220E00UL) +#define CHIP_EXID (0x00000000UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMV71J21 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (26000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (52000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (78000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (104000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (131000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (150000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMV71J21_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/samv71n19.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/samv71n19.h new file mode 100644 index 00000000..30abc83f --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/samv71n19.h @@ -0,0 +1,646 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71N19_ +#define _SAMV71N19_ + +/** \addtogroup SAMV71N19_definitions SAMV71N19 definitions + This file defines all structures and symbols for SAMV71N19: + - registers and bit-fields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMV71N19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N19_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMV71N19 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMV71N19 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMV71N19 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMV71N19 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMV71N19 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMV71N19 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMV71N19 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMV71N19 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMV71N19 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMV71N19 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMV71N19 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMV71N19 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAMV71N19 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMV71N19 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMV71N19 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMV71N19 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAMV71N19 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMV71N19 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMV71N19 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMV71N19 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMV71N19 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMV71N19 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMV71N19 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMV71N19 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAMV71N19 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMV71N19 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMV71N19 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMV71N19 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMV71N19 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMV71N19 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAMV71N19 MCAN Controller 0 (MCAN0) */ + MCAN0_LINE1_IRQn = 36, /**< 36 SAMV71Q21 MCAN Controller 0 LINE1 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAMV71N19 MCAN Controller 1 (MCAN1) */ + MCAN1_LINE1_IRQn = 38, /**< 38 SAMV71Q21 MCAN Controller 1 LINE1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAMV71N19 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAMV71N19 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAMV71N19 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAMV71N19 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMV71N19 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMV71N19 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMV71N19 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMV71N19 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAMV71N19 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMV71N19 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMV71N19 Timer/Counter 11 (TC11) */ + MLB_IRQn = 53, /**< 53 SAMV71N19 MediaLB (MLB) */ + AES_IRQn = 56, /**< 56 SAMV71N19 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMV71N19 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMV71N19 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMV71N19 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMV71N19 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAMV71N19 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pfnMCAN0_Line1_Handler; /* 36 MCAN Controller 0 */ + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pfnMCAN1_Line1_Handler; /* 38 MCAN Controller 1 */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pfnMLB_Handler; /* 53 MediaLB */ + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN0_Line1_Handler( void ); +void MCAN1_Handler ( void ); +void MCAN1_Line1_Handler( void ); +void MLB_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMV71N19 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMV71N19 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMV71N19 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMV71N19 does provide a FPU */ +#define __FPU_DP 1 /**< SAMV71N19 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMV71N19 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMV71N19 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMV71N19 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMV71N19 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samv71.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71N19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N19_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_mlb.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMV71N19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N19_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_mlb.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMV71N19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N19_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_MLB (53) /**< \brief MediaLB (MLB) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMV71N19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N19_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB (0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMV71N19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N19_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_samv71n19.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMV71N19 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x80000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (32u) +#define IRAM_SIZE (0x40000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMV71N19 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA12D0A00UL) +#define CHIP_EXID (0x00000001UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMV71N19 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (26000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (52000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (78000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (104000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (131000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (150000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMV71N19_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/samv71n20.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/samv71n20.h new file mode 100644 index 00000000..388123d9 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/samv71n20.h @@ -0,0 +1,639 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71N20_ +#define _SAMV71N20_ + +/** \addtogroup SAMV71N20_definitions SAMV71N20 definitions + This file defines all structures and symbols for SAMV71N20: + - registers and bit-fields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMV71N20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N20_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMV71N20 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMV71N20 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMV71N20 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMV71N20 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMV71N20 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMV71N20 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMV71N20 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMV71N20 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMV71N20 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMV71N20 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMV71N20 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMV71N20 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAMV71N20 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMV71N20 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMV71N20 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMV71N20 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAMV71N20 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMV71N20 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMV71N20 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMV71N20 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMV71N20 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMV71N20 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMV71N20 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMV71N20 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAMV71N20 Analog Front End 0 (AFEC0) */ + PWM0_IRQn = 31, /**< 31 SAMV71N20 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMV71N20 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMV71N20 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMV71N20 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAMV71N20 MCAN Controller 0 (MCAN0) */ + MCAN0_LINE1_IRQn = 36, /**< 36 SAMV71Q21 MCAN Controller 0 LINE1 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAMV71N20 MCAN Controller 1 (MCAN1) */ + MCAN1_LINE1_IRQn = 38, /**< 38 SAMV71Q21 MCAN Controller 1 LINE1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAMV71N20 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAMV71N20 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAMV71N20 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAMV71N20 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMV71N20 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMV71N20 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMV71N20 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMV71N20 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAMV71N20 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMV71N20 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMV71N20 Timer/Counter 11 (TC11) */ + MLB_IRQn = 53, /**< 53 SAMV71N20 MediaLB (MLB) */ + AES_IRQn = 56, /**< 56 SAMV71N20 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMV71N20 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMV71N20 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMV71N20 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMV71N20 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAMV71N20 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pvReserved30; + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pfnMCAN0_Line1_Handler; /* 36 MCAN Controller 0 */ + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pfnMCAN1_Line1_Handler; /* 38 MCAN Controller 1 */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pfnMLB_Handler; /* 53 MediaLB */ + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN0_Line1_Handler( void ); +void MCAN1_Handler ( void ); +void MCAN1_Line1_Handler( void ); +void MLB_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMV71N20 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMV71N20 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMV71N20 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMV71N20 does provide a FPU */ +#define __FPU_DP 1 /**< SAMV71N20 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMV71N20 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMV71N20 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMV71N20 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMV71N20 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samv71.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71N20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N20_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_mlb.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMV71N20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N20_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_mlb.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMV71N20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N20_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_MLB (53) /**< \brief MediaLB (MLB) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMV71N20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N20_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB (0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMV71N20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N20_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_samv71n20.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMV71N20 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x100000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (2048u) +#define IFLASH_NB_OF_LOCK_BITS (64u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMV71N20 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1220C00UL) +#define CHIP_EXID (0x00000001UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMV71N20 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (26000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (52000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (78000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (104000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (131000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (150000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMV71N20_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/samv71n21.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/samv71n21.h new file mode 100644 index 00000000..3159fc34 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/samv71n21.h @@ -0,0 +1,639 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71N21_ +#define _SAMV71N21_ + +/** \addtogroup SAMV71N21_definitions SAMV71N21 definitions + This file defines all structures and symbols for SAMV71N21: + - registers and bit-fields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMV71N21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N21_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMV71N21 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMV71N21 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMV71N21 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMV71N21 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMV71N21 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMV71N21 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMV71N21 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMV71N21 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMV71N21 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMV71N21 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMV71N21 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMV71N21 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAMV71N21 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMV71N21 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMV71N21 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMV71N21 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAMV71N21 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMV71N21 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMV71N21 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMV71N21 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMV71N21 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMV71N21 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMV71N21 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMV71N21 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAMV71N21 Analog Front End 0 (AFEC0) */ + PWM0_IRQn = 31, /**< 31 SAMV71N21 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMV71N21 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMV71N21 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMV71N21 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAMV71N21 MCAN Controller 0 (MCAN0) */ + MCAN0_LINE1_IRQn = 36, /**< 36 SAMV71Q21 MCAN Controller 0 LINE1 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAMV71N21 MCAN Controller 1 (MCAN1) */ + MCAN1_LINE1_IRQn = 38, /**< 38 SAMV71Q21 MCAN Controller 1 LINE1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAMV71N21 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAMV71N21 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAMV71N21 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAMV71N21 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMV71N21 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMV71N21 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMV71N21 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMV71N21 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAMV71N21 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMV71N21 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMV71N21 Timer/Counter 11 (TC11) */ + MLB_IRQn = 53, /**< 53 SAMV71N21 MediaLB (MLB) */ + AES_IRQn = 56, /**< 56 SAMV71N21 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMV71N21 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMV71N21 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMV71N21 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMV71N21 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAMV71N21 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pvReserved30; + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pfnMCAN0_Line1_Handler; /* 36 MCAN Controller 0 */ + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pfnMCAN1_Line1_Handler; /* 38 MCAN Controller 1 */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pfnMLB_Handler; /* 53 MediaLB */ + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN0_Line1_Handler( void ); +void MCAN1_Handler ( void ); +void MCAN1_Line1_Handler( void ); +void MLB_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMV71N21 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMV71N21 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMV71N21 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMV71N21 does provide a FPU */ +#define __FPU_DP 1 /**< SAMV71N21 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMV71N21 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMV71N21 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMV71N21 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMV71N21 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samv71.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71N21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N21_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_mlb.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMV71N21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N21_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_mlb.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMV71N21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N21_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_MLB (53) /**< \brief MediaLB (MLB) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMV71N21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N21_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB (0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMV71N21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N21_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_samv71n21.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMV71N21 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x200000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (4096u) +#define IFLASH_NB_OF_LOCK_BITS (128u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMV71N21 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1220E00UL) +#define CHIP_EXID (0x00000001UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMV71N21 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (26000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (52000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (78000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (104000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (131000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (150000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMV71N21_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/samv71q19.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/samv71q19.h new file mode 100644 index 00000000..a58298f2 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/samv71q19.h @@ -0,0 +1,694 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71Q19_ +#define _SAMV71Q19_ + +/** \addtogroup SAMV71Q19_definitions SAMV71Q19 definitions + This file defines all structures and symbols for SAMV71Q19: + - registers and bit-fields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMV71Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q19_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMV71Q19 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMV71Q19 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMV71Q19 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMV71Q19 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMV71Q19 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMV71Q19 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMV71Q19 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMV71Q19 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMV71Q19 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMV71Q19 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMV71Q19 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMV71Q19 Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 12, /**< 12 SAMV71Q19 Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 13, /**< 13 SAMV71Q19 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMV71Q19 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMV71Q19 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMV71Q19 Parallel I/O Controller D (PIOD) */ + PIOE_IRQn = 17, /**< 17 SAMV71Q19 Parallel I/O Controller E (PIOE) */ + HSMCI_IRQn = 18, /**< 18 SAMV71Q19 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMV71Q19 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMV71Q19 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMV71Q19 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMV71Q19 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMV71Q19 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMV71Q19 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMV71Q19 Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAMV71Q19 Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAMV71Q19 Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAMV71Q19 Timer/Counter 5 (TC5) */ + AFEC0_IRQn = 29, /**< 29 SAMV71Q19 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMV71Q19 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMV71Q19 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMV71Q19 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMV71Q19 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMV71Q19 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAMV71Q19 MCAN Controller 0 (MCAN0) */ + MCAN0_LINE1_IRQn = 36, /**< 36 SAMV71Q21 MCAN Controller 0 LINE1 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAMV71Q19 MCAN Controller 1 (MCAN1) */ + MCAN1_LINE1_IRQn = 38, /**< 38 SAMV71Q21 MCAN Controller 1 LINE1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAMV71Q19 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAMV71Q19 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAMV71Q19 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAMV71Q19 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMV71Q19 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMV71Q19 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMV71Q19 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMV71Q19 UART 4 (UART4) */ + TC6_IRQn = 47, /**< 47 SAMV71Q19 Timer/Counter 6 (TC6) */ + TC7_IRQn = 48, /**< 48 SAMV71Q19 Timer/Counter 7 (TC7) */ + TC8_IRQn = 49, /**< 49 SAMV71Q19 Timer/Counter 8 (TC8) */ + TC9_IRQn = 50, /**< 50 SAMV71Q19 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMV71Q19 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMV71Q19 Timer/Counter 11 (TC11) */ + MLB_IRQn = 53, /**< 53 SAMV71Q19 MediaLB (MLB) */ + AES_IRQn = 56, /**< 56 SAMV71Q19 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMV71Q19 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMV71Q19 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMV71Q19 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMV71Q19 Pulse Width Modulation 1 (PWM1) */ + SDRAMC_IRQn = 62, /**< 62 SAMV71Q19 SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 SAMV71Q19 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */ + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pfnMCAN0_Line1_Handler; /* 36 MCAN Controller 0 */ + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pfnMCAN1_Line1_Handler; /* 38 MCAN Controller 1 */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pfnTC6_Handler; /* 47 Timer/Counter 6 */ + void* pfnTC7_Handler; /* 48 Timer/Counter 7 */ + void* pfnTC8_Handler; /* 49 Timer/Counter 8 */ + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pfnMLB_Handler; /* 53 MediaLB */ + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */ + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN0_Line1_Handler( void ); +void MCAN1_Handler ( void ); +void MCAN1_Line1_Handler( void ); +void MLB_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMV71Q19 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMV71Q19 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMV71Q19 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMV71Q19 does provide a FPU */ +#define __FPU_DP 1 /**< SAMV71Q19 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMV71Q19 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMV71Q19 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMV71Q19 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMV71Q19 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samv71.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q19_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_mlb.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_sdramc.h" +#include "component/component_smc.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMV71Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q19_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_tc1.h" +#include "instance/instance_tc2.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_mlb.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_smc.h" +#include "instance/instance_sdramc.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_pioc.h" +#include "instance/instance_piod.h" +#include "instance/instance_pioe.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMV71Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q19_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */ +#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */ +#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_MLB (53) /**< \brief MediaLB (MLB) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMV71Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q19_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB (0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMV71Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q19_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_samv71q19.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMV71Q19 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x80000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (32u) +#define IRAM_SIZE (0x40000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMV71Q19 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA12D0A00UL) +#define CHIP_EXID (0x00000002UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMV71Q19 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (26000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (52000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (78000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (104000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (131000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (150000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMV71Q19_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/samv71q20.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/samv71q20.h new file mode 100644 index 00000000..34fd275b --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/samv71q20.h @@ -0,0 +1,693 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71Q20_ +#define _SAMV71Q20_ + +/** \addtogroup SAMV71Q20_definitions SAMV71Q20 definitions + This file defines all structures and symbols for SAMV71Q20: + - registers and bit-fields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMV71Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q20_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMV71Q20 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMV71Q20 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMV71Q20 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMV71Q20 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMV71Q20 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMV71Q20 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMV71Q20 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMV71Q20 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMV71Q20 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMV71Q20 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMV71Q20 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMV71Q20 Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 12, /**< 12 SAMV71Q20 Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 13, /**< 13 SAMV71Q20 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMV71Q20 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMV71Q20 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMV71Q20 Parallel I/O Controller D (PIOD) */ + PIOE_IRQn = 17, /**< 17 SAMV71Q20 Parallel I/O Controller E (PIOE) */ + HSMCI_IRQn = 18, /**< 18 SAMV71Q20 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMV71Q20 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMV71Q20 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMV71Q20 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMV71Q20 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMV71Q20 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMV71Q20 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMV71Q20 Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAMV71Q20 Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAMV71Q20 Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAMV71Q20 Timer/Counter 5 (TC5) */ + AFEC0_IRQn = 29, /**< 29 SAMV71Q20 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMV71Q20 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMV71Q20 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMV71Q20 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMV71Q20 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMV71Q20 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAMV71Q20 MCAN Controller 0 (MCAN0) */ + MCAN0_LINE1_IRQn = 36, /**< 36 SAMV71Q21 MCAN Controller 0 LINE1 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAMV71Q20 MCAN Controller 1 (MCAN1) */ + MCAN1_LINE1_IRQn = 38, /**< 38 SAMV71Q21 MCAN Controller 1 LINE1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAMV71Q20 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAMV71Q20 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAMV71Q20 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAMV71Q20 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMV71Q20 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMV71Q20 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMV71Q20 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMV71Q20 UART 4 (UART4) */ + TC6_IRQn = 47, /**< 47 SAMV71Q20 Timer/Counter 6 (TC6) */ + TC7_IRQn = 48, /**< 48 SAMV71Q20 Timer/Counter 7 (TC7) */ + TC8_IRQn = 49, /**< 49 SAMV71Q20 Timer/Counter 8 (TC8) */ + TC9_IRQn = 50, /**< 50 SAMV71Q20 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMV71Q20 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMV71Q20 Timer/Counter 11 (TC11) */ + MLB_IRQn = 53, /**< 53 SAMV71Q20 MediaLB (MLB) */ + AES_IRQn = 56, /**< 56 SAMV71Q20 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMV71Q20 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMV71Q20 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMV71Q20 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMV71Q20 Pulse Width Modulation 1 (PWM1) */ + SDRAMC_IRQn = 62, /**< 62 SAMV71Q20 SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 SAMV71Q20 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */ + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pfnMCAN0_Line1_Handler; /* 36 MCAN Controller 0 */ + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pfnMCAN1_Line1_Handler; /* 38 MCAN Controller 1 */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pfnTC6_Handler; /* 47 Timer/Counter 6 */ + void* pfnTC7_Handler; /* 48 Timer/Counter 7 */ + void* pfnTC8_Handler; /* 49 Timer/Counter 8 */ + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pfnMLB_Handler; /* 53 MediaLB */ + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */ + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN0_Line1_Handler( void ); +void MCAN1_Handler ( void ); +void MCAN1_Line1_Handler( void ); +void MLB_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMV71Q20 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMV71Q20 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMV71Q20 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMV71Q20 does provide a FPU */ +#define __FPU_DP 1 /**< SAMV71Q20 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMV71Q20 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMV71Q20 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMV71Q20 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMV71Q20 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samv71.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q20_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_mlb.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_sdramc.h" +#include "component/component_smc.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMV71Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q20_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_tc1.h" +#include "instance/instance_tc2.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_mlb.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_smc.h" +#include "instance/instance_sdramc.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_pioc.h" +#include "instance/instance_piod.h" +#include "instance/instance_pioe.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMV71Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q20_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */ +#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */ +#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_MLB (53) /**< \brief MediaLB (MLB) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMV71Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q20_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB (0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMV71Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q20_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_samv71q20.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMV71Q20 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x100000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (2048u) +#define IFLASH_NB_OF_LOCK_BITS (64u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMV71Q20 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1220C00UL) +#define CHIP_EXID (0x00000002UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMV71Q20 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (26000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (52000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (78000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (104000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (131000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (150000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMV71Q20_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/samv71q21.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/samv71q21.h new file mode 100644 index 00000000..6450c241 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/samv71q21.h @@ -0,0 +1,694 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71Q21_ +#define _SAMV71Q21_ + +/** \addtogroup SAMV71Q21_definitions SAMV71Q21 definitions + This file defines all structures and symbols for SAMV71Q21: + - registers and bit-fields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMV71Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q21_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMV71Q21 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMV71Q21 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMV71Q21 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMV71Q21 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMV71Q21 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMV71Q21 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMV71Q21 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMV71Q21 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMV71Q21 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMV71Q21 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMV71Q21 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMV71Q21 Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 12, /**< 12 SAMV71Q21 Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 13, /**< 13 SAMV71Q21 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMV71Q21 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMV71Q21 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMV71Q21 Parallel I/O Controller D (PIOD) */ + PIOE_IRQn = 17, /**< 17 SAMV71Q21 Parallel I/O Controller E (PIOE) */ + HSMCI_IRQn = 18, /**< 18 SAMV71Q21 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMV71Q21 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMV71Q21 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMV71Q21 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMV71Q21 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMV71Q21 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMV71Q21 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMV71Q21 Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAMV71Q21 Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAMV71Q21 Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAMV71Q21 Timer/Counter 5 (TC5) */ + AFEC0_IRQn = 29, /**< 29 SAMV71Q21 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMV71Q21 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMV71Q21 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMV71Q21 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMV71Q21 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMV71Q21 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAMV71Q21 MCAN Controller 0 (MCAN0) */ + MCAN0_LINE1_IRQn = 36, /**< 36 SAMV71Q21 MCAN Controller 0 LINE1 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAMV71Q21 MCAN Controller 1 (MCAN1) */ + MCAN1_LINE1_IRQn = 38, /**< 38 SAMV71Q21 MCAN Controller 1 LINE1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAMV71Q21 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAMV71Q21 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAMV71Q21 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAMV71Q21 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMV71Q21 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMV71Q21 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMV71Q21 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMV71Q21 UART 4 (UART4) */ + TC6_IRQn = 47, /**< 47 SAMV71Q21 Timer/Counter 6 (TC6) */ + TC7_IRQn = 48, /**< 48 SAMV71Q21 Timer/Counter 7 (TC7) */ + TC8_IRQn = 49, /**< 49 SAMV71Q21 Timer/Counter 8 (TC8) */ + TC9_IRQn = 50, /**< 50 SAMV71Q21 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMV71Q21 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMV71Q21 Timer/Counter 11 (TC11) */ + MLB_IRQn = 53, /**< 53 SAMV71Q21 MediaLB (MLB) */ + AES_IRQn = 56, /**< 56 SAMV71Q21 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMV71Q21 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMV71Q21 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMV71Q21 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMV71Q21 Pulse Width Modulation 1 (PWM1) */ + SDRAMC_IRQn = 62, /**< 62 SAMV71Q21 SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 SAMV71Q21 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */ + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pfnMCAN0_Line1_Handler; /* 36 MCAN Controller 0 */ + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pfnMCAN1_Line1_Handler; /* 38 MCAN Controller 1 */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pfnTC6_Handler; /* 47 Timer/Counter 6 */ + void* pfnTC7_Handler; /* 48 Timer/Counter 7 */ + void* pfnTC8_Handler; /* 49 Timer/Counter 8 */ + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pfnMLB_Handler; /* 53 MediaLB */ + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */ + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN0_Line1_Handler ( void ); +void MCAN1_Handler ( void ); +void MCAN1_Line1_Handler ( void ); +void MLB_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMV71Q21 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMV71Q21 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMV71Q21 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMV71Q21 does provide a FPU */ +#define __FPU_DP 1 /**< SAMV71Q21 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMV71Q21 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMV71Q21 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMV71Q21 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMV71Q21 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samv71.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q21_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_mlb.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_sdramc.h" +#include "component/component_smc.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMV71Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q21_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_tc1.h" +#include "instance/instance_tc2.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_mlb.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_smc.h" +#include "instance/instance_sdramc.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_pioc.h" +#include "instance/instance_piod.h" +#include "instance/instance_pioe.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMV71Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q21_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */ +#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */ +#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_MLB (53) /**< \brief MediaLB (MLB) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMV71Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q21_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB (0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMV71Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q21_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_samv71q21.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMV71Q21 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x200000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (4096u) +#define IFLASH_NB_OF_LOCK_BITS (128u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ +#define USBHS_RAM_ADDR (0xA0100000u)/**< USB RAM base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMV71Q21 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1220E00UL) +#define CHIP_EXID (0x00000002UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMV71Q21 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (26000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (52000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (78000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (104000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (131000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (150000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMV71Q21_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/system_samv71.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/system_samv71.h new file mode 100644 index 00000000..09092957 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/samv7/system_samv71.h @@ -0,0 +1,73 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef SYSTEM_SAMV71_H_INCLUDED +#define SYSTEM_SAMV71_H_INCLUDED + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/* @endcond */ + +#include + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + +/** + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void); + +/** + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void); + +/** + * Initialize flash. + */ +void system_init_flash(uint32_t dw_clk); + +void sysclk_enable_usb(void); +void sysclk_disable_usb(void); + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/* @endcond */ + +#endif /* SYSTEM_SAMV71_H_INCLUDED */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/sdramc.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/sdramc.h new file mode 100644 index 00000000..0ffb9cd2 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/sdramc.h @@ -0,0 +1,70 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Definitions and function prototype for SDRAMC. + */ + +// --------------------------------------------------------------------------- +// SDRAM +// --------------------------------------------------------------------------- +/** SDRAMC Configuration */ +#define EBI_SDRAMC_ADDR (0x70000000u) + +/** SDRAM bus width */ +#define BOARD_SDRAM_BUSWIDTH 16 + + +typedef struct _SSdramc_config +{ + uint32_t dwColumnBits ; // Number of Column Bits + uint32_t dwRowBits ; // Number of Row Bits + uint32_t dwBanks ; // Number of Banks + uint32_t dwCAS ; // CAS Latency + uint32_t dwDataBusWidth ; // Data Bus Width + uint32_t dwWriteRecoveryDelay ; // Write Recovery Delay + uint32_t dwRowCycleDelay_RowRefreshCycle ; // Row Cycle Delay and Row Refresh Cycle + uint32_t dwRowPrechargeDelay ; // Row Precharge Delay + uint32_t dwRowColumnDelay ; // Row to Column Delay + uint32_t dwActivePrechargeDelay ; // Active to Precharge Delay + uint32_t dwExitSelfRefreshActiveDelay ; // Exit Self Refresh to Active Delay + uint32_t dwBK1 ; // bk1 addr + +} SSdramc_config ; + +typedef struct _SSdramc_Memory +{ + SSdramc_config cfg ; + +} SSdramc_Memory ; + +extern void SDRAMC_Configure( SSdramc_Memory* pMemory, + uint32_t dwClockFrequency ) ; diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/smc.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/smc.h new file mode 100644 index 00000000..4bd303b8 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/smc.h @@ -0,0 +1,174 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** +* \file +* +* Definitions and function prototype for SMC module +*/ + +#ifndef _SMC_ +#define _SMC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ +typedef union _SmcStatus { + uint8_t BStatus; + struct _SmcStatusBits { + uint8_t smcSts:1, /**< NAND Flash Controller Status */ + xfrDone:1, /**< NFC Data Transfer Terminated */ + cmdDone:1, /**< Command Done */ + rbEdge: 1, /**< Ready/Busy Line 3 Edge Detected*/ + hammingReady:1; /**< Hamming ecc ready */ + } bStatus; +} SmcStatus; + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ +/* + * NFC definitions + */ + +/** Base address of NFC SRAM */ +#define NFC_SRAM_BASE_ADDRESS 0x200000 +/** Base address for NFC Address Command */ +#define NFC_CMD_BASE_ADDR 0x70000000 + + +/* -------- NFCADDR_CMD : NFC Address Command -------- */ +#define NFCADDR_CMD_CMD1 (0xFFu << 2) +/* Command Register Value for Cycle 1 */ +#define NFCADDR_CMD_CMD2 (0xFFu << 10) +/* Command Register Value for Cycle 2 */ +#define NFCADDR_CMD_VCMD2 (0x1u << 18) +/* Valid Cycle 2 Command */ +#define NFCADDR_CMD_ACYCLE (0x7u << 19) +/* Number of Address required for the current command */ +#define NFCADDR_CMD_ACYCLE_NONE (0x0u << 19) +/* No address cycle */ +#define NFCADDR_CMD_ACYCLE_ONE (0x1u << 19) +/* One address cycle */ +#define NFCADDR_CMD_ACYCLE_TWO (0x2u << 19) +/* Two address cycles */ +#define NFCADDR_CMD_ACYCLE_THREE (0x3u << 19) +/* Three address cycles */ +#define NFCADDR_CMD_ACYCLE_FOUR (0x4u << 19) +/* Four address cycles */ +#define NFCADDR_CMD_ACYCLE_FIVE (0x5u << 19) +/* Five address cycles */ +#define NFCADDR_CMD_CSID (0x7u << 22) +/* Chip Select Identifier */ +#define NFCADDR_CMD_CSID_0 (0x0u << 22) +/* CS0 */ +#define NFCADDR_CMD_CSID_1 (0x1u << 22) +/* CS1 */ +#define NFCADDR_CMD_CSID_2 (0x2u << 22) +/* CS2 */ +#define NFCADDR_CMD_CSID_3 (0x3u << 22) +/* CS3 */ +#define NFCADDR_CMD_CSID_4 (0x4u << 22) +/* CS4 */ +#define NFCADDR_CMD_CSID_5 (0x5u << 22) +/* CS5 */ +#define NFCADDR_CMD_CSID_6 (0x6u << 22) +/* CS6 */ +#define NFCADDR_CMD_CSID_7 (0x7u << 22) +/* CS7 */ +#define NFCADDR_CMD_DATAEN (0x1u << 25) +/* NFC Data Enable */ +#define NFCADDR_CMD_DATADIS (0x0u << 25) +/* NFC Data disable */ +#define NFCADDR_CMD_NFCRD (0x0u << 26) +/* NFC Read Enable */ +#define NFCADDR_CMD_NFCWR (0x1u << 26) +/* NFC Write Enable */ +#define NFCADDR_CMD_NFCCMD (0x1u << 27) +/* NFC Command Enable */ + +/* + * ECC definitions (Hsiao Code Errors) + */ + +/** A single bit was incorrect but has been recovered. */ +#define Hsiao_ERROR_SINGLEBIT 1 + +/** The original code has been corrupted. */ +#define Hsiao_ERROR_ECC 2 + +/** Multiple bits are incorrect in the data and they cannot be corrected. */ +#define Hsiao_ERROR_MULTIPLEBITS 3 + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/* + * NFC functions + */ + +extern void SMC_NFC_Configure(uint32_t mode); +extern void SMC_NFC_Reset(void); +extern void SMC_NFC_EnableNfc(void); +extern void SMC_NFC_EnableSpareRead(void); +extern void SMC_NFC_DisableSpareRead(void); +extern void SMC_NFC_EnableSpareWrite(void); +extern void SMC_NFC_DisableSpareWrite(void); +extern uint8_t SMC_NFC_isSpareRead(void); +extern uint8_t SMC_NFC_isSpareWrite(void); +extern uint8_t SMC_NFC_isTransferComplete(void); +extern uint8_t SMC_NFC_isReadyBusy(void); +extern uint8_t SMC_NFC_isNfcBusy(void); +extern uint32_t SMC_NFC_GetStatus(void); + +extern void SMC_NFC_SendCommand(uint32_t cmd, uint32_t addressCycle, + uint32_t cycle0); +extern void SMC_NFC_Wait_CommandDone(void); +extern void SMC_NFC_Wait_XfrDone(void); +extern void SMC_NFC_Wait_RBbusy(void); +extern void SMC_NFC_Wait_HammingReady(void); + +extern void SMC_ECC_Configure(uint32_t type, uint32_t pageSize); +extern uint32_t SMC_ECC_GetCorrectoinType(void); +extern uint8_t SMC_ECC_GetStatus(uint8_t eccNumber); + +extern void SMC_ECC_GetValue(uint32_t *ecc); +extern void SMC_ECC_GetEccParity(uint32_t pageDataSize, uint8_t *code, + uint8_t busWidth); +extern uint8_t SMC_ECC_VerifyHsiao(uint8_t *data, uint32_t size, + const uint8_t *originalCode, const uint8_t *verifyCode, uint8_t busWidth); + +#endif /* #ifndef _SMC_ */ + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/spi.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/spi.h new file mode 100644 index 00000000..2063c150 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/spi.h @@ -0,0 +1,114 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface for Serial Peripheral Interface (SPI) controller. + * + */ + +#ifndef _SPI_ +#define _SPI_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Macros + *----------------------------------------------------------------------------*/ + +/** + * + * Here are several macros which should be used when configuring a SPI + * peripheral. + * + * \section spi_configuration_macros SPI Configuration Macros + * - \ref SPI_PCS + * - \ref SPI_SCBR + * - \ref SPI_DLYBS + * - \ref SPI_DLYBCT + */ + +/** Calculate the PCS field value given the chip select NPCS value */ +#define SPI_PCS(npcs) SPI_MR_PCS((~(1 << npcs) & 0xF)) + +/** Calculates the value of the CSR SCBR field given the baudrate and MCK. */ +#define SPI_SCBR(baudrate, masterClock) \ + SPI_CSR_SCBR((uint32_t)(masterClock / baudrate)) + +/** Calculates the value of the CSR DLYBS field given the desired delay (in ns) */ +#define SPI_DLYBS(delay, masterClock) \ + SPI_CSR_DLYBS((uint32_t) (((masterClock / 1000000) * delay) / 1000)+1) + +/** Calculates the value of the CSR DLYBCT field given the desired delay (in ns) */ +#define SPI_DLYBCT(delay, masterClock) \ + SPI_CSR_DLYBCT ((uint32_t) (((masterClock / 1000000) * delay) / 32000)+1) + +/*------------------------------------------------------------------------------ */ + +#ifdef __cplusplus + extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void SPI_Enable( Spi* spi ) ; +extern void SPI_Disable( Spi* spi ) ; + +extern void SPI_EnableIt( Spi* spi, uint32_t dwSources ) ; +extern void SPI_DisableIt( Spi* spi, uint32_t dwSources ) ; + +extern void SPI_Configure( Spi* spi, uint32_t dwId, uint32_t dwConfiguration ) ; +extern void SPI_SetMode( Spi* spi, uint32_t dwConfiguration ); + +extern void SPI_ChipSelect( Spi* spi, uint8_t cS); +extern void SPI_ReleaseCS( Spi* spi ); + +extern void SPI_ConfigureNPCS( Spi* spi, uint32_t dwNpcs, uint32_t dwConfiguration ) ; +extern void SPI_ConfigureCSMode( Spi* spi, uint32_t dwNpcs, uint32_t bReleaseOnLast ); + +extern uint32_t SPI_Read( Spi* spi ) ; +extern void SPI_Write( Spi* spi, uint32_t dwNpcs, uint16_t wData ) ; +extern void SPI_WriteLast( Spi* spi, uint32_t dwNpcs, uint16_t wData ); + +extern uint32_t SPI_GetStatus( Spi* spi ) ; +extern uint32_t SPI_IsFinished( Spi* pSpi ) ; + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _SPI_ */ + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/spi_dma.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/spi_dma.h new file mode 100644 index 00000000..d9d8754d --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/spi_dma.h @@ -0,0 +1,148 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Implementation of SPI driver, transfer data through DMA. + * + */ + +#ifndef _SPI_DMA_ +#define _SPI_DMA_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +/** An unspecified error has occurred.*/ +#define SPID_ERROR 1 + +/** SPI driver is currently in use.*/ +#define SPID_ERROR_LOCK 2 + +/*---------------------------------------------------------------------------- + * Macros + *----------------------------------------------------------------------------*/ + +/** Calculates the value of the SCBR field of the Chip Select Register + given MCK and SPCK.*/ +#define SPID_CSR_SCBR(mck, spck) SPI_CSR_SCBR((mck) / (spck)) + +/** Calculates the value of the DLYBS field of the Chip Select Register + given delay in ns and MCK.*/ +#define SPID_CSR_DLYBS(mck, delay) SPI_CSR_DLYBS((((delay) * \ + ((mck) / 1000000)) / 1000) + 1) + +/** Calculates the value of the DLYBCT field of the Chip Select Register + given delay in ns and MCK.*/ +#define SPID_CSR_DLYBCT(mck, delay) SPI_CSR_DLYBCT((((delay) / 32 * \ + ((mck) / 1000000)) / 1000) + 1) + +#ifdef __cplusplus + extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** SPI transfer complete callback. */ +typedef void (*SpidCallback)( uint8_t, void* ) ; + +/** \brief Spi Transfer Request prepared by the application upper layer. + * + * This structure is sent to the SPI_SendCommand function to start the transfer. + * At the end of the transfer, the callback is invoked by the interrupt handler. + */ +typedef struct _SpidCmd +{ + /** Pointer to the Tx data. */ + uint8_t *pTxBuff; + /** Tx size in bytes. */ + uint8_t TxSize; + /** Pointer to the Rx data. */ + uint8_t *pRxBuff; + /** Rx size in bytes. */ + uint16_t RxSize; + /** SPI chip select. */ + uint8_t spiCs; + /** Callback function invoked at the end of transfer. */ + SpidCallback callback; + /** Callback arguments. */ + void *pArgument; +} SpidCmd ; + +/** Constant structure associated with SPI port. This structure prevents + client applications to have access in the same time. */ +typedef struct _Spid +{ + /** Pointer to SPI Hardware registers */ + Spi* pSpiHw ; + /** Current SpiCommand being processed */ + SpidCmd *pCurrentCommand ; + /** Pointer to DMA driver */ + sXdmad* pXdmad; + /** SPI Id as defined in the product datasheet */ + uint8_t spiId ; + /** Mutual exclusion semaphore. */ + volatile int8_t semaphore ; +} Spid ; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern uint32_t SPID_Configure( Spid* pSpid, + Spi* pSpiHw, + uint8_t spiId, + uint32_t SpiMode, + sXdmad* pXdmad ) ; + +extern void SPID_ConfigureCS( Spid* pSpid, uint32_t dwCS, uint32_t dwCsr ) ; + +extern uint32_t SPID_SendCommand( Spid* pSpid, SpidCmd* pCommand ) ; + +extern void SPID_Handler( Spid* pSpid ) ; + +extern void SPID_DmaHandler( Spid *pSpid ); + +extern uint32_t SPID_IsBusy( const Spid* pSpid ) ; + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _SPI_DMA_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/ssc.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/ssc.h new file mode 100644 index 00000000..8fbaf67e --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/ssc.h @@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface for Synchronous Serial (SSC) controller. + * + */ + +#ifndef _SSC_ +#define _SSC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +extern void SSC_Configure(Ssc *ssc, uint32_t bitRate, uint32_t masterClock); +extern void SSC_ConfigureTransmitter(Ssc *ssc, uint32_t tcmr, uint32_t tfmr); +extern void SSC_ConfigureReceiver(Ssc *ssc, uint32_t rcmr, uint32_t rfmr); +extern void SSC_EnableTransmitter(Ssc *ssc); +extern void SSC_DisableTransmitter(Ssc *ssc); +extern void SSC_EnableReceiver(Ssc *ssc); +extern void SSC_DisableReceiver(Ssc *ssc ); +extern void SSC_EnableInterrupts(Ssc *ssc, uint32_t sources); +extern void SSC_DisableInterrupts(Ssc *ssc, uint32_t sources); +extern void SSC_Write(Ssc *ssc, uint32_t frame); +extern uint32_t SSC_Read(Ssc *ssc ); +extern uint8_t SSC_IsRxReady(Ssc *ssc); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _SSC_ */ + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/supc.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/supc.h new file mode 100644 index 00000000..85133033 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/supc.h @@ -0,0 +1,75 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SUPC_H_ +#define _SUPC_H_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include + + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + + + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + extern "C" { +#endif + + + +void SUPC_SelectExtCrystal32K(void); +uint8_t SUPC_IsSlowClkExtCrystal32K(void); +uint8_t SUPC_Read_Status(uint32_t status); +void SUPC_DisableSupplyMonitor(void); +void SUPC_DisableVoltageReg(void); +void SUPC_ConfigSupplyMonitor(uint32_t Config); +void SUPC_BrownoutDetectEnable(uint8_t enable); +void SUPC_BrownoutResetEnable(void); +void SUPC_SramBackupMode(uint8_t enable); +void SUPC_BypassXtal32KOsc(void); +void SUPC_EnablesWakeupInput(uint32_t Input, uint8_t enable); +void SUPC_SetLowPowerDebounce(uint8_t period); +void SUPC_SetWakeupDebounce(uint8_t period); +void SUPC_EnablesWakeupMode(uint32_t Regs, uint8_t enable); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _PMC_ */ + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/tc.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/tc.h new file mode 100644 index 00000000..714f4d2c --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/tc.h @@ -0,0 +1,77 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \section Purpose + * + * Interface for configuring and using Timer Counter (TC) peripherals. + * + * \section Usage + * -# Optionally, use TC_FindMckDivisor() to let the program find the best + * TCCLKS field value automatically. + * -# Configure a Timer Counter in the desired mode using TC_Configure(). + * -# Start or stop the timer clock using TC_Start() and TC_Stop(). + */ + +#ifndef _TC_ +#define _TC_ + +/*------------------------------------------------------------------------------ + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*------------------------------------------------------------------------------ + * Global functions + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + extern "C" { +#endif + +extern void TC_Configure( Tc *pTc, uint32_t dwChannel, uint32_t dwMode ) ; + +extern void TC_Start( Tc *pTc, uint32_t dwChannel ) ; + +extern void TC_Stop( Tc *pTc, uint32_t dwChannel ) ; + +extern uint32_t TC_FindMckDivisor( uint32_t dwFreq, uint32_t dwMCk, + uint32_t *dwDiv, uint32_t *dwTcClks, uint32_t dwBoardMCK ) ; + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _TC_ */ + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/timetick.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/timetick.h new file mode 100644 index 00000000..7893a719 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/timetick.h @@ -0,0 +1,103 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \par Purpose + * + * Methods and definitions for Global time tick and wait functions. + * + * Defines a common and simplest use of Time Tick, to increase tickCount + * every 1ms, the application can get this value through GetTickCount(). + * + * \par Usage + * + * -# Configure the System Tick with TimeTick_Configure() when MCK changed + * \note + * Must be done before any invoke of GetTickCount(), Wait() or Sleep(). + * -# Uses GetTickCount to get current tick value. + * -# Uses Wait to wait several ms. + * -# Uses Sleep to enter wait for interrupt mode to wait several ms. + * + */ + +#ifndef _TIMETICK_ +#define _TIMETICK_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +typedef struct +{ + volatile uint32_t *pTimer1; + volatile uint32_t *pTimer2; + volatile uint32_t *pTimer3; + volatile uint32_t *pTimer4; +}SyTickDelayCounter_t; + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ +typedef struct _TimeEvent +{ + uint32_t event; + uint32_t time_tick; + uint32_t time_start; + uint32_t occur; + struct _TimeEvent *pPreEvent; + struct _TimeEvent *pNextEvent; +}TimeEvent; + +/*---------------------------------------------------------------------------- + * Global functions + *----------------------------------------------------------------------------*/ + +uint32_t TimeTick_Configure( void ) ; + +void TimeTick_Increment( uint32_t dwInc ) ; + +uint32_t GetDelayInTicks(uint32_t startTick,uint32_t endTick); + +uint32_t GetTicks(void); + +void Wait( volatile uint32_t dwMs ) ; + +void Sleep( volatile uint32_t dwMs ) ; + +extern void SetTimeEvent(TimeEvent* pEvent); + +#endif /* _TIMETICK_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/trace.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/trace.h new file mode 100644 index 00000000..9d765d57 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/trace.h @@ -0,0 +1,230 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \par Purpose + * + * Standard output methods for reporting debug information, warnings and + * errors, which can be easily be turned on/off. + * + * \par Usage + * -# Initialize the DBGU using TRACE_CONFIGURE() if you intend to eventually + * disable ALL traces; otherwise use DBGU_Configure(). + * -# Uses the TRACE_DEBUG(), TRACE_INFO(), TRACE_WARNING(), TRACE_ERROR() + * TRACE_FATAL() macros to output traces throughout the program. + * -# Each type of trace has a level : Debug 5, Info 4, Warning 3, Error 2 + * and Fatal 1. Disable a group of traces by changing the value of + * TRACE_LEVEL during compilation; traces with a level bigger than TRACE_LEVEL + * are not generated. To generate no trace, use the reserved value 0. + * -# Trace disabling can be static or dynamic. If dynamic disabling is selected + * the trace level can be modified in runtime. If static disabling is selected + * the disabled traces are not compiled. + * + * \par traceLevels Trace level description + * -# TRACE_DEBUG (5): Traces whose only purpose is for debugging the program, + * and which do not produce meaningful information otherwise. + * -# TRACE_INFO (4): Informational trace about the program execution. Should + * enable the user to see the execution flow. + * -# TRACE_WARNING (3): Indicates that a minor error has happened. In most case + * it can be discarded safely; it may even be expected. + * -# TRACE_ERROR (2): Indicates an error which may not stop the program execution, + * but which indicates there is a problem with the code. + * -# TRACE_FATAL (1): Indicates a major error which prevents the program from going + * any further. + */ + +#ifndef _TRACE_ +#define _TRACE_ + +/* + * Headers + */ + +#include "pio.h" + +#include + +/* + * Global Definitions + */ + +/** Softpack Version */ +#define SOFTPACK_VERSION "1.4" + +#define TRACE_LEVEL_DEBUG 5 +#define TRACE_LEVEL_INFO 4 +#define TRACE_LEVEL_WARNING 3 +#define TRACE_LEVEL_ERROR 2 +#define TRACE_LEVEL_FATAL 1 +#define TRACE_LEVEL_NO_TRACE 0 + +/* By default, all traces are output except the debug one. */ +#if !defined(TRACE_LEVEL) +#define TRACE_LEVEL TRACE_LEVEL_INFO +#endif + +/* By default, trace level is static (not dynamic) */ +#if !defined(DYN_TRACES) +#define DYN_TRACES 0 +#endif + +#if defined(NOTRACE) +#error "Error: NOTRACE has to be not defined !" +#endif + +#undef NOTRACE +#if (DYN_TRACES==0) + #if (TRACE_LEVEL == TRACE_LEVEL_NO_TRACE) + #define NOTRACE + #endif +#endif + + + +/* ------------------------------------------------------------------------------ + * Global Macros + * ------------------------------------------------------------------------------ + */ + +extern void TRACE_CONFIGURE( uint32_t dwBaudRate, uint32_t dwMCk ) ; + +/** + * Initializes the DBGU for ISP project + * + * \param mode DBGU mode. + * \param baudrate DBGU baudrate. + * \param mck Master clock frequency. + */ +#ifndef DYNTRACE +#define DYNTRACE 0 +#endif + +#if (TRACE_LEVEL==0) && (DYNTRACE==0) +#define TRACE_CONFIGURE_ISP(mode, baudrate, mck) {} +#else +#define TRACE_CONFIGURE_ISP(mode, baudrate, mck) { \ + const Pin pinsUART0[] = {PINS_UART}; \ + PIO_Configure(pinsUART0, PIO_LISTSIZE(pinsUART0)); \ + UART_Configure( baudrate, mck ) ; \ + } +#endif + +/** + * Outputs a formatted string using 'printf' if the log level is high + * enough. Can be disabled by defining TRACE_LEVEL=0 during compilation. + * \param ... Additional parameters depending on formatted string. + */ +#if defined(NOTRACE) + +/* Empty macro */ +#define TRACE_DEBUG(...) { } +#define TRACE_INFO(...) { } +#define TRACE_WARNING(...) { } +#define TRACE_ERROR(...) { } +#define TRACE_FATAL(...) { while(1); } + +#define TRACE_DEBUG_WP(...) { } +#define TRACE_INFO_WP(...) { } +#define TRACE_WARNING_WP(...) { } +#define TRACE_ERROR_WP(...) { } +#define TRACE_FATAL_WP(...) { while(1); } + +#elif (DYN_TRACES == 1) + +/* Trace output depends on dwTraceLevel value */ +#define TRACE_DEBUG(...) { if (dwTraceLevel >= TRACE_LEVEL_DEBUG) { printf("-D- " __VA_ARGS__); } } +#define TRACE_INFO(...) { if (dwTraceLevel >= TRACE_LEVEL_INFO) { printf("-I- " __VA_ARGS__); } } +#define TRACE_WARNING(...) { if (dwTraceLevel >= TRACE_LEVEL_WARNING) { printf("-W- " __VA_ARGS__); } } +#define TRACE_ERROR(...) { if (dwTraceLevel >= TRACE_LEVEL_ERROR) { printf("-E- " __VA_ARGS__); } } +#define TRACE_FATAL(...) { if (dwTraceLevel >= TRACE_LEVEL_FATAL) { printf("-F- " __VA_ARGS__); while(1); } } + +#define TRACE_DEBUG_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_DEBUG) { printf(__VA_ARGS__); } } +#define TRACE_INFO_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_INFO) { printf(__VA_ARGS__); } } +#define TRACE_WARNING_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_WARNING) { printf(__VA_ARGS__); } } +#define TRACE_ERROR_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_ERROR) { printf(__VA_ARGS__); } } +#define TRACE_FATAL_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_FATAL) { printf(__VA_ARGS__); while(1); } } + +#else + +/* Trace compilation depends on TRACE_LEVEL value */ +#if (TRACE_LEVEL >= TRACE_LEVEL_DEBUG) +#define TRACE_DEBUG(...) { printf("-D- " __VA_ARGS__); } +#define TRACE_DEBUG_WP(...) { printf(__VA_ARGS__); } +#else +#define TRACE_DEBUG(...) { } +#define TRACE_DEBUG_WP(...) { } +#endif + +#if (TRACE_LEVEL >= TRACE_LEVEL_INFO) +#define TRACE_INFO(...) { printf("-I- " __VA_ARGS__); } +#define TRACE_INFO_WP(...) { printf(__VA_ARGS__); } +#else +#define TRACE_INFO(...) { } +#define TRACE_INFO_WP(...) { } +#endif + +#if (TRACE_LEVEL >= TRACE_LEVEL_WARNING) +#define TRACE_WARNING(...) { printf("-W- " __VA_ARGS__); } +#define TRACE_WARNING_WP(...) { printf(__VA_ARGS__); } +#else +#define TRACE_WARNING(...) { } +#define TRACE_WARNING_WP(...) { } +#endif + +#if (TRACE_LEVEL >= TRACE_LEVEL_ERROR) +#define TRACE_ERROR(...) { printf("-E- " __VA_ARGS__); } +#define TRACE_ERROR_WP(...) { printf(__VA_ARGS__); } +#else +#define TRACE_ERROR(...) { } +#define TRACE_ERROR_WP(...) { } +#endif + +#if (TRACE_LEVEL >= TRACE_LEVEL_FATAL) +#define TRACE_FATAL(...) { printf("-F- " __VA_ARGS__); while(1); } +#define TRACE_FATAL_WP(...) { printf(__VA_ARGS__); while(1); } +#else +#define TRACE_FATAL(...) { while(1); } +#define TRACE_FATAL_WP(...) { while(1); } +#endif + +#endif + + +/** + * Exported variables + */ +/** Depending on DYN_TRACES, dwTraceLevel is a modifiable runtime variable or a define */ +#if !defined(NOTRACE) && (DYN_TRACES == 1) + extern uint32_t dwTraceLevel ; +#endif + +#endif //#ifndef TRACE_H + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/trng.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/trng.h new file mode 100644 index 00000000..29b28314 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/trng.h @@ -0,0 +1,50 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _TRNG_ +#define _TRNG_ + +/*------------------------------------------------------------------------------ + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +/*----------------------------------------------------------------------------*/ +/* Exported functions */ +/*----------------------------------------------------------------------------*/ + +void TRNG_Enable(void); +void TRNG_Disable(void); +void TRNG_EnableIt(void); +void TRNG_DisableIt(void); +uint32_t TRNG_GetStatus(void); +uint32_t TRNG_GetRandData(void); + +#endif /* #ifndef _TRNG_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/twi.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/twi.h new file mode 100644 index 00000000..6b848e40 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/twi.h @@ -0,0 +1,114 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface for configuration the Two Wire Interface (TWI) peripheral. + * + */ + +#ifndef _TWI_ +#define _TWI_ + +/*------------------------------------------------------------------------------ + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*---------------------------------------------------------------------------- + * Macros + *----------------------------------------------------------------------------*/ +/* Returns 1 if the TXRDY bit (ready to transmit data) is set in the given + status register value.*/ +#define TWI_STATUS_TXRDY(status) ((status & TWIHS_SR_TXRDY) == TWIHS_SR_TXRDY) + +/* Returns 1 if the RXRDY bit (ready to receive data) is set in the given + status register value.*/ +#define TWI_STATUS_RXRDY(status) ((status & TWIHS_SR_RXRDY) == TWIHS_SR_RXRDY) + +/* Returns 1 if the TXCOMP bit (transfer complete) is set in the given + status register value.*/ +#define TWI_STATUS_TXCOMP(status) ((status & TWIHS_SR_TXCOMP) == TWIHS_SR_TXCOMP) + +#ifdef __cplusplus + extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * External function + *----------------------------------------------------------------------------*/ + +extern void TWI_ConfigureMaster(Twihs *pTwi, uint32_t twck, uint32_t mck); + +extern void TWI_ConfigureSlave(Twihs *pTwi, uint8_t slaveAddress); + +extern void TWI_Stop(Twihs *pTwi); + +extern void TWI_StartRead( + Twihs *pTwi, + uint8_t address, + uint32_t iaddress, + uint8_t isize); + +extern uint8_t TWI_ReadByte(Twihs *pTwi); + +extern void TWI_WriteByte(Twihs *pTwi, uint8_t byte); + +extern void TWI_StartWrite( + Twihs *pTwi, + uint8_t address, + uint32_t iaddress, + uint8_t isize, + uint8_t byte); + +extern uint8_t TWI_ByteReceived(Twihs *pTwi); + +extern uint8_t TWI_ByteSent(Twihs *pTwi); + +extern uint8_t TWI_TransferComplete(Twihs *pTwi); + +extern void TWI_EnableIt(Twihs *pTwi, uint32_t sources); + +extern void TWI_DisableIt(Twihs *pTwi, uint32_t sources); + +extern uint32_t TWI_GetStatus(Twihs *pTwi); + +extern uint32_t TWI_GetMaskedStatus(Twihs *pTwi); + +extern void TWI_SendSTOPCondition(Twihs *pTwi); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _TWI_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/twid.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/twid.h new file mode 100644 index 00000000..23015097 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/twid.h @@ -0,0 +1,142 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _TWID_ +#define _TWID_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*---------------------------------------------------------------------------- + * Definition + *----------------------------------------------------------------------------*/ + +/** TWI driver is currently busy. */ +#define TWID_ERROR_BUSY 1 + + /** Transfer is still pending.*/ +#define ASYNC_STATUS_PENDING 0xFF +#ifdef __cplusplus + extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + + /*---------------------------------------------------------------------------- + * Type + *----------------------------------------------------------------------------*/ +/** \brief Asynchronous transfer descriptor. */ +typedef struct _Async +{ + /** Asynchronous transfer status.*/ + volatile uint32_t status ; + /** Callback function to invoke when transfer completes or fails.*/ + void *callback ; + /** Driver storage area; do not use.*/ + uint8_t pStorage[9] ; +} Async ; + +/** \brief TWI driver structure. Holds the internal state of the driver.*/ +typedef struct _Twid +{ + /** Pointer to the underlying TWI peripheral.*/ + Twihs *pTwi ; + /** Current asynchronous transfer being processed.*/ + Async *pTransfer ; +} Twid; + +/** \brief TWI driver structure. Holds the internal state of the driver.*/ +typedef struct +{ + uint8_t Twi_id; + /** Pointer to the underlying TWI driver.*/ + Twid *pTwid ; + /** Pointer to the underlying DMA driver for TWI.*/ + sXdmad *pTwiDma; +} TwihsDma; + +/*---------------------------------------------------------------------------- + * Export functions + *----------------------------------------------------------------------------*/ +extern void TWID_Initialize( Twid *pTwid, Twihs *pTwi ) ; +extern void TWID_DmaInitialize(TwihsDma *pTwidma, Twihs *pTwi, uint8_t bPolling); + +extern void TWID_Handler( Twid *pTwid ) ; + +extern uint32_t ASYNC_IsFinished( Async* pAsync ) ; + +extern uint8_t TWID_Read( + Twid *pTwid, + uint8_t address, + uint32_t iaddress, + uint8_t isize, + uint8_t *pData, + uint32_t num, + Async *pAsync); + +extern uint8_t TWID_Write( + Twid *pTwid, + uint8_t address, + uint32_t iaddress, + uint8_t isize, + uint8_t *pData, + uint32_t num, + Async *pAsync); + +extern uint8_t TWID_DmaRead( + TwihsDma *pTwiXdma, + uint8_t address, + uint32_t iaddress, + uint8_t isize, + uint8_t *pData, + uint32_t num, + Async *pAsync); + +extern uint8_t TWID_DmaWrite( + TwihsDma *pTwiXdma, + uint8_t address, + uint32_t iaddress, + uint8_t isize, + uint8_t *pData, + uint32_t num, + Async *pAsync); + +#ifdef __cplusplus +} +#endif + +#endif //#ifndef TWID_H + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/uart.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/uart.h new file mode 100644 index 00000000..aa3de6e6 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/uart.h @@ -0,0 +1,69 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + +#ifndef UART_H +#define UART_H + + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +void UART_Configure(Uart *uart, uint32_t mode, uint32_t baudrate, + uint32_t masterClock); + +void UART_SetTransmitterEnabled(Uart *uart, uint8_t enabled); + +void UART_SetReceiverEnabled(Uart *uart, uint8_t enabled); + +void UART_PutChar( Uart *uart, uint8_t c); + +uint32_t UART_IsRxReady(Uart *uart); + +uint8_t UART_GetChar(Uart *uart); + +uint32_t UART_GetStatus(Uart *uart); + +void UART_EnableIt(Uart *uart,uint32_t mode); + +void UART_DisableIt(Uart *uart,uint32_t mode); + +uint32_t UART_GetItMask(Uart *uart); + +void UART_SendBuffer(Uart *uart, uint8_t *pBuffer, uint32_t BuffLen); + +void UART_ReceiveBuffer(Uart *uart, uint8_t *pBuffer, uint32_t BuffLen); + +void UART_CompareConfig(Uart *uart, uint8_t Val1, uint8_t Val2); + +uint32_t UART_IsTxReady(Uart *uart); + +#endif //#ifndef UART_H + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/uart_dma.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/uart_dma.h new file mode 100644 index 00000000..9fe9a157 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/uart_dma.h @@ -0,0 +1,139 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Implementation of UART driver, transfer data through DMA. + * + */ + +#ifndef _UART_DMA_ +#define _UART_DMA_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +/** An unspecified error has occurred.*/ +#define UARTD_ERROR 1 + +/** UART driver is currently in use.*/ +#define UARTD_ERROR_LOCK 2 + + +#ifdef __cplusplus + extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** UART transfer complete callback. */ +typedef void (*UartdCallback)( uint8_t, void* ) ; + +/** \brief usart Transfer Request prepared by the application upper layer. + * + * This structure is sent to the UART_Send or UART_Rcv to start the transfer. + * At the end of the transfer, the callback is invoked by the interrupt handler. + */ +typedef struct +{ + /** Pointer to the Buffer. */ + uint8_t *pBuff; + /** Buff size in bytes. */ + uint32_t BuffSize; + /** Dma channel num. */ + uint32_t ChNum; + /** Callback function invoked at the end of transfer. */ + UartdCallback callback; + /** Callback arguments. */ + void *pArgument; + /** flag to indicate the current transfer. */ + volatile uint8_t sempaphore; + /* DMA LLI structure */ + LinkedListDescriporView1 *pLLIview; + /* DMA transfer type */ + eXdmadProgState dmaProgrammingMode; + /* DMA LLI size */ + uint16_t dmaBlockSize; + /* Flag using ring buffer or FiFo*/ + uint8_t dmaRingBuffer; +} UartChannel ; + +/** Constant structure associated with UART port. This structure prevents + client applications to have access in the same time. */ +typedef struct +{ + /** USART Id as defined in the product datasheet */ + uint8_t uartId ; + /** Pointer to DMA driver */ + sXdmad* pXdmad; + /** Pointer to UART Hardware registers */ + Uart* pUartHw ; + /** Current Uart Rx channel */ + UartChannel *pRxChannel ; + /** Current Uart Tx channel */ + UartChannel *pTxChannel ; +} UartDma; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +uint32_t UARTD_Configure( UartDma *pUartd , + uint8_t uartId, + uint32_t uartMode, + uint32_t baud, + uint32_t clk ); + +uint32_t UARTD_EnableTxChannels( UartDma *pUartd, UartChannel *pTxCh); + +uint32_t UARTD_EnableRxChannels( UartDma *pUartd, UartChannel *pRxCh); + +uint32_t UARTD_DisableTxChannels( UartDma *pUartd, UartChannel *pTxCh); + +uint32_t UARTD_DisableRxChannels( UartDma *pUartd, UartChannel *pRxCh); + +uint32_t UARTD_SendData( UartDma* pUartd ) ; + +uint32_t UARTD_RcvData( UartDma *pUartd); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _UART_DMA_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/usart.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/usart.h new file mode 100644 index 00000000..8469523a --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/usart.h @@ -0,0 +1,164 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \par Purpose + * + * This module provides several definitions and methods for using an USART + * peripheral. + * + * \par Usage + * + * -# Enable the USART peripheral clock in the PMC. + * -# Enable the required USART PIOs (see pio.h). + * -# Configure the UART by calling USART_Configure. + * -# Enable the transmitter and/or the receiver of the USART using + * USART_SetTransmitterEnabled and USART_SetReceiverEnabled. + * -# Send data through the USART using the USART_Write methods. + * -# Receive data from the USART using the USART_Read functions; the + * availability of data can be polled + * with USART_IsDataAvailable. + * -# Disable the transmitter and/or the receiver of the USART with + * USART_SetTransmitterEnabled and USART_SetReceiverEnabled. + */ + +#ifndef _USART_ +#define _USART_ + +/*------------------------------------------------------------------------------ + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*------------------------------------------------------------------------------ + * Definitions + *----------------------------------------------------------------------------*/ + +/** \section USART_mode USART modes + * This section lists several common operating modes for an USART peripheral. + * + * \b Modes + * - USART_MODE_ASYNCHRONOUS + * - USART_MODE_IRDA + */ + +/** Basic asynchronous mode, i.e. 8 bits no parity.*/ +#define USART_MODE_ASYNCHRONOUS (US_MR_CHRL_8_BIT | US_MR_PAR_NO) + +#define MAX_RX_TIMEOUT 131071 + +/** IRDA mode*/ +#define USART_MODE_IRDA \ + (US_MR_USART_MODE_IRDA | US_MR_CHRL_8_BIT | US_MR_PAR_NO | US_MR_FILTER) + +/** SPI mode*/ +#define AT91C_US_USMODE_SPIM 0xE +#define US_SPI_CPOL_0 (0x0<<16) +#define US_SPI_CPHA_0 (0x0<<8) +#define US_SPI_CPOL_1 (0x1<<16) +#define US_SPI_CPHA_1 (0x1<<8) +#define US_SPI_BPMODE_0 (US_SPI_CPOL_0|US_SPI_CPHA_1) +#define US_SPI_BPMODE_1 (US_SPI_CPOL_0|US_SPI_CPHA_0) +#define US_SPI_BPMODE_2 (US_SPI_CPOL_1|US_SPI_CPHA_1) +#define US_SPI_BPMODE_3 (US_SPI_CPOL_1|US_SPI_CPHA_0) + +#ifdef __cplusplus + extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Exported functions */ +/*------------------------------------------------------------------------------*/ + + +void USART_Configure( Usart *pUsart, uint32_t mode, uint32_t baudrate, + uint32_t masterClock ) ; + +void USART_SetBaudrate(Usart *pUsart, uint8_t OverSamp, uint32_t baudrate, + uint32_t masterClock); + +uint32_t USART_GetStatus( Usart *usart ) ; + + +void USART_ResetRx(Usart *pUsart); + +void USART_ResetTx(Usart *pUsart); + +void USART_EnableTx(Usart *pUsart); + +void USART_EnableRx(Usart *pUsart); + +void USART_DisableRx(Usart *pUsart); + +void USART_DisableTx(Usart *pUsart); + +void USART_EnableIt( Usart *usart,uint32_t mode ) ; + +void USART_DisableIt( Usart *usart,uint32_t mode ) ; + +uint32_t USART_GetItMask( Usart * usart ) ; + +void USART_SetTransmitterEnabled( Usart *usart, uint8_t enabled ) ; + +void USART_SetReceiverEnabled( Usart *usart, uint8_t enabled ) ; + +void USART_SetRTSEnabled(Usart *usart, uint8_t enabled); + +void USART_Write( Usart *usart, uint16_t data, volatile uint32_t timeOut ) ; + +uint16_t USART_Read( Usart *usart, volatile uint32_t timeOut ) ; + +uint8_t USART_IsDataAvailable( Usart *usart ) ; + +void USART_SetIrdaFilter(Usart *pUsart, uint8_t filter); + +void USART_PutChar( Usart *usart, uint8_t c ) ; + +uint32_t USART_IsRxReady( Usart *usart ) ; + +uint8_t USART_GetChar( Usart *usart ) ; + +void USART_EnableRecvTimeOut(Usart *usart, uint32_t timeout); + +void USART_EnableTxTimeGaurd(Usart *pUsart, uint32_t TimeGaurd); + +void USART_AcknowledgeRxTimeOut(Usart *usart, uint8_t Periodic); + + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _USART_ */ + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/usart_dma.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/usart_dma.h new file mode 100644 index 00000000..105b9578 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/usart_dma.h @@ -0,0 +1,139 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Implementation of USART driver, transfer data through DMA. + * + */ + +#ifndef _USART_DMA_H_ +#define _USART_DMA_H_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +/** An unspecified error has occurred.*/ +#define USARTD_ERROR 1 + +/** USART driver is currently in use.*/ +#define USARTD_ERROR_LOCK 2 + + +#ifdef __cplusplus + extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** USART transfer complete callback. */ +typedef void (*UsartdCallback)( uint8_t, void* ) ; + +/** \brief usart Transfer Request prepared by the application upper layer. + * + * This structure is sent to the USART_Send or USART_Rcv to start the transfer. + * At the end of the transfer, the callback is invoked by the interrupt handler. + */ +typedef struct +{ + /** Pointer to the Buffer. */ + uint8_t *pBuff; + /** Buff size in bytes. */ + uint32_t BuffSize; + /** Dma channel num. */ + uint8_t ChNum; + /** Callback function invoked at the end of transfer. */ + UsartdCallback callback; + /** Callback arguments. */ + void *pArgument; + /** flag to indicate the current transfer progress */ + volatile uint8_t dmaProgress; + /* DMA LLI structure */ + LinkedListDescriporView1 *pLLIview; + /* DMA transfer type */ + eXdmadProgState dmaProgrammingMode; + /* DMA LLI size or num of micro block*/ + uint16_t dmaBlockSize; + /* Flag using ring buffer or FiFo*/ + uint8_t dmaRingBuffer; +} UsartChannel ; + +/** Constant structure associated with USART port. This structure prevents + client applications to have access in the same time. */ +typedef struct +{ + /** USART Id as defined in the product datasheet */ + uint8_t usartId ; + /** Pointer to USART Hardware registers */ + Usart* pUsartHw ; + /** Current Usart Rx channel */ + UsartChannel *pRxChannel ; + /** Current Usart Tx channel */ + UsartChannel *pTxChannel ; + /** Pointer to DMA driver */ + sXdmad* pXdmad; +} UsartDma; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +uint32_t USARTD_Configure( UsartDma *pUsartd , + uint8_t USARTId, + uint32_t UsartMode, + uint32_t BaudRate, + uint32_t UsartClk); + +uint32_t USARTD_EnableTxChannels( UsartDma *pUsartd, UsartChannel *pTxCh); + +uint32_t USARTD_EnableRxChannels( UsartDma *pUsartd, UsartChannel *pRxCh); + +uint32_t USARTD_DisableTxChannels( UsartDma *pUsartd, UsartChannel *pTxCh); + +uint32_t USARTD_DisableRxChannels( UsartDma *pUsartd, UsartChannel *pTxCh); + +uint32_t USARTD_SendData( UsartDma* pUsartd ) ; + +uint32_t USARTD_RcvData( UsartDma *pUsartd); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _USART_DMA_ */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/usbhs.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/usbhs.h new file mode 100644 index 00000000..7a65059a --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/usbhs.h @@ -0,0 +1,1687 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2010, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +#ifndef USBHS_H +#define USBHS_H +/** addtogroup usbd_hal + *@{ + */ + +#define USB_DEVICE_HS_SUPPORT + +//! Control endpoint size +#define USB_DEVICE_EP_CTRL_SIZE 64 + +/** Indicates chip has an UDP High Speed. */ +#define CHIP_USB_UDP + +/** Indicates chip has an internal pull-up. */ +#define CHIP_USB_PULLUP_INTERNAL + +/** Number of USB endpoints */ +#define CHIP_USB_NUMENDPOINTS 10 + +/** Endpoints max packet size */ +#define CHIP_USB_ENDPOINTS_MAXPACKETSIZE(ep) \ + ((ep == 0) ? 64 : 1024) + +/** Endpoints Number of Bank */ +#define CHIP_USB_ENDPOINTS_BANKS(ep) ((ep==0)?1:((ep<=2)?3:2)) + + +#define CHIP_USB_ENDPOINTS_HBW(ep) ((((ep)>=1) &&((ep)<=2))?true:false) + +/** Endpoints DMA support */ +#define CHIP_USB_ENDPOINTS_DMA(ep) ((((ep)>=1)&&((ep)<=7))?true:false) + +/** Max size of the FMA FIFO */ +#define DMA_MAX_FIFO_SIZE (65536/1) +/** fifo space size in DW */ +#define EPT_VIRTUAL_SIZE 16384 + + + //! @name USBHS Host IP properties +//! +//! @{ +//! Get maximal number of endpoints +#define uhd_get_pipe_max_nbr() (9) +#define USBHS_EPT_NUM (uhd_get_pipe_max_nbr()+1) + //! Get maximal number of banks of endpoints +#define uhd_get_pipe_bank_max_nbr(ep) ((ep == 0) ? 1 : (( ep <= 2) ? 3 : 2)) + //! Get maximal size of endpoint (3X, 1024/64) +#define uhd_get_pipe_size_max(ep) (((ep) == 0) ? 64 : 1024) + //! Get DMA support of endpoints +#define Is_uhd_pipe_dma_supported(ep) ((((ep) >= 1) && ((ep) <= 6)) ? true : false) + //! Get High Band Width support of endpoints +#define Is_uhd_pipe_high_bw_supported(ep) (((ep) >= 2) ? true : false) +//! @} + +typedef enum +{ + HOST_MODE= 0, + DEVICE_MODE=1 +}USB_Mode_t; + +//! Maximum transfer size on USB DMA +#define UHD_PIPE_MAX_TRANS 0x8000 + +/** +================================= + USBHS_CTRL +================================= +**/ + +/** + * \brief Freeze or unfreeze USB clock + * \param pUsbhs Pointer to an USBHS instance. + * \param Enable Enable or disable + */ +__STATIC_INLINE void USBHS_FreezeClock(Usbhs *pUsbhs) +{ + pUsbhs->USBHS_CTRL |= USBHS_CTRL_FRZCLK; +} + +/** + * \brief Freeze or unfreeze USB clock + * \param pUsbhs Pointer to an USBHS instance. + * \param Enable Enable or disable + */ +__STATIC_INLINE void USBHS_UnFreezeClock(Usbhs *pUsbhs) +{ + pUsbhs->USBHS_CTRL &= ~((uint32_t)USBHS_CTRL_FRZCLK); +} +/** + * \brief Freeze or unfreeze USB clock + * \param pUsbhs Pointer to an USBHS instance. + * \param Enable Enable or disable + */ +__STATIC_INLINE void USBHS_VBusHWC(Usbhs *pUsbhs, uint8_t Enable) +{ + + if(!Enable) { + pUsbhs->USBHS_CTRL |= (1<<8); + } else { + pUsbhs->USBHS_CTRL &= ~((uint32_t)(1<<8)); + } +} + +/** + * \brief Enables or disables USB + * \param pUsbhs Pointer to an USBHS instance. + * \param Enable Enable or disable + */ + +__STATIC_INLINE void USBHS_UsbEnable(Usbhs *pUsbhs, uint8_t Enable) +{ + if(Enable) { + pUsbhs->USBHS_CTRL |= USBHS_CTRL_USBE; + } else { + pUsbhs->USBHS_CTRL &= ~((uint32_t)USBHS_CTRL_USBE); + } +} + + +/** + * \brief Device or Host Mode + * \param pUsbhs Pointer to an USBHS instance. + * \param Mode Device or Host Mode + */ + +__STATIC_INLINE void USBHS_UsbMode(Usbhs *pUsbhs, USB_Mode_t Mode) +{ + if(Mode) { + pUsbhs->USBHS_CTRL |= USBHS_CTRL_UIMOD_DEVICE; + } else { + pUsbhs->USBHS_CTRL &= ~((uint32_t)USBHS_CTRL_UIMOD_DEVICE); + } +} + +/********************* USBHS_SR *****************/ + +/** + * \brief Check if clock is usable or not + * \param pUsbhs Pointer to an USBHS instance. + * \return 1 if USB clock is usable + */ + +__STATIC_INLINE uint8_t USBHS_ISUsableClock(Usbhs *pUsbhs) +{ + return (( pUsbhs->USBHS_SR & USBHS_SR_CLKUSABLE) >> 14); +} + + +/** + * \brief Raise interrupt for endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \return USB status + */ + +__STATIC_INLINE uint32_t USBHS_ReadStatus(Usbhs *pUsbhs) +{ + return (pUsbhs->USBHS_SR); +} + +/** + * \brief Enable or disable USB address + * \param pUsbhs Pointer to an USBHS instance. + * \return USB speed status + */ + +__STATIC_INLINE uint32_t USBHS_GetUsbSpeed(Usbhs *pUsbhs) +{ + return ( (pUsbhs->USBHS_SR & USBHS_SR_SPEED_Msk) ); +} + + +/** + * \brief Enable or disable USB address + * \param pUsbhs Pointer to an USBHS instance. + * \return USB speed status + */ + +__STATIC_INLINE bool USBHS_IsUsbFullSpeed(Usbhs *pUsbhs) +{ + return ( (pUsbhs->USBHS_SR & USBHS_SR_SPEED_Msk) == USBHS_SR_SPEED_FULL_SPEED) ? true:false; +} + + +/** + * \brief Enable or disable USB address + * \param pUsbhs Pointer to an USBHS instance. + * \return USB speed status + */ + +__STATIC_INLINE bool USBHS_IsUsbHighSpeed(Usbhs *pUsbhs) +{ + return ( (pUsbhs->USBHS_SR & USBHS_SR_SPEED_Msk) == USBHS_SR_SPEED_HIGH_SPEED) ? true:false; +} + +/** + * \brief Enable or disable USB address + * \param pUsbhs Pointer to an USBHS instance. + * \return USB speed status + */ + +__STATIC_INLINE bool USBHS_IsUsbLowSpeed(Usbhs *pUsbhs) +{ + return ( (pUsbhs->USBHS_SR & USBHS_SR_SPEED_Msk) == USBHS_SR_SPEED_LOW_SPEED) ? true:false; +} +/********************* USBHS_SCR *****************/ + +/** + * \brief Raise interrupt for endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param AckType Interrupt Acknowledge type + */ + +__STATIC_INLINE void USBHS_Ack(Usbhs *pUsbhs, uint32_t AckType) +{ + pUsbhs->USBHS_SCR |= AckType; +} + +/********************* USBHS_SFR *****************/ + +/** + * \brief Raise interrupt for endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param SetStatus Set USB status + */ + +__STATIC_INLINE void USBHS_Set(Usbhs *pUsbhs, uint32_t SetStatus) +{ + pUsbhs->USBHS_SFR |= SetStatus; +} + + + /*-------------------------------------------------------- + * =========== USB Device functions ====================== + *---------------------------------------------------------*/ + +/** + * \brief Enable or disable USB address + * \param pUsbhs Pointer to an USBHS instance. + * \param SetStatus Set USB status + */ + +__STATIC_INLINE void USBHS_EnableAddress(Usbhs *pUsbhs, uint8_t Enable) +{ + if(Enable) { + pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_ADDEN; + } else { + pUsbhs->USBHS_DEVCTRL &= ~((uint32_t)USBHS_DEVCTRL_ADDEN); + } +} + +/** + * \brief Configure USB address and enable or disable it + * \param pUsbhs Pointer to an USBHS instance. + * \param Addr USB device status + */ + +__STATIC_INLINE void USBHS_SetAddress(Usbhs *pUsbhs, uint8_t Addr) +{ + pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_UADD(Addr); + pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_ADDEN; +} + +/** + * \brief Get USB address + * \param pUsbhs Pointer to an USBHS instance. + */ + +__STATIC_INLINE uint8_t USBHS_GetAddress(Usbhs *pUsbhs) +{ + return ( pUsbhs->USBHS_DEVCTRL & USBHS_DEVCTRL_UADD_Msk); +} + +/** + * \brief Attach or detach USB. + * \param pUsbhs Pointer to an USBHS instance. + * \param Enable Attachs or detach USB device + */ + +__STATIC_INLINE void USBHS_DetachUsb(Usbhs *pUsbhs, uint8_t Enable) +{ + if(Enable) { + pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_DETACH; + } else { + pUsbhs->USBHS_DEVCTRL &= ~((uint32_t)USBHS_DEVCTRL_DETACH); + } + +} + +/** + * \brief Force Low Speed mode + * \param pUsbhs Pointer to an USBHS instance. + * \param Enable Enables the Full speed + */ + +__STATIC_INLINE void USBHS_ForceLowSpeed(Usbhs *pUsbhs, uint8_t Enable) +{ + if(Enable) { + pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_LS; + } else { + pUsbhs->USBHS_DEVCTRL &= ~((uint32_t)USBHS_DEVCTRL_LS); + } +} + +/** + * \brief Disable/Enables High Speed mode + * \param pUsbhs Pointer to an USBHS instance. + * \param Enable Enables/disable option + */ + +__STATIC_INLINE void USBHS_EnableHighSpeed(Usbhs *pUsbhs, uint8_t Enable) +{ + uint32_t cfg = pUsbhs->USBHS_DEVCTRL; + cfg &= ~((uint32_t)USBHS_DEVCTRL_SPDCONF_Msk); + if(Enable) { + pUsbhs->USBHS_DEVCTRL |= cfg; + } else { + pUsbhs->USBHS_DEVCTRL |= (cfg | USBHS_DEVCTRL_SPDCONF_FORCED_FS); + } + +} + +/** + * \brief Set Remote WakeUp mode + * \param pUsbhs Pointer to an USBHS instance. + */ + +__STATIC_INLINE void USBHS_SetRemoteWakeUp(Usbhs *pUsbhs) +{ + pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_RMWKUP; +} + +/** + * \brief Disable/Enables Test mode + * \param pUsbhs Pointer to an USBHS instance. + * \param mode Enables/disable option + */ + +__STATIC_INLINE void USBHS_EnableTestMode(Usbhs *pUsbhs, uint32_t mode) +{ + pUsbhs->USBHS_DEVCTRL |= mode; +} + + +/** + * \brief Disable/Enables HS Test mode + * \param pUsbhs Pointer to an USBHS instance. + */ + +__STATIC_INLINE void USBHS_EnableHSTestMode(Usbhs *pUsbhs) +{ + pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_SPDCONF_HIGH_SPEED; +} + +/** + * \brief Read status for an interrupt + * \param pUsbhs Pointer to an USBHS instance. + * \param IntType Interrupt type + */ + +__STATIC_INLINE uint32_t USBHS_ReadIntStatus(Usbhs *pUsbhs, uint32_t IntType) +{ + return (pUsbhs->USBHS_DEVISR & IntType); +} + +/** + * \brief Read status for an Endpoint + * \param pUsbhs Pointer to an USBHS instance. + * \param EpNum Endpoint + */ + +__STATIC_INLINE uint32_t USBHS_ReadEpIntStatus(Usbhs *pUsbhs, uint8_t EpNum) +{ + return (pUsbhs->USBHS_DEVISR & ( USBHS_DEVISR_PEP_0 << EpNum) ); +} + +/** + * \brief Read status for a DMA Endpoint + * \param pUsbhs Pointer to an USBHS instance. + * \param DmaNum DMA Endpoint + */ +__STATIC_INLINE uint32_t USBHS_ReadDmaIntStatus(Usbhs *pUsbhs, uint8_t DmaNum) +{ + return (pUsbhs->USBHS_DEVISR & ( USBHS_DEVISR_DMA_1 << DmaNum) ); +} + +/** + * \brief Acknowledge interrupt for endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param IntType Interrupt Type + */ + +__STATIC_INLINE void USBHS_AckInt(Usbhs *pUsbhs, uint32_t IntType) +{ + pUsbhs->USBHS_DEVICR |= IntType; +} + +/** + * \brief Raise interrupt for endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param IntType Interrupt Type + */ + + +__STATIC_INLINE void USBHS_RaiseInt(Usbhs *pUsbhs, uint32_t IntType) +{ + pUsbhs->USBHS_DEVIFR |= IntType; +} + +/** + * \brief Raise DMA interrupt for endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param IntType Interrupt Type + */ +__STATIC_INLINE void USBHS_RaiseDmaInt(Usbhs *pUsbhs, uint8_t Dma) +{ + assert(Dma< USBHSDEVDMA_NUMBER); + pUsbhs->USBHS_DEVIFR |= ( USBHS_DEVIFR_DMA_1 << Dma ); +} + +/** + * \brief check for interrupt of endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param IntType Interrupt Type + */ + +__STATIC_INLINE uint32_t USBHS_IsIntEnable(Usbhs *pUsbhs, uint32_t IntType) +{ + return (pUsbhs->USBHS_DEVIMR & IntType); +} + +/** + * \brief Check if endpoint's interrupt is enabled for a given endpoint number + * \param pUsbhs Pointer to an USBHS instance. + * \param EpNum Endpoint number + */ + +__STATIC_INLINE uint32_t USBHS_IsIntEnableEP(Usbhs *pUsbhs, uint8_t EpNum) +{ + return (pUsbhs->USBHS_DEVIMR & (USBHS_DEVIMR_PEP_0 << EpNum )); +} + + +/** + * \brief Check if endpoint's DMA interrupt is enabled for a given endpoint + * DMA number + * \param pUsbhs Pointer to an USBHS instance. + * \param DmaNum Endpoint's DMA number + */ + +__STATIC_INLINE uint32_t USBHS_IsDmaIntEnable(Usbhs *pUsbhs, uint8_t DmaNum) +{ + return (pUsbhs->USBHS_DEVIMR & (USBHS_DEVIMR_DMA_1 << DmaNum)); +} + + +/** + * \brief Enables Interrupt + * \param pUsbhs Pointer to an USBHS instance. + * \param IntType Interrupt Type + */ +__STATIC_INLINE void USBHS_EnableInt(Usbhs *pUsbhs, uint32_t IntType) +{ + pUsbhs->USBHS_DEVIER |= IntType; +} + +/** + * \brief Enables interrupt for a given endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param DmaNum Endpoint's DMA number + */ +__STATIC_INLINE void USBHS_EnableIntEP(Usbhs *pUsbhs, uint8_t EpNum) +{ + pUsbhs->USBHS_DEVIER |= (USBHS_DEVIER_PEP_0 << EpNum); +} + +/** + * \brief Enables DMA interrupt for a given endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param DmaEp Endpoint's DMA interrupt number + */ + +__STATIC_INLINE void USBHS_EnableDMAIntEP(Usbhs *pUsbhs, uint32_t DmaEp) +{ + assert(DmaEp< USBHSDEVDMA_NUMBER); + pUsbhs->USBHS_DEVIER |= (USBHS_DEVIER_DMA_1 << DmaEp); +} + + /** + * \brief Disables interrupt for endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param IntType Int type + */ + +__STATIC_INLINE void USBHS_DisableInt(Usbhs *pUsbhs, uint32_t IntType) +{ + pUsbhs->USBHS_DEVIDR |= IntType; +} + + /** + * \brief Disables interrupt for endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param Ep Endpoint number + */ + +__STATIC_INLINE void USBHS_DisableIntEP(Usbhs *pUsbhs, uint8_t Ep) +{ + pUsbhs->USBHS_DEVIDR |= (USBHS_DEVIDR_PEP_0 << Ep); +} + + /** + * \brief Disables DMA interrupt for endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param DmaEp Endpoint's DMA number + */ +__STATIC_INLINE void USBHS_DisableDMAIntEP(Usbhs *pUsbhs, uint8_t DmaEp) +{ + assert(DmaEp< USBHSDEVDMA_NUMBER); + pUsbhs->USBHS_DEVIDR |= (USBHS_DEVIDR_DMA_1 << DmaEp); +} + + + /** + * \brief Enables or disables endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param Enable Enable/disable endpoint + */ + +__STATIC_INLINE void USBHS_EnableEP(Usbhs *pUsbhs, uint8_t Ep, uint8_t Enable) +{ + if(Enable) { + pUsbhs->USBHS_DEVEPT |= (USBHS_DEVEPT_EPEN0 << Ep); + } else { + pUsbhs->USBHS_DEVEPT &= ~(uint32_t)(USBHS_DEVEPT_EPEN0 << Ep); + } + +} + + + /** + * \brief Rests Endpoint + * \param pUsbhs Pointer to an USBHS instance. + * \param Ep Endpoint Number + */ + +__STATIC_INLINE void USBHS_ResetEP(Usbhs *pUsbhs, uint8_t Ep) +{ + pUsbhs->USBHS_DEVEPT |= (USBHS_DEVEPT_EPRST0 << Ep); + //pUsbhs->USBHS_DEVEPT &= ~(uint32_t)(USBHS_DEVEPT_EPRST0 << Ep); +} + + /** + * \brief Checks if Endpoint is enable + * \param pUsbhs Pointer to an USBHS instance. + * \param Ep Endpoint Number + */ + +__STATIC_INLINE uint32_t USBHS_IsEPEnabled(Usbhs *pUsbhs, uint8_t Ep) +{ + return (pUsbhs->USBHS_DEVEPT & (USBHS_DEVEPT_EPEN0 << Ep) ); +} + + /** + * \brief Get MicrFrame number + * \param pUsbhs Pointer to an USBHS instance. + * \retruns Micro frame number + */ +__STATIC_INLINE uint8_t USBHS_GetMicroFrameNum(Usbhs *pUsbhs) +{ + return (pUsbhs->USBHS_DEVFNUM & USBHS_DEVFNUM_MFNUM_Msk); +} + + + /** + * \brief Get Frame number + * \param pUsbhs Pointer to an USBHS instance. + * \retruns frame number + */ +__STATIC_INLINE uint8_t USBHS_GetFrameNum(Usbhs *pUsbhs) +{ + return ( (pUsbhs->USBHS_DEVFNUM & USBHS_DEVFNUM_FNUM_Msk) + >> USBHS_DEVFNUM_FNUM_Pos); +} + + /** + * \brief Get Frame number CRC error + * \param pUsbhs Pointer to an USBHS instance. + * \retruns Frame number error status + */ +__STATIC_INLINE uint8_t USBHS_GetFrameNumCrcErr(Usbhs *pUsbhs) +{ + return ( (pUsbhs->USBHS_DEVFNUM & USBHS_DEVFNUM_FNCERR) >> 15); +} + + /*----------------------------------------- + * =========== USB Device's Endpoint functions ======== + *------------------------------------------*/ + +/** + * Set Endpoints configuration + * Bank size, type and direction + */ +__STATIC_INLINE void USBHS_ConfigureEPs(Usbhs *pUsbhs, const uint8_t Ep, + const uint8_t Type, const uint8_t Dir, + const uint8_t Size, const uint8_t Bank) +{ + + pUsbhs->USBHS_DEVEPTCFG[Ep] |= + ((Size << USBHS_DEVEPTCFG_EPSIZE_Pos) & USBHS_DEVEPTCFG_EPSIZE_Msk); + pUsbhs->USBHS_DEVEPTCFG[Ep] |= + ((Dir << 8 ) & USBHS_DEVEPTCFG_EPDIR); + pUsbhs->USBHS_DEVEPTCFG[Ep] |= + (( (Type) << USBHS_DEVEPTCFG_EPTYPE_Pos) & USBHS_DEVEPTCFG_EPTYPE_Msk); + pUsbhs->USBHS_DEVEPTCFG[Ep] |= + (( (Bank) << USBHS_DEVEPTCFG_EPBK_Pos) & USBHS_DEVEPTCFG_EPBK_Msk); +} + + +/** + * Enable or disable Auto switch of banks + */ +__STATIC_INLINE void USBHS_AutoSwitchBankEnable(Usbhs *pUsbhs, uint8_t Ep, uint8_t Enable) +{ + if(Enable) { + pUsbhs->USBHS_DEVEPTCFG[Ep] |=USBHS_DEVEPTCFG_AUTOSW; + } else { + pUsbhs->USBHS_DEVEPTCFG[Ep] &= ~((uint32_t)USBHS_DEVEPTCFG_AUTOSW); + } +} + + +/** + * Allocate Endpoint memory + */ +__STATIC_INLINE void USBHS_AllocateMemory(Usbhs *pUsbhs, uint8_t Ep) +{ + pUsbhs->USBHS_DEVEPTCFG[Ep] |=USBHS_DEVEPTCFG_ALLOC; +} + + +/** + * Free allocated Endpoint memory + */ +__STATIC_INLINE void USBHS_FreeMemory(Usbhs *pUsbhs, uint8_t Ep) +{ + pUsbhs->USBHS_DEVEPTCFG[Ep] &= ~((uint32_t)USBHS_DEVEPTCFG_ALLOC); +} + + +/** + * Get Endpoint configuration + */ +__STATIC_INLINE uint32_t USBHS_GetConfigureEPs(Usbhs *pUsbhs, uint8_t Ep, + uint32_t IntType) +{ + return ((pUsbhs->USBHS_DEVEPTCFG[Ep] ) & IntType); +} + +/** + * Get Endpoint Type + */ +__STATIC_INLINE uint8_t USBHS_GetEpType(Usbhs *pUsbhs, uint8_t Ep) +{ + return ((pUsbhs->USBHS_DEVEPTCFG[Ep] & USBHS_DEVEPTCFG_EPTYPE_Msk) + >> USBHS_DEVEPTCFG_EPTYPE_Pos); +} + +/** + * Get Endpoint Size + */ +__STATIC_INLINE uint32_t USBHS_GetEpSize(Usbhs *pUsbhs, uint8_t Ep) +{ + return ( 8 << ( (pUsbhs->USBHS_DEVEPTCFG[Ep] & USBHS_DEVEPTCFG_EPSIZE_Msk) + >> USBHS_DEVEPTCFG_EPSIZE_Pos) ); +} + + +/** + * Sets ISO endpoint's Number of Transfer for High Speed + */ +__STATIC_INLINE void USBHS_SetIsoTrans(Usbhs *pUsbhs, uint8_t Ep, + uint8_t nbTrans) +{ + pUsbhs->USBHS_DEVEPTCFG[Ep] |= USBHS_DEVEPTCFG_NBTRANS(nbTrans) ; +} + +/** + * Check for interrupt types enabled for a given endpoint + */ +__STATIC_INLINE uint32_t USBHS_IsEpIntEnable(Usbhs *pUsbhs, uint8_t Ep, + uint32_t EpIntType) +{ + return (pUsbhs->USBHS_DEVEPTIMR[Ep] & EpIntType); +} + + +/** + * Enables an interrupt type for a given endpoint + */ +__STATIC_INLINE void USBHS_EnableEPIntType(Usbhs *pUsbhs, uint8_t Ep, + uint32_t EpInt) +{ + pUsbhs->USBHS_DEVEPTIER[Ep] |= EpInt; +} + +/** + * Enables an interrupt type for a given endpoint + */ +__STATIC_INLINE uint32_t USBHS_IsBankKilled(Usbhs *pUsbhs, uint8_t Ep) +{ + return (pUsbhs->USBHS_DEVEPTIMR[Ep] & USBHS_DEVEPTIMR_KILLBK); +} + +/** + * Enables an interrupt type for a given endpoint + */ +__STATIC_INLINE void USBHS_KillBank(Usbhs *pUsbhs, uint8_t Ep) +{ + pUsbhs->USBHS_DEVEPTIER[Ep] = USBHS_DEVEPTIER_KILLBKS; +} +/** + * Disables an interrupt type for a given endpoint + */ +__STATIC_INLINE void USBHS_DisableEPIntType(Usbhs *pUsbhs, uint8_t Ep, + uint32_t EpInt) +{ + pUsbhs->USBHS_DEVEPTIDR[Ep] |= EpInt; +} + +/** + * Clears register/acknowledge for a given endpoint + */ +__STATIC_INLINE void USBHS_AckEpInterrupt(Usbhs *pUsbhs, uint8_t Ep, uint32_t EpInt) +{ + pUsbhs->USBHS_DEVEPTICR[Ep] |= EpInt; +} + +/** + * Sets/Raise register for a given endpoint + */ +__STATIC_INLINE void USBHS_RaiseEPInt(Usbhs *pUsbhs, uint8_t Ep, uint32_t EpInt) +{ + pUsbhs->USBHS_DEVEPTIFR[Ep] |= EpInt; +} + +/** + * Gets interrupt status for a given EP + */ +__STATIC_INLINE uint32_t USBHS_ReadEPStatus(Usbhs *pUsbhs, uint8_t Ep, + uint32_t EpInt) +{ + return (pUsbhs->USBHS_DEVEPTISR[Ep] & EpInt); +} + +/** + * Check if given endpoint's bank is free + */ +__STATIC_INLINE uint8_t USBHS_IsBankFree(Usbhs *pUsbhs, uint8_t Ep) +{ + if( (pUsbhs->USBHS_DEVEPTISR[Ep] & USBHS_DEVEPTISR_NBUSYBK_Msk)) { + return false; + } else { + return true; + } +} + +/** + * Read endpoint's bank number in use + */ +__STATIC_INLINE uint8_t USBHS_NumOfBanksInUse(Usbhs *pUsbhs, uint8_t Ep) +{ + return ( (pUsbhs->USBHS_DEVEPTISR[Ep] & USBHS_DEVEPTISR_NBUSYBK_Msk) + >> USBHS_DEVEPTISR_NBUSYBK_Pos); +} + + +/** + * Read endpoint's bank number in use + */ +__STATIC_INLINE uint16_t USBHS_ByteCount(Usbhs *pUsbhs, uint8_t Ep) +{ + return (uint16_t)( (pUsbhs->USBHS_DEVEPTISR[Ep] & USBHS_DEVEPTISR_BYCT_Msk) + >> USBHS_DEVEPTISR_BYCT_Pos); +} + + /*-------------------------------------------------------- + * =========== USB Device's Ep's DMA functions ========= + *---------------------------------------------------------*/ + + /** + * \brief Sets DMA next descriptor address + * \param pUsbDma USBHS device DMA instance + * \param Desc NDA address + */ +__STATIC_INLINE void USBHS_SetDmaNDA(UsbhsDevdma *pUsbDma, uint32_t Desc) +{ + pUsbDma->USBHS_DEVDMANXTDSC = Desc; +} + + /** + * \brief Gets DMA next descriptor address + * \param pUsbDma USBHS device DMA instance + * \return Next DMA descriptor + */ +__STATIC_INLINE uint32_t USBHS_GetDmaNDA(UsbhsDevdma *pUsbDma) +{ + return (pUsbDma->USBHS_DEVDMANXTDSC); +} + + /** + * \brief Sets USBHS's DMA Buffer addresse + * \param pUsbDma USBHS device DMA instance + * \param Addr DMA's buffer Addrs + */ +__STATIC_INLINE void USBHS_SetDmaBuffAdd(UsbhsDevdma *pUsbDma, uint32_t Addr) +{ + pUsbDma->USBHS_DEVDMAADDRESS = Addr; +} + + + /** + * \brief Gets USBHS's DMA Buffer addresse + * \param pUsbDma USBHS device DMA instance + * \return DMA addrs + */ +__STATIC_INLINE uint32_t USBHS_GetDmaBuffAdd(UsbhsDevdma *pUsbDma) +{ + return (pUsbDma->USBHS_DEVDMAADDRESS); +} + + /** + * \brief Setup the USBHS DMA + * \param pUsbDma USBHS device DMA instance + * \param Cfg DMA's configuration + */ +__STATIC_INLINE void USBHS_ConfigureDma(UsbhsDevdma *pUsbDma, uint32_t Cfg) +{ + pUsbDma->USBHS_DEVDMACONTROL |= Cfg; +} + + /** + * \brief Get DMA configuration + * \param pUsbDma USBHS device DMA instance + * \return DMA control setup + */ +__STATIC_INLINE uint32_t USBHS_GetDmaConfiguration(UsbhsDevdma *pUsbDma) +{ + return (pUsbDma->USBHS_DEVDMACONTROL); +} + + + /** + * \brief Set DMA status + * \param pUsbDma USBHS device DMA instance + * \Status Set DMA status + */ +__STATIC_INLINE void USBHS_SetDmaStatus(UsbhsDevdma *pUsbDma, uint32_t Status) +{ + pUsbDma->USBHS_DEVDMASTATUS = Status; +} + + + /** + * \brief Get Dma Status + * \param pUsbDma USBHS device DMA instance + * \return Dma status + */ +__STATIC_INLINE uint32_t USBHS_GetDmaStatus(UsbhsDevdma *pUsbDma) +{ + return (pUsbDma->USBHS_DEVDMASTATUS); +} + + + /** + * \brief Get DMA buffer's count + * \param pUsbDma USBHS device DMA instance + * \return Buffer count + */ +__STATIC_INLINE uint16_t USBHS_GetDmaBuffCount(UsbhsDevdma *pUsbDma) +{ + return ( (pUsbDma->USBHS_DEVDMASTATUS & USBHS_DEVDMASTATUS_BUFF_COUNT_Msk) + >> USBHS_DEVDMASTATUS_BUFF_COUNT_Pos); +} + + + /*-------------------------------------------------------- + * =========== USB Host Functions ======================== + *---------------------------------------------------------*/ + +/** Number of USB endpoints */ +#define CHIP_USB_NUMPIPE 10 +/** Number of USB endpoints */ +#define CHIP_USB_DMA_NUMPIPE 7 + +/** Endpoints max paxcket size */ +#define CHIP_USB_PIPE_MAXPACKETSIZE(ep) \ + ((ep == 0) ? 64 : 1024) + +/** Endpoints Number of Bank */ +#define CHIP_USB_PIPE_BANKS(ep) ((ep==0)?1:((ep<=2)?3:2)) + + +#define CHIP_USB_PIPE_HBW(ep) ((((ep)>=1) &&((ep)<=2))?true:false) + +/** Endpoints DMA support */ +#define CHIP_USB_PIPE_DMA(ep) ((((ep)>=1)&&((ep)<=7))?true:false) + + /** + * \brief Sets USB host's speed to Normal , it sets to HS from FS + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_SetHostHighSpeed(Usbhs *pUsbhs) +{ + pUsbhs->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_SPDCONF_Msk; + pUsbhs->USBHS_HSTCTRL |= USBHS_HSTCTRL_SPDCONF_NORMAL; +} + + /** + * \brief Sets USB host's speed to Low speed + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_SetHostLowSpeed(Usbhs *pUsbhs) +{ + pUsbhs->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_SPDCONF_Msk; + pUsbhs->USBHS_HSTCTRL |= USBHS_HSTCTRL_SPDCONF_LOW_POWER; +} + + /** + * \brief Sets USB host's speed to forced Full speed + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_SetHostForcedFullSpeed(Usbhs *pUsbhs) +{ + pUsbhs->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_SPDCONF_Msk; + pUsbhs->USBHS_HSTCTRL |= USBHS_HSTCTRL_SPDCONF_FORCED_FS; +} + + /** + * \brief Sets USB host sends reste signal on USB Bus + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_Reset(void) +{ + USBHS->USBHS_HSTCTRL |= USBHS_HSTCTRL_RESET; +} + + /** + * \brief Sets USB host sends reste signal on USB Bus + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_StopReset(void) +{ + USBHS->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_RESET; +} + + /** + * \brief Sets USB host send Resume on USB bus + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_Resume(void) +{ + USBHS->USBHS_HSTCTRL |= USBHS_HSTCTRL_RESUME; +} + + /** + * \brief Sets USB host Enable the Generation of Start of Frame + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_EnableSOF(Usbhs *pUsbhs) +{ + pUsbhs->USBHS_HSTCTRL |= USBHS_HSTCTRL_SOFE; +} + + /** + * \brief Sets USB host Enable the Generation of Start of Frame + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint8_t USBHS_IsEnableSOF(Usbhs *pUsbhs) +{ + return (pUsbhs->USBHS_HSTCTRL & USBHS_HSTCTRL_SOFE) >> 8; +} + /** + * \brief Sets USB host disable the Generation of Start of Frame + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_DisableSOF(void) +{ + USBHS->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_SOFE; +} + + /** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_GetHostStatus(Usbhs *pUsbhs, uint8_t IntType) +{ + return (pUsbhs->USBHS_HSTISR & IntType); +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_GetHostPipeStatus(Usbhs *pUsbhs, uint8_t PipeInt) +{ + assert( PipeInt < CHIP_USB_NUMPIPE); + return (pUsbhs->USBHS_HSTISR & ( USBHS_HSTISR_PEP_0 << PipeInt) ); +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_GetHostDmaPipeStatus(Usbhs *pUsbhs, uint8_t PipeInt) +{ + assert( PipeInt); + assert( PipeInt < CHIP_USB_DMA_NUMPIPE); + return (pUsbhs->USBHS_HSTISR & ( USBHS_HSTISR_DMA_1 << PipeInt) ); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_ClearHostStatus(Usbhs *pUsbhs, uint32_t IntType) +{ + pUsbhs->USBHS_HSTICR = IntType; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_SetHostStatus(Usbhs *pUsbhs, uint32_t IntType) +{ + pUsbhs->USBHS_HSTIFR = IntType; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_SetHostDmaStatus(Usbhs *pUsbhs, uint8_t PipeInt) +{ + assert( PipeInt); + assert( PipeInt < CHIP_USB_DMA_NUMPIPE); + pUsbhs->USBHS_HSTIFR = (USBHS_HSTIFR_DMA_1 << PipeInt) ; +} + +/*** Interrupt Mask ****/ +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint8_t USBHS_IsHostIntEnable(Usbhs *pUsbhs, uint8_t IntType) +{ + return (pUsbhs->USBHS_HSTIMR & IntType) ; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_IsHostPipeIntEnable(Usbhs *pUsbhs, uint8_t PipeInt) +{ + assert( PipeInt < CHIP_USB_NUMPIPE); + return ( pUsbhs->USBHS_HSTIMR & (USBHS_HSTIMR_PEP_0 << PipeInt) ); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_IsHostDmaIntEnable(Usbhs *pUsbhs, uint8_t PipeInt) +{ + assert( PipeInt); + assert( PipeInt < CHIP_USB_DMA_NUMPIPE); + return ( pUsbhs->USBHS_HSTIMR & (USBHS_HSTIMR_DMA_1 << PipeInt) ); +} + +/*** Interrupt Disable ****/ +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostIntDisable(Usbhs *pUsbhs, uint32_t IntType) +{ + pUsbhs->USBHS_HSTIDR = IntType ; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostPipeIntDisable(Usbhs *pUsbhs, uint8_t PipeInt) +{ + assert( PipeInt < CHIP_USB_NUMPIPE); + pUsbhs->USBHS_HSTIDR = (USBHS_HSTIDR_PEP_0 << PipeInt); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostDmaIntDisable(Usbhs *pUsbhs, uint8_t PipeInt) +{ + assert( PipeInt); + assert( PipeInt < CHIP_USB_DMA_NUMPIPE); + pUsbhs->USBHS_HSTIDR = (USBHS_HSTIDR_DMA_1 << PipeInt) ; +} + +/*** Interrupt Enable ****/ + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostIntEnable(Usbhs *pUsbhs, uint32_t IntType) +{ + pUsbhs->USBHS_HSTIER = IntType ; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostPipeIntEnable(Usbhs *pUsbhs, uint8_t PipeInt) +{ + assert( PipeInt < CHIP_USB_NUMPIPE); + pUsbhs->USBHS_HSTIER =(USBHS_HSTIER_PEP_0 << PipeInt) ; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostDmaIntEnable(Usbhs *pUsbhs, uint8_t PipeInt) +{ + assert( PipeInt < CHIP_USB_DMA_NUMPIPE); + pUsbhs->USBHS_HSTIER |= (USBHS_HSTIER_DMA_1 << PipeInt); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint16_t USBHS_HostGetSOF(void) +{ + return ( (USBHS->USBHS_HSTFNUM & USBHS_HSTFNUM_FNUM_Msk) >> USBHS_HSTFNUM_FNUM_Pos); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint16_t USBHS_HostGetFramePos(void) +{ + return ( (USBHS->USBHS_HSTFNUM & USBHS_HSTFNUM_FLENHIGH_Msk) >> USBHS_HSTFNUM_FLENHIGH_Pos); +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint16_t USBHS_HostGetMSOF(void) +{ + return ( (USBHS->USBHS_HSTFNUM & USBHS_HSTFNUM_MFNUM_Msk) >> USBHS_HSTFNUM_MFNUM_Pos); +} + +__STATIC_INLINE void USBHS_HostSetAddr(Usbhs *pUsbhs, uint8_t Pipe, uint8_t Addr) +{ + assert( Pipe < CHIP_USB_NUMPIPE); + if (Pipe <4) + { + pUsbhs->USBHS_HSTADDR1 |= (Addr << (8*Pipe)); + } + else if( (Pipe <8) && (Pipe >=4)) + { + pUsbhs->USBHS_HSTADDR2 |= (Addr << (8* (Pipe -4))); + } + else + { + pUsbhs->USBHS_HSTADDR3 |= (Addr << (8*(Pipe -8))); + } + +} + +__STATIC_INLINE uint8_t USBHS_HostGetAddr(Usbhs *pUsbhs, uint8_t Pipe) +{ + assert( Pipe < CHIP_USB_NUMPIPE); + if (Pipe <4) + { + return ( pUsbhs->USBHS_HSTADDR1 >> (8*Pipe)) ; + } + else if( (Pipe <8) && (Pipe >=4)) + { + return (pUsbhs->USBHS_HSTADDR2 >> (8*(Pipe -4))); + } + else + { + return (pUsbhs->USBHS_HSTADDR3 >> (8*(Pipe -8))); + } + +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostPipeEnable(Usbhs *pUsbhs, uint8_t Pipe) +{ + assert( Pipe < CHIP_USB_NUMPIPE); + pUsbhs->USBHS_HSTPIP |= (USBHS_HSTPIP_PEN0 << Pipe); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostPipeDisable(Usbhs *pUsbhs, uint8_t Pipe) +{ + assert( Pipe < CHIP_USB_NUMPIPE); + pUsbhs->USBHS_HSTPIP &= ~(USBHS_HSTPIP_PEN0 << Pipe); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_IsHostPipeEnable(Usbhs *pUsbhs, uint8_t Pipe) +{ + assert( Pipe < CHIP_USB_NUMPIPE); + return (pUsbhs->USBHS_HSTPIP &(USBHS_HSTPIP_PEN0 << Pipe)); +} +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostPipeReset(Usbhs *pUsbhs, uint8_t Pipe) +{ + assert( Pipe < CHIP_USB_NUMPIPE); + pUsbhs->USBHS_HSTPIP |= (USBHS_HSTPIP_PRST0 << Pipe); + pUsbhs->USBHS_HSTPIP &= ~(USBHS_HSTPIP_PRST0 << Pipe); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostConfigure(Usbhs *pUsbhs, uint8_t Pipe, uint32_t pipeBank, uint8_t pipeSize, uint32_t pipeType, uint32_t pipeToken, uint8_t pipeEpNum, uint8_t PipeIntFreq) +{ + assert( Pipe < CHIP_USB_NUMPIPE); + pUsbhs->USBHS_HSTPIPCFG[Pipe] |= ( pipeBank | pipeToken | USBHS_HSTPIPCFG_PSIZE(pipeSize) | pipeType | USBHS_HSTPIPCFG_PEPNUM(pipeEpNum) | USBHS_HSTPIPCFG_INTFRQ(PipeIntFreq)); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostAllocMem(Usbhs *pUsbhs, uint8_t Pipe) +{ + pUsbhs->USBHS_HSTPIPCFG[Pipe] |= USBHS_HSTPIPCFG_ALLOC; + +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostFreeMem(Usbhs *pUsbhs, uint8_t Pipe) +{ + pUsbhs->USBHS_HSTPIPCFG[Pipe] &= ~USBHS_HSTPIPCFG_ALLOC; + +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint16_t USBHS_HostGetSize(Usbhs *pUsbhs, uint8_t Pipe) +{ + return (8 << ((pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PSIZE_Msk) >> USBHS_HSTPIPCFG_PSIZE_Pos)) ; + +} + + /** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostSetToken(Usbhs *pUsbhs, uint8_t Pipe, uint32_t Token) +{ + pUsbhs->USBHS_HSTPIPCFG[Pipe] &= ~USBHS_HSTPIPCFG_PTOKEN_Msk; + pUsbhs->USBHS_HSTPIPCFG[Pipe] |= Token; + +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_HostGetToken(Usbhs *pUsbhs, uint8_t Pipe) +{ + return (pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PTOKEN_Msk) ; + +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostSetPipeType(Usbhs *pUsbhs, uint8_t Pipe, uint8_t PipeType) +{ + pUsbhs->USBHS_HSTPIPCFG[Pipe] &= ~USBHS_HSTPIPCFG_PTYPE_Msk ; + pUsbhs->USBHS_HSTPIPCFG[Pipe] |= PipeType ; + +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_HostGetPipeType(Usbhs *pUsbhs, uint8_t Pipe ) +{ + return (pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PTYPE_Msk) ; + +} + +__STATIC_INLINE uint8_t USBHS_GetPipeEpAddr(Usbhs *pUsbhs, uint8_t Pipe) +{ + + if( USBHS_HostGetToken(USBHS, Pipe) == USBHS_HSTPIPCFG_PTOKEN_IN) + { + return ( ((pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PEPNUM_Msk) >> USBHS_HSTPIPCFG_PEPNUM_Pos) | 0x80); + } + else + { + return ( ((pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PEPNUM_Msk) >> USBHS_HSTPIPCFG_PEPNUM_Pos) | 0x00) ; + } +} + + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostEnableAutoSw(Usbhs *pUsbhs, uint8_t Pipe) +{ + pUsbhs->USBHS_HSTPIPCFG[Pipe] |= USBHS_HSTPIPCFG_AUTOSW; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostDisableAutoSw(Usbhs *pUsbhs, uint8_t Pipe) +{ + pUsbhs->USBHS_HSTPIPCFG[Pipe] &= ~USBHS_HSTPIPCFG_AUTOSW; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostSetIntFreq(Usbhs *pUsbhs, uint8_t Pipe, uint8_t Freq) +{ + pUsbhs->USBHS_HSTPIPCFG[Pipe] |= USBHS_HSTPIPCFG_BINTERVAL(Freq); +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostEnablePing(Usbhs *pUsbhs, uint8_t Pipe) +{ + pUsbhs->USBHS_HSTPIPCFG[Pipe] |= USBHS_HSTPIPCFG_PINGEN; +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint8_t USBHS_HostGetDataTogSeq(Usbhs *pUsbhs, uint8_t Pipe) +{ + return ( (pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_HSTPIPISR_DTSEQ_Msk) >> USBHS_HSTPIPISR_DTSEQ_Pos ) ; +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint8_t USBHS_HostGetNumOfBusyBank(Usbhs *pUsbhs, uint8_t Pipe) +{ + return ( (pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_HSTPIPISR_NBUSYBK_Msk) >> USBHS_HSTPIPISR_NBUSYBK_Pos ) ; +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint8_t USBHS_HostGetCurrentBank(Usbhs *pUsbhs, uint8_t Pipe) +{ + return ( (pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_HSTPIPISR_CURRBK_Msk) >> USBHS_HSTPIPISR_CURRBK_Pos ) ; +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint8_t USBHS_HostGetPipeByteCount(Usbhs *pUsbhs, uint8_t Pipe) +{ + return ( (pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_HSTPIPISR_PBYCT_Msk) >> USBHS_HSTPIPISR_PBYCT_Pos ) ; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_IsHostConfigOk(Usbhs *pUsbhs, uint8_t Pipe) +{ + return (pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_DEVEPTISR_CFGOK); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_HostGetIntTypeStatus(Usbhs *pUsbhs, uint8_t Pipe, uint32_t intType) +{ + return (pUsbhs->USBHS_HSTPIPISR[Pipe] & intType); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostAckPipeIntType(Usbhs *pUsbhs, uint8_t Pipe, uint32_t intType) +{ + pUsbhs->USBHS_HSTPIPICR[Pipe] = intType; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostSetPipeIntType(Usbhs *pUsbhs, uint8_t Pipe, uint32_t intType) +{ + pUsbhs->USBHS_HSTPIPIFR[Pipe] = intType; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_IsHostPipeIntTypeEnable(Usbhs *pUsbhs, uint8_t Pipe, uint32_t intType) +{ + return ( pUsbhs->USBHS_HSTPIPIMR[Pipe] & intType); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostDisablePipeIntType(Usbhs *pUsbhs, uint8_t Pipe, uint32_t intType) +{ + pUsbhs->USBHS_HSTPIPIDR[Pipe] = intType; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostEnablePipeIntType(Usbhs *pUsbhs, uint8_t Pipe, uint32_t intType) +{ + pUsbhs->USBHS_HSTPIPIER[Pipe] = intType; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostEnableInReq(Usbhs *pUsbhs, uint8_t Pipe) +{ + pUsbhs->USBHS_HSTPIPINRQ[Pipe] |= USBHS_HSTPIPINRQ_INMODE; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostDisableInReq(Usbhs *pUsbhs, uint8_t Pipe) +{ + pUsbhs->USBHS_HSTPIPINRQ[Pipe] &= ~USBHS_HSTPIPINRQ_INMODE; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint8_t USBHS_IsHostInReqEnable(Usbhs *pUsbhs, uint8_t Pipe) +{ + return ((pUsbhs->USBHS_HSTPIPINRQ[Pipe] & USBHS_HSTPIPINRQ_INMODE) >> 8); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostInReq(Usbhs *pUsbhs, uint8_t Pipe, uint8_t InReq) +{ + pUsbhs->USBHS_HSTPIPINRQ[Pipe] = USBHS_HSTPIPINRQ_INRQ(InReq-1); +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostSetErr(Usbhs *pUsbhs, uint8_t Pipe, uint8_t Err) +{ + pUsbhs->USBHS_HSTPIPERR[Pipe] |= Err; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint8_t USBHS_HostGetErr(Usbhs *pUsbhs, uint8_t Pipe, uint8_t Err) +{ + return (pUsbhs->USBHS_HSTPIPERR[Pipe] & Err); +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostClearErr(Usbhs *pUsbhs, uint8_t Pipe, uint8_t Err) +{ + pUsbhs->USBHS_HSTPIPERR[Pipe] = Err; +} + + +__STATIC_INLINE uint8_t USBHS_GetInterruptPipeNum(void) +{ + uint32_t status = USBHS->USBHS_HSTISR; + uint32_t mask = USBHS->USBHS_HSTIMR; + return ctz(((status & mask) >> 8) | (1 << USBHS_EPT_NUM)); +} + +static inline uint8_t USBHS_GetInterruptPipeDmaNum(void) +{ + uint32_t status = USBHS->USBHS_HSTISR; + uint32_t mask = USBHS->USBHS_HSTIMR; + return (ctz(((status & mask) >> 25) | (1 << (USBHS_EPT_NUM-1))) + 1); +} + /*-------------------------------------------------------- + * =========== USB Host's pipe DMA functions ========= + *---------------------------------------------------------*/ + + /** + * \brief Sets DMA next descriptor address + * \param pUsbDma USBHS device DMA instance + * \param Desc NDA addrs + */ +__STATIC_INLINE void USBHS_SetHostDmaNDA(UsbhsHstdma *pUsbDma, uint32_t Desc) +{ + pUsbDma->USBHS_HSTDMANXTDSC = Desc; +} + + /** + * \brief Gets DMA next descriptor address + * \param pUsbDma USBHS device DMA instance + * \return Next DMA descriptor + */ +__STATIC_INLINE uint32_t USBHS_GetHostDmaNDA(UsbhsHstdma *pUsbDma) +{ + return (pUsbDma->USBHS_HSTDMANXTDSC); +} + + /** + * \brief Sets USBHS's DMA Buffer addresse + * \param pUsbDma USBHS device DMA instance + * \param Addr DMA's buffer Addrs + */ +__STATIC_INLINE void USBHS_SetHostDmaBuffAdd(UsbhsHstdma *pUsbDma, uint32_t Addr) +{ + pUsbDma->USBHS_HSTDMAADDRESS = Addr; +} + + + /** + * \brief Gets USBHS's DMA Buffer addresse + * \param pUsbDma USBHS device DMA instance + * \return DMA addrs + */ +__STATIC_INLINE uint32_t USBHS_GetHostDmaBuffAdd(UsbhsHstdma *pUsbDma) +{ + return (pUsbDma->USBHS_HSTDMAADDRESS); +} + + /** + * \brief Setup the USBHS DMA + * \param pUsbDma USBHS device DMA instance + * \param Cfg DMA's configuration + */ +__STATIC_INLINE void USBHS_HostConfigureDma(UsbhsHstdma *pUsbDma, uint32_t Cfg) +{ + pUsbDma->USBHS_HSTDMACONTROL |= Cfg; +} + + /** + * \brief Get DMA configuration + * \param pUsbDma USBHS device DMA instance + * \return DMA control setup + */ +__STATIC_INLINE uint32_t USBHS_GetHostDmaConfiguration(UsbhsHstdma *pUsbDma) +{ + return (pUsbDma->USBHS_HSTDMACONTROL); +} + + + /** + * \brief Set DMA status + * \param pUsbDma USBHS device DMA instance + * \Status Set DMA status + */ +__STATIC_INLINE void USBHS_SetHostPipeDmaStatus(UsbhsHstdma *pUsbDma, uint32_t Status) +{ + pUsbDma->USBHS_HSTDMASTATUS = Status; +} + + + /** + * \brief Get Dma Status + * \param pUsbDma USBHS device DMA instance + * \return Dma status + */ +__STATIC_INLINE uint32_t USBHS_GetHostPipeDmaStatus(UsbhsHstdma *pUsbDma) +{ + return (pUsbDma->USBHS_HSTDMASTATUS); +} + +/**@}*/ +#endif /* #ifndef USBHS_H */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/video.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/video.h new file mode 100644 index 00000000..6976d0f4 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/video.h @@ -0,0 +1,80 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _VIDEO_H +#define _VIDEO_H + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ +/** Type of video is YUV */ +#define YUV 0 +/** Type of video is RGB */ +#define RGB 1 + +/*---------------------------------------------------------------------------- + * Type + *----------------------------------------------------------------------------*/ +typedef struct _isi_Video +{ + /** LCD Vertical Size */ + uint32_t lcd_vsize; + /** LCD Horizontal Size*/ + uint32_t lcd_hsize; + /** LCD Number of Bit Per Pixel*/ + uint32_t lcd_nbpp; + /** LCD Frame Buffer Address*/ + uint32_t lcd_fb_addr; + /** Base address for the frame buffer descriptors list*/ + uint32_t Isi_fbd_base; + /** Start of Line Delay*/ + uint32_t Hblank; + /** Start of frame Delay */ + uint32_t Vblank; + /** Vertical size of the Image sensor [0..2047]*/ + uint32_t codec_vsize; + /** Horizontal size of the Image sensor [0..2047]*/ + uint32_t codec_hsize; + /** Base address for codec DMA*/ + uint32_t codec_fb_addr; + /** Base address for the frame buffer descriptors list*/ + uint32_t codec_fbd_base; + /** Buffer index */ + uint32_t IsiPrevBuffIndex; + /** Type of video */ + uint8_t rgb_or_yuv; +}isi_Video, *pIsi_Video; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +extern void VIDEO_Ycc2Rgb(uint8_t *ycc, uint16_t *rgb, uint32_t len); + +#endif + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/wdt.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/wdt.h new file mode 100644 index 00000000..ee5b7d2c --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/wdt.h @@ -0,0 +1,74 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \section Purpose + * Interface for Watchdog Timer (WDT) controller. + * + * \section Usage + * -# Enable watchdog with given mode using \ref WDT_Enable(). + * -# Disable watchdog using \ref WDT_Disable() + * -# Restart the watchdog using \ref WDT_Restart(). + * -# Get watchdog status using \ref WDT_GetStatus(). + * -# Calculate watchdog period value using \ref WDT_GetPeriod(). + */ + +#ifndef _WDT_ +#define _WDT_ + +#include "chip.h" + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void WDT_Enable( Wdt* pWDT, uint32_t dwMode ) ; + +extern void WDT_Disable( Wdt* pWDT ) ; + +extern void WDT_Restart( Wdt* pWDT ) ; + +extern uint32_t WDT_GetStatus( Wdt* pWDT ) ; + +extern uint32_t WDT_GetPeriod( uint32_t dwMs ) ; + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _WDT_ */ + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/xdma_hardware_interface.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/xdma_hardware_interface.h new file mode 100644 index 00000000..f9e47626 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/xdma_hardware_interface.h @@ -0,0 +1,58 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _XDMAD_IF_H +#define _XDMAD_IF_H + +/*---------------------------------------------------------------------------- + * Includes + *----------------------------------------------------------------------------*/ + +#include "chip.h" +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** DMA hardware interface */ +typedef struct _XdmaHardwareInterface { + uint8_t bXdmac; /**< DMA Controller number */ + uint32_t bPeriphID; /**< Peripheral ID */ + uint8_t bTransfer; /**< Transfer type 0: Tx, 1 :Rx*/ + uint8_t bIfID; /**< DMA Interface ID */ +} XdmaHardwareInterface; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern uint8_t XDMAIF_IsValidatedPeripherOnDma( uint8_t bPeriphID); +extern uint8_t XDMAIF_Get_ChannelNumber (uint8_t bPeriphID, uint8_t bTransfer); + +#endif //#ifndef _XDMAD_IF_H + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/xdmac.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/xdmac.h new file mode 100644 index 00000000..ecd3496e --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/xdmac.h @@ -0,0 +1,177 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/** \addtogroup dmac_module Working with DMAC + * + * \section Usage + *
    + *
  • Enable or disable the a DMAC controller with DMAC_Enable() and or + * DMAC_Disable().
    • + *
  • Enable or disable %Dma interrupt using DMAC_EnableIt()or + * DMAC_DisableIt().
    • + *
  • Get %Dma interrupt status by DMAC_GetStatus() and + * DMAC_GetInterruptMask().
    • + *
  • Enable or disable specified %Dma channel with DMAC_EnableChannel() or + * DMAC_DisableChannel().
    • + *
  • Get %Dma channel status by DMAC_GetChannelStatus().
    • + *
  • ControlA and ControlB register is set by DMAC_SetControlA() and + * DMAC_SetControlB().
    • + *
  • Configure source and/or destination start address with + * DMAC_SetSourceAddr() and/or DMAC_SetDestinationAddr().
    • + *
  • Set %Dma descriptor address using DMAC_SetDescriptorAddr().
    • + *
  • Set source transfer buffer size with DMAC_SetBufferSize().
    • + *
  • Configure source and/or destination Picture-In-Picuture mode with + * DMAC_SetSourcePip() and/or DMAC_SetDestPip().
    • + *
+ * + * For more accurate information, please look at the DMAC section of the + * Datasheet. + * + * \sa \ref dmad_module + * + * Related files :\n + * \ref dmac.c\n + * \ref dmac.h.\n + * + */ + +#ifndef DMAC_H +#define DMAC_H +/**@{*/ + +/*------------------------------------------------------------------------------ + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include +#include + +/*------------------------------------------------------------------------------ + * Definitions + *----------------------------------------------------------------------------*/ + +/** \addtogroup dmac_defines DMAC Definitions + * @{ + */ +/** Number of DMA channels */ +#define XDMAC_CONTROLLER_NUM 1 +/** Number of DMA channels */ +#define XDMAC_CHANNEL_NUM 24 +/** Max DMA single transfer size */ +#define XDMAC_MAX_BT_SIZE 0xFFFF +/** @}*/ + +/*---------------------------------------------------------------------------- + * Macro + *----------------------------------------------------------------------------*/ +#define XDMA_GET_DATASIZE(size) ((size==0)? XDMAC_CC_DWIDTH_BYTE : \ + ((size==1)? XDMAC_CC_DWIDTH_HALFWORD : \ + (XDMAC_CC_DWIDTH_WORD ))) +#define XDMA_GET_CC_SAM(s) ((s==0)? XDMAC_CC_SAM_FIXED_AM : \ + ((s==1)? XDMAC_CC_SAM_INCREMENTED_AM : \ + ((s==2)? XDMAC_CC_SAM_UBS_AM : \ + XDMAC_CC_SAM_UBS_DS_AM ))) +#define XDMA_GET_CC_DAM(d) ((d==0)? XDMAC_CC_DAM_FIXED_AM : \ + ((d==1)? XDMAC_CC_DAM_INCREMENTED_AM : \ + ((d==2)? XDMAC_CC_DAM_UBS_AM : \ + XDMAC_CC_DAM_UBS_DS_AM ))) +#define XDMA_GET_CC_MEMSET(m) ((m==0)? XDMAC_CC_MEMSET_NORMAL_MODE : \ + XDMAC_CC_MEMSET_HW_MODE) + +/*------------------------------------------------------------------------------ + * Global functions + *----------------------------------------------------------------------------*/ +/** \addtogroup dmac_functions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +extern uint32_t XDMAC_GetType( Xdmac *pXdmac); +extern uint32_t XDMAC_GetConfig( Xdmac *pXdmac); +extern uint32_t XDMAC_GetArbiter( Xdmac *pXdmac); +extern void XDMAC_EnableGIt (Xdmac *pXdmac, uint8_t dwInteruptMask ); +extern void XDMAC_DisableGIt (Xdmac *pXdmac, uint8_t dwInteruptMask ); +extern uint32_t XDMAC_GetGItMask( Xdmac *pXdmac ); +extern uint32_t XDMAC_GetGIsr( Xdmac *pXdmac ); +extern uint32_t XDMAC_GetMaskedGIsr( Xdmac *pXdmac ); +extern void XDMAC_EnableChannel( Xdmac *pXdmac, uint8_t channel ); +extern void XDMAC_EnableChannels( Xdmac *pXdmac, uint32_t bmChannels ); +extern void XDMAC_DisableChannel( Xdmac *pXdmac, uint8_t channel ); +extern void XDMAC_DisableChannels( Xdmac *pXdmac, uint32_t bmChannels ); +extern uint32_t XDMAC_GetGlobalChStatus(Xdmac *pXdmac); +extern void XDMAC_SuspendReadChannel( Xdmac *pXdmac, uint8_t channel ); +extern void XDMAC_SuspendWriteChannel( Xdmac *pXdmac, uint8_t channel ); +extern void XDMAC_SuspendReadWriteChannel( Xdmac *pXdmac, uint8_t channel ); +extern void XDMAC_ResumeReadWriteChannel( Xdmac *pXdmac, uint8_t channel ); +extern void XDMAC_SoftwareTransferReq(Xdmac *pXdmac, uint8_t channel); +extern uint32_t XDMAC_GetSoftwareTransferStatus(Xdmac *pXdmac); +extern void XDMAC_SoftwareFlushReq(Xdmac *pXdmac, uint8_t channel); +extern void XDMAC_EnableChannelIt (Xdmac *pXdmac, uint8_t channel, + uint8_t dwInteruptMask ); +extern void XDMAC_DisableChannelIt (Xdmac *pXdmac, uint8_t channel, + uint8_t dwInteruptMask ); +extern uint32_t XDMAC_GetChannelItMask (Xdmac *pXdmac, uint8_t channel); +extern uint32_t XDMAC_GetChannelIsr (Xdmac *pXdmac, uint8_t channel); +extern uint32_t XDMAC_GetMaskChannelIsr (Xdmac *pXdmac, uint8_t channel); +extern void XDMAC_SetSourceAddr(Xdmac *pXdmac, uint8_t channel, uint32_t addr); +extern void XDMAC_SetDestinationAddr(Xdmac *pXdmac, uint8_t channel, + uint32_t addr); +extern void XDMAC_SetDescriptorAddr(Xdmac *pXdmac, uint8_t channel, + uint32_t addr, uint8_t ndaif); +extern void XDMAC_SetDescriptorControl(Xdmac *pXdmac, uint8_t channel, + uint8_t config); +extern void XDMAC_SetMicroblockControl(Xdmac *pXdmac, uint8_t channel, + uint32_t ublen); +extern void XDMAC_SetBlockControl(Xdmac *pXdmac, uint8_t channel, + uint16_t blen); +extern void XDMAC_SetChannelConfig(Xdmac *pXdmac, uint8_t channel, + uint32_t config); +extern uint32_t XDMAC_GetChannelConfig(Xdmac *pXdmac, uint8_t channel); +extern void XDMAC_SetDataStride_MemPattern(Xdmac *pXdmac, uint8_t channel, + uint32_t dds_msp); +extern void XDMAC_SetSourceMicroBlockStride(Xdmac *pXdmac, uint8_t channel, + uint32_t subs); +extern void XDMAC_SetDestinationMicroBlockStride(Xdmac *pXdmac, uint8_t channel, + uint32_t dubs); +extern uint32_t XDMAC_GetChDestinationAddr(Xdmac *pXdmac, uint8_t channel); +#ifdef __cplusplus +} +#endif + +/** @}*/ +/**@}*/ +#endif //#ifndef DMAC_H + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/xdmad.h b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/xdmad.h new file mode 100644 index 00000000..877f20e7 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/libchip_samv7/include/xdmad.h @@ -0,0 +1,260 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _XDMAD_H +#define _XDMAD_H + + +/*---------------------------------------------------------------------------- + * Includes + *----------------------------------------------------------------------------*/ + +#include "chip.h" +#include + + +/** \addtogroup dmad_defines DMA Driver Defines + @{*/ +/*---------------------------------------------------------------------------- + * Consts + *----------------------------------------------------------------------------*/ +#define XDMAD_TRANSFER_MEMORY 0xFF /**< DMA transfer from or to memory */ +#define XDMAD_ALLOC_FAILED 0xFFFF /**< Channel allocate failed */ + +#define XDMAD_TRANSFER_TX 0 +#define XDMAD_TRANSFER_RX 1 + +/* XDMA_MBR_UBC */ +#define XDMA_UBC_NDE (0x1u << 24) +#define XDMA_UBC_NDE_FETCH_DIS (0x0u << 24) +#define XDMA_UBC_NDE_FETCH_EN (0x1u << 24) +#define XDMA_UBC_NSEN (0x1u << 25) +#define XDMA_UBC_NSEN_UNCHANGED (0x0u << 25) +#define XDMA_UBC_NSEN_UPDATED (0x1u << 25) +#define XDMA_UBC_NDEN (0x1u << 26) +#define XDMA_UBC_NDEN_UNCHANGED (0x0u << 26) +#define XDMA_UBC_NDEN_UPDATED (0x1u << 26) +#define XDMA_UBC_NVIEW_Pos 27 +#define XDMA_UBC_NVIEW_Msk (0x3u << XDMA_UBC_NVIEW_Pos) +#define XDMA_UBC_NVIEW_NDV0 (0x0u << XDMA_UBC_NVIEW_Pos) +#define XDMA_UBC_NVIEW_NDV1 (0x1u << XDMA_UBC_NVIEW_Pos) +#define XDMA_UBC_NVIEW_NDV2 (0x2u << XDMA_UBC_NVIEW_Pos) +#define XDMA_UBC_NVIEW_NDV3 (0x3u << XDMA_UBC_NVIEW_Pos) + +/*---------------------------------------------------------------------------- + * MACRO + *----------------------------------------------------------------------------*/ + +/** @}*/ + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ +/** \addtogroup dmad_structs DMA Driver Structs + @{*/ + +/** DMA status or return code */ +typedef enum _XdmadStatus { + XDMAD_OK = 0, /**< Operation is successful */ + XDMAD_PARTIAL_DONE, + XDMAD_DONE, + XDMAD_BUSY, /**< Channel occupied or transfer not finished */ + XDMAD_ERROR, /**< Operation failed */ + XDMAD_CANCELED /**< Operation cancelled */ +} eXdmadStatus, eXdmadRC; + +/** DMA state for channel */ +typedef enum _XdmadState { + XDMAD_STATE_FREE = 0, /**< Free channel */ + XDMAD_STATE_ALLOCATED, /**< Allocated to some peripheral */ + XDMAD_STATE_START, /**< DMA started */ + XDMAD_STATE_IN_XFR, /**< DMA in transferring */ + XDMAD_STATE_DONE, /**< DMA transfer done */ + XDMAD_STATE_HALTED, /**< DMA transfer stopped */ +} eXdmadState; + +/** DMA Programming state for channel */ +typedef enum _XdmadProgState { + XDMAD_SINGLE= 0, + XDMAD_MULTI, + XDMAD_LLI, +} eXdmadProgState; + +/** DMA transfer callback */ +typedef void (*XdmadTransferCallback)(uint32_t Channel, void* pArg); + +/** DMA driver channel */ +typedef struct _XdmadChannel { + XdmadTransferCallback fCallback; /**< Callback */ + void* pArg; /**< Callback argument */ + uint8_t bIrqOwner; /**< Uses DMA handler or external one */ + uint8_t bSrcPeriphID; /**< HW ID for source */ + uint8_t bDstPeriphID; /**< HW ID for destination */ + uint8_t bSrcTxIfID; /**< DMA Tx Interface ID for source */ + uint8_t bSrcRxIfID; /**< DMA Rx Interface ID for source */ + uint8_t bDstTxIfID; /**< DMA Tx Interface ID for destination */ + uint8_t bDstRxIfID; /**< DMA Rx Interface ID for destination */ + volatile uint8_t state; /**< DMA channel state */ +} sXdmadChannel; + +/** DMA driver instance */ +typedef struct _Xdmad { + Xdmac *pXdmacs; + sXdmadChannel XdmaChannels[XDMACCHID_NUMBER]; + uint8_t numControllers; + uint8_t numChannels; + uint8_t pollingMode; + uint8_t pollingTimeout; + uint8_t xdmaMutex; +} sXdmad; + +typedef struct _XdmadCfg { + /** Microblock Control Member. */ + uint32_t mbr_ubc; + /** Source Address Member. */ + uint32_t mbr_sa; + /** Destination Address Member. */ + uint32_t mbr_da; + /** Configuration Register. */ + uint32_t mbr_cfg; + /** Block Control Member. */ + uint32_t mbr_bc; + /** Data Stride Member. */ + uint32_t mbr_ds; + /** Source Microblock Stride Member. */ + uint32_t mbr_sus; + /** Destination Microblock Stride Member. */ + uint32_t mbr_dus; +} sXdmadCfg; + +/** \brief Structure for storing parameters for DMA view0 that can be + * performed by the DMA Master transfer.*/ +typedef struct _LinkedListDescriporView0 +{ + /** Next Descriptor Address number. */ + uint32_t mbr_nda; + /** Microblock Control Member. */ + uint32_t mbr_ubc; + /** Transfer Address Member. */ + uint32_t mbr_ta; +}LinkedListDescriporView0; + +/** \brief Structure for storing parameters for DMA view1 that can be + * performed by the DMA Master transfer.*/ +typedef struct _LinkedListDescriporView1 +{ + /** Next Descriptor Address number. */ + uint32_t mbr_nda; + /** Microblock Control Member. */ + uint32_t mbr_ubc; + /** Source Address Member. */ + uint32_t mbr_sa; + /** Destination Address Member. */ + uint32_t mbr_da; +}LinkedListDescriporView1; + +/** \brief Structure for storing parameters for DMA view2 that can be + * performed by the DMA Master transfer.*/ +typedef struct _LinkedListDescriporView2 +{ + /** Next Descriptor Address number. */ + uint32_t mbr_nda; + /** Microblock Control Member. */ + uint32_t mbr_ubc; + /** Source Address Member. */ + uint32_t mbr_sa; + /** Destination Address Member. */ + uint32_t mbr_da; + /** Configuration Register. */ + uint32_t mbr_cfg; +}LinkedListDescriporView2; + +/** \brief Structure for storing parameters for DMA view3 that can be + * performed by the DMA Master transfer.*/ +typedef struct _LinkedListDescriporView3 +{ + /** Next Descriptor Address number. */ + uint32_t mbr_nda; + /** Microblock Control Member. */ + uint32_t mbr_ubc; + /** Source Address Member. */ + uint32_t mbr_sa; + /** Destination Address Member. */ + uint32_t mbr_da; + /** Configuration Register. */ + uint32_t mbr_cfg; + /** Block Control Member. */ + uint32_t mbr_bc; + /** Data Stride Member. */ + uint32_t mbr_ds; + /** Source Microblock Stride Member. */ + uint32_t mbr_sus; + /** Destination Microblock Stride Member. */ + uint32_t mbr_dus; +}LinkedListDescriporView3; + +/** @}*/ + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +/** \addtogroup dmad_functions DMA Driver Functions + @{*/ +extern void XDMAD_Initialize( sXdmad *pXdmad, + uint8_t bPollingMode ); + +extern void XDMAD_Handler( sXdmad *pDmad); + +extern uint32_t XDMAD_AllocateChannel( sXdmad *pXdmad, + uint8_t bSrcID, uint8_t bDstID); +extern eXdmadRC XDMAD_FreeChannel( sXdmad *pXdmad, uint32_t dwChannel ); + +extern eXdmadRC XDMAD_ConfigureTransfer( sXdmad *pXdmad, + uint32_t dwChannel, + sXdmadCfg *pXdmaParam, + uint32_t dwXdmaDescCfg, + uint32_t dwXdmaDescAddr, + uint32_t dwXdmaIntEn); + +extern eXdmadRC XDMAD_PrepareChannel( sXdmad *pXdmad, uint32_t dwChannel); + +extern eXdmadRC XDMAD_IsTransferDone( sXdmad *pXdmad, uint32_t dwChannel ); + +extern eXdmadRC XDMAD_StartTransfer( sXdmad *pXdmad, uint32_t dwChannel ); + +extern eXdmadRC XDMAD_SetCallback( sXdmad *pXdmad, + uint32_t dwChannel, + XdmadTransferCallback fCallback, + void* pArg ); + +extern eXdmadRC XDMAD_StopTransfer( sXdmad *pXdmad, uint32_t dwChannel ); +/** @}*/ +/**@}*/ +#endif //#ifndef _XDMAD_H + diff --git a/ports_module/cortex-m7/iar/example_build/libraries/libraries.a b/ports_module/cortex-m7/iar/example_build/libraries/libraries.a new file mode 100644 index 00000000..1e67e315 Binary files /dev/null and b/ports_module/cortex-m7/iar/example_build/libraries/libraries.a differ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/utils/md5/md5.h b/ports_module/cortex-m7/iar/example_build/libraries/utils/md5/md5.h new file mode 100644 index 00000000..698c995d --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/utils/md5/md5.h @@ -0,0 +1,91 @@ +/* + Copyright (C) 1999, 2002 Aladdin Enterprises. All rights reserved. + + This software is provided 'as-is', without any express or implied + warranty. In no event will the authors be held liable for any damages + arising from the use of this software. + + Permission is granted to anyone to use this software for any purpose, + including commercial applications, and to alter it and redistribute it + freely, subject to the following restrictions: + + 1. The origin of this software must not be misrepresented; you must not + claim that you wrote the original software. If you use this software + in a product, an acknowledgment in the product documentation would be + appreciated but is not required. + 2. Altered source versions must be plainly marked as such, and must not be + misrepresented as being the original software. + 3. This notice may not be removed or altered from any source distribution. + + L. Peter Deutsch + ghost@aladdin.com + + */ +/* $Id: md5.h,v 1.4 2002/04/13 19:20:28 lpd Exp $ */ +/* + Independent implementation of MD5 (RFC 1321). + + This code implements the MD5 Algorithm defined in RFC 1321, whose + text is available at + http://www.ietf.org/rfc/rfc1321.txt + The code is derived from the text of the RFC, including the test suite + (section A.5) but excluding the rest of Appendix A. It does not include + any code or documentation that is identified in the RFC as being + copyrighted. + + The original and principal author of md5.h is L. Peter Deutsch + . Other authors are noted in the change history + that follows (in reverse chronological order): + + 2002-04-13 lpd Removed support for non-ANSI compilers; removed + references to Ghostscript; clarified derivation from RFC 1321; + now handles byte order either statically or dynamically. + 1999-11-04 lpd Edited comments slightly for automatic TOC extraction. + 1999-10-18 lpd Fixed typo in header comment (ansi2knr rather than md5); + added conditionalization for C++ compilation from Martin + Purschke . + 1999-05-03 lpd Original version. + */ + +#ifndef md5_INCLUDED +# define md5_INCLUDED + +/* + * This package supports both compile-time and run-time determination of CPU + * byte order. If ARCH_IS_BIG_ENDIAN is defined as 0, the code will be + * compiled to run only on little-endian CPUs; if ARCH_IS_BIG_ENDIAN is + * defined as non-zero, the code will be compiled to run only on big-endian + * CPUs; if ARCH_IS_BIG_ENDIAN is not defined, the code will be compiled to + * run on either big- or little-endian CPUs, but will run slightly less + * efficiently on either one than if ARCH_IS_BIG_ENDIAN is defined. + */ + +typedef unsigned char md5_byte_t; /* 8-bit byte */ +typedef unsigned int md5_word_t; /* 32-bit word */ + +/* Define the state of the MD5 Algorithm. */ +typedef struct md5_state_s { + md5_word_t count[2]; /* message length in bits, lsw first */ + md5_word_t abcd[4]; /* digest buffer */ + md5_byte_t buf[64]; /* accumulate block */ +} md5_state_t; + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Initialize the algorithm. */ +void md5_init(md5_state_t *pms); + +/* Append a string to the message. */ +void md5_append(md5_state_t *pms, const md5_byte_t *data, int nbytes); + +/* Finish the message and return the digest. */ +void md5_finish(md5_state_t *pms, md5_byte_t digest[16]); + +#ifdef __cplusplus +} /* end extern "C" */ +#endif + +#endif /* md5_INCLUDED */ diff --git a/ports_module/cortex-m7/iar/example_build/libraries/utils/utility.h b/ports_module/cortex-m7/iar/example_build/libraries/utils/utility.h new file mode 100644 index 00000000..e695376a --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/libraries/utils/utility.h @@ -0,0 +1,111 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef UTILITY_H +#define UTILITY_H + +#include "chip.h" + + + +#define RESET_CYCLE_COUNTER() do { \ + CoreDebug->DEMCR = CoreDebug_DEMCR_TRCENA_Msk; \ + __DSB(); DWT->LAR = 0xC5ACCE55; __DSB(); \ + DWT->CTRL &= ~DWT_CTRL_CYCCNTENA_Msk; \ + DWT->CYCCNT = 0; \ + DWT->CTRL = DWT_CTRL_CYCCNTENA_Msk; \ + }while(0) + +#define GET_CYCLE_COUNTER(x) x=DWT->CYCCNT; + +#define LockMutex(mut, timeout) get_lock(&mut, 1, &timeout) + +#define ReleaseMutex(mut) free_lock(&mut) + +#define GetResource(mut, max, timeout) get_lock(&mut, max, &timeout) + +#define FreeResource(mut) free_lock(&mut) + + +__STATIC_INLINE uint8_t Is_LockFree(volatile uint8_t *Lock_Variable) +{ + /* return Variable value*/ + return __LDREXB(Lock_Variable); + +} + +__STATIC_INLINE uint8_t get_lock(volatile uint8_t *Lock_Variable, const uint8_t maxValue, volatile uint32_t *pTimeout) +{ + while (*pTimeout) + { + if(__LDREXB(Lock_Variable) < maxValue) + { + /* Set the Variable */ + while( __STREXB(((*Lock_Variable) + 1), Lock_Variable) ) + { + if(!(*pTimeout)--) + { + return 1; // quit if timeout + } + } + /* Memory access barrier */ + __DMB(); + TRACE_DEBUG("Mutex locked "); + return 0; + } + + ((*pTimeout)--); + } + return 1; +} + + + +__STATIC_INLINE uint8_t free_lock(volatile uint8_t *Lock_Variable) +{ + /* Memory access barrier Ensure memory operations completed before releasing lock */ + __DSB(); + if(__LDREXB(Lock_Variable)) + { + __STREXB( ((*Lock_Variable) - 1), Lock_Variable); + TRACE_DEBUG("Mutex freed "); + __DSB(); + __DMB(); // Ensure memory operations completed before + return 0; + } + else + { + return 1; + } + + +} + + +#endif /* UTILITY_H */ diff --git a/ports_module/cortex-m7/iar/example_build/sample_threadx.c b/ports_module/cortex-m7/iar/example_build/sample_threadx.c new file mode 100644 index 00000000..9a626828 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/sample_threadx.c @@ -0,0 +1,381 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. Please refer to Chapter 6 of the ThreadX User Guide for a complete + description of this demonstration. */ + +/* Optimize by disabling basic ThreadX error checking. */ +#define TX_DISABLE_ERROR_CHECKING + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define memory pool. */ + +UCHAR memory_pool[DEMO_BYTE_POOL_SIZE]; + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Please refer to Chapter 6 of the ThreadX User Guide for a complete + description of this demonstration. */ + + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_pool, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} diff --git a/ports_module/cortex-m7/iar/example_build/sample_threadx.ewd b/ports_module/cortex-m7/iar/example_build/sample_threadx.ewd new file mode 100644 index 00000000..6f975a27 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/sample_threadx.ewd @@ -0,0 +1,2974 @@ + + + 3 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 32 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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@@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x200; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + +define symbol FlashConfig_start__= 0x00000400; +define symbol FlashConfig_end__ = 0x0000040f; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to (FlashConfig_start__ - 1)] | [from (FlashConfig_end__+1) to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +define region FlashConfig_region = mem:[from FlashConfig_start__ to FlashConfig_end__]; + +initialize by copy { readwrite }; +initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; + +place in FlashConfig_region + {section FlashConfig}; + +place in RAM_region { last section FREE_MEM}; + diff --git a/ports_module/cortex-m7/iar/example_build/sample_threadx_module.c b/ports_module/cortex-m7/iar/example_build/sample_threadx_module.c new file mode 100644 index 00000000..c1dec374 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/sample_threadx_module.c @@ -0,0 +1,427 @@ +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, + event flags group, byte pool, and block pool. */ + +/* Specify that this is a module! */ + +#define TXM_MODULE + + +/* Include the ThreadX module definitions. */ + +#include "txm_module.h" + + +/* Define constants. */ + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the pool space in the bss section of the module. ULONG is used to + get the word alignment. */ + +ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD *thread_0; +TX_THREAD *thread_1; +TX_THREAD *thread_2; +TX_THREAD *thread_3; +TX_THREAD *thread_4; +TX_THREAD *thread_5; +TX_THREAD *thread_6; +TX_THREAD *thread_7; +TX_QUEUE *queue_0; +TX_SEMAPHORE *semaphore_0; +TX_MUTEX *mutex_0; +TX_EVENT_FLAGS_GROUP *event_flags_0; +TX_BYTE_POOL *byte_pool_0; +TX_BLOCK_POOL *block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; +ULONG semaphore_0_puts; +ULONG event_0_sets; +ULONG queue_0_sends; + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + +void semaphore_0_notify(TX_SEMAPHORE *semaphore_ptr) +{ + + if (semaphore_ptr == semaphore_0) + semaphore_0_puts++; +} + + +void event_0_notify(TX_EVENT_FLAGS_GROUP *event_flag_group_ptr) +{ + + if (event_flag_group_ptr == event_flags_0) + event_0_sets++; +} + + +void queue_0_notify(TX_QUEUE *queue_ptr) +{ + + if (queue_ptr == queue_0) + queue_0_sends++; +} + + +/* Define the module start function. */ + +void demo_module_start(ULONG id) +{ + +CHAR *pointer; + + /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + the control block(s). */ + txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_2, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_3, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_4, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_5, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_6, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_7, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&queue_0, sizeof(TX_QUEUE)); + txm_module_object_allocate((void*)&semaphore_0, sizeof(TX_SEMAPHORE)); + txm_module_object_allocate((void*)&mutex_0, sizeof(TX_MUTEX)); + txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); + txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); + txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(queue_0, "module queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + tx_queue_send_notify(queue_0, queue_0_notify); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(semaphore_0, "module semaphore 0", 1); + + tx_semaphore_put_notify(semaphore_0, semaphore_0_notify); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(event_flags_0, "module event flags 0"); + + tx_event_flags_set_notify(event_flags_0, event_0_notify); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(mutex_0, "module mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(block_pool_0, "module block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + /* Test external memory sharing. */ + *(ULONG *)0x90000000 = 0xABABABAB; + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + diff --git a/ports_module/cortex-m7/iar/example_build/sample_threadx_module.ewd b/ports_module/cortex-m7/iar/example_build/sample_threadx_module.ewd new file mode 100644 index 00000000..21bf663c --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/sample_threadx_module.ewd @@ -0,0 +1,2974 @@ + + + 3 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 32 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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@@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x080f0000; +define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20027FFF; +define symbol __ICFEDIT_region_RAM_end__ = 0x2004FFFF; +define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; + +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +define movable block ROPI with alignment = 4, fixed order +{ + ro object txm_module_preamble.o, + ro, + ro data +}; + +define movable block RWPI with alignment = 8, fixed order, static base +{ + rw, + block HEAP +}; + +place in ROM_region { block ROPI }; +place in RAM_region { block RWPI }; \ No newline at end of file diff --git a/ports_module/cortex-m7/iar/example_build/sample_threadx_module_manager.c b/ports_module/cortex-m7/iar/example_build/sample_threadx_module_manager.c new file mode 100644 index 00000000..e2223dad --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/sample_threadx_module_manager.c @@ -0,0 +1,108 @@ +/* Small demonstration of the ThreadX module manager. */ + +#include "tx_api.h" +#include "txm_module.h" + +#define DEMO_STACK_SIZE 1024 + +/* Define the ThreadX object control blocks... */ + +TX_THREAD module_manager; +TXM_MODULE_INSTANCE my_module; + + +/* Define the object pool area. */ + +UCHAR object_memory[8192]; + + +/* Define the count of memory faults. */ + +ULONG memory_faults; + + +/* Define thread prototypes. */ + +void module_manager_entry(ULONG thread_input); + + +/* Define fault handler. */ + +VOID module_fault_handler(TX_THREAD *thread, TXM_MODULE_INSTANCE *module) +{ + + /* Just increment the fault counter. */ + memory_faults++; +} + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = (CHAR*)first_unused_memory; + + + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + pointer = pointer + DEMO_STACK_SIZE; +} + + + + +/* Define the test threads. */ + +void module_manager_entry(ULONG thread_input) +{ + + /* Initialize the module manager. */ + txm_module_manager_initialize((VOID *) 0x90000000, 0xE000); + + txm_module_manager_object_pool_create(object_memory, sizeof(object_memory)); + + /* Register a fault handler. */ + txm_module_manager_memory_fault_notify(module_fault_handler); + + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ + txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0x80f0000); + + /* Enable 128 byte read/write shared memory region at 0x90000000. */ + txm_module_manager_external_memory_enable(&my_module, (void *) 0x90000000, 128, TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE); + + /* Start the module. */ + txm_module_manager_start(&my_module); + + /* Sleep for a while.... */ + tx_thread_sleep(1000); + + /* Stop the module. */ + txm_module_manager_stop(&my_module); + + /* Unload the module. */ + txm_module_manager_unload(&my_module); + + /* Load the module that is already there. */ + txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0x80f0000); + + /* Start the module again. */ + txm_module_manager_start(&my_module); + + /* Now just spin... */ + while(1) + { + + tx_thread_sleep(100); + } +} diff --git a/ports_module/cortex-m7/iar/example_build/sample_threadx_module_manager.ewd b/ports_module/cortex-m7/iar/example_build/sample_threadx_module_manager.ewd new file mode 100644 index 00000000..902cac18 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/sample_threadx_module_manager.ewd @@ -0,0 +1,2974 @@ + + + 3 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 32 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 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__ICFEDIT_region_ITCMRAM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block 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+ + + 34050 + 0A0000000A0000006E0000006E000000 + 0000000000000000FE0200001A000000 + 8192 + 0 + 0 + 744 + 0 + + + 1 + + + + 34048 + 34049 + 34050 + 34051 + 34052 + 34053 + 34054 + 34055 + 34056 + 34057 + 34058 + 34059 + 34060 + 34061 + 34062 + 34063 + 34064 + 34065 + + + + 010000000300000001000000000000000000000001000000010000000200000000000000010000000100000000000000280000002800000000000000 + + + + diff --git a/ports_module/cortex-m7/iar/example_build/settings/sample_threadx.Debug.cspy.bat b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx.Debug.cspy.bat new file mode 100644 index 00000000..f91b20a7 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%~1" == "" goto debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\tasks\st_work\threadx_07242020_rc2\ports_module\cortex-m7\iar\example_build\settings\sample_threadx.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\tasks\st_work\threadx_07242020_rc2\ports_module\cortex-m7\iar\example_build\settings\sample_threadx.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\tasks\st_work\threadx_07242020_rc2\ports_module\cortex-m7\iar\example_build\settings\sample_threadx.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\Users\nisohack\Documents\work\tasks\st_work\threadx_07242020_rc2\ports_module\cortex-m7\iar\example_build\settings\sample_threadx.Debug.driver.xcl" + +@echo off +:end \ No newline at end of file diff --git a/ports_module/cortex-m7/iar/example_build/settings/sample_threadx.Debug.cspy.ps1 b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx.Debug.cspy.ps1 new file mode 100644 index 00000000..74493b77 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx.Debug.cspy.ps1 @@ -0,0 +1,31 @@ +param([String]$debugfile = ""); + +# This powershell file has been generated by the IAR Embedded Workbench +# C - SPY Debugger, as an aid to preparing a command line for running +# the cspybat command line utility using the appropriate settings. +# +# Note that this file is generated every time a new debug session +# is initialized, so you may want to move or rename the file before +# making changes. +# +# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed +# by the name of the debug file (usually an ELF / DWARF or UBROF file). +# +# Read about available command line parameters in the C - SPY Debugging +# Guide. Hints about additional command line parameters that may be +# useful in specific cases : +# --download_only Downloads a code image without starting a debug +# session afterwards. +# --silent Omits the sign - on message. +# --timeout Limits the maximum allowed execution time. +# + + +if ($debugfile -eq "") +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\tasks\st_work\threadx_07242020_rc2\ports_module\cortex-m7\iar\example_build\settings\sample_threadx.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\tasks\st_work\threadx_07242020_rc2\ports_module\cortex-m7\iar\example_build\settings\sample_threadx.Debug.driver.xcl" +} +else +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\tasks\st_work\threadx_07242020_rc2\ports_module\cortex-m7\iar\example_build\settings\sample_threadx.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\Users\nisohack\Documents\work\tasks\st_work\threadx_07242020_rc2\ports_module\cortex-m7\iar\example_build\settings\sample_threadx.Debug.driver.xcl" +} diff --git a/ports_module/cortex-m7/iar/example_build/settings/sample_threadx.Debug.driver.xcl b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx.Debug.driver.xcl new file mode 100644 index 00000000..c0ab94e4 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx.Debug.driver.xcl @@ -0,0 +1,13 @@ +"--endian=little" + +"--cpu=Cortex-M7" + +"--fpu=VFPv5_SP" + +"--semihosting" + +"--multicore_nr_of_cores=1" + + + + diff --git a/ports_module/cortex-m7/iar/example_build/settings/sample_threadx.Debug.general.xcl b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx.Debug.general.xcl new file mode 100644 index 00000000..1cfc618e --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx.Debug.general.xcl @@ -0,0 +1,11 @@ +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armproc.dll" + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armsim2.dll" + +"C:\Users\nisohack\Documents\work\tasks\st_work\threadx_07242020_rc2\ports_module\cortex-m7\iar\example_build\Debug\Exe\sample_threadx.out" + +--plugin="C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armbat.dll" + + + + diff --git a/ports_module/cortex-m7/iar/example_build/settings/sample_threadx.crun b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx.crun new file mode 100644 index 00000000..d71ea555 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx.crun @@ -0,0 +1,13 @@ + + + 1 + + + * + * + * + 0 + 1 + + + diff --git a/ports_module/cortex-m7/iar/example_build/settings/sample_threadx.dbgdt b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx.dbgdt new file mode 100644 index 00000000..ef591ee6 --- /dev/null +++ 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+ + + 34122 + 0A0000000A0000006E0000006E000000 + 0000000000000000150300001A000000 + 8192 + 0 + 0 + 767 + 0 + + + 1 + + + + diff --git a/ports_module/cortex-m7/iar/example_build/settings/sample_threadx.dnx b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx.dnx new file mode 100644 index 00000000..43a997c2 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx.dnx @@ -0,0 +1,99 @@ + + + + 0 + 1 + 90 + 1 + 1 + 1 + main + 0 + 50 + + + 0 + 1 + + + 1461626342 + + + 0 + + + _ 0 + _ 0 + + + 0 + + + 0 + 0 + 0 + + + 0 + 1 + 0 + 0 + + + 0 + + + 1 + + + _ 0 + _ "" + + + _ 0 + _ "" + _ 0 + + + 0 + 0 + 1 + 0 + 1 + 0 + + + 0 + 0 + 1 + 0 + 1 + + + 0 + + + 0 + + + 1 + _ 0 9999 0 9999 1 0 0 100 0 1 "SysTick 1 0x3C" + 1 + + + 1 + 0 + 1 + 0 + 1 + + + 0 + 0 + + + 10000000 + 0 + 1 + + diff --git a/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module.Debug.cspy.bat b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module.Debug.cspy.bat new file mode 100644 index 00000000..0d64664e --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%~1" == "" goto debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m7\iar\example_build\settings\sample_threadx_module.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m7\iar\example_build\settings\sample_threadx_module.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m7\iar\example_build\settings\sample_threadx_module.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m7\iar\example_build\settings\sample_threadx_module.Debug.driver.xcl" + +@echo off +:end \ No newline at end of file diff --git a/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module.Debug.cspy.ps1 b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module.Debug.cspy.ps1 new file mode 100644 index 00000000..c549a6ee --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module.Debug.cspy.ps1 @@ -0,0 +1,31 @@ +param([String]$debugfile = ""); + +# This powershell file has been generated by the IAR Embedded Workbench +# C - SPY Debugger, as an aid to preparing a command line for running +# the cspybat command line utility using the appropriate settings. +# +# Note that this file is generated every time a new debug session +# is initialized, so you may want to move or rename the file before +# making changes. +# +# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed +# by the name of the debug file (usually an ELF / DWARF or UBROF file). +# +# Read about available command line parameters in the C - SPY Debugging +# Guide. Hints about additional command line parameters that may be +# useful in specific cases : +# --download_only Downloads a code image without starting a debug +# session afterwards. +# --silent Omits the sign - on message. +# --timeout Limits the maximum allowed execution time. +# + + +if ($debugfile -eq "") +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m7\iar\example_build\settings\sample_threadx_module.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m7\iar\example_build\settings\sample_threadx_module.Debug.driver.xcl" +} +else +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m7\iar\example_build\settings\sample_threadx_module.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m7\iar\example_build\settings\sample_threadx_module.Debug.driver.xcl" +} diff --git a/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module.Debug.driver.xcl b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module.Debug.driver.xcl new file mode 100644 index 00000000..b5f366cc --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module.Debug.driver.xcl @@ -0,0 +1,13 @@ +"--endian=little" + +"--cpu=Cortex-M7" + +"--fpu=None" + +"--semihosting" + +"--multicore_nr_of_cores=1" + + + + diff --git a/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module.Debug.general.xcl b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module.Debug.general.xcl new file mode 100644 index 00000000..ea598fba --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module.Debug.general.xcl @@ -0,0 +1,11 @@ +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armproc.dll" + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armsim2.dll" + +"C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m7\iar\example_build\Debug\Exe\sample_threadx_module.out" + +--plugin="C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armbat.dll" + + + + diff --git a/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module.crun b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module.crun new file mode 100644 index 00000000..d71ea555 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module.crun @@ -0,0 +1,13 @@ + + + 1 + + + * + * + * + 0 + 1 + + + diff --git a/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module.dbgdt b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module.dbgdt new file mode 100644 index 00000000..73e71f6e --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module.dbgdt @@ -0,0 +1,4 @@ + + + + diff --git a/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module.dnx b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module.dnx new file mode 100644 index 00000000..1872e83f --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module.dnx @@ -0,0 +1,58 @@ + + + + 0 + 0 + 1 + 0 + 1 + 0 + + + 0 + 0 + 1 + 0 + 1 + + + 0 + 1 + 90 + 1 + 1 + 1 + main + 0 + 50 + + + 0 + + + 0 + + + 1 + + + 1 + 0 + 1 + 0 + 1 + + + 0 + 1 + + + 0 + 0 + + + 10000000 + 0 + 1 + + diff --git a/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module_manager.Debug.cspy.bat b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module_manager.Debug.cspy.bat new file mode 100644 index 00000000..a532d244 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module_manager.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%~1" == "" goto debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m7\iar\example_build\settings\sample_threadx_module_manager.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m7\iar\example_build\settings\sample_threadx_module_manager.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m7\iar\example_build\settings\sample_threadx_module_manager.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m7\iar\example_build\settings\sample_threadx_module_manager.Debug.driver.xcl" + +@echo off +:end \ No newline at end of file diff --git a/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module_manager.Debug.cspy.ps1 b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module_manager.Debug.cspy.ps1 new file mode 100644 index 00000000..b8af99d4 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module_manager.Debug.cspy.ps1 @@ -0,0 +1,31 @@ +param([String]$debugfile = ""); + +# This powershell file has been generated by the IAR Embedded Workbench +# C - SPY Debugger, as an aid to preparing a command line for running +# the cspybat command line utility using the appropriate settings. +# +# Note that this file is generated every time a new debug session +# is initialized, so you may want to move or rename the file before +# making changes. +# +# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed +# by the name of the debug file (usually an ELF / DWARF or UBROF file). +# +# Read about available command line parameters in the C - SPY Debugging +# Guide. Hints about additional command line parameters that may be +# useful in specific cases : +# --download_only Downloads a code image without starting a debug +# session afterwards. +# --silent Omits the sign - on message. +# --timeout Limits the maximum allowed execution time. +# + + +if ($debugfile -eq "") +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m7\iar\example_build\settings\sample_threadx_module_manager.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m7\iar\example_build\settings\sample_threadx_module_manager.Debug.driver.xcl" +} +else +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m7\iar\example_build\settings\sample_threadx_module_manager.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m7\iar\example_build\settings\sample_threadx_module_manager.Debug.driver.xcl" +} diff --git a/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module_manager.Debug.driver.xcl b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module_manager.Debug.driver.xcl new file mode 100644 index 00000000..4dc7c280 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module_manager.Debug.driver.xcl @@ -0,0 +1,19 @@ +"--endian=little" + +"--cpu=Cortex-M7" + +"--fpu=VFPv5_SP" + +"-p" + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\CONFIG\debugger\ST\STM32F746IG.ddf" + +"--semihosting" + +"--device=STM32F746IG" + +"--multicore_nr_of_cores=1" + + + + diff --git a/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module_manager.Debug.general.xcl b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module_manager.Debug.general.xcl new file mode 100644 index 00000000..80a06546 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module_manager.Debug.general.xcl @@ -0,0 +1,19 @@ +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armproc.dll" + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armsim2.dll" + +"C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m7\iar\example_build\Debug\Exe\sample_threadx_module_manager_stm32f4xx.out" + +--plugin="C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armbat.dll" + +--device_macro="C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\config\debugger\ST\STM32F7xx.dmac" + +--device_macro="C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\config\debugger\ST\STM32F7xx_DBG.dmac" + +--device_macro="C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\config\debugger\ST\STM32F7xx_OB.dmac" + +--device_macro="C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\config\debugger\ST\STM32F7xx_TRACE.dmac" + + + + diff --git a/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module_manager.crun b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module_manager.crun new file mode 100644 index 00000000..d71ea555 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module_manager.crun @@ -0,0 +1,13 @@ + + + 1 + + + * + * + * + 0 + 1 + + + diff --git a/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module_manager.dbgdt b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module_manager.dbgdt new file mode 100644 index 00000000..7f17243d --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module_manager.dbgdt @@ -0,0 +1,1300 @@ + + + + + 34048 + 34049 + 34050 + 34051 + 34052 + 34053 + 34054 + 34055 + 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+ + + 34050 + 0A0000000A0000006E0000006E000000 + 0000000000000000150300001A000000 + 8192 + 0 + 0 + 767 + 0 + + + 1 + + + + diff --git a/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module_manager.dnx b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module_manager.dnx new file mode 100644 index 00000000..b8585020 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module_manager.dnx @@ -0,0 +1,133 @@ + + + + 0 + 1 + 90 + 1 + 1 + 1 + main + 0 + 50 + + + _ 0 + _ 0 + + + 2229266535 + + + 0 + 1 + + + 0 + 0 + 0 + + + 0 + 1 + + + _ 0 + _ 0 + + + 0 + + + ULONG[3] 4 0 + + + {W}1:param_0 4 0 + + + 0 + 1 + 0 + 0 + + + 0 + + + 1 + + + _ 0 + _ "" + + + _ 0 + _ "" + _ 0 + + + 0 + 0 + 1 + 0 + 1 + 0 + + + 0 + 0 + 1 + 0 + 1 + + + 0 + + + _ 0 "STD_CODE2" "0x08002F32" 0 0 1 "" 0 "" + 1 + + + 1 + _ 0 9999 0 9999 1 0 0 100 0 1 "SysTick 1 0x3C" + 1 + + + 1 + 0 + 1 + 0 + 1 + _ 0 134217728 135266303 1 + _ 0 536870912 537198591 0 + _ 0 541392896 541458432 0 + 3 + + + _ "C:\Users\nisohack\Documents\work\tasks\st_work\threadx_07242020_rc2\common\src\tx_block_allocate.c" "" + _ "C:\Users\nisohack\Documents\work\tasks\st_work\threadx_07242020_rc2\common\src\tx_block_pool_cleanup.c" "" + _ "C:\Users\nisohack\Documents\work\tasks\st_work\threadx_07242020_rc2\common\src\tx_block_pool_create.c" "" + _ "C:\Users\nisohack\Documents\work\tasks\st_work\threadx_07242020_rc2\common\src\tx_block_pool_delete.c" "" + _ "C:\Users\nisohack\Documents\work\tasks\st_work\threadx_07242020_rc2\common\src\tx_block_pool_info_get.c" "" + _ "C:\Users\nisohack\Documents\work\tasks\st_work\threadx_07242020_rc2\common\src\tx_block_pool_performance_info_get.c" "" + _ "C:\Users\nisohack\Documents\work\tasks\st_work\threadx_07242020_rc2\common\src\tx_block_pool_performance_system_info_get.c" "" + _ "C:\Users\nisohack\Documents\work\tasks\st_work\threadx_07242020_rc2\common\src\tx_block_pool_prioritize.c" "" + _ "C:\Users\nisohack\Documents\work\tasks\st_work\threadx_07242020_rc2\common\src\tx_block_release.c" "" + _ "C:\Users\nisohack\Documents\work\tasks\st_work\threadx_07242020_rc2\common\src\tx_byte_allocate.c" "" + _ "C:\Users\nisohack\Documents\work\tasks\st_work\threadx_07242020_rc2\common\src\tx_byte_pool_cleanup.c" "" + _ "C:\Users\nisohack\Documents\work\tasks\st_work\threadx_07242020_rc2\common\src\tx_byte_pool_create.c" "" + _ "C:\Users\nisohack\Documents\work\tasks\st_work\threadx_07242020_rc2\common\src\tx_byte_pool_delete.c" "" + _ "C:\Users\nisohack\Documents\work\tasks\st_work\threadx_07242020_rc2\common\src\tx_byte_pool_info_get.c" "" + _ "C:\Users\nisohack\Documents\work\tasks\st_work\threadx_07242020_rc2\common\src\tx_byte_pool_performance_info_get.c" "" + _ "C:\Users\nisohack\Documents\work\tasks\st_work\threadx_07242020_rc2\common\src\tx_byte_pool_performance_system_info_get.c" "" + _ "C:\Users\nisohack\Documents\work\tasks\st_work\threadx_07242020_rc2\common\src\tx_byte_pool_prioritize.c" "" + _ "C:\Users\nisohack\Documents\work\tasks\st_work\threadx_07242020_rc2\common\src\tx_byte_pool_search.c" "" + 18 + 1 + + + 10000000 + 0 + 1 + + diff --git a/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module_manager.reggroups b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module_manager.reggroups new file mode 100644 index 00000000..5f282702 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/settings/sample_threadx_module_manager.reggroups @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/ports_module/cortex-m7/iar/example_build/settings/tx.Debug.cspy.bat b/ports_module/cortex-m7/iar/example_build/settings/tx.Debug.cspy.bat new file mode 100644 index 00000000..d76cfad9 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/settings/tx.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%~1" == "" goto debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" + +@echo off +:end \ No newline at end of file diff --git a/ports_module/cortex-m7/iar/example_build/settings/tx.Debug.cspy.ps1 b/ports_module/cortex-m7/iar/example_build/settings/tx.Debug.cspy.ps1 new file mode 100644 index 00000000..1c1ba13b --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/settings/tx.Debug.cspy.ps1 @@ -0,0 +1,31 @@ +param([String]$debugfile = ""); + +# This powershell file has been generated by the IAR Embedded Workbench +# C - SPY Debugger, as an aid to preparing a command line for running +# the cspybat command line utility using the appropriate settings. +# +# Note that this file is generated every time a new debug session +# is initialized, so you may want to move or rename the file before +# making changes. +# +# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed +# by the name of the debug file (usually an ELF / DWARF or UBROF file). +# +# Read about available command line parameters in the C - SPY Debugging +# Guide. Hints about additional command line parameters that may be +# useful in specific cases : +# --download_only Downloads a code image without starting a debug +# session afterwards. +# --silent Omits the sign - on message. +# --timeout Limits the maximum allowed execution time. +# + + +if ($debugfile -eq "") +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" +} +else +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\common\bin\cspybat" -f "C:\release\threadx\settings\tx.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\release\threadx\settings\tx.Debug.driver.xcl" +} diff --git a/ports_module/cortex-m7/iar/example_build/settings/tx.Debug.driver.xcl b/ports_module/cortex-m7/iar/example_build/settings/tx.Debug.driver.xcl new file mode 100644 index 00000000..b5f366cc --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/settings/tx.Debug.driver.xcl @@ -0,0 +1,13 @@ +"--endian=little" + +"--cpu=Cortex-M7" + +"--fpu=None" + +"--semihosting" + +"--multicore_nr_of_cores=1" + + + + diff --git a/ports_module/cortex-m7/iar/example_build/settings/tx.Debug.general.xcl b/ports_module/cortex-m7/iar/example_build/settings/tx.Debug.general.xcl new file mode 100644 index 00000000..ef6d6dd5 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/settings/tx.Debug.general.xcl @@ -0,0 +1,11 @@ +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\bin\armproc.dll" + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\bin\armsim2.dll" + +"C:\release\threadx\Debug\Exe\tx.out" + +--plugin "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.0\arm\bin\armbat.dll" + + + + diff --git a/ports_module/cortex-m7/iar/example_build/settings/tx.crun b/ports_module/cortex-m7/iar/example_build/settings/tx.crun new file mode 100644 index 00000000..d71ea555 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/settings/tx.crun @@ -0,0 +1,13 @@ + + + 1 + + + * + * + * + 0 + 1 + + + diff --git a/ports_module/cortex-m7/iar/example_build/settings/tx.dbgdt b/ports_module/cortex-m7/iar/example_build/settings/tx.dbgdt new file mode 100644 index 00000000..73e71f6e --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/settings/tx.dbgdt @@ -0,0 +1,4 @@ + + + + diff --git a/ports_module/cortex-m7/iar/example_build/settings/tx.dnx b/ports_module/cortex-m7/iar/example_build/settings/tx.dnx new file mode 100644 index 00000000..1872e83f --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/settings/tx.dnx @@ -0,0 +1,58 @@ + + + + 0 + 0 + 1 + 0 + 1 + 0 + + + 0 + 0 + 1 + 0 + 1 + + + 0 + 1 + 90 + 1 + 1 + 1 + main + 0 + 50 + + + 0 + + + 0 + + + 1 + + + 1 + 0 + 1 + 0 + 1 + + + 0 + 1 + + + 0 + 0 + + + 10000000 + 0 + 1 + + diff --git a/ports_module/cortex-m7/iar/example_build/settings/txm.Debug.cspy.bat b/ports_module/cortex-m7/iar/example_build/settings/txm.Debug.cspy.bat new file mode 100644 index 00000000..56db7d18 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/settings/txm.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%~1" == "" goto debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m7\iar\example_build\settings\txm.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m7\iar\example_build\settings\txm.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m7\iar\example_build\settings\txm.Debug.general.xcl" "--debug_file=%~1" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m7\iar\example_build\settings\txm.Debug.driver.xcl" + +@echo off +:end \ No newline at end of file diff --git a/ports_module/cortex-m7/iar/example_build/settings/txm.Debug.cspy.ps1 b/ports_module/cortex-m7/iar/example_build/settings/txm.Debug.cspy.ps1 new file mode 100644 index 00000000..e8c822e5 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/settings/txm.Debug.cspy.ps1 @@ -0,0 +1,31 @@ +param([String]$debugfile = ""); + +# This powershell file has been generated by the IAR Embedded Workbench +# C - SPY Debugger, as an aid to preparing a command line for running +# the cspybat command line utility using the appropriate settings. +# +# Note that this file is generated every time a new debug session +# is initialized, so you may want to move or rename the file before +# making changes. +# +# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed +# by the name of the debug file (usually an ELF / DWARF or UBROF file). +# +# Read about available command line parameters in the C - SPY Debugging +# Guide. Hints about additional command line parameters that may be +# useful in specific cases : +# --download_only Downloads a code image without starting a debug +# session afterwards. +# --silent Omits the sign - on message. +# --timeout Limits the maximum allowed execution time. +# + + +if ($debugfile -eq "") +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m7\iar\example_build\settings\txm.Debug.general.xcl" --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m7\iar\example_build\settings\txm.Debug.driver.xcl" +} +else +{ +& "C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\common\bin\cspybat" -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m7\iar\example_build\settings\txm.Debug.general.xcl" --debug_file=$debugfile --backend -f "C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m7\iar\example_build\settings\txm.Debug.driver.xcl" +} diff --git a/ports_module/cortex-m7/iar/example_build/settings/txm.Debug.driver.xcl b/ports_module/cortex-m7/iar/example_build/settings/txm.Debug.driver.xcl new file mode 100644 index 00000000..b5f366cc --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/settings/txm.Debug.driver.xcl @@ -0,0 +1,13 @@ +"--endian=little" + +"--cpu=Cortex-M7" + +"--fpu=None" + +"--semihosting" + +"--multicore_nr_of_cores=1" + + + + diff --git a/ports_module/cortex-m7/iar/example_build/settings/txm.Debug.general.xcl b/ports_module/cortex-m7/iar/example_build/settings/txm.Debug.general.xcl new file mode 100644 index 00000000..7a84fea8 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/settings/txm.Debug.general.xcl @@ -0,0 +1,11 @@ +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armproc.dll" + +"C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armsim2.dll" + +"C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_module\cortex-m7\iar\example_build\Debug\Exe\txm.out" + +--plugin="C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4\arm\bin\armbat.dll" + + + + diff --git a/ports_module/cortex-m7/iar/example_build/settings/txm.crun b/ports_module/cortex-m7/iar/example_build/settings/txm.crun new file mode 100644 index 00000000..d71ea555 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/settings/txm.crun @@ -0,0 +1,13 @@ + + + 1 + + + * + * + * + 0 + 1 + + + diff --git a/ports_module/cortex-m7/iar/example_build/settings/txm.dbgdt b/ports_module/cortex-m7/iar/example_build/settings/txm.dbgdt new file mode 100644 index 00000000..9e08d965 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/settings/txm.dbgdt @@ -0,0 +1,4 @@ + + + + diff --git a/ports_module/cortex-m7/iar/example_build/settings/txm.dnx b/ports_module/cortex-m7/iar/example_build/settings/txm.dnx new file mode 100644 index 00000000..25e4c4ba --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/settings/txm.dnx @@ -0,0 +1,58 @@ + + + + 0 + 1 + 90 + 1 + 1 + 1 + main + 0 + 50 + + + 0 + 1 + + + 0 + 0 + 1 + 0 + 1 + 0 + + + 0 + 0 + 1 + 0 + 1 + + + 0 + + + 0 + + + 1 + + + 1 + 0 + 1 + 0 + 1 + + + 0 + 0 + + + 10000000 + 0 + 1 + + diff --git a/ports_module/cortex-m7/iar/example_build/startup.s b/ports_module/cortex-m7/iar/example_build/startup.s new file mode 100644 index 00000000..b1d725f7 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/startup.s @@ -0,0 +1,730 @@ +;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** +;* File Name : startup_stm32f746xx.s +;* Author : MCD Application Team +;* Version : V1.1.0 +;* Date : 30-December-2016 +;* Description : STM32F746xx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M7 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD RNG_IRQHandler ; Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD SAI2_IRQHandler ; SAI2 + DCD QUADSPI_IRQHandler ; QUADSPI + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD SPDIF_RX_IRQHandler ; SPDIF_RX +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK SDMMC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC1_IRQHandler + B SDMMC1_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK ETH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_IRQHandler + B ETH_IRQHandler + + PUBWEAK ETH_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_WKUP_IRQHandler + B ETH_WKUP_IRQHandler + + PUBWEAK CAN2_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN2_TX_IRQHandler + B CAN2_TX_IRQHandler + + PUBWEAK CAN2_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN2_RX0_IRQHandler + B CAN2_RX0_IRQHandler + + PUBWEAK CAN2_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN2_RX1_IRQHandler + B CAN2_RX1_IRQHandler + + PUBWEAK CAN2_SCE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN2_SCE_IRQHandler + B CAN2_SCE_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_OUT_IRQHandler + B OTG_HS_EP1_OUT_IRQHandler + + PUBWEAK OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_IN_IRQHandler + B OTG_HS_EP1_IN_IRQHandler + + PUBWEAK OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_WKUP_IRQHandler + B OTG_HS_WKUP_IRQHandler + + PUBWEAK OTG_HS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_IRQHandler + B OTG_HS_IRQHandler + + PUBWEAK DCMI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DCMI_IRQHandler + B DCMI_IRQHandler + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_IRQHandler + B RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK UART7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART7_IRQHandler + B UART7_IRQHandler + + PUBWEAK UART8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART8_IRQHandler + B UART8_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + PUBWEAK SPI6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI6_IRQHandler + B SPI6_IRQHandler + + PUBWEAK SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler + + PUBWEAK LTDC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_IRQHandler + B LTDC_IRQHandler + + PUBWEAK LTDC_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler + + PUBWEAK DMA2D_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler + + PUBWEAK SAI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI2_IRQHandler + B SAI2_IRQHandler + + PUBWEAK QUADSPI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + + PUBWEAK LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler + + PUBWEAK I2C4_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_EV_IRQHandler + B I2C4_EV_IRQHandler + + PUBWEAK I2C4_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_ER_IRQHandler + B I2C4_ER_IRQHandler + + PUBWEAK SPDIF_RX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPDIF_RX_IRQHandler + B SPDIF_RX_IRQHandler + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/ports_module/cortex-m7/iar/example_build/tx.ewd b/ports_module/cortex-m7/iar/example_build/tx.ewd new file mode 100644 index 00000000..5bb89d18 --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/tx.ewd @@ -0,0 +1,2974 @@ + + + 3 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 32 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 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+;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_initialize.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_initialize_unused_memory + EXTERN _tx_timer_interrupt + EXTERN __vector_table + EXTERN _tx_execution_isr_enter + EXTERN _tx_execution_isr_exit +; +; +SYSTEM_CLOCK EQU 25000000 +SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1) + + RSEG FREE_MEM:DATA + PUBLIC __tx_free_memory_start +__tx_free_memory_start + DS32 4 +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-M7/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + PUBLIC _tx_initialize_low_level +_tx_initialize_low_level: +; +; /* Ensure that interrupts are disabled. */ +; + CPSID i ; Disable interrupts +; +; +; /* Set base of available memory to end of non-initialised RAM area. */ +; + LDR r0, =__tx_free_memory_start ; Get end of non-initialized RAM area + LDR r2, =_tx_initialize_unused_memory ; Build address of unused memory pointer + STR r0, [r2, #0] ; Save first free memory address +; +; /* Enable the cycle count register. */ +; + LDR r0, =0xE0001000 ; Build address of DWT register + LDR r1, [r0] ; Pickup the current value + ORR r1, r1, #1 ; Set the CYCCNTENA bit + STR r1, [r0] ; Enable the cycle count register +; +; /* Setup Vector Table Offset Register. */ +; + MOV r0, #0xE000E000 ; Build address of NVIC registers + LDR r1, =__vector_table ; Pickup address of vector table + STR r1, [r0, #0xD08] ; Set vector table address +; +; /* Set system stack pointer from vector value. */ +; + LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer + LDR r1, =__vector_table ; Pickup address of vector table + LDR r1, [r1] ; Pickup reset stack pointer + STR r1, [r0] ; Save system stack pointer +; +; /* Configure SysTick. */ +; + MOV r0, #0xE000E000 ; Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] ; Setup SysTick Reload Value + MOV r1, #0x7 ; Build SysTick Control Enable Value + STR r1, [r0, #0x10] ; Setup SysTick Control +; +; /* Configure handler priorities. */ +; + LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM + STR r1, [r0, #0xD18] ; Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv + STR r1, [r0, #0xD1C] ; Setup System Handlers 8-11 Priority Registers + ; Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM + STR r1, [r0, #0xD20] ; Setup System Handlers 12-15 Priority Registers + ; Note: PnSV must be lowest priority, which is 0xFF +; +; /* Return to caller. */ +; + BX lr +;} +; +; + PUBLIC SysTick_Handler + PUBLIC __tx_SysTickHandler +__tx_SysTickHandler: +SysTick_Handler: +; +; VOID SysTick_Handler (VOID) +; { +; + PUSH {r0, lr} +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_enter ; Call the ISR enter function +#endif + BL _tx_timer_interrupt +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + BL _tx_execution_isr_exit ; Call the ISR exit function +#endif + POP {r0, lr} + BX LR +; } + END + diff --git a/ports_module/cortex-m7/iar/example_build/txm.ewd b/ports_module/cortex-m7/iar/example_build/txm.ewd new file mode 100644 index 00000000..21bf663c --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/txm.ewd @@ -0,0 +1,2974 @@ + + + 3 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 32 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_semaphore_performance_info_get.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_semaphore_performance_system_info_get.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_semaphore_prioritize.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_semaphore_put.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_semaphore_put_notify.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_thread_create.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_thread_delete.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_thread_entry_exit_notify.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_thread_identify.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_thread_info_get.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_thread_interrupt_control.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_thread_performance_info_get.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_thread_performance_system_info_get.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_thread_preemption_change.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_thread_priority_change.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_thread_relinquish.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_thread_reset.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_thread_resume.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_thread_sleep.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_thread_stack_error_notify.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_thread_suspend.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_thread_terminate.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_thread_time_slice_change.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_thread_wait_abort.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_time_get.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_time_set.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_timer_activate.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_timer_change.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_timer_create.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_timer_deactivate.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_timer_delete.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_timer_info_get.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_timer_performance_info_get.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_timer_performance_system_info_get.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_trace_buffer_full_notify.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_trace_disable.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_trace_enable.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_trace_event_filter.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_trace_event_unfilter.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_trace_interrupt_control.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_trace_isr_enter_insert.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_trace_isr_exit_insert.c + + + $PROJ_DIR$\..\..\..\..\modules\module_lib\src\txm_trace_user_event_insert.c + + + diff --git a/ports_module/cortex-m7/iar/example_build/txm_module_preamble.s b/ports_module/cortex-m7/iar/example_build/txm_module_preamble.s new file mode 100644 index 00000000..44819d7f --- /dev/null +++ b/ports_module/cortex-m7/iar/example_build/txm_module_preamble.s @@ -0,0 +1,70 @@ + SECTION .text:CODE + + AAPCS INTERWORK, ROPI, RWPI_COMPATIBLE, VFP_COMPATIBLE + PRESERVE8 + + /* Define public symbols. */ + + PUBLIC __txm_module_preamble + + + /* Define application-specific start/stop entry points for the module. */ + + EXTERN demo_module_start + + + /* Define common external refrences. */ + + EXTERN _txm_module_thread_shell_entry + EXTERN _txm_module_callback_request_thread_entry + EXTERN ROPI$$Length + EXTERN RWPI$$Length + + DATA +__txm_module_preamble: + DC32 0x4D4F4455 ; Module ID + DC32 0x5 ; Module Major Version + DC32 0x6 ; Module Minor Version + DC32 32 ; Module Preamble Size in 32-bit words + DC32 0x12345678 ; Module ID (application defined) + DC32 0x00000007 ; Module Properties where: + ; Bits 31-24: Compiler ID + ; 0 -> IAR + ; 1 -> RVDS + ; 2 -> GNU + ; Bit 0: 0 -> Privileged mode execution + ; 1 -> User mode execution + ; Bit 1: 0 -> No MPU protection + ; 1 -> MPU protection (must have user mode selected) + ; Bit 2: 0 -> Disable shared/external memory access + ; 1 -> Enable shared/external memory access + DC32 _txm_module_thread_shell_entry - . - 0 ; Module Shell Entry Point + DC32 demo_module_start - . - 0 ; Module Start Thread Entry Point + DC32 0 ; Module Stop Thread Entry Point + DC32 1 ; Module Start/Stop Thread Priority + DC32 1024 ; Module Start/Stop Thread Stack Size + DC32 _txm_module_callback_request_thread_entry - . - 0 ; Module Callback Thread Entry + DC32 1 ; Module Callback Thread Priority + DC32 1024 ; Module Callback Thread Stack Size + DC32 ROPI$$Length ; Module Code Size + DC32 RWPI$$Length ; Module Data Size + DC32 0 ; Reserved 0 + DC32 0 ; Reserved 1 + DC32 0 ; Reserved 2 + DC32 0 ; Reserved 3 + DC32 0 ; Reserved 4 + DC32 0 ; Reserved 5 + DC32 0 ; Reserved 6 + DC32 0 ; Reserved 7 + DC32 0 ; Reserved 8 + DC32 0 ; Reserved 9 + DC32 0 ; Reserved 10 + DC32 0 ; Reserved 11 + DC32 0 ; Reserved 12 + DC32 0 ; Reserved 13 + DC32 0 ; Reserved 14 + DC32 0 ; Reserved 15 + + END + + diff --git a/ports_module/cortex-m7/iar/inc/tx_port.h b/ports_module/cortex-m7/iar/inc/tx_port.h new file mode 100644 index 00000000..745fb5fe --- /dev/null +++ b/ports_module/cortex-m7/iar/inc/tx_port.h @@ -0,0 +1,528 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-M7/IAR */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include +#include +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX Cortex-M3 port. */ + +#define TX_INT_DISABLE 1 /* Disable interrupts */ +#define TX_INT_ENABLE 0 /* Enable interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) +#endif +#else +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif + +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; \ + VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; +#endif +#ifndef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#define TX_THREAD_EXTENSION_3 +#else +#define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ + unsigned long long tx_thread_execution_time_last_start; +#endif + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#if (__VER__ < 8000000) +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); +#else +void *_tx_iar_create_per_thread_tls_area(void); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); +void __iar_Initlocks(void); + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#endif +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + + +#ifdef __ARMVFP__ + +#ifdef TX_MISRA_ENABLE + +ULONG _tx_misra_control_get(void); +void _tx_misra_control_set(ULONG value); +ULONG _tx_misra_fpccr_get(void); +void _tx_misra_vfp_touch(void); + +#endif + +/* A completed thread falls into _thread_shell_entry and we can simply deactivate the FPU via CONTROL.FPCA + in order to ensure no lazy stacking will occur. */ + +#ifndef TX_MISRA_ENABLE + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_CONTROL(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_CONTROL(_tx_vfp_state); \ + } +#else + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } + +#endif + +/* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. + If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + the lazy FPU save, then restore the CONTROL.FPCA state. */ + +#ifndef TX_MISRA_ENABLE + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_CONTROL(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_CONTROL(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = *((ULONG *) 0xE000EF34); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_CONTROL(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + __asm volatile ("vmov.f32 s0, s0"); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = __get_CONTROL(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_CONTROL(_tx_vfp_state); \ + } \ + } \ + } \ + } +#else + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = _tx_misra_fpccr_get(); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + _tx_misra_vfp_touch(); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + } \ + } \ + } +#endif + +#else + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + +#endif + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define the get system state macro. */ + +#ifndef TX_THREAD_GET_SYSTEM_STATE +#ifndef TX_MISRA_ENABLE +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | __get_IPSR()) +#else +ULONG _tx_misra_ipsr_get(VOID); +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get()) +#endif +#endif + + +/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value + indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h + for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always + zero after initialization for Cortex-M ports. */ + +#ifndef TX_THREAD_SYSTEM_RETURN_CHECK +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#endif + + +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to + prevent early scheduling on Cortex-M parts. */ + +#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT)__CLZ(__RBIT((m))); + +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +/* The embedded assembler blocks are design so as to be inlinable by the + armlink linker inlining. This requires them to consist of either a + single 32-bit instruction, or either one or two 16-bit instructions + followed by a "BX lr". Note that to reduce the critical region size, the + 16-bit "CPSID i" instruction is preceeded by a 16-bit NOP */ + +#ifdef TX_DISABLE_INLINE + +UINT _tx_thread_interrupt_disable(VOID); +VOID _tx_thread_interrupt_restore(UINT previous_posture); + +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); + +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA __istate_t interrupt_save; +#define TX_DISABLE {interrupt_save = __get_interrupt_state();__disable_interrupt();}; +#define TX_RESTORE {__set_interrupt_state(interrupt_save);}; + +#define _tx_thread_system_return _tx_thread_system_return_inline + +static void _tx_thread_system_return_inline(void) +{ +__istate_t interrupt_save; + + /* Set PendSV to invoke ThreadX scheduler. */ + *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + if (__get_IPSR() == 0) + { + interrupt_save = __get_interrupt_state(); + __enable_interrupt(); + __set_interrupt_state(interrupt_save); + } +} + +#endif + + +/* Define FPU extension for the Cortex-M7. Each is assumed to be called in the context of the executing + thread. These are no longer needed, but are preserved for backward compatibility only. */ + +void tx_thread_fpu_enable(void); +void tx_thread_fpu_disable(void); + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/IAR Version 6.0.1 *"; +#else +#ifdef TX_MISRA_ENABLE +extern CHAR _tx_version_id[100]; +#else +extern CHAR _tx_version_id[]; +#endif +#endif + + +#endif + + + diff --git a/ports_module/cortex-m7/iar/inc/txm_module_port.h b/ports_module/cortex-m7/iar/inc/txm_module_port.h new file mode 100644 index 00000000..2e101a44 --- /dev/null +++ b/ports_module/cortex-m7/iar/inc/txm_module_port.h @@ -0,0 +1,359 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* txm_module_port.h Cortex-M7/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the basic module constants, interface structures, */ +/* and function prototypes. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TXM_MODULE_PORT_H +#define TXM_MODULE_PORT_H + +/* It is assumed that the base ThreadX tx_port.h file has been modified to add the + following extensions to the ThreadX thread control block (this code should replace + the corresponding macro define in tx_port.h): + +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; \ + VOID *tx_thread_iar_tls_pointer; + +The following extensions must also be defined in tx_port.h: + +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); + +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); +*/ + +#define TXM_MODULE_THREAD_ENTRY_INFO_USER_EXTENSION + +/**************************************************************************/ +/* User-adjustable constants */ +/**************************************************************************/ + +/* Define the kernel stack size for a module thread. */ +#ifndef TXM_MODULE_KERNEL_STACK_SIZE +#define TXM_MODULE_KERNEL_STACK_SIZE 512 +#endif + +/* For the following 3 access control settings, change TEX and C, B, S (bits 21 through 16 of MPU_RASR) + * to reflect your system memory attributes (cache, shareable, memory type). */ +/* Code region access control: privileged read-only, outer & inner write-back, normal memory, shareable. */ +#define TXM_MODULE_MPU_CODE_ACCESS_CONTROL 0x06070000 +/* Data region access control: execute never, read/write, outer & inner write-back, normal memory, shareable. */ +#define TXM_MODULE_MPU_DATA_ACCESS_CONTROL 0x13070000 +/* Shared region access control: execute never, read-only, outer & inner write-back, normal memory, shareable. */ +#define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 + +/**************************************************************************/ +/* End of user-adjustable constants */ +/**************************************************************************/ + + + +/* Define constants specific to the tools the module can be built with for this particular modules port. */ + +#define TXM_MODULE_IAR_COMPILER 0x00000000 +#define TXM_MODULE_RVDS_COMPILER 0x01000000 +#define TXM_MODULE_GNU_COMPILER 0x02000000 +#define TXM_MODULE_COMPILER_MASK 0xFF000000 +#define TXM_MODULE_OPTIONS_MASK 0x000000FF + + +/* Define the properties for this particular module port. */ + +#define TXM_MODULE_MEMORY_PROTECTION_ENABLED + +#ifdef TXM_MODULE_MEMORY_PROTECTION_ENABLED +#define TXM_MODULE_REQUIRE_ALLOCATED_OBJECT_MEMORY +#else +#define TXM_MODULE_REQUIRE_LOCAL_OBJECT_MEMORY +#endif + +#define TXM_MODULE_USER_MODE 0x00000001 +#define TXM_MODULE_MEMORY_PROTECTION 0x00000002 +#define TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS 0x00000004 + + +/* Define the supported options for this module. */ + +#define TXM_MODULE_MANAGER_SUPPORTED_OPTIONS (TXM_MODULE_USER_MODE | TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS) +#define TXM_MODULE_MANAGER_REQUIRED_OPTIONS 0 + + +/* Define offset adjustments according to the compiler used to build the module. */ + +#define TXM_MODULE_IAR_SHELL_ADJUST 24 +#define TXM_MODULE_IAR_START_ADJUST 28 +#define TXM_MODULE_IAR_STOP_ADJUST 32 +#define TXM_MODULE_IAR_CALLBACK_ADJUST 44 + +#define TXM_MODULE_RVDS_SHELL_ADJUST 0 +#define TXM_MODULE_RVDS_START_ADJUST 0 +#define TXM_MODULE_RVDS_STOP_ADJUST 0 +#define TXM_MODULE_RVDS_CALLBACK_ADJUST 0 + +#define TXM_MODULE_GNU_SHELL_ADJUST 24 +#define TXM_MODULE_GNU_START_ADJUST 28 +#define TXM_MODULE_GNU_STOP_ADJUST 32 +#define TXM_MODULE_GNU_CALLBACK_ADJUST 44 + + +/* Define other module port-specific constants. */ + +/* Define INLINE_DECLARE to inline for IAR compiler. */ + +#define INLINE_DECLARE inline + +/* Define the number of MPU entries assigned to the code and data sections. + On Cortex-M7 parts, there are 16 total entries. ThreadX uses one for access + to the kernel entry function, thus 15 remain for code and data protection. */ +#define TXM_MODULE_MPU_TOTAL_ENTRIES 16 +#define TXM_MODULE_MPU_CODE_ENTRIES 4 +#define TXM_MODULE_MPU_DATA_ENTRIES 4 +#define TXM_MODULE_MPU_SHARED_ENTRIES 3 + +#define TXM_MODULE_MPU_KERNEL_ENTRY_INDEX 0 +#define TXM_MODULE_MPU_SHARED_INDEX 9 + +#define TXM_ENABLE_REGION 0x01 + +/* There are 2 registers to set up each MPU region: MPU_RBAR, MPU_RASR. */ +typedef struct TXM_MODULE_MPU_INFO_STRUCT +{ + ULONG txm_module_mpu_region_address; + ULONG txm_module_mpu_region_attribute_size; +} TXM_MODULE_MPU_INFO; +/* Shared memory region attributes. */ +#define TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE 1 +#define TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT 0x01000000 + +/* Define the port-extensions to the module manager instance structure. */ + +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_count; \ + ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES]; + + +/* Define the memory fault information structure that is populated when a memory fault occurs. */ + + +typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT +{ + TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr; + VOID *txm_module_manager_memory_fault_info_code_location; + ULONG txm_module_manager_memory_fault_info_shcsr; + ULONG txm_module_manager_memory_fault_info_mmfsr; + ULONG txm_module_manager_memory_fault_info_mmfar; + ULONG txm_module_manager_memory_fault_info_control; + ULONG txm_module_manager_memory_fault_info_sp; + ULONG txm_module_manager_memory_fault_info_r0; + ULONG txm_module_manager_memory_fault_info_r1; + ULONG txm_module_manager_memory_fault_info_r2; + ULONG txm_module_manager_memory_fault_info_r3; + ULONG txm_module_manager_memory_fault_info_r4; + ULONG txm_module_manager_memory_fault_info_r5; + ULONG txm_module_manager_memory_fault_info_r6; + ULONG txm_module_manager_memory_fault_info_r7; + ULONG txm_module_manager_memory_fault_info_r8; + ULONG txm_module_manager_memory_fault_info_r9; + ULONG txm_module_manager_memory_fault_info_r10; + ULONG txm_module_manager_memory_fault_info_r11; + ULONG txm_module_manager_memory_fault_info_r12; + ULONG txm_module_manager_memory_fault_info_lr; + ULONG txm_module_manager_memory_fault_info_xpsr; +} TXM_MODULE_MANAGER_MEMORY_FAULT_INFO; + + +#define TXM_MODULE_MANAGER_FAULT_INFO \ + TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; + +/* Define the macro to check the stack available in dispatch. */ +#define TXM_MODULE_MANAGER_CHECK_STACK_AVAILABLE \ + ULONG stack_available; \ + __asm("MOV %0, SP" : "=r"(stack_available)); \ + stack_available -= (ULONG)_tx_thread_current_ptr->tx_thread_stack_start; \ + if((stack_available < TXM_MODULE_MINIMUM_STACK_AVAILABLE) || \ + (stack_available > _tx_thread_current_ptr->tx_thread_stack_size)) \ + { \ + return(TX_SIZE_ERROR); \ + } + + +/* Define the macro to check the code alignment. */ + +#define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment) \ + { \ + ULONG temp; \ + temp = (ULONG) module_location; \ + temp = temp & (code_alignment - 1); \ + if (temp) \ + { \ + _tx_mutex_put(&_txm_module_manager_mutex); \ + return(TXM_MODULE_ALIGNMENT_ERROR); \ + } \ + } + + +/* Define the macro to adjust the alignment and size for code/data areas. */ + +#define TXM_MODULE_MANAGER_ALIGNMENT_ADJUST(module_preamble, code_size, code_alignment, data_size, data_alignment) _txm_module_manager_alignment_adjust(module_preamble, &code_size, &code_alignment, &data_size, &data_alignment); + + +/* Define the macro to adjust the symbols in the module preamble. */ + +#define TXM_MODULE_MANAGER_CALCULATE_ADJUSTMENTS(properties, shell_function_adjust, start_function_adjust, stop_function_adjust, callback_function_adjust) \ + if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_IAR_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_IAR_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_IAR_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_IAR_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_IAR_CALLBACK_ADJUST; \ + } \ + else if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_RVDS_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_RVDS_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_RVDS_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_RVDS_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_RVDS_CALLBACK_ADJUST; \ + } \ + else \ + { \ + shell_function_adjust = TXM_MODULE_GNU_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_GNU_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_GNU_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_GNU_CALLBACK_ADJUST; \ + } + + +/* Define the macro to populate the thread control block with module port-specific information. + Check if the module is in user mode and set up txm_module_thread_entry_info_kernel_call_dispatcher accordingly. +*/ + +#define TXM_MODULE_MANAGER_THREAD_SETUP(thread_ptr, module_instance) \ + thread_ptr -> tx_thread_module_current_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \ + thread_ptr -> tx_thread_module_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \ + if (thread_ptr -> tx_thread_module_user_mode) \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_user_mode_entry; \ + } \ + else \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_kernel_dispatch; \ + } + + +/* Define the macro to populate the module control block with module port-specific information. + If memory protection is enabled, set up the MPU registers. +*/ +#define TXM_MODULE_MANAGER_MODULE_SETUP(module_instance) \ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE) \ + { \ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) \ + { \ + _txm_module_manager_mm_register_setup(module_instance); \ + } \ + } \ + else \ + { \ + /* Do nothing. */ \ + } + +/* Define the macro to perform port-specific functions when unloading the module. */ +/* Nothing needs to be done for this port. */ +#define TXM_MODULE_MANAGER_MODULE_UNLOAD(module_instance) + +/* Define the macro to perform port-specific functions when passing function pointer to kernel. */ +/* Determine if the pointer is within the module's code memory. */ +#define TXM_MODULE_MANAGER_CHECK_FUNCTION_POINTER(module_instance, pointer) \ + if (((pointer < sizeof(TXM_MODULE_PREAMBLE) + (ULONG) module_instance -> txm_module_instance_code_start) || \ + ((pointer+sizeof(pointer)) > (ULONG) module_instance -> txm_module_instance_code_end)) \ + && (pointer != (ULONG) TX_NULL)) \ + { \ + return(TX_PTR_ERROR); \ + } + +/* Define some internal prototypes to this module port. */ + +#ifndef TX_SOURCE_CODE +#define txm_module_manager_memory_fault_notify _txm_module_manager_memory_fault_notify +#endif + + +#define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES \ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment); \ +ULONG _txm_module_manager_data_pointer_check(TXM_MODULE_INSTANCE *module_instance, ULONG pointer); \ +VOID _txm_module_manager_memory_fault_handler(VOID); \ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)); \ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \ +ULONG _txm_power_of_two_block_size(ULONG size); \ +ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length); \ +ULONG _txm_module_manager_region_size_get(ULONG block_size); \ +UCHAR _txm_module_manager_shared_memory_check_outside(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size); \ +UCHAR _txm_module_manager_shared_memory_check_inside(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size); \ +UCHAR _txm_module_manager_shared_memory_check_inside_byte(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr); + +#define TXM_MODULE_MANAGER_VERSION_ID \ +CHAR _txm_module_manager_version_id[] = \ + "Copyright (c) 1996-2018 Express Logic Inc. * ThreadX Module Cortex-M7/MPU/IAR Version G5.8.2 *"; + +#endif + diff --git a/ports_module/cortex-m7/iar/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex-m7/iar/module_lib/src/txm_module_thread_shell_entry.c new file mode 100644 index 00000000..0e10bf64 --- /dev/null +++ b/ports_module/cortex-m7/iar/module_lib/src/txm_module_thread_shell_entry.c @@ -0,0 +1,176 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#ifndef TXM_MODULE +#define TXM_MODULE +#endif + +#ifndef TX_SOURCE_CODE +#define TX_SOURCE_CODE +#endif + + +/* Include necessary system files. */ + +#include "txm_module.h" +#include "tx_thread.h" + +/* Define the global module entry pointer from the start thread of the module. */ + +TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; + + +/* Define the dispatch function pointer used in the module implementation. */ + +ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3); + + +/* Define the IAR startup code that clears the uninitialized global data and sets up the + preset global variables. */ + +extern VOID __iar_data_init3(VOID); + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_thread_shell_entry Cortex-M7/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calls the specified entry function of the thread. It */ +/* also provides a place for the thread's entry function to return. */ +/* If the thread returns, this function places the thread in a */ +/* "COMPLETED" state. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to current thread */ +/* thread_info Pointer to thread entry info */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __iar_data_init3 IAR global initialization function*/ +/* thread_entry Thread's entry function */ +/* tx_thread_resume Resume the module callback thread */ +/* _txm_module_thread_system_suspend Module thread suspension routine */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) +{ + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + VOID (*entry_exit_notify)(TX_THREAD *, UINT); +#endif + + + /* Determine if this is the start thread. If so, we must prepare the module for + execution. If not, simply skip the C startup code. */ + if (thread_info -> txm_module_thread_entry_info_start_thread) + { + + /* Initialize the IAR C environment. */ + __iar_data_init3(); + + /* Save the entry info pointer, for later use. */ + _txm_module_entry_info = thread_info; + + /* Save the kernel function dispatch address. This is used to make all resident calls from + the module. */ + _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; + + /* Ensure that we have a valid pointer. */ + while (!_txm_module_kernel_call_dispatcher) + { + + /* Loop here, if an error is present getting the dispatch function pointer! + An error here typically indicates the resident portion of _tx_thread_schedule + is not supporting the trap to obtain the function pointer. */ + } + + /* Resume the module's callback thread, already created in the manager. */ + _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); + } + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has been entered! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_ENTRY); + } +#endif + + /* Call current thread's entry function. */ + (thread_info -> txm_module_thread_entry_info_entry) (thread_info -> txm_module_thread_entry_info_parameter); + + /* Suspend thread with a "completed" state. */ + + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine again. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has exited! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_EXIT); + } +#endif + + /* Call actual thread suspension routine. */ + _txm_module_thread_system_suspend(thread_ptr); + +#ifdef TX_SAFETY_CRITICAL + + /* If we ever get here, raise safety critical exception. */ + TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0); +#endif +} + diff --git a/ports_module/cortex-m7/iar/module_manager/src/tx_iar.c b/ports_module/cortex-m7/iar/module_manager/src/tx_iar.c new file mode 100644 index 00000000..dd719370 --- /dev/null +++ b/ports_module/cortex-m7/iar/module_manager/src/tx_iar.c @@ -0,0 +1,804 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** IAR Multithreaded Library Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Define IAR library for tools prior to version 8. */ + +#if (__VER__ < 8000000) + + +/* IAR version 7 and below. */ + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_mutex.h" + + +/* This implementation requires that the following macros are defined in the + tx_port.h file and is included with the following code segments: + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) __iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION __iar_dlib_perthread_access(0); +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. + + Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. +*/ + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT + +#include + + +#if _MULTI_THREAD + +TX_MUTEX __tx_iar_system_lock_mutexes[_MAX_LOCK]; +UINT __tx_iar_system_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_system_lock_no_mutexes; +UINT __tx_iar_system_lock_internal_errors; +UINT __tx_iar_system_lock_isr_caller; + + +/* Define the TLS access function for the IAR library. */ + +void _DLIB_TLS_MEMORY *__iar_dlib_perthread_access(void _DLIB_TLS_MEMORY *symbp) +{ + +char _DLIB_TLS_MEMORY *p = 0; + + /* Is there a current thread? */ + if (_tx_thread_current_ptr) + p = (char _DLIB_TLS_MEMORY *) _tx_thread_current_ptr -> tx_thread_iar_tls_pointer; + else + p = (void _DLIB_TLS_MEMORY *) __segment_begin("__DLIB_PERTHREAD"); + p += __IAR_DLIB_PERTHREAD_SYMBOL_OFFSET(symbp); + return (void _DLIB_TLS_MEMORY *) p; +} + + +/* Define mutexes for IAR library. */ + +void __iar_system_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_LOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_system_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_system_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_system_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_system_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_system_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } +} + +void __iar_system_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } +} + + +#if _DLIB_FILE_DESCRIPTOR + +TX_MUTEX __tx_iar_file_lock_mutexes[_MAX_FLOCK]; +UINT __tx_iar_file_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_file_lock_no_mutexes; +UINT __tx_iar_file_lock_internal_errors; +UINT __tx_iar_file_lock_isr_caller; + + +void __iar_file_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_FLOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_file_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_file_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_file_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_file_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_file_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} + +void __iar_file_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} +#endif /* _DLIB_FILE_DESCRIPTOR */ + +#endif /* _MULTI_THREAD */ + +#endif /* TX_ENABLE_IAR_LIBRARY_SUPPORT */ + +#else /* IAR version 8 and above. */ + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_mutex.h" + +/* This implementation requires that the following macros are defined in the + tx_port.h file and is included with the following code segments: + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 +#endif + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +void *_tx_iar_create_per_thread_tls_area(void); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); +void __iar_Initlocks(void); + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = __iar_dlib_perthread_allocate(); +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {__iar_dlib_perthread_deallocate(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#else +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + + This should be done automatically if TX_ENABLE_IAR_LIBRARY_SUPPORT is defined while building the ThreadX library and the + application. + + Finally, the project options General Options -> Library Configuration should have the "Enable thread support in library" box selected. +*/ + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT + +#include + + +void * __aeabi_read_tp(); + +void* _tx_iar_create_per_thread_tls_area(); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); + +#pragma section="__iar_tls$$DATA" + +/* Define the TLS access function for the IAR library. */ +void * __aeabi_read_tp(void) +{ + void *p = 0; + TX_THREAD *thread_ptr = _tx_thread_current_ptr; + if (thread_ptr) + { + p = thread_ptr->tx_thread_iar_tls_pointer; + } + else + { + p = __section_begin("__iar_tls$$DATA"); + } + return p; +} + +/* Define the TLS creation and destruction to use malloc/free. */ + +void* _tx_iar_create_per_thread_tls_area() +{ + UINT tls_size = __iar_tls_size(); + + /* Get memory for TLS. */ + void *p = malloc(tls_size); + + /* Initialize TLS-area and run constructors for objects in TLS */ + __iar_tls_init(p); + return p; +} + +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr) +{ + /* Destroy objects living in TLS */ + __call_thread_dtors(); + free(tls_ptr); +} + +#ifndef _MAX_LOCK +#define _MAX_LOCK 4 +#endif + +static TX_MUTEX __tx_iar_system_lock_mutexes[_MAX_LOCK]; +static UINT __tx_iar_system_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_system_lock_no_mutexes; +UINT __tx_iar_system_lock_internal_errors; +UINT __tx_iar_system_lock_isr_caller; + + +/* Define mutexes for IAR library. */ + +void __iar_system_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_LOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_system_lock_mutexes[__tx_iar_system_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_system_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_system_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_system_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR System Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_system_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_system_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_system_Mtxlock(__iar_Rmtx *m) +{ + if (*m) + { + UINT status; + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } + } +} + +void __iar_system_Mtxunlock(__iar_Rmtx *m) +{ + if (*m) + { + UINT status; + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_system_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_system_lock_isr_caller++; + } + } +} + + +#if _DLIB_FILE_DESCRIPTOR + +#include /* Added to get access to FOPEN_MAX */ +#ifndef _MAX_FLOCK +#define _MAX_FLOCK FOPEN_MAX /* Define _MAX_FLOCK as the maximum number of open files */ +#endif + + +TX_MUTEX __tx_iar_file_lock_mutexes[_MAX_FLOCK]; +UINT __tx_iar_file_lock_next_free_mutex = 0; + + +/* Define error counters, just for debug purposes. */ + +UINT __tx_iar_file_lock_no_mutexes; +UINT __tx_iar_file_lock_internal_errors; +UINT __tx_iar_file_lock_isr_caller; + + +void __iar_file_Mtxinit(__iar_Rmtx *m) +{ + +UINT i; +UINT status; +TX_MUTEX *mutex_ptr; + + + /* First, find a free mutex in the list. */ + for (i = 0; i < _MAX_FLOCK; i++) + { + + /* Setup a pointer to the start of the next free mutex. */ + mutex_ptr = &__tx_iar_file_lock_mutexes[__tx_iar_file_lock_next_free_mutex++]; + + /* Check for wrap-around on the next free mutex. */ + if (__tx_iar_file_lock_next_free_mutex >= _MAX_LOCK) + { + + /* Yes, set the free index back to 0. */ + __tx_iar_file_lock_next_free_mutex = 0; + } + + /* Is this mutex free? */ + if (mutex_ptr -> tx_mutex_id != TX_MUTEX_ID) + { + + /* Yes, this mutex is free, get out of the loop! */ + break; + } + } + + /* Determine if a free mutex was found. */ + if (i >= _MAX_LOCK) + { + + /* Error! No more free mutexes! */ + + /* Increment the no mutexes error counter. */ + __tx_iar_file_lock_no_mutexes++; + + /* Set return pointer to NULL. */ + *m = TX_NULL; + + /* Return. */ + return; + } + + /* Now create the ThreadX mutex for the IAR library. */ + status = _tx_mutex_create(mutex_ptr, "IAR File Library Lock", TX_NO_INHERIT); + + /* Determine if the creation was successful. */ + if (status == TX_SUCCESS) + { + + /* Yes, successful creation, return mutex pointer. */ + *m = (VOID *) mutex_ptr; + } + else + { + + /* Increment the internal error counter. */ + __tx_iar_file_lock_internal_errors++; + + /* Return a NULL pointer to indicate an error. */ + *m = TX_NULL; + } +} + +void __iar_file_Mtxdst(__iar_Rmtx *m) +{ + + /* Simply delete the mutex. */ + _tx_mutex_delete((TX_MUTEX *) *m); +} + +void __iar_file_Mtxlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex locks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Get the mutex. */ + status = _tx_mutex_get((TX_MUTEX *) *m, TX_WAIT_FOREVER); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} + +void __iar_file_Mtxunlock(__iar_Rmtx *m) +{ + +UINT status; + + + /* Determine the caller's context. Mutex unlocks are only available from initialization and + threads. */ + if ((_tx_thread_system_state == 0) || (_tx_thread_system_state >= TX_INITIALIZE_IN_PROGRESS)) + { + + /* Release the mutex. */ + status = _tx_mutex_put((TX_MUTEX *) *m); + + /* Check the status of the mutex release. */ + if (status) + { + + /* Internal error, increment the counter. */ + __tx_iar_file_lock_internal_errors++; + } + } + else + { + + /* Increment the ISR caller error. */ + __tx_iar_file_lock_isr_caller++; + } +} +#endif /* _DLIB_FILE_DESCRIPTOR */ + +#endif /* TX_ENABLE_IAR_LIBRARY_SUPPORT */ + +#endif /* IAR version 8 and above. */ diff --git a/ports_module/cortex-m7/iar/module_manager/src/tx_misra.s b/ports_module/cortex-m7/iar/module_manager/src/tx_misra.s new file mode 100644 index 00000000..8a13551e --- /dev/null +++ b/ports_module/cortex-m7/iar/module_manager/src/tx_misra.s @@ -0,0 +1,1074 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** ThreadX MISRA Compliance */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + #define SHT_PROGBITS 0x1 + + EXTERN __aeabi_memset + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_interrupt_disable + EXTERN _tx_thread_interrupt_restore + EXTERN _tx_thread_stack_analyze + EXTERN _tx_thread_stack_error_handler + EXTERN _tx_thread_system_state +#ifdef TX_ENABLE_EVENT_TRACE + EXTERN _tx_trace_buffer_current_ptr + EXTERN _tx_trace_buffer_end_ptr + EXTERN _tx_trace_buffer_start_ptr + EXTERN _tx_trace_event_enable_bits + EXTERN _tx_trace_full_notify_function + EXTERN _tx_trace_header_ptr +#endif + + PUBLIC _tx_misra_always_true + PUBLIC _tx_misra_block_pool_to_uchar_pointer_convert + PUBLIC _tx_misra_byte_pool_to_uchar_pointer_convert + PUBLIC _tx_misra_char_to_uchar_pointer_convert + PUBLIC _tx_misra_const_char_to_char_pointer_convert +#ifdef TX_ENABLE_EVENT_TRACE + PUBLIC _tx_misra_entry_to_uchar_pointer_convert +#endif + PUBLIC _tx_misra_indirect_void_to_uchar_pointer_convert + PUBLIC _tx_misra_memset + PUBLIC _tx_misra_message_copy +#ifdef TX_ENABLE_EVENT_TRACE + PUBLIC _tx_misra_object_to_uchar_pointer_convert +#endif + PUBLIC _tx_misra_pointer_to_ulong_convert + PUBLIC _tx_misra_status_get + PUBLIC _tx_misra_thread_stack_check +#ifdef TX_ENABLE_EVENT_TRACE + PUBLIC _tx_misra_time_stamp_get +#endif + PUBLIC _tx_misra_timer_indirect_to_void_pointer_convert + PUBLIC _tx_misra_timer_pointer_add + PUBLIC _tx_misra_timer_pointer_dif +#ifdef TX_ENABLE_EVENT_TRACE + PUBLIC _tx_misra_trace_event_insert +#endif + PUBLIC _tx_misra_uchar_pointer_add + PUBLIC _tx_misra_uchar_pointer_dif + PUBLIC _tx_misra_uchar_pointer_sub + PUBLIC _tx_misra_uchar_to_align_type_pointer_convert + PUBLIC _tx_misra_uchar_to_block_pool_pointer_convert +#ifdef TX_ENABLE_EVENT_TRACE + PUBLIC _tx_misra_uchar_to_entry_pointer_convert + PUBLIC _tx_misra_uchar_to_header_pointer_convert +#endif + PUBLIC _tx_misra_uchar_to_indirect_byte_pool_pointer_convert + PUBLIC _tx_misra_uchar_to_indirect_uchar_pointer_convert +#ifdef TX_ENABLE_EVENT_TRACE + PUBLIC _tx_misra_uchar_to_object_pointer_convert +#endif + PUBLIC _tx_misra_uchar_to_void_pointer_convert + PUBLIC _tx_misra_ulong_pointer_add + PUBLIC _tx_misra_ulong_pointer_dif + PUBLIC _tx_misra_ulong_pointer_sub + PUBLIC _tx_misra_ulong_to_pointer_convert + PUBLIC _tx_misra_ulong_to_thread_pointer_convert + PUBLIC _tx_misra_user_timer_pointer_get + PUBLIC _tx_misra_void_to_block_pool_pointer_convert + PUBLIC _tx_misra_void_to_byte_pool_pointer_convert + PUBLIC _tx_misra_void_to_event_flags_pointer_convert + PUBLIC _tx_misra_void_to_indirect_uchar_pointer_convert + PUBLIC _tx_misra_void_to_mutex_pointer_convert + PUBLIC _tx_misra_void_to_queue_pointer_convert + PUBLIC _tx_misra_void_to_semaphore_pointer_convert + PUBLIC _tx_misra_void_to_thread_pointer_convert + PUBLIC _tx_misra_void_to_uchar_pointer_convert + PUBLIC _tx_misra_void_to_ulong_pointer_convert + PUBLIC _tx_misra_ipsr_get + PUBLIC _tx_misra_control_get + PUBLIC _tx_misra_control_set +#ifdef __ARMVFP__ + PUBLIC _tx_misra_fpccr_get + PUBLIC _tx_misra_vfp_touch +#endif + PUBLIC _tx_version_id + + + SECTION `.data`:DATA:REORDER:NOROOT(2) + DATA +// 51 CHAR _tx_version_id[100] = "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX 6.0.1 MISRA C Compliant *"; +_tx_version_id: + DC8 43H, 6FH, 70H, 79H, 72H, 69H, 67H, 68H + DC8 74H, 20H, 28H, 63H, 29H, 20H, 31H, 39H + DC8 39H, 36H, 2DH, 32H, 30H, 31H, 38H, 20H + DC8 45H, 78H, 70H, 72H, 65H, 73H, 73H, 20H + DC8 4CH, 6FH, 67H, 69H, 63H, 20H, 49H, 6EH + DC8 63H, 2EH, 20H, 2AH, 20H, 54H, 68H, 72H + DC8 65H, 61H, 64H, 58H, 20H, 35H, 2EH, 38H + DC8 20H, 4DH, 49H, 53H, 52H, 41H, 20H, 43H + DC8 20H, 43H, 6FH, 6DH, 70H, 6CH, 69H, 61H + DC8 6EH, 74H, 20H, 2AH, 0 + DC8 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_memset(VOID *ptr, UINT value, UINT size); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_memset: + PUSH {R4,LR} + MOVS R4,R0 + MOVS R0,R2 + MOVS R2,R1 + MOVS R1,R0 + MOVS R0,R4 + BL __aeabi_memset + POP {R4,PC} ;; return + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UCHAR *_tx_misra_uchar_pointer_add(UCHAR *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_pointer_add: + ADD R0,R0,R1 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UCHAR *_tx_misra_uchar_pointer_sub(UCHAR *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_pointer_sub: + RSBS R1,R1,#+0 + ADD R0,R0,R1 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_uchar_pointer_dif(UCHAR *ptr1, UCHAR *ptr2); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_pointer_dif: + SUBS R0,R0,R1 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_pointer_to_ulong_convert: + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG *_tx_misra_ulong_pointer_add(ULONG *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_ulong_pointer_add: + ADD R0,R0,R1, LSL #+2 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG *_tx_misra_ulong_pointer_sub(ULONG *ptr, ULONG amount); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_ulong_pointer_sub: + MVNS R2,#+3 + MULS R1,R2,R1 + ADD R0,R0,R1 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_ulong_pointer_dif(ULONG *ptr1, ULONG *ptr2); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_ulong_pointer_dif: + SUBS R0,R0,R1 + ASRS R0,R0,#+2 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_ulong_to_pointer_convert: + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_message_copy(ULONG **source, ULONG **destination, */ +/** UINT size); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_message_copy: + PUSH {R4,R5} + LDR R3,[R0, #+0] + LDR R4,[R1, #+0] + LDR R5,[R3, #+0] + STR R5,[R4, #+0] + ADDS R4,R4,#+4 + ADDS R3,R3,#+4 + CMP R2,#+2 + BCC.N ??_tx_misra_message_copy_0 + SUBS R2,R2,#+1 + B.N ??_tx_misra_message_copy_1 +??_tx_misra_message_copy_2: + LDR R5,[R3, #+0] + STR R5,[R4, #+0] + ADDS R4,R4,#+4 + ADDS R3,R3,#+4 + SUBS R2,R2,#+1 +??_tx_misra_message_copy_1: + CMP R2,#+0 + BNE.N ??_tx_misra_message_copy_2 +??_tx_misra_message_copy_0: + STR R3,[R0, #+0] + STR R4,[R1, #+0] + POP {R4,R5} + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_timer_pointer_dif(TX_TIMER_INTERNAL **ptr1, */ +/** TX_TIMER_INTERNAL **ptr2); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_timer_pointer_dif: + SUBS R0,R0,R1 + ASRS R0,R0,#+2 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** TX_TIMER_INTERNAL **_tx_misra_timer_pointer_add(TX_TIMER_INTERNAL */ +/** **ptr1, ULONG size); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_timer_pointer_add: + ADD R0,R0,R1, LSL #+2 + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_user_timer_pointer_get(TX_TIMER_INTERNAL */ +/** *internal_timer, TX_TIMER **user_timer); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_user_timer_pointer_get: + ADDS R2,R0,#+8 + SUBS R2,R2,R0 + RSBS R2,R2,#+0 + ADD R0,R0,R2 + STR R0,[R1, #+0] + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_thread_stack_check(TX_THREAD *thread_ptr, */ +/** VOID **highest_stack); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_thread_stack_check: + PUSH {R3-R5,LR} + MOVS R4,R0 + MOVS R5,R1 + BL _tx_thread_interrupt_disable + CMP R4,#+0 + BEQ.N ??_tx_misra_thread_stack_check_0 + LDR R1,[R4, #+0] + LDR.N R2,??DataTable2 ;; 0x54485244 + CMP R1,R2 + BNE.N ??_tx_misra_thread_stack_check_0 + LDR R1,[R4, #+8] + LDR R2,[R5, #+0] + CMP R1,R2 + BCS.N ??_tx_misra_thread_stack_check_1 + LDR R1,[R4, #+8] + STR R1,[R5, #+0] +??_tx_misra_thread_stack_check_1: + LDR R1,[R4, #+12] + LDR R1,[R1, #+0] + CMP R1,#-269488145 + BNE.N ??_tx_misra_thread_stack_check_2 + LDR R1,[R4, #+16] + LDR R1,[R1, #+1] + CMP R1,#-269488145 + BNE.N ??_tx_misra_thread_stack_check_2 + LDR R1,[R5, #+0] + LDR R2,[R4, #+12] + CMP R1,R2 + BCS.N ??_tx_misra_thread_stack_check_3 +??_tx_misra_thread_stack_check_2: + BL _tx_thread_interrupt_restore + MOVS R0,R4 + BL _tx_thread_stack_error_handler + BL _tx_thread_interrupt_disable +??_tx_misra_thread_stack_check_3: + LDR R1,[R5, #+0] + LDR R1,[R1, #-4] + CMP R1,#-269488145 + BEQ.N ??_tx_misra_thread_stack_check_0 + BL _tx_thread_interrupt_restore + MOVS R0,R4 + BL _tx_thread_stack_analyze + BL _tx_thread_interrupt_disable +??_tx_misra_thread_stack_check_0: + BL _tx_thread_interrupt_restore + POP {R0,R4,R5,PC} ;; return + +#ifdef TX_ENABLE_EVENT_TRACE + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID _tx_misra_trace_event_insert(ULONG event_id, */ +/** VOID *info_field_1, ULONG info_field_2, ULONG info_field_3, */ +/** ULONG info_field_4, ULONG filter, ULONG time_stamp); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_trace_event_insert: + PUSH {R3-R7,LR} + LDR.N R4,??DataTable2_1 + LDR R4,[R4, #+0] + CMP R4,#+0 + BEQ.N ??_tx_misra_trace_event_insert_0 + LDR.N R5,??DataTable2_2 + LDR R5,[R5, #+0] + LDR R6,[SP, #+28] + TST R5,R6 + BEQ.N ??_tx_misra_trace_event_insert_0 + LDR.N R5,??DataTable2_3 + LDR R5,[R5, #+0] + LDR.N R6,??DataTable2_4 + LDR R6,[R6, #+0] + CMP R5,#+0 + BNE.N ??_tx_misra_trace_event_insert_1 + LDR R5,[R6, #+44] + LDR R7,[R6, #+60] + LSLS R7,R7,#+16 + ORRS R7,R7,#0x80000000 + ORRS R5,R7,R5 + B.N ??_tx_misra_trace_event_insert_2 +??_tx_misra_trace_event_insert_1: + CMP R5,#-252645136 + BCS.N ??_tx_misra_trace_event_insert_3 + MOVS R5,R6 + MOVS R6,#-1 + B.N ??_tx_misra_trace_event_insert_2 +??_tx_misra_trace_event_insert_3: + MOVS R6,#-252645136 + MOVS R5,#+0 +??_tx_misra_trace_event_insert_2: + STR R6,[R4, #+0] + STR R5,[R4, #+4] + STR R0,[R4, #+8] + LDR R0,[SP, #+32] + STR R0,[R4, #+12] + STR R1,[R4, #+16] + STR R2,[R4, #+20] + STR R3,[R4, #+24] + LDR R0,[SP, #+24] + STR R0,[R4, #+28] + ADDS R4,R4,#+32 + LDR.N R0,??DataTable2_5 + LDR R0,[R0, #+0] + CMP R4,R0 + BCC.N ??_tx_misra_trace_event_insert_4 + LDR.N R0,??DataTable2_6 + LDR R4,[R0, #+0] + LDR.N R0,??DataTable2_1 + STR R4,[R0, #+0] + LDR.N R0,??DataTable2_7 + LDR R0,[R0, #+0] + STR R4,[R0, #+32] + LDR.N R0,??DataTable2_8 + LDR R0,[R0, #+0] + CMP R0,#+0 + BEQ.N ??_tx_misra_trace_event_insert_0 + LDR.N R0,??DataTable2_7 + LDR R0,[R0, #+0] + LDR.N R1,??DataTable2_8 + LDR R1,[R1, #+0] + BLX R1 + B.N ??_tx_misra_trace_event_insert_0 +??_tx_misra_trace_event_insert_4: + LDR.N R0,??DataTable2_1 + STR R4,[R0, #+0] + LDR.N R0,??DataTable2_7 + LDR R0,[R0, #+0] + STR R4,[R0, #+32] +??_tx_misra_trace_event_insert_0: + POP {R0,R4-R7,PC} ;; return + + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_1: + DC32 _tx_trace_buffer_current_ptr + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_2: + DC32 _tx_trace_event_enable_bits + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_5: + DC32 _tx_trace_buffer_end_ptr + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_6: + DC32 _tx_trace_buffer_start_ptr + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_7: + DC32 _tx_trace_header_ptr + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_8: + DC32 _tx_trace_full_notify_function + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ULONG _tx_misra_time_stamp_get(VOID); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_time_stamp_get: + MOVS R0,#+0 + BX LR ;; return + +#endif + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2: + DC32 0x54485244 + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_3: + DC32 _tx_thread_system_state + + SECTION `.text`:CODE:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA +??DataTable2_4: + DC32 _tx_thread_current_ptr + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UINT _tx_misra_always_true(void); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_always_true: + MOVS R0,#+1 + BX LR ;; return + + +/******************************************************************************************/ +/******************************************************************************************/ +/** */ +/** UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr); */ +/** */ +/******************************************************************************************/ +/******************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_indirect_void_to_uchar_pointer_convert: + BX LR ;; return + + +/***************************************************************************************/ +/***************************************************************************************/ +/** */ +/** UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); */ +/** */ +/***************************************************************************************/ +/***************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_indirect_uchar_pointer_convert: + BX LR ;; return + + +/***********************************************************************************/ +/***********************************************************************************/ +/** */ +/** UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); */ +/** */ +/***********************************************************************************/ +/***********************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_block_pool_to_uchar_pointer_convert: + BX LR ;; return + + +/******************************************************************************************/ +/******************************************************************************************/ +/** */ +/** TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); */ +/** */ +/******************************************************************************************/ +/******************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_block_pool_pointer_convert: + BX LR ;; return + + +/*****************************************************************************/ +/*****************************************************************************/ +/** */ +/** UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); */ +/** */ +/*****************************************************************************/ +/*****************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_uchar_pointer_convert: + BX LR ;; return + + +/************************************************************************************/ +/************************************************************************************/ +/** */ +/** TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); */ +/** */ +/************************************************************************************/ +/************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_block_pool_pointer_convert: + BX LR ;; return + + +/**************************************************************************************/ +/**************************************************************************************/ +/** */ +/** UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); */ +/** */ +/**************************************************************************************/ +/**************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_indirect_uchar_pointer_convert: + BX LR ;; return + + +/*****************************************************************************************/ +/*****************************************************************************************/ +/** */ +/** TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); */ +/** */ +/*****************************************************************************************/ +/*****************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_byte_pool_pointer_convert: + BX LR ;; return + + +/***************************************************************************************/ +/***************************************************************************************/ +/** */ +/** UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); */ +/** */ +/***************************************************************************************/ +/***************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_byte_pool_to_uchar_pointer_convert: + BX LR ;; return + + +/*****************************************************************************************/ +/*****************************************************************************************/ +/** */ +/** ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); */ +/** */ +/*****************************************************************************************/ +/*****************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_align_type_pointer_convert: + BX LR ;; return + + +/****************************************************************************************************/ +/****************************************************************************************************/ +/** */ +/** TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); */ +/** */ +/****************************************************************************************************/ +/****************************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_indirect_byte_pool_pointer_convert: + BX LR ;; return + + +/**************************************************************************************************/ +/**************************************************************************************************/ +/** */ +/** TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); */ +/** */ +/**************************************************************************************************/ +/**************************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_event_flags_pointer_convert: + BX LR ;; return + + +/*****************************************************************************/ +/*****************************************************************************/ +/** */ +/** ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); */ +/** */ +/*****************************************************************************/ +/*****************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_ulong_pointer_convert: + BX LR ;; return + + +/********************************************************************************/ +/********************************************************************************/ +/** */ +/** TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); */ +/** */ +/********************************************************************************/ +/********************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_mutex_pointer_convert: + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** UINT _tx_misra_status_get(UINT status); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_status_get: + MOVS R0,#+0 + BX LR ;; return + + +/********************************************************************************/ +/********************************************************************************/ +/** */ +/** TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); */ +/** */ +/********************************************************************************/ +/********************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_queue_pointer_convert: + BX LR ;; return + + +/****************************************************************************************/ +/****************************************************************************************/ +/** */ +/** TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); */ +/** */ +/****************************************************************************************/ +/****************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_semaphore_pointer_convert: + BX LR ;; return + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_void_pointer_convert: + BX LR ;; return + + +/*********************************************************************************/ +/*********************************************************************************/ +/** */ +/** TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); */ +/** */ +/*********************************************************************************/ +/*********************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_ulong_to_thread_pointer_convert: + BX LR ;; return + + +/***************************************************************************************************/ +/***************************************************************************************************/ +/** */ +/** VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); */ +/** */ +/***************************************************************************************************/ +/***************************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_timer_indirect_to_void_pointer_convert: + BX LR ;; return + + +/***************************************************************************************/ +/***************************************************************************************/ +/** */ +/** CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); */ +/** */ +/***************************************************************************************/ +/***************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_const_char_to_char_pointer_convert: + BX LR ;; return + + +/**********************************************************************************/ +/**********************************************************************************/ +/** */ +/** TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer); */ +/** */ +/**********************************************************************************/ +/**********************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_void_to_thread_pointer_convert: + BX LR ;; return + + +#ifdef TX_ENABLE_EVENT_TRACE + +/************************************************************************************************/ +/************************************************************************************************/ +/** */ +/** UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); */ +/** */ +/************************************************************************************************/ +/************************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_object_to_uchar_pointer_convert: + BX LR ;; return + + +/************************************************************************************************/ +/************************************************************************************************/ +/** */ +/** TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); */ +/** */ +/************************************************************************************************/ +/************************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_object_pointer_convert: + BX LR ;; return + + +/******************************************************************************************/ +/******************************************************************************************/ +/** */ +/** TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); */ +/** */ +/******************************************************************************************/ +/******************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_header_pointer_convert: + BX LR ;; return + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_uchar_to_entry_pointer_convert: + BX LR ;; return + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_entry_to_uchar_pointer_convert: + BX LR ;; return +#endif + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_char_to_uchar_pointer_convert: + BX LR ;; return + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** ULONG _tx_misra_ipsr_get(void); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_ipsr_get: + MRS R0, IPSR + BX LR ;; return + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** ULONG _tx_misra_control_get(void); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_control_get: + MRS R0, CONTROL + BX LR ;; return + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** void _tx_misra_control_set(ULONG value); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_control_set: + MSR CONTROL, R0 + BX LR ;; return + + +#ifdef __ARMVFP__ + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** ULONG _tx_misra_fpccr_get(void); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(2) + THUMB +_tx_misra_fpccr_get: + LDR r0, =0xE000EF34 ; Build FPCCR address + LDR r0, [r0] ; Load FPCCR value + BX LR ;; return + + +/***********************************************************************************************/ +/***********************************************************************************************/ +/** */ +/** void _tx_misra_vfp_touch(void); */ +/** */ +/***********************************************************************************************/ +/***********************************************************************************************/ + + SECTION `.text`:CODE:NOROOT(1) + THUMB +_tx_misra_vfp_touch: + vmov.f32 s0, s0 + BX LR ;; return + +#endif + + + SECTION `.iar_vfe_header`:DATA:NOALLOC:NOROOT(2) + SECTION_TYPE SHT_PROGBITS, 0 + DATA + DC32 0 + + END diff --git a/ports_module/cortex-m7/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex-m7/iar/module_manager/src/tx_thread_context_restore.s new file mode 100644 index 00000000..f671f2d4 --- /dev/null +++ b/ports_module/cortex-m7/iar/module_manager/src/tx_thread_context_restore.s @@ -0,0 +1,105 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_schedule + EXTERN _tx_thread_preempt_disable + EXTERN _tx_execution_isr_exit +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-M7/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + PUBLIC _tx_thread_context_restore +_tx_thread_context_restore: + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + PUSH {r0,lr} ; Save ISR lr + BL _tx_execution_isr_exit ; Call the ISR exit function + POP {r0,lr} ; Restore ISR lr +#endif +; + POP {lr} + BX lr +; +;} + END + diff --git a/ports_module/cortex-m7/iar/module_manager/src/tx_thread_context_save.s b/ports_module/cortex-m7/iar/module_manager/src/tx_thread_context_save.s new file mode 100644 index 00000000..1febcc18 --- /dev/null +++ b/ports_module/cortex-m7/iar/module_manager/src/tx_thread_context_save.s @@ -0,0 +1,97 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + EXTERN _tx_thread_system_state + EXTERN _tx_thread_current_ptr + EXTERN _tx_execution_isr_enter +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-M7/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + PUBLIC _tx_thread_context_save +_tx_thread_context_save: +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is starting. */ +; + PUSH {r0, lr} ; Save return address + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {r0, lr} ; Recover return address +#endif +; +; /* Context is already saved - just return! */ +; + BX lr +;} + END diff --git a/ports_module/cortex-m7/iar/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex-m7/iar/module_manager/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..2e95e0f7 --- /dev/null +++ b/ports_module/cortex-m7/iar/module_manager/src/tx_thread_interrupt_control.s @@ -0,0 +1,86 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-M7/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + PUBLIC _tx_thread_interrupt_control +_tx_thread_interrupt_control: +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r1, PRIMASK + MSR PRIMASK, r0 + MOV r0, r1 + BX lr +; +;} + END + diff --git a/ports_module/cortex-m7/iar/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex-m7/iar/module_manager/src/tx_thread_interrupt_disable.s new file mode 100644 index 00000000..e435b0b8 --- /dev/null +++ b/ports_module/cortex-m7/iar/module_manager/src/tx_thread_interrupt_disable.s @@ -0,0 +1,84 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-M7/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts and returning */ +;/* the previous interrupt lockout posture. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(UINT new_posture) +;{ + PUBLIC _tx_thread_interrupt_disable +_tx_thread_interrupt_disable: +; +; /* Return current interrupt lockout posture. */ +; + MRS r0, PRIMASK + CPSID i + BX lr +; +;} + END diff --git a/ports_module/cortex-m7/iar/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex-m7/iar/module_manager/src/tx_thread_interrupt_restore.s new file mode 100644 index 00000000..cfdb140d --- /dev/null +++ b/ports_module/cortex-m7/iar/module_manager/src/tx_thread_interrupt_restore.s @@ -0,0 +1,83 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-M7/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for restoring the previous */ +;/* interrupt lockout posture. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* previous_posture Previous interrupt posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_interrupt_restore(UINT new_posture) +;{ + PUBLIC _tx_thread_interrupt_restore +_tx_thread_interrupt_restore: +; +; /* Restore previous interrupt lockout posture. */ +; + MSR PRIMASK, r0 + BX lr +; +;} + END diff --git a/ports_module/cortex-m7/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex-m7/iar/module_manager/src/tx_thread_schedule.s new file mode 100644 index 00000000..9f06add8 --- /dev/null +++ b/ports_module/cortex-m7/iar/module_manager/src/tx_thread_schedule.s @@ -0,0 +1,581 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_execution_thread_enter + EXTERN _tx_execution_thread_exit + EXTERN _tx_thread_preempt_disable + EXTERN _txm_module_manager_memory_fault_handler + EXTERN _txm_module_manager_memory_fault_info +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule Cortex-M7/MPU/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + PUBLIC _tx_thread_schedule +_tx_thread_schedule: +; +; /* This function should only ever be called on Cortex-M +; from the first schedule request. Subsequent scheduling occurs +; from the PendSV handling routines below. */ +; +; /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ +; + MOV r0, #0 ; Build value for TX_FALSE + LDR r2, =_tx_thread_preempt_disable ; Build address of preempt disable flag + STR r0, [r2, #0] ; Clear preempt disable flag +; +; /* Clear CONTROL.FPCA bit so FPU registers aren't unnecessarily stacked. */ +; +#ifdef __ARMVFP__ + MRS r0, CONTROL ; Pickup current CONTROL register + BIC r0, r0, #4 ; Clear the FPCA bit + MSR CONTROL, r0 ; Setup new CONTROL register +#endif +; +; /* Enable memory fault registers. */ +; + LDR r0, =0xE000ED24 ; Build SHCSR address + LDR r1, =0x70000 ; Enable Usage, Bus, and MemManage faults + STR r1, [r0] ; +; +; /* Enable interrupts */ +; + CPSIE i +; +; /* Enter the scheduler for the first time. */ +; + MOV r0, #0x10000000 ; Load PENDSVSET bit + MOV r1, #0xE000E000 ; Load NVIC base + STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR + NOP ; + NOP ; + NOP ; + NOP ; +__wait_loop: + B __wait_loop +; +; /* We should never get here - ever! */ +; + BKPT 0xEF ; Setup error conditions + BX lr ; +;} +; + +; +; /* Memory Exception Handler. */ +; + PUBLIC MemManage_Handler +MemManage_Handler: +;{ + CPSID i ; Disable interrupts +; +; /* Now pickup and store all the fault related information. */ +; + LDR r12,=_txm_module_manager_memory_fault_info ; Pickup fault info struct + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup the current thread pointer + STR r1, [r12, #0] ; Save current thread pointer in fault info structure + LDR r0, =0xE000ED24 ; Build SHCSR address + LDR r1, [r0] ; Pickup SHCSR + STR r1, [r12, #8] ; Save SHCSR + LDR r0, =0xE000ED28 ; Build MMFSR address + LDR r1, [r0] ; Pickup MMFSR (and other fault status too!) + STR r1, [r12, #12] ; Save MMFSR + LDR r0, =0xE000ED34 ; Build MMFAR address + LDR r1, [r0] ; Pickup MMFAR + STR r1, [r12, #16] ; Save MMFAR + MRS r0, CONTROL ; Pickup current CONTROL register + STR r0, [r12, #20] ; Save CONTROL + MRS r1, PSP ; Pickup thread stack pointer + STR r1, [r12, #24] ; Save thread stack pointer + LDR r0, [r1] ; Pickup saved r0 + STR r0, [r12, #28] ; Save r0 + LDR r0, [r1, #4] ; Pickup saved r1 + STR r0, [r12, #32] ; Save r1 + STR r2, [r12, #36] ; Save r2 + STR r3, [r12, #40] ; Save r3 + STR r4, [r12, #44] ; Save r4 + STR r5, [r12, #48] ; Save r5 + STR r6, [r12, #52] ; Save r6 + STR r7, [r12, #56] ; Save r7 + STR r8, [r12, #60] ; Save r8 + STR r9, [r12, #64] ; Save r9 + STR r10,[r12, #68] ; Save r10 + STR r11,[r12, #72] ; Save r11 + LDR r0, [r1, #16] ; Pickup saved r12 + STR r0, [r12, #76] ; Save r12 + LDR r0, [r1, #20] ; Pickup saved lr + STR r0, [r12, #80] ; Save lr + LDR r0, [r1, #24] ; Pickup instruction address at point of fault + STR r0, [r12, #4] ; Save point of fault + LDR r0, [r1, #28] ; Pickup xPSR + STR r0, [r12, #84] ; Save xPSR + + MRS r0, CONTROL ; Pickup current CONTROL register + BIC r0, r0, #1 ; Clear the UNPRIV bit + MSR CONTROL, r0 ; Setup new CONTROL register + + LDR r0, =0xE000ED28 ; Build the Memory Management Fault Status Register (MMFSR) + LDRB r1, [r0] ; Pickup the MMFSR, with the following bit definitions: + ; Bit 0 = 1 -> Instruction address violation + ; Bit 1 = 1 -> Load/store address violation + ; Bit 7 = 1 -> MMFAR is valid + STRB r1, [r0] ; Clear the MMFSR + +#ifdef __ARMVFP__ + LDR r0, =0xE000EF34 ; Cleanup FPU context: Load FPCCR address + LDR r1, [r0] ; Load FPCCR + BIC r1, r1, #1 ; Clear the lazy preservation active bit + STR r1, [r0] ; Store the value +#endif + + BL _txm_module_manager_memory_fault_handler ; Call memory manager fault handler + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + CPSID i ; Disable interrupts + BL _tx_execution_thread_exit ; Call the thread exit function + CPSIE i ; Enable interrupts +#endif + + MOV r1, #0 ; Build NULL value + LDR r0, =_tx_thread_current_ptr ; Pickup address of current thread pointer + STR r1, [r0] ; Clear current thread pointer + + ; Return from MemManage_Handler exception + LDR r0, =0xE000ED04 ; Load ICSR + LDR r1, =0x10000000 ; Set PENDSVSET bit + STR r1, [r0] ; Store ICSR + DSB ; Wait for memory access to complete + CPSIE i ; Enable interrupts + MOV lr, #0xFFFFFFFD ; Load exception return code + BX lr ; Return from exception +;} + +; +; /* Generic context PendSV handler. */ +; + PUBLIC PendSV_Handler + PUBLIC __tx_PendSVHandler +PendSV_Handler: +__tx_PendSVHandler: +; +; /* Get current thread value and new thread pointer. */ +; +__tx_ts_handler: + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + CPSID i ; Disable interrupts + PUSH {r0, lr} ; Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit ; Call the thread exit function + POP {r0, lr} ; Recover LR + CPSIE i ; Enable interrupts +#endif + MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address + MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address + MOV r3, #0 ; Build NULL value + LDR r1, [r0] ; Pickup current thread pointer +; +; /* Determine if there is a current thread to finish preserving. */ +; + CBZ r1, __tx_ts_new ; If NULL, skip preservation +; +; /* Recover PSP and preserve current thread context. */ +; + STR r3, [r0] ; Set _tx_thread_current_ptr to NULL + MRS r12, PSP ; Pickup PSP pointer (thread's stack pointer) + STMDB r12!, {r4-r11} ; Save its remaining registers +#ifdef __ARMVFP__ + TST LR, #0x10 ; Determine if the VFP extended frame is present + BNE _skip_vfp_save + VSTMDB r12!,{s16-s31} ; Yes, save additional VFP registers +_skip_vfp_save: +#endif + MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable + STMDB r12!, {LR} ; Save LR on the stack +; +; /* Determine if time-slice is active. If it isn't, skip time handling processing. */ +; + LDR r5, [r4] ; Pickup current time-slice + STR r12, [r1, #8] ; Save the thread stack pointer + CBZ r5, __tx_ts_new ; If not active, skip processing +; +; /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ +; + STR r5, [r1, #24] ; Save current time-slice +; +; /* Clear the global time-slice. */ +; + STR r3, [r4] ; Clear time-slice +; +; +; /* Executing thread is now completely preserved!!! */ +; +__tx_ts_new: +; +; /* Now we are looking for a new thread to execute! */ +; + CPSID i ; Disable interrupts + LDR r1, [r2] ; Is there another thread ready to execute? + CBZ r1, __tx_ts_wait ; No, skip to the wait processing +; +; /* Yes, another thread is ready for else, make the current thread the new thread. */ +; + STR r1, [r0] ; Setup the current thread pointer to the new thread + CPSIE i ; Enable interrupts +; +; /* Increment the thread run count. */ +; +__tx_ts_restore: + LDR r7, [r1, #4] ; Pickup the current thread run count + MOV32 r4, _tx_timer_time_slice ; Build address of time-slice variable + LDR r5, [r1, #24] ; Pickup thread's current time-slice + ADD r7, r7, #1 ; Increment the thread run count + STR r7, [r1, #4] ; Store the new run count +; +; /* Setup global time-slice with thread's current time-slice. */ +; + STR r5, [r4] ; Setup global time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + PUSH {r0, r1} ; Save r0 and r1 + BL _tx_execution_thread_enter ; Call the thread execution enter function + POP {r0, r1} ; Recover r0 and r1 +#endif +; +; /* Restore the thread context and PSP. */ +; + LDR r12, [r1, #8] ; Pickup thread's stack pointer + + MRS r5, CONTROL ; Pickup current CONTROL register + LDR r4, [r1, #0x98] ; Pickup current user mode flag + BIC r5, r5, #1 ; Clear the UNPRIV bit + ORR r4, r4, r5 ; Build new CONTROL register + MSR CONTROL, r4 ; Setup new CONTROL register + + LDR r0, =0xE000ED94 ; Build MPU control reg address + MOV r3, #0 ; Build disable value + STR r3, [r0] ; Disable MPU + LDR r0, [r1, #0x90] ; Pickup the module instance pointer + CBZ r0, skip_mpu_setup ; Is this thread owned by a module? No, skip MPU setup + LDR r1, [r0, #0x64] ; Pickup MPU register[0] + CBZ r1, skip_mpu_setup ; Is protection required for this module? No, skip MPU setup + LDR r1, =0xE000ED9C ; Build address of MPU base register + + ; Use alias registers to quickly load MPU + ADD r0, r0, #100 ; Build address of MPU register start in thread control block + LDM r0!,{r2-r9} ; Load MPU regions 0-3 + STM r1,{r2-r9} ; Store MPU regions 0-3 + LDM r0!,{r2-r9} ; Load MPU regions 4-7 + STM r1,{r2-r9} ; Store MPU regions 4-7 + LDM r0!,{r2-r9} ; Load MPU regions 8-11 + STM r1,{r2-r9} ; Store MPU regions 8-11 + LDM r0!,{r2-r9} ; Load MPU regions 12-15 + STM r1,{r2-r9} ; Store MPU regions 12-15 + LDR r0, =0xE000ED94 ; Build MPU control reg address + MOV r1, #5 ; Build enable value with background region enabled + STR r1, [r0] ; Enable MPU +skip_mpu_setup: + LDMIA r12!, {LR} ; Pickup LR +#ifdef __ARMVFP__ + TST LR, #0x10 ; Determine if the VFP extended frame is present + BNE _skip_vfp_restore ; If not, skip VFP restore + VLDMIA r12!, {s16-s31} ; Yes, restore additional VFP registers +_skip_vfp_restore: +#endif + LDMIA r12!, {r4-r11} ; Recover thread's registers + MSR PSP, r12 ; Setup the thread's stack pointer +; +; /* Return to thread. */ +; + BX lr ; Return to thread! +; +; /* The following is the idle wait processing... in this case, no threads are ready for execution and the +; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts +; are disabled to allow use of WFI for waiting for a thread to arrive. */ +; +__tx_ts_wait: + CPSID i ; Disable interrupts + LDR r1, [r2] ; Pickup the next thread to execute pointer + STR r1, [r0] ; Store it in the current pointer + CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready! +#ifdef TX_ENABLE_WFI + DSB ; Ensure no outstanding memory transactions + WFI ; Wait for interrupt + ISB ; Ensure pipeline is flushed +#endif + CPSIE i ; Enable interrupts + B __tx_ts_wait ; Loop to continue waiting +; +; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are +; already in the handler! */ +; +__tx_ts_ready: + MOV r7, #0x08000000 ; Build clear PendSV value + MOV r8, #0xE000E000 ; Build base NVIC address + STR r7, [r8, #0xD04] ; Clear any PendSV +; +; /* Re-enable interrupts and restore new thread. */ +; + CPSIE i ; Enable interrupts + B __tx_ts_restore ; Restore the thread +;} + +; +; /* SVC Handler. */ +; + PUBLIC SVC_Handler + PUBLIC __tx_SVCallHandler +SVC_Handler: +__tx_SVCallHandler: +;{ + MRS r0, PSP ; Pickup the PSP stack + LDR r1, [r0, #24] ; Pickup the point of interrupt + LDRB r2, [r1, #-2] ; Pickup the SVC parameter + ; + ; Determine which SVC trap we are processing + ; + CMP r2, #1 ; Is it the entry into ThreadX? + BNE _tx_thread_user_return ; No, return to user mode + ; + ; At this point we have an SVC 1, which means we are entering the kernel from a module thread with user mode selected + ; + LDR r2, =_txm_module_priv-1 ; Subtract 1 because of THUMB mode. + CMP r1, r2 ; Did we come from user_mode_entry? + IT NE ; If no (not equal), then... + BXNE lr ; return from where we came. + + LDR r3, [r0, #20] ; This is the saved LR + LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r2, [r1] ; Pickup current thread pointer + MOV r1, #0 ; Build clear value + STR r1, [r2, #0x98] ; Clear the current user mode selection for thread + STR r3, [r2, #0xA0] ; Save the original LR in thread control block + + ; If there is memory protection, use kernel stack + LDR r0, [r2, #0x90] ; Load the module instance ptr + LDR r0, [r0, #0x0C] ; Load the module property flags + TST r0, #2 ; Check if memory protected + BEQ _tx_skip_kernel_stack_enter + + ; Switch to the module thread's kernel stack + LDR r0, [r2, #0xA8] ; Load the module kernel stack end +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r1, [r2, #0xA4] ; Load the module kernel stack start + LDR r3, [r2, #0xAC] ; Load the module kernel stack size + STR r1, [r2, #12] ; Set stack start + STR r0, [r2, #16] ; Set stack end + STR r3, [r2, #20] ; Set stack size +#endif + + MRS r3, PSP ; Pickup thread stack pointer + STR r3, [r2, #0xB0] ; Save thread stack pointer + + ; Build kernel stack by copying thread stack two registers at a time + ADD r3, r3, #32 ; start at bottom of hardware stack + LDMDB r3!,{r1-r2} ; + STMDB r0!,{r1-r2} ; + LDMDB r3!,{r1-r2} ; + STMDB r0!,{r1-r2} ; + LDMDB r3!,{r1-r2} ; + STMDB r0!,{r1-r2} ; + LDMDB r3!,{r1-r2} ; + STMDB r0!,{r1-r2} ; + + MSR PSP, r0 ; Set kernel stack pointer + +_tx_skip_kernel_stack_enter: + MRS r0, CONTROL ; Pickup current CONTROL register + BIC r0, r0, #1 ; Clear the UNPRIV bit + MSR CONTROL, r0 ; Setup new CONTROL register + BX lr ; Return to thread + +_tx_thread_user_return: + + LDR r2, =_txm_module_user_mode_exit-1 ; Subtract 1 because of THUMB mode. + CMP r1, r2 ; Did we come from user_mode_exit? + IT NE ; If no (not equal), then... + BXNE lr ; return from where we came + + LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r2, [r1] ; Pickup current thread pointer + LDR r1, [r2, #0x9C] ; Pick up user mode + STR r1, [r2, #0x98] ; Set the current user mode selection for thread + + ; If there is memory protection, use kernel stack + LDR r0, [r2, #0x90] ; Load the module instance ptr + LDR r0, [r0, #0x0C] ; Load the module property flags + TST r0, #2 ; Check if memory protected + BEQ _tx_skip_kernel_stack_exit + +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + LDR r0, [r2, #0xB4] ; Load the module thread stack start + LDR r1, [r2, #0xB8] ; Load the module thread stack end + LDR r3, [r2, #0xBC] ; Load the module thread stack size + STR r0, [r2, #12] ; Set stack start + STR r1, [r2, #16] ; Set stack end + STR r3, [r2, #20] ; Set stack size +#endif + LDR r0, [r2, #0xB0] ; Load the module thread stack pointer + MRS r3, PSP ; Pickup kernel stack pointer + + ; Copy kernel hardware stack to module thread stack. + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + LDM r3!,{r1-r2} + STM r0!,{r1-r2} + SUB r0, r0, #32 ; Subtract 32 to get back to top of stack + MSR PSP, r0 ; Set thread stack pointer + + LDR r1, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r2, [r1] ; Pickup current thread pointer + LDR r1, [r2, #0x9C] ; Pick up user mode + +_tx_skip_kernel_stack_exit: + MRS r0, CONTROL ; Pickup current CONTROL register + ORR r0, r0, r1 ; OR in the user mode bit + MSR CONTROL, r0 ; Setup new CONTROL register + BX lr ; Return to thread +;} + +; +; /* Kernel entry function from user mode. */ +; + EXTERN _txm_module_manager_kernel_dispatch +; + SECTION `.text`:CODE:NOROOT(5) + THUMB + ALIGNROM 5 +;VOID _txm_module_manager_user_mode_entry(VOID) +;{ + PUBLIC _txm_module_manager_user_mode_entry +_txm_module_manager_user_mode_entry: + SVC 1 ; Enter kernel +_txm_module_priv: + ; At this point, we are out of user mode. The original LR has been saved in the + ; thread control block. Simply call the kernel dispatch function. + BL _txm_module_manager_kernel_dispatch + + ; Pickup the original LR value while still in privileged mode + LDR r2, =_tx_thread_current_ptr ; Build current thread pointer address + LDR r3, [r2] ; Pickup current thread pointer + LDR lr, [r3, #0xA0] ; Pickup saved LR from original call + + SVC 2 ; Exit kernel and return to user mode +_txm_module_user_mode_exit: + BX lr ; Return to the caller + NOP + NOP + NOP + NOP +;} + +; +#ifdef __ARMVFP__ + + PUBLIC tx_thread_fpu_enable +tx_thread_fpu_enable: +; +; /* Automatic VPF logic is supported, this function is present only for +; backward compatibility purposes and therefore simply returns. */ +; + BX LR ; Return to caller + + PUBLIC tx_thread_fpu_disable +tx_thread_fpu_disable: +; +; /* Automatic VPF logic is supported, this function is present only for +; backward compatibility purposes and therefore simply returns. */ +; + BX LR ; Return to caller + +#endif + + END diff --git a/ports_module/cortex-m7/iar/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex-m7/iar/module_manager/src/tx_thread_stack_build.s new file mode 100644 index 00000000..36518e5e --- /dev/null +++ b/ports_module/cortex-m7/iar/module_manager/src/tx_thread_stack_build.s @@ -0,0 +1,144 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-M7/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + PUBLIC _tx_thread_stack_build +_tx_thread_stack_build: +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-M7 should look like the following after it is built: +; +; Stack Top: +; LR Interrupted LR (LR at time of PENDSV) +; r4 Initial value for r4 +; r5 Initial value for r5 +; r6 Initial value for r6 +; r7 Initial value for r7 +; r8 Initial value for r8 +; r9 Initial value for r9 +; r10 Initial value for r10 +; r11 Initial value for r11 +; r0 Initial value for r0 (Hardware stack starts here!!) +; r1 Initial value for r1 +; r2 Initial value for r2 +; r3 Initial value for r3 +; r12 Initial value for r12 +; lr Initial value for lr +; pc Initial value for pc +; xPSR Initial value for xPSR +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #0x7 ; Align frame for 8-byte alignment + SUB r2, r2, #68 ; Subtract frame size + LDR r3, =0xFFFFFFFD ; Build initial LR value + STR r3, [r2, #0] ; Save on the stack +; +; /* Actually build the stack frame. */ +; + MOV r3, #0 ; Build initial register value + STR r3, [r2, #4] ; Store initial r4 + STR r3, [r2, #8] ; Store initial r5 + STR r3, [r2, #12] ; Store initial r6 + STR r3, [r2, #16] ; Store initial r7 + STR r3, [r2, #20] ; Store initial r8 + STR r3, [r2, #24] ; Store initial r9 + STR r3, [r2, #28] ; Store initial r10 + STR r3, [r2, #32] ; Store initial r11 +; +; /* Hardware stack follows. / +; + STR r3, [r2, #36] ; Store initial r0 + STR r3, [r2, #40] ; Store initial r1 + STR r3, [r2, #44] ; Store initial r2 + STR r3, [r2, #48] ; Store initial r3 + STR r3, [r2, #52] ; Store initial r12 + MOV r3, #0xFFFFFFFF ; Poison EXC_RETURN value + STR r3, [r2, #56] ; Store initial lr + STR r1, [r2, #60] ; Store initial pc + MOV r3, #0x01000000 ; Only T-bit need be set + STR r3, [r2, #64] ; Store initial xPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block + BX lr ; Return to caller +;} + END + diff --git a/ports_module/cortex-m7/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex-m7/iar/module_manager/src/tx_thread_system_return.s new file mode 100644 index 00000000..126a9c78 --- /dev/null +++ b/ports_module/cortex-m7/iar/module_manager/src/tx_thread_system_return.s @@ -0,0 +1,97 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-M7/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + PUBLIC _tx_thread_system_return +_tx_thread_system_return??rA: +_tx_thread_system_return: +; +; /* Return to real scheduler via PendSV. Note that this routine is often +; replaced with in-line assembly in tx_port.h to improved performance. */ +; + MOV r0, #0x10000000 ; Load PENDSVSET bit + MOV r1, #0xE000E000 ; Load NVIC base + STR r0, [r1, #0xD04] ; Set PENDSVBIT in ICSR + MRS r0, IPSR ; Pickup IPSR + CMP r0, #0 ; Is it a thread returning? + BNE _isr_context ; If ISR, skip interrupt enable + MRS r1, PRIMASK ; Thread context returning, pickup PRIMASK + CPSIE i ; Enable interrupts + MSR PRIMASK, r1 ; Restore original interrupt posture +_isr_context: + BX lr ; Return to caller +;} + END diff --git a/ports_module/cortex-m7/iar/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex-m7/iar/module_manager/src/tx_timer_interrupt.s new file mode 100644 index 00000000..c900f267 --- /dev/null +++ b/ports_module/cortex-m7/iar/module_manager/src/tx_timer_interrupt.s @@ -0,0 +1,268 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_timer.h" +;#include "tx_thread.h" +; +; +;Define Assembly language external references... +; + EXTERN _tx_timer_time_slice + EXTERN _tx_timer_system_clock + EXTERN _tx_timer_current_ptr + EXTERN _tx_timer_list_start + EXTERN _tx_timer_list_end + EXTERN _tx_timer_expired_time_slice + EXTERN _tx_timer_expired + EXTERN _tx_thread_time_slice + EXTERN _tx_timer_expiration_process + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_thread_preempt_disable +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-M7/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* the expiration functions are called. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + PUBLIC _tx_timer_interrupt +_tx_timer_interrupt: +; +; /* Upon entry to this routine, it is assumed that the compiler scratch registers are available +; for use. */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + MOV32 r1, _tx_timer_system_clock ; Pickup address of system clock + LDR r0, [r1, #0] ; Pickup system clock + ADD r0, r0, #1 ; Increment system clock + STR r0, [r1, #0] ; Store new system clock +; +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice + LDR r2, [r3, #0] ; Pickup time-slice + CBZ r2, __tx_timer_no_time_slice ; Is it non-active? + ; Yes, skip time-slice processing +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; + SUB r2, r2, #1 ; Decrement the time-slice + STR r2, [r3, #0] ; Store new time-slice value +; +; /* Check for expiration. */ +; if (__tx_timer_time_slice == 0) +; + CBNZ r2, __tx_timer_no_time_slice ; Has it expired? +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup address of expired flag + MOV r0, #1 ; Build expired value + STR r0, [r3, #0] ; Set time-slice expiration flag +; +; } +; +__tx_timer_no_time_slice: +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + MOV32 r1, _tx_timer_current_ptr ; Pickup current timer pointer address + LDR r0, [r1, #0] ; Pickup current timer + LDR r2, [r0, #0] ; Pickup timer list entry + CBZ r2, __tx_timer_no_timer ; Is there anything in the list? + ; No, just increment the timer +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + MOV32 r3, _tx_timer_expired ; Pickup expiration flag address + MOV r2, #1 ; Build expired value + STR r2, [r3, #0] ; Set expired flag + B __tx_timer_done ; Finished timer processing +; +; } +; else +; { +__tx_timer_no_timer: +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ADD r0, r0, #4 ; Move to next timer +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + MOV32 r3, _tx_timer_list_end ; Pickup addr of timer list end + LDR r2, [r3, #0] ; Pickup list end + CMP r0, r2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, skip wrap-around logic +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + MOV32 r3, _tx_timer_list_start ; Pickup addr of timer list start + LDR r0, [r3, #0] ; Set current pointer to list start +; +__tx_timer_skip_wrap: +; + STR r0, [r1, #0] ; Store new current timer pointer +; } +; +__tx_timer_done: +; +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of expired flag + LDR r2, [r3, #0] ; Pickup time-slice expired flag + CBNZ r2, __tx_something_expired ; Did a time-slice expire? + ; If non-zero, time-slice expired + MOV32 r1, _tx_timer_expired ; Pickup addr of other expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CBZ r0, __tx_timer_nothing_expired ; Did a timer expire? + ; No, nothing expired +; +__tx_something_expired: +; +; + STMDB sp!, {r0, lr} ; Save the lr register on the stack + ; and save r0 just to keep 8-byte alignment +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + MOV32 r1, _tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CBZ r0, __tx_timer_dont_activate ; Check for timer expiration + ; If not set, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BL _tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate: +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r2, [r3, #0] ; Pickup the actual flag + CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set + ; No, skip time-slice processing +; +; /* Time slice interrupted thread. */ +; _tx_thread_time_slice(); + + BL _tx_thread_time_slice ; Call time-slice processing + MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag + LDR r1, [r0] ; Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice ; Yes, skip the PendSV logic + MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup the current thread pointer + MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address + LDR r3, [r2] ; Pickup the execute thread pointer + MOV32 r0, 0xE000ED04 ; Build address of control register + MOV32 r2, 0x10000000 ; Build value for PendSV bit + CMP r1, r3 ; Are they the same? + BEQ __tx_timer_skip_time_slice ; If the same, there was no time-slice performed + STR r2, [r0] ; Not the same, issue the PendSV for preemption +__tx_timer_skip_time_slice: +; +; } +; +__tx_timer_not_ts_expiration: +; + LDMIA sp!, {r0, lr} ; Recover lr register (r0 is just there for + ; the 8-byte stack alignment +; +; } +; +__tx_timer_nothing_expired: + + DSB ; Complete all memory access + BX lr ; Return to caller +; +;} + END + diff --git a/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_alignment_adjust.c new file mode 100644 index 00000000..e962906f --- /dev/null +++ b/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -0,0 +1,188 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_power_of_two_block_size Cortex-M7/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calculates a power of two size at or immediately above*/ +/* the input size and returns it to the caller. */ +/* */ +/* INPUT */ +/* */ +/* size Block size */ +/* */ +/* OUTPUT */ +/* */ +/* calculated size Rounded up to power of two */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_alignment_adjust Adjust alignment for Cortex-M */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_power_of_two_block_size(ULONG size) +{ + /* Check for 0 size. */ + if(size == 0) + return 0; + + /* Minimum MPU block size is 32. */ + if(size <= 32) + return 32; + + /* Bit twiddling trick to round to next high power of 2 + (if original size is power of 2, it will return original size. Perfect!) */ + size--; + size |= size >> 1; + size |= size >> 2; + size |= size >> 4; + size |= size >> 8; + size |= size >> 16; + size++; + + /* Return a power of 2 size at or above the input size. */ + return(size); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_alignment_adjust Cortex-M7/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function adjusts the alignment and size of the code and data */ +/* section for a given module implementation. */ +/* */ +/* INPUT */ +/* */ +/* module_preamble Pointer to module preamble */ +/* code_size Size of the code area (updated) */ +/* code_alignment Code area alignment (updated) */ +/* data_size Size of data area (updated) */ +/* data_alignment Data area alignment (updated) */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_power_of_two_block_size Calculate power of two size */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, + ULONG *code_size, + ULONG *code_alignment, + ULONG *data_size, + ULONG *data_alignment) +{ + +ULONG local_code_size; +ULONG local_code_alignment; +ULONG local_data_size; +ULONG local_data_alignment; +ULONG code_size_accum; +ULONG data_size_accum; + + /* Copy the input parameters into local variables for ease of use. */ + local_code_size = *code_size; + local_code_alignment = *code_alignment; + local_data_size = *data_size; + local_data_alignment = *data_alignment; + + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + local_code_alignment = _txm_power_of_two_block_size(local_code_size) >> 2; + code_size_accum = local_code_alignment + local_code_alignment; + code_size_accum = code_size_accum + (_txm_power_of_two_block_size(local_code_size - code_size_accum) >> 1); + code_size_accum = code_size_accum + _txm_power_of_two_block_size(local_code_size - code_size_accum); + local_code_size = code_size_accum; + + /* Determine data block sizes. Minimize the alignment requirement. + There are 4 MPU data entries available. The following is how the data size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to data size. + 2. 1/4 of the largest power of two that is greater than or equal to data size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + local_data_alignment = _txm_power_of_two_block_size(local_data_size) >> 2; + data_size_accum = local_data_alignment + local_data_alignment; + data_size_accum = data_size_accum + (_txm_power_of_two_block_size(local_data_size - data_size_accum) >> 1); + data_size_accum = data_size_accum + _txm_power_of_two_block_size(local_data_size - data_size_accum); + local_data_size = data_size_accum; + + /* Return all the information to the caller. */ + *code_size = local_code_size; + *code_alignment = local_code_alignment; + *data_size = local_data_size; + *data_alignment = local_data_alignment; +} + + + diff --git a/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_external_memory_enable.c new file mode 100644 index 00000000..f17e7388 --- /dev/null +++ b/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -0,0 +1,195 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_mutex.h" +#include "tx_queue.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_external_memory_enable Cortex-M7/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates an entry in the MPU table for a shared */ +/* memory space. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* start_address Start address of memory */ +/* length Length of external memory */ +/* attributes Memory attributes (r/w) */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_mutex_get Get protection mutex */ +/* _tx_mutex_put Release protection mutex */ +/* _txm_power_of_two_block_size Round length to power of two */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, + VOID *start_address, + ULONG length, + UINT attributes) +{ + +ULONG block_size; +ULONG region_size; +ULONG srd_bits; +ULONG size_register; +ULONG address; +ULONG shared_index; +ULONG attributes_check = 0; + + /* Determine if the module manager has been initialized. */ + if (_txm_module_manager_ready != TX_TRUE) + { + + /* Module manager has not been initialized. */ + return(TX_NOT_AVAILABLE); + } + + /* Determine if the module is valid. */ + if (module_instance == TX_NULL) + { + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Get module manager protection mutex. */ + _tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER); + + /* Determine if the module instance is valid. */ + if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) + { + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Determine if the module instance is in the loaded state. */ + if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) + { + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not ready. */ + return(TX_START_ERROR); + } + + /* Determine if there are shared memory entries available. */ + if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) + { + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* No more entries available. */ + return(TX_NO_MEMORY); + } + + /* Start address and length must adhere to Cortex-M7 MPU. + The address must align with the block size. */ + + block_size = _txm_power_of_two_block_size(length); + address = (ULONG) start_address; + if(address != (address & ~(block_size - 1))) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return alignment error. */ + return(TXM_MODULE_ALIGNMENT_ERROR); + } + + /* At this point, we have a valid address and block size. + Set up MPU registers. */ + + /* Pick up index into shared memory entries. */ + shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; + + /* Save address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_address = address | shared_index | 0x10; + + /* Calculate the region size. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Calculate the subregion bits. */ + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, length); + + /* Generate SRD, size, and enable attributes. */ + size_register = srd_bits | region_size | TXM_ENABLE_REGION | TXM_MODULE_MPU_SHARED_ACCESS_CONTROL; + + /* Check for optional write attribute. */ + if(attributes & TXM_MODULE_MANAGER_SHARED_ATTRIBUTE_WRITE) + { + attributes_check = TXM_MODULE_MANAGER_ATTRIBUTE_WRITE_MPU_BIT; + } + + /* Save attribute-size register. */ + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_attribute_size = attributes_check | size_register; + + /* Keep track of shared memory address and length in module instance. */ + module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; + module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; + + /* Increment counter. */ + module_instance -> txm_module_instance_shared_memory_count++; + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return success. */ + return(TX_SUCCESS); +} + diff --git a/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_memory_fault_handler.c new file mode 100644 index 00000000..5aac2bac --- /dev/null +++ b/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -0,0 +1,114 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + +/* Define a macro that can be used to allocate global variables useful to + store information about the last fault. This macro is defined in + txm_module_port.h and is usually populated in the assembly language + fault handling prior to the code calling _txm_module_manager_memory_fault_handler. */ + +TXM_MODULE_MANAGER_FAULT_INFO + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_handler Cortex-M7/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles a fault associated with a memory protected */ +/* module. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_terminate Terminate thread */ +/* */ +/* CALLED BY */ +/* */ +/* Fault handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_memory_fault_handler(VOID) +{ + +TXM_MODULE_INSTANCE *module_instance_ptr; +TX_THREAD *thread_ptr; + + + /* Pickup the current thread. */ + thread_ptr = _tx_thread_current_ptr; + + /* Initialize the module instance pointer to NULL. */ + module_instance_ptr = TX_NULL; + + /* Is there a thread? */ + if (thread_ptr) + { + + /* Pickup the module instance. */ + module_instance_ptr = thread_ptr -> tx_thread_module_instance_ptr; + + /* Terminate the current thread. */ + _tx_thread_terminate(_tx_thread_current_ptr); + } + + /* Determine if there is a user memory fault notification callback. */ + if (_txm_module_manager_fault_notify) + { + + /* Yes, call the user's notification memory fault callback. */ + (_txm_module_manager_fault_notify)(thread_ptr, module_instance_ptr); + } +} + diff --git a/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_memory_fault_notify.c new file mode 100644 index 00000000..cd8c1e29 --- /dev/null +++ b/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -0,0 +1,86 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the external user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_notify Cortex-M7/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application callback when/if a memory */ +/* fault occurs. The supplied thread is automatically terminated, but */ +/* any other threads in the same module may still execute. */ +/* */ +/* INPUT */ +/* */ +/* notify_function Memory fault notification */ +/* function, NULL disables. */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +{ + + /* Setup notification function. */ + _txm_module_manager_fault_notify = notify_function; + + /* Return success. */ + return(TX_SUCCESS); +} + diff --git a/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_mm_register_setup.c new file mode 100644 index 00000000..c797080c --- /dev/null +++ b/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -0,0 +1,656 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" +#include "txm_module_manager_util.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_region_size_get Cortex-M7/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function converts the region size in bytes to the block size */ +/* for the Cortex-M7 MPU specification. */ +/* */ +/* INPUT */ +/* */ +/* block_size Size of the block in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* MPU size specification */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_module_manager_region_size_get(ULONG block_size) +{ + +ULONG return_value; + + + /* Process relative to the input block size. */ + if (block_size == 32) + { + return_value = 0x04; + } + else if (block_size == 64) + { + return_value = 0x05; + } + else if (block_size == 128) + { + return_value = 0x06; + } + else if (block_size == 256) + { + return_value = 0x07; + } + else if (block_size == 512) + { + return_value = 0x08; + } + else if (block_size == 1024) + { + return_value = 0x09; + } + else if (block_size == 2048) + { + return_value = 0x0A; + } + else if (block_size == 4096) + { + return_value = 0x0B; + } + else if (block_size == 8192) + { + return_value = 0x0C; + } + else if (block_size == 16384) + { + return_value = 0x0D; + } + else if (block_size == 32768) + { + return_value = 0x0E; + } + else if (block_size == 65536) + { + return_value = 0x0F; + } + else if (block_size == 131072) + { + return_value = 0x10; + } + else if (block_size == 262144) + { + return_value = 0x11; + } + else if (block_size == 524288) + { + return_value = 0x12; + } + else if (block_size == 1048576) + { + return_value = 0x13; + } + else if (block_size == 2097152) + { + return_value = 0x14; + } + else + { + /* Max 4MB MPU pages for modules. */ + return_value = 0x15; + } + + return(return_value); +} + + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_calculate_srd_bits Cortex-M7/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calculates the SRD bits that need to be set to */ +/* protect "length" bytes in a block. */ +/* */ +/* INPUT */ +/* */ +/* block_size Size of the block in bytes */ +/* length Actual length in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* SRD bits to be OR'ed with region attribute register. */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_mm_register_setup */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +ULONG _txm_module_manager_calculate_srd_bits(ULONG block_size, ULONG length) +{ + +ULONG srd_bits = 0; +UINT srd_bit_index; + + /* length is smaller than block_size, set SRD bits if block_size is 256 or more. */ + if((block_size >= 256) && (length < block_size)) + { + /* Divide block_size by 8 by shifting right 3. Result is size of subregion. */ + block_size = block_size >> 3; + + /* Set SRD index into attribute register. */ + srd_bit_index = 8; + + /* If subregion overlaps length, move to the next subregion. */ + while(length > block_size) + { + length = length - block_size; + srd_bit_index++; + } + /* Check for a portion of code remaining. */ + if(length) + { + srd_bit_index++; + } + + /* Set unused subregion bits. */ + while(srd_bit_index < 16) + { + srd_bits = srd_bits | (0x1 << srd_bit_index); + srd_bit_index++; + } + } + + return(srd_bits); +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_mm_register_setup Cortex-M7/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets up the MPU register definitions based on the */ +/* module's memory characteristics. */ +/* MPU layout for the Cortex-M7: */ +/* Entry Description */ +/* 0 Kernel mode entry */ +/* 1 Module code region */ +/* 2 Module code region */ +/* 3 Module code region */ +/* 4 Module code region */ +/* 5 Module data region */ +/* 6 Module data region */ +/* 7 Module data region */ +/* 8 Module data region */ +/* 9 Module shared memory region */ +/* 10 Module shared memory region */ +/* 11 Module shared memory region */ +/* 12 Unused region */ +/* 13 Unused region */ +/* 14 Unused region */ +/* 15 Unused region */ +/* */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* */ +/* OUTPUT */ +/* */ +/* MPU specifications for module in module_instance */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_manager_region_size_get */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_thread_create */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) +{ + +ULONG code_address; +ULONG code_size; +ULONG data_address; +ULONG data_size; +ULONG start_stop_stack_size; +ULONG callback_stack_size; +ULONG block_size; +ULONG region_size; +ULONG srd_bits = 0; +UINT mpu_table_index; +UINT i; + + + /* Setup the first MPU region for kernel mode entry. */ + /* Set address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. + Mask address to proper range, region 0, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | 0x10; + /* Set the attributes, size (32 bytes) and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | (_txm_module_manager_region_size_get(32) << 1) | TXM_ENABLE_REGION; + /* End of kernel mode entry setup. */ + + /* Setup code protection. */ + + /* Initialize the MPU table index. */ + mpu_table_index = 1; + + /* Pickup code starting address and actual size. */ + code_address = (ULONG) module_instance -> txm_module_instance_code_start; + code_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size; + + /* Determine code block sizes. Minimize the alignment requirement. + There are 4 MPU code entries available. The following is how the code size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to code size. + 2. 1/4 of the largest power of two that is greater than or equal to code size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + + /* Now loop through to setup MPU protection for the code area. */ + for (i = 0; i < TXM_MODULE_MPU_CODE_ENTRIES; i++) + { + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to code size. */ + if (i < 2) + { + block_size = _txm_power_of_two_block_size(code_size) >> 2; + } + + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ + else if (i == 2) + { + /* Subtract (block_size*2) from code_size to calculate remaining space. */ + code_size = code_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(code_size) >> 1; + } + + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + else + { + /* Calculate remaining space. */ + code_size = code_size - block_size; + block_size = _txm_power_of_two_block_size(code_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, code_size); + } + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (code_address & ~(block_size - 1)) | mpu_table_index | 0x10; + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_CODE_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; + + /* Adjust the code address. */ + code_address = code_address + block_size; + + /* Increment MPU table index. */ + mpu_table_index++; + } + /* End of code protection. */ + + /* Setup data protection. */ + + /* Reset SRD bitfield. */ + srd_bits = 0; + + /* Pickup data starting address and actual size. */ + data_address = (ULONG) module_instance -> txm_module_instance_data_start; + + /* Adjust the size of the module elements to be aligned to the default alignment. We do this + so that when we partition the allocated memory, we can simply place these regions right beside + each other without having to align their pointers. Note this only works when they all have + the same alignment. */ + + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; + start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; + callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; + + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + /* Update the data size to include thread stacks. */ + data_size = data_size + start_stop_stack_size + callback_stack_size; + + /* Determine data block sizes. Minimize the alignment requirement. + There are 4 MPU data entries available. The following is how the data size + will be distributed: + 1. 1/4 of the largest power of two that is greater than or equal to data size. + 2. 1/4 of the largest power of two that is greater than or equal to data size. + 3. Largest power of 2 that fits in the remaining space. + 4. Smallest power of 2 that exceeds the remaining space, minimum 32. */ + + /* Now loop through to setup MPU protection for the data area. */ + for (i = 0; i < TXM_MODULE_MPU_DATA_ENTRIES; i++) + { + /* First two MPU blocks are 1/4 of the largest power of two + that is greater than or equal to data size. */ + if (i < 2) + { + block_size = _txm_power_of_two_block_size(data_size) >> 2; + } + + /* Third MPU block is the largest power of 2 that fits in the remaining space. */ + else if (i == 2) + { + /* Subtract (block_size*2) from data_size to calculate remaining space. */ + data_size = data_size - (block_size << 1); + block_size = _txm_power_of_two_block_size(data_size) >> 1; + } + + /* Last MPU block is the smallest power of 2 that exceeds the remaining space, minimum 32. */ + else + { + /* Calculate remaining space. */ + data_size = data_size - block_size; + block_size = _txm_power_of_two_block_size(data_size); + srd_bits = _txm_module_manager_calculate_srd_bits(block_size, data_size); + } + + /* Calculate the region size information. */ + region_size = (_txm_module_manager_region_size_get(block_size) << 1); + + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = (data_address & ~(block_size - 1)) | mpu_table_index | 0x10; + /* Build the attribute-size register with permissions, SRD, size, enable. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_attribute_size = TXM_MODULE_MPU_DATA_ACCESS_CONTROL | srd_bits | region_size | TXM_ENABLE_REGION; + + /* Adjust the data address. */ + data_address = data_address + block_size; + + /* Increment MPU table index. */ + mpu_table_index++; + } + + /* Setup MPU for the remaining regions. */ + while (mpu_table_index < TXM_MODULE_MPU_TOTAL_ENTRIES) + { + /* Build the base address register with address, MPU region, set Valid bit. */ + module_instance -> txm_module_instance_mpu_registers[mpu_table_index].txm_module_mpu_region_address = mpu_table_index | 0x10; + + /* Increment MPU table index. */ + mpu_table_index++; + } + +} + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_shared_memory_check_outside */ +/* Cortex-M7/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks if the specified object is outside shared */ +/* memory. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* obj_ptr Pointer to the object */ +/* obj_size Size of the object */ +/* */ +/* OUTPUT */ +/* */ +/* Whether the object is outside the shared memory region. */ +/* */ +/* CALLS */ +/* */ +/* N/A */ +/* */ +/* CALLED BY */ +/* */ +/* Module dispatch check functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UCHAR _txm_module_manager_shared_memory_check_outside(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) +{ + +UINT shared_memory_index; +UINT num_shared_memory_mpu_entries; +ALIGN_TYPE shared_memory_address_start; +ALIGN_TYPE shared_memory_address_end; + + num_shared_memory_mpu_entries = module_instance -> txm_module_instance_shared_memory_count; + for (shared_memory_index = 0; shared_memory_index < num_shared_memory_mpu_entries; shared_memory_index++) + { + + shared_memory_address_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address[shared_memory_index]; + shared_memory_address_end = shared_memory_address_start + module_instance -> txm_module_instance_shared_memory_length[shared_memory_index]; + + if (TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_EXCLUSIVE(shared_memory_address_start, shared_memory_address_end, + obj_ptr, obj_size)) + { + return(TX_FALSE); + } + } + + return(TX_TRUE); +} + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_shared_memory_check_inside Cortex-M7/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks if the specified object is inside shared */ +/* memory. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* obj_ptr Pointer to the object */ +/* obj_size Size of the object */ +/* */ +/* OUTPUT */ +/* */ +/* Whether the object is inside the shared memory region. */ +/* */ +/* CALLS */ +/* */ +/* N/A */ +/* */ +/* CALLED BY */ +/* */ +/* Module dispatch check functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UCHAR _txm_module_manager_shared_memory_check_inside(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) +{ + +UINT shared_memory_index; +UINT num_shared_memory_mpu_entries; +ALIGN_TYPE shared_memory_address_start; +ALIGN_TYPE shared_memory_address_end; + + num_shared_memory_mpu_entries = module_instance -> txm_module_instance_shared_memory_count; + for (shared_memory_index = 0; shared_memory_index < num_shared_memory_mpu_entries; shared_memory_index++) + { + + shared_memory_address_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address[shared_memory_index]; + shared_memory_address_end = shared_memory_address_start + module_instance -> txm_module_instance_shared_memory_length[shared_memory_index]; + + if (TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_EXCLUSIVE(shared_memory_address_start, shared_memory_address_end, + obj_ptr, obj_size)) + { + return(TX_TRUE); + } + } + + return(TX_FALSE); +} + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_shared_memory_check_inside_byte */ +/* Cortex-M7/MPU/IAR */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks if the specified byte is inside shared memory. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* byte_ptr Pointer to the byte */ +/* */ +/* OUTPUT */ +/* */ +/* Whether the byte is inside the shared memory region. */ +/* */ +/* CALLS */ +/* */ +/* N/A */ +/* */ +/* CALLED BY */ +/* */ +/* Module dispatch check functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +UCHAR _txm_module_manager_shared_memory_check_inside_byte(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE byte_ptr) +{ + +UINT shared_memory_index; +UINT num_shared_memory_mpu_entries; +ALIGN_TYPE shared_memory_address_start; +ALIGN_TYPE shared_memory_address_end; + + num_shared_memory_mpu_entries = module_instance -> txm_module_instance_shared_memory_count; + for (shared_memory_index = 0; shared_memory_index < num_shared_memory_mpu_entries; shared_memory_index++) + { + + shared_memory_address_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address[shared_memory_index]; + shared_memory_address_end = shared_memory_address_start + module_instance -> txm_module_instance_shared_memory_length[shared_memory_index]; + + if (TXM_MODULE_MANAGER_CHECK_INSIDE_RANGE_EXCLUSIVE_BYTE(shared_memory_address_start, shared_memory_address_end, + byte_ptr)) + { + return(TX_TRUE); + } + } + + return(TX_FALSE); +} diff --git a/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_thread_stack_build.s new file mode 100644 index 00000000..50f5b003 --- /dev/null +++ b/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_thread_stack_build.s @@ -0,0 +1,153 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Module Manager */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _txm_module_manager_thread_stack_build Cortex-M7/MPU/IAR */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread */ +;/* function_ptr Pointer to shell function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 Scott Larson Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +;{ + PUBLIC _txm_module_manager_thread_stack_build +_txm_module_manager_thread_stack_build: +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-M should look like the following after it is built: +; +; Stack Top: +; LR Interrupted LR (LR at time of PENDSV) +; r4 Initial value for r4 +; r5 Initial value for r5 +; r6 Initial value for r6 +; r7 Initial value for r7 +; r8 Initial value for r8 +; r9 Initial value for r9 +; r10 (sl) Initial value for r10 (sl) +; r11 Initial value for r11 +; r0 Initial value for r0 (Hardware stack starts here!!) +; r1 Initial value for r1 +; r2 Initial value for r2 +; r3 Initial value for r3 +; r12 Initial value for r12 +; lr Initial value for lr +; pc Initial value for pc +; xPSR Initial value for xPSR +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #0x7 ; Align frame + SUB r2, r2, #68 ; Subtract frame size + LDR r3, =0xFFFFFFFD ; Build initial LR value + STR r3, [r2, #0] ; Save on the stack +; +; /* Actually build the stack frame. */ +; + MOV r3, #0 ; Build initial register value + STR r3, [r2, #4] ; Store initial r4 + STR r3, [r2, #8] ; Store initial r5 + STR r3, [r2, #12] ; Store initial r6 + STR r3, [r2, #16] ; Store initial r7 + STR r3, [r2, #20] ; Store initial r8 + LDR r3, [r0, #12] ; Pickup stack starting address + STR r3, [r2, #28] ; Store initial r10 (sl) + MOV r3, #0 ; Build initial register value + STR r3, [r2, #32] ; Store initial r11 +; +; /* Hardware stack follows. / +; + STR r0, [r2, #36] ; Store initial r0, which is the thread control block + + LDR r3, [r0, #8] ; Pickup thread entry info pointer,which is in the stack pointer position of the thread control block. + ; It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this + ; function with the actual, initial stack pointer. + STR r3, [r2, #40] ; Store initial r1, which is the module entry information. + LDR r3, [r3, #8] ; Pickup data base register from the module information + STR r3, [r2, #24] ; Store initial r9 (data base register) + MOV r3, #0 ; Clear r3 again + + STR r3, [r2, #44] ; Store initial r2 + STR r3, [r2, #48] ; Store initial r3 + STR r3, [r2, #52] ; Store initial r12 + MOV r3, #0xFFFFFFFF ; Poison EXC_RETURN value + STR r3, [r2, #56] ; Store initial lr + STR r1, [r2, #60] ; Store initial pc + MOV r3, #0x01000000 ; Only T-bit need be set + STR r3, [r2, #64] ; Store initial xPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block + BX lr ; Return to caller +;} + END + diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.lock b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.lock new file mode 100644 index 00000000..e69de29b diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.log b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.log new file mode 100644 index 00000000..bfda2511 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.log @@ -0,0 +1,3457 @@ +!SESSION 2015-09-28 16:00:20.788 ----------------------------------------------- +eclipse.buildId=unknown +java.version=1.8.0_25 +java.vendor=Oracle Corporation +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US +Command-line arguments: -os win32 -ws win32 -arch x86 -data C:\temp1663\tesp + +!ENTRY org.eclipse.cdt.core 1 0 2015-09-28 16:03:16.758 +!MESSAGE Indexed 'tx' (0 sources, 0 headers) in 0.003 sec: 0 declarations; 0 references; 0 unresolved inclusions; 0 syntax errors; 0 unresolved names (0%) + +!ENTRY org.eclipse.cdt.core 1 0 2015-09-28 16:08:56.869 +!MESSAGE Indexed 'sample_threadx' (0 sources, 0 headers) in 0 sec: 0 declarations; 0 references; 0 unresolved inclusions; 0 syntax errors; 0 unresolved names (0%) + +!ENTRY org.eclipse.debug.core 4 5012 2015-09-28 16:13:02.280 +!MESSAGE org.xml.sax.SAXParseException; lineNumber: 438; columnNumber: 1; Content is not allowed in trailing section. occurred while reading launch configuration file: C:\temp1663\tesp\.metadata\.plugins\org.eclipse.debug.core\.launches\sample_threadx Debug.launch. +!STACK 0 +org.xml.sax.SAXParseException; lineNumber: 438; columnNumber: 1; Content is not allowed in trailing section. + at com.sun.org.apache.xerces.internal.util.ErrorHandlerWrapper.createSAXParseException(ErrorHandlerWrapper.java:203) + at com.sun.org.apache.xerces.internal.util.ErrorHandlerWrapper.fatalError(ErrorHandlerWrapper.java:177) + at com.sun.org.apache.xerces.internal.impl.XMLErrorReporter.reportError(XMLErrorReporter.java:441) + at com.sun.org.apache.xerces.internal.impl.XMLErrorReporter.reportError(XMLErrorReporter.java:368) + at com.sun.org.apache.xerces.internal.impl.XMLScanner.reportFatalError(XMLScanner.java:1436) + at com.sun.org.apache.xerces.internal.impl.XMLDocumentScannerImpl$TrailingMiscDriver.next(XMLDocumentScannerImpl.java:1433) + at com.sun.org.apache.xerces.internal.impl.XMLDocumentScannerImpl.next(XMLDocumentScannerImpl.java:606) + at com.sun.org.apache.xerces.internal.impl.XMLDocumentFragmentScannerImpl.scanDocument(XMLDocumentFragmentScannerImpl.java:510) + at com.sun.org.apache.xerces.internal.parsers.XML11Configuration.parse(XML11Configuration.java:848) + at com.sun.org.apache.xerces.internal.parsers.XML11Configuration.parse(XML11Configuration.java:777) + at com.sun.org.apache.xerces.internal.parsers.XMLParser.parse(XMLParser.java:141) + at com.sun.org.apache.xerces.internal.parsers.DOMParser.parse(DOMParser.java:243) + at com.sun.org.apache.xerces.internal.jaxp.DocumentBuilderImpl.parse(DocumentBuilderImpl.java:348) + at org.eclipse.debug.internal.core.LaunchManager.createInfoFromXML(LaunchManager.java:954) + at org.eclipse.debug.internal.core.LaunchManager.getInfo(LaunchManager.java:1372) + at org.eclipse.debug.internal.core.LaunchConfiguration.getInfo(LaunchConfiguration.java:470) + at org.eclipse.debug.internal.core.LaunchConfiguration.getAttribute(LaunchConfiguration.java:416) + at org.eclipse.debug.ui.RefreshTab.getRefreshScope(RefreshTab.java:431) + at org.eclipse.cdt.launch.AbstractCLaunchDelegate$CLaunch.refresh(AbstractCLaunchDelegate.java:109) + at org.eclipse.cdt.launch.internal.ui.LaunchUIPlugin.launchesTerminated(LaunchUIPlugin.java:225) + at org.eclipse.debug.internal.core.LaunchManager$LaunchesNotifier.run(LaunchManager.java:318) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.debug.internal.core.LaunchManager$LaunchesNotifier.notify(LaunchManager.java:270) + at org.eclipse.debug.internal.core.LaunchManager.fireUpdate(LaunchManager.java:1055) + at org.eclipse.debug.core.Launch.fireTerminate(Launch.java:405) + at org.eclipse.debug.core.Launch.handleDebugEvents(Launch.java:577) + at org.eclipse.debug.core.DebugPlugin$EventNotifier.run(DebugPlugin.java:1151) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.debug.core.DebugPlugin$EventNotifier.dispatch(DebugPlugin.java:1187) + at org.eclipse.debug.core.DebugPlugin$EventDispatchJob.run(DebugPlugin.java:431) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) + +!ENTRY org.eclipse.e4.ui.workbench.swt 4 2 2015-09-28 16:13:17.470 +!MESSAGE Problems occurred when invoking code from plug-in: "org.eclipse.e4.ui.workbench.swt". +!STACK 0 +org.eclipse.e4.core.di.InjectionException: org.eclipse.swt.SWTException: Widget is disposed + at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:62) + at org.eclipse.e4.core.internal.di.InjectorImpl.processAnnotated(InjectorImpl.java:888) + at org.eclipse.e4.core.internal.di.InjectorImpl.disposed(InjectorImpl.java:390) + at org.eclipse.e4.core.internal.di.Requestor.disposed(Requestor.java:143) + at org.eclipse.e4.core.internal.contexts.ContextObjectSupplier$ContextInjectionListener.update(ContextObjectSupplier.java:76) + at org.eclipse.e4.core.internal.contexts.TrackableComputationExt.update(TrackableComputationExt.java:107) + at org.eclipse.e4.core.internal.contexts.TrackableComputationExt.handleInvalid(TrackableComputationExt.java:70) + at org.eclipse.e4.core.internal.contexts.EclipseContext.dispose(EclipseContext.java:175) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.clearContext(PartRenderingEngine.java:974) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeRemoveGui(PartRenderingEngine.java:954) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$3(PartRenderingEngine.java:862) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$8.run(PartRenderingEngine.java:857) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.removeGui(PartRenderingEngine.java:841) + at org.eclipse.ui.internal.WorkbenchWindow.hardClose(WorkbenchWindow.java:1937) + at org.eclipse.ui.internal.WorkbenchWindow.busyClose(WorkbenchWindow.java:1560) + at org.eclipse.ui.internal.WorkbenchWindow.access$15(WorkbenchWindow.java:1527) + at org.eclipse.ui.internal.WorkbenchWindow$10.run(WorkbenchWindow.java:1592) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:70) + at org.eclipse.ui.internal.WorkbenchWindow.close(WorkbenchWindow.java:1589) + at org.eclipse.ui.internal.Workbench$14.run(Workbench.java:1155) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench.busyClose(Workbench.java:1137) + at org.eclipse.ui.internal.Workbench.access$21(Workbench.java:1079) + at org.eclipse.ui.internal.Workbench$19.run(Workbench.java:1410) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:70) + at org.eclipse.ui.internal.Workbench.close(Workbench.java:1407) + at org.eclipse.ui.internal.Workbench.restart(Workbench.java:2677) + at org.eclipse.ui.internal.ide.actions.OpenWorkspaceAction.restart(OpenWorkspaceAction.java:282) + at org.eclipse.ui.internal.ide.actions.OpenWorkspaceAction.run(OpenWorkspaceAction.java:264) + at org.eclipse.ui.internal.ide.actions.OpenWorkspaceAction$OpenDialogAction.run(OpenWorkspaceAction.java:70) + at org.eclipse.jface.action.Action.runWithEvent(Action.java:519) + at org.eclipse.jface.action.ActionContributionItem.handleWidgetSelection(ActionContributionItem.java:595) + at org.eclipse.jface.action.ActionContributionItem.access$2(ActionContributionItem.java:511) + at org.eclipse.jface.action.ActionContributionItem$5.handleEvent(ActionContributionItem.java:420) + at org.eclipse.swt.widgets.EventTable.sendEvent(EventTable.java:84) + at org.eclipse.swt.widgets.Display.sendEvent(Display.java:4353) + at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1061) + at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1085) + at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1070) + at org.eclipse.swt.widgets.Widget.notifyListeners(Widget.java:782) + at org.eclipse.jface.action.ActionContributionItem$9.handleEvent(ActionContributionItem.java:1293) + at org.eclipse.swt.widgets.EventTable.sendEvent(EventTable.java:84) + at org.eclipse.swt.widgets.Display.sendEvent(Display.java:4353) + at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1061) + at org.eclipse.swt.widgets.Display.runDeferredEvents(Display.java:4172) + at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3761) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$9.run(PartRenderingEngine.java:1151) + at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.run(PartRenderingEngine.java:1032) + at org.eclipse.e4.ui.internal.workbench.E4Workbench.createAndRunUI(E4Workbench.java:148) + at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:636) + at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332) + at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:579) + at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:150) + at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:135) + at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:380) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:235) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:483) + at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:648) + at org.eclipse.equinox.launcher.Main.basicRun(Main.java:603) + at org.eclipse.equinox.launcher.Main.run(Main.java:1465) +Caused by: org.eclipse.swt.SWTException: Widget is disposed + at org.eclipse.swt.SWT.error(SWT.java:4441) + at org.eclipse.swt.SWT.error(SWT.java:4356) + at org.eclipse.swt.SWT.error(SWT.java:4327) + at org.eclipse.swt.widgets.Widget.error(Widget.java:476) + at org.eclipse.swt.widgets.Widget.checkWidget(Widget.java:348) + at org.eclipse.swt.widgets.Shell.getSize(Shell.java:1092) + at org.eclipse.ui.internal.quickaccess.SearchField.storeDialog(SearchField.java:580) + at org.eclipse.ui.internal.quickaccess.SearchField.dispose(SearchField.java:557) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:483) + at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:55) + ... 67 more + +!ENTRY org.eclipse.e4.ui.workbench 4 0 2015-09-28 16:13:17.470 +!MESSAGE Exception occurred while unrendering: org.eclipse.e4.ui.model.application.ui.basic.impl.TrimmedWindowImpl@74d228 (elementId: IDEWindow, tags: [topLevel], contributorURI: platform:/plugin/org.eclipse.ui.workbench) (widget: null, renderer: null, toBeRendered: true, onTop: false, visible: true, containerData: null, accessibilityPhrase: null) (label: %trimmedwindow.label.eclipseSDK, iconURI: null, tooltip: null, context: null, variables: [], x: 369, y: 52, width: 1024, height: 775) +!STACK 0 +org.eclipse.e4.core.di.InjectionException: org.eclipse.swt.SWTException: Widget is disposed + at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:62) + at org.eclipse.e4.core.internal.di.InjectorImpl.processAnnotated(InjectorImpl.java:888) + at org.eclipse.e4.core.internal.di.InjectorImpl.disposed(InjectorImpl.java:390) + at org.eclipse.e4.core.internal.di.Requestor.disposed(Requestor.java:143) + at org.eclipse.e4.core.internal.contexts.ContextObjectSupplier$ContextInjectionListener.update(ContextObjectSupplier.java:76) + at org.eclipse.e4.core.internal.contexts.TrackableComputationExt.update(TrackableComputationExt.java:107) + at org.eclipse.e4.core.internal.contexts.TrackableComputationExt.handleInvalid(TrackableComputationExt.java:70) + at org.eclipse.e4.core.internal.contexts.EclipseContext.dispose(EclipseContext.java:175) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.clearContext(PartRenderingEngine.java:974) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeRemoveGui(PartRenderingEngine.java:954) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$3(PartRenderingEngine.java:862) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$8.run(PartRenderingEngine.java:857) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.removeGui(PartRenderingEngine.java:841) + at org.eclipse.ui.internal.WorkbenchWindow.hardClose(WorkbenchWindow.java:1937) + at org.eclipse.ui.internal.WorkbenchWindow.busyClose(WorkbenchWindow.java:1560) + at org.eclipse.ui.internal.WorkbenchWindow.access$15(WorkbenchWindow.java:1527) + at org.eclipse.ui.internal.WorkbenchWindow$10.run(WorkbenchWindow.java:1592) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:70) + at org.eclipse.ui.internal.WorkbenchWindow.close(WorkbenchWindow.java:1589) + at org.eclipse.ui.internal.Workbench$14.run(Workbench.java:1155) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench.busyClose(Workbench.java:1137) + at org.eclipse.ui.internal.Workbench.access$21(Workbench.java:1079) + at org.eclipse.ui.internal.Workbench$19.run(Workbench.java:1410) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:70) + at org.eclipse.ui.internal.Workbench.close(Workbench.java:1407) + at org.eclipse.ui.internal.Workbench.restart(Workbench.java:2677) + at org.eclipse.ui.internal.ide.actions.OpenWorkspaceAction.restart(OpenWorkspaceAction.java:282) + at org.eclipse.ui.internal.ide.actions.OpenWorkspaceAction.run(OpenWorkspaceAction.java:264) + at org.eclipse.ui.internal.ide.actions.OpenWorkspaceAction$OpenDialogAction.run(OpenWorkspaceAction.java:70) + at org.eclipse.jface.action.Action.runWithEvent(Action.java:519) + at org.eclipse.jface.action.ActionContributionItem.handleWidgetSelection(ActionContributionItem.java:595) + at org.eclipse.jface.action.ActionContributionItem.access$2(ActionContributionItem.java:511) + at org.eclipse.jface.action.ActionContributionItem$5.handleEvent(ActionContributionItem.java:420) + at org.eclipse.swt.widgets.EventTable.sendEvent(EventTable.java:84) + at org.eclipse.swt.widgets.Display.sendEvent(Display.java:4353) + at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1061) + at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1085) + at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1070) + at org.eclipse.swt.widgets.Widget.notifyListeners(Widget.java:782) + at org.eclipse.jface.action.ActionContributionItem$9.handleEvent(ActionContributionItem.java:1293) + at org.eclipse.swt.widgets.EventTable.sendEvent(EventTable.java:84) + at org.eclipse.swt.widgets.Display.sendEvent(Display.java:4353) + at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1061) + at org.eclipse.swt.widgets.Display.runDeferredEvents(Display.java:4172) + at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3761) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$9.run(PartRenderingEngine.java:1151) + at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.run(PartRenderingEngine.java:1032) + at org.eclipse.e4.ui.internal.workbench.E4Workbench.createAndRunUI(E4Workbench.java:148) + at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:636) + at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332) + at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:579) + at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:150) + at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:135) + at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:380) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:235) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:483) + at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:648) + at org.eclipse.equinox.launcher.Main.basicRun(Main.java:603) + at org.eclipse.equinox.launcher.Main.run(Main.java:1465) +Caused by: org.eclipse.swt.SWTException: Widget is disposed + at org.eclipse.swt.SWT.error(SWT.java:4441) + at org.eclipse.swt.SWT.error(SWT.java:4356) + at org.eclipse.swt.SWT.error(SWT.java:4327) + at org.eclipse.swt.widgets.Widget.error(Widget.java:476) + at org.eclipse.swt.widgets.Widget.checkWidget(Widget.java:348) + at org.eclipse.swt.widgets.Shell.getSize(Shell.java:1092) + at org.eclipse.ui.internal.quickaccess.SearchField.storeDialog(SearchField.java:580) + at org.eclipse.ui.internal.quickaccess.SearchField.dispose(SearchField.java:557) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:483) + at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:55) + ... 67 more +!SESSION 2015-10-02 16:29:55.871 ----------------------------------------------- +eclipse.buildId=unknown +java.version=1.8.0_25 +java.vendor=Oracle Corporation +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US +Command-line arguments: -os win32 -ws win32 -arch x86 + +!ENTRY org.eclipse.jface 2 0 2015-10-02 16:30:38.664 +!MESSAGE Keybinding conflicts occurred. They may interfere with normal accelerator operation. +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-02 16:30:38.664 +!MESSAGE A conflict occurred for ALT+CTRL+I: +Binding(ALT+CTRL+I, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.include.browser,Open Include Browser, + Open an include browser on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1b69ccb, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+CTRL+I, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.include.browser,Open Include Browser, + Open an include browser on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1b69ccb, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-02 16:30:38.664 +!MESSAGE A conflict occurred for CTRL+SHIFT+T: +Binding(CTRL+SHIFT+T, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.opentype,Open Element, + Open an element in an Editor, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@9f0360, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+T, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.opentype,Open Element, + Open an element in an Editor, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@9f0360, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-02 16:30:38.664 +!MESSAGE A conflict occurred for ALT+SHIFT+R: +Binding(ALT+SHIFT+R, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.rename.element,Rename - Refactoring , + Renames the selected element, + Category(org.eclipse.cdt.ui.category.refactoring,Refactor - C++,C/C++ Refactorings,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@112b637, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+SHIFT+R, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.rename.element,Rename - Refactoring , + Renames the selected element, + Category(org.eclipse.cdt.ui.category.refactoring,Refactor - C++,C/C++ Refactorings,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@112b637, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-02 16:30:38.664 +!MESSAGE A conflict occurred for CTRL+SHIFT+G: +Binding(CTRL+SHIFT+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.findrefs,References, + Searches for references to the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@ea0b48, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.findrefs,References, + Searches for references to the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@ea0b48, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-02 16:30:38.664 +!MESSAGE A conflict occurred for CTRL+G: +Binding(CTRL+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration, + Searches for declarations of the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1eb8e9a, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration, + Searches for declarations of the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1eb8e9a, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-02 16:30:38.664 +!MESSAGE A conflict occurred for ALT+CTRL+H: +Binding(ALT+CTRL+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.call.hierarchy,Open Call Hierarchy, + Opens the call hierarchy for the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@15d1204, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+CTRL+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.call.hierarchy,Open Call Hierarchy, + Opens the call hierarchy for the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@15d1204, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-02 16:30:38.664 +!MESSAGE A conflict occurred for CTRL+SHIFT+H: +Binding(CTRL+SHIFT+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.open.type.in.hierarchy,Open Type in Hierarchy, + Open a type in the type hierarchy view, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@184a296, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.open.type.in.hierarchy,Open Type in Hierarchy, + Open a type in the type hierarchy view, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@184a296, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-02 16:30:38.664 +!MESSAGE A conflict occurred for F3: +Binding(F3, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.opendecl,Open Declaration, + Opens an editor on the selected element's declaration(s), + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1ea4b65, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(F3, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.opendecl,Open Declaration, + Opens an editor on the selected element's declaration(s), + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1ea4b65, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-02 16:30:38.664 +!MESSAGE A conflict occurred for F4: +Binding(F4, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.type.hierarchy,Open Type Hierarchy, + Open a type hierarchy on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@f6839c, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(F4, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.type.hierarchy,Open Type Hierarchy, + Open a type hierarchy on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@f6839c, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) + +!ENTRY org.eclipse.debug.core 4 2 2015-10-02 17:42:00.298 +!MESSAGE Problems occurred when invoking code from plug-in: "org.eclipse.debug.core". +!STACK 0 +org.eclipse.swt.SWTException: Device is disposed + at org.eclipse.swt.SWT.error(SWT.java:4441) + at org.eclipse.swt.SWT.error(SWT.java:4356) + at org.eclipse.swt.SWT.error(SWT.java:4327) + at org.eclipse.swt.widgets.Display.error(Display.java:1258) + at org.eclipse.swt.widgets.Display.getThread(Display.java:2602) + at org.eclipse.debug.internal.ui.stringsubstitution.SelectedResourceManager.getActiveWindow(SelectedResourceManager.java:239) + at org.eclipse.debug.ui.DebugUITools.getDebugContext(DebugUITools.java:229) + at org.eclipse.cdt.debug.internal.ui.actions.RemoveAllGlobalsActionDelegate.update(RemoveAllGlobalsActionDelegate.java:99) + at org.eclipse.cdt.debug.internal.ui.actions.RemoveAllGlobalsActionDelegate.handleDebugEvents(RemoveAllGlobalsActionDelegate.java:131) + at org.eclipse.debug.core.DebugPlugin$EventNotifier.run(DebugPlugin.java:1151) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.debug.core.DebugPlugin$EventNotifier.dispatch(DebugPlugin.java:1187) + at org.eclipse.debug.core.DebugPlugin$EventDispatchJob.run(DebugPlugin.java:431) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) + +!ENTRY org.eclipse.debug.core 4 125 2015-10-02 17:42:00.298 +!MESSAGE An exception occurred while dispatching debug events. +!STACK 0 +org.eclipse.swt.SWTException: Device is disposed + at org.eclipse.swt.SWT.error(SWT.java:4441) + at org.eclipse.swt.SWT.error(SWT.java:4356) + at org.eclipse.swt.SWT.error(SWT.java:4327) + at org.eclipse.swt.widgets.Display.error(Display.java:1258) + at org.eclipse.swt.widgets.Display.getThread(Display.java:2602) + at org.eclipse.debug.internal.ui.stringsubstitution.SelectedResourceManager.getActiveWindow(SelectedResourceManager.java:239) + at org.eclipse.debug.ui.DebugUITools.getDebugContext(DebugUITools.java:229) + at org.eclipse.cdt.debug.internal.ui.actions.RemoveAllGlobalsActionDelegate.update(RemoveAllGlobalsActionDelegate.java:99) + at org.eclipse.cdt.debug.internal.ui.actions.RemoveAllGlobalsActionDelegate.handleDebugEvents(RemoveAllGlobalsActionDelegate.java:131) + at org.eclipse.debug.core.DebugPlugin$EventNotifier.run(DebugPlugin.java:1151) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.debug.core.DebugPlugin$EventNotifier.dispatch(DebugPlugin.java:1187) + at org.eclipse.debug.core.DebugPlugin$EventDispatchJob.run(DebugPlugin.java:431) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) +!SESSION 2015-10-05 13:04:20.828 ----------------------------------------------- +eclipse.buildId=unknown +java.version=1.8.0_25 +java.vendor=Oracle Corporation +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US +Command-line arguments: -os win32 -ws win32 -arch x86 + +!ENTRY org.eclipse.jface 2 0 2015-10-05 13:23:37.148 +!MESSAGE Keybinding conflicts occurred. They may interfere with normal accelerator operation. +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-05 13:23:37.148 +!MESSAGE A conflict occurred for ALT+CTRL+I: +Binding(ALT+CTRL+I, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.include.browser,Open Include Browser, + Open an include browser on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@3cdce6, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+CTRL+I, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.include.browser,Open Include Browser, + Open an include browser on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@3cdce6, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-05 13:23:37.148 +!MESSAGE A conflict occurred for CTRL+SHIFT+G: +Binding(CTRL+SHIFT+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.findrefs,References, + Searches for references to the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@15453dc, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.findrefs,References, + Searches for references to the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@15453dc, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-05 13:23:37.148 +!MESSAGE A conflict occurred for CTRL+G: +Binding(CTRL+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration, + Searches for declarations of the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@a8e1f7, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration, + Searches for declarations of the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@a8e1f7, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-05 13:23:37.148 +!MESSAGE A conflict occurred for ALT+CTRL+H: +Binding(ALT+CTRL+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.call.hierarchy,Open Call Hierarchy, + Opens the call hierarchy for the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@7edea3, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+CTRL+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.call.hierarchy,Open Call Hierarchy, + Opens the call hierarchy for the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@7edea3, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-05 13:23:37.148 +!MESSAGE A conflict occurred for CTRL+SHIFT+H: +Binding(CTRL+SHIFT+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.open.type.in.hierarchy,Open Type in Hierarchy, + Open a type in the type hierarchy view, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@ffee26, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.open.type.in.hierarchy,Open Type in Hierarchy, + Open a type in the type hierarchy view, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@ffee26, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-05 13:23:37.148 +!MESSAGE A conflict occurred for F4: +Binding(F4, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.type.hierarchy,Open Type Hierarchy, + Open a type hierarchy on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1149b96, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(F4, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.type.hierarchy,Open Type Hierarchy, + Open a type hierarchy on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1149b96, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-05 13:23:37.148 +!MESSAGE A conflict occurred for ALT+SHIFT+R: +Binding(ALT+SHIFT+R, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.rename.element,Rename - Refactoring , + Renames the selected element, + Category(org.eclipse.cdt.ui.category.refactoring,Refactor - C++,C/C++ Refactorings,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@7c6dda, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+SHIFT+R, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.rename.element,Rename - Refactoring , + Renames the selected element, + Category(org.eclipse.cdt.ui.category.refactoring,Refactor - C++,C/C++ Refactorings,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@7c6dda, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-05 13:23:37.148 +!MESSAGE A conflict occurred for CTRL+SHIFT+T: +Binding(CTRL+SHIFT+T, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.opentype,Open Element, + Open an element in an Editor, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@3d31b0, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+T, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.opentype,Open Element, + Open an element in an Editor, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@3d31b0, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-05 13:23:37.148 +!MESSAGE A conflict occurred for F3: +Binding(F3, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.opendecl,Open Declaration, + Opens an editor on the selected element's declaration(s), + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@12a690f, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(F3, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.opendecl,Open Declaration, + Opens an editor on the selected element's declaration(s), + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@12a690f, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SESSION 2015-10-06 09:33:14.510 ----------------------------------------------- +eclipse.buildId=unknown +java.version=1.8.0_25 +java.vendor=Oracle Corporation +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US +Command-line arguments: -os win32 -ws win32 -arch x86 + +!ENTRY org.eclipse.jface 2 0 2015-10-06 09:48:22.677 +!MESSAGE Keybinding conflicts occurred. They may interfere with normal accelerator operation. +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-06 09:48:22.677 +!MESSAGE A conflict occurred for CTRL+SHIFT+T: +Binding(CTRL+SHIFT+T, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.opentype,Open Element, + Open an element in an Editor, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@8206aa, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+T, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.opentype,Open Element, + Open an element in an Editor, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@8206aa, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-06 09:48:22.677 +!MESSAGE A conflict occurred for F4: +Binding(F4, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.type.hierarchy,Open Type Hierarchy, + Open a type hierarchy on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@e8535e, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(F4, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.type.hierarchy,Open Type Hierarchy, + Open a type hierarchy on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@e8535e, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-06 09:48:22.677 +!MESSAGE A conflict occurred for CTRL+SHIFT+G: +Binding(CTRL+SHIFT+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.findrefs,References, + Searches for references to the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1f4742b, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.findrefs,References, + Searches for references to the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1f4742b, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-06 09:48:22.677 +!MESSAGE A conflict occurred for CTRL+G: +Binding(CTRL+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration, + Searches for declarations of the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1b3de87, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration, + Searches for declarations of the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1b3de87, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-06 09:48:22.677 +!MESSAGE A conflict occurred for ALT+CTRL+H: +Binding(ALT+CTRL+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.call.hierarchy,Open Call Hierarchy, + Opens the call hierarchy for the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@132284d, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+CTRL+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.call.hierarchy,Open Call Hierarchy, + Opens the call hierarchy for the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@132284d, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-06 09:48:22.677 +!MESSAGE A conflict occurred for CTRL+SHIFT+H: +Binding(CTRL+SHIFT+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.open.type.in.hierarchy,Open Type in Hierarchy, + Open a type in the type hierarchy view, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@15ae856, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.open.type.in.hierarchy,Open Type in Hierarchy, + Open a type in the type hierarchy view, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@15ae856, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-06 09:48:22.677 +!MESSAGE A conflict occurred for ALT+SHIFT+R: +Binding(ALT+SHIFT+R, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.rename.element,Rename - Refactoring , + Renames the selected element, + Category(org.eclipse.cdt.ui.category.refactoring,Refactor - C++,C/C++ Refactorings,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@15b83fa, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+SHIFT+R, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.rename.element,Rename - Refactoring , + Renames the selected element, + Category(org.eclipse.cdt.ui.category.refactoring,Refactor - C++,C/C++ Refactorings,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@15b83fa, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-06 09:48:22.677 +!MESSAGE A conflict occurred for F3: +Binding(F3, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.opendecl,Open Declaration, + Opens an editor on the selected element's declaration(s), + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@3b3ab0, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(F3, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.opendecl,Open Declaration, + Opens an editor on the selected element's declaration(s), + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@3b3ab0, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-06 09:48:22.677 +!MESSAGE A conflict occurred for ALT+CTRL+I: +Binding(ALT+CTRL+I, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.include.browser,Open Include Browser, + Open an include browser on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@55167a, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+CTRL+I, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.include.browser,Open Include Browser, + Open an include browser on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@55167a, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SESSION 2015-10-08 14:32:52.274 ----------------------------------------------- +eclipse.buildId=unknown +java.version=1.8.0_25 +java.vendor=Oracle Corporation +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US +Command-line arguments: -os win32 -ws win32 -arch x86 -data C:\temp1663\working_base_hs + +!ENTRY org.eclipse.jface 2 0 2015-10-08 14:58:59.494 +!MESSAGE Keybinding conflicts occurred. They may interfere with normal accelerator operation. +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-08 14:58:59.494 +!MESSAGE A conflict occurred for ALT+CTRL+I: +Binding(ALT+CTRL+I, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.include.browser,Open Include Browser, + Open an include browser on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@d85a18, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+CTRL+I, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.include.browser,Open Include Browser, + Open an include browser on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@d85a18, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-08 14:58:59.494 +!MESSAGE A conflict occurred for CTRL+SHIFT+T: +Binding(CTRL+SHIFT+T, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.opentype,Open Element, + Open an element in an Editor, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1575bad, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+T, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.opentype,Open Element, + Open an element in an Editor, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1575bad, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-08 14:58:59.494 +!MESSAGE A conflict occurred for CTRL+SHIFT+G: +Binding(CTRL+SHIFT+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.findrefs,References, + Searches for references to the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1e89472, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.findrefs,References, + Searches for references to the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1e89472, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-08 14:58:59.494 +!MESSAGE A conflict occurred for CTRL+G: +Binding(CTRL+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration, + Searches for declarations of the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1965d0c, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration, + Searches for declarations of the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1965d0c, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-08 14:58:59.494 +!MESSAGE A conflict occurred for ALT+CTRL+H: +Binding(ALT+CTRL+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.call.hierarchy,Open Call Hierarchy, + Opens the call hierarchy for the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@182d1bc, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+CTRL+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.call.hierarchy,Open Call Hierarchy, + Opens the call hierarchy for the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@182d1bc, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-08 14:58:59.494 +!MESSAGE A conflict occurred for CTRL+SHIFT+H: +Binding(CTRL+SHIFT+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.open.type.in.hierarchy,Open Type in Hierarchy, + Open a type in the type hierarchy view, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@8d7592, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.open.type.in.hierarchy,Open Type in Hierarchy, + Open a type in the type hierarchy view, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@8d7592, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-08 14:58:59.494 +!MESSAGE A conflict occurred for F4: +Binding(F4, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.type.hierarchy,Open Type Hierarchy, + Open a type hierarchy on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@19737f5, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(F4, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.type.hierarchy,Open Type Hierarchy, + Open a type hierarchy on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@19737f5, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-08 14:58:59.494 +!MESSAGE A conflict occurred for F3: +Binding(F3, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.opendecl,Open Declaration, + Opens an editor on the selected element's declaration(s), + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@aa73f6, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(F3, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.opendecl,Open Declaration, + Opens an editor on the selected element's declaration(s), + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@aa73f6, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-08 14:58:59.494 +!MESSAGE A conflict occurred for ALT+SHIFT+R: +Binding(ALT+SHIFT+R, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.rename.element,Rename - Refactoring , + Renames the selected element, + Category(org.eclipse.cdt.ui.category.refactoring,Refactor - C++,C/C++ Refactorings,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@15e422e, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+SHIFT+R, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.rename.element,Rename - Refactoring , + Renames the selected element, + Category(org.eclipse.cdt.ui.category.refactoring,Refactor - C++,C/C++ Refactorings,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@15e422e, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) + +!ENTRY org.eclipse.cdt.debug.core 4 1000 2015-10-08 15:24:49.427 +!MESSAGE Internal error logged from CDI Debug: +!STACK 0 +org.eclipse.cdt.debug.core.cdi.TargetInvocationException: Can't load "C:\temp1663\working_base_hs\sample_threadx\Debug\sample_threadx.elf"[] + at com.arc.cdt.debug.seecode.internal.core.cdi.Target.loadProgram(Target.java:1289) + at com.arc.cdt.debug.seecode.internal.core.cdi.Target.confirmLoaded(Target.java:945) + at com.arc.cdt.debug.seecode.internal.core.cdi.Target.getRegisterGroups(Target.java:1816) + at org.eclipse.cdt.debug.internal.core.CRegisterManager.initialize(CRegisterManager.java:138) + at org.eclipse.cdt.debug.internal.core.model.CDebugTarget.getRegisterManager(CDebugTarget.java:1808) + at org.eclipse.cdt.debug.internal.core.model.CDebugTarget.initializeRegisters(CDebugTarget.java:425) + at org.eclipse.cdt.debug.internal.core.model.CDebugTarget.initialize(CDebugTarget.java:319) + at org.eclipse.cdt.debug.internal.core.model.CDebugTarget.(CDebugTarget.java:301) + at org.eclipse.cdt.debug.core.CDIDebugModel$1.run(CDIDebugModel.java:133) + at org.eclipse.core.internal.resources.Workspace.run(Workspace.java:2313) + at org.eclipse.core.internal.resources.Workspace.run(Workspace.java:2295) + at org.eclipse.cdt.debug.core.CDIDebugModel.newDebugTarget(CDIDebugModel.java:138) + at org.eclipse.cdt.launch.internal.LocalCDILaunchDelegate.launchLocalDebugSession(LocalCDILaunchDelegate.java:213) + at org.eclipse.cdt.launch.internal.LocalCDILaunchDelegate.launchDebugger(LocalCDILaunchDelegate.java:136) + at org.eclipse.cdt.launch.internal.LocalCDILaunchDelegate.launch(LocalCDILaunchDelegate.java:80) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:885) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:739) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:1039) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1256) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) + +!ENTRY org.eclipse.cdt.debug.core 4 1000 2015-10-08 15:25:33.059 +!MESSAGE Internal error logged from CDI Debug: +!STACK 0 +org.eclipse.cdt.debug.core.cdi.TargetInvocationException: Can't load "C:\temp1663\working_base_hs\sample_threadx\Debug\sample_threadx.elf"[] + at com.arc.cdt.debug.seecode.internal.core.cdi.Target.loadProgram(Target.java:1289) + at com.arc.cdt.debug.seecode.internal.core.cdi.Target.confirmLoaded(Target.java:945) + at com.arc.cdt.debug.seecode.internal.core.cdi.Target.getRegisterGroups(Target.java:1816) + at org.eclipse.cdt.debug.internal.core.CRegisterManager.initialize(CRegisterManager.java:138) + at org.eclipse.cdt.debug.internal.core.model.CDebugTarget.getRegisterManager(CDebugTarget.java:1808) + at org.eclipse.cdt.debug.internal.core.model.CDebugTarget.initializeRegisters(CDebugTarget.java:425) + at org.eclipse.cdt.debug.internal.core.model.CDebugTarget.initialize(CDebugTarget.java:319) + at org.eclipse.cdt.debug.internal.core.model.CDebugTarget.(CDebugTarget.java:301) + at org.eclipse.cdt.debug.core.CDIDebugModel$1.run(CDIDebugModel.java:133) + at org.eclipse.core.internal.resources.Workspace.run(Workspace.java:2313) + at org.eclipse.core.internal.resources.Workspace.run(Workspace.java:2295) + at org.eclipse.cdt.debug.core.CDIDebugModel.newDebugTarget(CDIDebugModel.java:138) + at org.eclipse.cdt.launch.internal.LocalCDILaunchDelegate.launchLocalDebugSession(LocalCDILaunchDelegate.java:213) + at org.eclipse.cdt.launch.internal.LocalCDILaunchDelegate.launchDebugger(LocalCDILaunchDelegate.java:136) + at org.eclipse.cdt.launch.internal.LocalCDILaunchDelegate.launch(LocalCDILaunchDelegate.java:80) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:885) + at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:739) + at org.eclipse.debug.internal.ui.DebugUIPlugin.buildAndLaunch(DebugUIPlugin.java:1039) + at org.eclipse.debug.internal.ui.DebugUIPlugin$8.run(DebugUIPlugin.java:1256) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) +!SESSION 2015-10-09 15:41:22.142 ----------------------------------------------- +eclipse.buildId=unknown +java.version=1.8.0_25 +java.vendor=Oracle Corporation +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US +Command-line arguments: -os win32 -ws win32 -arch x86 + +!ENTRY org.eclipse.debug.ui 4 2 2015-10-09 16:32:33.850 +!MESSAGE Problems occurred when invoking code from plug-in: "org.eclipse.debug.ui". +!STACK 0 +java.lang.NullPointerException + at org.eclipse.debug.core.sourcelookup.containers.CompositeSourceContainer.getSourceContainers(CompositeSourceContainer.java:134) + at org.eclipse.cdt.debug.internal.core.sourcelookup.SourceUtils.getCompilationPath(SourceUtils.java:205) + at org.eclipse.cdt.debug.internal.core.sourcelookup.CSourceLookupDirector.getCompilationPath(CSourceLookupDirector.java:181) + at org.eclipse.cdt.debug.internal.ui.actions.RunToLineAdapter.convertPath(RunToLineAdapter.java:171) + at org.eclipse.cdt.debug.internal.ui.actions.RunToLineAdapter.canRunToLine(RunToLineAdapter.java:141) + at org.eclipse.debug.internal.ui.actions.RetargetRunToLineAction.canPerformAction(RetargetRunToLineAction.java:95) + at org.eclipse.debug.internal.ui.actions.RetargetAction.isTargetEnabled(RetargetAction.java:245) + at org.eclipse.debug.internal.ui.actions.RetargetRunToLineAction$DebugContextListener.contextActivated(RetargetRunToLineAction.java:51) + at org.eclipse.debug.internal.ui.actions.RetargetRunToLineAction$DebugContextListener.debugContextChanged(RetargetRunToLineAction.java:57) + at org.eclipse.debug.internal.ui.contexts.DebugWindowContextService$1.run(DebugWindowContextService.java:223) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.debug.internal.ui.contexts.DebugWindowContextService.notify(DebugWindowContextService.java:220) + at org.eclipse.debug.internal.ui.contexts.DebugWindowContextService.notify(DebugWindowContextService.java:195) + at org.eclipse.debug.internal.ui.contexts.DebugWindowContextService.debugContextChanged(DebugWindowContextService.java:436) + at org.eclipse.debug.ui.contexts.AbstractDebugContextProvider$1.run(AbstractDebugContextProvider.java:83) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.debug.ui.contexts.AbstractDebugContextProvider.fire(AbstractDebugContextProvider.java:80) + at org.eclipse.debug.internal.ui.views.launch.LaunchView$ContextProviderProxy.debugContextChanged(LaunchView.java:518) + at org.eclipse.debug.ui.contexts.AbstractDebugContextProvider$1.run(AbstractDebugContextProvider.java:83) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.debug.ui.contexts.AbstractDebugContextProvider.fire(AbstractDebugContextProvider.java:80) + at org.eclipse.debug.internal.ui.views.launch.LaunchView$TreeViewerContextProvider.possibleChange(LaunchView.java:404) + at org.eclipse.debug.internal.ui.views.launch.LaunchView$TreeViewerContextProvider$Visitor.visit(LaunchView.java:326) + at org.eclipse.debug.internal.ui.viewers.model.provisional.ModelDelta.doAccept(ModelDelta.java:401) + at org.eclipse.debug.internal.ui.viewers.model.provisional.ModelDelta.doAccept(ModelDelta.java:404) + at org.eclipse.debug.internal.ui.viewers.model.provisional.ModelDelta.doAccept(ModelDelta.java:404) + at org.eclipse.debug.internal.ui.viewers.model.provisional.ModelDelta.accept(ModelDelta.java:397) + at org.eclipse.debug.internal.ui.views.launch.LaunchView$TreeViewerContextProvider.modelChanged(LaunchView.java:434) + at org.eclipse.debug.internal.ui.viewers.model.TreeModelContentProvider.doModelChanged(TreeModelContentProvider.java:427) + at org.eclipse.debug.internal.ui.viewers.model.TreeModelContentProvider.access$0(TreeModelContentProvider.java:413) + at org.eclipse.debug.internal.ui.viewers.model.TreeModelContentProvider$2.run(TreeModelContentProvider.java:401) + at org.eclipse.swt.widgets.RunnableLock.run(RunnableLock.java:35) + at org.eclipse.swt.widgets.Synchronizer.runAsyncMessages(Synchronizer.java:136) + at org.eclipse.swt.widgets.Display.runAsyncMessages(Display.java:4147) + at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3764) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$9.run(PartRenderingEngine.java:1151) + at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.run(PartRenderingEngine.java:1032) + at org.eclipse.e4.ui.internal.workbench.E4Workbench.createAndRunUI(E4Workbench.java:148) + at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:636) + at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332) + at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:579) + at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:150) + at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:135) + at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:380) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:235) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:483) + at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:648) + at org.eclipse.equinox.launcher.Main.basicRun(Main.java:603) + at org.eclipse.equinox.launcher.Main.run(Main.java:1465) + +!ENTRY org.eclipse.debug.ui 4 120 2015-10-09 16:32:33.881 +!MESSAGE Error logged from Debug UI: +!STACK 0 +java.lang.NullPointerException + at org.eclipse.debug.core.sourcelookup.containers.CompositeSourceContainer.getSourceContainers(CompositeSourceContainer.java:134) + at org.eclipse.cdt.debug.internal.core.sourcelookup.SourceUtils.getCompilationPath(SourceUtils.java:205) + at org.eclipse.cdt.debug.internal.core.sourcelookup.CSourceLookupDirector.getCompilationPath(CSourceLookupDirector.java:181) + at org.eclipse.cdt.debug.internal.ui.actions.RunToLineAdapter.convertPath(RunToLineAdapter.java:171) + at org.eclipse.cdt.debug.internal.ui.actions.RunToLineAdapter.canRunToLine(RunToLineAdapter.java:141) + at org.eclipse.debug.internal.ui.actions.RetargetRunToLineAction.canPerformAction(RetargetRunToLineAction.java:95) + at org.eclipse.debug.internal.ui.actions.RetargetAction.isTargetEnabled(RetargetAction.java:245) + at org.eclipse.debug.internal.ui.actions.RetargetRunToLineAction$DebugContextListener.contextActivated(RetargetRunToLineAction.java:51) + at org.eclipse.debug.internal.ui.actions.RetargetRunToLineAction$DebugContextListener.debugContextChanged(RetargetRunToLineAction.java:57) + at org.eclipse.debug.internal.ui.contexts.DebugWindowContextService$1.run(DebugWindowContextService.java:223) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.debug.internal.ui.contexts.DebugWindowContextService.notify(DebugWindowContextService.java:220) + at org.eclipse.debug.internal.ui.contexts.DebugWindowContextService.notify(DebugWindowContextService.java:195) + at org.eclipse.debug.internal.ui.contexts.DebugWindowContextService.debugContextChanged(DebugWindowContextService.java:436) + at org.eclipse.debug.ui.contexts.AbstractDebugContextProvider$1.run(AbstractDebugContextProvider.java:83) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.debug.ui.contexts.AbstractDebugContextProvider.fire(AbstractDebugContextProvider.java:80) + at org.eclipse.debug.internal.ui.views.launch.LaunchView$ContextProviderProxy.debugContextChanged(LaunchView.java:518) + at org.eclipse.debug.ui.contexts.AbstractDebugContextProvider$1.run(AbstractDebugContextProvider.java:83) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.debug.ui.contexts.AbstractDebugContextProvider.fire(AbstractDebugContextProvider.java:80) + at org.eclipse.debug.internal.ui.views.launch.LaunchView$TreeViewerContextProvider.possibleChange(LaunchView.java:404) + at org.eclipse.debug.internal.ui.views.launch.LaunchView$TreeViewerContextProvider$Visitor.visit(LaunchView.java:326) + at org.eclipse.debug.internal.ui.viewers.model.provisional.ModelDelta.doAccept(ModelDelta.java:401) + at org.eclipse.debug.internal.ui.viewers.model.provisional.ModelDelta.doAccept(ModelDelta.java:404) + at org.eclipse.debug.internal.ui.viewers.model.provisional.ModelDelta.doAccept(ModelDelta.java:404) + at org.eclipse.debug.internal.ui.viewers.model.provisional.ModelDelta.accept(ModelDelta.java:397) + at org.eclipse.debug.internal.ui.views.launch.LaunchView$TreeViewerContextProvider.modelChanged(LaunchView.java:434) + at org.eclipse.debug.internal.ui.viewers.model.TreeModelContentProvider.doModelChanged(TreeModelContentProvider.java:427) + at org.eclipse.debug.internal.ui.viewers.model.TreeModelContentProvider.access$0(TreeModelContentProvider.java:413) + at org.eclipse.debug.internal.ui.viewers.model.TreeModelContentProvider$2.run(TreeModelContentProvider.java:401) + at org.eclipse.swt.widgets.RunnableLock.run(RunnableLock.java:35) + at org.eclipse.swt.widgets.Synchronizer.runAsyncMessages(Synchronizer.java:136) + at org.eclipse.swt.widgets.Display.runAsyncMessages(Display.java:4147) + at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3764) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$9.run(PartRenderingEngine.java:1151) + at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.run(PartRenderingEngine.java:1032) + at org.eclipse.e4.ui.internal.workbench.E4Workbench.createAndRunUI(E4Workbench.java:148) + at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:636) + at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332) + at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:579) + at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:150) + at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:135) + at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:380) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:235) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:483) + at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:648) + at org.eclipse.equinox.launcher.Main.basicRun(Main.java:603) + at org.eclipse.equinox.launcher.Main.run(Main.java:1465) + +!ENTRY org.eclipse.debug.core 4 2 2015-10-09 17:50:18.411 +!MESSAGE Problems occurred when invoking code from plug-in: "org.eclipse.debug.core". +!STACK 0 +org.eclipse.swt.SWTException: Device is disposed + at org.eclipse.swt.SWT.error(SWT.java:4441) + at org.eclipse.swt.SWT.error(SWT.java:4356) + at org.eclipse.swt.SWT.error(SWT.java:4327) + at org.eclipse.swt.widgets.Display.error(Display.java:1258) + at org.eclipse.swt.widgets.Display.getThread(Display.java:2602) + at org.eclipse.debug.internal.ui.stringsubstitution.SelectedResourceManager.getActiveWindow(SelectedResourceManager.java:239) + at org.eclipse.debug.ui.DebugUITools.getDebugContext(DebugUITools.java:229) + at org.eclipse.cdt.debug.internal.ui.actions.RemoveAllGlobalsActionDelegate.update(RemoveAllGlobalsActionDelegate.java:99) + at org.eclipse.cdt.debug.internal.ui.actions.RemoveAllGlobalsActionDelegate.handleDebugEvents(RemoveAllGlobalsActionDelegate.java:131) + at org.eclipse.debug.core.DebugPlugin$EventNotifier.run(DebugPlugin.java:1151) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.debug.core.DebugPlugin$EventNotifier.dispatch(DebugPlugin.java:1187) + at org.eclipse.debug.core.DebugPlugin$EventDispatchJob.run(DebugPlugin.java:431) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) + +!ENTRY org.eclipse.debug.core 4 125 2015-10-09 17:50:18.411 +!MESSAGE An exception occurred while dispatching debug events. +!STACK 0 +org.eclipse.swt.SWTException: Device is disposed + at org.eclipse.swt.SWT.error(SWT.java:4441) + at org.eclipse.swt.SWT.error(SWT.java:4356) + at org.eclipse.swt.SWT.error(SWT.java:4327) + at org.eclipse.swt.widgets.Display.error(Display.java:1258) + at org.eclipse.swt.widgets.Display.getThread(Display.java:2602) + at org.eclipse.debug.internal.ui.stringsubstitution.SelectedResourceManager.getActiveWindow(SelectedResourceManager.java:239) + at org.eclipse.debug.ui.DebugUITools.getDebugContext(DebugUITools.java:229) + at org.eclipse.cdt.debug.internal.ui.actions.RemoveAllGlobalsActionDelegate.update(RemoveAllGlobalsActionDelegate.java:99) + at org.eclipse.cdt.debug.internal.ui.actions.RemoveAllGlobalsActionDelegate.handleDebugEvents(RemoveAllGlobalsActionDelegate.java:131) + at org.eclipse.debug.core.DebugPlugin$EventNotifier.run(DebugPlugin.java:1151) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.debug.core.DebugPlugin$EventNotifier.dispatch(DebugPlugin.java:1187) + at org.eclipse.debug.core.DebugPlugin$EventDispatchJob.run(DebugPlugin.java:431) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) +!SESSION 2015-10-12 11:12:05.433 ----------------------------------------------- +eclipse.buildId=unknown +java.version=1.8.0_25 +java.vendor=Oracle Corporation +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US +Command-line arguments: -os win32 -ws win32 -arch x86 + +!ENTRY org.eclipse.jface 2 0 2015-10-12 11:45:51.753 +!MESSAGE Keybinding conflicts occurred. They may interfere with normal accelerator operation. +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-12 11:45:51.753 +!MESSAGE A conflict occurred for CTRL+SHIFT+T: +Binding(CTRL+SHIFT+T, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.opentype,Open Element, + Open an element in an Editor, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1a045bd, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+T, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.opentype,Open Element, + Open an element in an Editor, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1a045bd, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-12 11:45:51.753 +!MESSAGE A conflict occurred for F3: +Binding(F3, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.opendecl,Open Declaration, + Opens an editor on the selected element's declaration(s), + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@fada78, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(F3, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.opendecl,Open Declaration, + Opens an editor on the selected element's declaration(s), + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@fada78, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-12 11:45:51.753 +!MESSAGE A conflict occurred for F4: +Binding(F4, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.type.hierarchy,Open Type Hierarchy, + Open a type hierarchy on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@cc9674, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(F4, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.type.hierarchy,Open Type Hierarchy, + Open a type hierarchy on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@cc9674, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-12 11:45:51.753 +!MESSAGE A conflict occurred for ALT+SHIFT+R: +Binding(ALT+SHIFT+R, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.rename.element,Rename - Refactoring , + Renames the selected element, + Category(org.eclipse.cdt.ui.category.refactoring,Refactor - C++,C/C++ Refactorings,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@120387e, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+SHIFT+R, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.rename.element,Rename - Refactoring , + Renames the selected element, + Category(org.eclipse.cdt.ui.category.refactoring,Refactor - C++,C/C++ Refactorings,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@120387e, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-12 11:45:51.753 +!MESSAGE A conflict occurred for CTRL+SHIFT+G: +Binding(CTRL+SHIFT+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.findrefs,References, + Searches for references to the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@d8100a, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.findrefs,References, + Searches for references to the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@d8100a, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-12 11:45:51.753 +!MESSAGE A conflict occurred for CTRL+G: +Binding(CTRL+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration, + Searches for declarations of the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@d925b3, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration, + Searches for declarations of the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@d925b3, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-12 11:45:51.753 +!MESSAGE A conflict occurred for ALT+CTRL+H: +Binding(ALT+CTRL+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.call.hierarchy,Open Call Hierarchy, + Opens the call hierarchy for the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@d46f2a, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+CTRL+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.call.hierarchy,Open Call Hierarchy, + Opens the call hierarchy for the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@d46f2a, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-12 11:45:51.753 +!MESSAGE A conflict occurred for CTRL+SHIFT+H: +Binding(CTRL+SHIFT+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.open.type.in.hierarchy,Open Type in Hierarchy, + Open a type in the type hierarchy view, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@754906, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.open.type.in.hierarchy,Open Type in Hierarchy, + Open a type in the type hierarchy view, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@754906, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-12 11:45:51.753 +!MESSAGE A conflict occurred for ALT+CTRL+I: +Binding(ALT+CTRL+I, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.include.browser,Open Include Browser, + Open an include browser on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@db5482, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+CTRL+I, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.include.browser,Open Include Browser, + Open an include browser on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@db5482, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) + +!ENTRY org.eclipse.debug.core 4 2 2015-10-12 13:31:22.583 +!MESSAGE Problems occurred when invoking code from plug-in: "org.eclipse.debug.core". +!STACK 0 +org.eclipse.swt.SWTException: Device is disposed + at org.eclipse.swt.SWT.error(SWT.java:4441) + at org.eclipse.swt.SWT.error(SWT.java:4356) + at org.eclipse.swt.SWT.error(SWT.java:4327) + at org.eclipse.swt.widgets.Display.error(Display.java:1258) + at org.eclipse.swt.widgets.Display.getThread(Display.java:2602) + at org.eclipse.debug.internal.ui.stringsubstitution.SelectedResourceManager.getActiveWindow(SelectedResourceManager.java:239) + at org.eclipse.debug.ui.DebugUITools.getDebugContext(DebugUITools.java:229) + at org.eclipse.cdt.debug.internal.ui.actions.RemoveAllGlobalsActionDelegate.update(RemoveAllGlobalsActionDelegate.java:99) + at org.eclipse.cdt.debug.internal.ui.actions.RemoveAllGlobalsActionDelegate.handleDebugEvents(RemoveAllGlobalsActionDelegate.java:131) + at org.eclipse.debug.core.DebugPlugin$EventNotifier.run(DebugPlugin.java:1151) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.debug.core.DebugPlugin$EventNotifier.dispatch(DebugPlugin.java:1187) + at org.eclipse.debug.core.DebugPlugin$EventDispatchJob.run(DebugPlugin.java:431) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) + +!ENTRY org.eclipse.debug.core 4 125 2015-10-12 13:31:22.583 +!MESSAGE An exception occurred while dispatching debug events. +!STACK 0 +org.eclipse.swt.SWTException: Device is disposed + at org.eclipse.swt.SWT.error(SWT.java:4441) + at org.eclipse.swt.SWT.error(SWT.java:4356) + at org.eclipse.swt.SWT.error(SWT.java:4327) + at org.eclipse.swt.widgets.Display.error(Display.java:1258) + at org.eclipse.swt.widgets.Display.getThread(Display.java:2602) + at org.eclipse.debug.internal.ui.stringsubstitution.SelectedResourceManager.getActiveWindow(SelectedResourceManager.java:239) + at org.eclipse.debug.ui.DebugUITools.getDebugContext(DebugUITools.java:229) + at org.eclipse.cdt.debug.internal.ui.actions.RemoveAllGlobalsActionDelegate.update(RemoveAllGlobalsActionDelegate.java:99) + at org.eclipse.cdt.debug.internal.ui.actions.RemoveAllGlobalsActionDelegate.handleDebugEvents(RemoveAllGlobalsActionDelegate.java:131) + at org.eclipse.debug.core.DebugPlugin$EventNotifier.run(DebugPlugin.java:1151) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.debug.core.DebugPlugin$EventNotifier.dispatch(DebugPlugin.java:1187) + at org.eclipse.debug.core.DebugPlugin$EventDispatchJob.run(DebugPlugin.java:431) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:54) +!SESSION 2015-10-12 13:33:52.888 ----------------------------------------------- +eclipse.buildId=unknown +java.version=1.8.0_25 +java.vendor=Oracle Corporation +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US +Command-line arguments: -os win32 -ws win32 -arch x86 + +!ENTRY org.eclipse.jface 2 0 2015-10-12 13:34:34.005 +!MESSAGE Keybinding conflicts occurred. They may interfere with normal accelerator operation. +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-12 13:34:34.005 +!MESSAGE A conflict occurred for F3: +Binding(F3, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.opendecl,Open Declaration, + Opens an editor on the selected element's declaration(s), + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@906078, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(F3, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.opendecl,Open Declaration, + Opens an editor on the selected element's declaration(s), + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@906078, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-12 13:34:34.005 +!MESSAGE A conflict occurred for CTRL+SHIFT+G: +Binding(CTRL+SHIFT+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.findrefs,References, + Searches for references to the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1d5c7f6, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.findrefs,References, + Searches for references to the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1d5c7f6, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-12 13:34:34.005 +!MESSAGE A conflict occurred for CTRL+G: +Binding(CTRL+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration, + Searches for declarations of the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@124ab90, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration, + Searches for declarations of the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@124ab90, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-12 13:34:34.005 +!MESSAGE A conflict occurred for ALT+CTRL+H: +Binding(ALT+CTRL+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.call.hierarchy,Open Call Hierarchy, + Opens the call hierarchy for the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@ef1934, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+CTRL+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.call.hierarchy,Open Call Hierarchy, + Opens the call hierarchy for the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@ef1934, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-12 13:34:34.005 +!MESSAGE A conflict occurred for CTRL+SHIFT+H: +Binding(CTRL+SHIFT+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.open.type.in.hierarchy,Open Type in Hierarchy, + Open a type in the type hierarchy view, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@11522f1, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.open.type.in.hierarchy,Open Type in Hierarchy, + Open a type in the type hierarchy view, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@11522f1, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-12 13:34:34.005 +!MESSAGE A conflict occurred for F4: +Binding(F4, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.type.hierarchy,Open Type Hierarchy, + Open a type hierarchy on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@5eba52, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(F4, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.type.hierarchy,Open Type Hierarchy, + Open a type hierarchy on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@5eba52, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-12 13:34:34.005 +!MESSAGE A conflict occurred for ALT+SHIFT+R: +Binding(ALT+SHIFT+R, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.rename.element,Rename - Refactoring , + Renames the selected element, + Category(org.eclipse.cdt.ui.category.refactoring,Refactor - C++,C/C++ Refactorings,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@34f8e2, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+SHIFT+R, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.rename.element,Rename - Refactoring , + Renames the selected element, + Category(org.eclipse.cdt.ui.category.refactoring,Refactor - C++,C/C++ Refactorings,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@34f8e2, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-12 13:34:34.005 +!MESSAGE A conflict occurred for CTRL+SHIFT+T: +Binding(CTRL+SHIFT+T, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.opentype,Open Element, + Open an element in an Editor, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@2a7429, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+T, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.opentype,Open Element, + Open an element in an Editor, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@2a7429, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2015-10-12 13:34:34.005 +!MESSAGE A conflict occurred for ALT+CTRL+I: +Binding(ALT+CTRL+I, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.include.browser,Open Include Browser, + Open an include browser on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@a8c837, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+CTRL+I, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.include.browser,Open Include Browser, + Open an include browser on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@a8c837, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SESSION 2017-04-05 21:13:21.705 ----------------------------------------------- +eclipse.buildId=unknown +java.version=1.8.0_25 +java.vendor=Oracle Corporation +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US +Command-line arguments: -os win32 -ws win32 -arch x86 -data C:\arc_hs_smp + +!ENTRY org.eclipse.e4.ui.workbench 2 0 2017-04-05 21:13:25.522 +!MESSAGE Could not run processor +!STACK 0 +org.eclipse.e4.core.di.InjectionException: java.lang.NullPointerException + at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:62) + at org.eclipse.e4.core.internal.di.InjectorImpl.invokeUsingClass(InjectorImpl.java:247) + at org.eclipse.e4.core.internal.di.InjectorImpl.invoke(InjectorImpl.java:225) + at org.eclipse.e4.core.contexts.ContextInjectionFactory.invoke(ContextInjectionFactory.java:107) + at org.eclipse.e4.ui.internal.workbench.ModelAssembler.runProcessor(ModelAssembler.java:259) + at org.eclipse.e4.ui.internal.workbench.ModelAssembler.runProcessors(ModelAssembler.java:221) + at org.eclipse.e4.ui.internal.workbench.ModelAssembler.processModel(ModelAssembler.java:85) + at org.eclipse.e4.ui.internal.workbench.ResourceHandler.loadMostRecentModel(ResourceHandler.java:265) + at org.eclipse.e4.ui.internal.workbench.swt.E4Application.loadApplicationModel(E4Application.java:435) + at org.eclipse.e4.ui.internal.workbench.swt.E4Application.createE4Workbench(E4Application.java:260) + at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:601) + at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:332) + at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:579) + at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:150) + at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:135) + at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:382) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:236) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:483) + at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:648) + at org.eclipse.equinox.launcher.Main.basicRun(Main.java:603) + at org.eclipse.equinox.launcher.Main.run(Main.java:1465) +Caused by: java.lang.NullPointerException + at org.eclipse.cdt.launchbar.ui.internal.LaunchBarInjector.injectLaunchBar(LaunchBarInjector.java:109) + at org.eclipse.cdt.launchbar.ui.internal.LaunchBarInjector.injectIntoAll(LaunchBarInjector.java:84) + at org.eclipse.cdt.launchbar.ui.internal.LaunchBarInjector.execute(LaunchBarInjector.java:46) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:483) + at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:55) + ... 26 more +!SESSION 2017-04-12 14:48:09.151 ----------------------------------------------- +eclipse.buildId=unknown +java.version=1.8.0_25 +java.vendor=Oracle Corporation +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US +Command-line arguments: -os win32 -ws win32 -arch x86 + +!ENTRY org.eclipse.core.resources 2 10035 2017-04-12 14:48:12.987 +!MESSAGE The workspace exited with unsaved changes in the previous session; refreshing workspace to recover changes. +!SESSION 2017-04-13 18:52:12.107 ----------------------------------------------- +eclipse.buildId=unknown +java.version=1.8.0_25 +java.vendor=Oracle Corporation +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US +Command-line arguments: -os win32 -ws win32 -arch x86 + +!ENTRY org.eclipse.jface 2 0 2017-04-13 18:59:00.860 +!MESSAGE Keybinding conflicts occurred. They may interfere with normal accelerator operation. +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-13 18:59:00.860 +!MESSAGE A conflict occurred for ALT+SHIFT+R: +Binding(ALT+SHIFT+R, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.rename.element,Rename - Refactoring , + Renames the selected element, + Category(org.eclipse.cdt.ui.category.refactoring,Refactor - C++,C/C++ Refactorings,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1e23e94, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+SHIFT+R, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.rename.element,Rename - Refactoring , + Renames the selected element, + Category(org.eclipse.cdt.ui.category.refactoring,Refactor - C++,C/C++ Refactorings,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1e23e94, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-13 18:59:00.860 +!MESSAGE A conflict occurred for CTRL+SHIFT+T: +Binding(CTRL+SHIFT+T, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.opentype,Open Element, + Open an element in an Editor, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1c78556, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+T, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.opentype,Open Element, + Open an element in an Editor, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1c78556, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-13 18:59:00.860 +!MESSAGE A conflict occurred for F4: +Binding(F4, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.type.hierarchy,Open Type Hierarchy, + Open a type hierarchy on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1134e01, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(F4, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.type.hierarchy,Open Type Hierarchy, + Open a type hierarchy on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1134e01, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-13 18:59:00.860 +!MESSAGE A conflict occurred for ALT+CTRL+I: +Binding(ALT+CTRL+I, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.include.browser,Open Include Browser, + Open an include browser on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@d28106, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+CTRL+I, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.include.browser,Open Include Browser, + Open an include browser on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@d28106, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-13 18:59:00.860 +!MESSAGE A conflict occurred for CTRL+SHIFT+G: +Binding(CTRL+SHIFT+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.findrefs,References, + Searches for references to the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@3c1b56, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.findrefs,References, + Searches for references to the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@3c1b56, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-13 18:59:00.861 +!MESSAGE A conflict occurred for CTRL+G: +Binding(CTRL+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration, + Searches for declarations of the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1b8ce72, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration, + Searches for declarations of the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1b8ce72, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-13 18:59:00.861 +!MESSAGE A conflict occurred for ALT+CTRL+H: +Binding(ALT+CTRL+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.call.hierarchy,Open Call Hierarchy, + Opens the call hierarchy for the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@e4eb42, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+CTRL+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.call.hierarchy,Open Call Hierarchy, + Opens the call hierarchy for the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@e4eb42, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-13 18:59:00.861 +!MESSAGE A conflict occurred for CTRL+SHIFT+H: +Binding(CTRL+SHIFT+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.open.type.in.hierarchy,Open Type in Hierarchy, + Open a type in the type hierarchy view, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@388769, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.open.type.in.hierarchy,Open Type in Hierarchy, + Open a type in the type hierarchy view, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@388769, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-13 18:59:00.861 +!MESSAGE A conflict occurred for F3: +Binding(F3, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.opendecl,Open Declaration, + Opens an editor on the selected element's declaration(s), + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@54cdd3, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(F3, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.opendecl,Open Declaration, + Opens an editor on the selected element's declaration(s), + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@54cdd3, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SESSION 2017-04-14 09:52:07.324 ----------------------------------------------- +eclipse.buildId=unknown +java.version=1.8.0_25 +java.vendor=Oracle Corporation +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US +Command-line arguments: -os win32 -ws win32 -arch x86 + +!ENTRY org.eclipse.jface 2 0 2017-04-14 10:30:59.237 +!MESSAGE Keybinding conflicts occurred. They may interfere with normal accelerator operation. +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-14 10:30:59.237 +!MESSAGE A conflict occurred for F3: +Binding(F3, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.opendecl,Open Declaration, + Opens an editor on the selected element's declaration(s), + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@d6769b, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(F3, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.opendecl,Open Declaration, + Opens an editor on the selected element's declaration(s), + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@d6769b, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-14 10:30:59.237 +!MESSAGE A conflict occurred for ALT+CTRL+I: +Binding(ALT+CTRL+I, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.include.browser,Open Include Browser, + Open an include browser on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1e2377, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+CTRL+I, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.include.browser,Open Include Browser, + Open an include browser on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1e2377, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-14 10:30:59.237 +!MESSAGE A conflict occurred for CTRL+SHIFT+T: +Binding(CTRL+SHIFT+T, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.opentype,Open Element, + Open an element in an Editor, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@ccb9f0, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+T, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.opentype,Open Element, + Open an element in an Editor, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@ccb9f0, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-14 10:30:59.237 +!MESSAGE A conflict occurred for F4: +Binding(F4, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.type.hierarchy,Open Type Hierarchy, + Open a type hierarchy on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@a2eca6, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(F4, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.type.hierarchy,Open Type Hierarchy, + Open a type hierarchy on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@a2eca6, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-14 10:30:59.237 +!MESSAGE A conflict occurred for ALT+SHIFT+R: +Binding(ALT+SHIFT+R, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.rename.element,Rename - Refactoring , + Renames the selected element, + Category(org.eclipse.cdt.ui.category.refactoring,Refactor - C++,C/C++ Refactorings,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1ef3847, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+SHIFT+R, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.rename.element,Rename - Refactoring , + Renames the selected element, + Category(org.eclipse.cdt.ui.category.refactoring,Refactor - C++,C/C++ Refactorings,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1ef3847, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-14 10:30:59.237 +!MESSAGE A conflict occurred for CTRL+SHIFT+G: +Binding(CTRL+SHIFT+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.findrefs,References, + Searches for references to the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@33bb96, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.findrefs,References, + Searches for references to the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@33bb96, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-14 10:30:59.237 +!MESSAGE A conflict occurred for CTRL+G: +Binding(CTRL+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration, + Searches for declarations of the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@19b8759, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration, + Searches for declarations of the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@19b8759, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-14 10:30:59.237 +!MESSAGE A conflict occurred for ALT+CTRL+H: +Binding(ALT+CTRL+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.call.hierarchy,Open Call Hierarchy, + Opens the call hierarchy for the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@8d8f50, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+CTRL+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.call.hierarchy,Open Call Hierarchy, + Opens the call hierarchy for the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@8d8f50, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-14 10:30:59.237 +!MESSAGE A conflict occurred for CTRL+SHIFT+H: +Binding(CTRL+SHIFT+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.open.type.in.hierarchy,Open Type in Hierarchy, + Open a type in the type hierarchy view, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@30ab46, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.open.type.in.hierarchy,Open Type in Hierarchy, + Open a type in the type hierarchy view, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@30ab46, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SESSION 2017-04-14 15:41:40.975 ----------------------------------------------- +eclipse.buildId=unknown +java.version=1.8.0_25 +java.vendor=Oracle Corporation +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US +Command-line arguments: -os win32 -ws win32 -arch x86 + +!ENTRY org.eclipse.jface 2 0 2017-04-14 15:42:42.858 +!MESSAGE Keybinding conflicts occurred. They may interfere with normal accelerator operation. +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-14 15:42:42.858 +!MESSAGE A conflict occurred for CTRL+SHIFT+T: +Binding(CTRL+SHIFT+T, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.opentype,Open Element, + Open an element in an Editor, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@98adb2, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+T, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.opentype,Open Element, + Open an element in an Editor, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@98adb2, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-14 15:42:42.858 +!MESSAGE A conflict occurred for F4: +Binding(F4, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.type.hierarchy,Open Type Hierarchy, + Open a type hierarchy on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@3d0ff8, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(F4, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.type.hierarchy,Open Type Hierarchy, + Open a type hierarchy on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@3d0ff8, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-14 15:42:42.858 +!MESSAGE A conflict occurred for F3: +Binding(F3, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.opendecl,Open Declaration, + Opens an editor on the selected element's declaration(s), + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@b73a92, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(F3, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.opendecl,Open Declaration, + Opens an editor on the selected element's declaration(s), + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@b73a92, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-14 15:42:42.858 +!MESSAGE A conflict occurred for ALT+SHIFT+R: +Binding(ALT+SHIFT+R, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.rename.element,Rename - Refactoring , + Renames the selected element, + Category(org.eclipse.cdt.ui.category.refactoring,Refactor - C++,C/C++ Refactorings,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@13faf1d, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+SHIFT+R, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.rename.element,Rename - Refactoring , + Renames the selected element, + Category(org.eclipse.cdt.ui.category.refactoring,Refactor - C++,C/C++ Refactorings,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@13faf1d, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-14 15:42:42.858 +!MESSAGE A conflict occurred for ALT+CTRL+I: +Binding(ALT+CTRL+I, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.include.browser,Open Include Browser, + Open an include browser on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@17835, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+CTRL+I, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.include.browser,Open Include Browser, + Open an include browser on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@17835, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-14 15:42:42.858 +!MESSAGE A conflict occurred for CTRL+SHIFT+G: +Binding(CTRL+SHIFT+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.findrefs,References, + Searches for references to the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@7f3c2, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.findrefs,References, + Searches for references to the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@7f3c2, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-14 15:42:42.858 +!MESSAGE A conflict occurred for CTRL+G: +Binding(CTRL+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration, + Searches for declarations of the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@14134ba, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration, + Searches for declarations of the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@14134ba, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-14 15:42:42.859 +!MESSAGE A conflict occurred for ALT+CTRL+H: +Binding(ALT+CTRL+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.call.hierarchy,Open Call Hierarchy, + Opens the call hierarchy for the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1063e08, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+CTRL+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.call.hierarchy,Open Call Hierarchy, + Opens the call hierarchy for the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1063e08, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-14 15:42:42.859 +!MESSAGE A conflict occurred for CTRL+SHIFT+H: +Binding(CTRL+SHIFT+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.open.type.in.hierarchy,Open Type in Hierarchy, + Open a type in the type hierarchy view, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@fb240d, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.open.type.in.hierarchy,Open Type in Hierarchy, + Open a type in the type hierarchy view, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@fb240d, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SESSION 2017-04-14 16:25:38.323 ----------------------------------------------- +eclipse.buildId=unknown +java.version=1.8.0_25 +java.vendor=Oracle Corporation +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US +Command-line arguments: -os win32 -ws win32 -arch x86 -data C:\arc_hs_smp + +!ENTRY org.eclipse.jface 2 0 2017-04-14 16:43:54.200 +!MESSAGE Keybinding conflicts occurred. They may interfere with normal accelerator operation. +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-14 16:43:54.200 +!MESSAGE A conflict occurred for ALT+CTRL+I: +Binding(ALT+CTRL+I, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.include.browser,Open Include Browser, + Open an include browser on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@10dc104, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+CTRL+I, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.include.browser,Open Include Browser, + Open an include browser on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@10dc104, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-14 16:43:54.200 +!MESSAGE A conflict occurred for F3: +Binding(F3, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.opendecl,Open Declaration, + Opens an editor on the selected element's declaration(s), + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@110ee00, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(F3, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.opendecl,Open Declaration, + Opens an editor on the selected element's declaration(s), + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@110ee00, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-14 16:43:54.200 +!MESSAGE A conflict occurred for F4: +Binding(F4, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.type.hierarchy,Open Type Hierarchy, + Open a type hierarchy on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@6a5b35, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(F4, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.type.hierarchy,Open Type Hierarchy, + Open a type hierarchy on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@6a5b35, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-14 16:43:54.200 +!MESSAGE A conflict occurred for CTRL+SHIFT+T: +Binding(CTRL+SHIFT+T, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.opentype,Open Element, + Open an element in an Editor, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@656a25, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+T, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.opentype,Open Element, + Open an element in an Editor, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@656a25, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-14 16:43:54.200 +!MESSAGE A conflict occurred for ALT+SHIFT+R: +Binding(ALT+SHIFT+R, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.rename.element,Rename - Refactoring , + Renames the selected element, + Category(org.eclipse.cdt.ui.category.refactoring,Refactor - C++,C/C++ Refactorings,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@143800c, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+SHIFT+R, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.rename.element,Rename - Refactoring , + Renames the selected element, + Category(org.eclipse.cdt.ui.category.refactoring,Refactor - C++,C/C++ Refactorings,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@143800c, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-14 16:43:54.200 +!MESSAGE A conflict occurred for CTRL+SHIFT+G: +Binding(CTRL+SHIFT+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.findrefs,References, + Searches for references to the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1fb044a, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.findrefs,References, + Searches for references to the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1fb044a, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-14 16:43:54.200 +!MESSAGE A conflict occurred for CTRL+G: +Binding(CTRL+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration, + Searches for declarations of the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@12c5533, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration, + Searches for declarations of the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@12c5533, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-14 16:43:54.200 +!MESSAGE A conflict occurred for ALT+CTRL+H: +Binding(ALT+CTRL+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.call.hierarchy,Open Call Hierarchy, + Opens the call hierarchy for the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@453e71, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+CTRL+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.call.hierarchy,Open Call Hierarchy, + Opens the call hierarchy for the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@453e71, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-14 16:43:54.200 +!MESSAGE A conflict occurred for CTRL+SHIFT+H: +Binding(CTRL+SHIFT+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.open.type.in.hierarchy,Open Type in Hierarchy, + Open a type in the type hierarchy view, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@14f8b15, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.open.type.in.hierarchy,Open Type in Hierarchy, + Open a type in the type hierarchy view, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@14f8b15, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SESSION 2017-04-17 11:28:10.366 ----------------------------------------------- +eclipse.buildId=unknown +java.version=1.8.0_25 +java.vendor=Oracle Corporation +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US +Command-line arguments: -os win32 -ws win32 -arch x86 + +!ENTRY org.eclipse.jface 2 0 2017-04-17 14:06:33.920 +!MESSAGE Keybinding conflicts occurred. They may interfere with normal accelerator operation. +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-17 14:06:33.920 +!MESSAGE A conflict occurred for F4: +Binding(F4, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.type.hierarchy,Open Type Hierarchy, + Open a type hierarchy on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@32db14, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(F4, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.type.hierarchy,Open Type Hierarchy, + Open a type hierarchy on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@32db14, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-17 14:06:33.920 +!MESSAGE A conflict occurred for ALT+SHIFT+R: +Binding(ALT+SHIFT+R, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.rename.element,Rename - Refactoring , + Renames the selected element, + Category(org.eclipse.cdt.ui.category.refactoring,Refactor - C++,C/C++ Refactorings,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@87903a, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+SHIFT+R, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.text.rename.element,Rename - Refactoring , + Renames the selected element, + Category(org.eclipse.cdt.ui.category.refactoring,Refactor - C++,C/C++ Refactorings,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@87903a, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-17 14:06:33.920 +!MESSAGE A conflict occurred for CTRL+SHIFT+T: +Binding(CTRL+SHIFT+T, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.opentype,Open Element, + Open an element in an Editor, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@3a9ceb, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+T, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.opentype,Open Element, + Open an element in an Editor, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@3a9ceb, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-17 14:06:33.920 +!MESSAGE A conflict occurred for CTRL+SHIFT+G: +Binding(CTRL+SHIFT+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.findrefs,References, + Searches for references to the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1148f1, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.findrefs,References, + Searches for references to the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@1148f1, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-17 14:06:33.920 +!MESSAGE A conflict occurred for CTRL+G: +Binding(CTRL+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration, + Searches for declarations of the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@49df5c, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+G, + ParameterizedCommand(Command(org.eclipse.cdt.ui.search.finddecl,Declaration, + Searches for declarations of the selected element in the workspace, + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@49df5c, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-17 14:06:33.920 +!MESSAGE A conflict occurred for ALT+CTRL+H: +Binding(ALT+CTRL+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.call.hierarchy,Open Call Hierarchy, + Opens the call hierarchy for the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@989af, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+CTRL+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.call.hierarchy,Open Call Hierarchy, + Opens the call hierarchy for the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@989af, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-17 14:06:33.920 +!MESSAGE A conflict occurred for CTRL+SHIFT+H: +Binding(CTRL+SHIFT+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.open.type.in.hierarchy,Open Type in Hierarchy, + Open a type in the type hierarchy view, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@be88c1, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(CTRL+SHIFT+H, + ParameterizedCommand(Command(org.eclipse.cdt.ui.navigate.open.type.in.hierarchy,Open Type in Hierarchy, + Open a type in the type hierarchy view, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@be88c1, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-17 14:06:33.920 +!MESSAGE A conflict occurred for F3: +Binding(F3, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.opendecl,Open Declaration, + Opens an editor on the selected element's declaration(s), + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@540be7, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(F3, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.opendecl,Open Declaration, + Opens an editor on the selected element's declaration(s), + Category(org.eclipse.cdt.ui.category.source,C/C++ Source,C/C++ Source Actions,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@540be7, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SUBENTRY 1 org.eclipse.jface 2 0 2017-04-17 14:06:33.920 +!MESSAGE A conflict occurred for ALT+CTRL+I: +Binding(ALT+CTRL+I, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.include.browser,Open Include Browser, + Open an include browser on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@2d850e, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cEditorScope,,,system) +Binding(ALT+CTRL+I, + ParameterizedCommand(Command(org.eclipse.cdt.ui.edit.open.include.browser,Open Include Browser, + Open an include browser on the selected element, + Category(org.eclipse.ui.category.navigate,Navigate,null,true), + org.eclipse.ui.internal.WorkbenchHandlerServiceHandler@2d850e, + ,,true),null), + org.eclipse.ui.defaultAcceleratorConfiguration, + org.eclipse.cdt.ui.cViewScope,,,system) +!SESSION 2017-04-17 16:44:11.304 ----------------------------------------------- +eclipse.buildId=unknown +java.version=1.8.0_25 +java.vendor=Oracle Corporation +BootLoader constants: OS=win32, ARCH=x86, WS=win32, NL=en_US +Command-line arguments: -os win32 -ws win32 -arch x86 -data C:\arc_hs_smp\for_intel_04-17-17 + +!ENTRY org.eclipse.core.resources 2 10035 2017-04-17 16:44:13.326 +!MESSAGE The workspace exited with unsaved changes in the previous session; refreshing workspace to recover changes. +!SESSION 2020-06-18 12:56:44.148 ----------------------------------------------- +eclipse.buildId=unknown +java.fullversion=1.8.0_212-b03 +JRE 1.8.0 Windows 8 amd64-64-Bit Compressed References 20190417_339 (JIT enabled, AOT enabled) +OpenJ9 - bad1d4d06 +OMR - 4a4278e6 +JCL - 5590c4f818 based on jdk8u212-b03 +BootLoader constants: OS=win32, ARCH=x86_64, WS=win32, NL=en_US +Command-line arguments: -os win32 -ws win32 -arch x86_64 + +!ENTRY org.eclipse.core.resources 4 567 2020-06-18 12:56:55.661 +!MESSAGE Workspace restored, but some problems occurred. +!SUBENTRY 1 org.eclipse.core.resources 4 567 2020-06-18 12:56:55.661 +!MESSAGE Could not read metadata for 'demo_threadx'. +!STACK 1 +org.eclipse.core.internal.resources.ResourceException: The project description file (.project) for 'demo_threadx' is missing. This file contains important information about the project. The project will not function properly until this file is restored. + at org.eclipse.core.internal.localstore.FileSystemResourceManager.read(FileSystemResourceManager.java:907) + at org.eclipse.core.internal.resources.SaveManager.restoreMetaInfo(SaveManager.java:904) + at org.eclipse.core.internal.resources.SaveManager.restoreMetaInfo(SaveManager.java:884) + at org.eclipse.core.internal.resources.SaveManager.restore(SaveManager.java:735) + at org.eclipse.core.internal.resources.SaveManager.startup(SaveManager.java:1587) + at org.eclipse.core.internal.resources.Workspace.startup(Workspace.java:2399) + at org.eclipse.core.internal.resources.Workspace.open(Workspace.java:2156) + at org.eclipse.core.resources.ResourcesPlugin.start(ResourcesPlugin.java:464) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.sources.SingleSourcePackage.loadClass(SingleSourcePackage.java:36) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:419) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:139) + at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:388) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:243) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:498) + at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:673) + at org.eclipse.equinox.launcher.Main.basicRun(Main.java:610) + at org.eclipse.equinox.launcher.Main.run(Main.java:1519) +!SUBENTRY 2 org.eclipse.core.resources 4 567 2020-06-18 12:56:55.663 +!MESSAGE The project description file (.project) for 'demo_threadx' is missing. This file contains important information about the project. The project will not function properly until this file is restored. + +!ENTRY org.eclipse.ui 4 4 2020-06-18 12:57:01.938 +!MESSAGE Unable to create part +!SUBENTRY 1 org.eclipse.core.filebuffers 4 0 2020-06-18 12:57:01.938 +!MESSAGE Cannot determine URI for '/sample_threadx/arc.c'. +!STACK 1 +org.eclipse.core.runtime.CoreException: Cannot determine URI for '/sample_threadx/arc.c'. + at org.eclipse.core.internal.filebuffers.ResourceFileBuffer.create(ResourceFileBuffer.java:239) + at org.eclipse.core.internal.filebuffers.TextFileBufferManager.connect(TextFileBufferManager.java:112) + at org.eclipse.ui.editors.text.TextFileDocumentProvider.createFileInfo(TextFileDocumentProvider.java:560) + at org.eclipse.cdt.internal.ui.editor.CDocumentProvider.createFileInfo(CDocumentProvider.java:786) + at org.eclipse.ui.editors.text.TextFileDocumentProvider.connect(TextFileDocumentProvider.java:478) + at org.eclipse.cdt.internal.ui.editor.CDocumentProvider.connect(CDocumentProvider.java:718) + at org.eclipse.ui.texteditor.AbstractTextEditor.doSetInput(AbstractTextEditor.java:4178) + at org.eclipse.ui.texteditor.StatusTextEditor.doSetInput(StatusTextEditor.java:229) + at org.eclipse.ui.texteditor.AbstractDecoratedTextEditor.doSetInput(AbstractDecoratedTextEditor.java:1466) + at org.eclipse.ui.editors.text.TextEditor.doSetInput(TextEditor.java:150) + at org.eclipse.cdt.internal.ui.editor.CEditor.internalDoSetInput(CEditor.java:1368) + at org.eclipse.cdt.internal.ui.editor.CEditor.doSetInput(CEditor.java:1333) + at org.eclipse.ui.texteditor.AbstractTextEditor$5.run(AbstractTextEditor.java:3154) + at org.eclipse.ui.internal.WorkbenchWindow.run(WorkbenchWindow.java:2126) + at org.eclipse.ui.texteditor.AbstractTextEditor.internalInit(AbstractTextEditor.java:3172) + at org.eclipse.ui.texteditor.AbstractTextEditor.init(AbstractTextEditor.java:3197) + at org.eclipse.ui.internal.EditorReference.initialize(EditorReference.java:362) + at org.eclipse.ui.internal.e4.compatibility.CompatibilityPart.create(CompatibilityPart.java:318) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:498) + at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:55) + at org.eclipse.e4.core.internal.di.InjectorImpl.processAnnotated(InjectorImpl.java:966) + at org.eclipse.e4.core.internal.di.InjectorImpl.processAnnotated(InjectorImpl.java:931) + at org.eclipse.e4.core.internal.di.InjectorImpl.inject(InjectorImpl.java:151) + at org.eclipse.e4.core.internal.di.InjectorImpl.internalMake(InjectorImpl.java:375) + at org.eclipse.e4.core.internal.di.InjectorImpl.make(InjectorImpl.java:294) + at org.eclipse.e4.core.contexts.ContextInjectionFactory.make(ContextInjectionFactory.java:162) + at org.eclipse.e4.ui.internal.workbench.ReflectionContributionFactory.createFromBundle(ReflectionContributionFactory.java:105) + at org.eclipse.e4.ui.internal.workbench.ReflectionContributionFactory.doCreate(ReflectionContributionFactory.java:74) + at org.eclipse.e4.ui.internal.workbench.ReflectionContributionFactory.create(ReflectionContributionFactory.java:56) + at org.eclipse.e4.ui.workbench.renderers.swt.ContributedPartRenderer.createWidget(ContributedPartRenderer.java:129) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createWidget(PartRenderingEngine.java:975) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:651) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:757) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$0(PartRenderingEngine.java:728) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$2.run(PartRenderingEngine.java:722) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:706) + at org.eclipse.e4.ui.workbench.renderers.swt.StackRenderer.showTab(StackRenderer.java:1324) + at org.eclipse.e4.ui.workbench.renderers.swt.LazyStackRenderer.postProcess(LazyStackRenderer.java:103) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:669) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:757) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$0(PartRenderingEngine.java:728) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$2.run(PartRenderingEngine.java:722) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:706) + at org.eclipse.e4.ui.workbench.renderers.swt.SWTPartRenderer.processContents(SWTPartRenderer.java:70) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:665) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$1.run(PartRenderingEngine.java:536) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:520) + at org.eclipse.e4.ui.workbench.renderers.swt.ElementReferenceRenderer.createWidget(ElementReferenceRenderer.java:70) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createWidget(PartRenderingEngine.java:975) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:651) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:757) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$0(PartRenderingEngine.java:728) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$2.run(PartRenderingEngine.java:722) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:706) + at org.eclipse.e4.ui.workbench.renderers.swt.SWTPartRenderer.processContents(SWTPartRenderer.java:70) + at org.eclipse.e4.ui.workbench.renderers.swt.SashRenderer.processContents(SashRenderer.java:142) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:665) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:757) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$0(PartRenderingEngine.java:728) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$2.run(PartRenderingEngine.java:722) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:706) + at org.eclipse.e4.ui.workbench.renderers.swt.SWTPartRenderer.processContents(SWTPartRenderer.java:70) + at org.eclipse.e4.ui.workbench.renderers.swt.SashRenderer.processContents(SashRenderer.java:142) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:665) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:757) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$0(PartRenderingEngine.java:728) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$2.run(PartRenderingEngine.java:722) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:706) + at org.eclipse.e4.ui.workbench.renderers.swt.SWTPartRenderer.processContents(SWTPartRenderer.java:70) + at org.eclipse.e4.ui.workbench.renderers.swt.SashRenderer.processContents(SashRenderer.java:142) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:665) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:757) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$0(PartRenderingEngine.java:728) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$2.run(PartRenderingEngine.java:722) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:706) + at org.eclipse.e4.ui.workbench.renderers.swt.SWTPartRenderer.processContents(SWTPartRenderer.java:70) + at org.eclipse.e4.ui.workbench.renderers.swt.PerspectiveRenderer.processContents(PerspectiveRenderer.java:49) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:665) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:757) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$0(PartRenderingEngine.java:728) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$2.run(PartRenderingEngine.java:722) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:706) + at org.eclipse.e4.ui.workbench.renderers.swt.PerspectiveStackRenderer.showTab(PerspectiveStackRenderer.java:82) + at org.eclipse.e4.ui.workbench.renderers.swt.LazyStackRenderer.postProcess(LazyStackRenderer.java:103) + at org.eclipse.e4.ui.workbench.renderers.swt.PerspectiveStackRenderer.postProcess(PerspectiveStackRenderer.java:63) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:669) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:757) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$0(PartRenderingEngine.java:728) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$2.run(PartRenderingEngine.java:722) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:706) + at org.eclipse.e4.ui.workbench.renderers.swt.SWTPartRenderer.processContents(SWTPartRenderer.java:70) + at org.eclipse.e4.ui.workbench.renderers.swt.SashRenderer.processContents(SashRenderer.java:142) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:665) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:757) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$0(PartRenderingEngine.java:728) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$2.run(PartRenderingEngine.java:722) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:706) + at org.eclipse.e4.ui.workbench.renderers.swt.SWTPartRenderer.processContents(SWTPartRenderer.java:70) + at org.eclipse.e4.ui.workbench.renderers.swt.WBWRenderer.processContents(WBWRenderer.java:725) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:665) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.safeCreateGui(PartRenderingEngine.java:757) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.access$0(PartRenderingEngine.java:728) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$2.run(PartRenderingEngine.java:722) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.createGui(PartRenderingEngine.java:706) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$4.run(PartRenderingEngine.java:1059) + at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:336) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.run(PartRenderingEngine.java:1022) + at org.eclipse.e4.ui.internal.workbench.E4Workbench.createAndRunUI(E4Workbench.java:150) + at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:693) + at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:336) + at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:610) + at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:148) + at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:138) + at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:388) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:243) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:498) + at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:673) + at org.eclipse.equinox.launcher.Main.basicRun(Main.java:610) + at org.eclipse.equinox.launcher.Main.run(Main.java:1519) +!SUBENTRY 2 org.eclipse.core.filebuffers 4 0 2020-06-18 12:57:01.938 +!MESSAGE Cannot determine URI for '/sample_threadx/arc.c'. + +!ENTRY org.eclipse.osgi 4 0 2020-06-18 12:57:02.815 +!MESSAGE An error occurred while automatically activating bundle com.synopsys.cdt.cnn.tools.ui (25). +!STACK 0 +org.osgi.framework.BundleException: Exception in com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start() of bundle com.synopsys.cdt.cnn.tools.ui. + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:795) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +Caused by: java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + ... 27 more +Root exception: +java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) + +!ENTRY org.eclipse.ui.workbench 4 2 2020-06-18 12:57:02.834 +!MESSAGE Problems occurred when invoking code from plug-in: "org.eclipse.ui.workbench". +!STACK 1 +org.eclipse.core.runtime.CoreException: Plug-in com.synopsys.cdt.cnn.tools.ui was unable to load class com.synopsys.cdt.cnn.tools.ui.LoadedAtStartup. + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.throwException(RegistryStrategyOSGI.java:194) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:176) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +Caused by: java.lang.ClassNotFoundException: An error occurred while automatically activating bundle com.synopsys.cdt.cnn.tools.ui (25). + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:116) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + ... 10 more +Caused by: org.osgi.framework.BundleException: Exception in com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start() of bundle com.synopsys.cdt.cnn.tools.ui. + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:795) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + ... 20 more +Caused by: java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + ... 27 more +!SUBENTRY 1 org.eclipse.equinox.registry 4 1 2020-06-18 12:57:02.836 +!MESSAGE Plug-in com.synopsys.cdt.cnn.tools.ui was unable to load class com.synopsys.cdt.cnn.tools.ui.LoadedAtStartup. +!STACK 0 +java.lang.ClassNotFoundException: An error occurred while automatically activating bundle com.synopsys.cdt.cnn.tools.ui (25). + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:116) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +Caused by: org.osgi.framework.BundleException: Exception in com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start() of bundle com.synopsys.cdt.cnn.tools.ui. + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:795) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + ... 20 more +Caused by: java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + ... 27 more +!SUBENTRY 1 org.eclipse.equinox.registry 4 1 2020-06-18 12:57:02.837 +!MESSAGE Plug-in com.synopsys.cdt.cnn.tools.ui was unable to load class com.synopsys.cdt.cnn.tools.ui.LoadedAtStartup. +!STACK 0 +java.lang.ClassNotFoundException: An error occurred while automatically activating bundle com.synopsys.cdt.cnn.tools.ui (25). + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:116) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +Caused by: org.osgi.framework.BundleException: Exception in com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start() of bundle com.synopsys.cdt.cnn.tools.ui. + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:795) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + ... 20 more +Caused by: java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + ... 27 more + +!ENTRY org.eclipse.ui 4 0 2020-06-18 12:57:02.853 +!MESSAGE Unable to execute early startup code for the org.eclipse.ui.IStartup extension contributed by the 'com.synopsys.cdt.cnn.tools.ui' plug-in. +!STACK 1 +org.eclipse.core.runtime.CoreException: Plug-in com.synopsys.cdt.cnn.tools.ui was unable to load class com.synopsys.cdt.cnn.tools.ui.LoadedAtStartup. + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.throwException(RegistryStrategyOSGI.java:194) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:176) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +Caused by: java.lang.ClassNotFoundException: An error occurred while automatically activating bundle com.synopsys.cdt.cnn.tools.ui (25). + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:116) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + ... 10 more +Caused by: org.osgi.framework.BundleException: Exception in com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start() of bundle com.synopsys.cdt.cnn.tools.ui. + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:795) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + ... 20 more +Caused by: java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + ... 27 more +!SUBENTRY 1 org.eclipse.equinox.registry 4 1 2020-06-18 12:57:02.854 +!MESSAGE Plug-in com.synopsys.cdt.cnn.tools.ui was unable to load class com.synopsys.cdt.cnn.tools.ui.LoadedAtStartup. +!STACK 0 +java.lang.ClassNotFoundException: An error occurred while automatically activating bundle com.synopsys.cdt.cnn.tools.ui (25). + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:116) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +Caused by: org.osgi.framework.BundleException: Exception in com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start() of bundle com.synopsys.cdt.cnn.tools.ui. + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:795) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + ... 20 more +Caused by: java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + ... 27 more + +!ENTRY org.eclipse.e4.ui.workbench 2 0 2020-06-18 12:57:03.228 +!MESSAGE Removing part descriptor with the 'org.eclipse.cdt.debug.ui.DisassemblyView' id and the 'Disassembly' description. Points to the invalid 'bundleclass://org.eclipse.ui.workbench/org.eclipse.ui.internal.e4.compatibility.CompatibilityView' class. + +!ENTRY org.eclipse.e4.ui.workbench 4 0 2020-06-18 13:07:50.324 +!MESSAGE Error setting focus to : org.eclipse.e4.ui.model.application.ui.basic.impl.PartImpl tx_port.h +!STACK 0 +org.eclipse.swt.SWTException: Widget is disposed + at org.eclipse.swt.SWT.error(SWT.java:4533) + at org.eclipse.swt.SWT.error(SWT.java:4448) + at org.eclipse.swt.SWT.error(SWT.java:4419) + at org.eclipse.swt.widgets.Widget.error(Widget.java:482) + at org.eclipse.swt.widgets.Widget.checkWidget(Widget.java:354) + at org.eclipse.swt.widgets.Control.setFocus(Control.java:3445) + at org.eclipse.swt.widgets.Composite.setFocus(Composite.java:1122) + at org.eclipse.swt.widgets.Composite.setFocus(Composite.java:1122) + at org.eclipse.ui.texteditor.StatusTextEditor.setFocus(StatusTextEditor.java:118) + at org.eclipse.ui.internal.e4.compatibility.CompatibilityPart.delegateSetFocus(CompatibilityPart.java:203) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:498) + at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:55) + at org.eclipse.e4.core.internal.di.InjectorImpl.invokeUsingClass(InjectorImpl.java:282) + at org.eclipse.e4.core.internal.di.InjectorImpl.invokeUsingClass(InjectorImpl.java:288) + at org.eclipse.e4.core.internal.di.InjectorImpl.invoke(InjectorImpl.java:259) + at org.eclipse.e4.core.contexts.ContextInjectionFactory.invoke(ContextInjectionFactory.java:107) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.focusGui(PartRenderingEngine.java:779) + at org.eclipse.e4.ui.workbench.renderers.swt.ContributedPartRenderer$2.setFocus(ContributedPartRenderer.java:102) + at org.eclipse.e4.ui.workbench.renderers.swt.StackRenderer$6.mouseUp(StackRenderer.java:1151) + at org.eclipse.swt.widgets.TypedListener.handleEvent(TypedListener.java:221) + at org.eclipse.swt.widgets.EventTable.sendEvent(EventTable.java:84) + at org.eclipse.swt.widgets.Display.sendEvent(Display.java:4418) + at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1079) + at org.eclipse.swt.widgets.Display.runDeferredEvents(Display.java:4236) + at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3824) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$4.run(PartRenderingEngine.java:1121) + at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:336) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.run(PartRenderingEngine.java:1022) + at org.eclipse.e4.ui.internal.workbench.E4Workbench.createAndRunUI(E4Workbench.java:150) + at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:693) + at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:336) + at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:610) + at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:148) + at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:138) + at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:388) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:243) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:498) + at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:673) + at org.eclipse.equinox.launcher.Main.basicRun(Main.java:610) + at org.eclipse.equinox.launcher.Main.run(Main.java:1519) + +!ENTRY org.eclipse.e4.ui.workbench 4 0 2020-06-18 13:07:51.530 +!MESSAGE Error setting focus to : org.eclipse.e4.ui.model.application.ui.basic.impl.PartImpl tx_api.h +!STACK 0 +org.eclipse.swt.SWTException: Widget is disposed + at org.eclipse.swt.SWT.error(SWT.java:4533) + at org.eclipse.swt.SWT.error(SWT.java:4448) + at org.eclipse.swt.SWT.error(SWT.java:4419) + at org.eclipse.swt.widgets.Widget.error(Widget.java:482) + at org.eclipse.swt.widgets.Widget.checkWidget(Widget.java:354) + at org.eclipse.swt.widgets.Control.setFocus(Control.java:3445) + at org.eclipse.swt.widgets.Composite.setFocus(Composite.java:1122) + at org.eclipse.swt.widgets.Composite.setFocus(Composite.java:1122) + at org.eclipse.ui.texteditor.StatusTextEditor.setFocus(StatusTextEditor.java:118) + at org.eclipse.ui.internal.e4.compatibility.CompatibilityPart.delegateSetFocus(CompatibilityPart.java:203) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:498) + at org.eclipse.e4.core.internal.di.MethodRequestor.execute(MethodRequestor.java:55) + at org.eclipse.e4.core.internal.di.InjectorImpl.invokeUsingClass(InjectorImpl.java:282) + at org.eclipse.e4.core.internal.di.InjectorImpl.invokeUsingClass(InjectorImpl.java:288) + at org.eclipse.e4.core.internal.di.InjectorImpl.invoke(InjectorImpl.java:259) + at org.eclipse.e4.core.contexts.ContextInjectionFactory.invoke(ContextInjectionFactory.java:107) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.focusGui(PartRenderingEngine.java:779) + at org.eclipse.e4.ui.workbench.renderers.swt.ContributedPartRenderer$2.setFocus(ContributedPartRenderer.java:102) + at org.eclipse.swt.custom.CTabItem.setFocus(CTabItem.java:332) + at org.eclipse.swt.custom.CTabFolder.setFocus(CTabFolder.java:2611) + at org.eclipse.swt.widgets.Control.fixFocus(Control.java:1069) + at org.eclipse.swt.widgets.Control.setVisible(Control.java:3972) + at org.eclipse.swt.custom.CTabFolder.setSelection(CTabFolder.java:3155) + at org.eclipse.swt.custom.CTabFolder.setSelection(CTabFolder.java:3112) + at org.eclipse.e4.ui.workbench.renderers.swt.StackRenderer.showTab(StackRenderer.java:1336) + at org.eclipse.e4.ui.workbench.renderers.swt.LazyStackRenderer$1.handleEvent(LazyStackRenderer.java:72) + at org.eclipse.e4.ui.services.internal.events.UIEventHandler$1.run(UIEventHandler.java:40) + at org.eclipse.swt.widgets.Synchronizer.syncExec(Synchronizer.java:233) + at org.eclipse.ui.internal.UISynchronizer.syncExec(UISynchronizer.java:145) + at org.eclipse.swt.widgets.Display.syncExec(Display.java:4821) + at org.eclipse.e4.ui.internal.workbench.swt.E4Application$1.syncExec(E4Application.java:211) + at org.eclipse.e4.ui.services.internal.events.UIEventHandler.handleEvent(UIEventHandler.java:36) + at org.eclipse.equinox.internal.event.EventHandlerWrapper.handleEvent(EventHandlerWrapper.java:201) + at org.eclipse.equinox.internal.event.EventHandlerTracker.dispatchEvent(EventHandlerTracker.java:197) + at org.eclipse.equinox.internal.event.EventHandlerTracker.dispatchEvent(EventHandlerTracker.java:1) + at org.eclipse.osgi.framework.eventmgr.EventManager.dispatchEvent(EventManager.java:230) + at org.eclipse.osgi.framework.eventmgr.ListenerQueue.dispatchEventSynchronous(ListenerQueue.java:148) + at org.eclipse.equinox.internal.event.EventAdminImpl.dispatchEvent(EventAdminImpl.java:135) + at org.eclipse.equinox.internal.event.EventAdminImpl.sendEvent(EventAdminImpl.java:78) + at org.eclipse.equinox.internal.event.EventComponent.sendEvent(EventComponent.java:39) + at org.eclipse.e4.ui.services.internal.events.EventBroker.send(EventBroker.java:94) + at org.eclipse.e4.ui.internal.workbench.UIEventPublisher.notifyChanged(UIEventPublisher.java:60) + at org.eclipse.emf.common.notify.impl.BasicNotifierImpl.eNotify(BasicNotifierImpl.java:374) + at org.eclipse.e4.ui.model.application.ui.impl.ElementContainerImpl.setSelectedElement(ElementContainerImpl.java:173) + at org.eclipse.e4.ui.internal.workbench.PartServiceImpl.hidePart(PartServiceImpl.java:1331) + at org.eclipse.e4.ui.internal.workbench.PartServiceImpl.hidePart(PartServiceImpl.java:1284) + at org.eclipse.e4.ui.workbench.renderers.swt.StackRenderer.closePart(StackRenderer.java:1296) + at org.eclipse.e4.ui.workbench.renderers.swt.StackRenderer.access$2(StackRenderer.java:1278) + at org.eclipse.e4.ui.workbench.renderers.swt.StackRenderer$7.close(StackRenderer.java:1163) + at org.eclipse.swt.custom.CTabFolder.onMouse(CTabFolder.java:1930) + at org.eclipse.swt.custom.CTabFolder$1.handleEvent(CTabFolder.java:338) + at org.eclipse.swt.widgets.EventTable.sendEvent(EventTable.java:84) + at org.eclipse.swt.widgets.Display.sendEvent(Display.java:4418) + at org.eclipse.swt.widgets.Widget.sendEvent(Widget.java:1079) + at org.eclipse.swt.widgets.Display.runDeferredEvents(Display.java:4236) + at org.eclipse.swt.widgets.Display.readAndDispatch(Display.java:3824) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine$4.run(PartRenderingEngine.java:1121) + at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:336) + at org.eclipse.e4.ui.internal.workbench.swt.PartRenderingEngine.run(PartRenderingEngine.java:1022) + at org.eclipse.e4.ui.internal.workbench.E4Workbench.createAndRunUI(E4Workbench.java:150) + at org.eclipse.ui.internal.Workbench$5.run(Workbench.java:693) + at org.eclipse.core.databinding.observable.Realm.runWithDefault(Realm.java:336) + at org.eclipse.ui.internal.Workbench.createAndRunWorkbench(Workbench.java:610) + at org.eclipse.ui.PlatformUI.createAndRunWorkbench(PlatformUI.java:148) + at org.eclipse.ui.internal.ide.application.IDEApplication.start(IDEApplication.java:138) + at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:196) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:134) + at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:388) + at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:243) + at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method) + at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62) + at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43) + at java.lang.reflect.Method.invoke(Method.java:498) + at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:673) + at org.eclipse.equinox.launcher.Main.basicRun(Main.java:610) + at org.eclipse.equinox.launcher.Main.run(Main.java:1519) + +!ENTRY org.eclipse.cdt.core 1 0 2020-06-18 13:08:13.337 +!MESSAGE Indexed 'sample_threadx' (2 sources, 2 headers) in 0.454 sec: 110 declarations; 266 references; 1 unresolved inclusions; 0 syntax errors; 105 unresolved names (22%) +!SESSION 2020-06-18 13:15:56.207 ----------------------------------------------- +eclipse.buildId=unknown +java.fullversion=1.8.0_212-b03 +JRE 1.8.0 Windows 8 amd64-64-Bit Compressed References 20190417_339 (JIT enabled, AOT enabled) +OpenJ9 - bad1d4d06 +OMR - 4a4278e6 +JCL - 5590c4f818 based on jdk8u212-b03 +BootLoader constants: OS=win32, ARCH=x86_64, WS=win32, NL=en_US +Command-line arguments: -os win32 -ws win32 -arch x86_64 + +!ENTRY org.eclipse.osgi 4 0 2020-06-18 13:20:45.992 +!MESSAGE An error occurred while automatically activating bundle com.synopsys.cdt.cnn.tools.ui (25). +!STACK 0 +org.osgi.framework.BundleException: Exception in com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start() of bundle com.synopsys.cdt.cnn.tools.ui. + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:795) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +Caused by: java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + ... 27 more +Root exception: +java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) + +!ENTRY org.eclipse.ui.workbench 4 2 2020-06-18 13:20:46.023 +!MESSAGE Problems occurred when invoking code from plug-in: "org.eclipse.ui.workbench". +!STACK 1 +org.eclipse.core.runtime.CoreException: Plug-in com.synopsys.cdt.cnn.tools.ui was unable to load class com.synopsys.cdt.cnn.tools.ui.LoadedAtStartup. + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.throwException(RegistryStrategyOSGI.java:194) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:176) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +Caused by: java.lang.ClassNotFoundException: An error occurred while automatically activating bundle com.synopsys.cdt.cnn.tools.ui (25). + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:116) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + ... 10 more +Caused by: org.osgi.framework.BundleException: Exception in com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start() of bundle com.synopsys.cdt.cnn.tools.ui. + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:795) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + ... 20 more +Caused by: java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + ... 27 more +!SUBENTRY 1 org.eclipse.equinox.registry 4 1 2020-06-18 13:20:46.023 +!MESSAGE Plug-in com.synopsys.cdt.cnn.tools.ui was unable to load class com.synopsys.cdt.cnn.tools.ui.LoadedAtStartup. +!STACK 0 +java.lang.ClassNotFoundException: An error occurred while automatically activating bundle com.synopsys.cdt.cnn.tools.ui (25). + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:116) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +Caused by: org.osgi.framework.BundleException: Exception in com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start() of bundle com.synopsys.cdt.cnn.tools.ui. + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:795) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + ... 20 more +Caused by: java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + ... 27 more +!SUBENTRY 1 org.eclipse.equinox.registry 4 1 2020-06-18 13:20:46.023 +!MESSAGE Plug-in com.synopsys.cdt.cnn.tools.ui was unable to load class com.synopsys.cdt.cnn.tools.ui.LoadedAtStartup. +!STACK 0 +java.lang.ClassNotFoundException: An error occurred while automatically activating bundle com.synopsys.cdt.cnn.tools.ui (25). + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:116) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +Caused by: org.osgi.framework.BundleException: Exception in com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start() of bundle com.synopsys.cdt.cnn.tools.ui. + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:795) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + ... 20 more +Caused by: java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + ... 27 more + +!ENTRY org.eclipse.ui 4 0 2020-06-18 13:20:46.039 +!MESSAGE Unable to execute early startup code for the org.eclipse.ui.IStartup extension contributed by the 'com.synopsys.cdt.cnn.tools.ui' plug-in. +!STACK 1 +org.eclipse.core.runtime.CoreException: Plug-in com.synopsys.cdt.cnn.tools.ui was unable to load class com.synopsys.cdt.cnn.tools.ui.LoadedAtStartup. + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.throwException(RegistryStrategyOSGI.java:194) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:176) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +Caused by: java.lang.ClassNotFoundException: An error occurred while automatically activating bundle com.synopsys.cdt.cnn.tools.ui (25). + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:116) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + ... 10 more +Caused by: org.osgi.framework.BundleException: Exception in com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start() of bundle com.synopsys.cdt.cnn.tools.ui. + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:795) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + ... 20 more +Caused by: java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + ... 27 more +!SUBENTRY 1 org.eclipse.equinox.registry 4 1 2020-06-18 13:20:46.039 +!MESSAGE Plug-in com.synopsys.cdt.cnn.tools.ui was unable to load class com.synopsys.cdt.cnn.tools.ui.LoadedAtStartup. +!STACK 0 +java.lang.ClassNotFoundException: An error occurred while automatically activating bundle com.synopsys.cdt.cnn.tools.ui (25). + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:116) + at org.eclipse.osgi.internal.loader.classpath.ClasspathManager.findLocalClass(ClasspathManager.java:529) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.findLocalClass(ModuleClassLoader.java:325) + at org.eclipse.osgi.internal.loader.BundleLoader.findLocalClass(BundleLoader.java:345) + at org.eclipse.osgi.internal.loader.BundleLoader.findClassInternal(BundleLoader.java:423) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:372) + at org.eclipse.osgi.internal.loader.BundleLoader.findClass(BundleLoader.java:364) + at org.eclipse.osgi.internal.loader.ModuleClassLoader.loadClass(ModuleClassLoader.java:161) + at java.lang.ClassLoader.loadClass(ClassLoader.java:874) + at org.eclipse.osgi.internal.framework.EquinoxBundle.loadClass(EquinoxBundle.java:564) + at org.eclipse.core.internal.registry.osgi.RegistryStrategyOSGI.createExecutableExtension(RegistryStrategyOSGI.java:174) + at org.eclipse.core.internal.registry.ExtensionRegistry.createExecutableExtension(ExtensionRegistry.java:905) + at org.eclipse.core.internal.registry.ConfigurationElement.createExecutableExtension(ConfigurationElement.java:243) + at org.eclipse.core.internal.registry.ConfigurationElementHandle.createExecutableExtension(ConfigurationElementHandle.java:55) + at org.eclipse.ui.internal.WorkbenchPlugin$1.run(WorkbenchPlugin.java:291) + at org.eclipse.swt.custom.BusyIndicator.showWhile(BusyIndicator.java:52) + at org.eclipse.ui.internal.WorkbenchPlugin.createExtension(WorkbenchPlugin.java:286) + at org.eclipse.ui.internal.EarlyStartupRunnable.run(EarlyStartupRunnable.java:53) + at org.eclipse.core.runtime.SafeRunner.run(SafeRunner.java:42) + at org.eclipse.ui.internal.Workbench$55.run(Workbench.java:2835) + at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) +Caused by: org.osgi.framework.BundleException: Exception in com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start() of bundle com.synopsys.cdt.cnn.tools.ui. + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:795) + at org.eclipse.osgi.internal.framework.BundleContextImpl.start(BundleContextImpl.java:724) + at org.eclipse.osgi.internal.framework.EquinoxBundle.startWorker0(EquinoxBundle.java:932) + at org.eclipse.osgi.internal.framework.EquinoxBundle$EquinoxModule.startWorker(EquinoxBundle.java:309) + at org.eclipse.osgi.container.Module.doStart(Module.java:581) + at org.eclipse.osgi.container.Module.start(Module.java:449) + at org.eclipse.osgi.framework.util.SecureAction.start(SecureAction.java:470) + at org.eclipse.osgi.internal.hooks.EclipseLazyStarter.postFindLocalClass(EclipseLazyStarter.java:107) + ... 20 more +Caused by: java.lang.NullPointerException + at org.eclipse.core.runtime.Path.(Path.java:228) + at org.eclipse.core.runtime.Path.(Path.java:186) + at com.synopsys.cdt.cnn.tools.ui.Netron.registerExt(Netron.java:12) + at com.synopsys.cdt.cnn.tools.ui.CNNToolsUIPlugin.start(CNNToolsUIPlugin.java:52) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:774) + at org.eclipse.osgi.internal.framework.BundleContextImpl$3.run(BundleContextImpl.java:1) + at java.security.AccessController.doPrivileged(AccessController.java:703) + at org.eclipse.osgi.internal.framework.BundleContextImpl.startActivator(BundleContextImpl.java:767) + ... 27 more + +!ENTRY org.eclipse.e4.ui.workbench 2 0 2020-06-18 13:20:46.358 +!MESSAGE Removing part descriptor with the 'org.eclipse.cdt.debug.ui.DisassemblyView' id and the 'Disassembly' description. Points to the invalid 'bundleclass://org.eclipse.ui.workbench/org.eclipse.ui.internal.e4.compatibility.CompatibilityView' class. diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.cdt.codan.ui/dialog_settings.xml b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.cdt.codan.ui/dialog_settings.xml new file mode 100644 index 00000000..bad736ef --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.cdt.codan.ui/dialog_settings.xml @@ -0,0 +1,4 @@ + +
+ +
diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.cdt.core/.log b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.cdt.core/.log new file mode 100644 index 00000000..1d051b80 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.cdt.core/.log @@ -0,0 +1,27 @@ +*** SESSION Sep 28, 2015 16:00:26.42 ------------------------------------------- +*** SESSION Sep 28, 2015 16:24:47.48 ------------------------------------------- +*** SESSION Sep 28, 2015 16:43:36.06 ------------------------------------------- +*** SESSION Oct 01, 2015 14:52:43.41 ------------------------------------------- +*** SESSION Oct 01, 2015 16:50:35.31 ------------------------------------------- +*** SESSION Oct 02, 2015 16:30:04.53 ------------------------------------------- +*** SESSION Oct 05, 2015 13:04:34.94 ------------------------------------------- +*** SESSION Oct 05, 2015 17:02:39.29 ------------------------------------------- +*** SESSION Oct 06, 2015 09:33:29.71 ------------------------------------------- +*** SESSION Oct 08, 2015 14:32:58.71 ------------------------------------------- +*** SESSION Oct 09, 2015 15:42:00.42 ------------------------------------------- +*** SESSION Oct 12, 2015 11:13:19.78 ------------------------------------------- +*** SESSION Oct 12, 2015 13:34:17.27 ------------------------------------------- +*** SESSION Oct 12, 2015 13:59:21.03 ------------------------------------------- +*** SESSION Apr 05, 2017 21:13:28.98 ------------------------------------------- +*** SESSION Apr 05, 2017 21:23:06.09 ------------------------------------------- +*** SESSION Apr 11, 2017 16:39:35.66 ------------------------------------------- +*** SESSION Apr 11, 2017 17:00:38.48 ------------------------------------------- +*** SESSION Apr 11, 2017 20:13:06.07 ------------------------------------------- +*** SESSION Apr 12, 2017 14:48:16.90 ------------------------------------------- +*** SESSION Apr 13, 2017 18:52:33.10 ------------------------------------------- +*** SESSION Apr 13, 2017 19:20:40.79 ------------------------------------------- +*** SESSION Apr 14, 2017 09:54:41.39 ------------------------------------------- +*** SESSION Apr 14, 2017 15:41:48.94 ------------------------------------------- +*** SESSION Apr 14, 2017 16:25:44.12 ------------------------------------------- +*** SESSION Apr 17, 2017 16:44:17.22 ------------------------------------------- +*** SESSION Jun 18, 2020 12:57:01.25 ------------------------------------------- diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.cdt.core/sample_threadx.1443481736829.pdom b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.cdt.core/sample_threadx.1443481736829.pdom new file mode 100644 index 00000000..fc72688a Binary files /dev/null and b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.cdt.core/sample_threadx.1443481736829.pdom differ diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.cdt.core/sample_threadx.1592510892863.pdom b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.cdt.core/sample_threadx.1592510892863.pdom new file mode 100644 index 00000000..83aa0e19 Binary files /dev/null and b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.cdt.core/sample_threadx.1592510892863.pdom differ diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.cdt.core/sample_threadx.language.settings.xml b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.cdt.core/sample_threadx.language.settings.xml new file mode 100644 index 00000000..d88b11c6 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.cdt.core/sample_threadx.language.settings.xml @@ -0,0 +1,4787 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.cdt.managedbuilder.core/spec.c new file mode 100644 index 00000000..e69de29b diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.cdt.managedbuilder.core/spec.cpp b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.cdt.managedbuilder.core/spec.cpp new file mode 100644 index 00000000..e69de29b diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.cdt.ui/cHelpSettings.xml b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.cdt.ui/cHelpSettings.xml new file mode 100644 index 00000000..64868cbf --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.cdt.ui/cHelpSettings.xml @@ -0,0 +1,6 @@ + + + + + + diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.cdt.ui/dialog_settings.xml b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.cdt.ui/dialog_settings.xml new file mode 100644 index 00000000..661aa8c7 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.cdt.ui/dialog_settings.xml @@ -0,0 +1,11 @@ + +
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diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/.history/f0/60943445c62300171ed8c82249418230 b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/.history/f0/60943445c62300171ed8c82249418230 new file mode 100644 index 00000000..ca0ad3cd --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/.history/f0/60943445c62300171ed8c82249418230 @@ -0,0 +1,444 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) 1996-2017 by Express Logic Inc. */ +/* */ +/* This software is copyrighted by and is the sole property of Express */ +/* Logic, Inc. All rights, title, ownership, or other interests */ +/* in the software remain the property of Express Logic, Inc. This */ +/* software may only be used in accordance with the corresponding */ +/* license agreement. Any unauthorized use, duplication, transmission, */ +/* distribution, or disclosure of this software is expressly forbidden. */ +/* */ +/* This Copyright notice may not be removed or modified without prior */ +/* written consent of Express Logic, Inc. */ +/* */ +/* Express Logic, Inc. reserves the right to modify this software */ +/* without notice. */ +/* */ +/* Express Logic, Inc. info@expresslogic.com */ +/* 11423 West Bernardo Court http://www.expresslogic.com */ +/* San Diego, CA 92127 */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h SMP/ARC_HS/MetaWare */ +/* 5.0 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Express Logic, Inc. */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* xx-xx-2017 William E. Lamie Initial SMP/ARC HS/MetaWare */ +/* Support Version 5.0 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Remove volatile for ThreadX source on the ARC. This is because the ARC + compiler generates different non-cache r/w access when using volatile + that is different from the assembly language access of the same + global variables in ThreadX. */ + +#ifdef TX_SOURCE_CODE +#define volatile +#else +#ifdef NX_SOURCE_CODE +#define volatile +#else +#ifdef FX_SOURCE_CODE +#define volatile +#else +#ifdef UX_SOURCE_CODE +#define volatile +#endif +#endif +#endif +#endif + +/************* Define ThreadX SMP constants. *************/ + +/* Define the ThreadX SMP maximum number of cores. */ + +#ifndef TX_THREAD_SMP_MAX_CORES +#define TX_THREAD_SMP_MAX_CORES 2 +#endif + + +/* Define the ThreadX SMP core mask. */ + +#ifndef TX_THREAD_SMP_CORE_MASK +#define TX_THREAD_SMP_CORE_MASK 0x3 /* Where bit 0 represents Core 0, bit 1 represents Core 1, etc. */ +#endif + + +/* Define INLINE_DECLARE to whitespace for MetaWare compiler. */ + +#define INLINE_DECLARE + + +/* Define dynamic number of cores option. When commented out, the number of cores is static. */ + +/* #define TX_THREAD_SMP_DYNAMIC_CORE_MAX */ + + +/* Define ThreadX SMP initialization macro. */ + +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION + + +/* Define ThreadX SMP pre-scheduler initialization. */ + +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION + + +/* Enable the inter-core interrupt logic. */ + +#define TX_THREAD_SMP_INTER_CORE_INTERRUPT + + +/* Determine if there is customer-specific wakeup logic needed. */ + +#ifdef TX_THREAD_SMP_WAKEUP_LOGIC + +/* Include customer-specific wakeup code. */ + +#include "tx_thread_smp_core_wakeup.h" +#else + +#ifdef TX_THREAD_SMP_DEFAULT_WAKEUP_LOGIC + +/* Default wakeup code. */ +#define TX_THREAD_SMP_WAKEUP_LOGIC +#define TX_THREAD_SMP_WAKEUP(i) _tx_thread_smp_core_preempt(i) +#endif +#endif + + +/* Ensure that the in-line resume/suspend define is not allowed. */ + +#ifdef TX_INLINE_THREAD_RESUME_SUSPEND +#undef TX_INLINE_THREAD_RESUME_SUSPEND +#endif + +/************* End ThreadX SMP constants. *************/ + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 800 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 2048 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARC HS port. */ + +#define TX_INT_ENABLE 0x0000001F /* Enable all interrupts */ +#define TX_INT_DISABLE_MASK 0x00000000 /* Disable all interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE ++_tx_trace_simulated_time +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS 0 + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#define TX_INLINE_INITIALIZATION + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 VOID *__mw_threadx_tls; \ + int __mw_errnum; \ + VOID (*__mw_thread_exit)(struct TX_THREAD_STRUCT *); +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + +#if __HIGHC__ + +/* The MetaWare thread safe C/C++ runtime library needs space to + store thread specific information. In addition, a function pointer + is also supplied so that certain thread-specific resources may be + released upon thread termination and/or thread completion. */ + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) \ + thread_ptr -> __mw_threadx_tls = 0; \ + thread_ptr -> __mw_errnum = 0; \ + thread_ptr -> __mw_thread_exit = TX_NULL; +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) \ + if (thread_ptr -> __mw_thread_exit) \ + (thread_ptr -> __mw_thread_exit) (thread_ptr); +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) \ + if (thread_ptr -> __mw_thread_exit) \ + (thread_ptr -> __mw_thread_exit) (thread_ptr); + +#else + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + +#endif + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/************* Define ThreadX SMP data types and function prototypes. *************/ + +struct TX_THREAD_STRUCT; + + +/* Define the ThreadX SMP protection structure. */ + +typedef struct TX_THREAD_SMP_PROTECT_STRUCT +{ + ULONG tx_thread_smp_protect_in_force; + struct TX_THREAD_STRUCT * + tx_thread_smp_protect_thread; + ULONG tx_thread_smp_protect_core; + ULONG tx_thread_smp_protect_count; + + /* Implementation specific information follows. */ + + ULONG tx_thread_smp_protect_get_caller; + ULONG tx_thread_smp_protect_status32; + ULONG tx_thread_smp_protect_release_caller; +} TX_THREAD_SMP_PROTECT; + + + +/* Define ThreadX SMP low-level assembly routines. */ + +struct TX_THREAD_STRUCT * _tx_thread_smp_current_thread_get(void); +UINT _tx_thread_smp_protect(void); +void _tx_thread_smp_unprotect(UINT interrupt_save); +ULONG _tx_thread_smp_current_state_get(void); +ULONG _tx_thread_smp_time_get(void); + + +/* Determine if SMP Debug is selected. If so, the function prototype is setup. Otherwise, the debug call is + simply mapped to whitespace. */ + +#ifdef TX_THREAD_SMP_DEBUG_ENABLE +void _tx_thread_smp_debug_entry_insert(ULONG id, ULONG suspend, VOID *thread_ptr); +#else +#define _tx_thread_smp_debug_entry_insert(a, b, c) +#endif + + +/* Define the get thread macro. */ + +#define TX_THREAD_GET_CURRENT(a) a = (TX_THREAD *) _tx_thread_smp_current_thread_get(); + + +/* Define the get core ID macro. */ + +#define TX_SMP_CORE_ID _tx_thread_smp_core_get() + + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_smp_protect(); +#define TX_RESTORE _tx_thread_smp_unprotect(interrupt_save); + + +/************* End ThreadX SMP data type and function prototype definitions. *************/ + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) 1996-YYYY Express Logic Inc. * ThreadX SMP/ARC_HS/MetaWare Version GVVVV.5.0 SN: ZZZZ *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + + + diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/.projects/sample_threadx/.indexes/properties.index b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/.projects/sample_threadx/.indexes/properties.index new file mode 100644 index 00000000..9cb4d44f Binary files /dev/null and b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/.projects/sample_threadx/.indexes/properties.index differ diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/.projects/sample_threadx/.markers.snap b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/.projects/sample_threadx/.markers.snap new file mode 100644 index 00000000..0b368ce1 Binary files /dev/null and b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/.projects/sample_threadx/.markers.snap differ diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/.projects/sample_threadx/.syncinfo.snap b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/.projects/sample_threadx/.syncinfo.snap new file mode 100644 index 00000000..0b368ce1 Binary files /dev/null and b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/.projects/sample_threadx/.syncinfo.snap differ diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/.projects/tx/.indexes/properties.index b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/.projects/tx/.indexes/properties.index new file mode 100644 index 00000000..77b66227 Binary files /dev/null and b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/.projects/tx/.indexes/properties.index differ diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/.projects/tx/.markers.snap b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/.projects/tx/.markers.snap new file mode 100644 index 00000000..0b368ce1 Binary files /dev/null and b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/.projects/tx/.markers.snap differ diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/.projects/tx/.syncinfo.snap b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/.projects/tx/.syncinfo.snap new file mode 100644 index 00000000..0b368ce1 Binary files /dev/null and b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/.projects/tx/.syncinfo.snap differ diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/history.version b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/history.version new file mode 100644 index 00000000..25cb955b --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/history.version @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.index b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.index new file mode 100644 index 00000000..bb2b32af Binary files /dev/null and b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.index differ diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.version b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.version new file mode 100644 index 00000000..6b2aaa76 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/.root/.indexes/properties.version @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/.root/.markers.snap b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/.root/.markers.snap new file mode 100644 index 00000000..0b368ce1 Binary files /dev/null and b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/.root/.markers.snap differ diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/.safetable/org.eclipse.core.resources b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/.safetable/org.eclipse.core.resources new file mode 100644 index 00000000..1747d887 Binary files /dev/null and b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/.safetable/org.eclipse.core.resources differ diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/27.snap b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/27.snap new file mode 100644 index 00000000..8a37d2c1 Binary files /dev/null and b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.resources/27.snap differ diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prefs b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prefs new file mode 100644 index 00000000..77ca49ab --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +macros/workspace=\r\n\r\n diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-sample_threadx.prefs b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-sample_threadx.prefs new file mode 100644 index 00000000..9c00dc4e --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-sample_threadx.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +indexer/preferenceScope=0 diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-tx.prefs b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-tx.prefs new file mode 100644 index 00000000..9c00dc4e --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.core.prj-tx.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +indexer/preferenceScope=0 diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.core.prefs b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.core.prefs new file mode 100644 index 00000000..9531fc3c --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.core.prefs @@ -0,0 +1,3 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.debug.core.cDebug.default_source_containers=\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n +org.eclipse.cdt.debug.corecDebug.Disassembly.instructionStepOn=true diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.ui.prefs b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.ui.prefs new file mode 100644 index 00000000..c03690a1 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.debug.ui.prefs @@ -0,0 +1,7 @@ +columnOrderKeyEXE=0,1,2,3,4,5 +columnOrderKeySF=0,1,2,3,4,5 +columnSortDirectionKeyEXE=128 +columnSortDirectionKeySF=128 +eclipse.preferences.version=1 +visibleColumnsKeyEXE=1,1,1,0,0,0 +visibleColumnsKeySF=1,1,0,0,0,0 diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.launchbar.core.prefs b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.launchbar.core.prefs new file mode 100644 index 00000000..c002721a --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.launchbar.core.prefs @@ -0,0 +1,5 @@ +activeConfigDesc=sample_threadx Debug.org.eclipse.cdt.launchbar.core.descriptor.default +configDescList=[sample_threadx Debug.org.eclipse.cdt.launchbar.core.descriptor.default] +sample_threadx\ Debug.org.eclipse.cdt.launchbar.core.descriptor.default/activeLaunchMode=debug +sample_threadx\ Debug.org.eclipse.cdt.launchbar.core.descriptor.default/activeLaunchTarget=org.eclipse.cdt.launchbar.core.target.local +eclipse.preferences.version=1 diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs new file mode 100644 index 00000000..cc2e0070 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.managedbuilder.core.prefs @@ -0,0 +1,5 @@ +eclipse.preferences.version=1 +properties/sample_threadx.com.arc.cdt.toolchain.arc.av2hs.exeProject.1700533761/com.arc.cdt.toolchain.av2hs.exeDebugConfig.585788724=av2hs.exe.debug.exeCompilerDebug.1743110770\=rebuildState\\\=false\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.exeDebugConfig.585788724\=rcState\\\=0\\r\\nrebuildState\\\=false\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.asmDebugExe.1483523628\=rebuildState\\\=false\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.exeToolChainDebug.1358823635\=rebuildState\\\=false\\r\\n\r\ncom.arc.cdt.toolchain.arc.archiver.886382681\=rebuildState\\\=false\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.exeLinkerDebug.672502322\=rebuildState\\\=false\\r\\n\r\n +properties/sample_threadx.com.arc.cdt.toolchain.arc.av2hs.exeProject.1700533761/com.arc.cdt.toolchain.av2hs.exeReleaseConfig.2024992869=com.arc.cdt.toolchain.av2hs.exelinkerRelease.934772409\=rebuildState\\\=true\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.asmReleaseExe.813382130\=rebuildState\\\=true\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.exeReleaseToolChain.202924782\=rebuildState\\\=true\\r\\n\r\ncom.arc.cdt.toolchain.arc.archiver.990750758\=rebuildState\\\=true\\r\\n\r\narc.cdt.toolchain.av2hs.exeCompilerRelease.1463268267\=rebuildState\\\=true\\r\\n\r\n +properties/tx.com.arc.cdt.toolchain.arc.av2hs.libProject.1128858457/com.arc.cdt.toolchain.av2hs.libDebugConfig.2063275274=com.arc.cdt.toolchain.av2hs.libDebugAsm.1626881776\=rebuildState\\\=false\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.ArDebug.178841002\=rebuildState\\\=true\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.libDebugConfig.2063275274\=rcState\\\=0\\r\\nrebuildState\\\=false\\r\\n\r\nav2hs.lib.debug.libCompiler.46227008\=rebuildState\\\=true\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.ArDebug.1591578035\=rebuildState\\\=false\\r\\n\r\nav2hs.lib.debug.libCompiler.2145942775\=rebuildState\\\=false\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.libDebugToolChain.22686690\=rebuildState\\\=true\\r\\n\r\ncom.arc.cdt.toolchain.arc.Linker.141619666\=rebuildState\\\=true\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.libDebugToolChain.1385404397\=rebuildState\\\=false\\r\\n\r\ncom.arc.cdt.toolchain.arc.Linker.41800372\=rebuildState\\\=false\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.libDebugAsm.262854485\=rebuildState\\\=true\\r\\n\r\n +properties/tx.com.arc.cdt.toolchain.arc.av2hs.libProject.1128858457/com.arc.cdt.toolchain.av2hs.libReleaseConfig.1202427021=com.arc.cdt.toolchain.av2hs.libCompilerRelease.1920721386\=rebuildState\\\=true\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.libReleaseAsm.1207600374\=rebuildState\\\=true\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.ArRelease.217147730\=rebuildState\\\=true\\r\\n\r\ncom.arc.cdt.toolchain.av2hs.libReleaseToolChain.1456119623\=rebuildState\\\=true\\r\\n\r\ncom.arc.cdt.toolchain.arc.Linker.1382145468\=rebuildState\\\=true\\r\\n\r\n diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs new file mode 100644 index 00000000..5e2da66d --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prefs @@ -0,0 +1,4 @@ +eclipse.preferences.version=1 +spelling_locale_initialized=true +useAnnotationsPrefPage=true +useQuickDiffPrefPage=true diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prj-sample_threadx.prefs b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prj-sample_threadx.prefs new file mode 100644 index 00000000..d6d44177 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prj-sample_threadx.prefs @@ -0,0 +1,3 @@ +buildConsole/keepLog=false +buildConsole/logLocation=C\:\\arc_hs_smp\\.metadata\\.plugins\\org.eclipse.cdt.ui\\sample_threadx.build.log +eclipse.preferences.version=1 diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prj-tx.prefs b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prj-tx.prefs new file mode 100644 index 00000000..d098905e --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.cdt.ui.prj-tx.prefs @@ -0,0 +1,3 @@ +buildConsole/keepLog=false +buildConsole/logLocation=C\:\\arc_hs_smp\\.metadata\\.plugins\\org.eclipse.cdt.ui\\tx.build.log +eclipse.preferences.version=1 diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 00000000..dffc6b51 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +version=1 diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs new file mode 100644 index 00000000..7bc76be7 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.core.prefs @@ -0,0 +1,5 @@ +//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.attachLaunchType=org.eclipse.cdt.dsf.gdb.launch.attachCLaunch,debug,; +//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.localCLaunch=org.eclipse.cdt.cdi.launch.localCLaunch,run,; +//org.eclipse.debug.core.PREFERRED_DELEGATES/org.eclipse.cdt.launch.postmortemLaunchType=org.eclipse.cdt.dsf.gdb.launch.coreCLaunch,debug,; +eclipse.preferences.version=1 +prefWatchExpressions=\r\n\r\n diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs new file mode 100644 index 00000000..38703762 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs @@ -0,0 +1,9 @@ +eclipse.preferences.version=1 +org.eclipse.debug.ui.PREF_LAUNCH_PERSPECTIVES=\r\n\r\n +org.eclipse.debug.ui.user_view_bindings=\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n +pref_state_memento.org.eclipse.debug.ui.BreakpointView=\r\n\r\n\r\n\r\n\r\n +pref_state_memento.org.eclipse.debug.ui.DebugVieworg.eclipse.debug.ui.DebugView=\r\n +pref_state_memento.org.eclipse.debug.ui.ModuleView=\r\n +pref_state_memento.org.eclipse.debug.ui.VariableView=\r\n +preferredDetailPanes=DefaultDetailPane\:DefaultDetailPane| +preferredTargets=org.eclipse.cdt.debug.ui.toggleCBreakpointTarget\:org.eclipse.cdt.debug.ui.toggleCBreakpointTarget|org.eclipse.cdt.debug.ui.toggleCBreakpointTarget,org.eclipse.cdt.debug.ui.toggleCDynamicPrintfTarget\:org.eclipse.cdt.debug.ui.toggleCBreakpointTarget| diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.editors.prefs b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.editors.prefs new file mode 100644 index 00000000..61f3bb8b --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.editors.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +overviewRuler_migration=migrated_3.1 diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs new file mode 100644 index 00000000..76ce67b9 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.ide.prefs @@ -0,0 +1,5 @@ +PROBLEMS_FILTERS_MIGRATE=true +eclipse.preferences.version=1 +platformState=1590536495337 +quickStart=true +tipsAndTricks=true diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs new file mode 100644 index 00000000..08076f23 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +showIntro=false diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs new file mode 100644 index 00000000..e2e3209c --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.ui.workbench.prefs @@ -0,0 +1,3 @@ +//org.eclipse.ui.commands/state/org.eclipse.ui.navigator.resources.nested.changeProjectPresentation/org.eclipse.ui.commands.radioState=false +UIActivities.org.eclipse.cdt.debug.cdigdbActivity=true +eclipse.preferences.version=1 diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.debug.core/.launches/sample_threadx Debug.launch b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.debug.core/.launches/sample_threadx Debug.launch new file mode 100644 index 00000000..077481e2 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.debug.core/.launches/sample_threadx Debug.launch @@ -0,0 +1,476 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+
+ + + + + + +
+
diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml new file mode 100644 index 00000000..c22cfeb5 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.debug.ui/launchConfigurationHistory.xml @@ -0,0 +1,23 @@ + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.e4.workbench/workbench.xmi b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.e4.workbench/workbench.xmi new file mode 100644 index 00000000..a0b79e26 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.e4.workbench/workbench.xmi @@ -0,0 +1,2041 @@ + + + + activeSchemeId:org.eclipse.ui.defaultAcceleratorConfiguration + ModelMigrationProcessor.001 + + + + + + + + topLevel + shellMaximized + + + + + persp.actionSet:com.arc.eclipse.aboutMWDebugger + persp.actionSet:com.arc.cdt.toolchain.PDFs + persp.actionSet:org.eclipse.ui.cheatsheets.actionSet + persp.actionSet:org.eclipse.search.searchActionSet + persp.actionSet:org.eclipse.ui.edit.text.actionSet.annotationNavigation + persp.actionSet:org.eclipse.ui.edit.text.actionSet.navigation + persp.actionSet:org.eclipse.ui.edit.text.actionSet.convertLineDelimitersTo + persp.actionSet:org.eclipse.ui.externaltools.ExternalToolsSet + persp.actionSet:org.eclipse.ui.actionSet.keyBindings + persp.actionSet:org.eclipse.ui.actionSet.openFiles + persp.actionSet:org.eclipse.cdt.ui.SearchActionSet + persp.actionSet:org.eclipse.cdt.ui.CElementCreationActionSet + persp.actionSet:org.eclipse.ui.NavigateActionSet + persp.viewSC:org.eclipse.ui.console.ConsoleView + persp.viewSC:org.eclipse.search.ui.views.SearchView + persp.viewSC:org.eclipse.ui.views.ContentOutline + persp.viewSC:org.eclipse.ui.views.ProblemView + persp.viewSC:org.eclipse.cdt.ui.CView + persp.viewSC:org.eclipse.ui.views.ResourceNavigator + persp.viewSC:org.eclipse.ui.views.PropertySheet + persp.viewSC:org.eclipse.ui.views.TaskList + persp.newWizSC:org.eclipse.cdt.ui.wizards.ConvertToMakeWizard + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewMakeFromExisting + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewCWizard1 + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewCWizard2 + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewSourceFolderCreationWizard + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewFolderCreationWizard + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewSourceFileCreationWizard + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewHeaderFileCreationWizard + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewFileCreationWizard + persp.newWizSC:org.eclipse.cdt.ui.wizards.NewClassCreationWizard + persp.viewSC:org.eclipse.pde.runtime.LogView + persp.showIn:org.eclipse.cdt.codan.internal.ui.views.ProblemDetails + persp.viewSC:org.eclipse.cdt.codan.internal.ui.views.ProblemDetails + persp.actionSet:org.eclipse.debug.ui.breakpointActionSet + persp.viewSC:org.eclipse.cdt.make.ui.views.MakeView + persp.actionSet:org.eclipse.cdt.make.ui.makeTargetActionSet + persp.perspSC:org.eclipse.debug.ui.DebugPerspective + persp.perspSC:org.eclipse.team.ui.TeamSynchronizingPerspective + persp.actionSet:org.eclipse.debug.ui.launchActionSet + persp.actionSet:org.eclipse.cdt.ui.buildConfigActionSet + persp.actionSet:org.eclipse.cdt.ui.NavigationActionSet + persp.actionSet:org.eclipse.cdt.ui.OpenActionSet + persp.actionSet:org.eclipse.cdt.ui.CodingActionSet + persp.actionSet:org.eclipse.ui.edit.text.actionSet.presentation + persp.showIn:org.eclipse.cdt.ui.includeBrowser + persp.showIn:org.eclipse.cdt.ui.CView + persp.showIn:org.eclipse.ui.navigator.ProjectExplorer + persp.viewSC:org.eclipse.ui.navigator.ProjectExplorer + persp.viewSC:org.eclipse.cdt.ui.includeBrowser + + + newtablook + + + + + + + + + + newtablook + + + + + + + newtablook + + + + + + + + + + + persp.actionSet:com.arc.eclipse.aboutMWDebugger + persp.actionSet:com.arc.cdt.toolchain.PDFs + persp.actionSet:org.eclipse.ui.cheatsheets.actionSet + persp.actionSet:org.eclipse.search.searchActionSet + persp.actionSet:org.eclipse.ui.edit.text.actionSet.annotationNavigation + persp.actionSet:org.eclipse.ui.edit.text.actionSet.navigation + persp.actionSet:org.eclipse.ui.edit.text.actionSet.convertLineDelimitersTo + persp.actionSet:org.eclipse.ui.externaltools.ExternalToolsSet + persp.actionSet:org.eclipse.ui.actionSet.keyBindings + persp.actionSet:org.eclipse.ui.actionSet.openFiles + persp.actionSet:org.eclipse.debug.ui.launchActionSet + persp.actionSet:org.eclipse.debug.ui.debugActionSet + persp.viewSC:org.eclipse.debug.ui.DebugView + persp.viewSC:org.eclipse.debug.ui.VariableView + persp.viewSC:org.eclipse.debug.ui.BreakpointView + persp.viewSC:org.eclipse.debug.ui.ExpressionView + persp.viewSC:org.eclipse.ui.views.ContentOutline + persp.viewSC:org.eclipse.ui.console.ConsoleView + persp.viewSC:org.eclipse.ui.views.TaskList + persp.viewSC:com.arc.cdt.debug.seecode.ui.views.disasm + persp.viewSC:com.arc.cdt.debug.seecode.ui.command + persp.viewSC:com.arc.cdt.debug.seecode.ui.views.memsearch + persp.viewSC:com.arc.cdt.seecode.errorlog + persp.viewSC:org.eclipse.cdt.debug.ui.SignalsView + persp.viewSC:org.eclipse.cdt.debug.ui.RegisterView + persp.viewSC:org.eclipse.debug.ui.ModuleView + persp.viewSC:org.eclipse.debug.ui.MemoryView + persp.viewSC:org.eclipse.ui.views.ProblemView + persp.viewSC:org.eclipse.cdt.debug.ui.executablesView + persp.actionSet:org.eclipse.cdt.debug.ui.debugActionSet + persp.actionSet:org.eclipse.cdt.debug.ui.debugActionSetExt + persp.viewSC:org.eclipse.cdt.dsf.gdb.ui.tracecontrol.view + persp.viewSC:org.eclipse.cdt.dsf.debug.ui.disassembly.view + persp.perspSC:org.eclipse.cdt.ui.CPerspective + persp.viewSC:org.eclipse.cdt.visualizer.view + persp.actionSet:org.eclipse.ui.NavigateActionSet + persp.actionSet:org.eclipse.debug.ui.breakpointActionSet + persp.viewSC:org.eclipse.pde.runtime.LogView + persp.actionSet:org.eclipse.cdt.debug.ui.debugActionSetExt2 + + + + + + newtablook + org.eclipse.e4.primaryNavigationStack + + + + + newtablook + + + + + newtablook + + + + + + + + + + + + + + + + + + + + + + + newtablook + + + + + + newtablook + org.eclipse.e4.secondaryNavigationStack + + + + + + + + + Standalone + + + + + + + newtablook + org.eclipse.e4.secondaryDataStack + + + + + + + + + + + newtablook + + + + + + + + + + + + + + + + + View + categoryTag:Help + + + View + categoryTag:General + + ViewMenu + menuContribution:menu + + + + + View + categoryTag:Help + + + + newtablook + org.eclipse.e4.primaryDataStack + EditorStack + active + noFocus + + + Editor + org.eclipse.cdt.ui.editor.CEditor + removeOnHide + active + + menuContribution:popup + popup:#CEditorContext + popup:org.eclipse.cdt.ui.editor.CEditor.EditorContext + popup:#AbstractTextEditorContext + + + menuContribution:popup + popup:#CEditorRulerContext + popup:org.eclipse.cdt.ui.editor.CEditor.RulerContext + popup:#AbstractTextEditorRulerContext + + + menuContribution:popup + popup:#OverviewRulerContext + + + + + + + View + categoryTag:General + + ViewMenu + menuContribution:menu + + + menuContribution:popup + popup:org.eclipse.ui.navigator.ProjectExplorer#PopupMenu + + + menuContribution:popup + popup:org.eclipse.ui.navigator.ProjectExplorer#PopupMenu + + + menuContribution:popup + popup:org.eclipse.ui.navigator.ProjectExplorer#PopupMenu + + + + + View + categoryTag:&C/C++ + + + View + categoryTag:General + + + View + categoryTag:General + + + + View + categoryTag:General + + ViewMenu + menuContribution:menu + + + menuContribution:popup + popup:org.eclipse.ui.views.ProblemView + popup:org.eclipse.ui.ide.MarkersView + + + menuContribution:popup + popup:org.eclipse.ui.views.ProblemView + popup:org.eclipse.ui.ide.MarkersView + + + menuContribution:popup + popup:org.eclipse.ui.views.ProblemView + popup:org.eclipse.ui.ide.MarkersView + + + + + View + categoryTag:General + + + + View + categoryTag:General + + ViewMenu + menuContribution:menu + + + menuContribution:popup + popup:org.eclipse.cdt.ui.CDTGlobalBuildConsole + + + menuContribution:popup + popup:org.eclipse.cdt.ui.CDTBuildConsole + + + menuContribution:popup + popup:org.eclipse.cdt.ui.CDTGlobalBuildConsole + + + menuContribution:popup + popup:org.eclipse.cdt.ui.CDTBuildConsole + + + menuContribution:popup + popup:org.eclipse.cdt.ui.CDTGlobalBuildConsole + + + menuContribution:popup + popup:org.eclipse.cdt.ui.CDTBuildConsole + + + + + View + categoryTag:General + + + + View + categoryTag:General + + ViewMenu + menuContribution:menu + + + menuContribution:popup + popup:#ASMOutlineContext + + + menuContribution:popup + popup:#ASMOutlineContext + + + menuContribution:popup + popup:#TranslationUnitOutlinerContext + + + menuContribution:popup + popup:#TranslationUnitOutlinerContext + + + menuContribution:popup + popup:#TranslationUnitOutlinerContext + + + menuContribution:popup + popup:#TranslationUnitOutlinerContext + + + menuContribution:popup + popup:#TranslationUnitOutlinerContext + + + + + View + categoryTag:Make + + + View + categoryTag:Terminal + + + + View + categoryTag:Debug + + ViewMenu + menuContribution:menu + + + + + + View + categoryTag:Debug + + ViewMenu + menuContribution:menu + + + + + + View + categoryTag:Debug + + ViewMenu + menuContribution:menu + + + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + + View + categoryTag:Debug + + ViewMenu + menuContribution:menu + + + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + View + categoryTag:Debug + + + + View + categoryTag:Debug + + ViewMenu + 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categoryTag:&C/C++ + + + + + View + categoryTag:&C/C++ + + + + + View + categoryTag:&C/C++ + + + + + View + categoryTag:General + + + + + View + categoryTag:Debug + + + + + View + categoryTag:Debug + + + + + View + categoryTag:Debug + + + + + View + categoryTag:Debug + + + + + View + categoryTag:Debug + + + + + View + categoryTag:Debug + + + + + View + categoryTag:Debug + + + + + View + categoryTag:Debug + + + + + View + categoryTag:Help + + + + + View + categoryTag:General + + + + + View + categoryTag:General + + + + + View + categoryTag:Team + + + + + View + categoryTag:Team + + + + + View + categoryTag:Terminal + + + + + View + categoryTag:General + + + + + View + categoryTag:General + + + + + View + categoryTag:Help + + + + + View + categoryTag:General + + + + + View + categoryTag:General + + + + + View + categoryTag:General + + + + + View + categoryTag:General + + + + + View + categoryTag:General + + + + + View + categoryTag:General + + + + + View + categoryTag:General + + + + + View + categoryTag:General + + + + + View + categoryTag:General + + + + + View + categoryTag:General + + + + + View + categoryTag:General + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2017/4/15/refactorings.history b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2017/4/15/refactorings.history new file mode 100644 index 00000000..5c2a14e3 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2017/4/15/refactorings.history @@ -0,0 +1,3 @@ + + + \ No newline at end of file diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2017/4/15/refactorings.index b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2017/4/15/refactorings.index new file mode 100644 index 00000000..53cdadda --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2017/4/15/refactorings.index @@ -0,0 +1,8 @@ +1491970036256 Delete resource 'tx/tx_thread_context_fast_restore.s' +1491970041634 Delete resource 'tx/tx_thread_context_fast_save.s' +1491970051557 Delete resource 'tx/tx_thread_register_bank_assign.s' +1491970093291 Delete resource 'tx/tx_initialize_fast_interrupt_setup.s' +1492209727732 Delete resource 'sample_threadx/tx_port_test_threads.s' +1492209734183 Delete resource 'sample_threadx/arc.bak' +1492209738993 Delete resource 'sample_threadx/sample_threadx.bak' +1492209743831 Delete resource 'sample_threadx/tx_initialize_low_level.bak' diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2020/6/25/refactorings.history b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2020/6/25/refactorings.history new file mode 100644 index 00000000..fb3ddb55 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2020/6/25/refactorings.history @@ -0,0 +1,3 @@ + + + \ No newline at end of file diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2020/6/25/refactorings.index b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2020/6/25/refactorings.index new file mode 100644 index 00000000..3d6f8352 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.ltk.core.refactoring/.refactorings/.workspace/2020/6/25/refactorings.index @@ -0,0 +1,3 @@ +1592510876244 Delete resource 'demo_threadx' +1592511041806 Delete 2 resources +1592511103706 Delete resource 'tx/src_generic' diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.ltk.ui.refactoring/dialog_settings.xml b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.ltk.ui.refactoring/dialog_settings.xml new file mode 100644 index 00000000..aa267842 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.ltk.ui.refactoring/dialog_settings.xml @@ -0,0 +1,7 @@ + +
+
+ + +
+
diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.ui.editors/dialog_settings.xml b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.ui.editors/dialog_settings.xml new file mode 100644 index 00000000..50f1edb3 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.ui.editors/dialog_settings.xml @@ -0,0 +1,5 @@ + +
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diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml new file mode 100644 index 00000000..ffb12cc6 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml @@ -0,0 +1,22 @@ + +
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diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml new file mode 100644 index 00000000..2504009a --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml @@ -0,0 +1,31 @@ + +
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diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml new file mode 100644 index 00000000..373b8d71 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml @@ -0,0 +1,4 @@ + + + + \ No newline at end of file diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.metadata/version.ini b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/version.ini new file mode 100644 index 00000000..0c03ef25 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.metadata/version.ini @@ -0,0 +1,3 @@ +#Thu Jun 18 13:20:39 PDT 2020 +org.eclipse.core.runtime=2 +org.eclipse.platform=4.6.3.v20170301-0400 diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.sc.project/.multi b/ports_smp/arc_hs_smp/metaware/example_build/.sc.project/.multi new file mode 100644 index 00000000..305b9131 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.sc.project/.multi @@ -0,0 +1,6 @@ +read ".sc.project/.sc.args.Core1.multi" +read ".sc.project/.sc.args.Core2.multi" +select +load +nohist readq .scrc +nohist nolog gui E> ok_to_load_windows diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.sc.project/.sc.args.Core1.multi b/ports_smp/arc_hs_smp/metaware/example_build/.sc.project/.sc.args.Core1.multi new file mode 100644 index 00000000..8e1e1aeb --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.sc.project/.sc.args.Core1.multi @@ -0,0 +1,10 @@ + +// ARGS: -pset=1 -psetname=Core1 sample_threadx\Debug\sample_threadx.elf -arconnect -connect_ici -av2hs -Xatomic -Xunaligned -core3 -Xmpy_option=mpy -Xtimer0 -Xtimer1 -nooptions -interrupts=32 -ext_interrupts=3 -prop=nsim_isa_num_actionpoints=8 -off=prefer_soft_bp -nogoifmain +macro multi_Core1 + nocomment prop DLL)=^C:\MWLite\MetaWare\arc/../../nSIM/lib/libsim^ + nocomment prop cpunum=$cid timer0_regs=1 timer1_regs=1 cloneable=1 icnts=1 killeds=1 delay_killeds=1 trace_enabled=1 semint)=^C:\MWLite\MetaWare\arc/bin/archw^ semint)=^C:\MWLite\MetaWare\arc/bin/prof.dll^ semint)=^C:\MWLite\MetaWare\arc/bin/profmm.dll^ nsim_isa_family=av2hs nsim_isa_core=3 arcver=83 nsim_isa_atomic_option=1 nsim_isa_shift_option=3 nsim_isa_code_density_option=2 nsim_isa_swap_option=1 nsim_isa_bitscan_option=1 nsim_isa_enable_timer_0=1 nsim_isa_enable_timer_1=1 nsim_isa_number_of_interrupts=32 nsim_isa_number_of_external_interrupts=3 nsim_isa_has_interrupts=1 nsim_connect=2 nsim_connect_ici=2 nsim_isa_unaligned_option=1 nsim_isa_mpy_option=6 nsim_isa_num_actionpoints=8 port=0x378 include_local_symbols=1 prefer_soft_bp=0 flush_pipe=0 prompt=mdb dname=MetaWare sys_cmpd=1 +endm +defclass name=class_multi_Core1 newsys=multi_Core1 clone_noprops=1 system1=ARC_DLL system2=BRC_DLL +defset Core1 [1] +newcmd [Core1] class_multi_Core1 +[Core1] defargs sample_threadx\Debug\sample_threadx.elf diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.sc.project/.sc.args.Core2.multi b/ports_smp/arc_hs_smp/metaware/example_build/.sc.project/.sc.args.Core2.multi new file mode 100644 index 00000000..31d45086 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.sc.project/.sc.args.Core2.multi @@ -0,0 +1,10 @@ + +// ARGS: -pset=2 -psetname=Core2 sample_threadx\Debug\sample_threadx.elf -arconnect -connect_ici -av2hs -Xatomic -Xunaligned -core3 -Xmpy_option=mpy -Xtimer0 -Xtimer1 -nooptions -interrupts=32 -ext_interrupts=3 -prop=nsim_isa_num_actionpoints=8 -off=prefer_soft_bp -nogoifmain +macro multi_Core2 + nocomment prop DLL)=^C:\MWLite\MetaWare\arc/../../nSIM/lib/libsim^ + nocomment prop cpunum=$cid timer0_regs=1 timer1_regs=1 cloneable=1 icnts=1 killeds=1 delay_killeds=1 trace_enabled=1 semint)=^C:\MWLite\MetaWare\arc/bin/archw^ semint)=^C:\MWLite\MetaWare\arc/bin/prof.dll^ semint)=^C:\MWLite\MetaWare\arc/bin/profmm.dll^ nsim_isa_family=av2hs nsim_isa_core=3 arcver=83 nsim_isa_atomic_option=1 nsim_isa_shift_option=3 nsim_isa_code_density_option=2 nsim_isa_swap_option=1 nsim_isa_bitscan_option=1 nsim_isa_enable_timer_0=1 nsim_isa_enable_timer_1=1 nsim_isa_number_of_interrupts=32 nsim_isa_number_of_external_interrupts=3 nsim_isa_has_interrupts=1 nsim_connect=2 nsim_connect_ici=2 nsim_isa_unaligned_option=1 nsim_isa_mpy_option=6 nsim_isa_num_actionpoints=8 port=0x378 include_local_symbols=1 prefer_soft_bp=0 flush_pipe=0 prompt=mdb dname=MetaWare sys_cmpd=1 +endm +defclass name=class_multi_Core2 newsys=multi_Core2 clone_noprops=1 system1=ARC_DLL system2=BRC_DLL +defset Core2 [2] +newcmd [Core2] class_multi_Core2 +[Core2] defargs sample_threadx\Debug\sample_threadx.elf diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.sc.project/.sc.project.windows b/ports_smp/arc_hs_smp/metaware/example_build/.sc.project/.sc.project.windows new file mode 100644 index 00000000..aeadb1b8 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.sc.project/.sc.project.windows @@ -0,0 +1,139 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ver 1.0; + + + + + + + + + + ver 1.0;E:thread_0_counter:0:0;E:thread_0_counter:0:0;E:thread_1_counter:0:0;E:thread_1_counter:0:0;E:thread_2_counter:0:0;E:thread_2_counter:0:0;E:thread_3_counter:0:0;E:thread_3_counter:0:0;E:thread_4_counter:0:0;E:thread_4_counter:0:0;E:thread_5_counter:0:0;E:thread_5_counter:0:0;E:thread_6_counter:0:0;E:thread_6_counter:0:0;E:thread_7_counter:0:0;E:thread_7_counter:0:0;E:_tx_timer_system_clock:0:0;E:_tx_timer_system_clock:0:0;E:_tx_thread_execute_ptr:0:0;M:1:1:0;E:_tx_thread_execute_ptr:0:0;E:thread_1:1:0;E:thread_1:0:0;E:thread_2:0:0;E:thread_2:0:0;E:thread_0:0:0;E:thread_0:0:0;E:_tx_thread_system_stack_ptr:0:0; + + + + + + + + diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.sc.project/.sc.project.xml b/ports_smp/arc_hs_smp/metaware/example_build/.sc.project/.sc.project.xml new file mode 100644 index 00000000..20a01ab0 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.sc.project/.sc.project.xml @@ -0,0 +1,5 @@ + + + + C:\arc_hs_smp\for_intel_04-17-17\.sc.project\.sc.project.windows + diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.sc.project/.sc2.Core1.properties b/ports_smp/arc_hs_smp/metaware/example_build/.sc.project/.sc2.Core1.properties new file mode 100644 index 00000000..5e94ba74 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.sc.project/.sc2.Core1.properties @@ -0,0 +1,25 @@ +ARC5_Core_Version=3 +ARC6_Core_Version=3 +ARC7_Core_Version=3 +ARC_arconnect=1 +ARC_atomic=1 +ARC_connect_ici=2 +ARC_default_ext_interrupts=0 +ARC_default_interrupts=0 +ARC_ext_interrupt_num=3 +ARC_interrupt_num=32 +ARC_interrupt_vector_count=32 +ARC_mpy_emoption=mpy +ARC_mpy_hsoption=mpy +ARC_parallel_port_address=0x378 +ARC_target=ARCSIM +ARC_timer0=1 +ARC_timer1=1 +ARC_unaligned=1 +Execute_to_main=0 +cmd_line_option=-prop\=nsim_isa_num_actionpoints\=8 -prop\=nsim_isa_num_actionpoints\=8 -prop\=nsim_isa_num_actionpoints\=8 -prop\=nsim_isa_num_actionpoints\=8 -prop\=nsim_isa_num_actionpoints\=8 +prefer_sw_bp=0 +program="sample_threadx\\\\Debug\\\\sample_threadx.elf" +v2em_core_version=3 +v2hs_core_version=3 +which_arc=ARCV2HS diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.sc.project/.sc2.Core2.properties b/ports_smp/arc_hs_smp/metaware/example_build/.sc.project/.sc2.Core2.properties new file mode 100644 index 00000000..5e94ba74 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.sc.project/.sc2.Core2.properties @@ -0,0 +1,25 @@ +ARC5_Core_Version=3 +ARC6_Core_Version=3 +ARC7_Core_Version=3 +ARC_arconnect=1 +ARC_atomic=1 +ARC_connect_ici=2 +ARC_default_ext_interrupts=0 +ARC_default_interrupts=0 +ARC_ext_interrupt_num=3 +ARC_interrupt_num=32 +ARC_interrupt_vector_count=32 +ARC_mpy_emoption=mpy +ARC_mpy_hsoption=mpy +ARC_parallel_port_address=0x378 +ARC_target=ARCSIM +ARC_timer0=1 +ARC_timer1=1 +ARC_unaligned=1 +Execute_to_main=0 +cmd_line_option=-prop\=nsim_isa_num_actionpoints\=8 -prop\=nsim_isa_num_actionpoints\=8 -prop\=nsim_isa_num_actionpoints\=8 -prop\=nsim_isa_num_actionpoints\=8 -prop\=nsim_isa_num_actionpoints\=8 +prefer_sw_bp=0 +program="sample_threadx\\\\Debug\\\\sample_threadx.elf" +v2em_core_version=3 +v2hs_core_version=3 +which_arc=ARCV2HS diff --git a/ports_smp/arc_hs_smp/metaware/example_build/.sc.project/.sc2.properties b/ports_smp/arc_hs_smp/metaware/example_build/.sc.project/.sc2.properties new file mode 100644 index 00000000..3e7c291e --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/.sc.project/.sc2.properties @@ -0,0 +1,3 @@ +ARC_parallel_port_address=0x378 +Execute_to_main=1 +cmd_line_option=-multifiles\=Core1,Core2 -OKN diff --git a/ports_smp/arc_hs_smp/metaware/example_build/run_threadx_smp_demo.bat b/ports_smp/arc_hs_smp/metaware/example_build/run_threadx_smp_demo.bat new file mode 100644 index 00000000..ab079d12 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/run_threadx_smp_demo.bat @@ -0,0 +1,4 @@ +set NSIM_MULTICORE=1 +mdb -pset=1 -psetname=Core1 sample_threadx\Debug\sample_threadx.elf -arconnect -connect_ici -av2hs -Xatomic -Xunaligned -core3 -Xmpy_option=mpy -Xtimer0 -Xtimer1 -nooptions -interrupts=32 -ext_interrupts=3 -prop=nsim_isa_num_actionpoints=8 -off=prefer_soft_bp -nogoifmain +mdb -pset=2 -psetname=Core2 sample_threadx\Debug\sample_threadx.elf -arconnect -connect_ici -av2hs -Xatomic -Xunaligned -core3 -Xmpy_option=mpy -Xtimer0 -Xtimer1 -nooptions -interrupts=32 -ext_interrupts=3 -prop=nsim_isa_num_actionpoints=8 -off=prefer_soft_bp -nogoifmain +mdb -multifiles=Core1,Core2 -OKN diff --git a/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/.bp.args b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/.bp.args new file mode 100644 index 00000000..020c9022 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/.bp.args @@ -0,0 +1,3 @@ +location=_tx_thread_system_return +condition_enabled=0 +cond= diff --git a/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/.bp.properties b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/.bp.properties new file mode 100644 index 00000000..8e467ac1 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/.bp.properties @@ -0,0 +1,13 @@ +#Debugger engine properties +#Fri Oct 02 16:50:37 PDT 2015 +ARG_ACTION={"location\=_tx_thread_system_return" "condition_enabled\=0" "cond\=" } +docTitle=break_dialog +LOCATION=_tx_thread_system_return +on_push=bpsaved +TYPE=either +TEMPORARY=false +OK_ON_ENTER=1 +OK_ENABLED=1 +ReadingXML=false +THREAD_SPECIFIC=false +CONDITION_ENABLED=false diff --git a/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/.cproject b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/.cproject new file mode 100644 index 00000000..114a8bd4 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/.cproject @@ -0,0 +1,188 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/.project b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/.project new file mode 100644 index 00000000..a1b15572 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/.project @@ -0,0 +1,26 @@ + + + sample_threadx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/.settings/language.settings.xml b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/.settings/language.settings.xml new file mode 100644 index 00000000..b88c974a --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/.settings/language.settings.xml @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/.settings/org.eclipse.cdt.codan.core.prefs b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 00000000..474b8a1e --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,69 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.codan.checkers.errnoreturn=Warning +org.eclipse.cdt.codan.checkers.errnoreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},implicit\=>false} +org.eclipse.cdt.codan.checkers.errreturnvalue=Error +org.eclipse.cdt.codan.checkers.errreturnvalue.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.checkers.noreturn=Error +org.eclipse.cdt.codan.checkers.noreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},implicit\=>false} +org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation=Error +org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem=Error +org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem=Warning +org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem=Error +org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem=Warning +org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},no_break_comment\=>"no break",last_case_param\=>false,empty_case_param\=>false} +org.eclipse.cdt.codan.internal.checkers.CatchByReference=Warning +org.eclipse.cdt.codan.internal.checkers.CatchByReference.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},unknown\=>false,exceptions\=>()} +org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem=Error +org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization=Warning +org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},skip\=>true} +org.eclipse.cdt.codan.internal.checkers.ExternalBindingProblem=Warning +org.eclipse.cdt.codan.internal.checkers.ExternalBindingProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.InvalidArguments=Error +org.eclipse.cdt.codan.internal.checkers.InvalidArguments.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem=Error +org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem=Error +org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem=Error +org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} +org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem=Error 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+org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}} diff --git a/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/arc.c b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/arc.c new file mode 100644 index 00000000..c5a58751 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/arc.c @@ -0,0 +1,150 @@ +/* ------------------------------------------ + * Copyright (c) 2016, Synopsys, Inc. All rights reserved. + + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + + * 1) Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + + * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + --------------------------------------------- */ + +#include "arc.h" + +/********************************************************************* + * Core Intc setup + *********************************************************************/ + +#define AUX_STAT32 0x00a + +#define AUX_IVT_BASE 0x025 +#define AUX_VOL 0x05e + +#define AUX_IRQ_CTRL 0x00E +#define AUX_IRQ_SEL 0x40b +#define AUX_IRQ_PRIO 0x206 + +#define INTC_DEF_PRIO 1 + + +/********************************************************************* + * Timers uses timer0 + *********************************************************************/ + +#define AUX_TIM0_CNT 0x021 +#define AUX_TIM0_CTRL 0x022 +#define AUX_TIM0_LIMIT 0x023 + + + +/********************************************************************* + * Inter Core interruts + *********************************************************************/ + +#define AUX_MCIP_BCR 0x0d0 +#define AUX_MCIP_CMD 0x600 +#define AUX_MCIP_WDATA 0x601 +#define AUX_MCIP_READBK 0x602 + +#define CMD_ICI_GENERATE_IRQ 0x1 +#define CMD_ICI_GENERATE_ACK 0x2 +#define CMD_ICI_READ_STATUS 0x3 +#define CMD_ICI_CHECK_SOURCE 0x4 + + + +void _tx_thread_smp_initialize_wait(void); +void arc_timer_setup(unsigned int cycles); + + +void arc_cpu_init(void) +{ + extern char VECT_TABLE_BASE[]; // from sample_threadx.lcf + _sr((unsigned int)VECT_TABLE_BASE, AUX_IVT_BASE); + + /* 0xc000_0000 in uncached */ + _sr(0xc0000000, AUX_VOL); + + /* setup irqs to interrupt at default interruption threshhold */ + _sr(IRQ_TIMER, AUX_IRQ_SEL); + _sr(INTC_DEF_PRIO, AUX_IRQ_PRIO); + + _sr(IRQ_IPI, AUX_IRQ_SEL); + _sr(INTC_DEF_PRIO, AUX_IRQ_PRIO); + +#ifndef TX_ZERO_BASED_CORE_ID + if (smp_processor_id() > 1) +#else + if (smp_processor_id() > 0) +#endif + _tx_thread_smp_initialize_wait(); + + arc_timer_setup(19999); +} + + +void arc_timer_setup(unsigned int cycles) +{ + _sr(cycles, AUX_TIM0_LIMIT); /* interupt after CNT == @cycles */ + _sr(0, AUX_TIM0_CNT); /* initial CNT */ + _sr(0x3, AUX_TIM0_CTRL); /* Interrupt enable, count only when NOT halted */ +} + + + +static inline void __mcip_cmd(unsigned int cmd, unsigned int param) +{ + struct mcip_cmd { + unsigned int cmd:8, param:16, pad:8; + } buf; + + buf.pad = 0; + buf.cmd = cmd; + buf.param = param; + + _sr(*(unsigned int *)&buf, AUX_MCIP_CMD); +} + + +void arc_ici_send(unsigned int cpu) +{ + int ipi_pend; + + __mcip_cmd(CMD_ICI_READ_STATUS, cpu); + ipi_pend = _lr(AUX_MCIP_READBK); + if (!ipi_pend) + __mcip_cmd(CMD_ICI_GENERATE_IRQ, cpu); +} + + +void arc_ici_handler(void) +{ + unsigned int senders, c; + + + __mcip_cmd(CMD_ICI_CHECK_SOURCE, 0); + + senders = _lr(AUX_MCIP_READBK); /* 1,2,4,8... */ + + /* No support interrupt coalescing yet */ + c = __ffs(senders); /* 0,1,2,3 */ + __mcip_cmd(CMD_ICI_GENERATE_ACK, c); +} diff --git a/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/arc.h b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/arc.h new file mode 100644 index 00000000..df7e59d8 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/arc.h @@ -0,0 +1,120 @@ +/* ------------------------------------------ + * Copyright (c) 2016, Synopsys, Inc. All rights reserved. + + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + + * 1) Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + + * 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + --------------------------------------------- */ + +#include "arc/arc_reg.h" + +/********************************************************************* + * Core Intc setup + *********************************************************************/ + +#ifndef __ARC_HDR__ +#define __ARC_HDR__ + +#ifndef NULL +#define NULL 0 +#endif + +#define IRQ_TIMER 16 +#define IRQ_IPI 19 + +#define CORE_PRIMARY 1 +#define CORE_SECONDARY 2 + +#define INTERRUPT_ENABLE (1 << 4) // according ISA (SETI instruction details) +#define INTERRUPT_LEVEL(L) ((L) << 0)//simple macro for user-friendly name conversion + + + +static inline int __ffs(unsigned long x) +{ + int n; + + asm volatile( + " ffs.f %0, %1 \n" /* 0..31; Z set if src 0 */ + " mov.z %0, 0 \n" /* return 0 if 0 */ + : "=r"(n) + : "r"(x) + : "cc"); + + return n; +} + +#define AUX_ID 0x004 + +static inline int smp_processor_id() +{ + unsigned int id = _lr(AUX_ID); + return (id >> 8) & 0xFF; +} + +static inline void arc_halt(void) +{ + asm volatile("flag 1\n"); +} + +/* no need for volatile */ +typedef unsigned int spinlock_t; + +static inline void spinlock_acquire(unsigned int *lock) +{ + unsigned int val; + + asm volatile( + "1: llock %[val], [%[slock]] \n" + " breq %[val], %[LOCKED], 1b \n" /* spin while LOCKED */ + " scond %[LOCKED], [%[slock]] \n" /* acquire */ + " bnz 1b \n" + " dmb 3 \n" + : [val] "=&r" (val) + : [slock] "r" (lock), + [LOCKED] "r" (1) + : "memory", "cc"); +} + +static inline void spinlock_release(unsigned int *lock) +{ + __asm__ __volatile__( + " dmb 3 \n" + " st %[UNLOCKED], [%[slock]] \n" + : + : [slock] "r" (lock), + [UNLOCKED] "r" (0) + : "memory"); +} + +static inline void arc_enable_ints(void) +{ + _seti(1); +} + +extern void arc_timer_setup(unsigned int); +extern void arc_register_isr(int irq, void (*fn)(int), int arg_to_isr); +extern void arc_ici_send(unsigned int cpu); + +#endif diff --git a/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/crt1cl.s b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/crt1cl.s new file mode 100644 index 00000000..474e4e70 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/crt1cl.s @@ -0,0 +1,166 @@ +; Copyright (c) 2000-2009 ARC International + .file "crt1cl.s" + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;;;; Startup +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + .text + .weak _SDA_BASE_ + + .macro jmpl,target + jl target ; "large" model call + .endm + + .on assume_short, assume_nop_short + .define S, _s + + ; Indicate whether registers should be initialized with 0 + ; This might be desirable if executing in an environment where + ; registers may contain undefined values on startup. + .define PERFORM_REGISTER_INITIALIZATION, 0 + + .section .text$crt00, text + .global _start + .type _start, @function + .reloc __crt_callmain, 0 +_start: + +.if PERFORM_REGISTER_INITIALIZATION + ; Initialize the register file. + ; Compiled code may generate sub r0, r1, r1, expecting to + ; load 0 into r0, but in some execution environments the individual + ; reads of r1 for the two source operands may return different + ; (garbage) values if r1 had never been written to since reset. + + .ifdef _ARC_RF16 + .irep num, 1, 2, 3, 10, 11, 12, 13, 14, 15 + mov r\&num, 0 + .endr + .else + .irep num, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25 + mov r\&num, 0 + .endr + .endif + +.endif + + .weak __xcheck + +.ifdef _PICTABLE + ; under PICTABLE, r0 is assumed to contain the base of the data segment + ; so must preserve it. __xcheck modifies only r0 and r1 and is + ; position-independent + mov r2, r0 + mov.f r0, __xcheck + beq .Linit_pic + + bl __xcheck + mov r0, r2 + + .Linit_pic: + .weak __PICTABLE__ + ; In PIC mode, we assume that we were loaded by a loader and may not + ; reside at the addresses that the ELF file was linked with. In + ; this case, the address of where the data segment has been loaded + ; is passed to _start in the r0 register. We figure out the new code + ; segment base ourselves. + mov r2, __PICTABLE__ + sub.f 0, r2, 0 + nop ; required for -a4 -core5 + beq no_pic + bl _init_pic + +no_pic: +.endif + + .Lsetstack: + ; like smp_processor_id() from arc.h + ; AUX_IDENTITY Reg [ 3 2 1 0 ] + ; ^^^ => 0 for Master, !0 otherwise + ; Note: this is setup for 2 cores and needs to be augmented if more than 2 cores + lr r0, [identity] + lsr r0, r0, 8 + bmsk r0, r0, 7 + .ifndef TX_ZERO_BASED_CORE_ID + breq r0, 2, .Lsecondary + .else + breq r0, 1, .Lsecondary + .endif + mov sp, STACK1_END ; initialize stack pointer, core 1 + b .Lcontinue +.Lsecondary: + mov sp, STACK2_END ; initialize stack pointer, core 2 +.Lcontinue: + mov gp, _SDA_BASE_ ; initialize small-data base register + mov fp, 0 ; initialize frame pointer + +__crt_start: + ; various components may get placed here by the linker: + ; priority optional component command-line option + ;---------------------------------------------------------------------- + ; 10 _init_ldi,_init_jli,_init_ei, automated + ; _init_sjli + ; 20 __crt_initcopy -Hcrt_initcopy + ; 25 __crt_initbss -Hcrt_initbss + ; 30 __crt_invcache -Hcrt_invcache + ; 70 __crt_inittimer -Hcrt_inittimer + ; 80 _init forced included below + ; 90 __crt_callmain forced, with + ; optional -Hcrt_argv + + .cfa_bf _start + + .section .text$crt99, text + .sectflag .text$crt99, include +; INIT CODE FALLS THROUGH TO _exit_halt + .cfa_ef + + .global _exit_halt + .type _exit_halt, @function +_exit_halt: + .cfa_bf _exit_halt + + flag 0x01 + nop + .if ! $is_arcv2 + ; ARC 700 serializes on 'flag', so no way to get back to here. + nop + nop + .endif + b _exit_halt + + .reloc main, 0; force main in if its in a library + .cfa_ef + + .section .text$crt80, text + .sectflag .text$crt80, include +__crt_init: + bl _init + + .previous + ; weak versions of small data symbols normally defined by the linker. + .weak _fsbss + .weak _esbss + .set _fsbss,0 + .set _esbss,0 + + ; weak versions of BSS section symbols in case there is no .bss section + .weak _fbss + .weak _ebss + .set _fbss,0 + .set _ebss,0 + + ; weak versions of heap section boundaries. If a .heap section + ; is provided, our low-level allocator "sbrk" allocates within it. + ; If no .heap is provided, we allocate from _end to the end of memory. + .weak _fheap + .weak _eheap + .set _fheap,0 + .set _eheap,0 + + ; reference the beginning of the stack for debugger's stack checking + .weak _fstack + .set _fstack,0 + + .end + diff --git a/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/crti.s b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/crti.s new file mode 100644 index 00000000..89a46599 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/crti.s @@ -0,0 +1,72 @@ +; Copyright (c) 2002-2005 ARC International + .file "crti.s" + .option %reg + .global _init, _fini + .extern __mw_cpp_init, __mw_cpp_exit + .macro jmpl,target + .if $core_version > 5 + jl target ; "large" model call + .else + lr %blink, [%status] + add %blink, %blink, 3 + j target + .endif + .endm + .if $isa == "ARCompact" + .on assume_short + .endif + + .section ".init",text +_init: + .if $isa == "ARC" + st %fp, [%sp, 0] + st %blink, [%sp, 4] + mov %fp, %sp + sub %sp, %sp, 16 + .else + .cfa_bf _init + push %blink + .cfa_push {%blink} + .endif + + .section ".init$999999", text, 1, 2, check_text_align=0 +; this is now brought in by a reference generated by the compiler +; jmpl __mw_cpp_init + .if $isa == "ARC" + ld %blink, [%fp, 4] + j.d [%blink] + ld.a %fp, [%sp, 16] + .else + pop %blink + .cfa_pop {%blink} + j [%blink] + .cfa_ef + .endif + + .section ".fini", text +_fini: + .if $isa == "ARC" + st %fp, [%sp, 0] + st %blink, [%sp, 4] + mov %fp, %sp + sub %sp, %sp, 16 + .else + .cfa_bf _fini + push %blink + .cfa_push {%blink} + .endif + + .section ".fini$999999", text, 1, 2, check_text_align=0 +; jmpl __mw_cpp_exit + .if $isa == "ARC" + ld %blink, [%fp, 4] + j.d [%blink] + ld.a %fp, [%sp, 16] + .else + pop %blink + .cfa_pop {%blink} + j [%blink] + .cfa_ef + .endif + .end + diff --git a/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/sample_threadx.c b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/sample_threadx.c new file mode 100644 index 00000000..107b90a7 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/sample_threadx.c @@ -0,0 +1,374 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); +void arc_cpu_init(void); + + +/* Define main entry point. */ + +int main() +{ + + /* ARC-specific initialization. */ + arc_cpu_init(); + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); + + return(0); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + +/* Define the test threads. */ +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + diff --git a/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/sample_threadx.cmd b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/sample_threadx.cmd new file mode 100644 index 00000000..ac4f3a6f --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/sample_threadx.cmd @@ -0,0 +1,61 @@ +// +// This is the linker script example (SRV3-style). +// (c) Synopsys, 2013 +// +// + +//number of exceptions and interrupts +NUMBER_OF_EXCEPTIONS = 16;//it is fixed (16) +NUMBER_OF_INTERRUPTS = 5;//depends on HW configuration + +//define Interrupt Vector Table size +IVT_SIZE_ITEMS = (NUMBER_OF_EXCEPTIONS + NUMBER_OF_INTERRUPTS);//the total IVT size (in "items") +IVT_SIZE_BYTES = IVT_SIZE_ITEMS * 4;//in bytes + +//define ICCM and DCCM locations +MEMORY { + + ICCM: ORIGIN = 0x00000000, LENGTH = 128K + DCCM: ORIGIN = 0x80000000, LENGTH = 128K +} + +//define sections and groups +SECTIONS { + GROUP: { + VECT_TABLE_BASE = .; + .ivt (TEXT) : # Interrupt table + { + ___ivt1 = .; + * (.ivt) + ___ivt2 = .; + // Make the IVT at least IVT_SIZE_BYTES + . += (___ivt2 - ___ivt1 < IVT_SIZE_BYTES) ? (IVT_SIZE_BYTES - (___ivt2 - ___ivt1)) : 0; + } + .ivh (TEXT) : // Interrupt handlers + + //TEXT sections + .text? : { *('.text$crt*') } + * (TEXT): {} + //Literals + * (LIT): {} + } > ICCM + + GROUP: { + //data sections + .sdata?: {} + .sbss?: {} + *(DATA): {} + *(BSS): {} + //stack + .stack ALIGN(4) SIZE(DEFINED _STACKSIZE?_STACKSIZE:4096): {} + + .stack1 ALIGN(4) SIZE(4096): {} + STACK1_END = .; + .stack2 ALIGN(4) SIZE(4096): {} + STACK2_END = .; + + //heap (empty) + .heap? ALIGN(4) SIZE(DEFINED _HEAPSIZE?_HEAPSIZE:0): {} + .free_memory: {} + } > DCCM + } diff --git a/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/tx_initialize_low_level.s b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/tx_initialize_low_level.s new file mode 100644 index 00000000..00cdffa2 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/tx_initialize_low_level.s @@ -0,0 +1,307 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; + .equ IRQ_SELECT, 0x40B + +; +; +; /* Define section for placement after all linker allocated RAM memory. This +; is used to calculate the first free address that is passed to +; tx_appication_define, soley for the ThreadX application's use. */ +; + .section ".free_memory","aw" + .align 4 + .global _tx_first_free_address +_tx_first_free_address: + .space 4 +; +; + .text +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level SMP/ARC_HS/MetaWare */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + .global _tx_initialize_low_level + .type _tx_initialize_low_level, @function +_tx_initialize_low_level: + +; +; /* Save the system stack pointer. */ +; _tx_thread_system_stack_ptr[0] = (VOID_PTR) (sp); +; + st sp, [gp, _tx_thread_system_stack_ptr@sda] ; Save system stack pointer +; +; +; /* Pickup the first available memory address. */ +; + mov r0, _tx_first_free_address ; Pickup first free memory address +; +; /* Save the first available memory address. */ +; _tx_initialize_unused_memory = (VOID_PTR) _end; +; + st r0, [gp, _tx_initialize_unused_memory@sda] +; +; +; /* Done, return to caller. */ +; + j_s.d [blink] ; Return to caller + nop +;} +; +; +; /* Define default vector table entries. */ +; + .global _tx_memory_error +_tx_memory_error: + flag 1 + nop + nop + nop + b _tx_memory_error + + .global _tx_instruction_error +_tx_instruction_error: + flag 1 + nop + nop + nop + b _tx_instruction_error + + .global _tx_ev_machine_check +_tx_ev_machine_check: + flag 1 + nop + nop + nop + b _tx_ev_machine_check + + .global _tx_ev_tblmiss_inst +_tx_ev_tblmiss_inst: + flag 1 + nop + nop + nop + b _tx_ev_tblmiss_inst + + .global _tx_ev_tblmiss_data +_tx_ev_tblmiss_data: + flag 1 + nop + nop + nop + b _tx_ev_tblmiss_data + + .global _tx_ev_protection_viol +_tx_ev_protection_viol: + flag 1 + nop + nop + nop + b _tx_ev_protection_viol + + .global _tx_ev_privilege_viol +_tx_ev_privilege_viol: + flag 1 + nop + nop + nop + b _tx_ev_privilege_viol + + .global _tx_ev_software_int +_tx_ev_software_int: + flag 1 + nop + nop + nop + b _tx_ev_software_int + + .global _tx_ev_trap +_tx_ev_trap: + flag 1 + nop + nop + nop + b _tx_ev_trap + + .global _tx_ev_extension +_tx_ev_extension: + flag 1 + nop + nop + nop + b _tx_ev_extension + + .global _tx_ev_divide_by_zero +_tx_ev_divide_by_zero: + flag 1 + nop + nop + nop + b _tx_ev_divide_by_zero + + .global _tx_ev_dc_error +_tx_ev_dc_error: + flag 1 + nop + nop + nop + b _tx_ev_dc_error + + .global _tx_ev_maligned +_tx_ev_maligned: + flag 1 + nop + nop + nop + b _tx_ev_maligned + + .global _tx_unsued_0 +_tx_unsued_0: + flag 1 + nop + nop + nop + b _tx_unsued_0 + + .global _tx_unused_1 +_tx_unused_1: + flag 1 + nop + nop + nop + b _tx_unused_1 + + .global _tx_timer_0 +_tx_timer_0: +; +; /* By default, setup Timer 0 as the ThreadX timer interrupt. */ +; + sub sp, sp, 160 ; Allocate an interrupt stack frame + st blink, [sp, 16] ; Save blink (blink must be saved before _tx_thread_context_save) + bl _tx_thread_context_save ; Save interrupt context +; +; /* Call ThreadX timer interrupt processing. */ +; + bl.d _tx_timer_interrupt ; Call ThreadX timer processing + sub sp, sp, 16 ; Allocate stack space (delay slot) + add sp, sp, 16 ; Recover stack space + +; /* Clear Timer 0 interrupt. */ +; + lr r0, [CONTROL0] ; Read control register + and r0, r0, 0xFFFFFFF7 ; Clear timer 0 interrupt bit + sr r0, [CONTROL0] ; Store control register + ld r0, [sp, 16] ; Recover r0 +; + b _tx_thread_context_restore ; Restore interrupt context +; flag 1 +; nop +; nop +; nop +; b _tx_timer_0 + + .global _tx_timer_1 +_tx_timer_1: + flag 1 + nop + nop + nop + b _tx_timer_1 + + .global _tx_undefined_0 +_tx_undefined_0: + flag 1 + nop + nop + nop + b _tx_undefined_0 + + .global _tx_smp_inter_core +_tx_smp_inter_core: +; +; /* Define the inter-core interrupt. */ +; + sub sp, sp, 160 ; Allocate an interrupt stack frame + st blink, [sp, 16] ; Save blink (blink must be saved before _tx_thread_context_save) + bl _tx_thread_context_save ; Save interrupt context +; +; /* Call ARC inter-core interrupt processing. */ +; + bl.d arc_ici_handler ; Call ARC inter-core processing + sub sp, sp, 16 ; Allocate stack space (delay slot) + add sp, sp, 16 ; Recover stack space +; + b _tx_thread_context_restore ; Restore interrupt context +; flag 1 +; nop +; nop +; nop +; b _tx_undefined_1 + + .global _tx_undefined_2 +_tx_undefined_2: + flag 1 + nop + nop + nop + b _tx_undefined_2 + + .end diff --git a/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/vectors.s b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/vectors.s new file mode 100644 index 00000000..d1fbfa27 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/vectors.s @@ -0,0 +1,29 @@ + +.file "vectors.s" +.section .ivt,text +;; This directive forces this section to stay resident even if stripped out by the -zpurgetext linker option +.sectflag .ivt,include + +;// handler's name type number name offset in IVT (hex/dec) +.long _start ; exception 0 program entry point offset 0x0 0 +.long _tx_memory_error ; exception 1 memory_error offset 0x4 4 +.long _tx_instruction_error ; exception 2 instruction_error offset 0x8 8 +.long _tx_ev_machine_check ; exception 3 EV_MachineCheck offset 0xC 12 +.long _tx_ev_tblmiss_inst ; exception 4 EV_TLBMissI offset 0x10 16 +.long _tx_ev_tblmiss_data ; exception 5 EV_TLBMissD offset 0x14 20 +.long _tx_ev_protection_viol ; exception 6 EV_ProtV offset 0x18 24 +.long _tx_ev_privilege_viol ; exception 7 EV_PrivilegeV offset 0x1C 28 +.long _tx_ev_software_int ; exception 8 EV_SWI offset 0x20 32 +.long _tx_ev_trap ; exception 9 EV_Trap offset 0x24 36 +.long _tx_ev_extension ; exception 10 EV_Extension offset 0x28 40 +.long _tx_ev_divide_by_zero ; exception 11 EV_DivZero offset 0x2C 44 +.long _tx_ev_dc_error ; exception 12 EV_DCError offset 0x30 48 +.long _tx_ev_maligned ; exception 13 EV_Maligned offset 0x34 52 +.long _tx_unsued_0 ; exception 14 unused offset 0x38 56 +.long _tx_unused_1 ; exception 15 unused offset 0x3C 60 +.long _tx_timer_0 ; IRQ 16 Timer 0 offset 0x40 64 +.long _tx_timer_1 ; IRQ 17 Timer 1 offset 0x44 68 +.long _tx_undefined_0 ; IRQ 18 offset 0x48 72 +.long _tx_smp_inter_core ; IRQ 19 offset 0x4C 76 +.long _tx_undefined_2 ; IRQ 20 offset 0x50 80 + diff --git a/ports_smp/arc_hs_smp/metaware/example_build/tx/.cproject b/ports_smp/arc_hs_smp/metaware/example_build/tx/.cproject new file mode 100644 index 00000000..92d41cef --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/tx/.cproject @@ -0,0 +1,181 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/arc_hs_smp/metaware/example_build/tx/.project b/ports_smp/arc_hs_smp/metaware/example_build/tx/.project new file mode 100644 index 00000000..10681969 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/tx/.project @@ -0,0 +1,48 @@ + + + tx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + inc_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_smp/inc + + + inc_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/inc + + + src_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_smp/src + + + src_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/src + + + diff --git a/ports_smp/arc_hs_smp/metaware/example_build/tx/.settings/language.settings.xml b/ports_smp/arc_hs_smp/metaware/example_build/tx/.settings/language.settings.xml new file mode 100644 index 00000000..fbb81b1a --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/example_build/tx/.settings/language.settings.xml @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/arc_hs_smp/metaware/inc/tx_port.h b/ports_smp/arc_hs_smp/metaware/inc/tx_port.h new file mode 100644 index 00000000..4513cc1d --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/inc/tx_port.h @@ -0,0 +1,415 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h SMP/ARC_HS/MetaWare */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Remove volatile for ThreadX source on the ARC. This is because the ARC + compiler generates different non-cache r/w access when using volatile + that is different from the assembly language access of the same + global variables in ThreadX. */ + +#ifdef TX_SOURCE_CODE +#define volatile +#else +#ifdef NX_SOURCE_CODE +#define volatile +#else +#ifdef FX_SOURCE_CODE +#define volatile +#else +#ifdef UX_SOURCE_CODE +#define volatile +#endif +#endif +#endif +#endif + +/************* Define ThreadX SMP constants. *************/ + +/* Define the ThreadX SMP maximum number of cores. */ + +#ifndef TX_THREAD_SMP_MAX_CORES +#define TX_THREAD_SMP_MAX_CORES 2 +#endif + + +/* Define the ThreadX SMP core mask. */ + +#ifndef TX_THREAD_SMP_CORE_MASK +#define TX_THREAD_SMP_CORE_MASK 0x3 /* Where bit 0 represents Core 0, bit 1 represents Core 1, etc. */ +#endif + + +/* Define INLINE_DECLARE to whitespace for MetaWare compiler. */ + +#define INLINE_DECLARE + + +/* Define dynamic number of cores option. When commented out, the number of cores is static. */ + +/* #define TX_THREAD_SMP_DYNAMIC_CORE_MAX */ + + +/* Define ThreadX SMP initialization macro. */ + +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION + + +/* Define ThreadX SMP pre-scheduler initialization. */ + +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION + + +/* Enable the inter-core interrupt logic. */ + +#define TX_THREAD_SMP_INTER_CORE_INTERRUPT + + +/* Determine if there is customer-specific wakeup logic needed. */ + +#ifdef TX_THREAD_SMP_WAKEUP_LOGIC + +/* Include customer-specific wakeup code. */ + +#include "tx_thread_smp_core_wakeup.h" +#else + +#ifdef TX_THREAD_SMP_DEFAULT_WAKEUP_LOGIC + +/* Default wakeup code. */ +#define TX_THREAD_SMP_WAKEUP_LOGIC +#define TX_THREAD_SMP_WAKEUP(i) _tx_thread_smp_core_preempt(i) +#endif +#endif + + +/* Ensure that the in-line resume/suspend define is not allowed. */ + +#ifdef TX_INLINE_THREAD_RESUME_SUSPEND +#undef TX_INLINE_THREAD_RESUME_SUSPEND +#endif + +/************* End ThreadX SMP constants. *************/ + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 800 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 2048 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARC HS port. */ + +#define TX_INT_ENABLE 0x0000001F /* Enable all interrupts */ +#define TX_INT_DISABLE_MASK 0x00000000 /* Disable all interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE _tx_thread_smp_time_get() +#endif +#else +#ifndef TX_TRACE_TIME_SOURCE +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 VOID *__mw_threadx_tls; \ + int __mw_errnum; \ + VOID (*__mw_thread_exit)(struct TX_THREAD_STRUCT *); +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + +#if __HIGHC__ + +/* The MetaWare thread safe C/C++ runtime library needs space to + store thread specific information. In addition, a function pointer + is also supplied so that certain thread-specific resources may be + released upon thread termination and/or thread completion. */ + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) \ + thread_ptr -> __mw_threadx_tls = 0; \ + thread_ptr -> __mw_errnum = 0; \ + thread_ptr -> __mw_thread_exit = TX_NULL; +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) \ + if (thread_ptr -> __mw_thread_exit) \ + (thread_ptr -> __mw_thread_exit) (thread_ptr); +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) \ + if (thread_ptr -> __mw_thread_exit) \ + (thread_ptr -> __mw_thread_exit) (thread_ptr); + +#else + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + +#endif + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/************* Define ThreadX SMP data types and function prototypes. *************/ + +struct TX_THREAD_STRUCT; + + +/* Define the ThreadX SMP protection structure. */ + +typedef struct TX_THREAD_SMP_PROTECT_STRUCT +{ + ULONG tx_thread_smp_protect_in_force; + struct TX_THREAD_STRUCT * + tx_thread_smp_protect_thread; + ULONG tx_thread_smp_protect_core; + ULONG tx_thread_smp_protect_count; + + /* Implementation specific information follows. */ + + ULONG tx_thread_smp_protect_get_caller; + ULONG tx_thread_smp_protect_status32; + ULONG tx_thread_smp_protect_release_caller; +} TX_THREAD_SMP_PROTECT; + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_smp_protect(); +#define TX_RESTORE _tx_thread_smp_unprotect(interrupt_save); + + +/************* End ThreadX SMP data type and function prototype definitions. *************/ + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/ARC_HS/MetaWare Version 6.0.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + + + + + diff --git a/ports_smp/arc_hs_smp/metaware/readme_threadx.txt b/ports_smp/arc_hs_smp/metaware/readme_threadx.txt new file mode 100644 index 00000000..512488da --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/readme_threadx.txt @@ -0,0 +1,205 @@ + Microsoft's Azure RTOS ThreadX SMP for ARC HS + + Using the MetaWare Tools + +1. Open the ThreadX SMP Workspace + +In order to build the ThreadX SMP library and the ThreadX SMP demonstration +first load the Azure RTOS Workspace, which is located inside the "example_build" +directory. + + +2. Building the ThreadX SMP run-time Library + +Building the ThreadX SMP library is easy; simply select the ThreadX library project +file "tx" and then select the build button. You should now observe the compilation +and assembly of the ThreadX SMP library. This project build produces the ThreadX SMP +library file tx.a. + + +3. Demonstration System + +The ThreadX demonstration is designed to execute under the MetaWare ARC HS SMP +simulation. The instructions that follow describe how to get the ThreadX SMP +demonstration running. + +Building the demonstration is easy; simply select the demonstration project file +"sample_threadx." At this point, select the build button and observe the +compilation, assembly, and linkage of the ThreadX SMP demonstration application. + +After the demonstration is built, execute the "run_threadx_smp_demo.bat" batch file +to invoke and load the ThreadX SMP demonstration. + +You are now ready to execute the ThreadX demonstration system. Select +breakpoints and data watches to observe the execution of the sample_threadx.c +SMP application. + + +4. System Initialization + +The system entry point using the MetaWare tools is at the label _start. +This is defined within the crt1.s file supplied by MetaWare. In addition, +this is where all static and global preset C variable initialization +processing is called from. + +After the MetaWare startup function completes, ThreadX initialization is +called. The main initialization function is _tx_initialize_low_level and +is located in the file tx_initialize_low_level.s. This function is +responsible for setting up various system data structures, and interrupt +vectors. + +By default free memory is assumed to start at the section .free_memory +which is referenced in tx_initialize_low_level.s and located in the +linker control file after all the linker defined RAM addresses. This is +the address passed to the application definition function, tx_application_define. + + +5. Register Usage and Stack Frames + +The ARC compiler assumes that registers r0-r12 are scratch registers for +each function. All other registers used by a C function must be preserved +by the function. ThreadX takes advantage of this in situations where a +context switch happens as a result of making a ThreadX service call (which +is itself a C function). In such cases, the saved context of a thread is +only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 LP_START blink + 0x08 LP_END fp + 0x0C LP_COUNT r26 + 0x10 blink r25 + 0x14 ilink r24 + 0x18 fp r23 + 0x1C r26 r22 + 0x20 r25 r21 + 0x24 r24 r20 + 0x28 r23 r19 + 0x2C r22 r18 + 0x30 r21 r17 + 0x34 r20 r16 + 0x38 r19 r15 + 0x3C r18 r14 + 0x40 r17 r13 + 0x44 r16 STATUS32 + 0x48 r15 r30 + 0x4C r14 + 0x50 r13 + 0x54 r12 + 0x58 r11 + 0x5C r10 + 0x60 r9 + 0x64 r8 + 0x68 r7 + 0x6C r6 + 0x70 r5 + 0x74 r4 + 0x78 r3 + 0x7C r2 + 0x80 r1 + 0x84 r0 + 0x88 r30 + 0x8C r58 - ACCL (optional) + 0x90 r59 - ACCH (optional) + 0x94 reserved + 0x98 reserved + 0x9C bta + 0xA0 point of interrupt + 0xA4 STATUS32 + + + +6. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the build_threadx.bat +file to remove the -g option and enable all compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for the +ARC HS processor, including support for software interrupts and fast +hardware interrupts. + +7.1 Software Interrupt Handling + +The following template should be used for software interrupts +managed by ThreadX: + + .global _tx_interrupt_x +_tx_interrupt_x: + sub sp, sp, 160 ; Allocate an interrupt stack frame + st blink, [sp, 16] ; Save blink (blink must be saved before _tx_thread_context_save) + bl _tx_thread_context_save ; Save interrupt context +; +; /* Application ISR processing goes here! Your ISR can be written in +; assembly language or in C. If it is written in C, you must allocate +; 16 bytes of stack space before it is called. This must also be +; recovered once your C ISR return. An example of this is shown below. +; +; If the ISR is written in assembly language, only the compiler scratch +; registers are available for use without saving/restoring (r0-r12). +; If use of additional registers are required they must be saved and +; restored. */ +; + bl.d your_ISR_written_in_C ; Call an ISR written in C + sub sp, sp, 16 ; Allocate stack space (delay slot) + add sp, sp, 16 ; Recover stack space + +; + b _tx_thread_context_restore ; Restore interrupt context + + +The application handles interrupts directly, which necessitates all register +preservation by the application's ISR. ISRs that do not use the ThreadX +_tx_thread_context_save and _tx_thread_context_restore routines are not +allowed access to the ThreadX API. In addition, custom application ISRs +should be higher priority than all ThreadX-managed ISRs. + + +8. ThreadX Timer Interrupt + +ThreadX SMP requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional but the remainder of +ThreadX will still run. + +By default, the ThreadX timer interrupt is mapped to the ARC HS auxiliary +timer 0, which generates low priority interrupts on interrupt vector 16. +It is easy to change the timer interrupt source and priority by changing the +setup code in tx_initialize_low_level.s. In addition, the ThreadX SMP timer +is mapped to core 0. To change to another core, please edit arc.c and +_tx_timer_interrupt.s. Only one core should be used as the ThreadX SMP +periodic timer interrupt source. + + +9. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX 6.0.1 for ARC HS using MetaWare tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_context_restore.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_context_restore.s new file mode 100644 index 00000000..e11426d0 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_context_restore.s @@ -0,0 +1,313 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; + .equ BTA, 0x412 +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore SMP/ARC_HS/MetaWare */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + .global _tx_thread_context_restore + .type _tx_thread_context_restore, @function +_tx_thread_context_restore: +; +; /* Note: it is assumed that the stack pointer is in the same position now as +; it was after the last context save call. */ +; +; /* Lockout interrupts. */ +; + clri ; Disable interrupts + nop ; Delay for interrupts to really be disabled + + .ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + bl.d _tx_execution_isr_exit ; Call the ISR exit function + sub sp, sp, 16 ; ..allocating some space on the stack + add sp, sp, 16 ; Recover the stack space + .endif +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state) +; { +; + lr r3, [IDENTITY] ; Pickup core ID + xbfu r3, r3, 8, 8 ; Shift down and isolate core ID + .ifndef TX_ZERO_BASED_CORE_ID + sub r3, r3, 1 ; Subtract 1 to make 0-based + .endif + asl r3, r3, 2 ; Build index into core arrays + mov r0, _tx_thread_system_state ; Build address of system state + add r1, r0, r3 ; + ld r0, [r1] ; Pickup system state + sub r0, r0, 1 ; Decrement the system state + st r0, [r1] ; Store the new system state + breq r0, 0, __tx_thread_not_nested_restore ; If zero, not a nested interrupt +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + +__tx_thread_nested_restore: + + .ifndef TX_DISABLE_LP + ld r0, [sp, 4] ; Recover LP_START + sr r0, [LP_START] ; Restore LP_START + ld r4, [sp, 8] ; Recover LP_END + sr r4, [LP_END] ; Restore LP_END + ld r2, [sp, 12] ; Recover LP_COUNT + mov LP_COUNT, r2 + .endif + + ld r2, [sp, 156] ; Pickup BTA + sr r2, [BTA] ; Recover BTA + .ifdef TX_ENABLE_ACC + ld r58, [sp, 140] ; Recover r58 + ld r59, [sp, 144] ; Recover r59 + .endif + ld blink, [sp, 16] ; Recover blink + ld r12, [sp, 84] ; Recover r12 + ld r11, [sp, 88] ; Recover r11 + ld r10, [sp, 92] ; Recover r10 + ld r9, [sp, 96] ; Recover r9 + ld r8, [sp, 100] ; Recover r8 + ld r7, [sp, 104] ; Recover r7 + ld r6, [sp, 108] ; Recover r6 + ld r5, [sp, 112] ; Recover r5 + ld r4, [sp, 116] ; Recover r4 + ld r3, [sp, 120] ; Recover r3 + ld r2, [sp, 124] ; Recover r2 + ld r1, [sp, 128] ; Recover r1 + ld r0, [sp, 132] ; Recover r0 + add sp, sp, 160 ; Recover interrupt stack frame + rtie ; Return from interrupt +; +; +; } +__tx_thread_not_nested_restore: +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr[core]) && (_tx_thread_current_ptr[core] == _tx_thread_execute_ptr[core]) +; || (_tx_thread_preempt_disable)) +; { +; + mov r1, _tx_thread_current_ptr ; Build current thread pointer address + add r1, r1, r3 ; + ld r0, [r1] ; Pickup current thread pointer + mov r2, _tx_thread_smp_protection ; Build protection address + sub.f 0, r0, 0 ; Set condition codes + beq.d __tx_thread_idle_system_restore ; If NULL, idle system was interrupted + lr r4, [AUX_IRQ_ACT] ; Pickup the interrupt active register + neg r5, r4 ; Negate + and r5, r4, r5 ; See if there are any other interrupts present + brne r4, r5, __tx_thread_no_preempt_restore ; If more interrupts, just return to the point of interrupt + mov r4, _tx_thread_execute_ptr ; Build address of next thread to execute for this core + add r4, r4, r3 ; + ld r4, [r4] ; Pickup next thread to execute + ld r2, [r2, 8] ; Pickup core that has protection + breq r0, r4, __tx_thread_no_preempt_restore ; If equal, simply restore executing thread + ld r5, [gp, _tx_thread_preempt_disable@sda] ; Pickup preempt disable flag + asr r4, r3, 2 ; Shift core index back down for core ID + brne r2, r4, __tx_thread_preempt_restore ; If the core doesn't have protection, preempt thread without looking at preempt disable flag + breq r5, 0, __tx_thread_preempt_restore ; If preempt disable not set, preempt executing thread +; +; +__tx_thread_no_preempt_restore: +; +; /* Restore interrupted thread or ISR. */ +; +; /* Pickup the saved stack pointer. */ +; sp = _tx_thread_current_ptr[core] -> tx_thread_stack_ptr; +; + +; /* Recover the saved context and return to the point of interrupt. */ +; + ld sp, [r0, 8] ; Switch back to thread's stack + + .ifndef TX_DISABLE_LP + ld r0, [sp, 4] ; Recover LP_START + sr r0, [LP_START] ; Restore LP_START + ld r4, [sp, 8] ; Recover LP_END + sr r4, [LP_END] ; Restore LP_END + ld r2, [sp, 12] ; Recover LP_COUNT + mov LP_COUNT, r2 + .endif + + ld r2, [sp, 156] ; Pickup BTA + sr r2, [BTA] ; Recover BTA + .ifdef TX_ENABLE_ACC + ld r58, [sp, 140] ; Recover r58 + ld r59, [sp, 144] ; Recover r59 + .endif + ld blink, [sp, 16] ; Recover blink + ld r12, [sp, 84] ; Recover r12 + ld r11, [sp, 88] ; Recover r11 + ld r10, [sp, 92] ; Recover r10 + ld r9, [sp, 96] ; Recover r9 + ld r8, [sp, 100] ; Recover r8 + ld r7, [sp, 104] ; Recover r7 + ld r6, [sp, 108] ; Recover r6 + ld r5, [sp, 112] ; Recover r5 + ld r4, [sp, 116] ; Recover r4 + ld r3, [sp, 120] ; Recover r3 + ld r2, [sp, 124] ; Recover r2 + ld r1, [sp, 128] ; Recover r1 + ld r0, [sp, 132] ; Recover r0 + add sp, sp, 160 ; Recover interrupt stack frame + rtie ; Return from interrupt +; +; } +; else +; { +__tx_thread_preempt_restore: +; + ld r7, [r0, 8] ; Pickup stack pointer + mov r6, 1 ; Build interrupt stack type + st r6, [r7, 0] ; Setup interrupt stack type + st fp, [r7, 24] ; Save fp + st gp, [r7, 28] ; Save gp + st r25, [r7, 32] ; Save r25 + st r24, [r7, 36] ; Save r24 + st r23, [r7, 40] ; Save r23 + st r22, [r7, 44] ; Save r22 + st r21, [r7, 48] ; Save r21 + st r20, [r7, 52] ; Save r20 + st r19, [r7, 56] ; Save r19 + st r18, [r7, 60] ; Save r18 + st r17, [r7, 64] ; Save r17 + st r16, [r7, 68] ; Save r16 + st r15, [r7, 72] ; Save r15 + st r14, [r7, 76] ; Save r14 + st r13, [r7, 80] ; Save r13 + st r30, [r7, 136] ; Save r30 +__tx_preempt_save_done: +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice) +; { +; + mov r5, _tx_timer_time_slice ; Build time-slice address + add r5, r5, r3 ; + ld r2, [r5] ; Pickup time-slice contents + mov r7, 0 ; Build clear/NULL value + breq r2, 0, __tx_thread_dont_save_ts ; No time-slice, don't need to save it +; +; _tx_thread_current_ptr[core] -> tx_thread_time_slice = _tx_timer_time_slice[core]; +; _tx_timer_time_slice = 0; +; + st r2, [r0, 24] ; If set, save remaining time-slice + st r7, [r5] ; If set, clear time slice +; +; } +__tx_thread_dont_save_ts: +; +; +; /* Clear the current thread pointer. */ +; _tx_thread_current_ptr[core] = TX_NULL; +; + st r7, [r1] ; Set current thread ptr to NULL +; +; /* Set bit indicating this thread is ready for execution. */ +; + dmb 3 ; Data memory barrier + st 1, [r0, 164] ; Set ready bit + + sub sp, sp, 8 ; Allocate a small stack frame on the system stack + lr r0, [STATUS32] ; Pickup STATUS32 + st r0, [sp, 4] ; Place on stack + mov r0, _tx_thread_schedule ; Build address of scheduler + st r0, [sp, 0] ; Write over the point of interrupt + rtie ; Return from interrupt to scheduler +; +; } +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; +__tx_thread_idle_system_restore: + + lr r4, [AUX_IRQ_ACT] ; Pickup the interrupt active register + neg r5, r4 ; Negate + and r5, r4, r5 ; See if there are any other interrupts present + sub.f 0, r4, r5 ; Set condition codes + bne __tx_thread_nested_restore ; If more interrupts, just return to the point of interrupt + + lr r0, [STATUS32] ; Pickup STATUS32 + st r0, [sp, 4] ; Place on stack + mov r0, _tx_thread_schedule ; Build address of scheduler + st r0, [sp, 0] ; Write over the point of interrupt + rtie ; Return from interrupt to scheduler +; +;} + .end + diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_context_save.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_context_save.s new file mode 100644 index 00000000..20fcf44b --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_context_save.s @@ -0,0 +1,254 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; + .equ BTA, 0x412 +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save SMP/ARC_HS/MetaWare */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + .global _tx_thread_context_save + .type _tx_thread_context_save, @function +_tx_thread_context_save: +; +; /* Upon entry to this routine, it is assumed that an interrupt stack frame +; has already been allocated, and the interrupted blink register is already saved. */ +; + clri ; Disable interrupts + st r1, [sp, 128] ; Save r1 + st r0, [sp, 132] ; Save r0 + st r3, [sp, 120] ; Save r3 + st r2, [sp, 124] ; Save r2 +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state++) +; { +; + lr r3, [IDENTITY] ; Pickup core ID + xbfu r3, r3, 8, 8 ; Shift down and isolate core ID + .ifndef TX_ZERO_BASED_CORE_ID + sub r3, r3, 1 ; Subtract 1 to make 0-based + .endif + asl r3, r3, 2 ; Build index into core arrays + mov r0, _tx_thread_system_state ; Build address of system state + add r1, r0, r3 ; + ld r0, [r1] ; Pickup system state + breq r0, 0, __tx_thread_not_nested_save ; If 0, we are not in a nested + ; condition +; +; /* Nested interrupt condition. */ +; + add r0, r0, 1 ; Increment the nested interrupt count + st r0, [r1] ; Update system state +; +; /* Save the rest of the scratch registers on the stack and return to the +; calling ISR. */ +; +__tx_thread_nested_save: ; Label is for special nested interrupt case from idle system save below + st r12, [sp, 84] ; Save r12 + st r11, [sp, 88] ; Save r11 + st r10, [sp, 92] ; Save r10 + st r9, [sp, 96] ; Save r9 + st r8, [sp, 100] ; Save r8 + st r7, [sp, 104] ; Save r7 + st r6, [sp, 108] ; Save r6 + st r5, [sp, 112] ; Save r5 + st r4, [sp, 116] ; Save r6 + lr r10, [LP_START] ; Pickup LP_START + lr r9, [LP_END] ; Pickup LP_END + st LP_COUNT, [sp, 12] ; Save LP_COUNT + st r10, [sp, 4] ; Save LP_START + st r9, [sp, 8] ; Save LP_END + .ifdef TX_ENABLE_ACC + st r58, [sp, 140] ; Save r58 + st r59, [sp, 144] ; Save r59 + .endif + lr r0, [BTA] ; Pickup BTA + st r0, [sp, 156] ; Save BTA + +; +; /* Return to the ISR. */ +; + .ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + sub sp, sp, 32 ; Allocating some space on the stack + st blink, [sp, 16] ; Save blink + bl.d _tx_execution_isr_enter ; Call the ISR enter function + nop ; Delay slot + ld blink, [sp, 16] ; Recover blink + add sp, sp, 32 ; Recover the stack space + .endif +; + + j.d [blink] ; Return to Level 1 ISR + st ilink, [sp, 20] ; Save ilink +; +__tx_thread_not_nested_save: +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr[core]) +; { +; + add r0, r0, 1 ; Increment the nested interrupt count + st r0, [r1] ; Update system state + mov r2, _tx_thread_current_ptr ; Build address of current thread pointer + add r2, r2, r3 ; + ld r1, [r2] ; Pickup current thread pointer + st r12, [sp, 84] ; Save r12 + st r11, [sp, 88] ; Save r11 + breq r1, 0, __tx_thread_idle_system_save ; If no thread is running, idle system was + ; interrupted. +; +; /* Save minimal context of interrupted thread. */ +; + st r10, [sp, 92] ; Save r10 + st r9, [sp, 96] ; Save r9 + st r8, [sp, 100] ; Save r8 + st r7, [sp, 104] ; Save r7 + st r6, [sp, 108] ; Save r6 + st r5, [sp, 112] ; Save r5 + st r4, [sp, 116] ; Save r4 + lr r10, [LP_START] ; Pickup LP_START + lr r9, [LP_END] ; Pickup LP_END + st LP_COUNT, [sp, 12] ; Save LP_COUNT + st r10, [sp, 4] ; Save LP_START + st r9, [sp, 8] ; Save LP_END + st ilink, [sp, 20] ; Save ilink + .ifdef TX_ENABLE_ACC + st r58, [sp, 140] ; Save r58 + st r59, [sp, 144] ; Save r59 + .endif + lr r0, [BTA] ; Pickup BTA + st r0, [sp, 156] ; Save BTA +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; +; + st sp, [r1, 8] ; Save thread's stack pointer + + .ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + sub sp, sp, 32 ; Allocating some space on the stack + st blink, [sp, 16] ; Save blink + bl.d _tx_execution_isr_enter ; Call the ISR enter function + nop ; Delay slot + ld blink, [sp, 16] ; Recover blink + add sp, sp, 32 ; Recover the stack space + .endif +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr[core]; +; + mov r1, _tx_thread_system_stack_ptr ; Build address of system stack pointer + add r1, r1, r3 ; + j_s.d [blink] ; Return to calling ISR + ld sp, [r1] ; Switch to system stack +; +; } +; else +; { +; +__tx_thread_idle_system_save: +; +; /* Interrupt occurred in the scheduling loop. */ +; + .ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + sub sp, sp, 32 ; Allocating some space on the stack + st blink, [sp, 16] ; Save blink + bl.d _tx_execution_isr_enter ; Call the ISR enter function + nop ; Delay slot + ld blink, [sp, 16] ; Recover blink + add sp, sp, 32 ; Recover the stack space + .endif +; +; /* See if we have a special nesting condition. This happens when the higher priority +; interrupt occurs before the nested interrupt logic is valid. */ +; + lr r0, [AUX_IRQ_ACT] ; Pickup the interrupt active register + neg r1, r0 ; Negate + and r1, r0, r1 ; See if there are any other interrupts present + brne r0, r1, __tx_thread_nested_save ; If more interrupts, go into the nested interrupt save logic +; +; /* Not much to do here, just adjust the stack pointer, and return to +; ISR processing. */ +; + j_s.d [blink] ; Return to ISR + add sp, sp, 160 ; Recover stack space +; +; } +;} + .end diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_interrupt_control.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..a3602006 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_interrupt_control.s @@ -0,0 +1,87 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control SMP/ARC_HS/MetaWare */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + .global _tx_thread_interrupt_control + .type _tx_thread_interrupt_control, @function +_tx_thread_interrupt_control: +; +; /* Pickup current interrupt lockout posture. */ +; + clri r1 ; Get current interrupt state +; +; /* Apply the new interrupt posture. */ +; + seti r0 ; Set desired interrupt state + j_s.d [blink] ; Return to caller with delay slot + mov r0, r1 ; Return previous mask value. Return value is TX_INT_DISABLE or TX_INT_ENABLE. +; +;} + .end diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_schedule.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_schedule.s new file mode 100644 index 00000000..f72b0106 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_schedule.s @@ -0,0 +1,297 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; + .equ BTA, 0x412 +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +; /* Define the lock for the ARC simulator workaround. The ARC HS SMP +; simulator does not execute cores in a lock-step fashion, i.e., a +; core can stall for many cycles while the other core executes. This +; does not happen on actual hardware and thus the need for a schedule +; lock is not required since: 1) ThreadX SMP will not load the same +; thread into two places on the _tx_thread_execute_list, and moving +; a thread from one entry on the _tx_thread_execute_list to another +; is more than the 5 instructions executed between examination of the +; the _tx_thread_execute_list thread and clearing its ready bit in +; preparation for scheduling. */ +; + .ifdef TX_ARC_SIMULATOR_WORKAROUND + .globl _tx_thread_schedule_lock + .size _tx_thread_schedule_lock, 4 + .type _tx_thread_schedule_lock,@object +_tx_thread_schedule_lock: + .word 0 + + .endif +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule SMP/ARC_HS/MetaWare */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr array. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + .global _tx_thread_schedule_restart +_tx_thread_schedule_restart: + .ifdef TX_ARC_SIMULATOR_WORKAROUND + mov r7, _tx_thread_schedule_lock + dmb 3 + mov r3, 0 + st r3, [r7] + dmb 3 + .endif + + .global _tx_thread_schedule + .type _tx_thread_schedule, @function +_tx_thread_schedule: +; + +; +; /* Enable interrupts. */ +; + mov r0, 0x1F ; Build enable interrupt value + seti r0 ; Enable interrupts +; +; /* Wait for a thread to execute. */ +; do +; { +; + lr r1, [IDENTITY] ; Pickup core ID + xbfu r1, r1, 8, 8 ; Shift down and isolate core ID + .ifndef TX_ZERO_BASED_CORE_ID + sub r1, r1, 1 ; Subtract 1 to make 0-based + .endif + asl r4, r1, 2 ; Build index into core arrays + mov r7, _tx_thread_execute_ptr ; Pickup base of the execute thread pointer + add r7, r7, r4 ; Build address of current thread pointer + +__tx_thread_schedule_loop: +; + clri ; Lockout interrupts + nop ; Delay for interrupts to really be disabled + .ifdef TX_ARC_SIMULATOR_WORKAROUND + mov r0, _tx_thread_schedule_lock + llock r5, [r0] + breq r5, 0, _continue + b _tx_thread_schedule +_continue: + add r5, r1, 1 + scond r5, [r0] + beq_s _got_lock + b _tx_thread_schedule +_got_lock: + .endif + + ld r0, [r7] ; Pickup next thread to execute + breq r0, 0, _tx_thread_schedule_restart ; If NULL, keep looking +; +; } +; while(_tx_thread_execute_ptr[core] == TX_NULL); +; +; +; /* Now make sure the thread's ready bit is set. */ +; + ld r5, [r0, 164] ; Pickup the ready bit for this thread to see if it can be executed + breq r5, 0, _tx_thread_schedule_restart ; If not set, start over + st 0, [r0, 164] ; Clear the ready bit now that this thread is being executed + dmb 3 ; Data memory barrier + + .ifdef TX_ARC_SIMULATOR_WORKAROUND + mov r7, _tx_thread_schedule_lock + dmb 3 + mov r3, 0 + st r3, [r7] + dmb 3 + .endif +; +; /* Yes! We have a thread to execute - transfer control to it. */ +; +; /* Setup the current thread pointer. */ +; _tx_thread_current_ptr[core] = _tx_thread_execute_ptr[core]; +; + mov r7, _tx_thread_current_ptr ; Build address of current thread pointer + add r7, r7, r4 ; + st r0, [r7] ; Setup current thread pointer +; +; /* Increment the run count for this thread. */ +; _tx_thread_current_ptr[core] -> tx_thread_run_count++; +; + ld r3, [r0, 4] ; Pickup run counter + ld r5, [r0, 24] ; Pickup time-slice for this thread + add r3, r3, 1 ; Increment run counter + st r3, [r0, 4] ; Store the new run counter +; +; /* Setup time-slice, if present. */ +; _tx_timer_time_slice[core] = _tx_thread_current_ptr -> tx_thread_time_slice; +; + mov r6, _tx_timer_time_slice ; Build address of time-slice for this core + add r6, r6, r4 ; + st r5, [r6] ; Setup time-slice +; + .ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + mov r13, r0 ; Save thread control block pointer + bl.d _tx_execution_thread_enter ; Call the thread execution enter function + sub sp, sp, 16 ; ..allocating some space on the stack + add sp, sp, 16 ; Recover the stack space + mov r0, r13 ; Recover thread control block pointer + .endif +; +; /* Switch to the thread's stack. */ +; sp = _tx_thread_execute_ptr[core] -> tx_thread_stack_ptr; +; + ld sp, [r0, 8] ; Switch to thread's stack +; +; /* Determine if an interrupt frame or a synchronous task suspension frame +; is present. */ +; + ld r1, [sp, 0] ; Pickup the stack type + brne r1, 0, __tx_thread_schedule_int_ret ; Compare to solicited stack type. If not, thread was interrupted + ld blink, [sp, 4] ; Recover blink + ld fp, [sp, 8] ; Recover fp + ld gp, [sp, 12] ; Recover gp + ld r25, [sp, 16] ; Recover r25 + ld r24, [sp, 20] ; Recover r24 + ld r23, [sp, 24] ; Recover r23 + ld r22, [sp, 28] ; Recover r22 + ld r21, [sp, 32] ; Recover r21 + ld r20, [sp, 36] ; Recover r20 + ld r19, [sp, 40] ; Recover r19 + ld r18, [sp, 44] ; Recover r18 + ld r17, [sp, 48] ; Recover r17 + ld r16, [sp, 52] ; Recover r16 + ld r15, [sp, 56] ; Recover r15 + ld r14, [sp, 60] ; Recover r14 + ld r13, [sp, 64] ; Recover r13 + ld r1, [sp, 68] ; Pickup status32 + ld r30, [sp, 72] ; Recover r30 + add sp, sp, 76 ; Recover solicited stack frame + j_s.d [blink] ; Return to thread and restore flags + seti r1 ; Recover STATUS32 +; +__tx_thread_schedule_int_ret: +; + mov r0, 0x2 ; Pretend level 1 interrupt is returning + sr r0, [AUX_IRQ_ACT] ; + + .ifndef TX_DISABLE_LP + ld r0, [sp, 4] ; Recover LP_START + sr r0, [LP_START] ; Restore LP_START + ld r1, [sp, 8] ; Recover LP_END + sr r1, [LP_END] ; Restore LP_END + ld r2, [sp, 12] ; Recover LP_COUNT + mov LP_COUNT, r2 + .endif + + ld r0, [sp, 156] ; Pickup saved BTA + sr r0, [BTA] ; Recover BTA + ld blink, [sp, 16] ; Recover blink + ld ilink, [sp, 20] ; Recover ilink + ld fp, [sp, 24] ; Recover fp + ld gp, [sp, 28] ; Recover gp + ld r25, [sp, 32] ; Recover r25 + ld r24, [sp, 36] ; Recover r24 + ld r23, [sp, 40] ; Recover r23 + ld r22, [sp, 44] ; Recover r22 + ld r21, [sp, 48] ; Recover r21 + ld r20, [sp, 52] ; Recover r20 + ld r19, [sp, 56] ; Recover r19 + ld r18, [sp, 60] ; Recover r18 + ld r17, [sp, 64] ; Recover r17 + ld r16, [sp, 68] ; Recover r16 + ld r15, [sp, 72] ; Recover r15 + ld r14, [sp, 76] ; Recover r14 + ld r13, [sp, 80] ; Recover r13 + ld r12, [sp, 84] ; Recover r12 + ld r11, [sp, 88] ; Recover r11 + ld r10, [sp, 92] ; Recover r10 + ld r9, [sp, 96] ; Recover r9 + ld r8, [sp, 100] ; Recover r8 + ld r7, [sp, 104] ; Recover r7 + ld r6, [sp, 108] ; Recover r6 + ld r5, [sp, 112] ; Recover r5 + ld r4, [sp, 116] ; Recover r4 + ld r3, [sp, 120] ; Recover r3 + ld r2, [sp, 124] ; Recover r2 + ld r1, [sp, 128] ; Recover r1 + ld r0, [sp, 132] ; Recover r0 + ld r30, [sp, 136] ; Recover r30 + .ifdef TX_ENABLE_ACC + ld r58, [sp, 140] ; Recover r58 + ld r59, [sp, 144] ; Recover r59 + .endif + add sp, sp, 160 ; Recover interrupt stack frame + rtie ; Return to point of interrupt +; +;} +; + .end + diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_core_get.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_core_get.s new file mode 100644 index 00000000..7c100af2 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_core_get.s @@ -0,0 +1,86 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +;#define TX_THREAD_SMP_SOURCE_CODE +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" */ +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_core_get SMP/ARC_HS/MetaWare */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function gets the currently running core number and returns it.*/ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* Core ID */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ + .global _tx_thread_smp_core_get + .type _tx_thread_smp_core_get, @function +_tx_thread_smp_core_get: +; +; /* Pickup core ID. */ +; + lr r0, [IDENTITY] ; Pickup core ID + xbfu r0, r0, 8, 8 ; Shift down and isolate core ID + j_s.d [blink] ; Return to caller with delay slot + .ifndef TX_ZERO_BASED_CORE_ID + sub r0, r0, 1 ; Subtract 1 to make 0-based + .else + nop ; + .endif + .end + diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_core_preempt.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_core_preempt.s new file mode 100644 index 00000000..dde6dda2 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_core_preempt.s @@ -0,0 +1,88 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +;#define TX_THREAD_SMP_SOURCE_CODE +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" */ +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_core_preempt SMP/ARC_HS/MetaWare */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function preempts the specified core in situations where the */ +;/* thread corresponding to this core is no longer ready or when the */ +;/* core must be used for a higher-priority thread. If the specified is */ +;/* the current core, this processing is skipped since the will give up */ +;/* control subsequently on its own. */ +;/* */ +;/* INPUT */ +;/* */ +;/* core The core to preempt */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ + .global _tx_thread_smp_core_preempt + .type _tx_thread_smp_core_preempt, @function +_tx_thread_smp_core_preempt: + sub sp, sp, 16 ; Allocate some stack space + st blink, [sp] ; Save return address + bl.d arc_ici_send ; Call ARC inter-core interrupt routine + sub sp, sp, 16 ; Allocate stack space (delay slot) + add sp, sp, 16 ; Recover stack space + ld blink, [sp] ; Recover return address + j_s.d [blink] ; Return to caller with delay slot + add sp, sp, 16 ; Recover stack space + + .end + diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_current_state_get.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_current_state_get.s new file mode 100644 index 00000000..bd886a8c --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_current_state_get.s @@ -0,0 +1,89 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +;#define TX_THREAD_SMP_SOURCE_CODE +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" */ +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_current_state_get SMP/ARC_HS/MetaWare */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is gets the current state of the calling core. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ + .global _tx_thread_smp_current_state_get + .type _tx_thread_smp_current_state_get, @function +_tx_thread_smp_current_state_get: + + clri r2 ; Disable interrupts + lr r0, [IDENTITY] ; Pickup core ID + xbfu r0, r0, 8, 8 ; Shift down and isolate core ID + .ifndef TX_ZERO_BASED_CORE_ID + sub r0, r0, 1 ; Subtract 1 to make 0-based + .endif + asl r0, r0, 2 ; Build index into _tx_thread_system_state + mov r1, _tx_thread_system_state ; Build address of _tx_thread_system_state + add r1, r1, r0 ; + ld r0, [r1] ; Pickup current system state for this core + j_s.d [blink] ; Return to caller with delay slot + seti r2 ; Restore previous interrupt state + + .end + diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_current_thread_get.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_current_thread_get.s new file mode 100644 index 00000000..8dbcfe91 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_current_thread_get.s @@ -0,0 +1,90 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +;#define TX_THREAD_SMP_SOURCE_CODE +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" */ +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_current_thread_get SMP/ARC_HS/MetaWare */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is gets the current thread of the calling core. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ + .global _tx_thread_smp_current_thread_get + .type _tx_thread_smp_current_thread_get, @function +_tx_thread_smp_current_thread_get: + + clri r2 ; Disable interrupts + lr r0, [IDENTITY] ; Pickup core ID + xbfu r0, r0, 8, 8 ; Shift down and isolate core ID + .ifndef TX_ZERO_BASED_CORE_ID + sub r0, r0, 1 ; Subtract 1 to make 0-based + .endif + asl r0, r0, 2 ; Build index into _tx_thread_current_ptr + mov r1, _tx_thread_current_ptr ; Build address of _tx_thread_current_ptr + add r1, r1, r0 ; + ld r0, [r1] ; Pickup current thread for this core + j_s.d [blink] ; Return to caller with delay slot + seti r2 ; Restore previous interrupt state + + .end + + diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_initialize_wait.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_initialize_wait.s new file mode 100644 index 00000000..a12afad5 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_initialize_wait.s @@ -0,0 +1,126 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +;#define TX_THREAD_SMP_SOURCE_CODE +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" */ +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_initialize_wait SMP/ARC_HS/MetaWare */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is the place where additional cores wait until */ +;/* initialization is complete before they enter the thread scheduling */ +;/* loop. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Hardware */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ + .global _tx_thread_smp_initialize_wait + .type _tx_thread_smp_initialize_wait, @function +_tx_thread_smp_initialize_wait: +; +; /* Lockout interrupts. */ +; + clri r2 ; Disable interrupts +; +; /* Pickup the CPU ID. */ +; + lr r0, [IDENTITY] ; Pickup core ID + xbfu r0, r0, 8, 8 ; Shift down and isolate core ID + .ifndef TX_ZERO_BASED_CORE_ID + sub r0, r0, 1 ; Subtract 1 to make 0-based + .endif + asl r0, r0, 2 ; Build index into _tx_thread_system_state + mov r1, _tx_thread_system_stack_ptr ; Build system stack pointer address + add r1, r1, r0 ; + st sp, [r1] ; Save this core's system address + + mov r1, _tx_thread_system_state ; Build system state pointer address + add r1, r1, r0 ; + mov r3, 0xF0F0F0F0 ; Build TX_INITIALIZE_IN_PROGRESS flag +wait_for_initialize: + ld r0, [r1] ; Pickup current system state for this core + ; Has the TX_INITIALIZE_IN_PROGRESS flag been set yet? + brne r3, r0, wait_for_initialize ; No, simply wait here until this value is set +; +; /* Pickup the release cores flag. */ +; + mov r3, 0 ; Build clear value +wait_for_release: + ld r0, [gp, _tx_thread_smp_release_cores_flag@sda] ; Pickup the release cores flag + breq r3, r0, wait_for_release ; No, simply wait here until this flag is set +; +; /* Core 0 has released this core. */ +; +; /* Clear this core's system state variable. */ +; + st r3, [r1] ; Clear this core's state value +; +; /* Now wait for core 0 to finish it's initialization. */ +; +core_0_wait_loop: + ld r0, [gp, _tx_thread_system_state@sda] ; Pickup core 0's state value + brne r3, r0, core_0_wait_loop ; If set, continue to wait here +; +; /* Initialize is complete, enter the scheduling loop! */ +; + b _tx_thread_schedule ; Return to scheduler.. + + .end + + diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_low_level_initialize.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_low_level_initialize.s new file mode 100644 index 00000000..6dec565b --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_low_level_initialize.s @@ -0,0 +1,79 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +;#define TX_THREAD_SMP_SOURCE_CODE +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" */ +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_low_level_initialize SMP/ARC_HS/MetaWare */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function performs low-level initialization of the booting */ +;/* core. */ +;/* */ +;/* INPUT */ +;/* */ +;/* number_of_cores Number of cores */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_high_level ThreadX high-level init */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ + .global _tx_thread_smp_low_level_initialize + .type _tx_thread_smp_low_level_initialize, @function +_tx_thread_smp_low_level_initialize: + + j_s.d [blink] ; Return to caller with delay slot + nop ; + + .end diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_protect.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_protect.s new file mode 100644 index 00000000..ea9e174a --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_protect.s @@ -0,0 +1,117 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +;#define TX_THREAD_SMP_SOURCE_CODE +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" */ +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_protect SMP/ARC_HS/MetaWare */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function gets protection for running inside the ThreadX */ +;/* source. This is acomplished by a combination of a test-and-set */ +;/* flag and periodically disabling interrupts. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* Previous Status Register */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ + .global _tx_thread_smp_protect + .type _tx_thread_smp_protect, @function +_tx_thread_smp_protect: + + clri r0 ; Disable interrupts + lr r1, [IDENTITY] ; Pickup core ID + xbfu r1, r1, 8, 8 ; Shift down and isolate core ID + .ifndef TX_ZERO_BASED_CORE_ID + sub r1, r1, 1 ; Subtract 1 to make 0-based + .endif + mov r2, 1 ; Build protection flag + mov r3, 0 ; Build clear value + mov r4, _tx_thread_smp_protection ; Build address of the protection structure + ld r5, [r4, 8] ; Pickup the owning core + breq r1, r5, _owned ; Check if the core already owns the protection + llock r6, [r4] ; Attempt to get the inter-core lock + breq r3, r6, _continue ; If the lock is available, continue + b.d _tx_thread_smp_protect ; Attempt to get the lock again + seti r0 ; Restore original interrupt posture +_continue: + scond r2, [r4] ; Attempt to set the lock + beq_s _got_lock ; If STATUS32[Z] flag is set, we got the lock! + b.d _tx_thread_smp_protect ; Attempt to get the lock again + seti r0 ; Restore original interrupt posture +_got_lock: + dmb 3 ; Data memory barrier + st r1, [r4, 8] ; Store the owning core + .ifdef TX_SMP_DEBUG_ENABLE + asl r0, r1, 2 ; Build index into _tx_thread_system_state + mov r7, _tx_thread_current_ptr ; Pickup base of the current thread pointer + add r7, r7, r0 ; Build address of current thread pointer + ld r8, [r7] ; Pickup the current thread pointer + st r8, [r4, 4] ; Save the current thread pointer + st blink, [r4, 16] ; Save last caller's return address + st r0, [r4, 20] ; Save STATUS32 + .endif +_owned: + ld r6, [r4, 12] ; Pickup ownership count + add r6, r6, 1 ; Increment ownership count + j_s.d [blink] ; Return to caller with delay slot + st r6, [r4, 12] ; Store new ownership count + + .end + + diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_time_get.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_time_get.s new file mode 100644 index 00000000..97e46261 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_time_get.s @@ -0,0 +1,80 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +;#define TX_THREAD_SMP_SOURCE_CODE +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" */ +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_time_get SMP/ARC_HS/MetaWare */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function gets the global time value that is used for debug */ +;/* information and event tracing. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* 32-bit time stamp */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ + .global _tx_thread_smp_time_get + .type _tx_thread_smp_time_get, @function +_tx_thread_smp_time_get: + + j_s.d [blink] ; Return to caller with delay slot + lr r0, [COUNT0] ; Return count 0 value + + .end + diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_unprotect.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_unprotect.s new file mode 100644 index 00000000..8fb802b3 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_smp_unprotect.s @@ -0,0 +1,107 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +;#define TX_THREAD_SMP_SOURCE_CODE +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" */ +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_unprotect SMP/ARC_HS/MetaWare */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function releases previously obtained protection. The supplied */ +;/* previous SR is restored. If the value of _tx_thread_system_state */ +;/* and _tx_thread_preempt_disable are both zero, then multithreading */ +;/* is enabled as well. */ +;/* */ +;/* INPUT */ +;/* */ +;/* Previous Status Register */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ + .global _tx_thread_smp_unprotect + .type _tx_thread_smp_unprotect, @function +_tx_thread_smp_unprotect: + clri ; Disable interrupts + lr r1, [IDENTITY] ; Pickup core ID + xbfu r1, r1, 8, 8 ; Shift down and isolate core ID + .ifndef TX_ZERO_BASED_CORE_ID + sub r1, r1, 1 ; Subtract 1 to make 0-based + .endif + mov r4, _tx_thread_smp_protection ; Build address of the protection structure + ld r5, [r4, 8] ; Pickup the owning core + brne r1, r5, _still_protected ; If not the owning core, protection is in force elsewhere + ld r6, [r4, 12] ; Pickup ownership count + breq r6, 0, _still_protected ; If zero, protection is still active + sub r6, r6, 1 ; Decrement the ownership count + st r6, [r4, 12] ; Store the ownership count + brne r6, 0, _still_protected ; If non-zero, protection is still active + ld r6, [gp, _tx_thread_preempt_disable@sda] ; Pickup preempt disable flag + brne r6, 0, _still_protected ; If non-zero, don't release the protection + mov r2, 0xFFFFFFFF ; Build invalid value + st r2, [r4, 8] ; Set the owning core to an invalid value + .ifdef TX_SMP_DEBUG_ENABLE + st blink, [r4, 24] ; Save caller of unprotect + .endif + mov r2, 0 ; Build clear value + dmb 3 ; Data memory barrier + st r2, [r4] ; Release the protection + dmb 3 ; Data memory barrier +_still_protected: + j_s.d [blink] ; Return to caller with delay slot + seti r0 ; Set desired interrupt state + + .end + diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_stack_build.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_stack_build.s new file mode 100644 index 00000000..5c9f5d48 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_stack_build.s @@ -0,0 +1,209 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + .equ LONG_ALIGN_MASK, 0xFFFFFFFC + .equ INT_ENABLE_BITS, 0x8000001E +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build SMP/ARC_HS/MetaWare */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + .global _tx_thread_stack_build + .type _tx_thread_stack_build, @function +_tx_thread_stack_build: +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the ARC HS should look like the following after it is built. +; Note that the extension registers are always assigned space here. +; +; Stack Top: 1 Interrupt stack frame type +; LP_START Initial loop start +; LP_END Initial loop end +; LP_COUNT Initial loop count +; blink Initial blink value +; ilink Initial ilink (point of interrupt) +; fp (r27) Initial fp (0) +; gp Initial gp +; r25 Initial r25 +; r24 Initial r24 +; r23 Initial r23 +; r22 Initial r22 +; r21 Initial r21 +; r20 Initial r20 +; r19 Initial r19 +; r18 Initial r18 +; r17 Initial r17 +; r16 Initial r16 +; r15 Initial r15 +; r14 Initial r14 +; r13 Initial r13 +; r12 Initial r12 +; r11 Initial r11 +; r10 Initial r10 +; r9 Initial r9 +; r8 Initial r8 +; r7 Initial r7 +; r6 Initial r6 +; r5 Initial r5 +; r4 Initial r4 +; r3 Initial r3 +; r2 Initial r2 +; r1 Initial r1 +; r0 Initial r0 +; r30 Initial r30 +; r58 Initial r58 +; r59 Initial r59 +; 0 Reserved +; 0 Reserved +; 0 Initial BTA +; 0 Point of Interrupt (thread entry point) +; 0 Initial STATUS32 +; 0 Backtrace +; 0 Backtrace +; 0 Backtrace +; 0 Backtrace +; +; *: these registers will only be saved and restored if flag -Xxmac_d16 is passed to hcac +; +; Stack Bottom: (higher memory address) */ +; + ld r3, [r0, 16] ; Pickup end of stack area + and r3, r3, LONG_ALIGN_MASK ; Ensure long-word alignment + sub r3, r3, 196 ; Allocate an interrupt stack frame (ARC HS) +; +; /* Actually build the stack frame. */ +; + st 1, [r3, 0] ; Store interrupt stack type on the + ; top of the stack + mov r5, 0 ; Build initial clear value + st r5, [r3, 4] ; Store initial LP_START + st r5, [r3, 8] ; Store initial LP_END + st r5, [r3, 12] ; Store initial LP_COUNT + st r5, [r3, 16] ; Store initial blink + st r1, [r3, 20] ; Store initial ilink + st r5, [r3, 24] ; Store initial fp (0 for backtrace) + st gp, [r3, 28] ; Store current gp + st r5, [r3, 32] ; Store initial r25 + st r5, [r3, 36] ; Store initial r24 + st r5, [r3, 40] ; Store initial r23 + st r5, [r3, 44] ; Store initial r22 + st r5, [r3, 48] ; Store initial r21 + st r5, [r3, 52] ; Store initial r20 + st r5, [r3, 56] ; Store initial r19 + st r5, [r3, 60] ; Store initial r18 + st r5, [r3, 64] ; Store initial r17 + st r5, [r3, 68] ; Store initial r16 + st r5, [r3, 72] ; Store initial r15 + st r5, [r3, 76] ; Store initial r14 + st r5, [r3, 80] ; Store initial r13 + st r5, [r3, 84] ; Store initial r12 + st r5, [r3, 88] ; Store initial r11 + st r5, [r3, 92] ; Store initial r10 + st r5, [r3, 96] ; Store initial r9 + st r5, [r3, 100] ; Store initial r8 + st r5, [r3, 104] ; Store initial r7 + st r5, [r3, 108] ; Store initial r6 + st r5, [r3, 112] ; Store initial r5 + st r5, [r3, 116] ; Store initial r4 + st r5, [r3, 120] ; Store initial r3 + st r5, [r3, 124] ; Store initial r2 + st r5, [r3, 128] ; Store initial r1 + st r5, [r3, 132] ; Store initial r0 + st r5, [r3, 136] ; Store initial r30 + st r5, [r3, 140] ; Store initial r58 + st r5, [r3, 144] ; Store initial r59 + st r5, [r3, 148] ; Reserved + st r5, [r3, 152] ; Reserved + st r5, [r3, 156] ; Store initial BTA + st r1, [r3, 160] ; Store initial point of entry + lr r6, [status32] ; Pickup STATUS32 + or r6, r6, INT_ENABLE_BITS ; Make sure interrupts are enabled + st r6, [r3, 164] ; Store initial STATUS32 + st r5, [r3, 168] ; Backtrace 0 + st r5, [r3, 172] ; Backtrace 0 + st r5, [r3, 176] ; Backtrace 0 + st r5, [r3, 180] ; Backtrace 0 +; +; /* Set ready bit in thread control block. */ +; + st 1, [r0, 164] ; Set ready bit in thread's control block +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r3; +; + j_s.d [blink] ; Return to caller + st r3, [r0, 8] ; Save stack pointer in thread's + ; control block +;} + .end + + diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_thread_system_return.s b/ports_smp/arc_hs_smp/metaware/src/tx_thread_system_return.s new file mode 100644 index 00000000..176cd79f --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/src/tx_thread_system_return.s @@ -0,0 +1,199 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return SMP/ARC_HS/MetaWare */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + .global _tx_thread_system_return + .type _tx_thread_system_return, @function +_tx_thread_system_return: +; +; /* Save minimal context on the stack. */ +; +; /* Lockout interrupts. */ +; + clri r2 ; Disable interrupts + lr r1, [IDENTITY] ; Pickup core ID + xbfu r1, r1, 8, 8 ; Shift down and isolate core ID + .ifndef TX_ZERO_BASED_CORE_ID + sub r1, r1, 1 ; Subtract 1 to make 0-based + .endif + asl r4, r1, 2 ; Build index into core arrays + mov r7, _tx_thread_current_ptr ; Pickup base of the current thread pointer + add r7, r7, r4 ; Build address of current thread pointer + ld r0, [r7] ; Pickup current thread ptr + sub sp, sp, 76 ; Allocate a solicited stack frame + mov r3, 0 ; Build a solicited stack type + st r3, [sp, 0] ; Store stack type on the top + st blink, [sp, 4] ; Save return address and flags + st fp, [sp, 8] ; Save fp + st r26, [sp, 12] ; Save r26 + st r25, [sp, 16] ; Save r25 + st r24, [sp, 20] ; Save r24 + st r23, [sp, 24] ; Save r23 + st r22, [sp, 28] ; Save r22 + st r21, [sp, 32] ; Save r21 + st r20, [sp, 36] ; Save r20 + st r19, [sp, 40] ; Save r19 + st r18, [sp, 44] ; Save r18 + st r17, [sp, 48] ; Save r17 + st r16, [sp, 52] ; Save r16 + st r15, [sp, 56] ; Save r15 + st r14, [sp, 60] ; Save r14 + st r13, [sp, 64] ; Save r13 + st r2, [sp, 68] ; Save status32 + st r30, [sp, 72] ; Save r30 +; +; /* Save current stack and switch to system stack. */ +; _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; +; sp = _tx_thread_system_stack_ptr[core]; +; +; + st sp, [r0, 8] ; Save thread's stack pointer + mov r6, _tx_thread_system_stack_ptr ; Pickup address of system stack pointer + add r6, r6, r4 ; Build address of this core's entry + ld sp, [r6] ; Switch to system stack +; + .ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + mov r13, r0 ; Save thread control block pointer + mov r14, r1 ; Save core executing + mov r15, r7 ; Save current thread pointer for core + mov r16, blink ; Save blink + bl.d _tx_execution_thread_exit ; Call the thread exit function + sub sp, sp, 16 ; ..allocating some space on the stack + add sp, sp, 16 ; Recover the stack space + ld r0, [gp, _tx_thread_current_ptr@sda] ; Pickup current thread ptr + mov r3, 0 ; Build clear value + mov r0, r13 ; Recover thread control block + mov r1, r14 ; Recover current core executing + mov r7, r15 ; Recover current thread pointer for core + mov blink, r16 ; Recover blink + asl r4, r1, 2 ; Build index into core arrays + + .endif +; +; /* Determine if the time-slice is active. */ +; if (_tx_timer_time_slice) +; { +; + mov r6, _tx_timer_time_slice ; Build address of current time-slice + add r6, r6, r4 ; + ld r5, [r6] ; Pickup current time-slice + breq r5, 0, __tx_thread_dont_save_ts ; If not, skip save processing +; +; /* Save time-slice for the thread and clear the current time-slice. */ +; _tx_thread_current_ptr[core] -> tx_thread_time_slice = _tx_timer_time_slice[core]; +; _tx_timer_time_slice = 0; +; + st r3, [r6] ; Clear time-slice variable + st r5, [r0, 24] ; Save current time-slice +; +; } +__tx_thread_dont_save_ts: +; +; /* Clear the current thread pointer. */ +; _tx_thread_current_ptr[core] = TX_NULL; +; + st r3, [r7] ; Clear current thread pointer +; +; /* Set ready bit in thread control block. */ +; + dmb 3 ; Data memory barrier + st 1, [r0, 164] ; Set ready bit for this thread +; +; /* Now clear protection. It is assumed that protection is in force whenever this routine is called. */ +; + mov r6, _tx_thread_smp_protection ; Pickup address of protection structure + + .ifdef TX_SMP_DEBUG_ENABLE + st blink, [r6, 24] ; Save last caller + ld r5, [r6, 4] ; Pickup last core owner +__error_loop: + brne r1, r5, __error_loop ; Check for an error - if found stay here! + .endif + + st r3, [gp, _tx_thread_preempt_disable@sda] ; Clear the preempt disable flag + st r3, [r6, 12] ; Clear the protection count + mov r5, 0xFFFFFFFF ; Build invalid core value + st r5, [r6, 8] ; Set core to an invalid value + dmb 3 ; Data memory barrier + st r3, [r6] ; Clear protection + dmb 3 ; Data memory barrier + + b _tx_thread_schedule ; Return to scheduler.. +; +;} + .end + + diff --git a/ports_smp/arc_hs_smp/metaware/src/tx_timer_interrupt.s b/ports_smp/arc_hs_smp/metaware/src/tx_timer_interrupt.s new file mode 100644 index 00000000..22111e76 --- /dev/null +++ b/ports_smp/arc_hs_smp/metaware/src/tx_timer_interrupt.s @@ -0,0 +1,206 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_timer.h" +;#include "tx_thread.h" +; +; +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt SMP/ARC_HS/MetaWare */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Process timer expiration */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* _tx_thread_context_save Save interrupt context */ +;/* _tx_thread_context_restore Restore interrupt context */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + .global _tx_timer_interrupt + .type _tx_timer_interrupt, @function +_tx_timer_interrupt: +; +; /* Upon entry to this routine, it is assumed that context save has already +; been called, and therefore the compiler scratch registers are available +; for use. */ +; + lr r1, [IDENTITY] ; Pickup core ID + xbfu r1, r1, 8, 8 ; Shift down and isolate core ID + .ifndef TX_ZERO_BASED_CORE_ID + sub r1, r1, 1 ; Subtract 1 to make 0-based + .endif + breq r1, 0, __tx_process_timer ; By default if core 0, process timer + j_s.d [blink] ; Return to caller with delay + nop ; +__tx_process_timer: + + sub sp, sp, 16 ; Allocate some stack space + st blink, [sp] ; Save return address + bl.d _tx_thread_smp_protect ; Get SMP protecton + sub sp, sp, 16 ; ..allocating some space on the stack + add sp, sp, 16 ; Recover the stack space + st r0, [sp, 4] ; Save returned interrupt posture on stack + ld r0, [gp,_tx_timer_interrupt_active@sda] ; Pickup current timer active count + add r0, r0, 1 ; Increment the active count + st r0, [gp,_tx_timer_interrupt_active@sda] ; Store the new timer active count + dmb 3 ; Data memory barrier +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + ld r0, [gp,_tx_timer_system_clock@sda] ; Pickup current system clock + add r0, r0, 1 ; Increment the system clock + st r0, [gp,_tx_timer_system_clock@sda] ; Store system clock back in memory +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + ld r0, [gp, _tx_timer_current_ptr@sda] ; Pickup current timer pointer + ld r2, [r0, 0] ; Pickup examine actual list entry + breq r2, 0, __tx_timer_no_timer ; + ; If NULL, no timer has expired, just move to the next entry +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + mov r1, 1 ; Build expiration value + b.d __tx_timer_done ; Skip moving the timer pointer + st r1, [gp, _tx_timer_expired@sda] ; Set the expired value +; +; } +; else +; { +__tx_timer_no_timer: +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ld r2, [gp, _tx_timer_list_end@sda] ; Pickup end of list + add r0, r0, 4 ; Move to next timer entry +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + st r0, [gp, _tx_timer_current_ptr@sda] ; Store the current timer + brne r0, r2, __tx_timer_skip_wrap ; If not equal, don't wrap the list +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + ld r2, [gp, _tx_timer_list_start@sda] ; Pickup start of timer list + st r2, [gp, _tx_timer_current_ptr@sda] ; Set current timer to the start +; +__tx_timer_skip_wrap: +; +; } +; +__tx_timer_done: +; +; +; /* See if anything has expired. */ +; if (_tx_timer_expired) +; { +; + breq r1, 0, __tx_timer_nothing_expired ; If 0, nothing has expired +; +__tx_something_expired: +; +; +; /* Process the timer expiration. */ +; /* _tx_timer_expiration_process(); */ + bl.d _tx_timer_expiration_process ; Call the timer expiration handling routine + sub sp, sp, 16 ; ..allocating some space on the stack + add sp, sp, 16 ; Recover the stack space +; +; } + +__tx_timer_nothing_expired: +; +; /* Call time-slice processing. */ +; /* _tx_thread_time_slice(); */ + + bl.d _tx_thread_time_slice ; Call time-slice processing + sub sp, sp, 16 ; ..allocating some stack space + add sp, sp, 16 ; Recover stack space +; +; } +; + ld r0, [gp,_tx_timer_interrupt_active@sda] ; Pickup current timer active count + sub r0, r0, 1 ; Decrement the active count + st r0, [gp,_tx_timer_interrupt_active@sda] ; Store the new timer active count + dmb 3 ; Data memory barrier + + ld r0, [sp, 4] ; Recover previous interrupt posture + bl.d _tx_thread_smp_unprotect ; Get SMP protecton + sub sp, sp, 16 ; ..allocating some space on the stack + add sp, sp, 16 ; Recover the stack space + ld blink, [sp] ; Recover original blink +; +; + j_s.d [blink] ; Return to caller with delay slot + add sp, sp, 16 ; Recover temporary stack space +; +;} + .end + diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/.cproject b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/.cproject new file mode 100644 index 00000000..de33a4b6 --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/.cproject @@ -0,0 +1,228 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/.project b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/.project new file mode 100644 index 00000000..725328bd --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/.project @@ -0,0 +1,27 @@ + + + sample_threadx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.arm.debug.ds.nature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/.settings/language.settings.xml b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/.settings/language.settings.xml new file mode 100644 index 00000000..8d860a09 --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/.settings/language.settings.xml @@ -0,0 +1,506 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_GIC.h b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_GIC.h new file mode 100644 index 00000000..bcff9373 --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_GIC.h @@ -0,0 +1,74 @@ +// ------------------------------------------------------------ +// Cortex-A5 MPCore - Interrupt Controller functions +// Header File +// +// Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#ifndef _CORTEXA_GIC_ +#define _CORTEXA_GIC_ + +// ------------------------------------------------------------ +// GIC +// ------------------------------------------------------------ + +// Typical calls to enable interrupt ID X: +// enable_irq_id(X) <-- Enable that ID +// set_irq_priority(X, 0) <-- Set the priority of X to 0 (the max priority) +// set_priority_mask(0x1F) <-- Set Core's priority mask to 0x1F (the lowest priority) +// enable_GIC() <-- Enable the GIC (global) +// enable_gic_processor_interface() <-- Enable the CPU interface (local to the core) +// + + +// Global enable of the Interrupt Distributor +void enableGIC(void); + +// Global disable of the Interrupt Distributor +void disableGIC(void); + +// Enables the interrupt source number ID +void enableIntID(unsigned int ID); + +// Disables the interrupt source number ID +void disableIntID(unsigned int ID); + +// Sets the priority of the specified ID +void setIntPriority(unsigned int ID, unsigned int priority); + +// Enables the processor interface +// Must be done on each core separately +void enableGICProcessorInterface(void); + +// Disables the processor interface +// Must be done on each core separately +void disableGICProcessorInterface(void); + +// Sets the Priority mask register for the core run on +// The reset value masks ALL interrupts! +void setPriorityMask(unsigned int priority); + +// Sets the Binary Point Register for the core run on +void setBinaryPoint(unsigned int priority); + +// Returns the value of the Interrupt Acknowledge Register +unsigned int readIntAck(void); + +// Writes ID to the End Of Interrupt register +void writeEOI(unsigned int ID); + +// ------------------------------------------------------------ +// SGI +// ------------------------------------------------------------ + +// Send a software generate interrupt +void sendSGI(unsigned int ID, unsigned int core_list, unsigned int filter_list); + +#endif + +// ------------------------------------------------------------ +// End of MP_GIC.h +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_GIC.s b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_GIC.s new file mode 100644 index 00000000..a9c4520d --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_GIC.s @@ -0,0 +1,282 @@ +;---------------------------------------------------------------- +; Copyright (c) 2005-2018 Arm Limited (or its affiliates). All rights reserved. +; Use, modification and redistribution of this file is subject to your possession of a +; valid End User License Agreement for the Arm Product of which these examples are part of +; and your compliance with all applicable terms and conditions of such licence agreement. +; +; Cortex-A5MP SMP example - Startup Code +;---------------------------------------------------------------- + + + + AREA MP_GIC, CODE, READONLY + +;---------------------------------------------------------------- +; GIC. Generic Interrupt Controller Architecture Specification +;---------------------------------------------------------------- + + ; CPU Interface offset from base of private peripheral space --> 0x0100 + ; Interrupt Distributor offset from base of private peripheral space --> 0x1000 + + ; Typical calls to enable interrupt ID X: + ; enableIntID(X) <-- Enable that ID + ; setIntPriority(X, 0) <-- Set the priority of X to 0 (the max priority) + ; setPriorityMask(0x1F) <-- Set CPU's priority mask to 0x1F (the lowest priority) + ; enableGIC() <-- Enable the GIC (global) + ; enableGICProcessorInterface() <-- Enable the CPU interface (local to the CPU) + + + EXPORT enableGIC + ; void enableGIC(void) + ; Global enable of the Interrupt Distributor +enableGIC PROC + ; Get base address of private peripheral space + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + ADD r0, r0, #0x1000 ; Add the GIC offset + + LDR r1, [r0] ; Read the GIC Enable Register (ICDDCR) + ORR r1, r1, #0x01 ; Set bit 0, the enable bit + STR r1, [r0] ; Write the GIC Enable Register (ICDDCR) + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT disableGIC + ; void disableGIC(void) + ; Global disable of the Interrupt Distributor +disableGIC PROC + ; Get base address of private peripheral space + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + ADD r0, r0, #0x1000 ; Add the GIC offset + + LDR r1, [r0] ; Read the GIC Enable Register (ICDDCR) + BIC r1, r1, #0x01 ; Clear bit 0, the enable bit + STR r1, [r0] ; Write the GIC Enable Register (ICDDCR) + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT enableIntID + ; void enableIntID(unsigned int ID) + ; Enables the interrupt source number ID +enableIntID PROC + ; Get base address of private peripheral space + MOV r1, r0 ; Back up passed in ID value + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + ; Each interrupt source has an enable bit in the GIC. These + ; are grouped into registers, with 32 sources per register + ; First, we need to identify which 32-bit block the interrupt lives in + MOV r2, r1 ; Make working copy of ID in r2 + MOV r2, r2, LSR #5 ; LSR by 5 places, affective divide by 32 + ; r2 now contains the 32-bit block this ID lives in + MOV r2, r2, LSL #2 ; Now multiply by 4, to convert offset into an address offset (four bytes per reg) + + ; Now work out which bit within the 32-bit block the ID is + AND r1, r1, #0x1F ; Mask off to give offset within 32-bit block + MOV r3, #1 ; Move enable value into r3 + MOV r3, r3, LSL r1 ; Shift it left to position of ID + + ADD r2, r2, #0x1100 ; Add the base offset of the Enable Set registers to the offset for the ID + STR r3, [r0, r2] ; Store out (ICDISER) + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT disableIntID + ; void disableIntID(unsigned int ID) + ; Disables the interrupt source number ID +disableIntID PROC + ; Get base address of private peripheral space + MOV r1, r0 ; Back up passed in ID value + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + ; First, we need to identify which 32-bit block the interrupt lives in + MOV r2, r1 ; Make working copy of ID in r2 + MOV r2, r2, LSR #5 ; LSR by 5 places, affective divide by 32 + ; r2 now contains the 32-bit block this ID lives in + MOV r2, r2, LSL #2 ; Now multiply by 4, to convert offset into an address offset (four bytes per reg) + + ; Now work out which bit within the 32-bit block the ID is + AND r1, r1, #0x1F ; Mask off to give offset within 32-bit block + MOV r3, #1 ; Move enable value into r3 + MOV r3, r3, LSL r1 ; Shift it left to position of ID in 32-bit block + + ADD r2, r2, #0x1180 ; Add the base offset of the Enable Clear registers to the offset for the ID + STR r3, [r0, r2] ; Store out (ICDICER) + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT setIntPriority + ; void setIntPriority(unsigned int ID, unsigned int priority) + ; Sets the priority of the specified ID + ; r0 = ID + ; r1 = priority +setIntPriority PROC + ; Get base address of private peripheral space + MOV r2, r0 ; Back up passed in ID value + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + ; r0 = base addr + ; r1 = priority + ; r2 = ID + + ; Make sure that priority value is only 5 bits, and convert to expected format + AND r1, r1, #0x1F + MOV r1, r1, LSL #3 + + ; Find which register this ID lives in + BIC r3, r2, #0x03 ; Make a copy of the ID, clearing off the bottom two bits + ; There are four IDs per reg, by clearing the bottom two bits we get an address offset + ADD r3, r3, #0x1400 ; Now add the offset of the Priority Level registers from the base of the private peripheral space + ADD r0, r0, r3 ; Now add in the base address of the private peripheral space, giving us the absolute address + + ; Now work out which ID in the register it is + AND r2, r2, #0x03 ; Clear all but the bottom two bits, leaves which ID in the reg it is (which byte) + MOV r2, r2, LSL #3 ; Multiply by 8, this gives a bit offset + + ; Read -> Modify -> Write + MOV r12, #0xFF ; 8 bit field mask + MOV r12, r12, LSL r2 ; Move mask into correct bit position + MOV r1, r1, LSL r2 ; Also, move passed in priority value into correct bit position + + LDR r3, [r0] ; Read current value of the Priority Level register (ICDIPR) + BIC r3, r3, r12 ; Clear appropriate field + ORR r3, r3, r1 ; Now OR in the priority value + STR r3, [r0] ; And store it back again (ICDIPR) + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT enableGICProcessorInterface + ; void enableGICProcessorInterface(void) + ; Enables the processor interface + ; Must be done on each core separately +enableGICProcessorInterface PROC + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + LDR r1, [r0, #0x100] ; Read the Processor Interface Control register (ICCICR/ICPICR) + ORR r1, r1, #0x03 ; Bit 0: Enables secure interrupts, Bit 1: Enables Non-Secure interrupts + BIC r1, r1, #0x08 ; Bit 3: Ensure Group 0 interrupts are signalled using IRQ, not FIQ + STR r1, [r0, #0x100] ; Write the Processor Interface Control register (ICCICR/ICPICR) + + BX lr + ENDP + + +; ------------------------------------------------------------ + + EXPORT disableGICProcessorInterface + ; void disableGICProcessorInterface(void) + ; Disables the processor interface + ; Must be done on each core separately +disableGICProcessorInterface PROC + + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + LDR r1, [r0, #0x100] ; Read the Processor Interface Control register (ICCICR/ICPICR) + BIC r1, r1, #0x03 ; Bit 0: Enables secure interrupts, Bit 1: Enables Non-Secure interrupts + STR r1, [r0, #0x100] ; Write the Processor Interface Control register (ICCICR/ICPICR) + + BX lr + ENDP + + +; ------------------------------------------------------------ + + EXPORT setPriorityMask + ; void setPriorityMask(unsigned int priority) + ; Sets the Priority mask register for the CPU run on + ; The reset value masks ALL interrupts! +setPriorityMask PROC + + ; Get base address of private peripheral space + MRC p15, 4, r1, c15, c0, 0 ; Read periph base address + + STR r0, [r1, #0x0104] ; Write the Priority Mask register (ICCPMR/ICCIPMR) + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT setBinaryPoint + ; void setBinaryPoint(unsigned int priority) + ; Sets the Binary Point Register for the CPU run on +setBinaryPoint PROC + + ; Get base address of private peripheral space + MRC p15, 4, r1, c15, c0, 0 ; Read periph base address + + STR r0, [r1, #0x0108] ; Write the Binary register (ICCBPR/ICCBPR) + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT readIntAck + ; unsigned int readIntAck(void) + ; Returns the value of the Interrupt Acknowledge Register +readIntAck PROC + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + LDR r0, [r0, #0x010C] ; Read the Interrupt Acknowledge Register (ICCIAR) + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT writeEOI + ; void writeEOI(unsigned int ID) + ; Writes ID to the End Of Interrupt register +writeEOI PROC + + ; Get base address of private peripheral space + MRC p15, 4, r1, c15, c0, 0 ; Read periph base address + + STR r0, [r1, #0x0110] ; Write ID to the End of Interrupt register (ICCEOIR) + + BX lr + ENDP + +;---------------------------------------------------------------- +; SGI +;---------------------------------------------------------------- + + EXPORT sendSGI + ; void sendSGI(unsigned int ID, unsigned int target_list, unsigned int filter_list); + ; Send a software generate interrupt +sendSGI PROC + AND r3, r0, #0x0F ; Mask off unused bits of ID, and move to r3 + AND r1, r1, #0x0F ; Mask off unused bits of target_filter + AND r2, r2, #0x0F ; Mask off unused bits of filter_list + + ORR r3, r3, r1, LSL #16 ; Combine ID and target_filter + ORR r3, r3, r2, LSL #24 ; and now the filter list + + ; Get the address of the GIC + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + ADD r0, r0, #0x1F00 ; Add offset of the sgi_trigger reg + + STR r3, [r0] ; Write to the Software Generated Interrupt Register (ICDSGIR) + + BX lr + ENDP + + + END + +;---------------------------------------------------------------- +; End of MP_GIC.s +;---------------------------------------------------------------- diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_GlobalTimer.h b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_GlobalTimer.h new file mode 100644 index 00000000..27a02dc7 --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_GlobalTimer.h @@ -0,0 +1,42 @@ +// ------------------------------------------------------------ +// Cortex-A MPCore - Global timer functions +// Header Filer +// +// Copyright ARM Ltd 2009. All rights reserved. +// ------------------------------------------------------------ + +#ifndef _CORTEXA_GLOBAL_TIMER_ +#define _CORTEXA_GLOBAL_TIMER_ + +// Typical set of calls to enable Timer: +// init_global_timer( AUTO_INCREMENT>, INCREMENT_VALUE ); +// set_global_timer_comparator( UPPER_32_BITS, LOWER_32_BITS ); +// start_global_timer(); + + +// Sets up the private timer +// r0: IF 0 (AutoIncrement) ELSE (SingleShot) +// r1: Increment value (ignored if auto_increment != 0) +void init_global_timer(unsigned int auto_increment, unsigned int increment_value) + +// Sets the comparator value for this CPU +void set_global_timer_comparator(unsigned int top, unsigned int bottom); + +// Starts the private timer +void start_global_timer(void); + +// Stops the private timer +void stop_global_timer(void); + +// Reads the current value of the timer count register +// Returns bits 63:32 in *top, and bits 31:0 in *bottom +void read_global_timer(unsigned int* top, unsigned int* bottom); + +// Clears the private timer interrupt +void clear_global_timer_irq(void); + +#endif + +// ------------------------------------------------------------ +// End of MP_PrivateTimer.h +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_GlobalTimer.s b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_GlobalTimer.s new file mode 100644 index 00000000..17997051 --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_GlobalTimer.s @@ -0,0 +1,168 @@ +; ------------------------------------------------------------ +; Cortex-A MPCore - Global timer functions +; +; Copyright ARM Ltd 2009. All rights reserved. +; ------------------------------------------------------------ + + PRESERVE8 + + AREA MP_PrivateTimer, CODE, READONLY + + ; PPI ID 27 + + + ; Typical set of calls to enable Timer: + ; init_global_timer() + ; set_global_timer_comparator() + ; start_global_timer() + +; ------------------------------------------------------------ + + EXPORT init_global_timer + ; void init_global_timer(unsigned int auto_increment, unsigned int increment_value) + ; Initializes the Global Timer, but does NOT set the enable bit + ; r0: IF 0 (AutoIncrement) ELSE (SingleShot) + ; r1: increment value +init_global_timer PROC + + ; Get base address of private perpherial space + MRC p15, 4, r2, c15, c0, 0 ; Read periph base address + + ; Control register bit layout + ; Bit 0 - Timer enable + ; Bit 1 - Comp enable + ; Bit 2 - IRQ enable + ; Bit 3 - Auto-increment enable + + ; Ensure the timer is disabled + LDR r3, [r2, #0x208] ; Read control reg + BIC r3, r3, #0x01 ; Clear enable bit + STR r3, [r2, #0x208] ; Write control reg + + ; Form control reg value + CMP r0, #0 ; Check whether to enable auto-reload + MOVNE r0, #0x00 ; No auto-reload + MOVEQ r0, #0x04 ; With auto-reload + STR r0, [r2, #0x208] ; Store to control register + + ; Store increment value + STREQ r1, [r2, #0x218] + + ; Clear timer value + MOV r0, #0x0 + STR r0, [r2, #0x0] + STR r0, [r2, #0x4] + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT set_global_timer_comparator + ; void set_global_timer_comparator(unsigned int top, unsigned int bottom); + ; Writes the comparator registers, and enable the comparator bit in the control register + ; r0: 63:32 of the comparator value + ; r1: 31:0 of the comparator value +set_global_timer_comparator PROC + + MRC p15, 4, r2, c15, c0, 0 ; Read periph base address + + ; Disable comparator before updating register + LDR r1, [r2, #0x208] ; Read control reg + BIC r3, r3, #0x02 ; Clear comparator enable bit + STR r3, [r2, #0x208] ; Write modified value back + + ; Write the comparator registers + STR r1, [r2, #0x210] ; Write lower 32 bits + STR r0, [r2, #0x214] ; Write upper 32 bits + DMB + + ; Re-enable the comparator + ORR r3, r3, #0x02 ; Set comparator enable bit + STR r3, [r2, #0x208] ; Write modified value back + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT start_global_timer + ; void start_global_timer(void) + ; Starts the global timer +start_global_timer PROC + + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + LDR r1, [r0, #0x208] ; Read control reg + ORR r1, r1, #0x01 ; Set enable bit + STR r1, [r0, #0x208] ; Write modified value back + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT stop_global_timer + ; void stop_global_timer + ; Stops the stop_global_timer timer +stop_global_timer PROC + + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + LDR r1, [r0, #0x208] ; Read control reg + BIC r1, r1, #0x01 ; Clear enable bit + STR r1, [r0, #0x208] ; Write modified value back + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT get_global_timer_count + ; void read_global_timer(unsigned int* top, unsigned int* bottom) + ; Reads the current value of the timer count register + ; r0: Address of unsigned int for bits 63:32 + ; r1: Address of unsigned int for bits 31:0 +get_global_timer_count PROC + +get_global_timer_count_loop + MRC p15, 4, r2, c15, c0, 0 ; Read periph base address + + LDR r12,[r2, #0x04] ; Read bits 63:32 + LDR r3, [r2, #0x00] ; Read bits 31:0 + LDR r2, [r2, #0x04] ; Re-read bits 63:32 + + CMP r2, r12 ; Have the top bits changed? + BNE get_global_timer_count_loop + + ; Store result out to pointers + STR r2, [r0] + STR r3, [r1] + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT clear_global_timer_irq + ; void clear_global_timer_irq(void) + ; Clears the global timer interrupt +clear_global_timer_irq PROC + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + ; Clear the interrupt by writing 0x1 to the Timer's Interrupt Status register + MOV r1, #1 + STR r1, [r0, #0x20C] + + BX lr + ENDP + +; ------------------------------------------------------------ +; End of code +; ------------------------------------------------------------ + + END + +; ------------------------------------------------------------ +; End of MP_GlobalTimer.s +; ------------------------------------------------------------ diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_Mutexes.h b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_Mutexes.h new file mode 100644 index 00000000..e410677b --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_Mutexes.h @@ -0,0 +1,40 @@ +// ------------------------------------------------------------ +// MP Mutex Header File +// +// Copyright (c) 2011-2014 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#ifndef MP_MUTEX_H +#define MP_MUTEX_H + +// 0xFF = unlocked +// 0x0 = Locked by CPU 0 +// 0x1 = Locked by CPU 1 +// 0x2 = Locked by CPU 2 +// 0x3 = Locked by CPU 3 +typedef struct +{ + unsigned int lock; +}mutex_t; + +// Places mutex into a known state +// r0 = address of mutex_t +void initMutex(mutex_t* pMutex); + +// Blocking call, returns once successfully locked a mutex +// r0 = address of mutex_t +void lockMutex(mutex_t* pMutex); + +// Releases (unlock) mutex. Fails if CPU not owner of mutex. +// returns 0x0 for success, and 0x1 for failure +// r0 = address of mutex_t +unsigned int unlockMutex(mutex_t* pMutex); + +// Returns 0x0 if mutex unlocked, 0x1 is locked +// r0 = address of mutex_t +unsigned int isMutexLocked(mutex_t* pMutex); + +#endif diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_Mutexes.s b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_Mutexes.s new file mode 100644 index 00000000..0574eab0 --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_Mutexes.s @@ -0,0 +1,123 @@ +; ------------------------------------------------------------ +; Cortex-A MPCore - Mutex Code +; +; Copyright (c) 2011-2012 Arm Limited (or its affiliates). All rights reserved. +; Use, modification and redistribution of this file is subject to your possession of a +; valid End User License Agreement for the Arm Product of which these examples are part of +; and your compliance with all applicable terms and conditions of such licence agreement. +; ------------------------------------------------------------ + + + + AREA MP_Mutexes, CODE, READONLY + + ;NOTES + ; struct mutex_t defined in MP_Mutexes.h + ; typedef struct mutex_t + ; { + ; unsigned int lock; <-- offset 0 + ; } + ; + ; lock: 0xFF=unlocked 0x0 = Locked by CPU 0, 0x1 = Locked by CPU 1, 0x2 = Locked by CPU 2, 0x3 = Locked by CPU 3 + ; + +UNLOCKED EQU 0xFF + +; ------------------------------------------------------------ + + EXPORT initMutex + ; void initMutex(mutex_t* pMutex) + ; Places mutex into a known state + ; r0 = address of mutex_t +initMutex PROC + + MOV r1, #UNLOCKED ; Mark as unlocked + STR r1, [r0] + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT lockMutex + ; void lockMutex(mutex_t* pMutex) + ; Blocking call, returns once successfully locked a mutex + ; r0 = address of mutex_t +lockMutex PROC + + ; Is mutex locked? + ; ----------------- + LDREX r1, [r0] ; Read lock field + CMP r1, #UNLOCKED ; Compare with "unlocked" + + WFENE ; If mutex is locked, go into standby + BNE lockMutex ; On waking re-check the mutex + + ; Attempt to lock mutex + ; ----------------------- + MRC p15, 0, r1, c0, c0, 5 ; Read CPU ID register + AND r1, r1, #0x03 ; Mask off, leaving the CPU ID field. + STREX r2, r1, [r0] ; Attempt to lock mutex, by write CPU's ID to lock field + CMP r2, #0x0 ; Check whether store completed successfully (0=succeeded) + BNE lockMutex ; If store failed, go back to beginning and try again + + DMB + + BX lr ; Return as mutex is now locked by this cpu + ENDP + +; ------------------------------------------------------------ + + EXPORT unlockMutex + ; unsigned int unlockMutex(mutex_t* pMutex) + ; Releases mutex, returns 0x0 for success and 0x1 for failure + ; r0 = address of mutex_t +unlockMutex PROC + + ; Does this CPU own the mutex? + ; ----------------------------- + MRC p15, 0, r1, c0, c0, 5 ; Read CPU ID register + AND r1, r1, #0x03 ; Mask off, leaving the CPU ID in r1 + LDR r2, [r0] ; Read the lock field of the mutex + CMP r1, r2 ; Compare ID of this CPU with the lock owner + MOVNE r0, #0x1 ; If ID doesn't match, return "fail" + BXNE lr + + + ; Unlock mutex + ; ------------- + DMB ; Ensure that accesses to shared resource have completed + + MOV r1, #UNLOCKED ; Write "unlocked" into lock field + STR r1, [r0] + + DSB ; Ensure that no instructions following the barrier execute until + ; all memory accesses prior to the barrier have completed. + + SEV ; Send event to other CPUs, wakes anyone waiting on a mutex (using WFE) + + MOV r0, #0x0 ; Return "success" + BX lr + + ENDP + +; ------------------------------------------------------------ + + EXPORT isMutexLocked + ; unsigned int isMutexLocked(mutex_t* pMutex) + ; Returns 0x0 if mutex unlocked, 0x1 is locked + ; r0 = address of mutex_t +isMutexLocked PROC + LDR r0, [r0] + CMP r0, #UNLOCKED + MOVEQ r0, #0x0 + MOVNE r0, #0x1 + BX lr + ENDP + + + END + +; ------------------------------------------------------------ +; End of MP_Mutexes.s +; ------------------------------------------------------------ diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_PrivateTimer.h b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_PrivateTimer.h new file mode 100644 index 00000000..b0ab212a --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_PrivateTimer.h @@ -0,0 +1,36 @@ +// ------------------------------------------------------------ +// Cortex-A MPCore - Private timer functions +// Header Filer +// +// Copyright ARM Ltd 2009. All rights reserved. +// ------------------------------------------------------------ + +#ifndef _CORTEXA_PRIVATE_TIMER_ +#define _CORTEXA_PRIVATE_TIMER_ + +// Typical set of calls to enable Timer: +// init_private_timer(0xXXXX, 0) <-- Counter down value of 0xXXXX, with auto-reload +// start_private_timer() + +// Sets up the private timer +// r0: initial load value +// r1: IF 0 (AutoReload) ELSE (SingleShot) +void init_private_timer(unsigned int load_value, unsigned int auto_reload); + +// Starts the private timer +void start_private_timer(void); + +// Stops the private timer +void stop_private_timer(void); + +// Reads the current value of the timer count register +unsigned int get_private_timer_count(void); + +// Clears the private timer interrupt +void clear_private_timer_irq(void); + +#endif + +// ------------------------------------------------------------ +// End of MP_PrivateTimer.h +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_PrivateTimer.s b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_PrivateTimer.s new file mode 100644 index 00000000..f8a1eefa --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_PrivateTimer.s @@ -0,0 +1,121 @@ +; ------------------------------------------------------------ +; Cortex-A MPCore - Private timer functions +; +; Copyright ARM Ltd 2009. All rights reserved. +; ------------------------------------------------------------ + + PRESERVE8 + + AREA MP_PrivateTimer, CODE, READONLY + + ; PPI ID 29 + + + ; Typical set of calls to enable Timer: + ; init_private_timer(0xXXXX, 0) <-- Counter down value of 0xXXXX, with auto-reload + ; start_private_timer() + + ; Timer offset from base of private peripheral space --> 0x600 + +; ------------------------------------------------------------ + + EXPORT init_private_timer + ; void init_private_timer(unsigned int load_value, unsigned int auto_reload) + ; Sets up the private timer + ; r0: initial load value + ; r1: IF 0 (AutoReload) ELSE (SingleShot) +init_private_timer PROC + + ; Get base address of private perpherial space + MOV r2, r0 ; Make a copy of r0 before corrupting + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + ; Set the load value + STR r2, [r0, #0x600] + + ; Control register bit layout + ; Bit 0 - Enable + ; Bit 1 - Auto-Reload ; see DE681117 + ; Bit 2 - IRQ Generation + + ; Form control reg value + CMP r1, #0 ; Check whether to enable auto-reload + MOVNE r2, #0x04 ; No auto-reload + MOVEQ r2, #0x06 ; With auto-reload + + ; Store to control register + STR r2, [r0, #0x608] + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT start_private_timer + ; void start_private_timer(void) + ; Starts the private timer +start_private_timer PROC + + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + LDR r1, [r0, #0x608] ; Read control reg + ORR r1, r1, #0x01 ; Set enable bit + STR r1, [r0, #0x608] ; Write modified value back + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT stop_private_timer + ; void stop_private_timer(void) + ; Stops the private timer +stop_private_timer PROC + + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + LDR r1, [r0, #0x608] ; Read control reg + BIC r1, r1, #0x01 ; Clear enable bit + STR r1, [r0, #0x608] ; Write modified value back + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT get_private_timer_count + ; unsigned int read_private_timer(void) + ; Reads the current value of the timer count register +get_private_timer_count PROC + + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + LDR r0, [r0, #0x604] ; Read count register + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT clear_private_timer_irq + ; void clear_private_timer_irq(void) + ; Clears the private timer interrupt +clear_private_timer_irq PROC + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + ; Clear the interrupt by writing 0x1 to the Timer's Interrupt Status register + MOV r1, #1 + STR r1, [r0, #0x60C] + + BX lr + ENDP + +; ------------------------------------------------------------ +; End of code +; ------------------------------------------------------------ + + END + +; ------------------------------------------------------------ +; End of MP_PrivateTimer.s +; ------------------------------------------------------------ diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_SCU.h b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_SCU.h new file mode 100644 index 00000000..a056bd3f --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_SCU.h @@ -0,0 +1,55 @@ +// ------------------------------------------------------------ +// Cortex-A9 MPCore - Snoop Control Unit +// Header File +// +// Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#ifndef _CORTEXA_SCU_ +#define _CORTEXA_SCU_ + +// ------------------------------------------------------------ +// Misc +// ------------------------------------------------------------ + +// Returns the number of cores in the cluster +// This is the format of the register, decided to leave it unchanged. +unsigned int getNumCPUs(void); + +// Go to sleep, never returns +void goToSleep(void); + +// ------------------------------------------------------------ +// SCU +// ------------------------------------------------------------ + +// Enables the SCU +void enableSCU(void); + +// The return value is 1 bit per core: +// bit 0 - CPU 0 +// bit 1 - CPU 1 +// etc... +unsigned int getCPUsInSMP(void); + + //Enable the broadcasting of cache & TLB maintenance operations +// When enabled AND in SMP, broadcast all "inner sharable" +// cache and TLM maintenance operations to other SMP cores +void enableMaintenanceBroadcast(void); + +// Disable the broadcasting of cache & TLB maintenance operations +void disableMaintenanceBroadcast(void); + +// cpu: 0x0=CPU 0 0x1=CPU 1 etc... +// This function invalidates the SCU copy of the tag rams +// for the specified core. +void secureSCUInvalidate(unsigned int cpu, unsigned int ways); + +#endif + +// ------------------------------------------------------------ +// End of MP_SCU.h +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_SCU.s b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_SCU.s new file mode 100644 index 00000000..2c24df11 --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/MP_SCU.s @@ -0,0 +1,132 @@ +;---------------------------------------------------------------- +; Copyright (c) 2005-2018 Arm Limited (or its affiliates). All rights reserved. +; Use, modification and redistribution of this file is subject to your possession of a +; valid End User License Agreement for the Arm Product of which these examples are part of +; and your compliance with all applicable terms and conditions of such licence agreement. +; +; Cortex-A SMP example - Startup Code +;---------------------------------------------------------------- + + + + AREA MP_SCU, CODE, READONLY + +;---------------------------------------------------------------- +; Misc +;---------------------------------------------------------------- + + EXPORT getNumCPUs + ; unsigned int getNumCPUs(void) + ; Returns the number of CPUs in the Cluster +getNumCPUs PROC + + ; Get base address of private peripheral space + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + LDR r0, [r0, #0x004] ; Read SCU Configuration register + AND r0, r0, #0x3 ; Bits 1:0 gives the number of cores-1 + ADD r0, r0, #1 + BX lr + ENDP + +;---------------------------------------------------------------- +; SCU +;---------------------------------------------------------------- + + ; SCU offset from base of private peripheral space --> 0x000 + + EXPORT enableSCU + ; void enableSCU(void) + ; Enables the SCU +enableSCU PROC + + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + LDR r1, [r0, #0x0] ; Read the SCU Control Register + ORR r1, r1, #0x1 ; Set bit 0 (The Enable bit) + STR r1, [r0, #0x0] ; Write back modifed value + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT getCPUsInSMP + ; unsigned int getCPUsInSMP(void) + ; The return value is 1 bit per core: + ; bit 0 - CPU 0 + ; bit 1 - CPU 1 + ; etc... +getCPUsInSMP PROC + + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + LDR r0, [r0, #0x004] ; Read SCU Configuration register + MOV r0, r0, LSR #4 ; Bits 7:4 gives the cores in SMP mode, shift then mask + AND r0, r0, #0x0F + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT enableMaintenanceBroadcast + ; void enableMaintenanceBroadcast(void) + ; Enable the broadcasting of cache & TLB maintenance operations + ; When enabled AND in SMP, broadcast all "inner sharable" + ; cache and TLM maintenance operations to other SMP cores +enableMaintenanceBroadcast PROC + MRC p15, 0, r0, c1, c0, 1 ; Read Aux Ctrl register + MOV r1, r0 + ORR r0, r0, #0x01 ; Set the FW bit (bit 0) + CMP r0, r1 + MCRNE p15, 0, r0, c1, c0, 1 ; Write Aux Ctrl register + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT disableMaintenanceBroadcast + ; void disableMaintenanceBroadcast(void) + ; Disable the broadcasting of cache & TLB maintenance operations +disableMaintenanceBroadcast PROC + MRC p15, 0, r0, c1, c0, 1 ; Read Aux Ctrl register + BIC r0, r0, #0x01 ; Clear the FW bit (bit 0) + MCR p15, 0, r0, c1, c0, 1 ; Write Aux Ctrl register + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT secureSCUInvalidate + ; void secureSCUInvalidate(unsigned int cpu, unsigned int ways) + ; cpu: 0x0=CPU 0 0x1=CPU 1 etc... + ; This function invalidates the SCU copy of the tag rams + ; for the specified core. Typically only done at start-up. + ; Possible flow: + ; - Invalidate L1 caches + ; - Invalidate SCU copy of TAG RAMs + ; - Join SMP +secureSCUInvalidate PROC + AND r0, r0, #0x03 ; Mask off unused bits of CPU ID + MOV r0, r0, LSL #2 ; Convert into bit offset (four bits per core) + + AND r1, r1, #0x0F ; Mask off unused bits of ways + MOV r1, r1, LSL r0 ; Shift ways into the correct CPU field + + MRC p15, 4, r2, c15, c0, 0 ; Read periph base address + + STR r1, [r2, #0x0C] ; Write to SCU Invalidate All in Secure State + + BX lr + + ENDP + + + END + +;---------------------------------------------------------------- +; End of MP_SCU.s +;---------------------------------------------------------------- diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/sample_threadx.c new file mode 100644 index 00000000..1b6df7c2 --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/sample_threadx.c @@ -0,0 +1,381 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_TIMER timer_0; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +#ifdef TX_ENABLE_EVENT_TRACE + +UCHAR event_buffer[65536]; + +#endif + + + +int main(void) +{ + + /* Enter ThreadX. */ + tx_kernel_enter(); + + return 0; +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + +#ifdef TX_ENABLE_EVENT_TRACE + + tx_trace_enable(event_buffer, sizeof(event_buffer), 32); +#endif + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/sample_threadx.launch b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/sample_threadx.launch new file mode 100644 index 00000000..70999d32 --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/sample_threadx.launch @@ -0,0 +1,158 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/sample_threadx.sct b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/sample_threadx.sct new file mode 100644 index 00000000..6cdf755a --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/sample_threadx.sct @@ -0,0 +1,37 @@ +;************************************************** +; Copyright (c) 2012 Arm Limited (or its affiliates). All rights reserved. +; Use, modification and redistribution of this file is subject to your possession of a +; valid End User License Agreement for the Arm Product of which these examples are part of +; and your compliance with all applicable terms and conditions of such licence agreement. +;************************************************** + +; Scatter-file for Cortex-A5 MPCore bare-metal example on Versatile Express + +; This scatter-file places application code, data, stack and heap at suitable addresses in memory map. + +; CoreTile Express A5x2 has 1GB SDRAM at 0x80000000 to 0xBFFFFFFF, which this scatter-file uses. + +LOAD 0x80000000 0x00010000 +{ + EXEC +0 + { + startup.o (StartUp, +FIRST) + * (+RO) + } + + ; App heap for all CPUs + ARM_LIB_HEAP +0 ALIGN 8 EMPTY 0x8000 {} + + ; App stacks for all CPUs - see startup.s + ARM_LIB_STACK +0 ALIGN 8 EMPTY 4*0x4000 {} + + ; IRQ stacks for all CPUs - see startup.s + IRQ_STACKS +0 ALIGN 8 EMPTY 4*1024 {} + + SHARED_DATA +0x0 + { + * (+RW,+ZI) + } + + PAGETABLES 0x80500000 EMPTY 0x00100000 {} +} \ No newline at end of file diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/startup.s b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/startup.s new file mode 100644 index 00000000..ce0e75a3 --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/startup.s @@ -0,0 +1,582 @@ +; ------------------------------------------------------------ +; Cortex-A5 MPCore Startup Code +; +; Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. +; Use, modification and redistribution of this file is subject to your possession of a +; valid End User License Agreement for the Arm Product of which these examples are part of +; and your compliance with all applicable terms and conditions of such licence agreement. +; ------------------------------------------------------------ + + PRESERVE8 + + AREA StartUp,CODE,READONLY + +; Standard definitions of mode bits and interrupt (I&F) flags in PSRs + +Mode_USR EQU 0x10 +Mode_FIQ EQU 0x11 +Mode_IRQ EQU 0x12 +Mode_SVC EQU 0x13 +Mode_ABT EQU 0x17 +Mode_UND EQU 0x1B +Mode_SYS EQU 0x1F + +I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled +F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled + + +; ------------------------------------------------------------ +; Porting defines +; ------------------------------------------------------------ + +L1_COHERENT EQU 0x00014c06 ; Template descriptor for coherent memory +L1_NONCOHERENT EQU 0x00000c1e ; Template descriptor for non-coherent memory +L1_DEVICE EQU 0x00000c16 ; Template descriptor for device memory + +; ------------------------------------------------------------ + + ENTRY + + EXPORT Vectors + +Vectors + B Reset_Handler + B Undefined_Handler + B SVC_Handler + B Prefetch_Handler + B Abort_Handler + B . ;Reserved vector + B IRQ_Handler + B FIQ_Handler + +; ------------------------------------------------------------ +; Handlers for unused exceptions +; ------------------------------------------------------------ + +Undefined_Handler + B Undefined_Handler +SVC_Handler + B SVC_Handler +Prefetch_Handler + B Prefetch_Handler +Abort_Handler + B Abort_Handler +FIQ_Handler + B FIQ_Handler + +; ------------------------------------------------------------ +; Imports +; ------------------------------------------------------------ + IMPORT readIntAck + IMPORT writeEOI + IMPORT enableGIC + IMPORT enableGICProcessorInterface + IMPORT setPriorityMask + IMPORT enableIntID + IMPORT setIntPriority + IMPORT enableSCU + IMPORT joinSMP + IMPORT clear_private_timer_irq + IMPORT init_private_timer + IMPORT start_private_timer + IMPORT secureSCUInvalidate + IMPORT enableMaintenanceBroadcast + IMPORT invalidateCaches + IMPORT disableHighVecs + IMPORT __main +; IMPORT main_app +; [EL Change Start] + IMPORT _tx_thread_smp_initialize_wait + IMPORT _tx_thread_smp_release_cores_flag + IMPORT _tx_thread_context_save + IMPORT _tx_thread_context_restore + IMPORT _tx_timer_interrupt + IMPORT _tx_thread_smp_inter_core_interrupts +; [EL Change End] + + IMPORT __use_two_region_memory + IMPORT ||Image$$ARM_LIB_STACK$$ZI$$Limit|| + IMPORT ||Image$$IRQ_STACKS$$ZI$$Limit|| + IMPORT ||Image$$PAGETABLES$$ZI$$Base|| + IMPORT ||Image$$EXEC$$Base|| + +; ------------------------------------------------------------ +; Interrupt Handler +; ------------------------------------------------------------ + + EXPORT IRQ_Handler + EXPORT __tx_irq_processing_return +IRQ_Handler PROC +; [EL Change Start] +; SUB lr, lr, #4 ; Pre-adjust lr +; SRSFD sp!, #Mode_IRQ ; Save lr and SPRS to IRQ mode stack +; PUSH {r0-r4, r12} ; Sace APCS corruptable registers to IRQ mode stack (and maintain 8 byte alignment) +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return + PUSH {r4, r5} ; Save some preserved registers (r5 is saved just for 8-byte alignment) +; [EL Change End] + + ; Acknowledge the interrupt + BL readIntAck + MOV r4, r0 + + ; + ; This example only uses (and enables) one. At this point + ; you would normally check the ID, and clear the source. + ; + + ; + ; Additonal code to handler private timer interrupt on CPU0 + ; + + CMP r0, #29 ; If not Private Timer interrupt (ID 29), by pass + BNE by_pass + +; [EL Change Start] +; MOV r0, #0x04 ; Code for SYS_WRITE0 +; LDR r1, =irq_handler_message0 +; SVC 0x123456 +; [EL Change End] + + ; Clear timer interrupt + BL clear_private_timer_irq + DSB +; [EL Change Start] + BL _tx_timer_interrupt ; Timer interrupt handler +; [EL Change End] + + B by_pass2 + +by_pass + +; [EL Change Start] + ; + ; Additional code to handle SGI on CPU0 + ; +; +; MRC p15, 0, r0, c0, c0, 5 ; Read CPU ID register +; ANDS r0, r0, #0x03 ; Mask off, leaving the CPU ID field +; BNE by_pass2 +; +; MOV r0, #0x04 ; Code for SYS_WRITE0 +; LDR r1, =irq_handler_message1 +; SVC 0x123456 +; +; /* Just increment the per-thread interrupt count for analysis purposes. */ +; + MRC p15, 0, r0, c0, c0, 5 ; Read CPU ID register + AND r0, r0, #0x03 ; Mask off, leaving the CPU ID field + LSL r0, r0, #2 ; Build offset to array indexes + LDR r1,=_tx_thread_smp_inter_core_interrupts ; Pickup base address of core interrupt counter array + ADD r1, r1, r0 ; Build array index + LDR r0, [r1] ; Pickup counter + ADD r0, r0, #1 ; Increment counter + STR r0, [r1] ; Store back counter +; +; [EL Change End] + + +by_pass2 + ; Write end of interrupt reg + MOV r0, r4 + BL writeEOI + +; [EL Change Start] + +; +; /* Jump to context restore to restore system context. */ + POP {r4, r5} ; Recover preserved registers + B _tx_thread_context_restore + +; POP {r0-r4, r12} ; Restore stacked APCS registers +; MOV r2, #0x01 ; Set r2 so CPU leaves holding pen +; RFEFD sp! ; Return from exception +; [EL Change End] + + ENDP + +; ------------------------------------------------------------ +; Reset Handler - Generic initialization, run by all CPUs +; ------------------------------------------------------------ + + EXPORT Reset_Handler +Reset_Handler PROC {} + +; ------------------------------------------------------------ +; Disable caches and MMU in case they were left enabled from an earlier run +; This does not need to be done from a cold reset +; ------------------------------------------------------------ + MRC p15, 0, r0, c1, c0, 0 ; Read System Control Register + BIC r0, r0, #(0x1 << 12) ; Clear I, bit 12, to disable I Cache + BIC r0, r0, #(0x1 << 2) ; Clear C, bit 2, to disable D Cache + BIC r0, r0, #(0x1 << 1) ; Clear A, bit 1, to disable strict alignment fault checking + BIC r0, r0, #0x1 ; Clear M, bit 0, to disable MMU + MCR p15, 0, r0, c1, c0, 0 ; Write System Control Register + ISB + +; The MMU is enabled later, before calling main(). Caches are enabled inside main(), +; after the MMU has been enabled and scatterloading has been performed. + + ; + ; Setup stacks + ;--------------- + + MRC p15, 0, r0, c0, c0, 5 ; Read CPU ID register + ANDS r0, r0, #0x03 ; Mask off, leaving the CPU ID field + + MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit + LDR r1, =||Image$$IRQ_STACKS$$ZI$$Limit|| + SUB r1, r1, r0, LSL #10 ; 1024 bytes of IRQ stack per CPU - see scatter.scat + MOV sp, r1 + + MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit ; Interrupts initially disabled + LDR r1, =||Image$$ARM_LIB_STACK$$ZI$$Limit|| ; App stacks for all CPUs + SUB r1, r1, r0, LSL #14 ; 0x4000 bytes of App stack per CPU - see scatter.scat + MOV sp, r1 + + ; + ; Set vector base address + ; ------------------------ + LDR r0, =Vectors + MCR p15, 0, r0, c12, c0, 0 ; Write Secure or Non-secure Vector Base Address + BL disableHighVecs ; Ensure that V-bit is cleared + + ; + ; Invalidate caches + ; ------------------ + BL invalidateCaches + + ; + ; Clear Branch Prediction Array + ; ------------------------------ + MOV r0, #0x0 + MCR p15, 0, r0, c7, c5, 6 ; BPIALL - Invalidate entire branch predictor array + + ; + ; Invalidate TLBs + ;------------------ + MOV r0, #0x0 + MCR p15, 0, r0, c8, c7, 0 ; TLBIALL - Invalidate entire Unified TLB + + ; + ; Set up Domain Access Control Reg + ; ---------------------------------- + ; b00 - No Access (abort) + ; b01 - Client (respect table entry) + ; b10 - RESERVED + ; b11 - Manager (ignore access permissions) + + MRC p15, 0, r0, c3, c0, 0 ; Read Domain Access Control Register + LDR r0, =0x55555555 ; Initialize every domain entry to b01 (client) + MCR p15, 0, r0, c3, c0, 0 ; Write Domain Access Control Register + + ;; + ;; Enable L1 Preloader - Auxiliary Control + ;; ----------------------------------------- + ;; Seems to undef on panda? + ;MRC p15, 0, r0, c1, c0, 1 ; Read ACTLR + ;ORR r0, r0, #0x4 + ;MCR p15, 0, r0, c1, c0, 1 ; Write ACTLR + ISB + + + ; + ; Set location of level 1 page table + ;------------------------------------ + ; 31:14 - Base addr + ; 13:5 - 0x0 + ; 4:3 - RGN 0x0 (Outer Noncachable) + ; 2 - P 0x0 + ; 1 - S 0x0 (Non-shared) + ; 0 - C 0x0 (Inner Noncachable) + LDR r0, =||Image$$PAGETABLES$$ZI$$Base|| + MSR TTBR0, r0 + + + ; + ; Activate VFP/NEON, if required + ;------------------------------- + + IF {TARGET_FEATURE_NEON} || {TARGET_FPU_VFP} + + ; Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11. + ; Enables Full Access i.e. in both privileged and non privileged modes + MRC p15, 0, r0, c1, c0, 2 ; Read Coprocessor Access Control Register (CPACR) + ORR r0, r0, #(0xF << 20) ; Enable access to CP 10 & 11 + MCR p15, 0, r0, c1, c0, 2 ; Write Coprocessor Access Control Register (CPACR) + ISB + + ; Switch on the VFP and NEON hardware + MOV r0, #0x40000000 + VMSR FPEXC, r0 ; Write FPEXC register, EN bit set + + ENDIF + +; [EL Change Start] + + LDR r0, =_tx_thread_smp_release_cores_flag ; Build address of release cores flag + MOV r1, #0 + STR r1, [r0] + +; [EL Change End] + ; + ; SMP initialization + ; ------------------- + MRC p15, 0, r0, c0, c0, 5 ; Read CPU ID register + ANDS r0, r0, #0x03 ; Mask off, leaving the CPU ID field + BEQ primaryCPUInit + BNE secondaryCPUsInit + + ENDP + + +; ------------------------------------------------------------ +; Initialization for PRIMARY CPU +; ------------------------------------------------------------ + + EXPORT primaryCPUInit +primaryCPUInit PROC + + ; Translation tables + ; ------------------- + ; The translation tables are generated at boot time. + ; First the table is zeroed. Then the individual valid + ; entries are written in + ; + + LDR r0, =||Image$$PAGETABLES$$ZI$$Base|| + + ; Fill table with zeros + MOV r2, #1024 ; Set r3 to loop count (4 entries per iteration, 1024 iterations) + MOV r1, r0 ; Make a copy of the base dst + MOV r3, #0 + MOV r4, #0 + MOV r5, #0 + MOV r6, #0 +ttb_zero_loop + STMIA r1!, {r3-r6} ; Store out four entries + SUBS r2, r2, #1 ; Decrement counter + BNE ttb_zero_loop + + ; + ; STANDARD ENTRIES + ; + + ; Region covering program code and data + LDR r1,=||Image$$EXEC$$Base|| ; Base physical address of program code and data + LSR r1,#20 ; Shift right to align to 1MB boundaries + LDR r3, =L1_COHERENT ; Descriptor template + ORR r3, r1, LSL#20 ; Combine address and template + STR r3, [r0, r1, LSL#2] ; Store table entry + + ; Entry for private address space + ; Needs to be marked as Device memory + MRC p15, 4, r1, c15, c0, 0 ; Get base address of private address space + LSR r1, r1, #20 ; Clear bottom 20 bits, to find which 1MB block it is in + LSL r2, r1, #2 ; Make a copy, and multiply by four. This gives offset into the page tables + LSL r1, r1, #20 ; Put back in address format + LDR r3, =L1_DEVICE ; Descriptor template + ORR r1, r1, r3 ; Combine address and template + STR r1, [r0, r2] ; Store table entry + + ; + ; OPTIONAL ENTRIES + ; You will need additional translations if: + ; - No RAM at zero, so cannot use flat mapping + ; - You wish to retarget + ; + ; If you wish to output to stdio to a UART you will need + ; an additional entry + ;LDR r1, =PABASE_UART ; Physical address of UART + ;LSR r1, r1, #20 ; Mask off bottom 20 bits to find which 1MB it is within + ;LSL r2, r1, #2 ; Make a copy and multiply by 4 to get table offset + ;LSL r1, r1, #20 ; Put back into address format + ;LDR r3, =L1_DEVICE ; Descriptor template + ;ORR r1, r1, r3 ; Combine address and template + ;STR r1, [r0, r2] ; Store table entry + + DSB + + + ; Enable MMU + ; ----------- + ; Leave the caches disabled until after scatter loading. + MRC p15, 0, r0, c1, c0, 0 ; Read System Control Register + ORR r0, r0, #0x1 ; Set M bit 0 to enable MMU before scatter loading + MCR p15, 0, r0, c1, c0, 0 ; Write System Control Register + ISB + + + ; Enable the SCU + ; --------------- + BL enableSCU + + ; + ; Join SMP + ; --------- + MOV r0, #0x0 ; Move CPU ID into r0 + MOV r1, #0xF ; Move 0xF (represents all four ways) into r1 + BL secureSCUInvalidate + BL joinSMP + BL enableMaintenanceBroadcast + + ; + ; GIC Init + ; --------- + BL enableGIC + BL enableGICProcessorInterface + + ; + ; Enable Private Timer for periodic IRQ + ; -------------------------------------- + MOV r0, #0x1F + BL setPriorityMask ; Set priority mask (local) + + ; [EL] Change start - don't enable interrupts here! + ;CPSIE i ; Clear CPSR I bit + ; [EL] Change end + + ; Enable the Private Timer Interrupt Source + MOV r0, #29 + MOV r1, #0 + BL enableIntID + + ; Set the priority + MOV r0, #29 + MOV r1, #0 + BL setIntPriority + + ; Configure Timer + MOV r0, #0xF0000 + MOV r1, #0x0 + BL init_private_timer + BL start_private_timer + + ; + ; Enable receipt of SGI 0 + ; ------------------------ + MOV r0, #0x0 ; ID + BL enableIntID + + MOV r0, #0x0 ; ID + MOV r1, #0x0 ; Priority + BL setIntPriority + + ; + ; Branch to C lib code + ; ---------------------- + B __main + + + ENDP + +; ------------------------------------------------------------ +; Initialization for SECONDARY CPUs +; ------------------------------------------------------------ + + EXPORT secondaryCPUsInit +secondaryCPUsInit PROC + + ; + ; GIC Init + ; --------- + BL enableGICProcessorInterface + + MOV r0, #0x1F ; Priority + BL setPriorityMask + + MOV r0, #0x0 ; ID + BL enableIntID + + MOV r0, #0x0 ; ID + MOV r1, #0x0 ; Priority + BL setIntPriority + + ; + ; Join SMP + ; --------- + MRC p15, 0, r0, c0, c0, 5 ; Read CPU ID register + ANDS r0, r0, #0x03 ; Mask off, leaving the CPU ID field + MOV r1, #0xF ; Move 0xF (represents all four ways) into r1 + BL secureSCUInvalidate + + BL joinSMP + BL enableMaintenanceBroadcast + +; [EL Change Start] + ; + ; Holding Pen + ; ------------ +; MOV r2, #0x00 ; Clear r2 +; CPSIE i ; Enable interrupts +holding_pen +; CMP r2, #0x0 ; r2 will be set to 0x1 by IRQ handler on receiving SGI +; WFIEQ +; BEQ holding_pen +; CPSID i ; IRQs not used in reset of example, so mask out interrupts +skip +; + ; + ; Branch to C lib code + ; ---------------------- +; B __main + + B _tx_thread_smp_initialize_wait +; [EL Change End] + + ; + ; The translation tables are generated by the primary CPU + ; The MMU cannot be enabled on the secondary CPUs until + ; they are released from the holding-pen + ; + + ; Enable MMU + ; ----------- + ; Leave the caches disabled until after scatter loading. + MRC p15, 0, r0, c1, c0, 0 ; Read System Control Register + ORR r0, r0, #0x1 ; Set M bit 0 to enable MMU before scatter loading + MCR p15, 0, r0, c1, c0, 0 ; Write System Control Register + ISB + + + ; + ; Branch to application + ; ---------------------- +; B main_app + + + ENDP + +; ------------------------------------------------------------ +; Enable caches +; This code must be run from a privileged mode +; ------------------------------------------------------------ + + AREA ENABLECACHES, CODE, READONLY + + EXPORT enable_caches + +enable_caches FUNCTION + +; ------------------------------------------------------------ +; Enable caches +; ------------------------------------------------------------ + + MRC p15, 0, r0, c1, c0, 0 ; Read System Control Register + ORR r0, r0, #(0x1 << 12) ; Set I bit 12 to enable I Cache + ORR r0, r0, #(0x1 << 2) ; Set C bit 2 to enable D Cache + MCR p15, 0, r0, c1, c0, 0 ; Write System Control Register + ISB + + BX lr + + ENDFUNC + + + END + +; ------------------------------------------------------------ +; End of startup.s +; ------------------------------------------------------------ diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/tx_initialize_low_level.s b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/tx_initialize_low_level.s new file mode 100644 index 00000000..36059fcc --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/tx_initialize_low_level.s @@ -0,0 +1,119 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_initialize.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +; +; + IMPORT _tx_thread_system_stack_ptr + IMPORT _tx_initialize_unused_memory + IMPORT _tx_version_id + IMPORT _tx_build_options + IMPORT ||Image$$SHARED_DATA$$ZI$$Limit|| +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level SMP/Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + EXPORT _tx_initialize_low_level +_tx_initialize_low_level +; +; /* Save the first available memory address. */ +; _tx_initialize_unused_memory = (VOID_PTR) (||Image$$SHARED_DATA$$ZI$$Limit||); +; + LDR r0, =||Image$$SHARED_DATA$$ZI$$Limit|| ; Get end of non-initialized RAM area + LDR r2, =_tx_initialize_unused_memory ; Pickup unused memory ptr address + STR r0, [r2, #0] ; Save first free memory address +; +; + +; /* Done, return to caller. */ +; + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +;} +; +; /* Reference build options and version ID to ensure they come in. */ +; + LDR r2, =_tx_build_options ; Pickup build options variable address + LDR r0, [r2, #0] ; Pickup build options content + LDR r2, =_tx_version_id ; Pickup version ID variable address + LDR r0, [r2, #0] ; Pickup version ID content +; +; + + END + diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/v7.h b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/v7.h new file mode 100644 index 00000000..5a08b43f --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/v7.h @@ -0,0 +1,155 @@ +// ------------------------------------------------------------ +// v7-A Cache, TLB and Branch Prediction Maintenance Operations +// Header File +// +// Copyright (c) 2011-2016 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#ifndef _ARMV7A_GENERIC_H +#define _ARMV7A_GENERIC_H + +// ------------------------------------------------------------ +// Memory barrier mnemonics +enum MemBarOpt { + RESERVED_0 = 0, RESERVED_1 = 1, OSHST = 2, OSH = 3, + RESERVED_4 = 4, RESERVED_5 = 5, NSHST = 6, NSH = 7, + RESERVED_8 = 8, RESERVED_9 = 9, ISHST = 10, ISH = 11, + RESERVED_12 = 12, RESERVED_13 = 13, ST = 14, SY = 15 +}; + +// +// Note: +// *_IS() stands for "inner shareable" +// DO NOT USE THESE FUNCTIONS ON A CORTEX-A8 +// + +// ------------------------------------------------------------ +// Interrupts +// Enable/disables IRQs (not FIQs) +void enableInterrupts(void); +void disableInterrupts(void); + +// ------------------------------------------------------------ +// Caches + +void invalidateCaches_IS(void); +void cleanInvalidateDCache(void); +void invalidateCaches_IS(void); +void enableCaches(void); +void disableCaches(void); +void invalidateCaches(void); +void cleanDCache(void); + +// ------------------------------------------------------------ +// TLBs + +void invalidateUnifiedTLB(void); +void invalidateUnifiedTLB_IS(void); + +// ------------------------------------------------------------ +// Branch prediction + +void flushBranchTargetCache(void); +void flushBranchTargetCache_IS(void); + +// ------------------------------------------------------------ +// High Vecs + +void enableHighVecs(void); +void disableHighVecs(void); + +// ------------------------------------------------------------ +// ID Registers + +unsigned int getMIDR(void); + +#define MIDR_IMPL_SHIFT 24 +#define MIDR_IMPL_MASK 0xFF +#define MIDR_VAR_SHIFT 20 +#define MIDR_VAR_MASK 0xF +#define MIDR_ARCH_SHIFT 16 +#define MIDR_ARCH_MASK 0xF +#define MIDR_PART_SHIFT 4 +#define MIDR_PART_MASK 0xFFF +#define MIDR_REV_SHIFT 0 +#define MIDR_REV_MASK 0xF + +// tmp = get_MIDR(); +// implementor = (tmp >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; +// variant = (tmp >> MIDR_VAR_SHIFT) & MIDR_VAR_MASK; +// architecture= (tmp >> MIDR_ARCH_SHIFT) & MIDR_ARCH_MASK; +// part_number = (tmp >> MIDR_PART_SHIFT) & MIDR_PART_MASK; +// revision = tmp & MIDR_REV_MASK; + +#define MIDR_PART_CA5 0xC05 +#define MIDR_PART_CA8 0xC08 +#define MIDR_PART_CA9 0xC09 + +unsigned int getMPIDR(void); + +#define MPIDR_FORMAT_SHIFT 31 +#define MPIDR_FORMAT_MASK 0x1 +#define MPIDR_UBIT_SHIFT 30 +#define MPIDR_UBIT_MASK 0x1 +#define MPIDR_CLUSTER_SHIFT 7 +#define MPIDR_CLUSTER_MASK 0xF +#define MPIDR_CPUID_SHIFT 0 +#define MPIDR_CPUID_MASK 0x3 + +#define MPIDR_CPUID_CPU0 0x0 +#define MPIDR_CPUID_CPU1 0x1 +#define MPIDR_CPUID_CPU2 0x2 +#define MPIDR_CPUID_CPU3 0x3 + +#define MPIDR_UNIPROCESSPR 0x1 + +#define MPDIR_NEW_FORMAT 0x1 + +// ------------------------------------------------------------ +// Context ID + +unsigned int getContextID(void); + +void setContextID(unsigned int); + +#define CONTEXTID_ASID_SHIFT 0 +#define CONTEXTID_ASID_MASK 0xFF +#define CONTEXTID_PROCID_SHIFT 8 +#define CONTEXTID_PROCID_MASK 0x00FFFFFF + +// tmp = getContextID(); +// ASID = tmp & CONTEXTID_ASID_MASK; +// PROCID = (tmp >> CONTEXTID_PROCID_SHIFT) & CONTEXTID_PROCID_MASK; + +// ------------------------------------------------------------ +// SMP related for Armv7-A MPCore processors +// +// DO NOT CALL THESE FUNCTIONS ON A CORTEX-A8 + +// Returns the base address of the private peripheral memory space +unsigned int getBaseAddr(void); + +// Returns the CPU ID (0 to 3) of the CPU executed on +#define MP_CPU0 (0) +#define MP_CPU1 (1) +#define MP_CPU2 (2) +#define MP_CPU3 (3) +unsigned int getCPUID(void); + +// Set this core as participating in SMP +void joinSMP(void); + +// Set this core as NOT participating in SMP +void leaveSMP(void); + +// Go to sleep, never returns +void goToSleep(void); + +#endif + +// ------------------------------------------------------------ +// End of v7.h +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/v7.s b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/v7.s new file mode 100644 index 00000000..35a94ff8 --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/v7.s @@ -0,0 +1,458 @@ +; ------------------------------------------------------------ +; v7-A Cache and Branch Prediction Maintenance Operations +; +; Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. +; Use, modification and redistribution of this file is subject to your possession of a +; valid End User License Agreement for the Arm Product of which these examples are part of +; and your compliance with all applicable terms and conditions of such licence agreement. +; ------------------------------------------------------------ + + + + AREA v7Opps,CODE,READONLY + +; ------------------------------------------------------------ +; Interrupt enable/disable +; ------------------------------------------------------------ + + ; Could use intrinsic instead of these + + EXPORT enableInterrupts + ; void enableInterrupts(void); +enableInterrupts PROC + CPSIE i + BX lr + ENDP + + EXPORT disableInterrupts + ; void disableInterrupts(void); +disableInterrupts PROC + CPSID i + BX lr + ENDP + +; ------------------------------------------------------------ +; Cache Maintenance +; ------------------------------------------------------------ + + EXPORT enableCaches + ; void enableCaches(void); +enableCaches PROC + MRC p15, 0, r0, c1, c0, 0 ; Read System Control Register + ORR r0, r0, #(1 << 2) ; Set C bit + ORR r0, r0, #(1 << 12) ; Set I bit + MCR p15, 0, r0, c1, c0, 0 ; Write System Control Register + ISB + BX lr + ENDP + + + EXPORT disableCaches + ; void disableCaches(void) +disableCaches PROC + MRC p15, 0, r0, c1, c0, 0 ; Read System Control Register + BIC r0, r0, #(1 << 2) ; Clear C bit + BIC r0, r0, #(1 << 12) ; Clear I bit + MCR p15, 0, r0, c1, c0, 0 ; Write System Control Register + ISB + BX lr + ENDP + + + EXPORT cleanDCache + ; void cleanDCache(void); +cleanDCache PROC + PUSH {r4-r12} + + ; + ; Based on code example given in section 11.2.4 of Armv7-A/R Architecture Reference Manual (DDI 0406B) + ; + + MRC p15, 1, r0, c0, c0, 1 ; Read CLIDR + ANDS r3, r0, #0x7000000 + MOV r3, r3, LSR #23 ; Cache level value (naturally aligned) + BEQ clean_dcache_finished + MOV r10, #0 + +clean_dcache_loop1 + ADD r2, r10, r10, LSR #1 ; Work out 3xcachelevel + MOV r1, r0, LSR r2 ; bottom 3 bits are the Cache type for this level + AND r1, r1, #7 ; get those 3 bits alone + CMP r1, #2 + BLT clean_dcache_skip ; no cache or only instruction cache at this level + MCR p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register + ISB ; ISB to sync the change to the CacheSizeID reg + MRC p15, 1, r1, c0, c0, 0 ; reads current Cache Size ID register + AND r2, r1, #7 ; extract the line length field + ADD r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes) + LDR r4, =0x3FF + ANDS r4, r4, r1, LSR #3 ; R4 is the max number on the way size (right aligned) + CLZ r5, r4 ; R5 is the bit position of the way size increment + LDR r7, =0x00007FFF + ANDS r7, r7, r1, LSR #13 ; R7 is the max number of the index size (right aligned) + +clean_dcache_loop2 + MOV r9, R4 ; R9 working copy of the max way size (right aligned) + +clean_dcache_loop3 + ORR r11, r10, r9, LSL r5 ; factor in the way number and cache number into R11 + ORR r11, r11, r7, LSL r2 ; factor in the index number + MCR p15, 0, r11, c7, c10, 2 ; DCCSW - clean by set/way + SUBS r9, r9, #1 ; decrement the way number + BGE clean_dcache_loop3 + SUBS r7, r7, #1 ; decrement the index + BGE clean_dcache_loop2 + +clean_dcache_skip + ADD r10, r10, #2 ; increment the cache number + CMP r3, r10 + BGT clean_dcache_loop1 + +clean_dcache_finished + POP {r4-r12} + + BX lr + ENDP + + EXPORT cleanInvalidateDCache + ; void cleanInvalidateDCache(void); +cleanInvalidateDCache PROC + PUSH {r4-r12} + + ; + ; Based on code example given in section 11.2.4 of Armv7-A/R Architecture Reference Manual (DDI 0406B) + ; + + MRC p15, 1, r0, c0, c0, 1 ; Read CLIDR + ANDS r3, r0, #0x7000000 + MOV r3, r3, LSR #23 ; Cache level value (naturally aligned) + BEQ clean_invalidate_dcache_finished + MOV r10, #0 + +clean_invalidate_dcache_loop1 + ADD r2, r10, r10, LSR #1 ; Work out 3xcachelevel + MOV r1, r0, LSR r2 ; bottom 3 bits are the Cache type for this level + AND r1, r1, #7 ; get those 3 bits alone + CMP r1, #2 + BLT clean_invalidate_dcache_skip ; no cache or only instruction cache at this level + MCR p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register + ISB ; ISB to sync the change to the CacheSizeID reg + MRC p15, 1, r1, c0, c0, 0 ; reads current Cache Size ID register + AND r2, r1, #7 ; extract the line length field + ADD r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes) + LDR r4, =0x3FF + ANDS r4, r4, r1, LSR #3 ; R4 is the max number on the way size (right aligned) + CLZ r5, r4 ; R5 is the bit position of the way size increment + LDR r7, =0x00007FFF + ANDS r7, r7, r1, LSR #13 ; R7 is the max number of the index size (right aligned) + +clean_invalidate_dcache_loop2 + MOV r9, R4 ; R9 working copy of the max way size (right aligned) + +clean_invalidate_dcache_loop3 + ORR r11, r10, r9, LSL r5 ; factor in the way number and cache number into R11 + ORR r11, r11, r7, LSL r2 ; factor in the index number + MCR p15, 0, r11, c7, c14, 2 ; DCCISW - clean and invalidate by set/way + SUBS r9, r9, #1 ; decrement the way number + BGE clean_invalidate_dcache_loop3 + SUBS r7, r7, #1 ; decrement the index + BGE clean_invalidate_dcache_loop2 + +clean_invalidate_dcache_skip + ADD r10, r10, #2 ; increment the cache number + CMP r3, r10 + BGT clean_invalidate_dcache_loop1 + +clean_invalidate_dcache_finished + POP {r4-r12} + + BX lr + ENDP + + + EXPORT invalidateCaches + ; void invalidateCaches(void); +invalidateCaches PROC + PUSH {r4-r12} + + ; + ; Based on code example given in section B2.2.4/11.2.4 of Armv7-A/R Architecture Reference Manual (DDI 0406B) + ; + + MOV r0, #0 + MCR p15, 0, r0, c7, c5, 0 ; ICIALLU - Invalidate entire I Cache, and flushes branch target cache + + MRC p15, 1, r0, c0, c0, 1 ; Read CLIDR + ANDS r3, r0, #0x7000000 + MOV r3, r3, LSR #23 ; Cache level value (naturally aligned) + BEQ invalidate_caches_finished + MOV r10, #0 + +invalidate_caches_loop1 + ADD r2, r10, r10, LSR #1 ; Work out 3xcachelevel + MOV r1, r0, LSR r2 ; bottom 3 bits are the Cache type for this level + AND r1, r1, #7 ; get those 3 bits alone + CMP r1, #2 + BLT invalidate_caches_skip ; no cache or only instruction cache at this level + MCR p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register + ISB ; ISB to sync the change to the CacheSizeID reg + MRC p15, 1, r1, c0, c0, 0 ; reads current Cache Size ID register + AND r2, r1, #7 ; extract the line length field + ADD r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes) + LDR r4, =0x3FF + ANDS r4, r4, r1, LSR #3 ; R4 is the max number on the way size (right aligned) + CLZ r5, r4 ; R5 is the bit position of the way size increment + LDR r7, =0x00007FFF + ANDS r7, r7, r1, LSR #13 ; R7 is the max number of the index size (right aligned) + +invalidate_caches_loop2 + MOV r9, R4 ; R9 working copy of the max way size (right aligned) + +invalidate_caches_loop3 + ORR r11, r10, r9, LSL r5 ; factor in the way number and cache number into R11 + ORR r11, r11, r7, LSL r2 ; factor in the index number + MCR p15, 0, r11, c7, c6, 2 ; DCISW - invalidate by set/way + SUBS r9, r9, #1 ; decrement the way number + BGE invalidate_caches_loop3 + SUBS r7, r7, #1 ; decrement the index + BGE invalidate_caches_loop2 + +invalidate_caches_skip + ADD r10, r10, #2 ; increment the cache number + CMP r3, r10 + BGT invalidate_caches_loop1 + +invalidate_caches_finished + POP {r4-r12} + BX lr + ENDP + + + EXPORT invalidateCaches_IS + ; void invalidateCaches_IS(void); +invalidateCaches_IS PROC + PUSH {r4-r12} + + MOV r0, #0 + MCR p15, 0, r0, c7, c1, 0 ; ICIALLUIS - Invalidate entire I Cache inner shareable + + MRC p15, 1, r0, c0, c0, 1 ; Read CLIDR + ANDS r3, r0, #0x7000000 + MOV r3, r3, LSR #23 ; Cache level value (naturally aligned) + BEQ invalidate_caches_is_finished + MOV r10, #0 + +invalidate_caches_is_loop1 + ADD r2, r10, r10, LSR #1 ; Work out 3xcachelevel + MOV r1, r0, LSR r2 ; bottom 3 bits are the Cache type for this level + AND r1, r1, #7 ; get those 3 bits alone + CMP r1, #2 + BLT invalidate_caches_is_skip ; no cache or only instruction cache at this level + MCR p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register + ISB ; ISB to sync the change to the CacheSizeID reg + MRC p15, 1, r1, c0, c0, 0 ; reads current Cache Size ID register + AND r2, r1, #7 ; extract the line length field + ADD r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes) + LDR r4, =0x3FF + ANDS r4, r4, r1, LSR #3 ; R4 is the max number on the way size (right aligned) + CLZ r5, r4 ; R5 is the bit position of the way size increment + LDR r7, =0x00007FFF + ANDS r7, r7, r1, LSR #13 ; R7 is the max number of the index size (right aligned) + +invalidate_caches_is_loop2 + MOV r9, R4 ; R9 working copy of the max way size (right aligned) + +invalidate_caches_is_loop3 + ORR r11, r10, r9, LSL r5 ; factor in the way number and cache number into R11 + ORR r11, r11, r7, LSL r2 ; factor in the index number + MCR p15, 0, r11, c7, c6, 2 ; DCISW - clean by set/way + SUBS r9, r9, #1 ; decrement the way number + BGE invalidate_caches_is_loop3 + SUBS r7, r7, #1 ; decrement the index + BGE invalidate_caches_is_loop2 + +invalidate_caches_is_skip + ADD r10, r10, #2 ; increment the cache number + CMP r3, r10 + BGT invalidate_caches_is_loop1 + +invalidate_caches_is_finished + POP {r4-r12} + BX lr + ENDP + +; ------------------------------------------------------------ +; TLB +; ------------------------------------------------------------ + + EXPORT invalidateUnifiedTLB + ; void invalidateUnifiedTLB(void); +invalidateUnifiedTLB PROC + MOV r0, #0 + MCR p15, 0, r0, c8, c7, 0 ; TLBIALL - Invalidate entire unified TLB + BX lr + ENDP + + EXPORT invalidateUnifiedTLB_IS + ; void invalidateUnifiedTLB_IS(void); +invalidateUnifiedTLB_IS PROC + MOV r0, #1 + MCR p15, 0, r0, c8, c3, 0 ; TLBIALLIS - Invalidate entire unified TLB Inner Shareable + BX lr + ENDP + +; ------------------------------------------------------------ +; Branch Prediction +; ------------------------------------------------------------ + + EXPORT flushBranchTargetCache + ; void flushBranchTargetCache(void) +flushBranchTargetCache PROC + MOV r0, #0 + MCR p15, 0, r0, c7, c5, 6 ; BPIALL - Invalidate entire branch predictor array + BX lr + ENDP + + EXPORT flushBranchTargetCache_IS + ; void flushBranchTargetCache_IS(void) +flushBranchTargetCache_IS PROC + MOV r0, #0 + MCR p15, 0, r0, c7, c1, 6 ; BPIALLIS - Invalidate entire branch predictor array Inner Shareable + BX lr + ENDP + +; ------------------------------------------------------------ +; High Vecs +; ------------------------------------------------------------ + + EXPORT enableHighVecs + ; void enableHighVecs(void); +enableHighVecs PROC + MRC p15, 0, r0, c1, c0, 0 ; Read Control Register + ORR r0, r0, #(1 << 13) ; Set the V bit (bit 13) + MCR p15, 0, r0, c1, c0, 0 ; Write Control Register + ISB + BX lr + ENDP + + EXPORT disableHighVecs + ; void disable_highvecs(void); +disableHighVecs PROC + MRC p15, 0, r0, c1, c0, 0 ; Read Control Register + BIC r0, r0, #(1 << 13) ; Clear the V bit (bit 13) + MCR p15, 0, r0, c1, c0, 0 ; Write Control Register + ISB + BX lr + ENDP + +; ------------------------------------------------------------ +; Context ID +; ------------------------------------------------------------ + + EXPORT getContextID + ; uint32_t getContextIDd(void); +getContextID PROC + MRC p15, 0, r0, c13, c0, 1 ; Read Context ID Register + BX lr + ENDP + + EXPORT setContextID + ; void setContextID(uint32_t); +setContextID PROC + MCR p15, 0, r0, c13, c0, 1 ; Write Context ID Register + BX lr + ENDP + +; ------------------------------------------------------------ +; ID registers +; ------------------------------------------------------------ + + EXPORT getMIDR + ; uint32_t getMIDR(void); +getMIDR PROC + MRC p15, 0, r0, c0, c0, 0 ; Read Main ID Register (MIDR) + BX lr + ENDP + + EXPORT getMPIDR + ; uint32_t getMPIDR(void); +getMPIDR PROC + MRC p15, 0, r0, c0 ,c0, 5; Read Multiprocessor ID register (MPIDR) + BX lr + ENDP + +; ------------------------------------------------------------ +; CP15 SMP related +; ------------------------------------------------------------ + + EXPORT getBaseAddr + ; uint32_t getBaseAddr(void) + ; Returns the value CBAR (base address of the private peripheral memory space) +getBaseAddr PROC + MRC p15, 4, r0, c15, c0, 0 ; Read peripheral base address + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT getCPUID + ; uint32_t getCPUID(void) + ; Returns the CPU ID (0 to 3) of the CPU executed on +getCPUID PROC + MRC p15, 0, r0, c0, c0, 5 ; Read CPU ID register + AND r0, r0, #0x03 ; Mask off, leaving the CPU ID field + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT goToSleep + ; void goToSleep(void) +goToSleep PROC + DSB ; Clear all pending data accesses + WFI ; Go into standby + B goToSleep ; Catch in case of rogue events + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT joinSMP + ; void joinSMP(void) + ; Sets the ACTRL.SMP bit +joinSMP PROC + + ; SMP status is controlled by bit 6 of the CP15 Aux Ctrl Reg + + MRC p15, 0, r0, c1, c0, 1 ; Read ACTLR + MOV r1, r0 + ORR r0, r0, #0x040 ; Set bit 6 + CMP r0, r1 + MCRNE p15, 0, r0, c1, c0, 1 ; Write ACTLR + ISB + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT leaveSMP + ; void leaveSMP(void) + ; Clear the ACTRL.SMP bit +leaveSMP PROC + + ; SMP status is controlled by bit 6 of the CP15 Aux Ctrl Reg + + MRC p15, 0, r0, c1, c0, 1 ; Read ACTLR + BIC r0, r0, #0x040 ; Clear bit 6 + MCR p15, 0, r0, c1, c0, 1 ; Write ACTLR + ISB + + BX lr + ENDP + + END + +; ------------------------------------------------------------ +; End of v7.s +; ------------------------------------------------------------ diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/tx/.cproject b/ports_smp/cortex_a5_smp/ac5/example_build/tx/.cproject new file mode 100644 index 00000000..eff9f4dd --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/example_build/tx/.cproject @@ -0,0 +1,202 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/tx/.project b/ports_smp/cortex_a5_smp/ac5/example_build/tx/.project new file mode 100644 index 00000000..10681969 --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/example_build/tx/.project @@ -0,0 +1,48 @@ + + + tx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + inc_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_smp/inc + + + inc_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/inc + + + src_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_smp/src + + + src_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/src + + + diff --git a/ports_smp/cortex_a5_smp/ac5/example_build/tx/.settings/language.settings.xml b/ports_smp/cortex_a5_smp/ac5/example_build/tx/.settings/language.settings.xml new file mode 100644 index 00000000..fc1f7590 --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/example_build/tx/.settings/language.settings.xml @@ -0,0 +1,506 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/cortex_a5_smp/ac5/inc/tx_port.h b/ports_smp/cortex_a5_smp/ac5/inc/tx_port.h new file mode 100644 index 00000000..bcc092a5 --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/inc/tx_port.h @@ -0,0 +1,406 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h SMP/Cortex-A5/AC5 */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/************* Define ThreadX SMP constants. *************/ + +/* Define the ThreadX SMP maximum number of cores. */ + +#ifndef TX_THREAD_SMP_MAX_CORES +#define TX_THREAD_SMP_MAX_CORES 2 +#endif + + +/* Define the ThreadX SMP core mask. */ + +#ifndef TX_THREAD_SMP_CORE_MASK +#define TX_THREAD_SMP_CORE_MASK 0x3 /* Where bit 0 represents Core 0, bit 1 represents Core 1, etc. */ +#endif + + +/* Define INLINE_DECLARE to whitespace for ARM compiler. */ + +#define INLINE_DECLARE + + +/* Define ThreadX SMP initialization macro. */ + +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION + + +/* Define ThreadX SMP pre-scheduler initialization. */ + +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION + + +/* Enable the inter-core interrupt logic. */ + +#define TX_THREAD_SMP_INTER_CORE_INTERRUPT + + +/* Determine if there is customer-specific wakeup logic needed. */ + +#ifdef TX_THREAD_SMP_WAKEUP_LOGIC + +/* Include customer-specific wakeup code. */ + +#include "tx_thread_smp_core_wakeup.h" +#else + +#ifdef TX_THREAD_SMP_DEFAULT_WAKEUP_LOGIC + +/* Default wakeup code. */ +#define TX_THREAD_SMP_WAKEUP_LOGIC +#define TX_THREAD_SMP_WAKEUP(i) _tx_thread_smp_core_preempt(i) +#endif +#endif + + +/* Ensure that the in-line resume/suspend define is not allowed. */ + +#ifdef TX_INLINE_THREAD_RESUME_SUSPEND +#undef TX_INLINE_THREAD_RESUME_SUSPEND +#endif + + +/************* End ThreadX SMP constants. *************/ + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE _tx_thread_smp_time_get() +#endif +#else +#ifndef TX_TRACE_TIME_SOURCE +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#ifndef __thumb + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + b = (ULONG) __clz((unsigned int) m); \ + b = 31 - b; +#endif +#endif + + +/************* Define ThreadX SMP data types and function prototypes. *************/ + +struct TX_THREAD_STRUCT; + + +/* Define the ThreadX SMP protection structure. */ + +typedef struct TX_THREAD_SMP_PROTECT_STRUCT +{ + ULONG tx_thread_smp_protect_in_force; + struct TX_THREAD_STRUCT * + tx_thread_smp_protect_thread; + ULONG tx_thread_smp_protect_core; + ULONG tx_thread_smp_protect_count; + + /* Implementation specific information follows. */ + + ULONG tx_thread_smp_protect_get_caller; + ULONG tx_thread_smp_protect_sr; + ULONG tx_thread_smp_protect_release_caller; +} TX_THREAD_SMP_PROTECT; + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_smp_protect(); +#define TX_RESTORE _tx_thread_smp_unprotect(interrupt_save); + + +/************* End ThreadX SMP data type and function prototype definitions. *************/ + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define VFP extension for the Cortex-A5. Each is assumed to be called in the context of the executing + thread. */ + +void tx_thread_vfp_enable(void); +void tx_thread_vfp_disable(void); + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Cortex-A5/AC5 Version 6.0.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + + + diff --git a/ports_smp/cortex_a5_smp/ac5/readme_threadx.txt b/ports_smp/cortex_a5_smp/ac5/readme_threadx.txt new file mode 100644 index 00000000..49cd8d4a --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/readme_threadx.txt @@ -0,0 +1,361 @@ + Microsoft's Azure RTOS ThreadX SMP for Cortex-A5 + + Thumb & 32-bit Mode + + Using the ARM Compiler 5 & DS + +1. Import the ThreadX Projects + +In order to build the ThreadX SMP library and the ThreadX SMP demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +into your DS workspace. + + +2. Building the ThreadX SMP run-time Library + +Building the ThreadX SMP library is easy; simply select the Eclipse project file +"tx" and then select the build button. You should now observe the compilation +and assembly of the ThreadX SMP library. This project build produces the ThreadX SMP +library file tx.a. + + +3. Demonstration System + +The ThreadX SMP demonstration is designed to execute under the DS debugger on the +VE_Cortex-A5x4 Bare Metal simulator. + +Building the demonstration is easy; simply open the workspace file, select the +sample_threadx project, and select the build button. Next, expand the demo ThreadX +project folder in the Project Explorer window, right-click on the 'sample_threadx.launch' +file, click 'Debug As', and then click 'sample_threadx' from the submenu. This will cause the +debugger to load the sample_threadx.axf ELF file and run to main. You are now ready +to execute the ThreadX demonstration. + + +4. System Initialization + +The entry point in ThreadX for the Cortex-A5 using AC5 tools is at label +Reset_Handler in startup.s. After the basic core initialization is complete, +control will transfer to __main, which is where all static and global pre-set +C variable initialization processing takes place. + +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. By default, the vector area is defined to be located in the Init area, +which is defined at the top of tx_initialize_low_level.s. This area is typically +located at 0. In situations where this is impossible, the vectors at the beginning +of the Init area should be copied to address 0. + +This is also where initialization of a periodic timer interrupt source +should take place. + +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input +parameter to your application definition function, tx_application_define. + + +5. Register Usage and Stack Frames + +The AC5 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread +is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 CPSR CPSR + 0x08 r0 (a1) r4 (v1) + 0x0C r1 (a2) r5 (v2) + 0x10 r2 (a3) r6 (v3) + 0x14 r3 (a4) r7 (v4) + 0x18 r4 (v1) r8 (v5) + 0x1C r5 (v2) r9 (v6) + 0x20 r6 (v3) r10 (v7) + 0x24 r7 (v4) r11 (fp) + 0x28 r8 (v5) r14 (lr) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) + 0x3C r14 (lr) + 0x40 PC + + +6. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the build_threadx.bat file to +remove the -g option and enable all compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-A5 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +7.1 Vector Area + +The Cortex-A5 vectors start at address zero. The demonstration system startup +Init area contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. + + +7.2 IRQ ISRs + +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested +IRQ interrupts. The following sub-sections define the IRQ capabilities. + + +7.2.1 Standard IRQ ISRs + +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +is the default IRQ handler defined in tx_initialize_low_level.s: + + EXPORT __tx_irq_handler + EXPORT __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save ; Jump to the context save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Application ISR call(s) go here! */ +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.2 Vectored IRQ ISRs + +The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified +by the particular implementation. The following is an example IRQ handler defined in +tx_initialize_low_level.s: + + EXPORT __tx_irq_example_handler +__tx_irq_example_handler +; +; /* Call context save to save system context. */ + + STMDB sp!, {r0-r3} ; Save some scratch registers + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers + BL _tx_thread_vectored_context_save ; Call the vectored IRQ context save +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Application ISR call goes here! */ +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.3 Nested IRQ Support + +By default, nested IRQ interrupt support is not enabled. To enable nested +IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING +defined. With this defined, two new IRQ interrupt management services are +available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. +These function should be called between the IRQ context save and restore +calls. + +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +by switching from IRQ mode to SYS mode and enabling IRQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested IRQ interrupts are no longer required, +calling the _tx_thread_irq_nesting_end service disables nesting by disabling +IRQ interrupts and switching back to IRQ mode in preparation for the IRQ +context restore service. + +The following is an example of enabling IRQ nested interrupts in a standard +IRQ handler: + + EXPORT __tx_irq_handler + EXPORT __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* Enable nested IRQ interrupts. NOTE: Since this service returns +; with IRQ interrupts enabled, all IRQ interrupt sources must be +; cleared prior to calling this service. */ + BL _tx_thread_irq_nesting_start +; +; /* Application ISR call(s) go here! */ +; +; /* Disable nested IRQ interrupts. The mode is switched back to +; IRQ mode and IRQ interrupts are disable upon return. */ + BL _tx_thread_irq_nesting_end +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.3 FIQ Interrupts + +By default, Cortex-A5 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made +from default FIQ ISRs, which is located in tx_initialize_low_level.s. + + +7.3.1 Managed FIQ Interrupts + +Full ThreadX management of FIQ interrupts is provided if the ThreadX sources +are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built +this way, the FIQ interrupt handlers are very similar to the IRQ interrupt +handlers defined previously. The following is default FIQ handler +defined in tx_initialize_low_level.s: + + + EXPORT __tx_fiq_handler + EXPORT __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Application FIQ handlers can be called here! */ +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +7.3.1.1 Nested FIQ Support + +By default, nested FIQ interrupt support is not enabled. To enable nested +FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING +defined. With this defined, two new FIQ interrupt management services are +available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. +These function should be called between the FIQ context save and restore +calls. + +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +by switching from FIQ mode to SYS mode and enabling FIQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested FIQ interrupts are no longer required, +calling the _tx_thread_fiq_nesting_end service disables nesting by disabling +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +context restore service. + +The following is an example of enabling FIQ nested interrupts in the +typical FIQ handler: + + + EXPORT __tx_fiq_handler + EXPORT __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Enable nested FIQ interrupts. NOTE: Since this service returns +; with FIQ interrupts enabled, all FIQ interrupt sources must be +; cleared prior to calling this service. */ + BL _tx_thread_fiq_nesting_start +; +; /* Application FIQ handlers can be called here! */ +; +; /* Disable nested FIQ interrupts. The mode is switched back to +; FIQ mode and FIQ interrupts are disable upon return. */ + BL _tx_thread_fiq_nesting_end +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +8. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional. However, all other +ThreadX services are operational without a periodic timer source. + +To add the timer interrupt processing, simply make a call to +_tx_timer_interrupt in the IRQ processing. An example of this can be +found in the file tx_initialize_low_level.s in the Integrator sub-directories. + + +9. Thumb/Cortex-A5 Mixed Mode + +By default, ThreadX is setup for running in Cortex-A5 32-bit mode. This is +also true for the demonstration system. It is possible to build any +ThreadX file and/or the application in Thumb mode. If any Thumb code +is used the entire ThreadX source- both C and assembly - should be built +with the "-apcs /interwork" option. + + +10. VFP Support + +By default, VFP support is disabled for each thread. If saving the context of the VFP registers +is needed, the following API call must be made from the context of the application thread - before +the VFP usage: + +void tx_thread_vfp_enable(void); + +After this API is called in the application, VFP registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the VFP registers +to be saved/restored. + +To disable VFP register context saving, simply call the following API: + +void tx_thread_vfp_disable(void); + + +11. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A5 using AC5 tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_context_restore.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_context_restore.s new file mode 100644 index 00000000..46a8080b --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_context_restore.s @@ -0,0 +1,371 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +;/* Include macros for modifying the wait list. */ +#include "tx_thread_smp_protection_wait_list_macros.h" + + IF :DEF:TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts +IRQ_MODE EQU 0xD2 ; IRQ mode +SVC_MODE EQU 0xD3 ; SVC mode + ELSE +DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts +IRQ_MODE EQU 0x92 ; IRQ mode +SVC_MODE EQU 0x93 ; SVC mode + ENDIF +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_execute_ptr + IMPORT _tx_timer_time_slice + IMPORT _tx_thread_schedule + IMPORT _tx_thread_preempt_disable + IMPORT _tx_timer_interrupt_active + IMPORT _tx_thread_smp_protection + IMPORT _tx_thread_smp_protect_wait_counts + IMPORT _tx_thread_smp_protect_wait_list + IMPORT _tx_thread_smp_protect_wait_list_lock_protect_in_force + IMPORT _tx_thread_smp_protect_wait_list_tail + IMPORT _tx_thread_smp_protect_wait_list_size + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_exit + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore SMP/Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + EXPORT _tx_thread_context_restore +_tx_thread_context_restore +; +; /* Lockout interrupts. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + BL _tx_execution_isr_exit ; Call the ISR exit function + ENDIF + +; /* Pickup the CPU ID. */ +; + MRC p15, 0, r10, c0, c0, 5 ; Read CPU ID register + AND r10, r10, #0x03 ; Mask off, leaving the CPU ID field + LSL r12, r10, #2 ; Build offset to array indexes +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state[core]) +; { +; + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + ADD r3, r3, r12 ; Build array offset + LDR r2, [r3, #0] ; Pickup system state + SUB r2, r2, #1 ; Decrement the counter + STR r2, [r3, #0] ; Store the counter + CMP r2, #0 ; Was this the first interrupt? + BEQ __tx_thread_not_nested_restore ; If so, not a nested restore +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +__tx_thread_not_nested_restore +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr[core]) && (_tx_thread_current_ptr[core] == _tx_thread_execute_ptr[core]) +; || (_tx_thread_preempt_disable)) +; { +; + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + ADD r1, r1, r12 ; Build index to this core's current thread ptr + LDR r0, [r1, #0] ; Pickup actual current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_restore ; Yes, idle system was interrupted +; + LDR r3, =_tx_thread_smp_protection ; Get address of protection structure + LDR r2, [r3, #8] ; Pickup owning core + CMP r2, r10 ; Is the owning core the same as the protected core? + BNE __tx_thread_skip_preempt_check ; No, skip the preempt disable check since this is only valid for the owning core + + LDR r3, =_tx_thread_preempt_disable ; Pickup preempt disable address + LDR r2, [r3, #0] ; Pickup actual preempt disable flag + CMP r2, #0 ; Is it set? + BNE __tx_thread_no_preempt_restore ; Yes, don't preempt this thread +__tx_thread_skip_preempt_check + + LDR r3, =_tx_thread_execute_ptr ; Pickup address of execute thread ptr + ADD r3, r3, r12 ; Build index to this core's execute thread ptr + LDR r2, [r3, #0] ; Pickup actual execute thread pointer + CMP r0, r2 ; Is the same thread highest priority? + BNE __tx_thread_preempt_restore ; No, preemption needs to happen +; +; +__tx_thread_no_preempt_restore +; +; /* Restore interrupted thread or ISR. */ +; +; /* Pickup the saved stack pointer. */ +; tmp_ptr = _tx_thread_current_ptr[core] -> tx_thread_stack_ptr; +; +; /* Recover the saved context and return to the point of interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +; else +; { +; +__tx_thread_preempt_restore +; +; /* Was the thread being preempted waiting for the lock? */ +; if (_tx_thread_smp_protect_wait_counts[this_core] != 0) +; { +; + LDR r1, =_tx_thread_smp_protect_wait_counts ; Load waiting count list + LDR r2, [r1, r10, LSL #2] ; Load waiting value for this core + CMP r2, #0 + BEQ _nobody_waiting_for_lock ; Is the core waiting for the lock? +; +; /* Do we not have the lock? This means the ISR never got the inter-core lock. */ +; if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core) +; { +; + LDR r1, =_tx_thread_smp_protection ; Load address of protection structure + LDR r2, [r1, #8] ; Pickup the owning core + CMP r10, r2 ; Compare our core to the owning core + BEQ _this_core_has_lock ; Do we have the lock? +; +; /* We don't have the lock. This core should be in the list. Remove it. */ +; _tx_thread_smp_protect_wait_list_remove(this_core); +; + MOV r0, r10 ; Move the core ID to r0 for the macro +macro_call0 _tx_thread_smp_protect_wait_list_remove ; Call macro to remove core from the list + B _nobody_waiting_for_lock ; Leave +; +; } +; else +; { +; /* We have the lock. This means the ISR got the inter-core lock, but +; never released it because it saw that there was someone waiting. +; Note this core is not in the list. */ +; +_this_core_has_lock +; +; /* We're no longer waiting. Note that this should be zero since this happens during thread preemption. */ +; _tx_thread_smp_protect_wait_counts[core]--; +; + LDR r1, =_tx_thread_smp_protect_wait_counts ; Load waiting count list + LDR r2, [r1, r10, LSL #2] ; Load waiting value for this core + SUB r2, r2, #1 ; Decrement waiting value. Should be zero now + STR r2, [r1, r10, LSL #2] ; Store new waiting value +; +; /* Now release the inter-core lock. */ +; +; /* Set protected core as invalid. */ +; _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF; +; + LDR r1, =_tx_thread_smp_protection ; Load address of protection structure + MOV r2, #0xFFFFFFFF ; Build invalid value + STR r2, [r1, #8] ; Mark the protected core as invalid + DMB ; Ensure that accesses to shared resource have completed +; +; /* Release protection. */ +; _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0; +; + MOV r2, #0 ; Build release protection value + STR r2, [r1, #0] ; Release the protection + DSB ISH ; To ensure update of the protection occurs before other CPUs awake +; +; /* Wake up waiting processors. Note interrupts are already enabled. */ +; + IF :DEF:TX_ENABLE_WFE + SEV ; Send event to other CPUs + ENDIF +; +; } +; } +; + +_nobody_waiting_for_lock + + LDMIA sp!, {r3, r10, r12, lr} ; Recover temporarily saved registers + MOV r1, lr ; Save lr (point of interrupt) + MOV r2, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r2 ; Enter SVC mode + STR r1, [sp, #-4]! ; Save point of interrupt + STMDB sp!, {r4-r12, lr} ; Save upper half of registers + MOV r4, r3 ; Save SPSR in r4 + MOV r2, #IRQ_MODE ; Build IRQ mode CPSR + MSR CPSR_c, r2 ; Enter IRQ mode + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOV r5, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r5 ; Enter SVC mode + STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack + + MRC p15, 0, r10, c0, c0, 5 ; Read CPU ID register + AND r10, r10, #0x03 ; Mask off, leaving the CPU ID field + LSL r12, r10, #2 ; Build offset to array indexes + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + ADD r1, r1, r12 ; Build index to current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + + IF {TARGET_FPU_VFP} = {TRUE} + LDR r2, [r0, #160] ; Pickup the VFP enabled flag + CMP r2, #0 ; Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save ; No, skip VFP IRQ save + VMRS r2, FPSCR ; Pickup the FPSCR + STR r2, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D0-D15} ; Save D0-D15 +_tx_skip_irq_vfp_save + ENDIF + + MOV r3, #1 ; Build interrupt stack type + STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR + STR sp, [r0, #8] ; Save stack pointer in thread control + ; block +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice[core]) +; { +; + LDR r3, =_tx_timer_interrupt_active ; Pickup timer interrupt active flag's address +_tx_wait_for_timer_to_finish + LDR r2, [r3, #0] ; Pickup timer interrupt active flag + CMP r2, #0 ; Is the timer interrupt active? + BNE _tx_wait_for_timer_to_finish ; If timer interrupt is active, wait until it completes + + LDR r3, =_tx_timer_time_slice ; Pickup time-slice variable address + ADD r3, r3, r12 ; Build index to core's time slice + LDR r2, [r3, #0] ; Pickup time-slice + CMP r2, #0 ; Is it active? + BEQ __tx_thread_dont_save_ts ; No, don't save it +; +; _tx_thread_current_ptr[core] -> tx_thread_time_slice = _tx_timer_time_slice[core]; +; _tx_timer_time_slice[core] = 0; +; + STR r2, [r0, #24] ; Save thread's time-slice + MOV r2, #0 ; Clear value + STR r2, [r3, #0] ; Disable global time-slice flag +; +; } +__tx_thread_dont_save_ts +; +; +; /* Clear the current task pointer. */ +; _tx_thread_current_ptr[core] = TX_NULL; +; + MOV r2, #0 ; NULL value + STR r2, [r1, #0] ; Clear current thread pointer +; +; /* Set bit indicating this thread is ready for execution. */ +; + LDR r2, [r0, #152] ; Pickup the ready bit + ORR r2, r2, #0x8000 ; Set ready bit (bit 15) + STR r2, [r0, #152] ; Make this thread ready for executing again + DMB ; Ensure that accesses to shared resource have completed +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; + B _tx_thread_schedule ; Return to scheduler +; } +; +__tx_thread_idle_system_restore +; +; /* Just return back to the scheduler! */ +; + MOV r3, #SVC_MODE ; Build SVC mode with interrupts disabled + MSR CPSR_c, r3 ; Change to SVC mode + B _tx_thread_schedule ; Return to scheduler +;} +; + END + diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_context_save.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_context_save.s new file mode 100644 index 00000000..384ea930 --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_context_save.s @@ -0,0 +1,203 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IMPORT __tx_irq_processing_return + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save SMP/Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + EXPORT _tx_thread_context_save +_tx_thread_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state[core]++) +; { +; + STMDB sp!, {r0-r3} ; Save some working registers +; +; /* Save the rest of the scratch registers on the stack and return to the +; calling ISR. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable FIQ interrupts + ENDIF +; +; /* Pickup the CPU ID. */ +; + MRC p15, 0, r10, c0, c0, 5 ; Read CPU ID register + AND r10, r10, #0x03 ; Mask off, leaving the CPU ID field + LSL r12, r10, #2 ; Build offset to array indexes +; + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + ADD r3, r3, r12 ; Build index into the system state array + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {r12, lr} ; Save ISR lr & r12 + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {r12, lr} ; Recover ISR lr & r12 + ENDIF + + B __tx_irq_processing_return ; Continue IRQ processing +; +__tx_thread_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr[core]) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + ADD r1, r1, r12 ; Build index into current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + ; scheduling loop - nothing needs saving! +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {r12, lr} ; Save ISR lr & r12 + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {r12, lr} ; Recover ISR lr & r12 + ENDIF + + B __tx_irq_processing_return ; Continue IRQ processing +; +; } +; else +; { +; +__tx_thread_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; processing. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {r12, lr} ; Save ISR lr & r12 + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {r12, lr} ; Recover ISR lr & r12 + ENDIF + + ADD sp, sp, #32 ; Recover saved registers + B __tx_irq_processing_return ; Continue IRQ processing +; +; } +;} +; + END + diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_interrupt_control.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..44060077 --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_interrupt_control.s @@ -0,0 +1,102 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT +INT_MASK EQU 0xC0 ; Interrupt bit mask + ELSE +INT_MASK EQU 0x80 ; Interrupt bit mask + ENDIF +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control SMP/Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + EXPORT _tx_thread_interrupt_control +_tx_thread_interrupt_control +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r3, CPSR ; Pickup current CPSR + BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits + ORR r1, r1, r0 ; Or-in new interrupt lockout bits +; +; /* Apply the new interrupt posture. */ +; + MSR CPSR_c, r1 ; Setup new CPSR + AND r0, r3, #INT_MASK ; Return previous interrupt mask + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +;} +; + END + diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_interrupt_disable.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_interrupt_disable.s new file mode 100644 index 00000000..58fa2e03 --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_interrupt_disable.s @@ -0,0 +1,95 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable SMP/Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(void) +;{ + EXPORT _tx_thread_interrupt_disable +_tx_thread_interrupt_disable +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r0, CPSR ; Pickup current CPSR +; +; /* Mask interrupts. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ + ELSE + CPSID i ; Disable IRQ + ENDIF + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +;} +; + END + diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_interrupt_restore.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_interrupt_restore.s new file mode 100644 index 00000000..b6a46df8 --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_interrupt_restore.s @@ -0,0 +1,87 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore SMP/Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for restoring interrupts to the state */ +;/* returned by a previous _tx_thread_interrupt_disable call. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_restore(UINT old_posture) +;{ + EXPORT _tx_thread_interrupt_restore +_tx_thread_interrupt_restore +; +; /* Apply the new interrupt posture. */ +; + MSR CPSR_c, r0 ; Setup new CPSR + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +;} +; + END + diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_irq_nesting_end.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_irq_nesting_end.s new file mode 100644 index 00000000..973cab86 --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_irq_nesting_end.s @@ -0,0 +1,110 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts + ELSE +DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts + ENDIF +MODE_MASK EQU 0x1F ; Mode mask +IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end SMP/Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_irq_nesting_end(VOID) +;{ + EXPORT _tx_thread_irq_nesting_end +_tx_thread_irq_nesting_end + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value + MSR CPSR_c, r0 ; Disable interrupts + LDMIA sp!, {lr, r1} ; Pickup saved lr (and r1 throw-away for + ; 8-byte alignment logic) + BIC r0, r0, #MODE_MASK ; Clear mode bits + ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR + MSR CPSR_c, r0 ; Re-enter IRQ mode + IF {INTER} = {TRUE} + BX r3 ; Return to caller + ELSE + MOV pc, r3 ; Return to caller + ENDIF +;} + END + diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_irq_nesting_start.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_irq_nesting_start.s new file mode 100644 index 00000000..e3459234 --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_irq_nesting_start.s @@ -0,0 +1,104 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +IRQ_DISABLE EQU 0x80 ; IRQ disable bit +MODE_MASK EQU 0x1F ; Mode mask +SYS_MODE_BITS EQU 0x1F ; System mode bits +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start SMP/Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_irq_nesting_start(VOID) +;{ + EXPORT _tx_thread_irq_nesting_start +_tx_thread_irq_nesting_start + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + BIC r0, r0, #MODE_MASK ; Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS ; Build system mode CPSR + MSR CPSR_c, r0 ; Enter system mode + STMDB sp!, {lr, r1} ; Push the system mode lr on the system mode stack + ; and push r1 just to keep 8-byte alignment + BIC r0, r0, #IRQ_DISABLE ; Build enable IRQ CPSR + MSR CPSR_c, r0 ; Enter system mode + IF {INTER} = {TRUE} + BX r3 ; Return to caller + ELSE + MOV pc, r3 ; Return to caller + ENDIF +;} +; + END + diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_schedule.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_schedule.s new file mode 100644 index 00000000..d71b3666 --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_schedule.s @@ -0,0 +1,314 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IMPORT _tx_thread_execute_ptr + IMPORT _tx_thread_current_ptr + IMPORT _tx_timer_time_slice + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_thread_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule SMP/Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + EXPORT _tx_thread_schedule +_tx_thread_schedule +; +; /* Enable interrupts. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSIE if ; Enable IRQ and FIQ interrupts + ELSE + CPSIE i ; Enable IRQ interrupts + ENDIF +; +; /* Pickup the CPU ID. */ +; + MRC p15, 0, r10, c0, c0, 5 ; Read CPU ID register + AND r10, r10, #0x03 ; Mask off, leaving the CPU ID field + LSL r12, r10, #2 ; Build offset to array indexes + + LDR r1, =_tx_thread_execute_ptr ; Address of thread execute ptr + ADD r1, r1, r12 ; Build offset to execute ptr for this core +; +; /* Lockout interrupts transfer control to it. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF +; +; /* Wait for a thread to execute. */ +; do +; { +; +; + LDR r0, [r1, #0] ; Pickup next thread to execute + CMP r0, #0 ; Is it NULL? + BEQ _tx_thread_schedule ; If so, keep looking for a thread +; +; } +; while(_tx_thread_execute_ptr[core] == TX_NULL); +; +; +; /* Get the lock for accessing the thread's ready bit. */ +; + MOV r2, #172 ; Build offset to the lock + ADD r2, r0, r2 ; Get the address to the lock + LDREX r3, [r2] ; Pickup the lock value + CMP r3, #0 ; Check if it's available + BNE _tx_thread_schedule ; No, lock not available + MOV r3, #1 ; Build the lock set value + STREX r4, r3, [r2] ; Try to get the lock + CMP r4, #0 ; Check if we got the lock + BNE _tx_thread_schedule ; No, another core got it first + DMB ; Ensure write to lock completes +; +; /* Now make sure the thread's ready bit is set. */ +; + LDR r3, [r0, #152] ; Pickup the thread ready bit + AND r4, r3, #0x8000 ; Isolate the ready bit + CMP r4, #0 ; Is it set? + BNE _tx_thread_ready_for_execution ; Yes, schedule the thread +; +; /* The ready bit isn't set. Release the lock and jump back to the scheduler. */ +; + MOV r3, #0 ; Build clear value + STR r3, [r2] ; Release the lock + DMB ; Ensure write to lock completes + B _tx_thread_schedule ; Jump back to the scheduler +; +_tx_thread_ready_for_execution +; +; /* We have a thread to execute. */ +; +; /* Clear the ready bit and release the lock. */ +; + BIC r3, r3, #0x8000 ; Clear ready bit + STR r3, [r0, #152] ; Store it back in the thread control block + DMB + MOV r3, #0 ; Build clear value for the lock + STR r3, [r2] ; Release the lock + DMB +; +; /* Setup the current thread pointer. */ +; _tx_thread_current_ptr[core] = _tx_thread_execute_ptr[core]; +; + LDR r2, =_tx_thread_current_ptr ; Pickup address of current thread + ADD r2, r2, r12 ; Build index into the current thread array + STR r0, [r2, #0] ; Setup current thread pointer +; +; /* In the time between reading the execute pointer and assigning +; it to the current pointer, the execute pointer was changed by +; some external code. If the current pointer was still null when +; the external code checked if a core preempt was necessary, then +; it wouldn't have done it and a preemption will be missed. To +; handle this, undo some things and jump back to the scheduler so +; it can schedule the new thread. */ +; + LDR r1, [r1, #0] ; Reload the execute pointer + CMP r0, r1 ; Did it change? + BEQ _execute_pointer_did_not_change ; If not, skip handling + + MOV r1, #0 ; Build clear value + STR r1, [r2, #0] ; Clear current thread pointer + + LDR r1, [r0, #152] ; Pickup the ready bit + ORR r1, r1, #0x8000 ; Set ready bit (bit 15) + STR r1, [r0, #152] ; Make this thread ready for executing again + DMB ; Ensure that accesses to shared resource have completed + + B _tx_thread_schedule ; Jump back to the scheduler to schedule the new thread + +_execute_pointer_did_not_change +; /* Increment the run count for this thread. */ +; _tx_thread_current_ptr[core] -> tx_thread_run_count++; +; + LDR r2, [r0, #4] ; Pickup run counter + LDR r3, [r0, #24] ; Pickup time-slice for this thread + ADD r2, r2, #1 ; Increment thread run-counter + STR r2, [r0, #4] ; Store the new run counter +; +; /* Setup time-slice, if present. */ +; _tx_timer_time_slice[core] = _tx_thread_current_ptr[core] -> tx_thread_time_slice; +; + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + ; variable + ADD r2, r2, r12 ; Build index into the time-slice array + LDR sp, [r0, #8] ; Switch stack pointers + STR r3, [r2, #0] ; Setup time-slice +; +; /* Switch to the thread's stack. */ +; sp = _tx_thread_execute_ptr[core] -> tx_thread_stack_ptr; +; + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + MOV r5, r0 ; Save r0 + BL _tx_execution_thread_enter ; Call the thread execution enter function + MOV r0, r5 ; Restore r0 + ENDIF +; +; /* Determine if an interrupt frame or a synchronous task suspension frame +; is present. */ +; + LDMIA sp!, {r4, r5} ; Pickup the stack type and saved CPSR + CMP r4, #0 ; Check for synchronous context switch + BEQ _tx_solicited_return + MSR SPSR_cxsf, r5 ; Setup SPSR for return + IF {TARGET_FPU_VFP} = {TRUE} + LDR r1, [r0, #160] ; Pickup the VFP enabled flag + CMP r1, #0 ; Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore ; No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} ; Recover D0-D15 + VLDMIA sp!, {D16-D31} ; Recover D16-D31 + LDR r4, [sp], #4 ; Pickup FPSCR + VMSR FPSCR, r4 ; Restore FPSCR +_tx_skip_interrupt_vfp_restore + ENDIF + LDMIA sp!, {r0-r12, lr, pc}^ ; Return to point of thread interrupt + +_tx_solicited_return + IF {TARGET_FPU_VFP} = {TRUE} + MSR CPSR_cxsf, r5 ; Recover CPSR + LDR r1, [r0, #160] ; Pickup the VFP enabled flag + CMP r1, #0 ; Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore ; No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} ; Recover D8-D15 + VLDMIA sp!, {D16-D31} ; Recover D16-D31 + LDR r4, [sp], #4 ; Pickup FPSCR + VMSR FPSCR, r4 ; Restore FPSCR +_tx_skip_solicited_vfp_restore + ENDIF + MSR CPSR_cxsf, r5 ; Recover CPSR + LDMIA sp!, {r4-r11, lr} ; Return to thread synchronously + BX lr ; Return to caller +; +;} +; + + IF {TARGET_FPU_VFP} = {TRUE} + EXPORT tx_thread_vfp_enable +tx_thread_vfp_enable + MRS r2, CPSR ; Pickup the CPSR + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF + MRC p15, 0, r1, c0, c0, 5 ; Read CPU ID register + AND r1, r1, #0x03 ; Mask off, leaving the CPU ID field + LSL r1, r1, #2 ; Build offset to array indexes + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + ADD r0, r0, r1 ; Build index into the current thread array + LDR r1, [r0] ; Pickup current thread pointer + CMP r1, #0 ; Check for NULL thread pointer + BEQ __tx_no_thread_to_enable ; If NULL, skip VFP enable + MOV r0, #1 ; Build enable value + STR r0, [r1, #160] ; Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable + MSR CPSR_cxsf, r2 ; Recover CPSR + BX LR ; Return to caller + + EXPORT tx_thread_vfp_disable +tx_thread_vfp_disable + MRS r2, CPSR ; Pickup the CPSR + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF + MRC p15, 0, r1, c0, c0, 5 ; Read CPU ID register + AND r1, r1, #0x03 ; Mask off, leaving the CPU ID field + LSL r1, r1, #2 ; Build offset to array indexes + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + ADD r0, r0, r1 ; Build index into the current thread array + LDR r1, [r0] ; Pickup current thread pointer + CMP r1, #0 ; Check for NULL thread pointer + BEQ __tx_no_thread_to_disable ; If NULL, skip VFP disable + MOV r0, #0 ; Build disable value + STR r0, [r1, #160] ; Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable + MSR CPSR_cxsf, r2 ; Recover CPSR + BX LR ; Return to caller + ENDIF +; +;} +; + END + diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_core_get.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_core_get.s new file mode 100644 index 00000000..fb3b07a4 --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_core_get.s @@ -0,0 +1,85 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +;#define TX_THREAD_SMP_SOURCE_CODE +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" */ +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_core_get SMP/Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function gets the currently running core number and returns it.*/ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* Core ID */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ + EXPORT _tx_thread_smp_core_get +_tx_thread_smp_core_get + MRC p15, 0, r0, c0, c0, 5 ; Read CPU ID register + AND r0, r0, #0x03 ; Mask off, leaving the CPU ID field + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF + + END + diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_core_preempt.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_core_preempt.s new file mode 100644 index 00000000..f64941ec --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_core_preempt.s @@ -0,0 +1,101 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +;#define TX_THREAD_SMP_SOURCE_CODE +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" */ +; +; + IMPORT sendSGI + + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_core_preempt SMP/Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function preempts the specified core in situations where the */ +;/* thread corresponding to this core is no longer ready or when the */ +;/* core must be used for a higher-priority thread. If the specified is */ +;/* the current core, this processing is skipped since the will give up */ +;/* control subsequently on its own. */ +;/* */ +;/* INPUT */ +;/* */ +;/* core The core to preempt */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ + EXPORT _tx_thread_smp_core_preempt +_tx_thread_smp_core_preempt + + STMDB sp!, {lr, r4} ; Save the lr and r4 register on the stack +; +; /* Place call to send inter-processor interrupt here! */ +; + DSB ; + MOV r1, #1 ; Build parameter list + LSL r1, r1, r0 ; + MOV r0, #0 ; + MOV r2, #0 ; + BL sendSGI ; Make call to send inter-processor interrupt + + LDMIA sp!, {lr, r4} ; Recover lr register and r4 + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF + + END + diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_current_state_get.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_current_state_get.s new file mode 100644 index 00000000..ae77e525 --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_current_state_get.s @@ -0,0 +1,103 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +;#define TX_THREAD_SMP_SOURCE_CODE +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" */ +; +; + IMPORT _tx_thread_system_state + + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_current_state_get SMP/Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is gets the current state of the calling core. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ + EXPORT _tx_thread_smp_current_state_get +_tx_thread_smp_current_state_get + + MRS r3, CPSR ; Pickup current CPSR + + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF +; +; /* Pickup the CPU ID. */ +; + MRC p15, 0, r2, c0, c0, 5 ; Read CPU ID register + AND r2, r2, #0x03 ; Mask off, leaving the CPU ID field + LSL r2, r2, #2 ; Build offset to array indexes + + LDR r1, =_tx_thread_system_state ; Pickup start of the current state array + ADD r1, r1, r2 ; Build index into the current state array + LDR r0, [r1] ; Pickup state for this core + MSR CPSR_c, r3 ; Restore CPSR + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF + + END + diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_current_thread_get.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_current_thread_get.s new file mode 100644 index 00000000..00b197d9 --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_current_thread_get.s @@ -0,0 +1,103 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +;#define TX_THREAD_SMP_SOURCE_CODE +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" */ +; +; + IMPORT _tx_thread_current_ptr + + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_current_thread_get SMP/Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is gets the current thread of the calling core. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ + EXPORT _tx_thread_smp_current_thread_get +_tx_thread_smp_current_thread_get + + MRS r3, CPSR ; Pickup current CPSR + + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF +; +; /* Pickup the CPU ID. */ +; + MRC p15, 0, r2, c0, c0, 5 ; Read CPU ID register + AND r2, r2, #0x03 ; Mask off, leaving the CPU ID field + LSL r2, r2, #2 ; Build offset to array indexes + + LDR r1, =_tx_thread_current_ptr ; Pickup start of the current thread array + ADD r1, r1, r2 ; Build index into the current thread array + LDR r0, [r1] ; Pickup current thread for this core + MSR CPSR_c, r3 ; Restore CPSR + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF + + END + diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_initialize_wait.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_initialize_wait.s new file mode 100644 index 00000000..67571ac4 --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_initialize_wait.s @@ -0,0 +1,140 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +;#define TX_THREAD_SMP_SOURCE_CODE +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" */ +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_smp_release_cores_flag + IMPORT _tx_thread_schedule + + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_initialize_wait SMP/Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is the place where additional cores wait until */ +;/* initialization is complete before they enter the thread scheduling */ +;/* loop. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Hardware */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ + EXPORT _tx_thread_smp_initialize_wait +_tx_thread_smp_initialize_wait + +; /* Lockout interrupts. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF +; +; /* Pickup the CPU ID. */ +; + MRC p15, 0, r10, c0, c0, 5 ; Read CPU ID register + AND r10, r10, #0x03 ; Mask off, leaving the CPU ID field + LSL r10, r10, #2 ; Build offset to array indexes +; +; /* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release +; flag. */ +; + LDR r3, =_tx_thread_system_state ; Build address of system state variable + ADD r3, r3, r10 ; Build index into the system state array + LDR r2, =0xF0F0F0F0 ; Build TX_INITIALIZE_IN_PROGRESS flag +wait_for_initialize + LDR r1, [r3] ; Pickup system state + CMP r1, r2 ; Has initialization completed? + BNE wait_for_initialize ; If different, wait here! +; +; /* Pickup the release cores flag. */ +; + LDR r2, =_tx_thread_smp_release_cores_flag ; Build address of release cores flag + +wait_for_release + LDR r3, [r2] ; Pickup the flag + CMP r3, #0 ; Is it set? + BEQ wait_for_release ; Wait for the flag to be set +; +; /* Core 0 has released this core. */ +; +; /* Clear this core's system state variable. */ +; + LDR r3, =_tx_thread_system_state ; Build address of system state variable + ADD r3, r3, r10 ; Build index into the system state array + MOV r0, #0 ; Build clear value + STR r0, [r3] ; Clear this core's entry in the system state array +; +; /* Now wait for core 0 to finish it's initialization. */ +; + LDR r3, =_tx_thread_system_state ; Build address of system state variable of logical 0 + +core_0_wait_loop + LDR r2, [r3] ; Pickup system state for core 0 + CMP r2, #0 ; Is it 0? + BNE core_0_wait_loop ; No, keep waiting for core 0 to finish its initialization +; +; /* Initialize is complete, enter the scheduling loop! */ +; + B _tx_thread_schedule ; Enter scheduling loop for this core! + + END + diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_low_level_initialize.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_low_level_initialize.s new file mode 100644 index 00000000..0d712322 --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_low_level_initialize.s @@ -0,0 +1,84 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +;#define TX_THREAD_SMP_SOURCE_CODE +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" */ +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_low_level_initialize SMP/Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function performs low-level initialization of the booting */ +;/* core. */ +;/* */ +;/* INPUT */ +;/* */ +;/* number_of_cores Number of cores */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_high_level ThreadX high-level init */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ + EXPORT _tx_thread_smp_low_level_initialize +_tx_thread_smp_low_level_initialize + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF + + END + diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_protect.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_protect.s new file mode 100644 index 00000000..517981fc --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_protect.s @@ -0,0 +1,370 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +;#define TX_THREAD_SMP_SOURCE_CODE +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" */ +; +; + +;/* Include macros for modifying the wait list. */ +#include "tx_thread_smp_protection_wait_list_macros.h" + + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_smp_protection + IMPORT _tx_thread_smp_protect_wait_counts + IMPORT _tx_thread_smp_protect_wait_list + IMPORT _tx_thread_smp_protect_wait_list_lock_protect_in_force + IMPORT _tx_thread_smp_protect_wait_list_head + IMPORT _tx_thread_smp_protect_wait_list_tail + IMPORT _tx_thread_smp_protect_wait_list_size + + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_protect SMP/Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function gets protection for running inside the ThreadX */ +;/* source. This is acomplished by a combination of a test-and-set */ +;/* flag and periodically disabling interrupts. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* Previous Status Register */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ + EXPORT _tx_thread_smp_protect +_tx_thread_smp_protect + + PUSH {r4-r6} ; Save registers we'll be using +; +; /* Disable interrupts so we don't get preempted. */ +; + MRS r0, CPSR ; Pickup current CPSR + + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF +; +; /* Do we already have protection? */ +; if (this_core == _tx_thread_smp_protection.tx_thread_smp_protect_core) +; { +; + MRC p15, 0, r1, c0, c0, 5 ; Read CPU ID register + AND r1, r1, #0x03 ; Mask off, leaving the CPU ID field + LDR r2, =_tx_thread_smp_protection ; Build address to protection structure + LDR r3, [r2, #8] ; Pickup the owning core + CMP r1, r3 ; Is it not this core? + BNE _protection_not_owned ; No, the protection is not already owned +; +; /* We already have protection. */ +; +; /* Increment the protection count. */ +; _tx_thread_smp_protection.tx_thread_smp_protect_count++; +; + LDR r3, [r2, #12] ; Pickup ownership count + ADD r3, r3, #1 ; Increment ownership count + STR r3, [r2, #12] ; Store ownership count + DMB + + B _return + +_protection_not_owned +; +; /* Is the lock available? */ +; if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0) +; { +; + LDREX r3, [r2, #0] ; Pickup the protection flag + CMP r3, #0 + BNE _start_waiting ; No, protection not available +; +; /* Is the list empty? */ +; if (_tx_thread_smp_protect_wait_list_head == _tx_thread_smp_protect_wait_list_tail) +; { +; + LDR r3, =_tx_thread_smp_protect_wait_list_head + LDR r3, [r3] + LDR r4, =_tx_thread_smp_protect_wait_list_tail + LDR r4, [r4] + CMP r3, r4 + BNE _list_not_empty +; +; /* Try to get the lock. */ +; if (write_exclusive(&_tx_thread_smp_protection.tx_thread_smp_protect_in_force, 1) == SUCCESS) +; { +; + MOV r3, #1 ; Build lock value + STREX r4, r3, [r2, #0] ; Attempt to get the protection + CMP r4, #0 + BNE _start_waiting ; Did it fail? +; +; /* We got the lock! */ +; _tx_thread_smp_protect_lock_got(); +; + DMB ; Ensure write to protection finishes +macro_call0 _tx_thread_smp_protect_lock_got ; Call the lock got function + + B _return + +_list_not_empty +; +; /* Are we at the front of the list? */ +; if (this_core == _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head]) +; { +; + LDR r3, =_tx_thread_smp_protect_wait_list_head ; Get the address of the head + LDR r3, [r3] ; Get the value of the head + LDR r4, =_tx_thread_smp_protect_wait_list ; Get the address of the list + LDR r4, [r4, r3, LSL #2] ; Get the value at the head index + + CMP r1, r4 + BNE _start_waiting +; +; /* Is the lock still available? */ +; if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0) +; { +; + LDR r3, [r2, #0] ; Pickup the protection flag + CMP r3, #0 + BNE _start_waiting ; No, protection not available +; +; /* Get the lock. */ +; _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1; +; + MOV r3, #1 ; Build lock value + STR r3, [r2, #0] ; Store lock value + DMB ; +; +; /* Got the lock. */ +; _tx_thread_smp_protect_lock_got(); +; +macro_call1 _tx_thread_smp_protect_lock_got +; +; /* Remove this core from the wait list. */ +; _tx_thread_smp_protect_remove_from_front_of_list(); +; +macro_call2 _tx_thread_smp_protect_remove_from_front_of_list + + B _return + +_start_waiting +; +; /* For one reason or another, we didn't get the lock. */ +; +; /* Increment wait count. */ +; _tx_thread_smp_protect_wait_counts[this_core]++; +; + LDR r3, =_tx_thread_smp_protect_wait_counts ; Load wait list counts + LDR r4, [r3, r1, LSL #2] ; Load waiting value for this core + ADD r4, r4, #1 ; Increment wait value + STR r4, [r3, r1, LSL #2] ; Store new wait value +; +; /* Have we not added ourselves to the list yet? */ +; if (_tx_thread_smp_protect_wait_counts[this_core] == 1) +; { +; + CMP r4, #1 + BNE _already_in_list0 ; Is this core already waiting? +; +; /* Add ourselves to the list. */ +; _tx_thread_smp_protect_wait_list_add(this_core); +; +macro_call3 _tx_thread_smp_protect_wait_list_add ; Call macro to add ourselves to the list +; +; } +; +_already_in_list0 +; +; /* Restore interrupts. */ +; + MSR CPSR_c, r0 ; Restore CPSR + IF :DEF:TX_ENABLE_WFE + WFE ; Go into standby + ENDIF +; +; /* We do this until we have the lock. */ +; while (1) +; { +; +_try_to_get_lock +; +; /* Disable interrupts so we don't get preempted. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF + + MRC p15, 0, r1, c0, c0, 5 ; Read CPU ID register + AND r1, r1, #0x03 ; Mask off, leaving the CPU ID field +; +; /* Do we already have protection? */ +; if (this_core == _tx_thread_smp_protection.tx_thread_smp_protect_core) +; { +; + LDR r3, [r2, #8] ; Pickup the owning core + CMP r3, r1 ; Is it this core? + BEQ _got_lock_after_waiting ; Yes, the protection is already owned. This means + ; an ISR preempted us and got protection +; +; } +; +; /* Are we at the front of the list? */ +; if (this_core == _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head]) +; { +; + LDR r3, =_tx_thread_smp_protect_wait_list_head ; Get the address of the head + LDR r3, [r3] ; Get the value of the head + LDR r4, =_tx_thread_smp_protect_wait_list ; Get the address of the list + LDR r4, [r4, r3, LSL #2] ; Get the value at the head index + + CMP r1, r4 + BNE _did_not_get_lock +; +; /* Is the lock still available? */ +; if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0) +; { +; + LDR r3, [r2, #0] ; Pickup the protection flag + CMP r3, #0 + BNE _did_not_get_lock ; No, protection not available +; +; /* Get the lock. */ +; _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1; +; + MOV r3, #1 ; Build lock value + STR r3, [r2, #0] ; Store lock value + DMB ; +; +; /* Got the lock. */ +; _tx_thread_smp_protect_lock_got(); +; +macro_call4 _tx_thread_smp_protect_lock_got +; +; /* Remove this core from the wait list. */ +; _tx_thread_smp_protect_remove_from_front_of_list(); +; +macro_call5 _tx_thread_smp_protect_remove_from_front_of_list + + B _got_lock_after_waiting + +_did_not_get_lock +; +; /* For one reason or another, we didn't get the lock. */ +; +; /* Were we removed from the list? This can happen if we're a thread +; and we got preempted. */ +; if (_tx_thread_smp_protect_wait_counts[this_core] == 0) +; { +; + LDR r3, =_tx_thread_smp_protect_wait_counts ; Load wait list counts + LDR r4, [r3, r1, LSL #2] ; Load waiting value for this core + CMP r4, #0 + BNE _already_in_list1 ; Is this core already in the list? +; +; /* Add ourselves to the list. */ +; _tx_thread_smp_protect_wait_list_add(this_core); +; +macro_call6 _tx_thread_smp_protect_wait_list_add ; Call macro to add ourselves to the list +; +; /* Our waiting count was also reset when we were preempted. Increment it again. */ +; _tx_thread_smp_protect_wait_counts[this_core]++; +; + LDR r3, =_tx_thread_smp_protect_wait_counts ; Load wait list counts + LDR r4, [r3, r1, LSL #2] ; Load waiting value for this core + ADD r4, r4, #1 ; Increment wait value + STR r4, [r3, r1, LSL #2] ; Store new wait value value +; +; } +; +_already_in_list1 +; +; /* Restore interrupts and try again. */ +; + MSR CPSR_c, r0 ; Restore CPSR + IF :DEF:TX_ENABLE_WFE + WFE ; Go into standby + ENDIF + B _try_to_get_lock ; On waking, restart the protection attempt + +_got_lock_after_waiting +; +; /* We're no longer waiting. */ +; _tx_thread_smp_protect_wait_counts[this_core]--; +; + LDR r3, =_tx_thread_smp_protect_wait_counts ; Load waiting list + LDR r4, [r3, r1, LSL #2] ; Load current wait value + SUB r4, r4, #1 ; Decrement wait value + STR r4, [r3, r1, LSL #2] ; Store new wait value value + +; +; /* Restore link register and return. */ +; +_return + + POP {r4-r6} ; Restore registers + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF + + END + diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_protection_wait_list_macros.h new file mode 100644 index 00000000..685b2180 --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_protection_wait_list_macros.h @@ -0,0 +1,315 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ + + MACRO +$label _tx_thread_smp_protect_lock_got +; +; /* Set the currently owned core. */ +; _tx_thread_smp_protection.tx_thread_smp_protect_core = this_core; +; + STR r1, [r2, #8] ; Store this core +; +; /* Increment the protection count. */ +; _tx_thread_smp_protection.tx_thread_smp_protect_count++; +; + LDR r3, [r2, #12] ; Pickup ownership count + ADD r3, r3, #1 ; Increment ownership count + STR r3, [r2, #12] ; Store ownership count + DMB + + IF :DEF:TX_MPCORE_DEBUG_ENABLE + LSL r3, r1, #2 ; Build offset to array indexes + LDR r4, =_tx_thread_current_ptr ; Pickup start of the current thread array + ADD r4, r3, r4 ; Build index into the current thread array + LDR r3, [r4] ; Pickup current thread for this core + STR r3, [r2, #4] ; Save current thread pointer + STR LR, [r2, #16] ; Save caller's return address + STR r0, [r2, #20] ; Save CPSR + ENDIF + + MEND + + MACRO +$label _tx_thread_smp_protect_remove_from_front_of_list +; +; /* Remove ourselves from the list. */ +; _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head++] = 0xFFFFFFFF; +; + MOV r3, #0xFFFFFFFF ; Build the invalid core value + LDR r4, =_tx_thread_smp_protect_wait_list_head ; Get the address of the head + LDR r5, [r4] ; Get the value of the head + LDR r6, =_tx_thread_smp_protect_wait_list ; Get the address of the list + STR r3, [r6, r5, LSL #2] ; Store the invalid core value + ADD r5, r5, #1 ; Increment the head +; +; /* Did we wrap? */ +; if (_tx_thread_smp_protect_wait_list_head == TX_THREAD_SMP_MAX_CORES + 1) +; { +; + LDR r3, =_tx_thread_smp_protect_wait_list_size ; Load address of core list size + LDR r3, [r3] ; Load the max cores value + CMP r5, r3 ; Compare the head to it + BNE $label._store_new_head ; Are we at the max? +; +; _tx_thread_smp_protect_wait_list_head = 0; +; + EOR r5, r5, r5 ; We're at the max. Set it to zero +; +; } +; +$label._store_new_head + + STR r5, [r4] ; Store the new head +; +; /* We have the lock! */ +; return; +; + MEND + + + MACRO +$label _tx_thread_smp_protect_wait_list_lock_get +;VOID _tx_thread_smp_protect_wait_list_lock_get() +;{ +; /* We do this until we have the lock. */ +; while (1) +; { +; +$label._tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock +; +; /* Is the list lock available? */ +; _tx_thread_smp_protect_wait_list_lock_protect_in_force = load_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force); +; + LDR r1, =_tx_thread_smp_protect_wait_list_lock_protect_in_force + LDREX r2, [r1] ; Pickup the protection flag +; +; if (protect_in_force == 0) +; { +; + CMP r2, #0 + BNE $label._tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock ; No, protection not available +; +; /* Try to get the list. */ +; int status = store_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force, 1); +; + MOV r2, #1 ; Build lock value + STREX r3, r2, [r1] ; Attempt to get the protection +; +; if (status == SUCCESS) +; + CMP r3, #0 + BNE $label._tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock ; Did it fail? If so, try again. +; +; /* We have the lock! */ +; return; +; + MEND + + + MACRO +$label _tx_thread_smp_protect_wait_list_add +;VOID _tx_thread_smp_protect_wait_list_add(UINT new_core) +;{ +; +; /* We're about to modify the list, so get the list lock. */ +; _tx_thread_smp_protect_wait_list_lock_get(); +; + PUSH {r1-r2} + +$label _tx_thread_smp_protect_wait_list_lock_get + + POP {r1-r2} +; +; /* Add this core. */ +; _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_tail++] = new_core; +; + LDR r3, =_tx_thread_smp_protect_wait_list_tail ; Get the address of the tail + LDR r4, [r3] ; Get the value of tail + LDR r5, =_tx_thread_smp_protect_wait_list ; Get the address of the list + STR r1, [r5, r4, LSL #2] ; Store the new core value + ADD r4, r4, #1 ; Increment the tail +; +; /* Did we wrap? */ +; if (_tx_thread_smp_protect_wait_list_tail == _tx_thread_smp_protect_wait_list_size) +; { +; + LDR r5, =_tx_thread_smp_protect_wait_list_size ; Load max cores address + LDR r5, [r5] ; Load max cores value + CMP r4, r5 ; Compare max cores to tail + BNE $label._tx_thread_smp_protect_wait_list_add__no_wrap ; Did we wrap? +; +; _tx_thread_smp_protect_wait_list_tail = 0; +; + MOV r4, #0 +; +; } +; +$label._tx_thread_smp_protect_wait_list_add__no_wrap + + STR r4, [r3] ; Store the new tail value. +; +; /* Release the list lock. */ +; _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; +; + MOV r3, #0 ; Build lock value + LDR r4, =_tx_thread_smp_protect_wait_list_lock_protect_in_force + STR r3, [r4] ; Store the new value + + MEND + + + MACRO +$label _tx_thread_smp_protect_wait_list_remove +;VOID _tx_thread_smp_protect_wait_list_remove(UINT core) +;{ +; +; /* Get the core index. */ +; UINT core_index; +; for (core_index = 0;; core_index++) +; + EOR r1, r1, r1 ; Clear for 'core_index' + LDR r2, =_tx_thread_smp_protect_wait_list ; Get the address of the list +; +; { +; +$label._tx_thread_smp_protect_wait_list_remove__check_cur_core +; +; /* Is this the core? */ +; if (_tx_thread_smp_protect_wait_list[core_index] == core) +; { +; break; +; + LDR r3, [r2, r1, LSL #2] ; Get the value at the current index + CMP r3, r0 ; Did we find the core? + BEQ $label._tx_thread_smp_protect_wait_list_remove__found_core +; +; } +; + ADD r1, r1, #1 ; Increment cur index + B $label._tx_thread_smp_protect_wait_list_remove__check_cur_core ; Restart the loop +; +; } +; +$label._tx_thread_smp_protect_wait_list_remove__found_core +; +; /* We're about to modify the list. Get the lock. We need the lock because another +; core could be simultaneously adding (a core is simultaneously trying to get +; the inter-core lock) or removing (a core is simultaneously being preempted, +; like what is currently happening). */ +; _tx_thread_smp_protect_wait_list_lock_get(); +; + PUSH {r1} + +$label _tx_thread_smp_protect_wait_list_lock_get + + POP {r1} +; +; /* We remove by shifting. */ +; while (core_index != _tx_thread_smp_protect_wait_list_tail) +; { +; +$label._tx_thread_smp_protect_wait_list_remove__compare_index_to_tail + + LDR r2, =_tx_thread_smp_protect_wait_list_tail ; Load tail address + LDR r2, [r2] ; Load tail value + CMP r1, r2 ; Compare cur index and tail + BEQ $label._tx_thread_smp_protect_wait_list_remove__removed +; +; UINT next_index = core_index + 1; +; + MOV r2, r1 ; Move current index to next index register + ADD r2, r2, #1 ; Add 1 +; +; if (next_index == _tx_thread_smp_protect_wait_list_size) +; { +; + LDR r3, =_tx_thread_smp_protect_wait_list_size + LDR r3, [r3] + CMP r2, r3 + BNE $label._tx_thread_smp_protect_wait_list_remove__next_index_no_wrap +; +; next_index = 0; +; + MOV r2, #0 +; +; } +; +$label._tx_thread_smp_protect_wait_list_remove__next_index_no_wrap +; +; list_cores[core_index] = list_cores[next_index]; +; + LDR r0, =_tx_thread_smp_protect_wait_list ; Get the address of the list + LDR r3, [r0, r2, LSL #2] ; Get the value at the next index + STR r3, [r0, r1, LSL #2] ; Store the value at the current index +; +; core_index = next_index; +; + MOV r1, r2 + + B $label._tx_thread_smp_protect_wait_list_remove__compare_index_to_tail +; +; } +; +$label._tx_thread_smp_protect_wait_list_remove__removed +; +; /* Now update the tail. */ +; if (_tx_thread_smp_protect_wait_list_tail == 0) +; { +; + LDR r0, =_tx_thread_smp_protect_wait_list_tail ; Load tail address + LDR r1, [r0] ; Load tail value + CMP r1, #0 + BNE $label._tx_thread_smp_protect_wait_list_remove__tail_not_zero +; +; _tx_thread_smp_protect_wait_list_tail = _tx_thread_smp_protect_wait_list_size; +; + LDR r2, =_tx_thread_smp_protect_wait_list_size + LDR r1, [r2] +; +; } +; +$label._tx_thread_smp_protect_wait_list_remove__tail_not_zero +; +; _tx_thread_smp_protect_wait_list_tail--; +; + SUB r1, r1, #1 + STR r1, [r0] ; Store new tail value +; +; /* Release the list lock. */ +; _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; +; + MOV r0, #0 ; Build lock value + LDR r1, =_tx_thread_smp_protect_wait_list_lock_protect_in_force ; Load lock address + STR r0, [r1] ; Store the new value +; +; /* We're no longer waiting. Note that this should be zero since, again, +; this function is only called when a thread preemption is occurring. */ +; _tx_thread_smp_protect_wait_counts[core]--; +; + MRC p15, 0, r0, c0, c0, 5 ; Read CPU ID register + AND r0, r0, #0x03 ; Mask off, leaving the CPU ID field + LDR r1, =_tx_thread_smp_protect_wait_counts ; Load wait list counts + LDR r2, [r1, r0, LSL #2] ; Load waiting value + SUB r2, r2, #1 ; Subtract 1 + STR r2, [r1, r0, LSL #2] ; Store new waiting value + MEND + diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_time_get.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_time_get.s new file mode 100644 index 00000000..9f7d7388 --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_time_get.s @@ -0,0 +1,88 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +;#define TX_THREAD_SMP_SOURCE_CODE +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" */ +; +; + + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_time_get SMP/Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function gets the global time value that is used for debug */ +;/* information and event tracing. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* 32-bit time stamp */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ + EXPORT _tx_thread_smp_time_get +_tx_thread_smp_time_get + + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + LDR r0, [r0, #0x604] ; Read count register + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF + + END + diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_unprotect.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_unprotect.s new file mode 100644 index 00000000..80b174de --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_smp_unprotect.s @@ -0,0 +1,142 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +;#define TX_THREAD_SMP_SOURCE_CODE +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" */ +; +; + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_smp_protection + IMPORT _tx_thread_preempt_disable + IMPORT _tx_thread_smp_protect_wait_counts + + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_unprotect SMP/Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function releases previously obtained protection. The supplied */ +;/* previous SR is restored. If the value of _tx_thread_system_state */ +;/* and _tx_thread_preempt_disable are both zero, then multithreading */ +;/* is enabled as well. */ +;/* */ +;/* INPUT */ +;/* */ +;/* Previous Status Register */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ + EXPORT _tx_thread_smp_unprotect +_tx_thread_smp_unprotect +; +; /* Lockout interrupts. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF + + MRC p15, 0, r1, c0, c0, 5 ; Read CPU ID register + AND r1, r1, #0x03 ; Mask off, leaving the CPU ID field + + LDR r2,=_tx_thread_smp_protection ; Build address of protection structure + LDR r3, [r2, #8] ; Pickup the owning core + CMP r1, r3 ; Is it this core? + BNE _still_protected ; If this is not the owning core, protection is in force elsewhere + + LDR r3, [r2, #12] ; Pickup the protection count + CMP r3, #0 ; Check to see if the protection is still active + BEQ _still_protected ; If the protection count is zero, protection has already been cleared + + SUB r3, r3, #1 ; Decrement the protection count + STR r3, [r2, #12] ; Store the new count back + CMP r3, #0 ; Check to see if the protection is still active + BNE _still_protected ; If the protection count is non-zero, protection is still in force + LDR r2,=_tx_thread_preempt_disable ; Build address of preempt disable flag + LDR r3, [r2] ; Pickup preempt disable flag + CMP r3, #0 ; Is the preempt disable flag set? + BNE _still_protected ; Yes, skip the protection release + + LDR r2,=_tx_thread_smp_protect_wait_counts ; Build build address of wait counts + LDR r3, [r2, r1, LSL #2] ; Pickup wait list value + CMP r3, #0 ; Are any entities on this core waiting? + BNE _still_protected ; Yes, skip the protection release + + LDR r2,=_tx_thread_smp_protection ; Build address of protection structure + MOV r3, #0xFFFFFFFF ; Build invalid value + STR r3, [r2, #8] ; Mark the protected core as invalid + IF :DEF:TX_MPCORE_DEBUG_ENABLE + STR LR, [r2, #16] ; Save caller's return address + ENDIF + DMB ; Ensure that accesses to shared resource have completed + MOV r3, #0 ; Build release protection value + STR r3, [r2, #0] ; Release the protection + DSB ; To ensure update of the protection occurs before other CPUs awake + IF :DEF:TX_ENABLE_WFE + SEV ; Send event to other CPUs, wakes anyone waiting on the protection (using WFE) + ENDIF + +_still_protected + MSR CPSR_c, r0 ; Restore CPSR + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF + + END + diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_stack_build.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_stack_build.s new file mode 100644 index 00000000..215bc0fc --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_stack_build.s @@ -0,0 +1,172 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +SVC_MODE EQU 0x13 ; SVC mode + IF :DEF:TX_ENABLE_FIQ_SUPPORT +CPSR_MASK EQU 0xDF ; Mask initial CPSR, IRQ & FIQ ints enabled + ELSE +CPSR_MASK EQU 0x9F ; Mask initial CPSR, IRQ ints enabled + ENDIF + +THUMB_BIT EQU 0x20 ; Thumb-bit + +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build SMP/Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + EXPORT _tx_thread_stack_build +_tx_thread_stack_build +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-A5 should look like the following after it is built: +; +; Stack Top: 1 Interrupt stack frame type +; CPSR Initial value for CPSR +; a1 (r0) Initial value for a1 +; a2 (r1) Initial value for a2 +; a3 (r2) Initial value for a3 +; a4 (r3) Initial value for a4 +; v1 (r4) Initial value for v1 +; v2 (r5) Initial value for v2 +; v3 (r6) Initial value for v3 +; v4 (r7) Initial value for v4 +; v5 (r8) Initial value for v5 +; sb (r9) Initial value for sb +; sl (r10) Initial value for sl +; fp (r11) Initial value for fp +; ip (r12) Initial value for ip +; lr (r14) Initial value for lr +; pc (r15) Initial value for pc +; 0 For stack backtracing +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #7 ; Ensure 8-byte alignment + SUB r2, r2, #76 ; Allocate space for the stack frame +; +; /* Actually build the stack frame. */ +; + MOV r3, #1 ; Build interrupt stack type + STR r3, [r2, #0] ; Store stack type + MOV r3, #0 ; Build initial register value + STR r3, [r2, #8] ; Store initial r0 + STR r3, [r2, #12] ; Store initial r1 + STR r3, [r2, #16] ; Store initial r2 + STR r3, [r2, #20] ; Store initial r3 + STR r3, [r2, #24] ; Store initial r4 + STR r3, [r2, #28] ; Store initial r5 + STR r3, [r2, #32] ; Store initial r6 + STR r3, [r2, #36] ; Store initial r7 + STR r3, [r2, #40] ; Store initial r8 + STR r3, [r2, #44] ; Store initial r9 + LDR r3, [r0, #12] ; Pickup stack starting address + STR r3, [r2, #48] ; Store initial r10 (sl) + MOV r3, #0 ; Build initial register value + STR r3, [r2, #52] ; Store initial r11 + STR r3, [r2, #56] ; Store initial r12 + STR r3, [r2, #60] ; Store initial lr + STR r1, [r2, #64] ; Store initial pc + STR r3, [r2, #68] ; 0 for back-trace + + MRS r3, CPSR ; Pickup CPSR + BIC r3, r3, #CPSR_MASK ; Mask mode bits of CPSR + ORR r3, r3, #SVC_MODE ; Build CPSR, SVC mode, interrupts enabled + BIC r3, r3, #THUMB_BIT ; Clear Thumb-bit by default + AND r1, r1, #1 ; Determine if the entry function is in Thumb mode + CMP r1, #1 ; Is the Thumb-bit set? + ORREQ r3, r3, #THUMB_BIT ; Yes, set the Thumb-bit + STR r3, [r2, #4] ; Store initial CPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block + +; +; /* Set ready bit in thread control block. */ +; + LDR r2, [r0, #152] ; Pickup word with ready bit + ORR r2, r2, #0x8000 ; Build ready bit set + STR r2, [r0, #152] ; Set ready bit + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +;} + END + diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_system_return.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_system_return.s new file mode 100644 index 00000000..83ff71d6 --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_system_return.s @@ -0,0 +1,205 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IMPORT _tx_thread_current_ptr + IMPORT _tx_timer_time_slice + IMPORT _tx_thread_schedule + IMPORT _tx_thread_preempt_disable + IMPORT _tx_thread_smp_protection + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_thread_exit + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return SMP/Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + EXPORT _tx_thread_system_return +_tx_thread_system_return +; +; /* Save minimal context on the stack. */ +; + STMDB sp!, {r4-r11, lr} ; Save minimal context +; +; /* Pickup the CPU ID. */ +; + MRC p15, 0, r10, c0, c0, 5 ; Read CPU ID register + AND r10, r10, #0x03 ; Mask off, leaving the CPU ID field + LSL r12, r10, #2 ; Build offset to array indexes + + LDR r3, =_tx_thread_current_ptr ; Pickup address of current ptr + ADD r3, r3, r12 ; Build index into current ptr array + LDR r0, [r3, #0] ; Pickup current thread pointer + IF {TARGET_FPU_VFP} = {TRUE} + LDR r1, [r0, #160] ; Pickup the VFP enabled flag + CMP r1, #0 ; Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save ; No, skip VFP solicited save + VMRS r4, FPSCR ; Pickup the FPSCR + STR r4, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D8-D15} ; Save D8-D15 +_tx_skip_solicited_vfp_save + ENDIF + MOV r4, #0 ; Build a solicited stack type + MRS r5, CPSR ; Pickup the CPSR + STMDB sp!, {r4-r5} ; Save type and CPSR +; +; /* Lockout interrupts. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + MOV r4, r0 ; Save r0 + MOV r5, r3 ; Save r3 + MOV r6, r12 ; Save r12 + BL _tx_execution_thread_exit ; Call the thread exit function + MOV r3, r5 ; Recover r3 + MOV r0, r4 ; Recover r4 + MOV r12,r6 ; Recover r12 + ENDIF +; + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + ADD r2, r2, r12 ; Build index into time-slice array + LDR r1, [r2, #0] ; Pickup current time slice +; +; /* Save current stack and switch to system stack. */ +; _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; +; sp = _tx_thread_system_stack_ptr[core]; +; + STR sp, [r0, #8] ; Save thread stack pointer +; +; /* Determine if the time-slice is active. */ +; if (_tx_timer_time_slice[core]) +; { +; + MOV r4, #0 ; Build clear value + CMP r1, #0 ; Is a time-slice active? + BEQ __tx_thread_dont_save_ts ; No, don't save the time-slice +; +; /* Save time-slice for the thread and clear the current time-slice. */ +; _tx_thread_current_ptr[core] -> tx_thread_time_slice = _tx_timer_time_slice[core]; +; _tx_timer_time_slice[core] = 0; +; + STR r4, [r2, #0] ; Clear time-slice + STR r1, [r0, #24] ; Save current time-slice +; +; } +__tx_thread_dont_save_ts +; +; /* Clear the current thread pointer. */ +; _tx_thread_current_ptr[core] = TX_NULL; +; + STR r4, [r3, #0] ; Clear current thread pointer +; +; /* Set ready bit in thread control block. */ +; + LDR r2, [r0, #152] ; Pickup word with ready bit + ORR r2, r2, #0x8000 ; Build ready bit set + DMB ; Ensure that accesses to shared resource have completed + STR r2, [r0, #152] ; Set ready bit +; +; /* Now clear protection. It is assumed that protection is in force whenever this routine is called. */ +; + LDR r3, =_tx_thread_smp_protection ; Pickup address of protection structure + + IF :DEF:TX_MPCORE_DEBUG_ENABLE + STR lr, [r3, #24] ; Save last caller + LDR r2, [r3, #4] ; Pickup owning thread + CMP r0, r2 ; Is it the same as the current thread? +__error_loop + BNE __error_loop ; If not, we have a problem!! + ENDIF + + LDR r1, =_tx_thread_preempt_disable ; Build address to preempt disable flag + MOV r2, #0 ; Build clear value + STR r2, [r1, #0] ; Clear preempt disable flag + STR r2, [r3, #12] ; Clear protection count + MOV r1, #0xFFFFFFFF ; Build invalid value + STR r1, [r3, #8] ; Set core to an invalid value + DMB ; Ensure that accesses to shared resource have completed + STR r2, [r3] ; Clear protection + DSB ; To ensure update of the shared resource occurs before other CPUs awake + SEV ; Send event to other CPUs, wakes anyone waiting on a mutex (using WFE) + + B _tx_thread_schedule ; Jump to scheduler! +; +;} + END + diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_thread_vectored_context_save.s b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_vectored_context_save.s new file mode 100644 index 00000000..5ed05531 --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_thread_vectored_context_save.s @@ -0,0 +1,209 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save SMP/Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_vectored_context_save(VOID) +;{ + EXPORT _tx_thread_vectored_context_save +_tx_thread_vectored_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state[core]++) +; { +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ENDIF +; +; /* Pickup the CPU ID. */ +; + MRC p15, 0, r10, c0, c0, 5 ; Read CPU ID register + AND r10, r10, #0x03 ; Mask off, leaving the CPU ID field + LSL r12, r10, #2 ; Build offset to array indexes + + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + ADD r3, r3, r12 ; Build index into the system state array + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Note: Minimal context of interrupted thread is already saved. */ +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {r12, lr} ; Save ISR lr & r12 + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {r12, lr} ; Recover ISR lr & r12 + ENDIF + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +__tx_thread_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr[core]) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + ADD r1, r1, r12 ; Build index into current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + ; scheduling loop - nothing needs saving! +; +; /* Note: Minimal context of interrupted thread is already saved. */ +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr[core]; +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {r12, lr} ; Save ISR lr & r12 + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {r12, lr} ; Recover ISR lr & r12 + ENDIF + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +; } +; else +; { +; +__tx_thread_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; processing. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {r12, lr} ; Save ISR lr & r12 + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {r12, lr} ; Recover ISR lr & r12 + ENDIF + + ADD sp, sp, #32 ; Recover saved registers + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +; } +;} +; + END + diff --git a/ports_smp/cortex_a5_smp/ac5/src/tx_timer_interrupt.s b/ports_smp/cortex_a5_smp/ac5/src/tx_timer_interrupt.s new file mode 100644 index 00000000..6ef1ec67 --- /dev/null +++ b/ports_smp/cortex_a5_smp/ac5/src/tx_timer_interrupt.s @@ -0,0 +1,229 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_timer.h" +;#include "tx_thread.h" +; +; +;Define Assembly language external references... +; + IMPORT _tx_timer_time_slice + IMPORT _tx_timer_system_clock + IMPORT _tx_timer_current_ptr + IMPORT _tx_timer_list_start + IMPORT _tx_timer_list_end + IMPORT _tx_timer_expired_time_slice + IMPORT _tx_timer_expired + IMPORT _tx_thread_time_slice + IMPORT _tx_timer_expiration_process + IMPORT _tx_timer_interrupt_active + IMPORT _tx_thread_smp_protect + IMPORT _tx_thread_smp_unprotect + IMPORT _tx_trace_isr_enter_insert + IMPORT _tx_trace_isr_exit_insert +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt SMP/Cortex-A5/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* _tx_thread_smp_protect Get SMP protection */ +;/* _tx_thread_smp_unprotect Releast SMP protection */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + EXPORT _tx_timer_interrupt +_tx_timer_interrupt +; +; /* Upon entry to this routine, it is assumed that context save has already +; been called, and therefore the compiler scratch registers are available +; for use. */ +; + MRC p15, 0, r0, c0, c0, 5 ; Read CPU ID register + AND r0, r0, #0x03 ; Mask off, leaving the CPU ID field + CMP r0, #0 ; Only process timer interrupts from core 0 (to change this simply change the constant!) + BEQ __tx_process_timer ; If the same process the interrupt + BX lr ; Return to caller if not matched +__tx_process_timer + + STMDB sp!, {lr, r4} ; Save the lr and r4 register on the stack + BL _tx_thread_smp_protect ; Get protection + MOV r4, r0 ; Save the return value in preserved register + + LDR r1, =_tx_timer_interrupt_active ; Pickup address of timer interrupt active count + LDR r0, [r1, #0] ; Pickup interrupt active count + ADD r0, r0, #1 ; Increment interrupt active count + STR r0, [r1, #0] ; Store new interrupt active count + DMB ; Ensure that accesses to shared resource have completed +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + LDR r1, =_tx_timer_system_clock ; Pickup address of system clock + LDR r0, [r1, #0] ; Pickup system clock + ADD r0, r0, #1 ; Increment system clock + STR r0, [r1, #0] ; Store new system clock +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + LDR r1, =_tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Check for previous timer expiration still active + BNE __tx_timer_done ; If so, skip timer processing + LDR r1, =_tx_timer_current_ptr ; Pickup current timer pointer addr + LDR r0, [r1, #0] ; Pickup current timer + LDR r2, [r0, #0] ; Pickup timer list entry + CMP r2, #0 ; Is there anything in the list? + BEQ __tx_timer_no_timer ; No, just increment the timer +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + LDR r3, =_tx_timer_expired ; Pickup expiration flag address + MOV r2, #1 ; Build expired value + STR r2, [r3, #0] ; Set expired flag + B __tx_timer_done ; Finished timer processing +; +; } +; else +; { +__tx_timer_no_timer +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ADD r0, r0, #4 ; Move to next timer +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + LDR r3, =_tx_timer_list_end ; Pickup addr of timer list end + LDR r2, [r3, #0] ; Pickup list end + CMP r0, r2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, skip wrap-around logic +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + LDR r3, =_tx_timer_list_start ; Pickup addr of timer list start + LDR r0, [r3, #0] ; Set current pointer to list start +; +__tx_timer_skip_wrap +; + STR r0, [r1, #0] ; Store new current timer pointer +; } +; +__tx_timer_done +; +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + LDR r1, =_tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Check for timer expiration + BEQ __tx_timer_dont_activate ; If not set, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BL _tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate +; +; /* Call time-slice processing. */ +; _tx_thread_time_slice(); + + BL _tx_thread_time_slice ; Call time-slice processing +; +; } +; + LDR r1, =_tx_timer_interrupt_active ; Pickup address of timer interrupt active count + LDR r0, [r1, #0] ; Pickup interrupt active count + SUB r0, r0, #1 ; Decrement interrupt active count + STR r0, [r1, #0] ; Store new interrupt active count + DMB ; Ensure that accesses to shared resource have completed +; +; /* Release protection. */ +; + MOV r0, r4 ; Pass the previous status register back + BL _tx_thread_smp_unprotect ; Release protection + + LDMIA sp!, {lr, r4} ; Recover lr register and r4 + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +;} + END + diff --git a/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/.cproject b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/.cproject new file mode 100644 index 00000000..73882e52 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/.cproject @@ -0,0 +1,76 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/.project b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/.project new file mode 100644 index 00000000..a1b15572 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/.project @@ -0,0 +1,26 @@ + + + sample_threadx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/.settings/language.settings.xml b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/.settings/language.settings.xml new file mode 100644 index 00000000..24bf8d9c --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/.settings/language.settings.xml @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/GICv3.h b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/GICv3.h new file mode 100644 index 00000000..b04cd97b --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/GICv3.h @@ -0,0 +1,561 @@ +/* + * GICv3.h - data types and function prototypes for GICv3 utility routines + * + * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. + * Use, modification and redistribution of this file is subject to your + * possession of a valid DS-5 end user licence agreement and your compliance + * with all applicable terms and conditions of such licence agreement. + */ +#ifndef GICV3_h +#define GICV3_h + +#include + +/* + * extra flags for GICD enable + */ +typedef enum +{ + gicdctlr_EnableGrp0 = (1 << 0), + gicdctlr_EnableGrp1NS = (1 << 1), + gicdctlr_EnableGrp1A = (1 << 1), + gicdctlr_EnableGrp1S = (1 << 2), + gicdctlr_EnableAll = (1 << 2) | (1 << 1) | (1 << 0), + gicdctlr_ARE_S = (1 << 4), /* Enable Secure state affinity routing */ + gicdctlr_ARE_NS = (1 << 5), /* Enable Non-Secure state affinity routing */ + gicdctlr_DS = (1 << 6), /* Disable Security support */ + gicdctlr_E1NWF = (1 << 7) /* Enable "1-of-N" wakeup model */ +} GICDCTLRFlags_t; + +/* + * modes for SPI routing + */ +typedef enum +{ + gicdirouter_ModeSpecific = 0, + gicdirouter_ModeAny = (1 << 31) +} GICDIROUTERBits_t; + +typedef enum +{ + gicdicfgr_Level = 0, + gicdicfgr_Edge = (1 << 1) +} GICDICFGRBits_t; + +typedef enum +{ + gicigroupr_G0S = 0, + gicigroupr_G1NS = (1 << 0), + gicigroupr_G1S = (1 << 2) +} GICIGROUPRBits_t; + +typedef enum +{ + gicrwaker_ProcessorSleep = (1 << 1), + gicrwaker_ChildrenAsleep = (1 << 2) +} GICRWAKERBits_t; + +/**********************************************************************/ + +/* + * Utility macros & functions + */ +#define RANGE_LIMIT(x) ((sizeof(x) / sizeof((x)[0])) - 1) + +static inline uint64_t gicv3PackAffinity(uint32_t aff3, uint32_t aff2, + uint32_t aff1, uint32_t aff0) +{ + /* + * only need to cast aff3 to get type promotion for all affinities + */ + return ((((uint64_t)aff3 & 0xff) << 32) | + ((aff2 & 0xff) << 16) | + ((aff1 & 0xff) << 8) | aff0); +} + +/**********************************************************************/ + +/* + * GIC Distributor Function Prototypes + */ + +/* + * ConfigGICD - configure GIC Distributor prior to enabling it + * + * Inputs: + * + * control - control flags + * + * Returns: + * + * + * + * NOTE: + * + * ConfigGICD() will set an absolute flags value, whereas + * {En,Dis}ableGICD() will only {set,clear} the flag bits + * passed as a parameter + */ +void ConfigGICD(GICDCTLRFlags_t flags); + +/* + * EnableGICD - top-level enable for GIC Distributor + * + * Inputs: + * + * flags - new control flags to set + * + * Returns: + * + * + * + * NOTE: + * + * ConfigGICD() will set an absolute flags value, whereas + * {En,Dis}ableGICD() will only {set,clear} the flag bits + * passed as a parameter + */ +void EnableGICD(GICDCTLRFlags_t flags); + +/* + * DisableGICD - top-level disable for GIC Distributor + * + * Inputs + * + * flags - control flags to clear + * + * Returns + * + * + * + * NOTE: + * + * ConfigGICD() will set an absolute flags value, whereas + * {En,Dis}ableGICD() will only {set,clear} the flag bits + * passed as a parameter + */ +void DisableGICD(GICDCTLRFlags_t flags); + +/* + * SyncAREinGICD - synchronise GICD Address Routing Enable bits + * + * Inputs + * + * flags - absolute flag bits to set in GIC Distributor + * + * dosync - flag whether to wait for ARE bits to match passed + * flag field (dosync = true), or whether to set absolute + * flag bits (dosync = false) + * + * Returns + * + * + * + * NOTE: + * + * This function is used to resolve a race in an MP system whereby secondary + * CPUs cannot reliably program all Redistributor registers until the + * primary CPU has enabled Address Routing. The primary CPU will call this + * function with dosync = false, while the secondaries will call it with + * dosync = true. + */ +void SyncAREinGICD(GICDCTLRFlags_t flags, uint32_t dosync); + +/* + * EnableSPI - enable a specific shared peripheral interrupt + * + * Inputs: + * + * id - which interrupt to enable + * + * Returns: + * + * + */ +void EnableSPI(uint32_t id); + +/* + * DisableSPI - disable a specific shared peripheral interrupt + * + * Inputs: + * + * id - which interrupt to disable + * + * Returns: + * + * + */ +void DisableSPI(uint32_t id); + +/* + * SetSPIPriority - configure the priority for a shared peripheral interrupt + * + * Inputs: + * + * id - interrupt identifier + * + * priority - 8-bit priority to program (see note below) + * + * Returns: + * + * + * + * Note: + * + * The GICv3 architecture makes this function sensitive to the Security + * context in terms of what effect it has on the programmed priority: no + * attempt is made to adjust for the reduced priority range available + * when making Non-Secure accesses to the GIC + */ +void SetSPIPriority(uint32_t id, uint32_t priority); + +/* + * GetSPIPriority - determine the priority for a shared peripheral interrupt + * + * Inputs: + * + * id - interrupt identifier + * + * Returns: + * + * interrupt priority in the range 0 - 0xff + */ +uint32_t GetSPIPriority(uint32_t id); + +/* + * SetSPIRoute - specify interrupt routing when gicdctlr_ARE is enabled + * + * Inputs: + * + * id - interrupt identifier + * + * affinity - prepacked "dotted quad" affinity routing. NOTE: use the + * gicv3PackAffinity() helper routine to generate this input + * + * mode - select routing mode (specific affinity, or any recipient) + * + * Returns: + * + * + */ +void SetSPIRoute(uint32_t id, uint64_t affinity, GICDIROUTERBits_t mode); + +/* + * GetSPIRoute - read ARE-enabled interrupt routing information + * + * Inputs: + * + * id - interrupt identifier + * + * Returns: + * + * routing configuration + */ +uint64_t GetSPIRoute(uint32_t id); + +/* + * SetSPITarget - configure the set of processor targets for an interrupt + * + * Inputs + * + * id - interrupt identifier + * + * target - 8-bit target bitmap + * + * Returns + * + * + */ +void SetSPITarget(uint32_t id, uint32_t target); + +/* + * GetSPITarget - read the set of processor targets for an interrupt + * + * Inputs + * + * id - interrupt identifier + * + * Returns + * + * 8-bit target bitmap + */ +uint32_t GetSPITarget(uint32_t id); + +/* + * ConfigureSPI - setup an interrupt as edge- or level-triggered + * + * Inputs + * + * id - interrupt identifier + * + * config - desired configuration + * + * Returns + * + * + */ +void ConfigureSPI(uint32_t id, GICDICFGRBits_t config); + +/* + * SetSPIPending - mark an interrupt as pending + * + * Inputs + * + * id - interrupt identifier + * + * Returns + * + * + */ +void SetSPIPending(uint32_t id); + +/* + * ClearSPIPending - mark an interrupt as not pending + * + * Inputs + * + * id - interrupt identifier + * + * Returns + * + * + */ +void ClearSPIPending(uint32_t id); + +/* + * GetSPIPending - query whether an interrupt is pending + * + * Inputs + * + * id - interrupt identifier + * + * Returns + * + * pending status + */ +uint32_t GetSPIPending(uint32_t id); + +/* + * SetSPISecurity - mark a shared peripheral interrupt as + * security + * + * Inputs + * + * id - which interrupt to mark + * + * group - the group for the interrupt + * + * Returns + * + * + */ +void SetSPISecurity(uint32_t id, GICIGROUPRBits_t group); + +/* + * SetSPISecurityBlock - mark a block of 32 shared peripheral + * interrupts as security + * + * Inputs: + * + * block - which block to mark (e.g. 1 = Ints 32-63) + * + * group - the group for the interrupts + * + * Returns: + * + * + */ +void SetSPISecurityBlock(uint32_t block, GICIGROUPRBits_t group); + +/* + * SetSPISecurityAll - mark all shared peripheral interrupts + * as security + * + * Inputs: + * + * group - the group for the interrupts + * + * Returns: + * + * + */ +void SetSPISecurityAll(GICIGROUPRBits_t group); + +/**********************************************************************/ + +/* + * GIC Re-Distributor Function Prototypes + * + * The model for calling Redistributor functions is that, rather than + * identifying the target redistributor with every function call, the + * SelectRedistributor() function is used to identify which redistributor + * is to be used for all functions until a different redistributor is + * explicitly selected + */ + +/* + * WakeupGICR - wake up a Redistributor + * + * Inputs: + * + * gicr - which Redistributor to wakeup + * + * Returns: + * + * + */ +void WakeupGICR(uint32_t gicr); + +/* + * EnablePrivateInt - enable a private (SGI/PPI) interrupt + * + * Inputs: + * + * gicr - which Redistributor to program + * + * id - which interrupt to enable + * + * Returns: + * + * + */ +void EnablePrivateInt(uint32_t gicr, uint32_t id); + +/* + * DisablePrivateInt - disable a private (SGI/PPI) interrupt + * + * Inputs: + * + * gicr - which Redistributor to program + * + * id - which interrupt to disable + * + * Returns: + * + * + */ +void DisablePrivateInt(uint32_t gicr, uint32_t id); + +/* + * SetPrivateIntPriority - configure the priority for a private + * (SGI/PPI) interrupt + * + * Inputs: + * + * gicr - which Redistributor to program + * + * id - interrupt identifier + * + * priority - 8-bit priority to program (see note below) + * + * Returns: + * + * + * + * Note: + * + * The GICv3 architecture makes this function sensitive to the Security + * context in terms of what effect it has on the programmed priority: no + * attempt is made to adjust for the reduced priority range available + * when making Non-Secure accesses to the GIC + */ +void SetPrivateIntPriority(uint32_t gicr, uint32_t id, uint32_t priority); + +/* + * GetPrivateIntPriority - configure the priority for a private + * (SGI/PPI) interrupt + * + * Inputs: + * + * gicr - which Redistributor to program + * + * id - interrupt identifier + * + * Returns: + * + * Int priority + */ +uint32_t GetPrivateIntPriority(uint32_t gicr, uint32_t id); + +/* + * SetPrivateIntPending - mark a private (SGI/PPI) interrupt as pending + * + * Inputs + * + * gicr - which Redistributor to program + * + * id - interrupt identifier + * + * Returns + * + * + */ +void SetPrivateIntPending(uint32_t gicr, uint32_t id); + +/* + * ClearPrivateIntPending - mark a private (SGI/PPI) interrupt as not pending + * + * Inputs + * + * gicr - which Redistributor to program + * + * id - interrupt identifier + * + * Returns + * + * + */ +void ClearPrivateIntPending(uint32_t gicr, uint32_t id); + +/* + * GetPrivateIntPending - query whether a private (SGI/PPI) interrupt is pending + * + * Inputs + * + * gicr - which Redistributor to program + * + * id - interrupt identifier + * + * Returns + * + * pending status + */ +uint32_t GetPrivateIntPending(uint32_t gicr, uint32_t id); + +/* + * SetPrivateIntSecurity - mark a private (SGI/PPI) interrupt as + * security + * + * Inputs + * + * gicr - which Redistributor to program + * + * id - which interrupt to mark + * + * group - the group for the interrupt + * + * Returns + * + * + */ +void SetPrivateIntSecurity(uint32_t gicr, uint32_t id, GICIGROUPRBits_t group); + +/* + * SetPrivateIntSecurityBlock - mark all 32 private (SGI/PPI) + * interrupts as security + * + * Inputs: + * + * gicr - which Redistributor to program + * + * group - the group for the interrupt + * + * Returns: + * + * + */ +void SetPrivateIntSecurityBlock(uint32_t gicr, GICIGROUPRBits_t group); + +#endif /* ndef GICV3_h */ + +/* EOF GICv3.h */ diff --git a/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/GICv3_gicc.h b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/GICv3_gicc.h new file mode 100644 index 00000000..bc2da074 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/GICv3_gicc.h @@ -0,0 +1,249 @@ +/* + * GICv3_gicc.h - prototypes and inline functions for GICC system register operations + * + * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. + * Use, modification and redistribution of this file is subject to your + * possession of a valid DS-5 end user licence agreement and your compliance + * with all applicable terms and conditions of such licence agreement. + */ +#ifndef GICV3_gicc_h +#define GICV3_gicc_h + +/**********************************************************************/ + +typedef enum +{ + sreSRE = (1 << 0), + sreDFB = (1 << 1), + sreDIB = (1 << 2), + sreEnable = (1 << 3) +} ICC_SREBits_t; + +static inline void setICC_SRE_EL1(ICC_SREBits_t mode) +{ + asm("msr ICC_SRE_EL1, %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline uint64_t getICC_SRE_EL1(void) +{ + uint64_t retc; + + asm("mrs %0, ICC_SRE_EL1\n" : "=r" (retc)); + + return retc; +} + +static inline void setICC_SRE_EL2(ICC_SREBits_t mode) +{ + asm("msr ICC_SRE_EL2, %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline uint64_t getICC_SRE_EL2(void) +{ + uint64_t retc; + + asm("mrs %0, ICC_SRE_EL2\n" : "=r" (retc)); + + return retc; +} + +static inline void setICC_SRE_EL3(ICC_SREBits_t mode) +{ + asm("msr ICC_SRE_EL3, %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline uint64_t getICC_SRE_EL3(void) +{ + uint64_t retc; + + asm("mrs %0, ICC_SRE_EL3\n" : "=r" (retc)); + + return retc; +} + +/**********************************************************************/ + +typedef enum +{ + igrpEnable = (1 << 0), + igrpEnableGrp1NS = (1 << 0), + igrpEnableGrp1S = (1 << 2) +} ICC_IGRPBits_t; + +static inline void setICC_IGRPEN0_EL1(ICC_IGRPBits_t mode) +{ + asm("msr ICC_IGRPEN0_EL1, %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline void setICC_IGRPEN1_EL1(ICC_IGRPBits_t mode) +{ + asm("msr ICC_IGRPEN1_EL1, %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline void setICC_IGRPEN1_EL3(ICC_IGRPBits_t mode) +{ + asm("msr ICC_IGRPEN1_EL3, %0\n; isb" :: "r" ((uint64_t)mode)); +} + +/**********************************************************************/ + +typedef enum +{ + ctlrCBPR = (1 << 0), + ctlrCBPR_EL1S = (1 << 0), + ctlrEOImode = (1 << 1), + ctlrCBPR_EL1NS = (1 << 1), + ctlrEOImode_EL3 = (1 << 2), + ctlrEOImode_EL1S = (1 << 3), + ctlrEOImode_EL1NS = (1 << 4), + ctlrRM = (1 << 5), + ctlrPMHE = (1 << 6) +} ICC_CTLRBits_t; + +static inline void setICC_CTLR_EL1(ICC_CTLRBits_t mode) +{ + asm("msr ICC_CTLR_EL1, %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline uint64_t getICC_CTLR_EL1(void) +{ + uint64_t retc; + + asm("mrs %0, ICC_CTLR_EL1\n" : "=r" (retc)); + + return retc; +} + +static inline void setICC_CTLR_EL3(ICC_CTLRBits_t mode) +{ + asm("msr ICC_CTLR_EL3, %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline uint64_t getICC_CTLR_EL3(void) +{ + uint64_t retc; + + asm("mrs %0, ICC_CTLR_EL3\n" : "=r" (retc)); + + return retc; +} + +/**********************************************************************/ + +static inline uint64_t getICC_IAR0(void) +{ + uint64_t retc; + + asm("mrs %0, ICC_IAR0_EL1\n" : "=r" (retc)); + + return retc; +} + +static inline uint64_t getICC_IAR1(void) +{ + uint64_t retc; + + asm("mrs %0, ICC_IAR1_EL1\n" : "=r" (retc)); + + return retc; +} + +static inline void setICC_EOIR0(uint32_t interrupt) +{ + asm("msr ICC_EOIR0_EL1, %0\n; isb" :: "r" ((uint64_t)interrupt)); +} + +static inline void setICC_EOIR1(uint32_t interrupt) +{ + asm("msr ICC_EOIR1_EL1, %0\n; isb" :: "r" ((uint64_t)interrupt)); +} + +static inline void setICC_DIR(uint32_t interrupt) +{ + asm("msr ICC_DIR_EL1, %0\n; isb" :: "r" ((uint64_t)interrupt)); +} + +static inline void setICC_PMR(uint32_t priority) +{ + asm("msr ICC_PMR_EL1, %0\n; isb" :: "r" ((uint64_t)priority)); +} + +static inline void setICC_BPR0(uint32_t binarypoint) +{ + asm("msr ICC_BPR0_EL1, %0\n; isb" :: "r" ((uint64_t)binarypoint)); +} + +static inline void setICC_BPR1(uint32_t binarypoint) +{ + asm("msr ICC_BPR1_EL1, %0\n; isb" :: "r" ((uint64_t)binarypoint)); +} + +static inline uint64_t getICC_BPR0(void) +{ + uint64_t retc; + + asm("mrs %0, ICC_BPR0_EL1\n" : "=r" (retc)); + + return retc; +} + +static inline uint64_t getICC_BPR1(void) +{ + uint64_t retc; + + asm("mrs %0, ICC_BPR1_EL1\n" : "=r" (retc)); + + return retc; +} + +static inline uint64_t getICC_RPR(void) +{ + uint64_t retc; + + asm("mrs %0, ICC_RPR_EL1\n" : "=r" (retc)); + + return retc; +} + +/**********************************************************************/ + +typedef enum +{ + sgirIRMTarget = 0, + sgirIRMAll = (1ull << 40) +} ICC_SGIRBits_t; + +static inline void setICC_SGI0R(uint8_t aff3, uint8_t aff2, + uint8_t aff1, ICC_SGIRBits_t irm, + uint16_t targetlist, uint8_t intid) +{ + uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \ + ((uint64_t)aff1 << 16) | irm | targetlist | \ + ((uint64_t)(intid & 0x0f) << 24)); + + asm("msr ICC_SGI0R_EL1, %0\n; isb" :: "r" (packedbits)); +} + +static inline void setICC_SGI1R(uint8_t aff3, uint8_t aff2, + uint8_t aff1, ICC_SGIRBits_t irm, + uint16_t targetlist, uint8_t intid) +{ + uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \ + ((uint64_t)aff1 << 16) | irm | targetlist | \ + ((uint64_t)(intid & 0x0f) << 24)); + + asm("msr ICC_SGI1R_EL1, %0\n; isb" :: "r" (packedbits)); +} + +static inline void setICC_ASGI1R(uint8_t aff3, uint8_t aff2, + uint8_t aff1, ICC_SGIRBits_t irm, + uint16_t targetlist, uint8_t intid) +{ + uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \ + ((uint64_t)aff1 << 16) | irm | targetlist | \ + ((uint64_t)(intid & 0x0f) << 24)); + + asm("msr ICC_ASGI1R_EL1, %0\n; isb" :: "r" (packedbits)); +} + +#endif /* ndef GICV3_gicc_h */ diff --git a/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/GICv3_gicd.c b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/GICv3_gicd.c new file mode 100644 index 00000000..e176b206 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/GICv3_gicd.c @@ -0,0 +1,339 @@ +/* + * GICv3_gicd.c - generic driver code for GICv3 distributor + * + * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. + * Use, modification and redistribution of this file is subject to your + * possession of a valid DS-5 end user licence agreement and your compliance + * with all applicable terms and conditions of such licence agreement. + */ +#include + +#include "GICv3.h" + +typedef struct +{ + volatile uint32_t GICD_CTLR; // +0x0000 + const volatile uint32_t GICD_TYPER; // +0x0004 + const volatile uint32_t GICD_IIDR; // +0x0008 + + const volatile uint32_t padding0; // +0x000c + + volatile uint32_t GICD_STATUSR; // +0x0010 + + const volatile uint32_t padding1[3]; // +0x0014 + + volatile uint32_t IMP_DEF[8]; // +0x0020 + + volatile uint32_t GICD_SETSPI_NSR; // +0x0040 + const volatile uint32_t padding2; // +0x0044 + volatile uint32_t GICD_CLRSPI_NSR; // +0x0048 + const volatile uint32_t padding3; // +0x004c + volatile uint32_t GICD_SETSPI_SR; // +0x0050 + const volatile uint32_t padding4; // +0x0054 + volatile uint32_t GICD_CLRSPI_SR; // +0x0058 + + const volatile uint32_t padding5[3]; // +0x005c + + volatile uint32_t GICD_SEIR; // +0x0068 + + const volatile uint32_t padding6[5]; // +0x006c + + volatile uint32_t GICD_IGROUPR[32]; // +0x0080 + + volatile uint32_t GICD_ISENABLER[32]; // +0x0100 + volatile uint32_t GICD_ICENABLER[32]; // +0x0180 + volatile uint32_t GICD_ISPENDR[32]; // +0x0200 + volatile uint32_t GICD_ICPENDR[32]; // +0x0280 + volatile uint32_t GICD_ISACTIVER[32]; // +0x0300 + volatile uint32_t GICD_ICACTIVER[32]; // +0x0380 + + volatile uint8_t GICD_IPRIORITYR[1024]; // +0x0400 + volatile uint8_t GICD_ITARGETSR[1024]; // +0x0800 + volatile uint32_t GICD_ICFGR[64]; // +0x0c00 + volatile uint32_t GICD_IGRPMODR[32]; // +0x0d00 + const volatile uint32_t padding7[32]; // +0x0d80 + volatile uint32_t GICD_NSACR[64]; // +0x0e00 + + volatile uint32_t GICD_SGIR; // +0x0f00 + + const volatile uint32_t padding8[3]; // +0x0f04 + + volatile uint32_t GICD_CPENDSGIR[4]; // +0x0f10 + volatile uint32_t GICD_SPENDSGIR[4]; // +0x0f20 + + const volatile uint32_t padding9[52]; // +0x0f30 + const volatile uint32_t padding10[5120]; // +0x1000 + + volatile uint64_t GICD_IROUTER[1024]; // +0x6000 +} GICv3_distributor; + +/* + * use the scatter file to place GICD + */ +static GICv3_distributor __attribute__((section(".bss.distributor"))) gicd; + +void ConfigGICD(GICDCTLRFlags_t flags) +{ + gicd.GICD_CTLR = flags; +} + +void EnableGICD(GICDCTLRFlags_t flags) +{ + gicd.GICD_CTLR |= flags; +} + +void DisableGICD(GICDCTLRFlags_t flags) +{ + gicd.GICD_CTLR &= ~flags; +} + +void SyncAREinGICD(GICDCTLRFlags_t flags, uint32_t dosync) +{ + if (dosync) + { + const uint32_t tmask = gicdctlr_ARE_S | gicdctlr_ARE_NS; + const uint32_t tval = flags & tmask; + + while ((gicd.GICD_CTLR & tmask) != tval) + continue; + } + else + gicd.GICD_CTLR = flags; +} + +void EnableSPI(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_ISENABLER has 32 interrupts per register + */ + bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); + id &= 32 - 1; + + gicd.GICD_ISENABLER[bank] = 1 << id; + + return; +} + +void DisableSPI(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_ISENABLER has 32 interrupts per register + */ + bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); + id &= 32 - 1; + + gicd.GICD_ICENABLER[bank] = 1 << id; + + return; +} + +void SetSPIPriority(uint32_t id, uint32_t priority) +{ + uint32_t bank; + + /* + * GICD_IPRIORITYR has one byte-wide entry per interrupt + */ + bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR); + + gicd.GICD_IPRIORITYR[bank] = priority; +} + +uint32_t GetSPIPriority(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_IPRIORITYR has one byte-wide entry per interrupt + */ + bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR); + + return (uint32_t)(gicd.GICD_IPRIORITYR[bank]); +} + +void SetSPIRoute(uint32_t id, uint64_t affinity, GICDIROUTERBits_t mode) +{ + uint32_t bank; + + /* + * GICD_IROUTER has one doubleword-wide entry per interrupt + */ + bank = id & RANGE_LIMIT(gicd.GICD_IROUTER); + + gicd.GICD_IROUTER[bank] = affinity | (uint64_t)mode; +} + +uint64_t GetSPIRoute(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_IROUTER has one doubleword-wide entry per interrupt + */ + bank = id & RANGE_LIMIT(gicd.GICD_IROUTER); + + return gicd.GICD_IROUTER[bank]; +} + +void SetSPITarget(uint32_t id, uint32_t target) +{ + uint32_t bank; + + /* + * GICD_ITARGETSR has one byte-wide entry per interrupt + */ + bank = id & RANGE_LIMIT(gicd.GICD_ITARGETSR); + + gicd.GICD_ITARGETSR[bank] = target; +} + +uint32_t GetSPITarget(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_ITARGETSR has one byte-wide entry per interrupt + */ + /* + * GICD_ITARGETSR has 4 interrupts per register, i.e. 8-bits of + * target bitmap per register + */ + bank = id & RANGE_LIMIT(gicd.GICD_ITARGETSR); + + return (uint32_t)(gicd.GICD_ITARGETSR[bank]); +} + +void ConfigureSPI(uint32_t id, GICDICFGRBits_t config) +{ + uint32_t bank, tmp; + + /* + * GICD_ICFGR has 16 interrupts per register, i.e. 2-bits of + * configuration per register + */ + bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); + config &= 3; + + id = (id & 0xf) << 1; + + tmp = gicd.GICD_ICFGR[bank]; + tmp &= ~(3 << id); + tmp |= config << id; + gicd.GICD_ICFGR[bank] = tmp; +} + +void SetSPIPending(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_ISPENDR has 32 interrupts per register + */ + bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISPENDR); + id &= 0x1f; + + gicd.GICD_ISPENDR[bank] = 1 << id; +} + +void ClearSPIPending(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_ICPENDR has 32 interrupts per register + */ + bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICPENDR); + id &= 0x1f; + + gicd.GICD_ICPENDR[bank] = 1 << id; +} + +uint32_t GetSPIPending(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_ICPENDR has 32 interrupts per register + */ + bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICPENDR); + id &= 0x1f; + + return (gicd.GICD_ICPENDR[bank] >> id) & 1; +} + +void SetSPISecurity(uint32_t id, GICIGROUPRBits_t group) +{ + uint32_t bank, groupmod; + + /* + * GICD_IGROUPR has 32 interrupts per register + */ + bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_IGROUPR); + id &= 0x1f; + + /* + * the single group argument is split into two separate + * registers, so filter out and remove the (new to gicv3) + * group modifier bit + */ + groupmod = (group >> 1) & 1; + group &= 1; + + /* + * either set or clear the Group bit for the interrupt as appropriate + */ + if (group) + gicd.GICD_IGROUPR[bank] |= 1 << id; + else + gicd.GICD_IGROUPR[bank] &= ~(1 << id); + + /* + * now deal with groupmod + */ + if (groupmod) + gicd.GICD_IGRPMODR[bank] |= 1 << id; + else + gicd.GICD_IGRPMODR[bank] &= ~(1 << id); +} + +void SetSPISecurityBlock(uint32_t block, GICIGROUPRBits_t group) +{ + uint32_t groupmod; + const uint32_t nbits = (sizeof group * 8) - 1; + + /* + * GICD_IGROUPR has 32 interrupts per register + */ + block &= RANGE_LIMIT(gicd.GICD_IGROUPR); + + /* + * get each bit of group config duplicated over all 32-bits in a word + */ + groupmod = (uint32_t)(((int32_t)group << (nbits - 1)) >> 31); + group = (uint32_t)(((int32_t)group << nbits) >> 31); + + /* + * set the security state for this block of SPIs + */ + gicd.GICD_IGROUPR[block] = group; + gicd.GICD_IGRPMODR[block] = groupmod; +} + +void SetSPISecurityAll(GICIGROUPRBits_t group) +{ + uint32_t block; + + /* + * GICD_TYPER.ITLinesNumber gives (No. SPIS / 32) - 1, and we + * want to iterate over all blocks excluding 0 (which are the + * SGI/PPI interrupts, and not relevant here) + */ + for (block = (gicd.GICD_TYPER & ((1 << 5) - 1)); block > 0; --block) + SetSPISecurityBlock(block, group); +} + +/* EOF GICv3_gicd.c */ diff --git a/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/GICv3_gicr.c b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/GICv3_gicr.c new file mode 100644 index 00000000..59ed616a --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/GICv3_gicr.c @@ -0,0 +1,279 @@ +/* + * GICv3_gicr.c - generic driver code for GICv3 redistributor + * + * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. + * Use, modification and redistribution of this file is subject to your + * possession of a valid DS-5 end user licence agreement and your compliance + * with all applicable terms and conditions of such licence agreement. + */ +#include "GICv3.h" + +/* + * physical LPI Redistributor register map + */ +typedef struct +{ + volatile uint32_t GICR_CTLR; // +0x0000 - RW - Redistributor Control Register + const volatile uint32_t GICR_IIDR; // +0x0004 - RO - Implementer Identification Register + const volatile uint32_t GICR_TYPER[2]; // +0x0008 - RO - Redistributor Type Register + volatile uint32_t GICR_STATUSR; // +0x0010 - RW - Error Reporting Status Register, optional + volatile uint32_t GICR_WAKER; // +0x0014 - RW - Redistributor Wake Register + const volatile uint32_t padding1[2]; // +0x0018 - RESERVED + volatile uint32_t IMPDEF1 ; // +0x0020 - ?? - IMPLEMENTATION DEFINED + const volatile uint32_t padding2[7]; // +0x0024 - RESERVED + volatile uint64_t GICR_SETLPIR; // +0x0040 - WO - Set LPI Pending Register + volatile uint64_t GICR_CLRLPIR; // +0x0048 - WO - Clear LPI Pending Register + const volatile uint32_t padding3[8]; // +0x0050 - RESERVED + volatile uint64_t GICR_PROPBASER; // +0x0070 - RW - Redistributor Properties Base Address Register + volatile uint64_t GICR_PENDBASER; // +0x0078 - RW - Redistributor LPI Pending Table Base Address Register + const volatile uint32_t padding4[8]; // +0x0080 - RESERVED + volatile uint64_t GICR_INVLPIR; // +0x00A0 - WO - Redistributor Invalidate LPI Register + const volatile uint32_t padding5[2]; // +0x00A8 - RESERVED + volatile uint64_t GICR_INVALLR; // +0x00B0 - WO - Redistributor Invalidate All Register + const volatile uint32_t padding6[2]; // +0x00B8 - RESERVED + volatile uint64_t GICR_SYNCR; // +0x00C0 - RO - Redistributor Synchronize Register + const volatile uint32_t padding7[2]; // +0x00C8 - RESERVED + const volatile uint32_t padding8[12]; // +0x00D0 - RESERVED + volatile uint64_t IMPDEF2; // +0x0100 - WO - IMPLEMENTATION DEFINED + const volatile uint32_t padding9[2]; // +0x0108 - RESERVED + volatile uint64_t IMPDEF3; // +0x0110 - WO - IMPLEMENTATION DEFINED + const volatile uint32_t padding10[2]; // +0x0118 - RESERVED +} GICv3_redistributor_RD; + +/* + * SGI and PPI Redistributor register map + */ +typedef struct +{ + const volatile uint32_t padding1[32]; // +0x0000 - RESERVED + volatile uint32_t GICR_IGROUPR0; // +0x0080 - RW - Interrupt Group Registers (Security Registers in GICv1) + const volatile uint32_t padding2[31]; // +0x0084 - RESERVED + volatile uint32_t GICR_ISENABLER; // +0x0100 - RW - Interrupt Set-Enable Registers + const volatile uint32_t padding3[31]; // +0x0104 - RESERVED + volatile uint32_t GICR_ICENABLER; // +0x0180 - RW - Interrupt Clear-Enable Registers + const volatile uint32_t padding4[31]; // +0x0184 - RESERVED + volatile uint32_t GICR_ISPENDR; // +0x0200 - RW - Interrupt Set-Pending Registers + const volatile uint32_t padding5[31]; // +0x0204 - RESERVED + volatile uint32_t GICR_ICPENDR; // +0x0280 - RW - Interrupt Clear-Pending Registers + const volatile uint32_t padding6[31]; // +0x0284 - RESERVED + volatile uint32_t GICR_ISACTIVER; // +0x0300 - RW - Interrupt Set-Active Register + const volatile uint32_t padding7[31]; // +0x0304 - RESERVED + volatile uint32_t GICR_ICACTIVER; // +0x0380 - RW - Interrupt Clear-Active Register + const volatile uint32_t padding8[31]; // +0x0184 - RESERVED + volatile uint8_t GICR_IPRIORITYR[32]; // +0x0400 - RW - Interrupt Priority Registers + const volatile uint32_t padding9[504]; // +0x0420 - RESERVED + volatile uint32_t GICR_ICnoFGR[2]; // +0x0C00 - RW - Interrupt Configuration Registers + const volatile uint32_t padding10[62]; // +0x0C08 - RESERVED + volatile uint32_t GICR_IGRPMODR0; // +0x0D00 - RW - ???? + const volatile uint32_t padding11[63]; // +0x0D04 - RESERVED + volatile uint32_t GICR_NSACR; // +0x0E00 - RW - Non-Secure Access Control Register +} GICv3_redistributor_SGI; + +/* + * We have a multiplicity of GIC Redistributors; on the GIC-AEM and + * GIC-500 they are arranged as one 128KB region per redistributor: one + * 64KB page of GICR LPI registers, and one 64KB page of GICR Private + * Int registers + */ +typedef struct +{ + union + { + GICv3_redistributor_RD RD_base; + uint8_t padding[64 * 1024]; + } RDblock; + + union + { + GICv3_redistributor_SGI SGI_base; + uint8_t padding[64 * 1024]; + } SGIblock; +} GICv3_GICR; + +/* + * use the scatter file to place GIC Redistributor base address + * + * although this code doesn't know how many Redistributor banks + * a particular system will have, we declare gicrbase as an array + * to avoid unwanted compiler optimisations when calculating the + * base of a particular Redistributor bank + */ +static const GICv3_GICR gicrbase[2] __attribute__((section (".bss.redistributor"))); + +/**********************************************************************/ + +/* + * utility functions to calculate base of a particular + * Redistributor bank + */ + +static inline GICv3_redistributor_RD *const getgicrRD(uint32_t gicr) +{ + GICv3_GICR *const arraybase = (GICv3_GICR *const)&gicrbase; + + return &((arraybase + gicr)->RDblock.RD_base); +} + +static inline GICv3_redistributor_SGI *const getgicrSGI(uint32_t gicr) +{ + GICv3_GICR *arraybase = (GICv3_GICR *)(&gicrbase); + + return &(arraybase[gicr].SGIblock.SGI_base); +} + +/**********************************************************************/ + +void WakeupGICR(uint32_t gicr) +{ + GICv3_redistributor_RD *const gicrRD = getgicrRD(gicr); + + /* + * step 1 - ensure GICR_WAKER.ProcessorSleep is off + */ + gicrRD->GICR_WAKER &= ~gicrwaker_ProcessorSleep; + + /* + * step 2 - wait for children asleep to be cleared + */ + while ((gicrRD->GICR_WAKER & gicrwaker_ChildrenAsleep) != 0) + continue; + + /* + * OK, GICR is go + */ + return; +} + +void EnablePrivateInt(uint32_t gicr, uint32_t id) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + id &= 0x1f; + + gicrSGI->GICR_ISENABLER = 1 << id; +} + +void DisablePrivateInt(uint32_t gicr, uint32_t id) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + id &= 0x1f; + + gicrSGI->GICR_ICENABLER = 1 << id; +} + +void SetPrivateIntPriority(uint32_t gicr, uint32_t id, uint32_t priority) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + /* + * GICD_IPRIORITYR has one byte-wide entry per interrupt + */ + id &= RANGE_LIMIT(gicrSGI->GICR_IPRIORITYR); + + gicrSGI->GICR_IPRIORITYR[id] = priority; +} + +uint32_t GetPrivateIntPriority(uint32_t gicr, uint32_t id) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + /* + * GICD_IPRIORITYR has one byte-wide entry per interrupt + */ + id &= RANGE_LIMIT(gicrSGI->GICR_IPRIORITYR); + + return (uint32_t)(gicrSGI->GICR_IPRIORITYR[id]); +} + +void SetPrivateIntPending(uint32_t gicr, uint32_t id) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + /* + * GICR_ISPENDR is one 32-bit register + */ + id &= 0x1f; + + gicrSGI->GICR_ISPENDR = 1 << id; +} + +void ClearPrivateIntPending(uint32_t gicr, uint32_t id) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + /* + * GICR_ICPENDR is one 32-bit register + */ + id &= 0x1f; + + gicrSGI->GICR_ICPENDR = 1 << id; +} + +uint32_t GetPrivateIntPending(uint32_t gicr, uint32_t id) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + /* + * GICR_ISPENDR is one 32-bit register + */ + id &= 0x1f; + + return (gicrSGI->GICR_ISPENDR >> id) & 0x01; +} + +void SetPrivateIntSecurity(uint32_t gicr, uint32_t id, GICIGROUPRBits_t group) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + uint32_t groupmod; + + /* + * GICR_IGROUPR0 is one 32-bit register + */ + id &= 0x1f; + + /* + * the single group argument is split into two separate + * registers, so filter out and remove the (new to gicv3) + * group modifier bit + */ + groupmod = (group >> 1) & 1; + group &= 1; + + /* + * either set or clear the Group bit for the interrupt as appropriate + */ + if (group) + gicrSGI->GICR_IGROUPR0 |= 1 << id; + else + gicrSGI->GICR_IGROUPR0 &= ~(1 << id); + + /* + * now deal with groupmod + */ + if (groupmod) + gicrSGI->GICR_IGRPMODR0 |= 1 << id; + else + gicrSGI->GICR_IGRPMODR0 &= ~(1 << id); +} + +void SetPrivateIntSecurityBlock(uint32_t gicr, GICIGROUPRBits_t group) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + const uint32_t nbits = (sizeof group * 8) - 1; + uint32_t groupmod; + + /* + * get each bit of group config duplicated over all 32-bits + */ + groupmod = (uint32_t)(((int32_t)group << (nbits - 1)) >> 31); + group = (uint32_t)(((int32_t)group << nbits) >> 31); + + /* + * set the security state for this block of SPIs + */ + gicrSGI->GICR_IGROUPR0 = group; + gicrSGI->GICR_IGRPMODR0 = groupmod; +} + +/* EOF GICv3_gicr.c */ diff --git a/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/MP_Mutexes.S b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/MP_Mutexes.S new file mode 100644 index 00000000..d5dfd898 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/MP_Mutexes.S @@ -0,0 +1,86 @@ +// +// Armv8-A AArch64 - Basic Mutex Example +// +// Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your +// possession of a valid DS-5 end user licence agreement and your compliance +// with all applicable terms and conditions of such licence agreement. +// + + + .text + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + + + .global _mutex_initialize + .global _mutex_acquire + .global _mutex_release + +// +// These routines implement the mutex management functions required for running +// the Arm C library in a multi-threaded environment. +// +// They use a value of 0 to represent an unlocked mutex, and 1 for a locked mutex +// +// ********************************************************************** +// + + .type _mutex_initialize, "function" + .cfi_startproc +_mutex_initialize: + + // + // mark the mutex as unlocked + // + mov w1, #0 + str w1, [x0] + + // + // we are running multi-threaded, so set a non-zero return + // value (function prototype says use 1) + // + mov w0, #1 + ret + .cfi_endproc + + + .type _mutex_acquire, "function" + .cfi_startproc +_mutex_acquire: + + // + // send ourselves an event, so we don't stick on the wfe at the + // top of the loop + // + sevl + + // + // wait until the mutex is available + // +loop: + wfe + ldaxr w1, [x0] + cbnz w1, loop + + // + // mutex is (at least, it was) available - try to claim it + // + mov w1, #1 + stxr w2, w1, [x0] + cbnz w2, loop + + // + // OK, we have the mutex, our work is done here + // + ret + .cfi_endproc + + + .type _mutex_release, "function" + .cfi_startproc +_mutex_release: + + mov w1, #0 + stlr w1, [x0] + ret + .cfi_endproc diff --git a/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/PPM_AEM.h b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/PPM_AEM.h new file mode 100644 index 00000000..da19e9b1 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/PPM_AEM.h @@ -0,0 +1,66 @@ +// +// Private Peripheral Map for the v8 Architecture Envelope Model +// +// Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your +// possession of a valid DS-5 end user licence agreement and your compliance +// with all applicable terms and conditions of such licence agreement. +// + +#ifndef PPM_AEM_H +#define PPM_AEM_H + +// +// Distributor layout +// +#define GICD_CTLR 0x0000 +#define GICD_TYPER 0x0004 +#define GICD_IIDR 0x0008 +#define GICD_IGROUP 0x0080 +#define GICD_ISENABLE 0x0100 +#define GICD_ICENABLE 0x0180 +#define GICD_ISPEND 0x0200 +#define GICD_ICPEND 0x0280 +#define GICD_ISACTIVE 0x0300 +#define GICD_ICACTIVE 0x0380 +#define GICD_IPRIORITY 0x0400 +#define GICD_ITARGETS 0x0800 +#define GICD_ICFG 0x0c00 +#define GICD_PPISR 0x0d00 +#define GICD_SPISR 0x0d04 +#define GICD_SGIR 0x0f00 +#define GICD_CPENDSGI 0x0f10 +#define GICD_SPENDSGI 0x0f20 +#define GICD_PIDR4 0x0fd0 +#define GICD_PIDR5 0x0fd4 +#define GICD_PIDR6 0x0fd8 +#define GICD_PIDR7 0x0fdc +#define GICD_PIDR0 0x0fe0 +#define GICD_PIDR1 0x0fe4 +#define GICD_PIDR2 0x0fe8 +#define GICD_PIDR3 0x0fec +#define GICD_CIDR0 0x0ff0 +#define GICD_CIDR1 0x0ff4 +#define GICD_CIDR2 0x0ff8 +#define GICD_CIDR3 0x0ffc + +// +// CPU Interface layout +// +#define GICC_CTLR 0x0000 +#define GICC_PMR 0x0004 +#define GICC_BPR 0x0008 +#define GICC_IAR 0x000c +#define GICC_EOIR 0x0010 +#define GICC_RPR 0x0014 +#define GICC_HPPIR 0x0018 +#define GICC_ABPR 0x001c +#define GICC_AIAR 0x0020 +#define GICC_AEOIR 0x0024 +#define GICC_AHPPIR 0x0028 +#define GICC_APR0 0x00d0 +#define GICC_NSAPR0 0x00e0 +#define GICC_IIDR 0x00fc +#define GICC_DIR 0x1000 + +#endif // PPM_AEM_H diff --git a/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/sample_threadx.c new file mode 100644 index 00000000..eea35faa --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/sample_threadx.c @@ -0,0 +1,389 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" +#include + +extern void init_timer(void); /* in timer_interrupts.c */ + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 0x20000 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define a memory area to create a byte pool in. */ + +UCHAR memory_area[DEMO_BYTE_POOL_SIZE] __attribute__((aligned (8))); + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_TIMER timer_0; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +#ifdef TX_ENABLE_EVENT_TRACE + +UCHAR event_buffer[65536]; + +#endif + + +int main(void) +{ + + /* Initialize timer. */ + init_timer(); + + /* Enter ThreadX. */ + tx_kernel_enter(); + + return 0; +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + +#ifdef TX_ENABLE_EVENT_TRACE + + tx_trace_enable(event_buffer, sizeof(event_buffer), 32); +#endif + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEMO_BYTE_POOL_SIZE); + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + diff --git a/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/sample_threadx.launch b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/sample_threadx.launch new file mode 100644 index 00000000..b5ca0dbf --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/sample_threadx.launch @@ -0,0 +1,398 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/sample_threadx.sct b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/sample_threadx.sct new file mode 100644 index 00000000..1288a328 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/sample_threadx.sct @@ -0,0 +1,262 @@ +;******************************************************** +; Scatter file for Armv8-A Startup code on FVP Base model +; Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. +; Use, modification and redistribution of this file is subject to your +; possession of a valid DS-5 end user licence agreement and your compliance +; with all applicable terms and conditions of such licence agreement. +;******************************************************** + +LOAD 0x80000000 +{ + EXEC +0 + { + startup.o (StartUp, +FIRST) + * (+RO, +RW, +ZI) + + } + ;XTABLES +0 ALIGN 0x1000 + ;{ + ; xtables.o (*) + ;} + + SYS_STACK +0 ALIGN 8 EMPTY 0x1000 + { + } + + ; + ; Separate heap - import symbol __use_two_region_memory + ; in source code for this to work correctly + ; + ARM_LIB_HEAP +0 ALIGN 64 EMPTY 0xA0000 {} + + ; + ; App stacks for all CPUs + ; All stacks and heap are aligned to a cache-line boundary + ; + ARM_LIB_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} + + ; + ; Handler stacks for all CPUs + ; All stacks and heap are aligned to a cache-line boundary + ; + HANDLER_STACK +0 ALIGN 64 EMPTY 4 * 0x4000 {} + + ; + ; Stacks for EL3 + ; + EL3_STACKS +0 ALIGN 64 EMPTY 4 * 0x1000 {} + ; + ; Strictly speaking, the L1 tables don't need to + ; be so strongly aligned, but no matter + ; + TTB0_L1 +0 ALIGN 4096 EMPTY 0x1000 {} + + ; + ; Various sets of L2 tables + ; + ; Alignment is 4KB, since the code uses a 4K page + ; granularity - larger granularities would require + ; correspondingly stricter alignment + ; + TTB0_L2_RAM +0 ALIGN 4096 EMPTY 0x1000 {} + + TTB0_L2_PRIVATE +0 ALIGN 4096 EMPTY 0x1000 {} + + TTB0_L2_PERIPH +0 ALIGN 4096 EMPTY 0x1000 {} + + ; + ; The startup code uses the end of this region to calculate + ; the top of memory - don't place any RAM regions after it + ; + TOP_OF_RAM +0 EMPTY 4 {} + + ; + ; CS3 Peripherals is a 64MB region from 0x1c000000 + ; that includes the following: + ; System Registers at 0x1C010000 + ; UART0 (PL011) at 0x1C090000 + ; Color LCD Controller (PL111) at 0x1C1F0000 + ; plus a number of others. + ; CS3_PERIPHERALS is used by the startup code for page-table generation + ; This region is not truly empty, but we have no + ; predefined objects that live within it + ; + CS3_PERIPHERALS 0x1c000000 EMPTY 0x90000 {} + + ; + ; Place the UART peripheral registers data structure + ; This is only really needed if USE_SERIAL_PORT is defined, but + ; the linker will remove unused sections if not needed +; PL011 0x1c090000 UNINIT 0x1000 +; { +; uart.o (+ZI) +; } + ; Note that some other CS3_PERIPHERALS follow this + + ; + ; GICv3 distributor + ; + GICD 0x2f000000 UNINIT 0x8000 + { + GICv3_gicd.o (.bss.distributor) + } + + ; + ; GICv3 redistributors + ; 128KB for each redistributor in the system + ; + GICR 0x2f100000 UNINIT 0x80000 + { + GICv3_gicr.o (.bss.redistributor) + } +} + + + + + +; Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; Redistributions of source code must retain the above copyright notice, this +; list of conditions and the following disclaimer. +; +; Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; +; Neither the name of ARM nor the names of its contributors may be used +; to endorse or promote products derived from this software without specific +; prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. + +;RO AlignExpr(0x80000000, 0x1000) +;{ +; C_SYNCH_SP0 +0 ALIGN 0x80 +; { +; vectors.o (_c_synch_sp0) +; } +; C_IRQ_SP0 +0 ALIGN 0x80 +; { +; vectors.o (_c_irq_sp0) +; } +; C_FIQ_SP0 +0 ALIGN 0x80 +; { +; vectors.o (_c_fiq_sp0) +; } +; C_SERROR_SP0 +0 ALIGN 0x80 +; { +; vectors.o (_c_serror_sp0) +; } +; +; C_SYNCH_SPX +0 ALIGN 0x80 +; { +; vectors.o (_c_synch_spx) +; } +; C_IRQ_SPX +0 ALIGN 0x80 +; { +; vectors.o (_c_irq_spx) +; } +; C_FIQ_SPX +0 ALIGN 0x80 +; { +; vectors.o (_c_fiq_spx) +; } +; C_SERROR_SPX +0 ALIGN 0x80 +; { +; vectors.o (_c_serror_spx) +; } +; +; L64_SYNCH +0 ALIGN 0x80 +; { +; vectors.o (_l64_synch) +; } +; L64_IRQ +0 ALIGN 0x80 +; { +; vectors.o (_l64_irq) +; } +; L64_FIQ +0 ALIGN 0x80 +; { +; vectors.o (_l64_fiq) +; } +; L64_SERROR +0 ALIGN 0x80 +; { +; vectors.o (_l64_serror) +; } +; +; L32_SYNCH +0 ALIGN 0x80 +; { +; vectors.o (_l32_synch) +; } +; L32_IRQ +0 ALIGN 0x80 +; { +; vectors.o (_l32_irq) +; } +; L32_FIQ +0 ALIGN 0x80 +; { +; vectors.o (_l32_fiq) +; } +; L32_SERROR +0 ALIGN 0x80 +; { +; vectors.o (_l32_serror) +; } +; +; ROSEC +0 ALIGN 8 +; { +; *( +RO ) +; } +; +; XTABLES +0 ALIGN 0x1000 +; { +; xtables.o (*) +; } +;} +; +;RW AlignExpr(ImageLimit(XTABLES), 0x1000) +;{ +; RWSEC +0 +; { +; *( +RW ) +; } +; +; ZISEC +0 +; { +; *( +ZI ) +; } +; +; SYS_STACK +0 ALIGN 8 EMPTY 0x1000 +; { +; } +; +; ; 512 MiB heap +; HEAP +0 ALIGN 8 EMPTY 0x10000000 +; { +; } +; +; ; Free Memory section +; FREE_MEMORY +0 ALIGN 8 EMPTY 0x10000000 +; { +; } +; +; ; Per-CPU 128 MiB task stacks +; TASK_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) +; { +; } +; +; ; Per-CPU 128 MiB handler stacks +; HANDLER_STACKS +0 ALIGN 16 EMPTY (4 * 0x8000000) +; { +; } +;} diff --git a/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/sp804_timer.c b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/sp804_timer.c new file mode 100644 index 00000000..4a454f16 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/sp804_timer.c @@ -0,0 +1,122 @@ +// ------------------------------------------------------------ +// SP804 Dual Timer +// +// Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your +// possession of a valid DS-5 end user licence agreement and your compliance +// with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#include "sp804_timer.h" + +#define TIMER_SP804_CTRL_TIMEREN (1 << 7) +#define TIMER_SP804_CTRL_TIMERMODE (1 << 6) // Bit 6: +#define TIMER_SP804_CTRL_INTENABLE (1 << 5) +#define TIMER_SP804_CTRL_TIMERSIZE (1 << 1) // Bit 1: 0=16-bit, 1=32-bit +#define TIMER_SP804_CTRL_ONESHOT (1 << 0) // Bit 0: 0=wrapping, 1=one-shot + +#define TIMER_SP804_CTRL_PRESCALE_1 (0 << 2) // clk/1 +#define TIMER_SP804_CTRL_PRESCALE_4 (1 << 2) // clk/4 +#define TIMER_SP804_CTRL_PRESCALE_8 (2 << 2) // clk/8 + +struct sp804_timer +{ + volatile uint32_t Time1Load; // +0x00 + const volatile uint32_t Time1Value; // +0x04 - RO + volatile uint32_t Timer1Control; // +0x08 + volatile uint32_t Timer1IntClr; // +0x0C - WO + const volatile uint32_t Timer1RIS; // +0x10 - RO + const volatile uint32_t Timer1MIS; // +0x14 - RO + volatile uint32_t Timer1BGLoad; // +0x18 + + volatile uint32_t Time2Load; // +0x20 + volatile uint32_t Time2Value; // +0x24 + volatile uint8_t Timer2Control; // +0x28 + volatile uint32_t Timer2IntClr; // +0x2C - WO + const volatile uint32_t Timer2RIS; // +0x30 - RO + const volatile uint32_t Timer2MIS; // +0x34 - RO + volatile uint32_t Timer2BGLoad; // +0x38 + + // Not including ID registers + +}; + +// Instance of the dual timer, will be placed using the scatter file +struct sp804_timer* dual_timer; + + +// Set base address of timer +// address - virtual address of SP804 timer +void setTimerBaseAddress(uint64_t address) +{ + dual_timer = (struct sp804_timer*)address; + return; +} + + +// Sets up the private timer +// load_value - Initial value of timer +// auto_reload - Periodic (SP804_AUTORELOAD) or one shot (SP804_SINGLESHOT) +// interrupt - Whether to generate an interrupt +void initTimer(uint32_t load_value, uint32_t auto_reload, uint32_t interrupt) +{ + uint32_t tmp = 0; + + dual_timer->Time1Load = load_value; + + // Fixed setting: 32-bit, no prescaling + tmp = TIMER_SP804_CTRL_TIMERSIZE | TIMER_SP804_CTRL_PRESCALE_1 | TIMER_SP804_CTRL_TIMERMODE; + + // Settings from parameters: interrupt generation & reload + tmp = tmp | interrupt | auto_reload; + + // Write control register + dual_timer->Timer1Control = tmp; + + return; +} + + +// Starts the timer +void startTimer(void) +{ + uint32_t tmp; + + tmp = dual_timer->Timer1Control; + tmp = tmp | TIMER_SP804_CTRL_TIMEREN; // Set TimerEn (bit 7) + dual_timer->Timer1Control = tmp; + + return; +} + + +// Stops the timer +void stopTimer(void) +{ + uint32_t tmp; + + tmp = dual_timer->Timer1Control; + tmp = tmp & ~TIMER_SP804_CTRL_TIMEREN; // Clear TimerEn (bit 7) + dual_timer->Timer1Control = tmp; + + return; +} + + +// Returns the current timer count +uint32_t getTimerCount(void) +{ + return dual_timer->Time1Value; +} + + +void clearTimerIrq(void) +{ + // A write to this register, of any value, clears the interrupt + dual_timer->Timer1IntClr = 1; +} + + +// ------------------------------------------------------------ +// End of sp804_timer.c +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/sp804_timer.h b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/sp804_timer.h new file mode 100644 index 00000000..d4c6d9e2 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/sp804_timer.h @@ -0,0 +1,53 @@ +// ------------------------------------------------------------ +// SP804 Dual Timer +// Header Filer +// +// Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your +// possession of a valid DS-5 end user licence agreement and your compliance +// with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#ifndef _SP804_TIMER_ +#define _SP804_TIMER_ + +#include + +// Set base address of timer +// address - virtual address of SP804 timer +void setTimerBaseAddress(uint64_t address); + + +// Sets up the private timer +// load_value - Initial value of timer +// auto_reload - Periodic (SP804_AUTORELOAD) or one shot (SP804_SINGLESHOT) +// interrupt - Whether to generate an interrupt + +#define SP804_AUTORELOAD (0) +#define SP804_SINGLESHOT (1) +#define SP804_GENERATE_IRQ (1 << 5) +#define SP804_NO_IRQ (0) + +void initTimer(uint32_t load_value, uint32_t auto_reload, uint32_t interrupt); + + +// Starts the timer +void startTimer(void); + + +// Stops the timer +void stopTimer(void); + + +// Returns the current timer count +uint32_t getTimerCount(void); + + +// Clears the timer interrupt +void clearTimerIrq(void); + +#endif + +// ------------------------------------------------------------ +// End of sp804_timer.h +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/startup.S b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/startup.S new file mode 100644 index 00000000..eea65315 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/startup.S @@ -0,0 +1,803 @@ +// ------------------------------------------------------------ +// Armv8-A MPCore EL3 AArch64 Startup Code +// +// Basic Vectors, MMU, caches and GICv3 initialization +// +// Exits in EL1 AArch64 +// +// Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your +// possession of a valid DS-5 end user licence agreement and your compliance +// with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#include "v8_mmu.h" +#include "v8_system.h" + + + .section StartUp, "ax" + .balign 4 + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + + + .global el1_vectors + .global el2_vectors + .global el3_vectors + + .global InvalidateUDCaches + .global ZeroBlock + + .global SetPrivateIntSecurityBlock + .global SetSPISecurityAll + .global SetPrivateIntPriority + + .global WakeupGICR + .global SyncAREinGICD + .global EnableGICD + .global EnablePrivateInt + .global GetPrivateIntPending + .global ClearPrivateIntPending + + .global __main + + .global Image$$EXEC$$RO$$Base + .global Image$$TTB0_L1$$ZI$$Base + .global Image$$TTB0_L2_RAM$$ZI$$Base + .global Image$$TTB0_L2_PERIPH$$ZI$$Base + .global Image$$TOP_OF_RAM$$ZI$$Base + .global Image$$GICD$$ZI$$Base + .global Image$$ARM_LIB_STACK$$ZI$$Limit + .global Image$$EL3_STACKS$$ZI$$Limit + .global Image$$CS3_PERIPHERALS$$ZI$$Base + // use separate stack and heap, as anticipated by scatter.scat + .global __use_two_region_memory + +is_mmu_ready: +.word 0 + + +// ------------------------------------------------------------ + + .global start64 + .type start64, "function" +start64: + + // + // program the VBARs + // + ldr x1, =el1_vectors + msr VBAR_EL1, x1 + + ldr x1, =el2_vectors + msr VBAR_EL2, x1 + + ldr x1, =el3_vectors + msr VBAR_EL3, x1 + + + // GIC-500 comes out of reset in GICv2 compatibility mode - first set + // system register enables for all relevant exception levels, and + // select GICv3 operating mode + // + msr SCR_EL3, xzr // Ensure NS bit is initially clear, so secure copy of ICC_SRE_EL1 can be configured + isb + + mov x0, #15 + msr ICC_SRE_EL3, x0 + isb + msr ICC_SRE_EL1, x0 // Secure copy of ICC_SRE_EL1 + + // + // set lower exception levels as non-secure, with no access + // back to EL2 or EL3, and are AArch64 capable + // + mov x3, #(SCR_EL3_RW | \ + SCR_EL3_SMD | \ + SCR_EL3_NS) // Set NS bit, to access Non-secure registers + msr SCR_EL3, x3 + isb + + mov x0, #15 + msr ICC_SRE_EL2, x0 + isb + msr ICC_SRE_EL1, x0 // Non-secure copy of ICC_SRE_EL1 + + + // + // no traps or VM modifications from the Hypervisor, EL1 is AArch64 + // + mov x2, #HCR_EL2_RW + msr HCR_EL2, x2 + + // + // VMID is still significant, even when virtualisation is not + // being used, so ensure VTTBR_EL2 is properly initialised + // + msr VTTBR_EL2, xzr + + // + // VMPIDR_EL2 holds the value of the Virtualization Multiprocessor ID. This is the value returned by Non-secure EL1 reads of MPIDR_EL1. + // VPIDR_EL2 holds the value of the Virtualization Processor ID. This is the value returned by Non-secure EL1 reads of MIDR_EL1. + // Both of these registers are architecturally UNKNOWN at reset, and so they must be set to the correct value + // (even if EL2/virtualization is not being used), otherwise non-secure EL1 reads of MPIDR_EL1/MIDR_EL1 will return garbage values. + // This guarantees that any future reads of MPIDR_EL1 and MIDR_EL1 from Non-secure EL1 will return the correct value. + // + mrs x0, MPIDR_EL1 + msr VMPIDR_EL2, x0 + mrs x0, MIDR_EL1 + msr VPIDR_EL2, x0 + + // extract the core number from MPIDR_EL1 and store it in + // x19 (defined by the AAPCS as callee-saved), so we can re-use + // the number later + // + bl GetCPUID + mov x19, x0 + + // + // neither EL3 nor EL2 trap floating point or accesses to CPACR + // + msr CPTR_EL3, xzr + msr CPTR_EL2, xzr + + // + // SCTLR_ELx may come out of reset with UNKNOWN values so we will + // set the fields to 0 except, possibly, the endianess field(s). + // Note that setting SCTLR_EL2 or the EL0 related fields of SCTLR_EL1 + // is not strictly needed, since we're never in EL2 or EL0 + // +#ifdef __ARM_BIG_ENDIAN + mov x0, #(SCTLR_ELx_EE | SCTLR_EL1_E0E) +#else + mov x0, #0 +#endif + msr SCTLR_EL3, x0 + msr SCTLR_EL2, x0 + msr SCTLR_EL1, x0 + +#ifdef CORTEXA + // + // Configure ACTLR_EL[23] + // ---------------------- + // + // These bits are IMPLEMENTATION DEFINED, so are different for + // different processors + // + // For Cortex-A57, the controls we set are: + // + // Enable lower level access to CPUACTLR_EL1 + // Enable lower level access to CPUECTLR_EL1 + // Enable lower level access to L2CTLR_EL1 + // Enable lower level access to L2ECTLR_EL1 + // Enable lower level access to L2ACTLR_EL1 + // + mov x0, #((1 << 0) | \ + (1 << 1) | \ + (1 << 4) | \ + (1 << 5) | \ + (1 << 6)) + + msr ACTLR_EL3, x0 + msr ACTLR_EL2, x0 + + // + // configure CPUECTLR_EL1 + // + // These bits are IMP DEF, so need to different for different + // processors + // + // SMPEN - bit 6 - Enables the processor to receive cache + // and TLB maintenance operations + // + // Note: For Cortex-A57/53 SMPEN should be set before enabling + // the caches and MMU, or performing any cache and TLB + // maintenance operations. + // + // This register has a defined reset value, so we use a + // read-modify-write sequence to set SMPEN + // + mrs x0, S3_1_c15_c2_1 // Read EL1 CPU Extended Control Register + orr x0, x0, #(1 << 6) // Set the SMPEN bit + msr S3_1_c15_c2_1, x0 // Write EL1 CPU Extended Control Register + + isb +#endif + + // + // That's the last of the control settings for now + // + // Note: no ISB after all these changes, as registers won't be + // accessed until after an exception return, which is itself a + // context synchronisation event + // + + // + // Setup some EL3 stack space, ready for calling some subroutines, below. + // + // Stack space allocation is CPU-specific, so use CPU + // number already held in x19 + // + // 2^12 bytes per CPU for the EL3 stacks + // + ldr x0, =Image$$EL3_STACKS$$ZI$$Limit + sub x0, x0, x19, lsl #12 + mov sp, x0 + + // + // we need to configure the GIC while still in secure mode, specifically + // all PPIs and SPIs have to be programmed as Group1 interrupts + // + + // + // Before the GIC can be reliably programmed, we need to + // enable Affinity Routing, as this affects where the configuration + // registers are (with Affinity Routing enabled, some registers are + // in the Redistributor, whereas those same registers are in the + // Distributor with Affinity Routing disabled (i.e. when in GICv2 + // compatibility mode). + // + mov x0, #(1 << 4) | (1 << 5) // gicdctlr_ARE_S | gicdctlr_ARE_NS + mov x1, x19 + bl SyncAREinGICD + + // + // The Redistributor comes out of reset assuming the processor is + // asleep - correct that assumption + // + mov w0, w19 + bl WakeupGICR + + // + // Now we're ready to set security and other initialisations + // + // This is a per-CPU configuration for these interrupts + // + // for the first cluster, CPU number is the redistributor index + // + mov w0, w19 + mov w1, #1 // gicigroupr_G1NS + bl SetPrivateIntSecurityBlock + + // + // While we're in the Secure World, set the priority mask low enough + // for it to be writable in the Non-Secure World + // + //mov x0, #16 << 3 // 5 bits of priority in the Secure world + mov x0, #0xFF // for Non-Secure interrupts + msr ICC_PMR_EL1, x0 + + // + // there's more GIC setup to do, but only for the primary CPU + // + cbnz x19, drop_to_el1 + + // + // There's more to do to the GIC - call the utility routine to set + // all SPIs to Group1 + // + mov w0, #1 // gicigroupr_G1NS + bl SetSPISecurityAll + + // + // Set up EL1 entry point and "dummy" exception return information, + // then perform exception return to enter EL1 + // + .global drop_to_el1 +drop_to_el1: + adr x1, el1_entry_aarch64 + msr ELR_EL3, x1 + mov x1, #(AARCH64_SPSR_EL1h | \ + AARCH64_SPSR_F | \ + AARCH64_SPSR_I | \ + AARCH64_SPSR_A) + msr SPSR_EL3, x1 + eret + + + +// ------------------------------------------------------------ +// EL1 - Common start-up code +// ------------------------------------------------------------ + + .global el1_entry_aarch64 + .type el1_entry_aarch64, "function" +el1_entry_aarch64: + + // + // Now we're in EL1, setup the application stack + // the scatter file allocates 2^14 bytes per app stack + // + ldr x0, =Image$$HANDLER_STACK$$ZI$$Limit + sub x0, x0, x19, lsl #14 + mov sp, x0 + MSR SPSel, #0 + ISB + ldr x0, =Image$$ARM_LIB_STACK$$ZI$$Limit + sub x0, x0, x19, lsl #14 + mov sp, x0 + + // + // Enable floating point + // + mov x0, #CPACR_EL1_FPEN + msr CPACR_EL1, x0 + + // + // Invalidate caches and TLBs for all stage 1 + // translations used at EL1 + // + // Cortex-A processors automatically invalidate their caches on reset + // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins). + // It is therefore not necessary for software to invalidate the caches + // on startup, however, this is done here in case of a warm reset. + bl InvalidateUDCaches + tlbi VMALLE1 + + + // + // Set TTBR0 Base address + // + // The CPUs share one set of translation tables that are + // generated by CPU0 at run-time + // + // TTBR1_EL1 is not used in this example + // + ldr x1, =Image$$TTB0_L1$$ZI$$Base + msr TTBR0_EL1, x1 + + + // + // Set up memory attributes + // + // These equate to: + // + // 0 -> 0b01000100 = 0x00000044 = Normal, Inner/Outer Non-Cacheable + // 1 -> 0b11111111 = 0x0000ff00 = Normal, Inner/Outer WriteBack Read/Write Allocate + // 2 -> 0b00000100 = 0x00040000 = Device-nGnRE + // + mov x1, #0xff44 + movk x1, #4, LSL #16 // equiv to: movk x1, #0x0000000000040000 + msr MAIR_EL1, x1 + + + // + // Set up TCR_EL1 + // + // We're using only TTBR0 (EPD1 = 1), and the page table entries: + // - are using an 8-bit ASID from TTBR0 + // - have a 4K granularity (TG0 = 0b00) + // - are outer-shareable (SH0 = 0b10) + // - are using Inner & Outer WBWA Normal memory ([IO]RGN0 = 0b01) + // - map + // + 32 bits of VA space (T0SZ = 0x20) + // + into a 32-bit PA space (IPS = 0b000) + // + // 36 32 28 24 20 16 12 8 4 0 + // -----+----+----+----+----+----+----+----+----+----+ + // | | |OOII| | | |OOII| | | + // TT | | |RRRR|E T | T| |RRRR|E T | T| + // BB | I I|TTSS|GGGG|P 1 | 1|TTSS|GGGG|P 0 | 0| + // IIA| P P|GGHH|NNNN|DAS | S|GGHH|NNNN|D S | S| + // 10S| S-S|1111|1111|11Z-|---Z|0000|0000|0 Z-|---Z| + // + // 000 0000 0000 0000 1000 0000 0010 0101 0010 0000 + // + // 0x 8 0 2 5 2 0 + // + // Note: the ISB is needed to ensure the changes to system + // context are before the write of SCTLR_EL1.M to enable + // the MMU. It is likely on a "real" implementation that + // this setup would work without an ISB, due to the + // amount of code that gets executed before enabling the + // MMU, but that would not be architecturally correct. + // + ldr x1, =0x0000000000802520 + msr TCR_EL1, x1 + isb + + // + // the primary CPU is going to use SGI 15 as a wakeup event + // to let us know when it is OK to proceed, so prepare for + // receiving that interrupt + // + // NS interrupt priorities run from 0 to 15, with 15 being + // too low a priority to ever raise an interrupt, so let's + // use 14 + // + mov w0, w19 + mov w1, #0 + mov w2, #14 << 4 // we're in NS world, so 4 bits of priority, + // 8-bit field, - 4 = 4-bit shift + bl SetPrivateIntPriority + + mov w0, w19 + mov w1, #0 + bl EnablePrivateInt + + // + // set priority mask as low as possible; although,being in the + // NS World, we can't set bit[7] of the priority, we still + // write all 8-bits of priority to an ICC register + // + mov x0, #31 << 3 + msr ICC_PMR_EL1, x0 + + // + // set global enable and wait for our interrupt to arrive + // + mov x0, #1 + msr ICC_IGRPEN1_EL1, x0 + isb + + // + // x19 already contains the CPU number, so branch to secondary + // code if we're not on CPU0 + // + cbnz x19, el1_secondary + + // + // Fall through to primary code + // + + +// +// ------------------------------------------------------------ +// +// EL1 - primary CPU init code +// +// This code is run on CPU0, while the other CPUs are in the +// holding pen +// + + .global el1_primary + .type el1_primary, "function" +el1_primary: + + // + // Turn on the banked GIC distributor enable, + // ready for individual CPU enables later + // + mov w0, #(1 << 1) // gicdctlr_EnableGrp1A + bl EnableGICD + + // + // Generate TTBR0 L1 + // + // at 4KB granularity, 32-bit VA space, table lookup starts at + // L1, with 1GB regions + // + // we are going to create entries pointing to L2 tables for a + // couple of these 1GB regions, the first of which is the + // RAM on the VE board model - get the table addresses and + // start by emptying out the L1 page tables (4 entries at L1 + // for a 4K granularity) + // + // x21 = address of L1 tables + // + ldr x21, =Image$$TTB0_L1$$ZI$$Base + mov x0, x21 + mov x1, #(4 << 3) + bl ZeroBlock + + // + // time to start mapping the RAM regions - clear out the + // L2 tables and point to them from the L1 tables + // + // x22 = address of L2 tables, needs to be remembered in case + // we want to re-use the tables for mapping peripherals + // + ldr x22, =Image$$TTB0_L2_RAM$$ZI$$Base + mov x1, #(512 << 3) + mov x0, x22 + bl ZeroBlock + + // + // Get the start address of RAM (the EXEC region) into x4 + // and calculate the offset into the L1 table (1GB per region, + // max 4GB) + // + // x23 = L1 table offset, saved for later comparison against + // peripheral offset + // + ldr x4, =Image$$EXEC$$RO$$Base + ubfx x23, x4, #30, #2 + + orr x1, x22, #TT_S1_ATTR_PAGE + str x1, [x21, x23, lsl #3] + + // + // we've already used the RAM start address in x4 - we now need + // to get this in terms of an offset into the L2 page tables, + // where each entry covers 2MB + // + ubfx x2, x4, #21, #9 + + // + // TOP_OF_RAM in the scatter file marks the end of the + // Execute region in RAM: convert the end of this region to an + // offset too, being careful to round up, then calculate the + // number of entries to write + // + ldr x5, =Image$$TOP_OF_RAM$$ZI$$Base + sub x3, x5, #1 + ubfx x3, x3, #21, #9 + add x3, x3, #1 + sub x3, x3, x2 + + // + // set x1 to the required page table attributes, then orr + // in the start address (modulo 2MB) + // + // L2 tables in our configuration cover 2MB per entry - map + // memory as Shared, Normal WBWA (MAIR[1]) with a flat + // VA->PA translation + // + bic x4, x4, #((1 << 21) - 1) + mov x1, #(TT_S1_ATTR_BLOCK | \ + (1 << TT_S1_ATTR_MATTR_LSB) | \ + TT_S1_ATTR_NS | \ + TT_S1_ATTR_AP_RW_PL1 | \ + TT_S1_ATTR_SH_INNER | \ + TT_S1_ATTR_AF | \ + TT_S1_ATTR_nG) + orr x1, x1, x4 + + // + // factor the offset into the page table address and then write + // the entries + // + add x0, x22, x2, lsl #3 + +loop1: + subs x3, x3, #1 + str x1, [x0], #8 + add x1, x1, #0x200, LSL #12 // equiv to add x1, x1, #(1 << 21) // 2MB per entry + bne loop1 + + + // + // now mapping the Peripheral regions - clear out the + // L2 tables and point to them from the L1 tables + // + // The assumption here is that all peripherals live within + // a common 1GB region (i.e. that there's a single set of + // L2 pages for all the peripherals). We only use a UART + // and the GIC in this example, so the assumption is sound + // + // x24 = address of L2 peripheral tables + // + ldr x24, =Image$$TTB0_L2_PERIPH$$ZI$$Base + + // + // get the GICD address into x4 and calculate + // the offset into the L1 table + // + // x25 = L1 table offset + // + ldr x4, =Image$$GICD$$ZI$$Base + ubfx x25, x4, #30, #2 + + // + // here's the tricky bit: it's possible that the peripherals are + // in the same 1GB region as the RAM, in which case we don't need + // to prime a separate set of L2 page tables, nor add them to the + // L1 tables + // + // if we're going to re-use the TTB0_L2_RAM tables, get their + // address into x24, which is used later on to write the PTEs + // + cmp x25, x23 + csel x24, x22, x24, EQ + b.eq nol2setup + + // + // Peripherals are in a separate 1GB region, and so have their own + // set of L2 tables - clean out the tables and add them to the L1 + // table + // + mov x0, x24 + mov x1, #512 << 3 + bl ZeroBlock + + orr x1, x24, #TT_S1_ATTR_PAGE + str x1, [x21, x25, lsl #3] + + // + // there's only going to be a single 2MB region for GICD (in + // x4) - get this in terms of an offset into the L2 page tables + // + // with larger systems, it is possible that the GIC redistributor + // registers require extra 2MB pages, in which case extra code + // would be required here + // +nol2setup: + ubfx x2, x4, #21, #9 + + // + // set x1 to the required page table attributes, then orr + // in the start address (modulo 2MB) + // + // L2 tables in our configuration cover 2MB per entry - map + // memory as NS Device-nGnRE (MAIR[2]) with a flat VA->PA + // translation + // + bic x4, x4, #((1 << 21) - 1) // start address mod 2MB + mov x1, #(TT_S1_ATTR_BLOCK | \ + (2 << TT_S1_ATTR_MATTR_LSB) | \ + TT_S1_ATTR_NS | \ + TT_S1_ATTR_AP_RW_PL1 | \ + TT_S1_ATTR_AF | \ + TT_S1_ATTR_nG) + orr x1, x1, x4 + + // + // only a single L2 entry for this, so no loop as we have for RAM, above + // + str x1, [x24, x2, lsl #3] + + // + // we have CS3_PERIPHERALS that include the UART controller + // + // Again, the code is making assumptions - this time that the CS3_PERIPHERALS + // region uses the same 1GB portion of the address space as the GICD, + // and thus shares the same set of L2 page tables + // + // Get CS3_PERIPHERALS address into x4 and calculate the offset into the + // L2 tables + // + ldr x4, =Image$$CS3_PERIPHERALS$$ZI$$Base + ubfx x2, x4, #21, #9 + + // + // set x1 to the required page table attributes, then orr + // in the start address (modulo 2MB) + // + // L2 tables in our configuration cover 2MB per entry - map + // memory as NS Device-nGnRE (MAIR[2]) with a flat VA->PA + // translation + // + bic x4, x4, #((1 << 21) - 1) // start address mod 2MB + mov x1, #(TT_S1_ATTR_BLOCK | \ + (2 << TT_S1_ATTR_MATTR_LSB) | \ + TT_S1_ATTR_NS | \ + TT_S1_ATTR_AP_RW_PL1 | \ + TT_S1_ATTR_AF | \ + TT_S1_ATTR_nG) + orr x1, x1, x4 + + // + // only a single L2 entry again - write it + // + str x1, [x24, x2, lsl #3] + + // + // issue a barrier to ensure all table entry writes are complete + // + dsb ish + + ldr x1, =is_mmu_ready + mov x2, #1 + str x2, [x1] + + // + // Enable the MMU. Caches will be enabled later, after scatterloading. + // + mrs x1, SCTLR_EL1 + orr x1, x1, #SCTLR_ELx_M + bic x1, x1, #SCTLR_ELx_A // Disable alignment fault checking. To enable, change bic to orr + msr SCTLR_EL1, x1 + isb + + // + // Branch to C library init code + // + b __main + + +// ------------------------------------------------------------ + +// AArch64 Arm C library startup add-in: + +// The Arm Architecture Reference Manual for Armv8-A states: +// +// Instruction accesses to Non-cacheable Normal memory can be held in instruction caches. +// Correspondingly, the sequence for ensuring that modifications to instructions are available +// for execution must include invalidation of the modified locations from the instruction cache, +// even if the instructions are held in Normal Non-cacheable memory. +// This includes cases where the instruction cache is disabled. +// +// To invalidate the AArch64 instruction cache after scatter-loading and before initialization of the stack and heap, +// it is necessary for the user to: +// +// * Implement instruction cache invalidation code in _platform_pre_stackheap_init. +// * Ensure all code on the path from the program entry up to and including _platform_pre_stackheap_init is located in a root region. +// +// In this example, this function is only called once, by the primary core + + .global _platform_pre_stackheap_init + .type _platform_pre_stackheap_init, "function" + .cfi_startproc +_platform_pre_stackheap_init: + dsb ish // ensure all previous stores have completed before invalidating + ic ialluis // I cache invalidate all inner shareable to PoU (which includes secondary cores) + dsb ish // ensure completion on inner shareable domain (which includes secondary cores) + isb + + // Scatter-loading is complete, so enable the caches here, so that the C-library's mutex initialization later will work + mrs x1, SCTLR_EL1 + orr x1, x1, #SCTLR_ELx_C + orr x1, x1, #SCTLR_ELx_I + msr SCTLR_EL1, x1 + isb + + ret + .cfi_endproc + + +// ------------------------------------------------------------ +// EL1 - secondary CPU init code +// +// This code is run on CPUs 1, 2, 3 etc.... +// ------------------------------------------------------------ + + .global el1_secondary + .type el1_secondary, "function" +el1_secondary: + +wait_for_mmu_ready: + ldr x1, =is_mmu_ready + ldr x1, [x1] + cmp x1, #1 + b.ne wait_for_mmu_ready + + // + // Enable the MMU and caches + // + mrs x1, SCTLR_EL1 + orr x1, x1, #SCTLR_ELx_M + orr x1, x1, #SCTLR_ELx_C + orr x1, x1, #SCTLR_ELx_I + bic x1, x1, #SCTLR_ELx_A // Disable alignment fault checking. To enable, change bic to orr + msr SCTLR_EL1, x1 + isb + + /* EL: Secondary core entrance. */ + B _tx_thread_smp_initialize_wait + +loop_wfi: + dsb SY // Clear all pending data accesses + wfi // Go to sleep + + // + // something woke us from our wait, was it the required interrupt? + // + mov w0, w19 + mov w1, #15 + bl GetPrivateIntPending + cbz w0, loop_wfi + + // + // it was - there's no need to actually take the interrupt, + // so just clear it + // + mov w0, w19 + mov w1, #15 + bl ClearPrivateIntPending + + // + // Branch to thread start + // + // B MainApp + + /** + * Retargeted to prevent the C library from doing its own stack and heap + * initialisation. + */ + .type __user_setup_stackheap, @function +__user_setup_stackheap: + ADRP X0, Image$$SYS_STACK$$ZI$$Limit + MOV SP, X0 + ADRP X0, Image$$ARM_LIB_HEAP$$ZI$$Base + ADRP X2, Image$$ARM_LIB_HEAP$$ZI$$Limit + RET + diff --git a/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/startup_AArch64-FVP_Base_AEMv8A.launch b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/startup_AArch64-FVP_Base_AEMv8A.launch new file mode 100644 index 00000000..fc1a8ba9 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/startup_AArch64-FVP_Base_AEMv8A.launch @@ -0,0 +1,401 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/timer_interrupts.c b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/timer_interrupts.c new file mode 100644 index 00000000..7b0996ef --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/timer_interrupts.c @@ -0,0 +1,152 @@ +/* Bare-metal example for Armv8-A FVP Base model */ + +/* Timer and interrupts */ + +/* Copyright (c) 2016 Arm Limited (or its affiliates). All rights reserved. */ +/* Use, modification and redistribution of this file is subject to your */ +/* possession of a valid DS-5 end user licence agreement and your compliance */ +/* with all applicable terms and conditions of such licence agreement. */ + +#include + +#include "GICv3.h" +#include "GICv3_gicc.h" +#include "sp804_timer.h" + +void _tx_timer_interrupt(void); + +// LED Base address +#define LED_BASE (volatile unsigned int *)0x1C010008 + + +void nudge_leds(void) // Move LEDs along +{ + static int state = 1; + static int value = 1; + + if (state) + { + int max = (1 << 7); + value <<= 1; + if (value == max) + state = 0; + } + else + { + value >>= 1; + if (value == 1) + state = 1; + } + + *LED_BASE = value; // Update LEDs hardware +} + + +// Initialize Timer 0 and Interrupt Controller +void init_timer(void) +{ + // Enable interrupts + __asm("MSR DAIFClr, #0xF"); + setICC_IGRPEN1_EL1(igrpEnable); + + // Configure the SP804 timer to generate an interrupt + setTimerBaseAddress(0x1C110000); + initTimer(0x200, SP804_AUTORELOAD, SP804_GENERATE_IRQ); + startTimer(); + + // The SP804 timer generates SPI INTID 34. Enable + // this ID, and route it to core 0.0.0.0 (this one!) + SetSPIRoute(34, 0, gicdirouter_ModeSpecific); // Route INTID 34 to 0.0.0.0 (this core) + SetSPIPriority(34, 0); // Set INTID 34 to priority to 0 + ConfigureSPI(34, gicdicfgr_Level); // Set INTID 34 as level-sensitive + EnableSPI(34); // Enable INTID 34 +} + + +// -------------------------------------------------------- + +void irqHandler(void) +{ + unsigned int ID; + + ID = getICC_IAR1(); // readIntAck(); + + // Check for reserved IDs + if ((1020 <= ID) && (ID <= 1023)) + { + //printf("irqHandler() - Reserved INTID %d\n\n", ID); + return; + } + + switch(ID) + { + case 34: + // Dual-Timer 0 (SP804) + //printf("irqHandler() - External timer interrupt\n\n"); + nudge_leds(); + clearTimerIrq(); + + /* Call ThreadX timer interrupt processing. */ + _tx_timer_interrupt(); + + break; + + default: + // Unexpected ID value + //printf("irqHandler() - Unexpected INTID %d\n\n", ID); + break; + } + + // Write the End of Interrupt register to tell the GIC + // we've finished handling the interrupt + setICC_EOIR1(ID); // writeAliasedEOI(ID); +} + +// -------------------------------------------------------- + +// Not actually used in this example, but provided for completeness + +void fiqHandler(void) +{ + unsigned int ID; + unsigned int aliased = 0; + + ID = getICC_IAR0(); // readIntAck(); + printf("fiqHandler() - Read %d from IAR0\n", ID); + + // Check for reserved IDs + if ((1020 <= ID) && (ID <= 1023)) + { + printf("fiqHandler() - Reserved INTID %d\n\n", ID); + ID = getICC_IAR1(); // readAliasedIntAck(); + printf("fiqHandler() - Read %d from AIAR\n", ID); + aliased = 1; + + // If still spurious then simply return + if ((1020 <= ID) && (ID <= 1023)) + return; + } + + switch(ID) + { + case 34: + // Dual-Timer 0 (SP804) + printf("fiqHandler() - External timer interrupt\n\n"); + clearTimerIrq(); + break; + + default: + // Unexpected ID value + printf("fiqHandler() - Unexpected INTID %d\n\n", ID); + break; + } + + // Write the End of Interrupt register to tell the GIC + // we've finished handling the interrupt + // NOTE: If the ID was read from the Aliased IAR, then + // the aliased EOI register must be used + if (aliased == 0) + setICC_EOIR0(ID); // writeEOI(ID); + else + setICC_EOIR1(ID); // writeAliasedEOI(ID); +} diff --git a/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/use_model_semihosting.ds b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/use_model_semihosting.ds new file mode 100644 index 00000000..6fde52b2 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/use_model_semihosting.ds @@ -0,0 +1 @@ +set semihosting enabled off diff --git a/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/v8_aarch64.S b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/v8_aarch64.S new file mode 100644 index 00000000..e2d81e5e --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/v8_aarch64.S @@ -0,0 +1,161 @@ +// ------------------------------------------------------------ +// Armv8-A AArch64 - Common helper functions +// +// Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your +// possession of a valid DS-5 end user licence agreement and your compliance +// with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#include "v8_system.h" + + .text + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + + .global EnableCachesEL1 + .global DisableCachesEL1 + .global InvalidateUDCaches + .global GetMIDR + .global GetMPIDR + .global GetCPUID + +// ------------------------------------------------------------ + +// +// void EnableCachesEL1(void) +// +// enable Instruction and Data caches +// + .type EnableCachesEL1, "function" + .cfi_startproc +EnableCachesEL1: + + mrs x0, SCTLR_EL1 + orr x0, x0, #SCTLR_ELx_I + orr x0, x0, #SCTLR_ELx_C + msr SCTLR_EL1, x0 + + isb + ret + .cfi_endproc + + +// ------------------------------------------------------------ + + .type DisableCachesEL1, "function" + .cfi_startproc +DisableCachesEL1: + + mrs x0, SCTLR_EL1 + bic x0, x0, #SCTLR_ELx_I + bic x0, x0, #SCTLR_ELx_C + msr SCTLR_EL1, x0 + + isb + ret + .cfi_endproc + + +// ------------------------------------------------------------ + +// +// void InvalidateUDCaches(void) +// +// Invalidate data and unified caches +// + .type InvalidateUDCaches, "function" + .cfi_startproc +InvalidateUDCaches: + // From the Armv8-A Architecture Reference Manual + + dmb ish // ensure all prior inner-shareable accesses have been observed + + mrs x0, CLIDR_EL1 + and w3, w0, #0x07000000 // get 2 x level of coherence + lsr w3, w3, #23 + cbz w3, finished + mov w10, #0 // w10 = 2 x cache level + mov w8, #1 // w8 = constant 0b1 +loop_level: + add w2, w10, w10, lsr #1 // calculate 3 x cache level + lsr w1, w0, w2 // extract 3-bit cache type for this level + and w1, w1, #0x7 + cmp w1, #2 + b.lt next_level // no data or unified cache at this level + msr CSSELR_EL1, x10 // select this cache level + isb // synchronize change of csselr + mrs x1, CCSIDR_EL1 // read ccsidr + and w2, w1, #7 // w2 = log2(linelen)-4 + add w2, w2, #4 // w2 = log2(linelen) + ubfx w4, w1, #3, #10 // w4 = max way number, right aligned + clz w5, w4 // w5 = 32-log2(ways), bit position of way in dc operand + lsl w9, w4, w5 // w9 = max way number, aligned to position in dc operand + lsl w16, w8, w5 // w16 = amount to decrement way number per iteration +loop_way: + ubfx w7, w1, #13, #15 // w7 = max set number, right aligned + lsl w7, w7, w2 // w7 = max set number, aligned to position in dc operand + lsl w17, w8, w2 // w17 = amount to decrement set number per iteration +loop_set: + orr w11, w10, w9 // w11 = combine way number and cache number ... + orr w11, w11, w7 // ... and set number for dc operand + dc isw, x11 // do data cache invalidate by set and way + subs w7, w7, w17 // decrement set number + b.ge loop_set + subs x9, x9, x16 // decrement way number + b.ge loop_way +next_level: + add w10, w10, #2 // increment 2 x cache level + cmp w3, w10 + b.gt loop_level + dsb sy // ensure completion of previous cache maintenance operation + isb +finished: + ret + .cfi_endproc + + +// ------------------------------------------------------------ + +// +// ID Register functions +// + + .type GetMIDR, "function" + .cfi_startproc +GetMIDR: + + mrs x0, MIDR_EL1 + ret + .cfi_endproc + + + .type GetMPIDR, "function" + .cfi_startproc +GetMPIDR: + + mrs x0, MPIDR_EL1 + ret + .cfi_endproc + + + .type GetCPUID, "function" + .cfi_startproc +GetCPUID: + + mrs x0, MIDR_EL1 + ubfx x0, x0, #4, #12 // extract PartNum + cmp x0, #0xD0A // Cortex-A75 + b.eq DynamIQ + cmp x0, #0xD05 // Cortex-A55 + b.eq DynamIQ + b Others +DynamIQ: + mrs x0, MPIDR_EL1 + ubfx x0, x0, #MPIDR_EL1_AFF1_LSB, #MPIDR_EL1_AFF_WIDTH + ret + +Others: + mrs x0, MPIDR_EL1 + ubfx x0, x0, #MPIDR_EL1_AFF0_LSB, #MPIDR_EL1_AFF_WIDTH + ret + .cfi_endproc diff --git a/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/v8_mmu.h b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/v8_mmu.h new file mode 100644 index 00000000..afb8b923 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/v8_mmu.h @@ -0,0 +1,118 @@ +// +// Defines for v8 Memory Model +// +// Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your +// possession of a valid DS-5 end user licence agreement and your compliance +// with all applicable terms and conditions of such licence agreement. +// + +#ifndef V8_MMU_H +#define V8_MMU_H + +// +// Translation Control Register fields +// +// RGN field encodings +// +#define TCR_RGN_NC 0b00 +#define TCR_RGN_WBWA 0b01 +#define TCR_RGN_WT 0b10 +#define TCR_RGN_WBRA 0b11 + +// +// Shareability encodings +// +#define TCR_SHARE_NONE 0b00 +#define TCR_SHARE_OUTER 0b10 +#define TCR_SHARE_INNER 0b11 + +// +// Granule size encodings +// +#define TCR_GRANULE_4K 0b00 +#define TCR_GRANULE_64K 0b01 +#define TCR_GRANULE_16K 0b10 + +// +// Physical Address sizes +// +#define TCR_SIZE_4G 0b000 +#define TCR_SIZE_64G 0b001 +#define TCR_SIZE_1T 0b010 +#define TCR_SIZE_4T 0b011 +#define TCR_SIZE_16T 0b100 +#define TCR_SIZE_256T 0b101 + +// +// Translation Control Register fields +// +#define TCR_EL1_T0SZ_SHIFT 0 +#define TCR_EL1_EPD0 (1 << 7) +#define TCR_EL1_IRGN0_SHIFT 8 +#define TCR_EL1_ORGN0_SHIFT 10 +#define TCR_EL1_SH0_SHIFT 12 +#define TCR_EL1_TG0_SHIFT 14 + +#define TCR_EL1_T1SZ_SHIFT 16 +#define TCR_EL1_A1 (1 << 22) +#define TCR_EL1_EPD1 (1 << 23) +#define TCR_EL1_IRGN1_SHIFT 24 +#define TCR_EL1_ORGN1_SHIFT 26 +#define TCR_EL1_SH1_SHIFT 28 +#define TCR_EL1_TG1_SHIFT 30 +#define TCR_EL1_IPS_SHIFT 32 +#define TCR_EL1_AS (1 << 36) +#define TCR_EL1_TBI0 (1 << 37) +#define TCR_EL1_TBI1 (1 << 38) + +// +// Stage 1 Translation Table descriptor fields +// +#define TT_S1_ATTR_FAULT (0b00 << 0) +#define TT_S1_ATTR_BLOCK (0b01 << 0) // Level 1/2 +#define TT_S1_ATTR_TABLE (0b11 << 0) // Level 0/1/2 +#define TT_S1_ATTR_PAGE (0b11 << 0) // Level 3 + +#define TT_S1_ATTR_MATTR_LSB 2 + +#define TT_S1_ATTR_NS (1 << 5) + +#define TT_S1_ATTR_AP_RW_PL1 (0b00 << 6) +#define TT_S1_ATTR_AP_RW_ANY (0b01 << 6) +#define TT_S1_ATTR_AP_RO_PL1 (0b10 << 6) +#define TT_S1_ATTR_AP_RO_ANY (0b11 << 6) + +#define TT_S1_ATTR_SH_NONE (0b00 << 8) +#define TT_S1_ATTR_SH_OUTER (0b10 << 8) +#define TT_S1_ATTR_SH_INNER (0b11 << 8) + +#define TT_S1_ATTR_AF (1 << 10) +#define TT_S1_ATTR_nG (1 << 11) + +#define TT_S1_ATTR_CONTIG (1 << 52) +#define TT_S1_ATTR_PXN (1 << 53) +#define TT_S1_ATTR_UXN (1 << 54) + +#define TT_S1_MAIR_DEV_nGnRnE 0b00000000 +#define TT_S1_MAIR_DEV_nGnRE 0b00000100 +#define TT_S1_MAIR_DEV_nGRE 0b00001000 +#define TT_S1_MAIR_DEV_GRE 0b00001100 + +// +// Inner and Outer Normal memory attributes use the same bit patterns +// Outer attributes just need to be shifted up +// +#define TT_S1_MAIR_OUTER_SHIFT 4 + +#define TT_S1_MAIR_WT_TRANS_RA 0b0010 + +#define TT_S1_MAIR_WB_TRANS_RA 0b0110 +#define TT_S1_MAIR_WB_TRANS_RWA 0b0111 + +#define TT_S1_MAIR_WT_RA 0b1010 + +#define TT_S1_MAIR_WB_RA 0b1110 +#define TT_S1_MAIR_WB_RWA 0b1111 + +#endif // V8_MMU_H diff --git a/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/v8_system.h b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/v8_system.h new file mode 100644 index 00000000..e54f2fc7 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/v8_system.h @@ -0,0 +1,115 @@ +// +// Defines for v8 System Registers +// +// Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your +// possession of a valid DS-5 end user licence agreement and your compliance +// with all applicable terms and conditions of such licence agreement. +// + +#ifndef V8_SYSTEM_H +#define V8_SYSTEM_H + +// +// AArch64 SPSR +// +#define AARCH64_SPSR_EL3h 0b1101 +#define AARCH64_SPSR_EL3t 0b1100 +#define AARCH64_SPSR_EL2h 0b1001 +#define AARCH64_SPSR_EL2t 0b1000 +#define AARCH64_SPSR_EL1h 0b0101 +#define AARCH64_SPSR_EL1t 0b0100 +#define AARCH64_SPSR_EL0t 0b0000 +#define AARCH64_SPSR_RW (1 << 4) +#define AARCH64_SPSR_F (1 << 6) +#define AARCH64_SPSR_I (1 << 7) +#define AARCH64_SPSR_A (1 << 8) +#define AARCH64_SPSR_D (1 << 9) +#define AARCH64_SPSR_IL (1 << 20) +#define AARCH64_SPSR_SS (1 << 21) +#define AARCH64_SPSR_V (1 << 28) +#define AARCH64_SPSR_C (1 << 29) +#define AARCH64_SPSR_Z (1 << 30) +#define AARCH64_SPSR_N (1 << 31) + +// +// Multiprocessor Affinity Register +// +#define MPIDR_EL1_AFF3_LSB 32 +#define MPIDR_EL1_U (1 << 30) +#define MPIDR_EL1_MT (1 << 24) +#define MPIDR_EL1_AFF2_LSB 16 +#define MPIDR_EL1_AFF1_LSB 8 +#define MPIDR_EL1_AFF0_LSB 0 +#define MPIDR_EL1_AFF_WIDTH 8 + +// +// Data Cache Zero ID Register +// +#define DCZID_EL0_BS_LSB 0 +#define DCZID_EL0_BS_WIDTH 4 +#define DCZID_EL0_DZP_LSB 5 +#define DCZID_EL0_DZP (1 << 5) + +// +// System Control Register +// +#define SCTLR_EL1_UCI (1 << 26) +#define SCTLR_ELx_EE (1 << 25) +#define SCTLR_EL1_E0E (1 << 24) +#define SCTLR_ELx_WXN (1 << 19) +#define SCTLR_EL1_nTWE (1 << 18) +#define SCTLR_EL1_nTWI (1 << 16) +#define SCTLR_EL1_UCT (1 << 15) +#define SCTLR_EL1_DZE (1 << 14) +#define SCTLR_ELx_I (1 << 12) +#define SCTLR_EL1_UMA (1 << 9) +#define SCTLR_EL1_SED (1 << 8) +#define SCTLR_EL1_ITD (1 << 7) +#define SCTLR_EL1_THEE (1 << 6) +#define SCTLR_EL1_CP15BEN (1 << 5) +#define SCTLR_EL1_SA0 (1 << 4) +#define SCTLR_ELx_SA (1 << 3) +#define SCTLR_ELx_C (1 << 2) +#define SCTLR_ELx_A (1 << 1) +#define SCTLR_ELx_M (1 << 0) + +// +// Architectural Feature Access Control Register +// +#define CPACR_EL1_TTA (1 << 28) +#define CPACR_EL1_FPEN (3 << 20) + +// +// Architectural Feature Trap Register +// +#define CPTR_ELx_TCPAC (1 << 31) +#define CPTR_ELx_TTA (1 << 20) +#define CPTR_ELx_TFP (1 << 10) + +// +// Secure Configuration Register +// +#define SCR_EL3_TWE (1 << 13) +#define SCR_EL3_TWI (1 << 12) +#define SCR_EL3_ST (1 << 11) +#define SCR_EL3_RW (1 << 10) +#define SCR_EL3_SIF (1 << 9) +#define SCR_EL3_HCE (1 << 8) +#define SCR_EL3_SMD (1 << 7) +#define SCR_EL3_EA (1 << 3) +#define SCR_EL3_FIQ (1 << 2) +#define SCR_EL3_IRQ (1 << 1) +#define SCR_EL3_NS (1 << 0) + +// +// Hypervisor Configuration Register +// +#define HCR_EL2_ID (1 << 33) +#define HCR_EL2_CD (1 << 32) +#define HCR_EL2_RW (1 << 31) +#define HCR_EL2_TRVM (1 << 30) +#define HCR_EL2_HVC (1 << 29) +#define HCR_EL2_TDZ (1 << 28) + +#endif // V8_SYSTEM_H diff --git a/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/v8_utils.S b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/v8_utils.S new file mode 100644 index 00000000..750488b7 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/v8_utils.S @@ -0,0 +1,69 @@ +// +// Simple utility routines for baremetal v8 code +// +// Copyright (c) 2013-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your +// possession of a valid DS-5 end user licence agreement and your compliance +// with all applicable terms and conditions of such licence agreement. +// + +#include "v8_system.h" + + .text + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + +// +// void *ZeroBlock(void *blockPtr, unsigned int nBytes) +// +// Zero fill a block of memory +// Fill memory pages or similar structures with zeros. +// The byte count must be a multiple of the block fill size (16 bytes) +// +// Inputs: +// blockPtr - base address of block to fill +// nBytes - block size, in bytes +// +// Returns: +// pointer to just filled block, NULL if nBytes is +// incompatible with block fill size +// + .global ZeroBlock + .type ZeroBlock, "function" + .cfi_startproc +ZeroBlock: + + // + // we fill data by steam, 16 bytes at a time: check that + // blocksize is a multiple of that + // + ubfx x2, x1, #0, #4 + cbnz x2, incompatible + + // + // we already have one register full of zeros, get another + // + mov x3, x2 + + // + // OK, set temporary pointer and away we go + // + add x0, x0, x1 + +loop0: + subs x1, x1, #16 + stp x2, x3, [x0, #-16]! + b.ne loop0 + + // + // that's all - x0 will be back to its start value + // + ret + + // + // parameters are incompatible with block size - return + // an indication that this is so + // +incompatible: + mov x0,#0 + ret + .cfi_endproc diff --git a/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/vectors.S b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/vectors.S new file mode 100644 index 00000000..be6d28a3 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/example_build/sample_threadx/vectors.S @@ -0,0 +1,252 @@ +// ------------------------------------------------------------ +// Armv8-A Vector tables +// +// Copyright (c) 2014-2016 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your +// possession of a valid DS-5 end user licence agreement and your compliance +// with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + + + .global el1_vectors + .global el2_vectors + .global el3_vectors + .global c0sync1 + .global irqHandler + .global fiqHandler + .global irqFirstLevelHandler + .global fiqFirstLevelHandler + + .section EL1VECTORS, "ax" + .align 11 + +// +// Current EL with SP0 +// +el1_vectors: +c0sync1: B c0sync1 + + .balign 0x80 +c0irq1: B irqFirstLevelHandler + + .balign 0x80 +c0fiq1: B fiqFirstLevelHandler + + .balign 0x80 +c0serr1: B c0serr1 + +// +// Current EL with SPx +// + .balign 0x80 +cxsync1: B cxsync1 + + .balign 0x80 +cxirq1: B irqFirstLevelHandler + + .balign 0x80 +cxfiq1: B fiqFirstLevelHandler + + .balign 0x80 +cxserr1: B cxserr1 + +// +// Lower EL using AArch64 +// + .balign 0x80 +l64sync1: B l64sync1 + + .balign 0x80 +l64irq1: B irqFirstLevelHandler + + .balign 0x80 +l64fiq1: B fiqFirstLevelHandler + + .balign 0x80 +l64serr1: B l64serr1 + +// +// Lower EL using AArch32 +// + .balign 0x80 +l32sync1: B l32sync1 + + .balign 0x80 +l32irq1: B irqFirstLevelHandler + + .balign 0x80 +l32fiq1: B fiqFirstLevelHandler + + .balign 0x80 +l32serr1: B l32serr1 + +//---------------------------------------------------------------- + + .section EL2VECTORS, "ax" + .align 11 + +// +// Current EL with SP0 +// +el2_vectors: +c0sync2: B c0sync2 + + .balign 0x80 +c0irq2: B irqFirstLevelHandler + + .balign 0x80 +c0fiq2: B fiqFirstLevelHandler + + .balign 0x80 +c0serr2: B c0serr2 + +// +// Current EL with SPx +// + .balign 0x80 +cxsync2: B cxsync2 + + .balign 0x80 +cxirq2: B irqFirstLevelHandler + + .balign 0x80 +cxfiq2: B fiqFirstLevelHandler + + .balign 0x80 +cxserr2: B cxserr2 + +// +// Lower EL using AArch64 +// + .balign 0x80 +l64sync2: B l64sync2 + + .balign 0x80 +l64irq2: B irqFirstLevelHandler + + .balign 0x80 +l64fiq2: B fiqFirstLevelHandler + + .balign 0x80 +l64serr2: B l64serr2 + +// +// Lower EL using AArch32 +// + .balign 0x80 +l32sync2: B l32sync2 + + .balign 0x80 +l32irq2: B irqFirstLevelHandler + + .balign 0x80 +l32fiq2: B fiqFirstLevelHandler + + .balign 0x80 +l32serr2: B l32serr2 + +//---------------------------------------------------------------- + + .section EL3VECTORS, "ax" + .align 11 + +// +// Current EL with SP0 +// +el3_vectors: +c0sync3: B c0sync3 + + .balign 0x80 +c0irq3: B irqFirstLevelHandler + + .balign 0x80 +c0fiq3: B fiqFirstLevelHandler + + .balign 0x80 +c0serr3: B c0serr3 + +// +// Current EL with SPx +// + .balign 0x80 +cxsync3: B cxsync3 + + .balign 0x80 +cxirq3: B irqFirstLevelHandler + + .balign 0x80 +cxfiq3: B fiqFirstLevelHandler + + .balign 0x80 +cxserr3: B cxserr3 + +// +// Lower EL using AArch64 +// + .balign 0x80 +l64sync3: B l64sync3 + + .balign 0x80 +l64irq3: B irqFirstLevelHandler + + .balign 0x80 +l64fiq3: B fiqFirstLevelHandler + + .balign 0x80 +l64serr3: B l64serr3 + +// +// Lower EL using AArch32 +// + .balign 0x80 +l32sync3: B l32sync3 + + .balign 0x80 +l32irq3: B irqFirstLevelHandler + + .balign 0x80 +l32fiq3: B fiqFirstLevelHandler + + .balign 0x80 +l32serr3: B l32serr3 + + + .section InterruptHandlers, "ax" + .balign 4 + + .type irqFirstLevelHandler, "function" +irqFirstLevelHandler: + MSR SPSel, 0 + STP x29, x30, [sp, #-16]! + BL _tx_thread_context_save + BL irqHandler + B _tx_thread_context_restore + + .type fiqFirstLevelHandler, "function" +fiqFirstLevelHandler: + STP x29, x30, [sp, #-16]! + STP x18, x19, [sp, #-16]! + STP x16, x17, [sp, #-16]! + STP x14, x15, [sp, #-16]! + STP x12, x13, [sp, #-16]! + STP x10, x11, [sp, #-16]! + STP x8, x9, [sp, #-16]! + STP x6, x7, [sp, #-16]! + STP x4, x5, [sp, #-16]! + STP x2, x3, [sp, #-16]! + STP x0, x1, [sp, #-16]! + + BL fiqHandler + + LDP x0, x1, [sp], #16 + LDP x2, x3, [sp], #16 + LDP x4, x5, [sp], #16 + LDP x6, x7, [sp], #16 + LDP x8, x9, [sp], #16 + LDP x10, x11, [sp], #16 + LDP x12, x13, [sp], #16 + LDP x14, x15, [sp], #16 + LDP x16, x17, [sp], #16 + LDP x18, x19, [sp], #16 + LDP x29, x30, [sp], #16 + ERET diff --git a/ports_smp/cortex_a5x_smp/ac6/example_build/tx/.cproject b/ports_smp/cortex_a5x_smp/ac6/example_build/tx/.cproject new file mode 100644 index 00000000..cd1ec8cd --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/example_build/tx/.cproject @@ -0,0 +1,148 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/cortex_a5x_smp/ac6/example_build/tx/.project b/ports_smp/cortex_a5x_smp/ac6/example_build/tx/.project new file mode 100644 index 00000000..10681969 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/example_build/tx/.project @@ -0,0 +1,48 @@ + + + tx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + inc_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_smp/inc + + + inc_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/inc + + + src_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_smp/src + + + src_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/src + + + diff --git a/ports_smp/cortex_a5x_smp/ac6/example_build/tx/.settings/language.settings.xml b/ports_smp/cortex_a5x_smp/ac6/example_build/tx/.settings/language.settings.xml new file mode 100644 index 00000000..97873aaa --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/example_build/tx/.settings/language.settings.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/cortex_a5x_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a5x_smp/ac6/inc/tx_port.h new file mode 100644 index 00000000..728ab0d9 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/inc/tx_port.h @@ -0,0 +1,432 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A5x-SMP/AC6 */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/************* Define ThreadX SMP constants. *************/ + +/* Define the ThreadX SMP maximum number of cores. */ + +#ifndef TX_THREAD_SMP_MAX_CORES +#define TX_THREAD_SMP_MAX_CORES 4 +#endif + + +/* Define the ThreadX SMP core mask. */ + +#ifndef TX_THREAD_SMP_CORE_MASK +#define TX_THREAD_SMP_CORE_MASK 0xF /* Where bit 0 represents Core 0, bit 1 represents Core 1, etc. */ +#endif + + +/* Define INLINE_DECLARE to whitespace for ARM compiler. */ + +#define INLINE_DECLARE + + +/* Define ThreadX SMP initialization macro. */ + +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION + + +/* Define ThreadX SMP pre-scheduler initialization. */ + +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION + + +/* Enable the inter-core interrupt logic. */ + +#define TX_THREAD_SMP_INTER_CORE_INTERRUPT + + +/* Determine if there is customer-specific wakeup logic needed. */ + +#ifdef TX_THREAD_SMP_WAKEUP_LOGIC + +/* Include customer-specific wakeup code. */ + +#include "tx_thread_smp_core_wakeup.h" +#else + +#ifdef TX_THREAD_SMP_DEFAULT_WAKEUP_LOGIC + +/* Default wakeup code. */ +#define TX_THREAD_SMP_WAKEUP_LOGIC +#define TX_THREAD_SMP_WAKEUP(i) _tx_thread_smp_core_preempt(i) +#endif +#endif + + +/* Ensure that the in-line resume/suspend define is not allowed. */ + +#ifdef TX_INLINE_THREAD_RESUME_SUSPEND +#undef TX_INLINE_THREAD_RESUME_SUSPEND +#endif + + +/************* End ThreadX SMP constants. *************/ + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef int LONG; +typedef unsigned int ULONG; +typedef unsigned long long ULONG64; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Override the alignment type to use 64-bit alignment and storage for pointers. */ + +#define ALIGN_TYPE_DEFINED +typedef unsigned long long ALIGN_TYPE; + + +/* Override the free block marker for byte pools to be a 64-bit constant. */ + +#define TX_BYTE_BLOCK_FREE ((ALIGN_TYPE) 0xFFFFEEEEFFFFEEEE) + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 4096 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#define TX_INT_ENABLE 0x00 /* Enable IRQ & FIQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE _tx_thread_smp_time_get() +#endif +#else +#ifndef TX_TRACE_TIME_SOURCE +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_fp_enable; +#define TX_THREAD_EXTENSION_3 VOID *tx_thread_extension_ptr; + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) b = (UINT) __builtin_ctz((unsigned int) m); + +#endif + + +/* Define the internal timer extension to also hold the thread pointer such that _tx_thread_timeout + can figure out what thread timeout to process. */ + +#define TX_TIMER_INTERNAL_EXTENSION VOID *tx_timer_internal_extension_ptr; + + +/* Define the thread timeout setup logic in _tx_thread_create. */ + +#define TX_THREAD_CREATE_TIMEOUT_SETUP(t) (t) -> tx_thread_timer.tx_timer_internal_timeout_function = &(_tx_thread_timeout); \ + (t) -> tx_thread_timer.tx_timer_internal_timeout_param = 0; \ + (t) -> tx_thread_timer.tx_timer_internal_extension_ptr = (VOID *) (t); + + +/* Define the thread timeout pointer setup in _tx_thread_timeout. */ + +#define TX_THREAD_TIMEOUT_POINTER_SETUP(t) (t) = (TX_THREAD *) _tx_timer_expired_timer_ptr -> tx_timer_internal_extension_ptr; + + +/************* Define ThreadX SMP data types and function prototypes. *************/ + +struct TX_THREAD_STRUCT; + + +/* Define the ThreadX SMP protection structure. */ + +typedef struct TX_THREAD_SMP_PROTECT_STRUCT +{ + ULONG tx_thread_smp_protect_in_force; + ULONG tx_thread_smp_protect_core; + ULONG tx_thread_smp_protect_count; + ULONG tx_thread_smp_protect_pad_0; + ULONG tx_thread_smp_protect_pad_1; + ULONG tx_thread_smp_protect_pad_2; + ULONG tx_thread_smp_protect_pad_3; +} TX_THREAD_SMP_PROTECT; + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_smp_protect(); +#define TX_RESTORE _tx_thread_smp_unprotect(interrupt_save); + +/************* End ThreadX SMP data type and function prototype definitions. *************/ + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define VFP extension for the Cortex-A5x. Each is assumed to be called in the context of the executing + thread. */ + +#ifndef TX_SOURCE_CODE +#define tx_thread_fp_enable _tx_thread_fp_enable +#define tx_thread_fp_disable _tx_thread_fp_disable +#endif + +VOID tx_thread_fp_enable(VOID); +VOID tx_thread_fp_disable(VOID); + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) 1996-2019 Express Logic Inc. * ThreadX Cortex-A5x-SMP/AC6 Version 6.0.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + + + + + diff --git a/ports_smp/cortex_a5x_smp/ac6/readme_threadx.txt b/ports_smp/cortex_a5x_smp/ac6/readme_threadx.txt new file mode 100644 index 00000000..d9459876 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/readme_threadx.txt @@ -0,0 +1,257 @@ + Microsoft's Azure RTOS ThreadX SMP for Cortex-A5x + + Using the ARM Compiler 6 & DS + +1. Import the ThreadX Projects + +In order to build the ThreadX SMP library and the ThreadX SMP demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +into your DS workspace. + +Note: the projects were made using DS-5, so DS will prompt you to migrate the projects. +This is expected, so please do so. + + +2. Building the ThreadX SMP run-time Library + +Building the ThreadX SMP library is easy; simply select the Eclipse project file +"tx" and then select the build button. You should now observe the compilation +and assembly of the ThreadX SMP library. This project build produces the ThreadX SMP +library file tx.a. + + +3. Demonstration System + +The ThreadX SMP demonstration is designed to execute under the DS debugger on the +'Debug Cortex-A53x4 SMP' FVP which must be downloaded from the ARM website and +requires a license. + +Building the demonstration is easy; simply select the sample_threadx project, and +select the build button. Next, in the sample_threadx project, right-click on the +sample_threadx.launch file and select 'Debug As -> sample_threadx'. The debugger is +setup for the Cortex-53x4 SMP FVP, so selecting "Debug" will launch the FVP, load +the sample_threadx.axf ELF file and run to main. You are now ready to execute the +ThreadX SMP demonstration. + + +4. System Initialization + +The entry point in ThreadX SMP for the Cortex-A5x using AC6 tools is at label +"entry". This is defined within the AC6 compiler's startup code. In addition, +this is where all static and global pre-set C variable initialization processing +takes place. + +The ThreadX SMP tx_initialize_low_level.s file is responsible for determining the +first available RAM address for use by the application, which is supplied as the +sole input parameter to your application definition function, tx_application_define. + + +5. Register Usage and Stack Frames + +The 64-bit AC6 compiler assumes that registers x0-x18 are scratch registers +for each function. All other registers used by a C function must be preserved +by the function. ThreadX SMP takes advantage of this in situations where a context +switch happens as a result of making a ThreadX SMP service call (which is itself a +C function). In such cases, the saved context of a thread is only the +non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + +FP not enabled and TX_THREAD.tx_thread_fp_enable == 0: + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x000 SPSR DAIF + 0x008 ELR 0 + 0x010 x28 x27 + 0x018 reserved x28 + 0x020 x26 x25 + 0x028 x27 x26 + 0x030 x24 x23 + 0x038 x25 x24 + 0x040 x22 x21 + 0x048 x23 x22 + 0x050 x20 x19 + 0x058 x21 x20 + 0x060 x18 x29 + 0x068 x19 x30 + 0x070 x16 + 0x078 x17 + 0x080 x14 + 0x088 x15 + 0x090 x12 + 0x098 x13 + 0x0A0 x10 + 0x0A8 x11 + 0x0B0 x8 + 0x0B8 x9 + 0x0C0 x6 + 0x0C8 x7 + 0x0D0 x4 + 0x0D8 x5 + 0x0E0 x2 + 0x0E8 x3 + 0x0F0 x0 + 0x0F8 x1 + 0x100 x29 + 0x108 x30 + + +FP enabled and TX_THREAD.tx_thread_fp_enable == 1: + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x000 SPSR DAIF + 0x008 ELR 0 + 0x010 FPSR FPSR + 0x018 FPCR FPCR + 0x020 q30 q14 + 0x030 q31 q15 + 0x040 q28 q12 + 0x050 q29 q13 + 0x060 q26 q10 + 0x070 q27 q11 + 0x080 q24 q8 + 0x090 q25 q9 + 0x0A0 q22 x27 + 0x0A8 x28 + 0x0B0 q23 x25 + 0x0B8 x26 + 0x0C0 q20 x23 + 0x0C8 x24 + 0x0D0 q21 x21 + 0x0D8 x22 + 0x0E0 q18 x19 + 0x0E8 x20 + 0x0F0 q19 x29 + 0x0F8 x30 + 0x100 q16 + 0x110 q17 + 0x120 q14 + 0x130 q15 + 0x140 q12 + 0x150 q13 + 0x160 q10 + 0x170 q11 + 0x180 q8 + 0x190 q9 + 0x1A0 q6 + 0x1B0 q7 + 0x1C0 q4 + 0x1D0 q5 + 0x1E0 q2 + 0x1F0 q3 + 0x200 q0 + 0x210 q1 + 0x220 x28 + 0x228 reserved + 0x230 x26 + 0x238 x27 + 0x240 x24 + 0x248 x25 + 0x250 x22 + 0x258 x23 + 0x260 x20 + 0x268 x21 + 0x270 x18 + 0x278 x19 + 0x280 x16 + 0x288 x17 + 0x290 x14 + 0x298 x15 + 0x2A0 x12 + 0x2A8 x13 + 0x2B0 x10 + 0x2B8 x11 + 0x2C0 x8 + 0x2C8 x9 + 0x2D0 x6 + 0x2D8 x7 + 0x2E0 x4 + 0x2E8 x5 + 0x2F0 x2 + 0x2F8 x3 + 0x300 x0 + 0x308 x1 + 0x310 x29 + 0x318 x30 + + + +6. Improving Performance + +The distribution version of ThreadX SMP is built without any compiler optimizations. +This makes it easy to debug because you can trace or set breakpoints inside of +ThreadX SMP itself. Of course, this costs some performance. To make it run faster, +you can change the project settings to the desired compiler optimization level. + +In addition, you can eliminate the ThreadX SMP basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX SMP provides complete and high-performance interrupt handling for Cortex-A5x +targets. Interrupts handlers for the 64-bit mode of the Cortex-A5x have the following +format: + + .global irq_handler +irq_handler: + MSR SPSel, 0 + STP x29, x30, [sp, #-16]! + BL _tx_thread_context_save + + /* Your ISR call goes here! */ + BL application_isr_handler + + B _tx_thread_context_restore + +By default, ThreadX SMP assumes EL3 level of execution. Running and taking exceptions in EL1 +and EL2 can be done by simply building the ThreadX library with either EL1 or EL2 defined. + + +8. ThreadX SMP Timer Interrupt + +ThreadX SMP requires a periodic interrupt source to manage all time-slicing, thread sleeps, +timeouts, and application timers. Without such a timer interrupt source, these services +are not functional. However, all other ThreadX services are operational without a +periodic timer source. + + +9. ARM FP Support + +By default, FP support is disabled for each thread. If saving the context of the FP registers +is needed, the following API call must be made from the context of the application thread - before +the FP usage: + +void tx_thread_fp_enable(void); + +After this API is called in the application, FP registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the FP registers +to be saved/restored. + +To disable FP register context saving, simply call the following API: + +void tx_thread_fp_disable(void); + + +10. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A5x using AC6 tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_initialize_low_level.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_initialize_low_level.S new file mode 100644 index 00000000..564dcfcf --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_initialize_low_level.S @@ -0,0 +1,114 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-A5x-SMP/AC6 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_initialize_low_level(VOID) +{ */ + .global _tx_initialize_low_level + .type _tx_initialize_low_level, @function +_tx_initialize_low_level: + + MSR DAIFSet, 0x3 // Lockout interrupts + + + /* Save the system stack pointer. */ + /* _tx_thread_system_stack_ptr = (VOID_PTR) (sp); */ + + LDR x0, =_tx_thread_system_stack_ptr // Pickup address of system stack ptr + MOV x1, sp // Pickup SP + SUB x1, x1, #15 // + BIC x1, x1, #0xF // Get 16-bit alignment + STR x1, [x0] // Store system stack + + /* Save the first available memory address. */ + /* _tx_initialize_unused_memory = (VOID_PTR) Image$$HEAP$$ZI$$Limit; */ + + LDR x0, =_tx_initialize_unused_memory // Pickup address of unused memory ptr + LDR x1, =heap_limit // Pickup unused memory address - A free + LDR x1, [x1] // memory section must be setup after the + // heap section. + STR x1, [x0] // Store unused memory address + + /* Done, return to caller. */ + + RET // Return to caller +/* } */ + + .align 3 +heap_limit: + .quad (Image$$TOP_OF_RAM$$ZI$$Limit) + diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_context_restore.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_context_restore.S new file mode 100644 index 00000000..7de6aedf --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_context_restore.S @@ -0,0 +1,393 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + +/* Include macros for modifying the wait list. */ +#include "tx_thread_smp_protection_wait_list_macros.h" + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore Cortex-A5x-SMP/AC6 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores the interrupt context if it is processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_restore(VOID) +{ */ + .global _tx_thread_context_restore + .type _tx_thread_context_restore, @function +_tx_thread_context_restore: + + /* Lockout interrupts. */ + + MSR DAIFSet, 0x3 // Lockout interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR exit function to indicate an ISR is complete. */ + + BL _tx_execution_isr_exit // Call the ISR exit function +#endif + + /* Pickup the CPU ID. */ + + MRS x8, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x2, x8, #8, #8 // Isolate cluster ID +#endif + UBFX x8, x8, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x8, x8, x2, LSL #2 // Calculate CPU ID +#endif + + /* Determine if interrupts are nested. */ + /* if (--_tx_thread_system_state) + { */ + + LDR x3, =_tx_thread_system_state // Pickup address of system state var + LDR w2, [x3, x8, LSL #2] // Pickup system state + SUB w2, w2, #1 // Decrement the counter + STR w2, [x3, x8, LSL #2] // Store the counter + CMP w2, #0 // Was this the first interrupt? + BEQ __tx_thread_not_nested_restore // If so, not a nested restore + + /* Interrupts are nested. */ + + /* Just recover the saved registers and return to the point of + interrupt. */ + + LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL +#ifdef EL1 + MSR SPSR_EL1, x4 // Setup SPSR for return + MSR ELR_EL1, x5 // Setup point of interrupt +#else +#ifdef EL2 + MSR SPSR_EL2, x4 // Setup SPSR for return + MSR ELR_EL2, x5 // Setup point of interrupt +#else + MSR SPSR_EL3, x4 // Setup SPSR for return + MSR ELR_EL3, x5 // Setup point of interrupt +#endif +#endif + LDP x18, x19, [sp], #16 // Recover x18, x19 + LDP x16, x17, [sp], #16 // Recover x16, x17 + LDP x14, x15, [sp], #16 // Recover x14, x15 + LDP x12, x13, [sp], #16 // Recover x12, x13 + LDP x10, x11, [sp], #16 // Recover x10, x11 + LDP x8, x9, [sp], #16 // Recover x8, x9 + LDP x6, x7, [sp], #16 // Recover x6, x7 + LDP x4, x5, [sp], #16 // Recover x4, x5 + LDP x2, x3, [sp], #16 // Recover x2, x3 + LDP x0, x1, [sp], #16 // Recover x0, x1 + LDP x29, x30, [sp], #16 // Recover x29, x30 + ERET // Return to point of interrupt + + /* } */ +__tx_thread_not_nested_restore: + + /* Determine if a thread was interrupted and no preemption is required. */ + /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) + || (_tx_thread_preempt_disable)) + { */ + + LDR x1, =_tx_thread_current_ptr // Pickup address of current thread ptr + LDR x0, [x1, x8, LSL #3] // Pickup actual current thread pointer + CMP x0, #0 // Is it NULL? + BEQ __tx_thread_idle_system_restore // Yes, idle system was interrupted + LDR x3, =_tx_thread_execute_ptr // Pickup address of execute thread ptr + LDR x2, [x3, x8, LSL #3] // Pickup actual execute thread pointer + CMP x0, x2 // Is the same thread highest priority? + BEQ __tx_thread_no_preempt_restore // Same thread in the execute list, + // no preemption needs to happen + LDR x3, =_tx_thread_smp_protection // Build address to protection structure + LDR w3, [x3, #4] // Pickup the owning core + CMP w3, w8 // Is it this core? + BNE __tx_thread_preempt_restore // No, proceed to preempt thread + + LDR x3, =_tx_thread_preempt_disable // Pickup preempt disable address + LDR w2, [x3, #0] // Pickup actual preempt disable flag + CMP w2, #0 // Is it set? + BEQ __tx_thread_preempt_restore // No, okay to preempt this thread + +__tx_thread_no_preempt_restore: + + /* Restore interrupted thread or ISR. */ + + /* Pickup the saved stack pointer. */ + /* sp = _tx_thread_current_ptr -> tx_thread_stack_ptr; */ + + LDR x4, [x0, #8] // Switch to thread stack pointer + MOV sp, x4 // + + /* Recover the saved context and return to the point of interrupt. */ + + LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL1 +#ifdef EL1 + MSR SPSR_EL1, x4 // Setup SPSR for return + MSR ELR_EL1, x5 // Setup point of interrupt +#else +#ifdef EL2 + MSR SPSR_EL2, x4 // Setup SPSR for return + MSR ELR_EL2, x5 // Setup point of interrupt +#else + MSR SPSR_EL3, x4 // Setup SPSR for return + MSR ELR_EL3, x5 // Setup point of interrupt +#endif +#endif + LDP x18, x19, [sp], #16 // Recover x18, x19 + LDP x16, x17, [sp], #16 // Recover x16, x17 + LDP x14, x15, [sp], #16 // Recover x14, x15 + LDP x12, x13, [sp], #16 // Recover x12, x13 + LDP x10, x11, [sp], #16 // Recover x10, x11 + LDP x8, x9, [sp], #16 // Recover x8, x9 + LDP x6, x7, [sp], #16 // Recover x6, x7 + LDP x4, x5, [sp], #16 // Recover x4, x5 + LDP x2, x3, [sp], #16 // Recover x2, x3 + LDP x0, x1, [sp], #16 // Recover x0, x1 + LDP x29, x30, [sp], #16 // Recover x29, x30 + ERET // Return to point of interrupt + + /* } + else + { */ +__tx_thread_preempt_restore: + + /* Was the thread being preempted waiting for the lock? */ + /* if (_tx_thread_smp_protect_wait_counts[this_core] != 0) + { */ + + LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list + LDR w3, [x2, x8, LSL #2] // Load waiting value for this core + CMP w3, #0 + BEQ _nobody_waiting_for_lock // Is the core waiting for the lock? + + /* Do we not have the lock? This means the ISR never got the inter-core lock. */ + /* if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core) + { */ + + LDR x2, =_tx_thread_smp_protection // Load address of protection structure + LDR w3, [x2, #4] // Pickup the owning core + CMP w8, w3 // Compare our core to the owning core + BEQ _this_core_has_lock // Do we have the lock? + + /* We don't have the lock. This core should be in the list. Remove it. */ + /* _tx_thread_smp_protect_wait_list_remove(this_core); */ + + _tx_thread_smp_protect_wait_list_remove // Call macro to remove core from the list + B _nobody_waiting_for_lock // Leave + + /* } + else + { */ + /* We have the lock. This means the ISR got the inter-core lock, but + never released it because it saw that there was someone waiting. + Note this core is not in the list. */ + +_this_core_has_lock: + + /* We're no longer waiting. Note that this should be zero since this happens during thread preemption. */ + /* _tx_thread_smp_protect_wait_counts[core]--; */ + + LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list + LDR w3, [x2, x8, LSL #2] // Load waiting value for this core + SUB w3, w3, #1 // Decrement waiting value. Should be zero now + STR w3, [x2, x8, LSL #2] // Store new waiting value + + /* Now release the inter-core lock. */ + + /* Set protected core as invalid. */ + /* _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF; */ + + LDR x2, =_tx_thread_smp_protection // Load address of protection structure + MOV w3, #0xFFFFFFFF // Build invalid value + STR w3, [x2, #4] // Mark the protected core as invalid + DMB ISH // Ensure that accesses to shared resource have completed + + /* Release protection. */ + /* _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0; */ + + MOV w3, #0 // Build release protection value + STR w3, [x2, #0] // Release the protection + DSB ISH // To ensure update of the protection occurs before other CPUs awake + + /* Wake up waiting processors. Note interrupts are already enabled. */ + +#ifdef TX_ENABLE_WFE + SEV // Send event to other CPUs +#endif + + /* } + } */ + +_nobody_waiting_for_lock: + + LDR x4, [x0, #8] // Switch to thread stack pointer + MOV sp, x4 // + + LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL1 + STP x20, x21, [sp, #-16]! // Save x20, x21 + STP x22, x23, [sp, #-16]! // Save x22, x23 + STP x24, x25, [sp, #-16]! // Save x24, x25 + STP x26, x27, [sp, #-16]! // Save x26, x27 + STP x28, x29, [sp, #-16]! // Save x28, x29 +#ifdef ENABLE_ARM_FP + LDR w3, [x0, #268] // Pickup FP enable flag + CMP w3, #0 // Is FP enabled? + BEQ _skip_fp_save // No, skip FP save + STP q0, q1, [sp, #-32]! // Save q0, q1 + STP q2, q3, [sp, #-32]! // Save q2, q3 + STP q4, q5, [sp, #-32]! // Save q4, q5 + STP q6, q7, [sp, #-32]! // Save q6, q7 + STP q8, q9, [sp, #-32]! // Save q8, q9 + STP q10, q11, [sp, #-32]! // Save q10, q11 + STP q12, q13, [sp, #-32]! // Save q12, q13 + STP q14, q15, [sp, #-32]! // Save q14, q15 + STP q16, q17, [sp, #-32]! // Save q16, q17 + STP q18, q19, [sp, #-32]! // Save q18, q19 + STP q20, q21, [sp, #-32]! // Save q20, q21 + STP q22, q23, [sp, #-32]! // Save q22, q23 + STP q24, q25, [sp, #-32]! // Save q24, q25 + STP q26, q27, [sp, #-32]! // Save q26, q27 + STP q28, q29, [sp, #-32]! // Save q28, q29 + STP q30, q31, [sp, #-32]! // Save q30, q31 + MRS x2, FPSR // Pickup FPSR + MRS x3, FPCR // Pickup FPCR + STP x2, x3, [sp, #-16]! // Save FPSR, FPCR +_skip_fp_save: +#endif + STP x4, x5, [sp, #-16]! // Save x4 (SPSR_EL3), x5 (ELR_E3) + + MOV x3, sp // Move sp into x3 + STR x3, [x0, #8] // Save stack pointer in thread control + // block + LDR x3, =_tx_thread_system_stack_ptr // Pickup address of system stack + LDR x4, [x3, x8, LSL #3] // Pickup system stack pointer + MOV sp, x4 // Setup system stack pointer + + + /* Save the remaining time-slice and disable it. */ + /* if (_tx_timer_time_slice) + { */ + + LDR x3, =_tx_timer_time_slice // Pickup time-slice variable address + LDR w2, [x3, x8, LSL #2] // Pickup time-slice + CMP w2, #0 // Is it active? + BEQ __tx_thread_dont_save_ts // No, don't save it + + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + STR w2, [x0, #36] // Save thread's time-slice + MOV w2, #0 // Clear value + STR w2, [x3, x8, LSL #2] // Disable global time-slice flag + + /* } */ +__tx_thread_dont_save_ts: + + + /* Clear the current task pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + MOV x2, #0 // NULL value + STR x2, [x1, x8, LSL #3] // Clear current thread pointer + + /* Set bit indicating this thread is ready for execution. */ + + MOV x2, #1 // Build ready flag + DMB ISH // Ensure that accesses to shared resource have completed + STR w2, [x0, #260] // Set thread's ready flag + + /* Return to the scheduler. */ + /* _tx_thread_schedule(); */ + + /* } */ + +__tx_thread_idle_system_restore: + + /* Just return back to the scheduler! */ + + LDR x1, =_tx_thread_schedule // Build address for _tx_thread_schedule +#ifdef EL1 + MSR ELR_EL1, x1 // Setup point of interrupt +// MOV x1, #0x4 // Setup EL1 return +// MSR spsr_el1, x1 // Move into SPSR +#else +#ifdef EL2 + MSR ELR_EL2, x1 // Setup point of interrupt +// MOV x1, #0x8 // Setup EL2 return +// MSR spsr_el2, x1 // Move into SPSR +#else + MSR ELR_EL3, x1 // Setup point of interrupt +// MOV x1, #0xC // Setup EL3 return +// MSR spsr_el3, x1 // Move into SPSR +#endif +#endif + ERET // Return to scheduler +/* } */ + + diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_context_save.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_context_save.S new file mode 100644 index 00000000..3152c49e --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_context_save.S @@ -0,0 +1,249 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save Cortex-A5x-SMP/AC6 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_save(VOID) +{ */ + .global _tx_thread_context_save + .type _tx_thread_context_save, @function +_tx_thread_context_save: + + /* Upon entry to this routine, it is assumed that IRQ/FIQ interrupts are locked + out, x29 (frame pointer), x30 (link register) are saved, we are in the proper EL, + and all other registers are intact. */ + + /* Check for a nested interrupt condition. */ + /* if (_tx_thread_system_state++) + { */ + + STP x0, x1, [sp, #-16]! // Save x0, x1 + STP x2, x3, [sp, #-16]! // Save x2, x3 + + /* Pickup the CPU ID. */ + + MRS x1, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x2, x1, #8, #8 // Isolate cluster ID +#endif + UBFX x1, x1, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x1, x1, x2, LSL #2 // Calculate CPU ID +#endif + + LDR x3, =_tx_thread_system_state // Pickup address of system state var + LDR w2, [x3, x1, LSL #2] // Pickup system state + CMP w2, #0 // Is this the first interrupt? + BEQ __tx_thread_not_nested_save // Yes, not a nested context save + + /* Nested interrupt condition. */ + + ADD w2, w2, #1 // Increment the nested interrupt counter + STR w2, [x3, x1, LSL #2] // Store it back in the variable + + /* Save the rest of the scratch registers on the stack and return to the + calling ISR. */ + + STP x4, x5, [sp, #-16]! // Save x4, x5 + STP x6, x7, [sp, #-16]! // Save x6, x7 + STP x8, x9, [sp, #-16]! // Save x8, x9 + STP x10, x11, [sp, #-16]! // Save x10, x11 + STP x12, x13, [sp, #-16]! // Save x12, x13 + STP x14, x15, [sp, #-16]! // Save x14, x15 + STP x16, x17, [sp, #-16]! // Save x16, x17 + STP x18, x19, [sp, #-16]! // Save x18, x19 +#ifdef EL1 + MRS x0, SPSR_EL1 // Pickup SPSR + MRS x1, ELR_EL1 // Pickup ELR (point of interrupt) +#else +#ifdef EL2 + MRS x0, SPSR_EL2 // Pickup SPSR + MRS x1, ELR_EL2 // Pickup ELR (point of interrupt) +#else + MRS x0, SPSR_EL3 // Pickup SPSR + MRS x1, ELR_EL3 // Pickup ELR (point of interrupt) +#endif +#endif + STP x0, x1, [sp, #-16]! // Save SPSR, ELR + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + STP x29, x30, [sp, #-16]! // Save x29, x30 + BL _tx_execution_isr_enter // Call the ISR enter function + LDP x29, x30, [sp], #16 // Recover x29, x30 +#endif + + /* Return to the ISR. */ + + RET // Return to ISR + +__tx_thread_not_nested_save: + /* } */ + + /* Otherwise, not nested, check to see if a thread was running. */ + /* else if (_tx_thread_current_ptr) + { */ + + ADD w2, w2, #1 // Increment the interrupt counter + STR w2, [x3, x1, LSL #2] // Store it back in the variable + LDR x2, =_tx_thread_current_ptr // Pickup address of current thread ptr + LDR x0, [x2, x1, LSL #3] // Pickup current thread pointer + CMP x0, #0 // Is it NULL? + BEQ __tx_thread_idle_system_save // If so, interrupt occurred in + // scheduling loop - nothing needs saving! + + /* Save minimal context of interrupted thread. */ + + STP x4, x5, [sp, #-16]! // Save x4, x5 + STP x6, x7, [sp, #-16]! // Save x6, x7 + STP x8, x9, [sp, #-16]! // Save x8, x9 + STP x10, x11, [sp, #-16]! // Save x10, x11 + STP x12, x13, [sp, #-16]! // Save x12, x13 + STP x14, x15, [sp, #-16]! // Save x14, x15 + STP x16, x17, [sp, #-16]! // Save x16, x17 + STP x18, x19, [sp, #-16]! // Save x18, x19 +#ifdef EL1 + MRS x4, SPSR_EL1 // Pickup SPSR + MRS x5, ELR_EL1 // Pickup ELR (point of interrupt) +#else +#ifdef EL2 + MRS x4, SPSR_EL2 // Pickup SPSR + MRS x5, ELR_EL2 // Pickup ELR (point of interrupt) +#else + MRS x4, SPSR_EL3 // Pickup SPSR + MRS x5, ELR_EL3 // Pickup ELR (point of interrupt) +#endif +#endif + STP x4, x5, [sp, #-16]! // Save SPSR, ELR + + /* Save the current stack pointer in the thread's control block. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + + MOV x4, sp // + STR x4, [x0, #8] // Save thread stack pointer + + /* Switch to the system stack. */ + /* sp = _tx_thread_system_stack_ptr; */ + + LDR x3, =_tx_thread_system_stack_ptr // Pickup address of system stack + MRS x1, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x2, x1, #8, #8 // Isolate cluster ID +#endif + UBFX x1, x1, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x1, x1, x2, LSL #2 // Calculate CPU ID +#endif + + LDR x4, [x3, x1, LSL #3] // Pickup system stack pointer + MOV sp, x4 // Setup system stack pointer + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + STP x29, x30, [sp, #-16]! // Save x29, x30 + BL _tx_execution_isr_enter // Call the ISR enter function + LDP x29, x30, [sp], #16 // Recover x29, x30 +#endif + + RET // Return to caller + + /* } + else + { */ + +__tx_thread_idle_system_save: + + /* Interrupt occurred in the scheduling loop. */ + + /* Not much to do here, just adjust the stack pointer, and return to IRQ + processing. */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + STP x29, x30, [sp, #-16]! // Save x29, x30 + BL _tx_execution_isr_enter // Call the ISR enter function + LDP x29, x30, [sp], #16 // Recover x29, x30 +#endif + + ADD sp, sp, #48 // Recover saved registers + RET // Continue IRQ processing + + /* } +} */ + + diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_fp_disable.c b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_fp_disable.c new file mode 100644 index 00000000..9ebe0e0e --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_fp_disable.c @@ -0,0 +1,95 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fp_disable Cortex-A5x-SMP/AC6 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function disables the FP for the currently executing thread. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_fp_disable(VOID) +{ + +TX_THREAD *thread_ptr; +ULONG system_state; + + + /* Pickup the current thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr); + + /* Get the system state. */ + system_state = TX_THREAD_GET_SYSTEM_STATE(); + + /* Make sure it is not NULL. */ + if (thread_ptr != TX_NULL) + { + + /* Thread is running... make sure the call is from the thread context. */ + if (system_state == 0) + { + + /* Yes, now set the FP enable flag to false in the TX_THREAD structure. */ + thread_ptr -> tx_thread_fp_enable = TX_FALSE; + } + } +} + diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_fp_enable.c b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_fp_enable.c new file mode 100644 index 00000000..0c32b7fd --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_fp_enable.c @@ -0,0 +1,95 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fp_enable Cortex-A5x-SMP/AC6 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function enabled the FP for the currently executing thread. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_fp_enable(VOID) +{ + +TX_THREAD *thread_ptr; +ULONG system_state; + + + /* Pickup the current thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr); + + /* Get the system state. */ + system_state = TX_THREAD_GET_SYSTEM_STATE(); + + /* Make sure it is not NULL. */ + if (thread_ptr != TX_NULL) + { + + /* Thread is running... make sure the call is from the thread context. */ + if (system_state == 0) + { + + /* Yes, now setup the FP enable flag in the TX_THREAD structure. */ + thread_ptr -> tx_thread_fp_enable = TX_TRUE; + } + } +} + diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..99a7323a --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_interrupt_control.S @@ -0,0 +1,89 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/*#define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control Cortex-A5x-SMP/AC6 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_control(UINT new_posture) +{ */ + .global _tx_thread_interrupt_control + .type _tx_thread_interrupt_control, @function +_tx_thread_interrupt_control: + + /* Pickup current interrupt lockout posture. */ + + MRS x1, DAIF // Pickup current interrupt posture + + /* Apply the new interrupt posture. */ + + MSR DAIF, x0 // Set new interrupt posture + MOV x0, x1 // Setup return value + RET // Return to caller +/* } */ + diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_interrupt_disable.S new file mode 100644 index 00000000..fb03b103 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_interrupt_disable.S @@ -0,0 +1,87 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_disable Cortex-A5x-SMP/AC6 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for disabling interrupts */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_disable(void) +{ */ + .global _tx_thread_interrupt_disable + .type _tx_thread_interrupt_disable, @function +_tx_thread_interrupt_disable: + + /* Pickup current interrupt lockout posture. */ + + MRS x0, DAIF // Pickup current interrupt lockout posture + + /* Mask interrupts. */ + + MSR DAIFSet, 0x3 // Lockout interrupts + RET // Return to caller +/* } */ + diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_interrupt_restore.S new file mode 100644 index 00000000..baf8543c --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_interrupt_restore.S @@ -0,0 +1,85 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_restore Cortex-A5x-SMP/AC6 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for restoring interrupts to the state */ +/* returned by a previous _tx_thread_interrupt_disable call. */ +/* */ +/* INPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_restore(UINT old_posture) +{ */ + .global _tx_thread_interrupt_restore + .type _tx_thread_interrupt_restore, @function +_tx_thread_interrupt_restore: + + /* Restore the old interrupt posture. */ + + MSR DAIF, x0 // Setup the old posture + RET // Return to caller + +/* } */ + diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_schedule.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_schedule.S new file mode 100644 index 00000000..be186a65 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_schedule.S @@ -0,0 +1,307 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule Cortex-A5x-SMP/AC6 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* _tx_thread_context_restore Restore thread's context */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_schedule(VOID) +{ */ + .global _tx_thread_schedule + .type _tx_thread_schedule, @function +_tx_thread_schedule: + + /* Enable interrupts. */ + + MSR DAIFClr, 0x3 // Enable interrupts + + /* Pickup the CPU ID. */ + + MRS x20, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x1, x20, #8, #8 // Isolate cluster ID +#endif + UBFX x20, x20, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x20, x20, x1, LSL #2 // Calculate CPU ID +#endif + + /* Wait for a thread to execute. */ + /* do + { */ + + LDR x1, =_tx_thread_execute_ptr // Address of thread execute ptr + +#ifdef TX_ENABLE_WFI +__tx_thread_schedule_loop: + MSR DAIFSet, 0x3 // Lockout interrupts + LDR x0, [x1, x20, LSL #3] // Pickup next thread to execute + CMP x0, #0 // Is it NULL? + BNE _tx_thread_schedule_thread // + MSR DAIFClr, 0x3 // Enable interrupts + WFI // + B __tx_thread_schedule_loop // Keep looking for a thread +_tx_thread_schedule_thread: +#else + MSR DAIFSet, 0x3 // Lockout interrupts + LDR x0, [x1, x20, LSL #3] // Pickup next thread to execute + CMP x0, #0 // Is it NULL? + BEQ _tx_thread_schedule // Keep looking for a thread +#endif + + /* } + while(_tx_thread_execute_ptr == TX_NULL); */ + + /* Get the lock for accessing the thread's ready bit. */ + + MOV w2, #280 // Build offset to the lock + ADD x2, x0, x2 // Get the address to the lock + LDAXR w3, [x2] // Pickup the lock value + CMP w3, #0 // Check if it's available + BNE _tx_thread_schedule // No, lock not available + MOV w3, #1 // Build the lock set value + STXR w4, w3, [x2] // Try to get the lock + CMP w4, #0 // Check if we got the lock + BNE _tx_thread_schedule // No, another core got it first + DMB ISH // Ensure write to lock completes + + /* Now make sure the thread's ready bit is set. */ + + LDR w3, [x0, #260] // Pickup the thread ready bit + CMP w3, #0 // Is it set? + BNE _tx_thread_ready_for_execution // Yes, schedule the thread + + /* The ready bit isn't set. Release the lock and jump back to the scheduler. */ + + MOV w3, #0 // Build clear value + STR w3, [x2] // Release the lock + DMB ISH // Ensure write to lock completes + B _tx_thread_schedule // Jump back to the scheduler + +_tx_thread_ready_for_execution: + + /* We have a thread to execute. */ + + /* Clear the ready bit and release the lock. */ + + MOV w3, #0 // Build clear value + STR w3, [x0, #260] // Store it back in the thread control block + DMB ISH + MOV w3, #0 // Build clear value for the lock + STR w3, [x2] // Release the lock + DMB ISH + + /* Setup the current thread pointer. */ + /* _tx_thread_current_ptr = _tx_thread_execute_ptr; */ + + LDR x2, =_tx_thread_current_ptr // Pickup address of current thread + STR x0, [x2, x20, LSL #3] // Setup current thread pointer + + LDR x1, [x1, x20, LSL #3] // Reload the execute pointer + CMP w0, w1 // Did it change? + BEQ _execute_pointer_did_not_change // If not, skip handling + + /* In the time between reading the execute pointer and assigning + it to the current pointer, the execute pointer was changed by + some external code. If the current pointer was still null when + the external code checked if a core preempt was necessary, then + it wouldn't have done it and a preemption will be missed. To + handle this, undo some things and jump back to the scheduler so + it can schedule the new thread. */ + + MOV w1, #0 // Build clear value + STR x1, [x2, x20, LSL #3] // Clear current thread pointer + + MOV w1, #1 // Build set value + STR w1, [x0, #260] // Re-set the ready bit + DMB ISH // + + B _tx_thread_schedule // Jump back to the scheduler to schedule the new thread + +_execute_pointer_did_not_change: + /* Increment the run count for this thread. */ + /* _tx_thread_current_ptr -> tx_thread_run_count++; */ + + LDR w2, [x0, #4] // Pickup run counter + LDR w3, [x0, #36] // Pickup time-slice for this thread + ADD w2, w2, #1 // Increment thread run-counter + STR w2, [x0, #4] // Store the new run counter + + /* Setup time-slice, if present. */ + /* _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; */ + + LDR x2, =_tx_timer_time_slice // Pickup address of time slice + // variable + LDR x4, [x0, #8] // Switch stack pointers + MOV sp, x4 // + STR w3, [x2, x20, LSL #2] // Setup time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread entry function to indicate the thread is executing. */ + + MOV x19, x0 // Save x0 + BL _tx_execution_thread_enter // Call the thread execution enter function + MOV x0, x19 // Restore x0 +#endif + + /* Switch to the thread's stack. */ + /* sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; */ + + /* Determine if an interrupt frame or a synchronous task suspension frame + is present. */ + + LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL1 + CMP x5, #0 // Check for synchronous context switch (ELR_EL1 = NULL) + BEQ _tx_solicited_return +#ifdef EL1 + MSR SPSR_EL1, x4 // Setup SPSR for return + MSR ELR_EL1, x5 // Setup point of interrupt +#else +#ifdef EL2 + MSR SPSR_EL2, x4 // Setup SPSR for return + MSR ELR_EL2, x5 // Setup point of interrupt +#else + MSR SPSR_EL3, x4 // Setup SPSR for return + MSR ELR_EL3, x5 // Setup point of interrupt +#endif +#endif +#ifdef ENABLE_ARM_FP + LDR w1, [x0, #268] // Pickup FP enable flag + CMP w1, #0 // Is FP enabled? + BEQ _skip_interrupt_fp_restore // No, skip FP restore + LDP x0, x1, [sp], #16 // Pickup FPSR, FPCR + MSR FPSR, x0 // Recover FPSR + MSR FPCR, x1 // Recover FPCR + LDP q30, q31, [sp], #32 // Recover q30, q31 + LDP q28, q29, [sp], #32 // Recover q28, q29 + LDP q26, q27, [sp], #32 // Recover q26, q27 + LDP q24, q25, [sp], #32 // Recover q24, q25 + LDP q22, q23, [sp], #32 // Recover q22, q23 + LDP q20, q21, [sp], #32 // Recover q20, q21 + LDP q18, q19, [sp], #32 // Recover q18, q19 + LDP q16, q17, [sp], #32 // Recover q16, q17 + LDP q14, q15, [sp], #32 // Recover q14, q15 + LDP q12, q13, [sp], #32 // Recover q12, q13 + LDP q10, q11, [sp], #32 // Recover q10, q11 + LDP q8, q9, [sp], #32 // Recover q8, q9 + LDP q6, q7, [sp], #32 // Recover q6, q7 + LDP q4, q5, [sp], #32 // Recover q4, q5 + LDP q2, q3, [sp], #32 // Recover q2, q3 + LDP q0, q1, [sp], #32 // Recover q0, q1 +_skip_interrupt_fp_restore: +#endif + LDP x28, x29, [sp], #16 // Recover x28 + LDP x26, x27, [sp], #16 // Recover x26, x27 + LDP x24, x25, [sp], #16 // Recover x24, x25 + LDP x22, x23, [sp], #16 // Recover x22, x23 + LDP x20, x21, [sp], #16 // Recover x20, x21 + LDP x18, x19, [sp], #16 // Recover x18, x19 + LDP x16, x17, [sp], #16 // Recover x16, x17 + LDP x14, x15, [sp], #16 // Recover x14, x15 + LDP x12, x13, [sp], #16 // Recover x12, x13 + LDP x10, x11, [sp], #16 // Recover x10, x11 + LDP x8, x9, [sp], #16 // Recover x8, x9 + LDP x6, x7, [sp], #16 // Recover x6, x7 + LDP x4, x5, [sp], #16 // Recover x4, x5 + LDP x2, x3, [sp], #16 // Recover x2, x3 + LDP x0, x1, [sp], #16 // Recover x0, x1 + LDP x29, x30, [sp], #16 // Recover x29, x30 + ERET // Return to point of interrupt + +_tx_solicited_return: + +#ifdef ENABLE_ARM_FP + LDR w1, [x0, #268] // Pickup FP enable flag + CMP w1, #0 // Is FP enabled? + BEQ _skip_solicited_fp_restore // No, skip FP restore + LDP x0, x1, [sp], #16 // Pickup FPSR, FPCR + MSR FPSR, x0 // Recover FPSR + MSR FPCR, x1 // Recover FPCR + LDP q14, q15, [sp], #32 // Recover q14, q15 + LDP q12, q13, [sp], #32 // Recover q12, q13 + LDP q10, q11, [sp], #32 // Recover q10, q11 + LDP q8, q9, [sp], #32 // Recover q8, q9 +_skip_solicited_fp_restore: +#endif + LDP x27, x28, [sp], #16 // Recover x27, x28 + LDP x25, x26, [sp], #16 // Recover x25, x26 + LDP x23, x24, [sp], #16 // Recover x23, x24 + LDP x21, x22, [sp], #16 // Recover x21, x22 + LDP x19, x20, [sp], #16 // Recover x19, x20 + LDP x29, x30, [sp], #16 // Recover x29, x30 + MSR DAIF, x4 // Recover DAIF + RET // Return to caller +/* } */ + + diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_core_get.S new file mode 100644 index 00000000..9d1fc758 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_core_get.S @@ -0,0 +1,89 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_core_get Cortex-A5x-SMP/AC6 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets the currently running core number and returns it.*/ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* Core ID */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Source */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_core_get + .type _tx_thread_smp_core_get, @function +_tx_thread_smp_core_get: + MRS x0, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x1, x0, #8, #8 // Isolate cluster ID +#endif + UBFX x0, x0, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x0, x0, x1, LSL #2 // Calculate CPU ID +#endif + RET + + diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_core_preempt.S new file mode 100644 index 00000000..0e615059 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_core_preempt.S @@ -0,0 +1,87 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_core_preempt Cortex-A5x-SMP/AC6 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function preempts the specified core in situations where the */ +/* thread corresponding to this core is no longer ready or when the */ +/* core must be used for a higher-priority thread. If the specified is */ +/* the current core, this processing is skipped since the will give up */ +/* control subsequently on its own. */ +/* */ +/* INPUT */ +/* */ +/* core The core to preempt */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Source */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_core_preempt + .type _tx_thread_smp_core_preempt, @function +_tx_thread_smp_core_preempt: + DSB ISH + MOV x2, #0x1 // + LSL x2, x2, x0 // Shift by the core ID + MSR ICC_SGI1R_EL1, x2 // Issue inter-core interrupt + RET + diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_current_state_get.S new file mode 100644 index 00000000..8b9d5dc3 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_current_state_get.S @@ -0,0 +1,95 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_current_state_get Cortex-A5x-SMP/AC6 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is gets the current state of the calling core. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_current_state_get + .type _tx_thread_smp_current_state_get, @function +_tx_thread_smp_current_state_get: + + MRS x1, DAIF // Pickup current interrupt posture + MSR DAIFSet, 0x3 // Lockout interrupts + MRS x2, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x3, x2, #8, #8 // Isolate cluster ID +#endif + UBFX x2, x2, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x2, x2, x3, LSL #2 // Calculate CPU ID +#endif + LDR x3, =_tx_thread_system_state // Pickup the base of the current system state array + LDR w0, [x3, x2, LSL #2] // Pickup the current system state for this core + MSR DAIF, x1 // Restore interrupt posture + RET + + diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_current_thread_get.S new file mode 100644 index 00000000..2013d4e6 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_current_thread_get.S @@ -0,0 +1,94 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_current_thread_get Cortex-A5x-SMP/AC6 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is gets the current thread of the calling core. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_current_thread_get + .type _tx_thread_smp_current_thread_get, @function +_tx_thread_smp_current_thread_get: + + MRS x1, DAIF // Pickup current interrupt posture + MSR DAIFSet, 0x3 // Lockout interrupts + MRS x2, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x3, x2, #8, #8 // Isolate cluster ID +#endif + UBFX x2, x2, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x2, x2, x3, LSL #2 // Calculate CPU ID +#endif + LDR x3, =_tx_thread_current_ptr // Pickup the base of the current thread pointer array + LDR x0, [x3, x2, LSL #3] // Pickup the current thread pointer for this core + MSR DAIF, x1 // Restore interrupt posture + RET + diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_initialize_wait.S new file mode 100644 index 00000000..d81a2654 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_initialize_wait.S @@ -0,0 +1,143 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_initialize_wait Cortex-A5x-SMP/AC6 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is the place where additional cores wait until */ +/* initialization is complete before they enter the thread scheduling */ +/* loop. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* Hardware */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_initialize_wait + .type _tx_thread_smp_initialize_wait, @function +_tx_thread_smp_initialize_wait: + + /* Lockout interrupts. */ + + MSR DAIFSet, 0x3 // Lockout interrupts + + /* Pickup the Core ID. */ + + MRS x2, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x3, x2, #8, #8 // Isolate cluster ID +#endif + UBFX x2, x2, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x2, x2, x3, LSL #2 // Calculate CPU ID +#endif + + /* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release + flag. */ + + LDR w1, =0xF0F0F0F0 // Build TX_INITIALIZE_IN_PROGRESS flag + LDR x3, =_tx_thread_system_state // Pickup the base of the current system state array +wait_for_initialize: + LDR w0, [x3, x2, LSL #2] // Pickup the current system state for this core + CMP w0, w1 // Make sure the TX_INITIALIZE_IN_PROGRESS flag is set + BNE wait_for_initialize // Not equal, just spin here + + /* Save the system stack pointer for this core. */ + + LDR x0, =_tx_thread_system_stack_ptr // Pickup address of system stack ptr + MOV x1, sp // Pickup SP + SUB x1, x1, #15 // + BIC x1, x1, #0xF // Get 16-bit alignment + STR x1, [x0, x2, LSL #3] // Store system stack pointer + + + /* Pickup the release cores flag. */ + + LDR x4, =_tx_thread_smp_release_cores_flag // Build address of release cores flag +wait_for_release: + LDR w0, [x4, #0] // Pickup the flag + CMP w0, #0 // Is it set? + BEQ wait_for_release // Wait for the flag to be set + + /* Core 0 has released this core. */ + + /* Clear this core's system state variable. */ + + MOV x0, #0 // Build clear value + STR w0, [x3, x2, LSL #2] // Set the current system state for this core to zero + + /* Now wait for core 0 to finish it's initialization. */ + +core_0_wait_loop: + LDR w0, [x3, #0] // Pickup the current system state for core 0 + CMP w0, #0 // Is it 0? + BNE core_0_wait_loop // No, keep waiting for core 0 to finish its initialization + + /* Initialization is complete, enter the scheduling loop! */ + + B _tx_thread_schedule // Enter the scheduling loop for this core + + RET + diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_low_level_initialize.S new file mode 100644 index 00000000..a3cf8f62 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_low_level_initialize.S @@ -0,0 +1,80 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_low_level_initialize Cortex-A5x-SMP/AC6 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function performs low-level initialization of the booting */ +/* core. */ +/* */ +/* INPUT */ +/* */ +/* number_of_cores Number of cores */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_high_level ThreadX high-level init */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_low_level_initialize + .type _tx_thread_smp_low_level_initialize, @function +_tx_thread_smp_low_level_initialize: + + RET diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_protect.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_protect.S new file mode 100644 index 00000000..0046488d --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_protect.S @@ -0,0 +1,364 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + +/* Include macros for modifying the wait list. */ +#include "tx_thread_smp_protection_wait_list_macros.h" + + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_protect Cortex-A5x-SMP/AC6 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets protection for running inside the ThreadX */ +/* source. This is acomplished by a combination of a test-and-set */ +/* flag and periodically disabling interrupts. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* Previous Status Register */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Source */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_protect + .type _tx_thread_smp_protect, @function +_tx_thread_smp_protect: + + /* Disable interrupts so we don't get preempted. */ + + MRS x0, DAIF // Pickup current interrupt posture + MSR DAIFSet, 0x3 // Lockout interrupts + + /* Pickup the CPU ID. */ + + MRS x1, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x7, x1, #8, #8 // Isolate cluster ID +#endif + UBFX x1, x1, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x1, x1, x7, LSL #2 // Calculate CPU ID +#endif + + /* Do we already have protection? */ + /* if (this_core == _tx_thread_smp_protection.tx_thread_smp_protect_core) + { */ + + LDR x2, =_tx_thread_smp_protection // Build address to protection structure + LDR w3, [x2, #4] // Pickup the owning core + CMP w1, w3 // Is it not this core? + BNE _protection_not_owned // No, the protection is not already owned + + /* We already have protection. */ + + /* Increment the protection count. */ + /* _tx_thread_smp_protection.tx_thread_smp_protect_count++; */ + + LDR w3, [x2, #8] // Pickup ownership count + ADD w3, w3, #1 // Increment ownership count + STR w3, [x2, #8] // Store ownership count + DMB ISH + + B _return + +_protection_not_owned: + + /* Is the lock available? */ + /* if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0) + { */ + + LDAXR w3, [x2, #0] // Pickup the protection flag + CMP w3, #0 + BNE _start_waiting // No, protection not available + + /* Is the list empty? */ + /* if (_tx_thread_smp_protect_wait_list_head == _tx_thread_smp_protect_wait_list_tail) + { */ + + LDR x3, =_tx_thread_smp_protect_wait_list_head + LDR w3, [x3] + LDR x4, =_tx_thread_smp_protect_wait_list_tail + LDR w4, [x4] + CMP w3, w4 + BNE _list_not_empty + + /* Try to get the lock. */ + /* if (write_exclusive(&_tx_thread_smp_protection.tx_thread_smp_protect_in_force, 1) == SUCCESS) + { */ + + MOV w3, #1 // Build lock value + STXR w4, w3, [x2, #0] // Attempt to get the protection + CMP w4, #0 + BNE _start_waiting // Did it fail? + + /* We got the lock! */ + /* _tx_thread_smp_protect_lock_got(); */ + + DMB ISH // Ensure write to protection finishes + _tx_thread_smp_protect_lock_got // Call the lock got function + + B _return + +_list_not_empty: + + /* Are we at the front of the list? */ + /* if (this_core == _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head]) + { */ + + LDR x3, =_tx_thread_smp_protect_wait_list_head // Get the address of the head + LDR w3, [x3] // Get the value of the head + LDR x4, =_tx_thread_smp_protect_wait_list // Get the address of the list + LDR w4, [x4, x3, LSL #2] // Get the value at the head index + + CMP w1, w4 + BNE _start_waiting + + /* Is the lock still available? */ + /* if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0) + { */ + + LDR w3, [x2, #0] // Pickup the protection flag + CMP w3, #0 + BNE _start_waiting // No, protection not available + + /* Get the lock. */ + /* _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1; */ + + MOV w3, #1 // Build lock value + STR w3, [x2, #0] // Store lock value + DMB ISH // + + /* Got the lock. */ + /* _tx_thread_smp_protect_lock_got(); */ + + _tx_thread_smp_protect_lock_got + + /* Remove this core from the wait list. */ + /* _tx_thread_smp_protect_remove_from_front_of_list(); */ + + _tx_thread_smp_protect_remove_from_front_of_list + + B _return + +_start_waiting: + + /* For one reason or another, we didn't get the lock. */ + + /* Increment wait count. */ + /* _tx_thread_smp_protect_wait_counts[this_core]++; */ + + LDR x3, =_tx_thread_smp_protect_wait_counts // Load wait list counts + LDR w4, [x3, x1, LSL #2] // Load waiting value for this core + ADD w4, w4, #1 // Increment wait value + STR w4, [x3, x1, LSL #2] // Store new wait value + + /* Have we not added ourselves to the list yet? */ + /* if (_tx_thread_smp_protect_wait_counts[this_core] == 1) + { */ + + CMP w4, #1 + BNE _already_in_list0 // Is this core already waiting? + + /* Add ourselves to the list. */ + /* _tx_thread_smp_protect_wait_list_add(this_core); */ + + _tx_thread_smp_protect_wait_list_add // Call macro to add ourselves to the list + + /* } */ + +_already_in_list0: + + /* Restore interrupts. */ + + MSR DAIF, x0 // Restore interrupts + ISB // +#ifdef TX_ENABLE_WFE + WFE // Go into standby +#endif + + /* We do this until we have the lock. */ + /* while (1) + { */ + +_try_to_get_lock: + + /* Disable interrupts so we don't get preempted. */ + + MRS x0, DAIF // Pickup current interrupt posture + MSR DAIFSet, 0x3 // Lockout interrupts + + /* Pickup the CPU ID. */ + + MRS x1, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x7, x1, #8, #8 // Isolate cluster ID +#endif + UBFX x1, x1, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x1, x1, x7, LSL #2 // Calculate CPU ID +#endif + + /* Do we already have protection? */ + /* if (this_core == _tx_thread_smp_protection.tx_thread_smp_protect_core) + { */ + + LDR w3, [x2, #4] // Pickup the owning core + CMP w3, w1 // Is it this core? + BEQ _got_lock_after_waiting // Yes, the protection is already owned. This means + // an ISR preempted us and got protection + + /* } */ + + /* Are we at the front of the list? */ + /* if (this_core == _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head]) + { */ + + LDR x3, =_tx_thread_smp_protect_wait_list_head // Get the address of the head + LDR w3, [x3] // Get the value of the head + LDR x4, =_tx_thread_smp_protect_wait_list // Get the address of the list + LDR w4, [x4, x3, LSL #2] // Get the value at the head index + + CMP w1, w4 + BNE _did_not_get_lock + + /* Is the lock still available? */ + /* if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0) + { */ + + LDR w3, [x2, #0] // Pickup the protection flag + CMP w3, #0 + BNE _did_not_get_lock // No, protection not available + + /* Get the lock. */ + /* _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1; */ + + MOV w3, #1 // Build lock value + STR w3, [x2, #0] // Store lock value + DMB ISH // + + /* Got the lock. */ + /* _tx_thread_smp_protect_lock_got(); */ + + _tx_thread_smp_protect_lock_got + + /* Remove this core from the wait list. */ + /* _tx_thread_smp_protect_remove_from_front_of_list(); */ + + _tx_thread_smp_protect_remove_from_front_of_list + + B _got_lock_after_waiting + +_did_not_get_lock: + + /* For one reason or another, we didn't get the lock. */ + + /* Were we removed from the list? This can happen if we're a thread + and we got preempted. */ + /* if (_tx_thread_smp_protect_wait_counts[this_core] == 0) + { */ + + LDR x3, =_tx_thread_smp_protect_wait_counts // Load wait list counts + LDR w4, [x3, x1, LSL #2] // Load waiting value for this core + CMP w4, #0 + BNE _already_in_list1 // Is this core already in the list? + + /* Add ourselves to the list. */ + /* _tx_thread_smp_protect_wait_list_add(this_core); */ + + _tx_thread_smp_protect_wait_list_add // Call macro to add ourselves to the list + + /* Our waiting count was also reset when we were preempted. Increment it again. */ + /* _tx_thread_smp_protect_wait_counts[this_core]++; */ + + LDR x3, =_tx_thread_smp_protect_wait_counts // Load wait list counts + LDR w4, [x3, x1, LSL #2] // Load waiting value for this core + ADD w4, w4, #1 // Increment wait value + STR w4, [x3, x1, LSL #2] // Store new wait value value + + /* } */ + +_already_in_list1: + + /* Restore interrupts and try again. */ + + MSR DAIF, x0 // Restore interrupts + ISB // +#ifdef TX_ENABLE_WFE + WFE // Go into standby +#endif + B _try_to_get_lock // On waking, restart the protection attempt + +_got_lock_after_waiting: + + /* We're no longer waiting. */ + /* _tx_thread_smp_protect_wait_counts[this_core]--; */ + + LDR x3, =_tx_thread_smp_protect_wait_counts // Load waiting list + LDR w4, [x3, x1, LSL #2] // Load current wait value + SUB w4, w4, #1 // Decrement wait value + STR w4, [x3, x1, LSL #2] // Store new wait value value + + /* Restore registers and return. */ + +_return: + + RET + diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h new file mode 100644 index 00000000..5c33d940 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_protection_wait_list_macros.h @@ -0,0 +1,296 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .macro _tx_thread_smp_protect_lock_got + + /* Set the currently owned core. */ + /* _tx_thread_smp_protection.tx_thread_smp_protect_core = this_core; */ + + STR w1, [x2, #4] // Store this core + + /* Increment the protection count. */ + /* _tx_thread_smp_protection.tx_thread_smp_protect_count++; */ + + LDR w3, [x2, #8] // Pickup ownership count + ADD w3, w3, #1 // Increment ownership count + STR w3, [x2, #8] // Store ownership count + DMB ISH + + .endm + + .macro _tx_thread_smp_protect_remove_from_front_of_list + + /* Remove ourselves from the list. */ + /* _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head++] = 0xFFFFFFFF; */ + + MOV w3, #0xFFFFFFFF // Build the invalid core value + LDR x4, =_tx_thread_smp_protect_wait_list_head // Get the address of the head + LDR w5, [x4] // Get the value of the head + LDR x6, =_tx_thread_smp_protect_wait_list // Get the address of the list + STR w3, [x6, x5, LSL #2] // Store the invalid core value + ADD w5, w5, #1 // Increment the head + + /* Did we wrap? */ + /* if (_tx_thread_smp_protect_wait_list_head == TX_THREAD_SMP_MAX_CORES + 1) + { */ + + LDR x3, =_tx_thread_smp_protect_wait_list_size // Load address of core list size + LDR w3, [x3] // Load the max cores value + CMP w5, w3 // Compare the head to it + BNE _store_new_head\@ // Are we at the max? + + /* _tx_thread_smp_protect_wait_list_head = 0; */ + + EOR w5, w5, w5 // We're at the max. Set it to zero + + /* } */ + +_store_new_head\@: + + STR w5, [x4] // Store the new head + + /* We have the lock! */ + /* return; */ + + .endm + + + .macro _tx_thread_smp_protect_wait_list_lock_get +/* VOID _tx_thread_smp_protect_wait_list_lock_get() +{ */ + /* We do this until we have the lock. */ + /* while (1) + { */ + +_tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@: + + /* Is the list lock available? */ + /* _tx_thread_smp_protect_wait_list_lock_protect_in_force = load_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force); */ + + LDR x1, =_tx_thread_smp_protect_wait_list_lock_protect_in_force + LDAXR w2, [x1] // Pickup the protection flag + + /* if (protect_in_force == 0) + { */ + + CMP w2, #0 + BNE _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@ // No, protection not available + + /* Try to get the list. */ + /* int status = store_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force, 1); */ + + MOV w2, #1 // Build lock value + STXR w3, w2, [x1] // Attempt to get the protection + + /* if (status == SUCCESS) */ + + CMP w3, #0 + BNE _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@ // Did it fail? If so, try again. + + /* We have the lock! */ + /* return; */ + + .endm + + + .macro _tx_thread_smp_protect_wait_list_add +/* VOID _tx_thread_smp_protect_wait_list_add(UINT new_core) +{ */ + + /* We're about to modify the list, so get the list lock. */ + /* _tx_thread_smp_protect_wait_list_lock_get(); */ + + STP x1, x2, [sp, #-16]! // Save registers we'll be using + + _tx_thread_smp_protect_wait_list_lock_get + + LDP x1, x2, [sp], #16 + + /* Add this core. */ + /* _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_tail++] = new_core; */ + + LDR x3, =_tx_thread_smp_protect_wait_list_tail // Get the address of the tail + LDR w4, [x3] // Get the value of tail + LDR x5, =_tx_thread_smp_protect_wait_list // Get the address of the list + STR w1, [x5, x4, LSL #2] // Store the new core value + ADD w4, w4, #1 // Increment the tail + + /* Did we wrap? */ + /* if (_tx_thread_smp_protect_wait_list_tail == _tx_thread_smp_protect_wait_list_size) + { */ + + LDR x5, =_tx_thread_smp_protect_wait_list_size // Load max cores address + LDR w5, [x5] // Load max cores value + CMP w4, w5 // Compare max cores to tail + BNE _tx_thread_smp_protect_wait_list_add__no_wrap\@ // Did we wrap? + + /* _tx_thread_smp_protect_wait_list_tail = 0; */ + + MOV w4, #0 + + /* } */ + +_tx_thread_smp_protect_wait_list_add__no_wrap\@: + + STR w4, [x3] // Store the new tail value. + + /* Release the list lock. */ + /* _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; */ + + MOV w3, #0 // Build lock value + LDR x4, =_tx_thread_smp_protect_wait_list_lock_protect_in_force + STR w3, [x4] // Store the new value + + .endm + + + .macro _tx_thread_smp_protect_wait_list_remove +/* VOID _tx_thread_smp_protect_wait_list_remove(UINT core) +{ */ + + /* Get the core index. */ + /* UINT core_index; + for (core_index = 0;; core_index++) */ + + EOR w4, w4, w4 // Clear for 'core_index' + LDR x2, =_tx_thread_smp_protect_wait_list // Get the address of the list + + /* { */ + +_tx_thread_smp_protect_wait_list_remove__check_cur_core\@: + + /* Is this the core? */ + /* if (_tx_thread_smp_protect_wait_list[core_index] == core) + { + break; */ + + LDR w3, [x2, x4, LSL #2] // Get the value at the current index + CMP w3, w8 // Did we find the core? + BEQ _tx_thread_smp_protect_wait_list_remove__found_core\@ + + /* } */ + + ADD w4, w4, #1 // Increment cur index + B _tx_thread_smp_protect_wait_list_remove__check_cur_core\@ // Restart the loop + + /* } */ + +_tx_thread_smp_protect_wait_list_remove__found_core\@: + + /* We're about to modify the list. Get the lock. We need the lock because another + core could be simultaneously adding (a core is simultaneously trying to get + the inter-core lock) or removing (a core is simultaneously being preempted, + like what is currently happening). */ + /* _tx_thread_smp_protect_wait_list_lock_get(); */ + + MOV x6, x1 + _tx_thread_smp_protect_wait_list_lock_get + MOV x1, x6 + + /* We remove by shifting. */ + /* while (core_index != _tx_thread_smp_protect_wait_list_tail) + { */ + +_tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@: + + LDR x2, =_tx_thread_smp_protect_wait_list_tail // Load tail address + LDR w2, [x2] // Load tail value + CMP w4, w2 // Compare cur index and tail + BEQ _tx_thread_smp_protect_wait_list_remove__removed\@ + + /* UINT next_index = core_index + 1; */ + + MOV w2, w4 // Move current index to next index register + ADD w2, w2, #1 // Add 1 + + /* if (next_index == _tx_thread_smp_protect_wait_list_size) + { */ + + LDR x3, =_tx_thread_smp_protect_wait_list_size + LDR w3, [x3] + CMP w2, w3 + BNE _tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@ + + /* next_index = 0; */ + + MOV w2, #0 + + /* } */ + +_tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@: + + /* list_cores[core_index] = list_cores[next_index]; */ + + LDR x5, =_tx_thread_smp_protect_wait_list // Get the address of the list + LDR w3, [x5, x2, LSL #2] // Get the value at the next index + STR w3, [x5, x4, LSL #2] // Store the value at the current index + + /* core_index = next_index; */ + + MOV w4, w2 + + B _tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@ + + /* } */ + +_tx_thread_smp_protect_wait_list_remove__removed\@: + + /* Now update the tail. */ + /* if (_tx_thread_smp_protect_wait_list_tail == 0) + { */ + + LDR x5, =_tx_thread_smp_protect_wait_list_tail // Load tail address + LDR w4, [x5] // Load tail value + CMP w4, #0 + BNE _tx_thread_smp_protect_wait_list_remove__tail_not_zero\@ + + /* _tx_thread_smp_protect_wait_list_tail = _tx_thread_smp_protect_wait_list_size; */ + + LDR x2, =_tx_thread_smp_protect_wait_list_size + LDR w4, [x2] + + /* } */ + +_tx_thread_smp_protect_wait_list_remove__tail_not_zero\@: + + /* _tx_thread_smp_protect_wait_list_tail--; */ + + SUB w4, w4, #1 + STR w4, [x5] // Store new tail value + + /* Release the list lock. */ + /* _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; */ + + MOV w2, #0 // Build lock value + LDR x4, =_tx_thread_smp_protect_wait_list_lock_protect_in_force // Load lock address + STR w2, [x4] // Store the new value + + /* We're no longer waiting. Note that this should be zero since, again, + this function is only called when a thread preemption is occurring. */ + /* _tx_thread_smp_protect_wait_counts[core]--; */ + LDR x4, =_tx_thread_smp_protect_wait_counts // Load wait list counts + LDR w2, [x4, x8, LSL #2] // Load waiting value + SUB w2, w2, #1 // Subtract 1 + STR w2, [x4, x8, LSL #2] // Store new waiting value + + .endm + diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_time_get.S new file mode 100644 index 00000000..1d2f4a96 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_time_get.S @@ -0,0 +1,83 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_time_get Cortex-A5x-SMP/AC6 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets the global time value that is used for debug */ +/* information and event tracing. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* 32-bit time stamp */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Source */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_time_get + .type _tx_thread_smp_time_get, @function +_tx_thread_smp_time_get: + MOV x0, #0 // FIXME: Get timer + RET + + diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_unprotect.S new file mode 100644 index 00000000..f8c31e60 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_smp_unprotect.S @@ -0,0 +1,130 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_unprotect Cortex-A5x-SMP/AC6 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function releases previously obtained protection. The supplied */ +/* previous SR is restored. If the value of _tx_thread_system_state */ +/* and _tx_thread_preempt_disable are both zero, then multithreading */ +/* is enabled as well. */ +/* */ +/* INPUT */ +/* */ +/* Previous Status Register */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Source */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_unprotect + .type _tx_thread_smp_unprotect, @function +_tx_thread_smp_unprotect: + MSR DAIFSet, 0x3 // Lockout interrupts + + MRS x1, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x2, x1, #8, #8 // Isolate cluster ID +#endif + UBFX x1, x1, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x1, x1, x2, LSL #2 // Calculate CPU ID +#endif + + LDR x2,=_tx_thread_smp_protection // Build address of protection structure + LDR w3, [x2, #4] // Pickup the owning core + CMP w1, w3 // Is it this core? + BNE _still_protected // If this is not the owning core, protection is in force elsewhere + + LDR w3, [x2, #8] // Pickup the protection count + CMP w3, #0 // Check to see if the protection is still active + BEQ _still_protected // If the protection count is zero, protection has already been cleared + + SUB w3, w3, #1 // Decrement the protection count + STR w3, [x2, #8] // Store the new count back + CMP w3, #0 // Check to see if the protection is still active + BNE _still_protected // If the protection count is non-zero, protection is still in force + LDR x2,=_tx_thread_preempt_disable // Build address of preempt disable flag + LDR w3, [x2] // Pickup preempt disable flag + CMP w3, #0 // Is the preempt disable flag set? + BNE _still_protected // Yes, skip the protection release + + LDR x2,=_tx_thread_smp_protect_wait_counts // Build build address of wait counts + LDR w3, [x2, x1, LSL #2] // Pickup wait list value + CMP w3, #0 // Are any entities on this core waiting? + BNE _still_protected // Yes, skip the protection release + + LDR x2,=_tx_thread_smp_protection // Build address of protection structure + MOV w3, #0xFFFFFFFF // Build invalid value + STR w3, [x2, #4] // Mark the protected core as invalid + DMB ISH // Ensure that accesses to shared resource have completed + MOV w3, #0 // Build release protection value + STR w3, [x2, #0] // Release the protection + DSB ISH // To ensure update of the protection occurs before other CPUs awake + +_still_protected: +#ifdef TX_ENABLE_WFE + SEV // Send event to other CPUs, wakes anyone waiting on the protection (using WFE) +#endif + MSR DAIF, x0 // Restore interrupt posture + RET + diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_stack_build.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_stack_build.S new file mode 100644 index 00000000..e4be8b6e --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_stack_build.S @@ -0,0 +1,172 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build Cortex-A5x-SMP/AC6 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +{ */ + .global _tx_thread_stack_build + .type _tx_thread_stack_build, @function +_tx_thread_stack_build: + + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-A5x should look like the following after it is built: + + Stack Top: SSPR Initial SSPR + ELR Point of interrupt + x28 Initial value for x28 + not used Not used + x26 Initial value for x26 + x27 Initial value for x27 + x24 Initial value for x24 + x25 Initial value for x25 + x22 Initial value for x22 + x23 Initial value for x23 + x20 Initial value for x20 + x21 Initial value for x21 + x18 Initial value for x18 + x19 Initial value for x19 + x16 Initial value for x16 + x17 Initial value for x17 + x14 Initial value for x14 + x15 Initial value for x15 + x12 Initial value for x12 + x13 Initial value for x13 + x10 Initial value for x10 + x11 Initial value for x11 + x8 Initial value for x8 + x9 Initial value for x9 + x6 Initial value for x6 + x7 Initial value for x7 + x4 Initial value for x4 + x5 Initial value for x5 + x2 Initial value for x2 + x3 Initial value for x3 + x0 Initial value for x0 + x1 Initial value for x1 + x29 Initial value for x29 (frame pointer) + x30 Initial value for x30 (link register) + 0 For stack backtracing + + Stack Bottom: (higher memory address) */ + + LDR x4, [x0, #24] // Pickup end of stack area + BIC x4, x4, #0xF // Ensure 16-byte alignment + + /* Actually build the stack frame. */ + + MOV x2, #0 // Build clear value + MOV x3, #0 // + + STP x2, x3, [x4, #-16]! // Set backtrace to 0 + STP x2, x3, [x4, #-16]! // Set initial x29, x30 + STP x2, x3, [x4, #-16]! // Set initial x0, x1 + STP x2, x3, [x4, #-16]! // Set initial x2, x3 + STP x2, x3, [x4, #-16]! // Set initial x4, x5 + STP x2, x3, [x4, #-16]! // Set initial x6, x7 + STP x2, x3, [x4, #-16]! // Set initial x8, x9 + STP x2, x3, [x4, #-16]! // Set initial x10, x11 + STP x2, x3, [x4, #-16]! // Set initial x12, x13 + STP x2, x3, [x4, #-16]! // Set initial x14, x15 + STP x2, x3, [x4, #-16]! // Set initial x16, x17 + STP x2, x3, [x4, #-16]! // Set initial x18, x19 + STP x2, x3, [x4, #-16]! // Set initial x20, x21 + STP x2, x3, [x4, #-16]! // Set initial x22, x23 + STP x2, x3, [x4, #-16]! // Set initial x24, x25 + STP x2, x3, [x4, #-16]! // Set initial x26, x27 + STP x2, x3, [x4, #-16]! // Set initial x28 +#ifdef EL1 + MOV x2, #0x4 // Build initial SPSR (EL1) +#else +#ifdef EL2 + MOV x2, #0x8 // Build initial SPSR (EL2) +#else + MOV x2, #0xC // Build initial SPSR (EL3) +#endif +#endif + MOV x3, x1 // Build initial ELR + STP x2, x3, [x4, #-16]! // Set initial SPSR & ELR + + /* Setup stack pointer. */ + /* thread_ptr -> tx_thread_stack_ptr = x2; */ + + STR x4, [x0, #8] // Save stack pointer in thread's + MOV x3, #1 // Build ready flag + STR w3, [x0, #260] // Set ready flag + RET // Return to caller + +/* } */ + + diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_system_return.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_system_return.S new file mode 100644 index 00000000..31e3c42c --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_system_return.S @@ -0,0 +1,191 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return Cortex-A5x-SMP/AC6 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the ThreadX system. Only a */ +/* minimal context is saved since the compiler assumes temp registers */ +/* are going to get slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_system_return(VOID) +{ */ + .global _tx_thread_system_return + .type _tx_thread_system_return, @function +_tx_thread_system_return: +; +; /* Save minimal context on the stack. */ +; + MRS x0, DAIF // Pickup DAIF + MSR DAIFSet, 0x3 // Lockout interrupts + STP x29, x30, [sp, #-16]! // Save x29 (frame pointer), x30 (link register) + STP x19, x20, [sp, #-16]! // Save x19, x20 + STP x21, x22, [sp, #-16]! // Save x21, x22 + STP x23, x24, [sp, #-16]! // Save x23, x24 + STP x25, x26, [sp, #-16]! // Save x25, x26 + STP x27, x28, [sp, #-16]! // Save x27, x28 + MRS x8, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x3, x8, #8, #8 // Isolate cluster ID +#endif + UBFX x8, x8, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x8, x8, x3, LSL #2 // Calculate CPU ID +#endif + LDR x5, =_tx_thread_current_ptr // Pickup address of current ptr + LDR x6, [x5, x8, LSL #3] // Pickup current thread pointer + +#ifdef ENABLE_ARM_FP + LDR w7, [x6, #268] // Pickup FP enable flag + CMP w7, #0 // Is FP enabled? + BEQ _skip_fp_save // No, skip FP save + STP q8, q9, [sp, #-32]! // Save q8, q9 + STP q10, q11, [sp, #-32]! // Save q10, q11 + STP q12, q13, [sp, #-32]! // Save q12, q13 + STP q14, q15, [sp, #-32]! // Save q14, q15 + MRS x2, FPSR // Pickup FPSR + MRS x3, FPCR // Pickup FPCR + STP x2, x3, [sp, #-16]! // Save FPSR, FPCR +_skip_fp_save: +#endif + + MOV x1, #0 // Clear x1 + STP x0, x1, [sp, #-16]! // Save DAIF and clear value for ELR_EK1 + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread exit function to indicate the thread is no longer executing. */ + + MOV x19, x5 // Save x5 + MOV x20, x6 // Save x6 + MOV x21, x8 // Save x2 + BL _tx_execution_thread_exit // Call the thread exit function + MOV x8, x21 // Restore x2 + MOV x5, x19 // Restore x5 + MOV x6, x20 // Restore x6 +#endif + + LDR x2, =_tx_timer_time_slice // Pickup address of time slice + LDR w1, [x2, x8, LSL #2] // Pickup current time slice + + /* Save current stack and switch to system stack. */ + /* _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; */ + /* sp = _tx_thread_system_stack_ptr[core]; */ + + MOV x4, sp // + STR x4, [x6, #8] // Save thread stack pointer + LDR x3, =_tx_thread_system_stack_ptr // Pickup address of system stack + LDR x4, [x3, x8, LSL #3] // Pickup system stack pointer + MOV sp, x4 // Setup system stack pointer + + /* Determine if the time-slice is active. */ + /* if (_tx_timer_time_slice[core]) + { */ + + MOV x4, #0 // Build clear value + CMP w1, #0 // Is a time-slice active? + BEQ __tx_thread_dont_save_ts // No, don't save the time-slice + + /* Save the current remaining time-slice. */ + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + STR w4, [x2, x8, LSL #2] // Clear time-slice + STR w1, [x6, #36] // Store current time-slice + + /* } */ +__tx_thread_dont_save_ts: + + /* Clear the current thread pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + STR x4, [x5, x8, LSL #3] // Clear current thread pointer + + /* Set ready bit in thread control block. */ + + MOV x3, #1 // Build ready value + STR w3, [x6, #260] // Make the thread ready + DMB ISH // + + /* Now clear protection. It is assumed that protection is in force whenever this routine is called. */ + + LDR x3, =_tx_thread_smp_protection // Pickup address of protection structure + LDR x1, =_tx_thread_preempt_disable // Build address to preempt disable flag + STR w4, [x1, #0] // Clear preempt disable flag + STR w4, [x3, #8] // Cear protection count + MOV x1, #0xFFFFFFFF // Build invalid value + STR w1, [x3, #4] // Set core to an invalid value + DMB ISH // Ensure that accesses to shared resource have completed + STR w4, [x3, #0] // Clear protection + DSB ISH // To ensure update of the shared resource occurs before other CPUs awake + SEV // Send event to other CPUs, wakes anyone waiting on a mutex (using WFE) + B _tx_thread_schedule // Jump to scheduler! + +/* } */ + + diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_timeout.c b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_timeout.c new file mode 100644 index 00000000..6e556c92 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_thread_timeout.c @@ -0,0 +1,165 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_timeout Cortex-A5x-SMP */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles thread timeout processing. Timeouts occur in */ +/* two flavors, namely the thread sleep timeout and all other service */ +/* call timeouts. Thread sleep timeouts are processed locally, while */ +/* the others are processed by the appropriate suspension clean-up */ +/* service. */ +/* */ +/* INPUT */ +/* */ +/* timeout_input Contains the thread pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* Suspension Cleanup Functions */ +/* _tx_thread_system_resume Resume thread */ +/* _tx_thread_system_ni_resume Non-interruptable resume thread */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_timer_expiration_process Timer expiration function */ +/* _tx_timer_thread_entry Timer thread function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_timeout(ULONG timeout_input) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_THREAD *thread_ptr; +VOID (*suspend_cleanup)(struct TX_THREAD_STRUCT *suspend_thread_ptr, ULONG suspension_sequence); +ULONG suspension_sequence; + + + /* Pickup the thread pointer. */ + TX_THREAD_TIMEOUT_POINTER_SETUP(thread_ptr) + + /* Disable interrupts. */ + TX_DISABLE + + /* Determine how the thread is currently suspended. */ + if (thread_ptr -> tx_thread_state == TX_SLEEP) + { + +#ifdef TX_NOT_INTERRUPTABLE + + /* Resume the thread! */ + _tx_thread_system_ni_resume(thread_ptr); + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Increment the disable preemption flag. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Lift the suspension on the sleeping thread. */ + _tx_thread_system_resume(thread_ptr); +#endif + } + else + { + + /* Process all other suspension timeouts. */ + +#ifdef TX_THREAD_ENABLE_PERFORMANCE_INFO + + /* Increment the total number of thread timeouts. */ + _tx_thread_performance_timeout_count++; + + /* Increment the number of timeouts for this thread. */ + thread_ptr -> tx_thread_performance_timeout_count++; +#endif + + /* Pickup the cleanup routine address. */ + suspend_cleanup = thread_ptr -> tx_thread_suspend_cleanup; + +#ifndef TX_NOT_INTERRUPTABLE + + /* Pickup the suspension sequence number that is used later to verify that the + cleanup is still necessary. */ + suspension_sequence = thread_ptr -> tx_thread_suspension_sequence; +#else + + /* When not interruptable is selected, the suspension sequence is not used - just set to 0. */ + suspension_sequence = ((ULONG) 0); +#endif + +#ifndef TX_NOT_INTERRUPTABLE + + /* Restore interrupts. */ + TX_RESTORE +#endif + + /* Call any cleanup routines. */ + if (suspend_cleanup != TX_NULL) + { + + /* Yes, there is a function to call. */ + (suspend_cleanup)(thread_ptr, suspension_sequence); + } + +#ifdef TX_NOT_INTERRUPTABLE + + /* Restore interrupts. */ + TX_RESTORE +#endif + } +} + diff --git a/ports_smp/cortex_a5x_smp/ac6/src/tx_timer_interrupt.S b/ports_smp/cortex_a5x_smp/ac6/src/tx_timer_interrupt.S new file mode 100644 index 00000000..92bc19df --- /dev/null +++ b/ports_smp/cortex_a5x_smp/ac6/src/tx_timer_interrupt.S @@ -0,0 +1,198 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_timer.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt Cortex-A5x-SMP/AC6 */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_timer_interrupt(VOID) +{ */ + .global _tx_timer_interrupt + .type _tx_timer_interrupt, @function +_tx_timer_interrupt: + + MRS x2, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x3, x2, #8, #8 // Isolate cluster ID +#endif + UBFX x2, x2, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x2, x2, x3, LSL #2 // Calculate CPU ID +#endif + CMP x2, #0 // Is this core 0? + BEQ __tx_process_timer // If desired core, continue processing + RET // Simply return if different core +__tx_process_timer: + + /* Upon entry to this routine, it is assumed that context save has already + been called, and therefore the compiler scratch registers are available + for use. */ + + STP x27, x28, [sp, #-16]! // Save x27, x28 + STP x29, x30, [sp, #-16]! // Save x29 (frame pointer), x30 (link register) + + /* Get inter-core protection. */ + + BL _tx_thread_smp_protect // Get inter-core protection + MOV x28, x0 // Save the return value in preserved register + + /* Increment the system clock. */ + /* _tx_timer_system_clock++; */ + + LDR x1, =_tx_timer_system_clock // Pickup address of system clock + LDR w0, [x1, #0] // Pickup system clock + ADD w0, w0, #1 // Increment system clock + STR w0, [x1, #0] // Store new system clock + + /* Test for timer expiration. */ + /* if (*_tx_timer_current_ptr) + { */ + + LDR x1, =_tx_timer_current_ptr // Pickup current timer pointer addr + LDR x0, [x1, #0] // Pickup current timer + LDR x2, [x0, #0] // Pickup timer list entry + CMP x2, #0 // Is there anything in the list? + BEQ __tx_timer_no_timer // No, just increment the timer + + /* Set expiration flag. */ + /* _tx_timer_expired = TX_TRUE; */ + + LDR x3, =_tx_timer_expired // Pickup expiration flag address + MOV w2, #1 // Build expired value + STR w2, [x3, #0] // Set expired flag + B __tx_timer_done // Finished timer processing + + /* } + else + { */ +__tx_timer_no_timer: + + /* No timer expired, increment the timer pointer. */ + /* _tx_timer_current_ptr++; */ + + ADD x0, x0, #8 // Move to next timer + + /* Check for wrap-around. */ + /* if (_tx_timer_current_ptr == _tx_timer_list_end) */ + + LDR x3, =_tx_timer_list_end // Pickup addr of timer list end + LDR x2, [x3, #0] // Pickup list end + CMP x0, x2 // Are we at list end? + BNE __tx_timer_skip_wrap // No, skip wrap-around logic + + /* Wrap to beginning of list. */ + /* _tx_timer_current_ptr = _tx_timer_list_start; */ + + LDR x3, =_tx_timer_list_start // Pickup addr of timer list start + LDR x0, [x3, #0] // Set current pointer to list start + +__tx_timer_skip_wrap: + + STR x0, [x1, #0] // Store new current timer pointer + /* } */ + +__tx_timer_done: + + /* Did a timer expire? */ + /* if (_tx_timer_expired) + { */ + + LDR x1, =_tx_timer_expired // Pickup addr of expired flag + LDR w0, [x1, #0] // Pickup timer expired flag + CMP w0, #0 // Check for timer expiration + BEQ __tx_timer_dont_activate // If not set, skip timer activation + + /* Process timer expiration. */ + /* _tx_timer_expiration_process(); */ + + BL _tx_timer_expiration_process // Call the timer expiration handling routine + + /* } */ +__tx_timer_dont_activate: + + /* Call time-slice processing. */ + /* _tx_thread_time_slice(); */ + BL _tx_thread_time_slice // Call time-slice processing + + /* Release inter-core protection. */ + + MOV x0, x28 // Pass the previous status register back + BL _tx_thread_smp_unprotect // Release protection + + LDP x29, x30, [sp], #16 // Recover x29, x30 + LDP x27, x28, [sp], #16 // Recover x27, x28 + RET // Return to caller + +/* } */ + + diff --git a/ports_smp/cortex_a5x_smp/gnu/example_build/common/GICv3.h b/ports_smp/cortex_a5x_smp/gnu/example_build/common/GICv3.h new file mode 100644 index 00000000..23bc7fd8 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/example_build/common/GICv3.h @@ -0,0 +1,561 @@ +/* + * GICv3.h - data types and function prototypes for GICv3 utility routines + * + * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. + * Use, modification and redistribution of this file is subject to your possession of a + * valid End User License Agreement for the Arm Product of which these examples are part of + * and your compliance with all applicable terms and conditions of such licence agreement. + */ +#ifndef GICV3_h +#define GICV3_h + +#include + +/* + * extra flags for GICD enable + */ +typedef enum +{ + gicdctlr_EnableGrp0 = (1 << 0), + gicdctlr_EnableGrp1NS = (1 << 1), + gicdctlr_EnableGrp1A = (1 << 1), + gicdctlr_EnableGrp1S = (1 << 2), + gicdctlr_EnableAll = (1 << 2) | (1 << 1) | (1 << 0), + gicdctlr_ARE_S = (1 << 4), /* Enable Secure state affinity routing */ + gicdctlr_ARE_NS = (1 << 5), /* Enable Non-Secure state affinity routing */ + gicdctlr_DS = (1 << 6), /* Disable Security support */ + gicdctlr_E1NWF = (1 << 7) /* Enable "1-of-N" wakeup model */ +} GICDCTLRFlags_t; + +/* + * modes for SPI routing + */ +typedef enum +{ + gicdirouter_ModeSpecific = 0, + gicdirouter_ModeAny = (1 << 31) +} GICDIROUTERBits_t; + +typedef enum +{ + gicdicfgr_Level = 0, + gicdicfgr_Edge = (1 << 1) +} GICDICFGRBits_t; + +typedef enum +{ + gicigroupr_G0S = 0, + gicigroupr_G1NS = (1 << 0), + gicigroupr_G1S = (1 << 2) +} GICIGROUPRBits_t; + +typedef enum +{ + gicrwaker_ProcessorSleep = (1 << 1), + gicrwaker_ChildrenAsleep = (1 << 2) +} GICRWAKERBits_t; + +/**********************************************************************/ + +/* + * Utility macros & functions + */ +#define RANGE_LIMIT(x) ((sizeof(x) / sizeof((x)[0])) - 1) + +static inline uint64_t gicv3PackAffinity(uint32_t aff3, uint32_t aff2, + uint32_t aff1, uint32_t aff0) +{ + /* + * only need to cast aff3 to get type promotion for all affinities + */ + return ((((uint64_t)aff3 & 0xff) << 32) | + ((aff2 & 0xff) << 16) | + ((aff1 & 0xff) << 8) | aff0); +} + +/**********************************************************************/ + +/* + * GIC Distributor Function Prototypes + */ + +/* + * ConfigGICD - configure GIC Distributor prior to enabling it + * + * Inputs: + * + * control - control flags + * + * Returns: + * + * + * + * NOTE: + * + * ConfigGICD() will set an absolute flags value, whereas + * {En,Dis}ableGICD() will only {set,clear} the flag bits + * passed as a parameter + */ +void ConfigGICD(GICDCTLRFlags_t flags); + +/* + * EnableGICD - top-level enable for GIC Distributor + * + * Inputs: + * + * flags - new control flags to set + * + * Returns: + * + * + * + * NOTE: + * + * ConfigGICD() will set an absolute flags value, whereas + * {En,Dis}ableGICD() will only {set,clear} the flag bits + * passed as a parameter + */ +void EnableGICD(GICDCTLRFlags_t flags); + +/* + * DisableGICD - top-level disable for GIC Distributor + * + * Inputs + * + * flags - control flags to clear + * + * Returns + * + * + * + * NOTE: + * + * ConfigGICD() will set an absolute flags value, whereas + * {En,Dis}ableGICD() will only {set,clear} the flag bits + * passed as a parameter + */ +void DisableGICD(GICDCTLRFlags_t flags); + +/* + * SyncAREinGICD - synchronise GICD Address Routing Enable bits + * + * Inputs + * + * flags - absolute flag bits to set in GIC Distributor + * + * dosync - flag whether to wait for ARE bits to match passed + * flag field (dosync = true), or whether to set absolute + * flag bits (dosync = false) + * + * Returns + * + * + * + * NOTE: + * + * This function is used to resolve a race in an MP system whereby secondary + * CPUs cannot reliably program all Redistributor registers until the + * primary CPU has enabled Address Routing. The primary CPU will call this + * function with dosync = false, while the secondaries will call it with + * dosync = true. + */ +void SyncAREinGICD(GICDCTLRFlags_t flags, uint32_t dosync); + +/* + * EnableSPI - enable a specific shared peripheral interrupt + * + * Inputs: + * + * id - which interrupt to enable + * + * Returns: + * + * + */ +void EnableSPI(uint32_t id); + +/* + * DisableSPI - disable a specific shared peripheral interrupt + * + * Inputs: + * + * id - which interrupt to disable + * + * Returns: + * + * + */ +void DisableSPI(uint32_t id); + +/* + * SetSPIPriority - configure the priority for a shared peripheral interrupt + * + * Inputs: + * + * id - interrupt identifier + * + * priority - 8-bit priority to program (see note below) + * + * Returns: + * + * + * + * Note: + * + * The GICv3 architecture makes this function sensitive to the Security + * context in terms of what effect it has on the programmed priority: no + * attempt is made to adjust for the reduced priority range available + * when making Non-Secure accesses to the GIC + */ +void SetSPIPriority(uint32_t id, uint32_t priority); + +/* + * GetSPIPriority - determine the priority for a shared peripheral interrupt + * + * Inputs: + * + * id - interrupt identifier + * + * Returns: + * + * interrupt priority in the range 0 - 0xff + */ +uint32_t GetSPIPriority(uint32_t id); + +/* + * SetSPIRoute - specify interrupt routing when gicdctlr_ARE is enabled + * + * Inputs: + * + * id - interrupt identifier + * + * affinity - prepacked "dotted quad" affinity routing. NOTE: use the + * gicv3PackAffinity() helper routine to generate this input + * + * mode - select routing mode (specific affinity, or any recipient) + * + * Returns: + * + * + */ +void SetSPIRoute(uint32_t id, uint64_t affinity, GICDIROUTERBits_t mode); + +/* + * GetSPIRoute - read ARE-enabled interrupt routing information + * + * Inputs: + * + * id - interrupt identifier + * + * Returns: + * + * routing configuration + */ +uint64_t GetSPIRoute(uint32_t id); + +/* + * SetSPITarget - configure the set of processor targets for an interrupt + * + * Inputs + * + * id - interrupt identifier + * + * target - 8-bit target bitmap + * + * Returns + * + * + */ +void SetSPITarget(uint32_t id, uint32_t target); + +/* + * GetSPITarget - read the set of processor targets for an interrupt + * + * Inputs + * + * id - interrupt identifier + * + * Returns + * + * 8-bit target bitmap + */ +uint32_t GetSPITarget(uint32_t id); + +/* + * ConfigureSPI - setup an interrupt as edge- or level-triggered + * + * Inputs + * + * id - interrupt identifier + * + * config - desired configuration + * + * Returns + * + * + */ +void ConfigureSPI(uint32_t id, GICDICFGRBits_t config); + +/* + * SetSPIPending - mark an interrupt as pending + * + * Inputs + * + * id - interrupt identifier + * + * Returns + * + * + */ +void SetSPIPending(uint32_t id); + +/* + * ClearSPIPending - mark an interrupt as not pending + * + * Inputs + * + * id - interrupt identifier + * + * Returns + * + * + */ +void ClearSPIPending(uint32_t id); + +/* + * GetSPIPending - query whether an interrupt is pending + * + * Inputs + * + * id - interrupt identifier + * + * Returns + * + * pending status + */ +uint32_t GetSPIPending(uint32_t id); + +/* + * SetSPISecurity - mark a shared peripheral interrupt as + * security + * + * Inputs + * + * id - which interrupt to mark + * + * group - the group for the interrupt + * + * Returns + * + * + */ +void SetSPISecurity(uint32_t id, GICIGROUPRBits_t group); + +/* + * SetSPISecurityBlock - mark a block of 32 shared peripheral + * interrupts as security + * + * Inputs: + * + * block - which block to mark (e.g. 1 = Ints 32-63) + * + * group - the group for the interrupts + * + * Returns: + * + * + */ +void SetSPISecurityBlock(uint32_t block, GICIGROUPRBits_t group); + +/* + * SetSPISecurityAll - mark all shared peripheral interrupts + * as security + * + * Inputs: + * + * group - the group for the interrupts + * + * Returns: + * + * + */ +void SetSPISecurityAll(GICIGROUPRBits_t group); + +/**********************************************************************/ + +/* + * GIC Re-Distributor Function Prototypes + * + * The model for calling Redistributor functions is that, rather than + * identifying the target redistributor with every function call, the + * SelectRedistributor() function is used to identify which redistributor + * is to be used for all functions until a different redistributor is + * explicitly selected + */ + +/* + * WakeupGICR - wake up a Redistributor + * + * Inputs: + * + * gicr - which Redistributor to wakeup + * + * Returns: + * + * + */ +void WakeupGICR(uint32_t gicr); + +/* + * EnablePrivateInt - enable a private (SGI/PPI) interrupt + * + * Inputs: + * + * gicr - which Redistributor to program + * + * id - which interrupt to enable + * + * Returns: + * + * + */ +void EnablePrivateInt(uint32_t gicr, uint32_t id); + +/* + * DisablePrivateInt - disable a private (SGI/PPI) interrupt + * + * Inputs: + * + * gicr - which Redistributor to program + * + * id - which interrupt to disable + * + * Returns: + * + * + */ +void DisablePrivateInt(uint32_t gicr, uint32_t id); + +/* + * SetPrivateIntPriority - configure the priority for a private + * (SGI/PPI) interrupt + * + * Inputs: + * + * gicr - which Redistributor to program + * + * id - interrupt identifier + * + * priority - 8-bit priority to program (see note below) + * + * Returns: + * + * + * + * Note: + * + * The GICv3 architecture makes this function sensitive to the Security + * context in terms of what effect it has on the programmed priority: no + * attempt is made to adjust for the reduced priority range available + * when making Non-Secure accesses to the GIC + */ +void SetPrivateIntPriority(uint32_t gicr, uint32_t id, uint32_t priority); + +/* + * GetPrivateIntPriority - configure the priority for a private + * (SGI/PPI) interrupt + * + * Inputs: + * + * gicr - which Redistributor to program + * + * id - interrupt identifier + * + * Returns: + * + * Int priority + */ +uint32_t GetPrivateIntPriority(uint32_t gicr, uint32_t id); + +/* + * SetPrivateIntPending - mark a private (SGI/PPI) interrupt as pending + * + * Inputs + * + * gicr - which Redistributor to program + * + * id - interrupt identifier + * + * Returns + * + * + */ +void SetPrivateIntPending(uint32_t gicr, uint32_t id); + +/* + * ClearPrivateIntPending - mark a private (SGI/PPI) interrupt as not pending + * + * Inputs + * + * gicr - which Redistributor to program + * + * id - interrupt identifier + * + * Returns + * + * + */ +void ClearPrivateIntPending(uint32_t gicr, uint32_t id); + +/* + * GetPrivateIntPending - query whether a private (SGI/PPI) interrupt is pending + * + * Inputs + * + * gicr - which Redistributor to program + * + * id - interrupt identifier + * + * Returns + * + * pending status + */ +uint32_t GetPrivateIntPending(uint32_t gicr, uint32_t id); + +/* + * SetPrivateIntSecurity - mark a private (SGI/PPI) interrupt as + * security + * + * Inputs + * + * gicr - which Redistributor to program + * + * id - which interrupt to mark + * + * group - the group for the interrupt + * + * Returns + * + * + */ +void SetPrivateIntSecurity(uint32_t gicr, uint32_t id, GICIGROUPRBits_t group); + +/* + * SetPrivateIntSecurityBlock - mark all 32 private (SGI/PPI) + * interrupts as security + * + * Inputs: + * + * gicr - which Redistributor to program + * + * group - the group for the interrupt + * + * Returns: + * + * + */ +void SetPrivateIntSecurityBlock(uint32_t gicr, GICIGROUPRBits_t group); + +#endif /* ndef GICV3_h */ + +/* EOF GICv3.h */ diff --git a/ports_smp/cortex_a5x_smp/gnu/example_build/common/GICv3_aliases.h b/ports_smp/cortex_a5x_smp/gnu/example_build/common/GICv3_aliases.h new file mode 100644 index 00000000..0928d14c --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/example_build/common/GICv3_aliases.h @@ -0,0 +1,113 @@ +// +// Aliases for GICv3 registers +// +// Copyright (c) 2016-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// + +#ifndef GICV3_ALIASES_H +#define GICV3_ALIASES_H + +#ifndef __clang__ + +/* + * Mapping of MSR and MRS to physical and virtual CPU interface registers + * + * Arm Generic Interrupt Controller Architecture Specification + * GIC architecture version 3.0 and version 4.0 + * Table 8-5 + */ +#define ICC_AP0R0_EL1 S3_0_C12_C8_4 +#define ICC_AP0R1_EL1 S3_0_C12_C8_5 +#define ICC_AP0R2_EL1 S3_0_C12_C8_6 +#define ICC_AP0R3_EL1 S3_0_C12_C8_7 + +#define ICC_AP1R0_EL1 S3_0_C12_C9_0 +#define ICC_AP1R1_EL1 S3_0_C12_C9_1 +#define ICC_AP1R2_EL1 S3_0_C12_C9_2 +#define ICC_AP1R3_EL1 S3_0_C12_C9_3 + +#define ICC_ASGI1R_EL1 S3_0_C12_C11_6 + +#define ICC_BPR0_EL1 S3_0_C12_C8_3 +#define ICC_BPR1_EL1 S3_0_C12_C12_3 + +#define ICC_CTLR_EL1 S3_0_C12_C12_4 +#define ICC_CTLR_EL3 S3_6_C12_C12_4 + +#define ICC_DIR_EL1 S3_0_C12_C11_1 + +#define ICC_EOIR0_EL1 S3_0_C12_C8_1 +#define ICC_EOIR1_EL1 S3_0_C12_C12_1 + +#define ICC_HPPIR0_EL1 S3_0_C12_C8_2 +#define ICC_HPPIR1_EL1 S3_0_C12_C12_2 + +#define ICC_IAR0_EL1 S3_0_C12_C8_0 +#define ICC_IAR1_EL1 S3_0_C12_C12_0 + +#define ICC_IGRPEN0_EL1 S3_0_C12_C12_6 +#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 +#define ICC_IGRPEN1_EL3 S3_6_C12_C12_7 + +#define ICC_PMR_EL1 S3_0_C4_C6_0 +#define ICC_RPR_EL1 S3_0_C12_C11_3 + +#define ICC_SGI0R_EL1 S3_0_C12_C11_7 +#define ICC_SGI1R_EL1 S3_0_C12_C11_5 + +#define ICC_SRE_EL1 S3_0_C12_C12_5 +#define ICC_SRE_EL2 S3_4_C12_C9_5 +#define ICC_SRE_EL3 S3_6_C12_C12_5 + +/* + * Mapping of MSR and MRS to virtual interface control registers + * + * Arm Generic Interrupt Controller Architecture Specification + * GIC architecture version 3.0 and version 4.0 + * Table 8-6 + */ +#define ICH_AP0R0_EL2 S3_4_C12_C8_0 +#define ICH_AP0R1_EL2 S3_4_C12_C8_1 +#define ICH_AP0R2_EL2 S3_4_C12_C8_2 +#define ICH_AP0R3_EL2 S3_4_C12_C8_3 + +#define ICH_AP1R0_EL2 S3_4_C12_C9_0 +#define ICH_AP1R1_EL2 S3_4_C12_C9_1 +#define ICH_AP1R2_EL2 S3_4_C12_C9_2 +#define ICH_AP1R3_EL2 S3_4_C12_C9_3 + +#define ICH_HCR_EL2 S3_4_C12_C11_0 + +#define ICH_VTR_EL2 S3_4_C12_C11_1 + +#define ICH_MISR_EL2 S3_4_C12_C11_2 + +#define ICH_EISR_EL2 S3_4_C12_C11_3 + +#define ICH_ELRSR_EL2 S3_4_C12_C11_5 + +#define ICH_VMCR_EL2 S3_4_C12_C11_7 + +#define ICH_LR0_EL2 S3_4_C12_C12_0 +#define ICH_LR1_EL2 S3_4_C12_C12_1 +#define ICH_LR2_EL2 S3_4_C12_C12_2 +#define ICH_LR3_EL2 S3_4_C12_C12_3 +#define ICH_LR4_EL2 S3_4_C12_C12_4 +#define ICH_LR5_EL2 S3_4_C12_C12_5 +#define ICH_LR6_EL2 S3_4_C12_C12_6 +#define ICH_LR7_EL2 S3_4_C12_C12_7 +#define ICH_LR8_EL2 S3_4_C12_C13_0 +#define ICH_LR9_EL2 S3_4_C12_C13_1 +#define ICH_LR10_EL2 S3_4_C12_C13_2 +#define ICH_LR11_EL2 S3_4_C12_C13_3 +#define ICH_LR12_EL2 S3_4_C12_C13_4 +#define ICH_LR13_EL2 S3_4_C12_C13_5 +#define ICH_LR14_EL2 S3_4_C12_C13_6 +#define ICH_LR15_EL2 S3_4_C12_C13_7 + +#endif /* not __clang__ */ + +#endif /* GICV3_ALIASES */ diff --git a/ports_smp/cortex_a5x_smp/gnu/example_build/common/GICv3_gicc.h b/ports_smp/cortex_a5x_smp/gnu/example_build/common/GICv3_gicc.h new file mode 100644 index 00000000..2b8a2d3e --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/example_build/common/GICv3_gicc.h @@ -0,0 +1,254 @@ +/* + * GICv3_gicc.h - prototypes and inline functions for GICC system register operations + * + * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. + * Use, modification and redistribution of this file is subject to your possession of a + * valid End User License Agreement for the Arm Product of which these examples are part of + * and your compliance with all applicable terms and conditions of such licence agreement. + */ +#ifndef GICV3_gicc_h +#define GICV3_gicc_h + +#include "GICv3_aliases.h" + +#define stringify_no_expansion(x) #x +#define stringify(x) stringify_no_expansion(x) + +/**********************************************************************/ + +typedef enum +{ + sreSRE = (1 << 0), + sreDFB = (1 << 1), + sreDIB = (1 << 2), + sreEnable = (1 << 3) +} ICC_SREBits_t; + +static inline void setICC_SRE_EL1(ICC_SREBits_t mode) +{ + asm("msr "stringify(ICC_SRE_EL1)", %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline uint64_t getICC_SRE_EL1(void) +{ + uint64_t retc; + + asm("mrs %0, "stringify(ICC_SRE_EL1)"\n" : "=r" (retc)); + + return retc; +} + +static inline void setICC_SRE_EL2(ICC_SREBits_t mode) +{ + asm("msr "stringify(ICC_SRE_EL2)", %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline uint64_t getICC_SRE_EL2(void) +{ + uint64_t retc; + + asm("mrs %0, "stringify(ICC_SRE_EL2)"\n" : "=r" (retc)); + + return retc; +} + +static inline void setICC_SRE_EL3(ICC_SREBits_t mode) +{ + asm("msr "stringify(ICC_SRE_EL3)", %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline uint64_t getICC_SRE_EL3(void) +{ + uint64_t retc; + + asm("mrs %0, "stringify(ICC_SRE_EL3)"\n" : "=r" (retc)); + + return retc; +} + +/**********************************************************************/ + +typedef enum +{ + igrpEnable = (1 << 0), + igrpEnableGrp1NS = (1 << 0), + igrpEnableGrp1S = (1 << 2) +} ICC_IGRPBits_t; + +static inline void setICC_IGRPEN0_EL1(ICC_IGRPBits_t mode) +{ + asm("msr "stringify(ICC_IGRPEN0_EL1)", %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline void setICC_IGRPEN1_EL1(ICC_IGRPBits_t mode) +{ + asm("msr "stringify(ICC_IGRPEN1_EL1)", %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline void setICC_IGRPEN1_EL3(ICC_IGRPBits_t mode) +{ + asm("msr "stringify(ICC_IGRPEN1_EL3)", %0\n; isb" :: "r" ((uint64_t)mode)); +} + +/**********************************************************************/ + +typedef enum +{ + ctlrCBPR = (1 << 0), + ctlrCBPR_EL1S = (1 << 0), + ctlrEOImode = (1 << 1), + ctlrCBPR_EL1NS = (1 << 1), + ctlrEOImode_EL3 = (1 << 2), + ctlrEOImode_EL1S = (1 << 3), + ctlrEOImode_EL1NS = (1 << 4), + ctlrRM = (1 << 5), + ctlrPMHE = (1 << 6) +} ICC_CTLRBits_t; + +static inline void setICC_CTLR_EL1(ICC_CTLRBits_t mode) +{ + asm("msr "stringify(ICC_CTLR_EL1)", %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline uint64_t getICC_CTLR_EL1(void) +{ + uint64_t retc; + + asm("mrs %0, "stringify(ICC_CTLR_EL1)"\n" : "=r" (retc)); + + return retc; +} + +static inline void setICC_CTLR_EL3(ICC_CTLRBits_t mode) +{ + asm("msr "stringify(ICC_CTLR_EL3)", %0\n; isb" :: "r" ((uint64_t)mode)); +} + +static inline uint64_t getICC_CTLR_EL3(void) +{ + uint64_t retc; + + asm("mrs %0, "stringify(ICC_CTLR_EL3)"\n" : "=r" (retc)); + + return retc; +} + +/**********************************************************************/ + +static inline uint64_t getICC_IAR0(void) +{ + uint64_t retc; + + asm("mrs %0, "stringify(ICC_IAR0_EL1)"\n" : "=r" (retc)); + + return retc; +} + +static inline uint64_t getICC_IAR1(void) +{ + uint64_t retc; + + asm("mrs %0, "stringify(ICC_IAR1_EL1)"\n" : "=r" (retc)); + + return retc; +} + +static inline void setICC_EOIR0(uint32_t interrupt) +{ + asm("msr "stringify(ICC_EOIR0_EL1)", %0\n; isb" :: "r" ((uint64_t)interrupt)); +} + +static inline void setICC_EOIR1(uint32_t interrupt) +{ + asm("msr "stringify(ICC_EOIR1_EL1)", %0\n; isb" :: "r" ((uint64_t)interrupt)); +} + +static inline void setICC_DIR(uint32_t interrupt) +{ + asm("msr "stringify(ICC_DIR_EL1)", %0\n; isb" :: "r" ((uint64_t)interrupt)); +} + +static inline void setICC_PMR(uint32_t priority) +{ + asm("msr "stringify(ICC_PMR_EL1)", %0\n; isb" :: "r" ((uint64_t)priority)); +} + +static inline void setICC_BPR0(uint32_t binarypoint) +{ + asm("msr "stringify(ICC_BPR0_EL1)", %0\n; isb" :: "r" ((uint64_t)binarypoint)); +} + +static inline void setICC_BPR1(uint32_t binarypoint) +{ + asm("msr "stringify(ICC_BPR1_EL1)", %0\n; isb" :: "r" ((uint64_t)binarypoint)); +} + +static inline uint64_t getICC_BPR0(void) +{ + uint64_t retc; + + asm("mrs %0, "stringify(ICC_BPR0_EL1)"\n" : "=r" (retc)); + + return retc; +} + +static inline uint64_t getICC_BPR1(void) +{ + uint64_t retc; + + asm("mrs %0, "stringify(ICC_BPR1_EL1)"\n" : "=r" (retc)); + + return retc; +} + +static inline uint64_t getICC_RPR(void) +{ + uint64_t retc; + + asm("mrs %0, "stringify(ICC_RPR_EL1)"\n" : "=r" (retc)); + + return retc; +} + +/**********************************************************************/ + +typedef enum +{ + sgirIRMTarget = 0, + sgirIRMAll = (1ull << 40) +} ICC_SGIRBits_t; + +static inline void setICC_SGI0R(uint8_t aff3, uint8_t aff2, + uint8_t aff1, ICC_SGIRBits_t irm, + uint16_t targetlist, uint8_t intid) +{ + uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \ + ((uint64_t)aff1 << 16) | irm | targetlist | \ + ((uint64_t)(intid & 0x0f) << 24)); + + asm("msr "stringify(ICC_SGI0R_EL1)", %0\n; isb" :: "r" (packedbits)); +} + +static inline void setICC_SGI1R(uint8_t aff3, uint8_t aff2, + uint8_t aff1, ICC_SGIRBits_t irm, + uint16_t targetlist, uint8_t intid) +{ + uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \ + ((uint64_t)aff1 << 16) | irm | targetlist | \ + ((uint64_t)(intid & 0x0f) << 24)); + + asm("msr "stringify(ICC_SGI1R_EL1)", %0\n; isb" :: "r" (packedbits)); +} + +static inline void setICC_ASGI1R(uint8_t aff3, uint8_t aff2, + uint8_t aff1, ICC_SGIRBits_t irm, + uint16_t targetlist, uint8_t intid) +{ + uint64_t packedbits = (((uint64_t)aff3 << 48) | ((uint64_t)aff2 << 32) | \ + ((uint64_t)aff1 << 16) | irm | targetlist | \ + ((uint64_t)(intid & 0x0f) << 24)); + + asm("msr "stringify(ICC_ASGI1R_EL1)", %0\n; isb" :: "r" (packedbits)); +} + +#endif /* ndef GICV3_gicc_h */ diff --git a/ports_smp/cortex_a5x_smp/gnu/example_build/common/GICv3_gicd.c b/ports_smp/cortex_a5x_smp/gnu/example_build/common/GICv3_gicd.c new file mode 100644 index 00000000..2cf9e843 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/example_build/common/GICv3_gicd.c @@ -0,0 +1,339 @@ +/* + * GICv3_gicd.c - generic driver code for GICv3 distributor + * + * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. + * Use, modification and redistribution of this file is subject to your possession of a + * valid End User License Agreement for the Arm Product of which these examples are part of + * and your compliance with all applicable terms and conditions of such licence agreement. + */ +#include + +#include "GICv3.h" + +typedef struct +{ + volatile uint32_t GICD_CTLR; // +0x0000 + const volatile uint32_t GICD_TYPER; // +0x0004 + const volatile uint32_t GICD_IIDR; // +0x0008 + + const volatile uint32_t padding0; // +0x000c + + volatile uint32_t GICD_STATUSR; // +0x0010 + + const volatile uint32_t padding1[3]; // +0x0014 + + volatile uint32_t IMP_DEF[8]; // +0x0020 + + volatile uint32_t GICD_SETSPI_NSR; // +0x0040 + const volatile uint32_t padding2; // +0x0044 + volatile uint32_t GICD_CLRSPI_NSR; // +0x0048 + const volatile uint32_t padding3; // +0x004c + volatile uint32_t GICD_SETSPI_SR; // +0x0050 + const volatile uint32_t padding4; // +0x0054 + volatile uint32_t GICD_CLRSPI_SR; // +0x0058 + + const volatile uint32_t padding5[3]; // +0x005c + + volatile uint32_t GICD_SEIR; // +0x0068 + + const volatile uint32_t padding6[5]; // +0x006c + + volatile uint32_t GICD_IGROUPR[32]; // +0x0080 + + volatile uint32_t GICD_ISENABLER[32]; // +0x0100 + volatile uint32_t GICD_ICENABLER[32]; // +0x0180 + volatile uint32_t GICD_ISPENDR[32]; // +0x0200 + volatile uint32_t GICD_ICPENDR[32]; // +0x0280 + volatile uint32_t GICD_ISACTIVER[32]; // +0x0300 + volatile uint32_t GICD_ICACTIVER[32]; // +0x0380 + + volatile uint8_t GICD_IPRIORITYR[1024]; // +0x0400 + volatile uint8_t GICD_ITARGETSR[1024]; // +0x0800 + volatile uint32_t GICD_ICFGR[64]; // +0x0c00 + volatile uint32_t GICD_IGRPMODR[32]; // +0x0d00 + const volatile uint32_t padding7[32]; // +0x0d80 + volatile uint32_t GICD_NSACR[64]; // +0x0e00 + + volatile uint32_t GICD_SGIR; // +0x0f00 + + const volatile uint32_t padding8[3]; // +0x0f04 + + volatile uint32_t GICD_CPENDSGIR[4]; // +0x0f10 + volatile uint32_t GICD_SPENDSGIR[4]; // +0x0f20 + + const volatile uint32_t padding9[52]; // +0x0f30 + const volatile uint32_t padding10[5120]; // +0x1000 + + volatile uint64_t GICD_IROUTER[1024]; // +0x6000 +} GICv3_distributor; + +/* + * use the scatter file to place GICD + */ +GICv3_distributor __attribute__((section(".gicd"))) gicd; + +void ConfigGICD(GICDCTLRFlags_t flags) +{ + gicd.GICD_CTLR = flags; +} + +void EnableGICD(GICDCTLRFlags_t flags) +{ + gicd.GICD_CTLR |= flags; +} + +void DisableGICD(GICDCTLRFlags_t flags) +{ + gicd.GICD_CTLR &= ~flags; +} + +void SyncAREinGICD(GICDCTLRFlags_t flags, uint32_t dosync) +{ + if (dosync) + { + const uint32_t tmask = gicdctlr_ARE_S | gicdctlr_ARE_NS; + const uint32_t tval = flags & tmask; + + while ((gicd.GICD_CTLR & tmask) != tval) + continue; + } + else + gicd.GICD_CTLR = flags; +} + +void EnableSPI(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_ISENABLER has 32 interrupts per register + */ + bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISENABLER); + id &= 32 - 1; + + gicd.GICD_ISENABLER[bank] = 1 << id; + + return; +} + +void DisableSPI(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_ISENABLER has 32 interrupts per register + */ + bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICENABLER); + id &= 32 - 1; + + gicd.GICD_ICENABLER[bank] = 1 << id; + + return; +} + +void SetSPIPriority(uint32_t id, uint32_t priority) +{ + uint32_t bank; + + /* + * GICD_IPRIORITYR has one byte-wide entry per interrupt + */ + bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR); + + gicd.GICD_IPRIORITYR[bank] = priority; +} + +uint32_t GetSPIPriority(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_IPRIORITYR has one byte-wide entry per interrupt + */ + bank = id & RANGE_LIMIT(gicd.GICD_IPRIORITYR); + + return (uint32_t)(gicd.GICD_IPRIORITYR[bank]); +} + +void SetSPIRoute(uint32_t id, uint64_t affinity, GICDIROUTERBits_t mode) +{ + uint32_t bank; + + /* + * GICD_IROUTER has one doubleword-wide entry per interrupt + */ + bank = id & RANGE_LIMIT(gicd.GICD_IROUTER); + + gicd.GICD_IROUTER[bank] = affinity | (uint64_t)mode; +} + +uint64_t GetSPIRoute(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_IROUTER has one doubleword-wide entry per interrupt + */ + bank = id & RANGE_LIMIT(gicd.GICD_IROUTER); + + return gicd.GICD_IROUTER[bank]; +} + +void SetSPITarget(uint32_t id, uint32_t target) +{ + uint32_t bank; + + /* + * GICD_ITARGETSR has one byte-wide entry per interrupt + */ + bank = id & RANGE_LIMIT(gicd.GICD_ITARGETSR); + + gicd.GICD_ITARGETSR[bank] = target; +} + +uint32_t GetSPITarget(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_ITARGETSR has one byte-wide entry per interrupt + */ + /* + * GICD_ITARGETSR has 4 interrupts per register, i.e. 8-bits of + * target bitmap per register + */ + bank = id & RANGE_LIMIT(gicd.GICD_ITARGETSR); + + return (uint32_t)(gicd.GICD_ITARGETSR[bank]); +} + +void ConfigureSPI(uint32_t id, GICDICFGRBits_t config) +{ + uint32_t bank, tmp; + + /* + * GICD_ICFGR has 16 interrupts per register, i.e. 2-bits of + * configuration per register + */ + bank = (id >> 4) & RANGE_LIMIT(gicd.GICD_ICFGR); + config &= 3; + + id = (id & 0xf) << 1; + + tmp = gicd.GICD_ICFGR[bank]; + tmp &= ~(3 << id); + tmp |= config << id; + gicd.GICD_ICFGR[bank] = tmp; +} + +void SetSPIPending(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_ISPENDR has 32 interrupts per register + */ + bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ISPENDR); + id &= 0x1f; + + gicd.GICD_ISPENDR[bank] = 1 << id; +} + +void ClearSPIPending(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_ICPENDR has 32 interrupts per register + */ + bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICPENDR); + id &= 0x1f; + + gicd.GICD_ICPENDR[bank] = 1 << id; +} + +uint32_t GetSPIPending(uint32_t id) +{ + uint32_t bank; + + /* + * GICD_ICPENDR has 32 interrupts per register + */ + bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_ICPENDR); + id &= 0x1f; + + return (gicd.GICD_ICPENDR[bank] >> id) & 1; +} + +void SetSPISecurity(uint32_t id, GICIGROUPRBits_t group) +{ + uint32_t bank, groupmod; + + /* + * GICD_IGROUPR has 32 interrupts per register + */ + bank = (id >> 5) & RANGE_LIMIT(gicd.GICD_IGROUPR); + id &= 0x1f; + + /* + * the single group argument is split into two separate + * registers, so filter out and remove the (new to gicv3) + * group modifier bit + */ + groupmod = (group >> 1) & 1; + group &= 1; + + /* + * either set or clear the Group bit for the interrupt as appropriate + */ + if (group) + gicd.GICD_IGROUPR[bank] |= 1 << id; + else + gicd.GICD_IGROUPR[bank] &= ~(1 << id); + + /* + * now deal with groupmod + */ + if (groupmod) + gicd.GICD_IGRPMODR[bank] |= 1 << id; + else + gicd.GICD_IGRPMODR[bank] &= ~(1 << id); +} + +void SetSPISecurityBlock(uint32_t block, GICIGROUPRBits_t group) +{ + uint32_t groupmod; + const uint32_t nbits = (sizeof group * 8) - 1; + + /* + * GICD_IGROUPR has 32 interrupts per register + */ + block &= RANGE_LIMIT(gicd.GICD_IGROUPR); + + /* + * get each bit of group config duplicated over all 32-bits in a word + */ + groupmod = (uint32_t)(((int32_t)group << (nbits - 1)) >> 31); + group = (uint32_t)(((int32_t)group << nbits) >> 31); + + /* + * set the security state for this block of SPIs + */ + gicd.GICD_IGROUPR[block] = group; + gicd.GICD_IGRPMODR[block] = groupmod; +} + +void SetSPISecurityAll(GICIGROUPRBits_t group) +{ + uint32_t block; + + /* + * GICD_TYPER.ITLinesNumber gives (No. SPIS / 32) - 1, and we + * want to iterate over all blocks excluding 0 (which are the + * SGI/PPI interrupts, and not relevant here) + */ + for (block = (gicd.GICD_TYPER & ((1 << 5) - 1)); block > 0; --block) + SetSPISecurityBlock(block, group); +} + +/* EOF GICv3_gicd.c */ diff --git a/ports_smp/cortex_a5x_smp/gnu/example_build/common/GICv3_gicr.c b/ports_smp/cortex_a5x_smp/gnu/example_build/common/GICv3_gicr.c new file mode 100644 index 00000000..ef5c8925 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/example_build/common/GICv3_gicr.c @@ -0,0 +1,289 @@ +/* + * GICv3_gicr.c - generic driver code for GICv3 redistributor + * + * Copyright (c) 2014-2018 Arm Limited (or its affiliates). All rights reserved. + * Use, modification and redistribution of this file is subject to your possession of a + * valid End User License Agreement for the Arm Product of which these examples are part of + * and your compliance with all applicable terms and conditions of such licence agreement. + */ +#include "GICv3.h" + +/* + * physical LPI Redistributor register map + */ +typedef struct +{ + volatile uint32_t GICR_CTLR; // +0x0000 - RW - Redistributor Control Register + const volatile uint32_t GICR_IIDR; // +0x0004 - RO - Implementer Identification Register + const volatile uint32_t GICR_TYPER[2]; // +0x0008 - RO - Redistributor Type Register + volatile uint32_t GICR_STATUSR; // +0x0010 - RW - Error Reporting Status Register, optional + volatile uint32_t GICR_WAKER; // +0x0014 - RW - Redistributor Wake Register + const volatile uint32_t padding1[2]; // +0x0018 - RESERVED +#ifndef USE_GIC600 + volatile uint32_t IMPDEF1[8]; // +0x0020 - ?? - IMPLEMENTATION DEFINED +#else + volatile uint32_t GICR_FCTLR; // +0x0020 - RW - Function Control Register + volatile uint32_t GICR_PWRR; // +0x0024 - RW - Power Management Control Register + volatile uint32_t GICR_CLASS; // +0x0028 - RW - Class Register + const volatile uint32_t padding2[5]; // +0x002C - RESERVED +#endif + volatile uint64_t GICR_SETLPIR; // +0x0040 - WO - Set LPI Pending Register + volatile uint64_t GICR_CLRLPIR; // +0x0048 - WO - Clear LPI Pending Register + const volatile uint32_t padding3[8]; // +0x0050 - RESERVED + volatile uint64_t GICR_PROPBASER; // +0x0070 - RW - Redistributor Properties Base Address Register + volatile uint64_t GICR_PENDBASER; // +0x0078 - RW - Redistributor LPI Pending Table Base Address Register + const volatile uint32_t padding4[8]; // +0x0080 - RESERVED + volatile uint64_t GICR_INVLPIR; // +0x00A0 - WO - Redistributor Invalidate LPI Register + const volatile uint32_t padding5[2]; // +0x00A8 - RESERVED + volatile uint64_t GICR_INVALLR; // +0x00B0 - WO - Redistributor Invalidate All Register + const volatile uint32_t padding6[2]; // +0x00B8 - RESERVED + volatile uint64_t GICR_SYNCR; // +0x00C0 - RO - Redistributor Synchronize Register + const volatile uint32_t padding7[2]; // +0x00C8 - RESERVED + const volatile uint32_t padding8[12]; // +0x00D0 - RESERVED + volatile uint64_t IMPDEF2; // +0x0100 - WO - IMPLEMENTATION DEFINED + const volatile uint32_t padding9[2]; // +0x0108 - RESERVED + volatile uint64_t IMPDEF3; // +0x0110 - WO - IMPLEMENTATION DEFINED + const volatile uint32_t padding10[2]; // +0x0118 - RESERVED +} GICv3_redistributor_RD; + +/* + * SGI and PPI Redistributor register map + */ +typedef struct +{ + const volatile uint32_t padding1[32]; // +0x0000 - RESERVED + volatile uint32_t GICR_IGROUPR0; // +0x0080 - RW - Interrupt Group Registers (Security Registers in GICv1) + const volatile uint32_t padding2[31]; // +0x0084 - RESERVED + volatile uint32_t GICR_ISENABLER; // +0x0100 - RW - Interrupt Set-Enable Registers + const volatile uint32_t padding3[31]; // +0x0104 - RESERVED + volatile uint32_t GICR_ICENABLER; // +0x0180 - RW - Interrupt Clear-Enable Registers + const volatile uint32_t padding4[31]; // +0x0184 - RESERVED + volatile uint32_t GICR_ISPENDR; // +0x0200 - RW - Interrupt Set-Pending Registers + const volatile uint32_t padding5[31]; // +0x0204 - RESERVED + volatile uint32_t GICR_ICPENDR; // +0x0280 - RW - Interrupt Clear-Pending Registers + const volatile uint32_t padding6[31]; // +0x0284 - RESERVED + volatile uint32_t GICR_ISACTIVER; // +0x0300 - RW - Interrupt Set-Active Register + const volatile uint32_t padding7[31]; // +0x0304 - RESERVED + volatile uint32_t GICR_ICACTIVER; // +0x0380 - RW - Interrupt Clear-Active Register + const volatile uint32_t padding8[31]; // +0x0184 - RESERVED + volatile uint8_t GICR_IPRIORITYR[32]; // +0x0400 - RW - Interrupt Priority Registers + const volatile uint32_t padding9[504]; // +0x0420 - RESERVED + volatile uint32_t GICR_ICnoFGR[2]; // +0x0C00 - RW - Interrupt Configuration Registers + const volatile uint32_t padding10[62]; // +0x0C08 - RESERVED + volatile uint32_t GICR_IGRPMODR0; // +0x0D00 - RW - ???? + const volatile uint32_t padding11[63]; // +0x0D04 - RESERVED + volatile uint32_t GICR_NSACR; // +0x0E00 - RW - Non-Secure Access Control Register +} GICv3_redistributor_SGI; + +/* + * We have a multiplicity of GIC Redistributors; on the GIC-AEM and + * GIC-500 they are arranged as one 128KB region per redistributor: one + * 64KB page of GICR LPI registers, and one 64KB page of GICR Private + * Int registers + */ +typedef struct +{ + union + { + GICv3_redistributor_RD RD_base; + uint8_t padding[64 * 1024]; + } RDblock; + + union + { + GICv3_redistributor_SGI SGI_base; + uint8_t padding[64 * 1024]; + } SGIblock; +} GICv3_GICR; + +/* + * use the scatter file to place GIC Redistributor base address + * + * although this code doesn't know how many Redistributor banks + * a particular system will have, we declare gicrbase as an array + * to avoid unwanted compiler optimisations when calculating the + * base of a particular Redistributor bank + */ +static const GICv3_GICR gicrbase[2] __attribute__((section (".gicr"))); + +/**********************************************************************/ + +/* + * utility functions to calculate base of a particular + * Redistributor bank + */ + +static inline GICv3_redistributor_RD *const getgicrRD(uint32_t gicr) +{ + GICv3_GICR *const arraybase = (GICv3_GICR *const)&gicrbase; + + return &((arraybase + gicr)->RDblock.RD_base); +} + +static inline GICv3_redistributor_SGI *const getgicrSGI(uint32_t gicr) +{ + GICv3_GICR *arraybase = (GICv3_GICR *)(&gicrbase); + + return &(arraybase[gicr].SGIblock.SGI_base); +} + +/**********************************************************************/ + +void WakeupGICR(uint32_t gicr) +{ + GICv3_redistributor_RD *const gicrRD = getgicrRD(gicr); +#ifdef USE_GIC600 + //Power up Re-distributor for GIC-600 + gicrRD->GICR_PWRR = 0x2; +#endif + + /* + * step 1 - ensure GICR_WAKER.ProcessorSleep is off + */ + gicrRD->GICR_WAKER &= ~gicrwaker_ProcessorSleep; + + /* + * step 2 - wait for children asleep to be cleared + */ + while ((gicrRD->GICR_WAKER & gicrwaker_ChildrenAsleep) != 0) + continue; + + /* + * OK, GICR is go + */ + return; +} + +void EnablePrivateInt(uint32_t gicr, uint32_t id) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + id &= 0x1f; + + gicrSGI->GICR_ISENABLER = 1 << id; +} + +void DisablePrivateInt(uint32_t gicr, uint32_t id) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + id &= 0x1f; + + gicrSGI->GICR_ICENABLER = 1 << id; +} + +void SetPrivateIntPriority(uint32_t gicr, uint32_t id, uint32_t priority) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + /* + * GICD_IPRIORITYR has one byte-wide entry per interrupt + */ + id &= RANGE_LIMIT(gicrSGI->GICR_IPRIORITYR); + + gicrSGI->GICR_IPRIORITYR[id] = priority; +} + +uint32_t GetPrivateIntPriority(uint32_t gicr, uint32_t id) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + /* + * GICD_IPRIORITYR has one byte-wide entry per interrupt + */ + id &= RANGE_LIMIT(gicrSGI->GICR_IPRIORITYR); + + return (uint32_t)(gicrSGI->GICR_IPRIORITYR[id]); +} + +void SetPrivateIntPending(uint32_t gicr, uint32_t id) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + /* + * GICR_ISPENDR is one 32-bit register + */ + id &= 0x1f; + + gicrSGI->GICR_ISPENDR = 1 << id; +} + +void ClearPrivateIntPending(uint32_t gicr, uint32_t id) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + /* + * GICR_ICPENDR is one 32-bit register + */ + id &= 0x1f; + + gicrSGI->GICR_ICPENDR = 1 << id; +} + +uint32_t GetPrivateIntPending(uint32_t gicr, uint32_t id) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + + /* + * GICR_ISPENDR is one 32-bit register + */ + id &= 0x1f; + + return (gicrSGI->GICR_ISPENDR >> id) & 0x01; +} + +void SetPrivateIntSecurity(uint32_t gicr, uint32_t id, GICIGROUPRBits_t group) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + uint32_t groupmod; + + /* + * GICR_IGROUPR0 is one 32-bit register + */ + id &= 0x1f; + + /* + * the single group argument is split into two separate + * registers, so filter out and remove the (new to gicv3) + * group modifier bit + */ + groupmod = (group >> 1) & 1; + group &= 1; + + /* + * either set or clear the Group bit for the interrupt as appropriate + */ + if (group) + gicrSGI->GICR_IGROUPR0 |= 1 << id; + else + gicrSGI->GICR_IGROUPR0 &= ~(1 << id); + + /* + * now deal with groupmod + */ + if (groupmod) + gicrSGI->GICR_IGRPMODR0 |= 1 << id; + else + gicrSGI->GICR_IGRPMODR0 &= ~(1 << id); +} + +void SetPrivateIntSecurityBlock(uint32_t gicr, GICIGROUPRBits_t group) +{ + GICv3_redistributor_SGI *const gicrSGI = getgicrSGI(gicr); + const uint32_t nbits = (sizeof group * 8) - 1; + uint32_t groupmod; + + /* + * get each bit of group config duplicated over all 32 bits + */ + groupmod = (uint32_t)(((int32_t)group << (nbits - 1)) >> 31); + group = (uint32_t)(((int32_t)group << nbits) >> 31); + + /* + * set the security state for this block of SPIs + */ + gicrSGI->GICR_IGROUPR0 = group; + gicrSGI->GICR_IGRPMODR0 = groupmod; +} + +/* EOF GICv3_gicr.c */ diff --git a/ports_smp/cortex_a5x_smp/gnu/example_build/common/MP_Mutexes.S b/ports_smp/cortex_a5x_smp/gnu/example_build/common/MP_Mutexes.S new file mode 100644 index 00000000..77fa0a0f --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/example_build/common/MP_Mutexes.S @@ -0,0 +1,86 @@ +// +// Armv8-A AArch64 - Basic Mutex Example +// +// Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// + + + .text + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + + + .global _mutex_initialize + .global _mutex_acquire + .global _mutex_release + +// +// These routines implement the mutex management functions required for running +// the Arm C library in a multi-threaded environment. +// +// They use a value of 0 to represent an unlocked mutex, and 1 for a locked mutex +// +// ********************************************************************** +// + + .type _mutex_initialize, "function" + .cfi_startproc +_mutex_initialize: + + // + // mark the mutex as unlocked + // + mov w1, #0 + str w1, [x0] + + // + // we are running multi-threaded, so set a non-zero return + // value (function prototype says use 1) + // + mov w0, #1 + ret + .cfi_endproc + + + .type _mutex_acquire, "function" + .cfi_startproc +_mutex_acquire: + + // + // send ourselves an event, so we don't stick on the wfe at the + // top of the loop + // + sevl + + // + // wait until the mutex is available + // +loop: + wfe + ldaxr w1, [x0] + cbnz w1, loop + + // + // mutex is (at least, it was) available - try to claim it + // + mov w1, #1 + stxr w2, w1, [x0] + cbnz w2, loop + + // + // OK, we have the mutex, our work is done here + // + ret + .cfi_endproc + + + .type _mutex_release, "function" + .cfi_startproc +_mutex_release: + + mov w1, #0 + stlr w1, [x0] + ret + .cfi_endproc diff --git a/ports_smp/cortex_a5x_smp/gnu/example_build/common/PPM_AEM.h b/ports_smp/cortex_a5x_smp/gnu/example_build/common/PPM_AEM.h new file mode 100644 index 00000000..52c9a0fe --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/example_build/common/PPM_AEM.h @@ -0,0 +1,66 @@ +// +// Private Peripheral Map for the v8 Architecture Envelope Model +// +// Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// + +#ifndef PPM_AEM_H +#define PPM_AEM_H + +// +// Distributor layout +// +#define GICD_CTLR 0x0000 +#define GICD_TYPER 0x0004 +#define GICD_IIDR 0x0008 +#define GICD_IGROUP 0x0080 +#define GICD_ISENABLE 0x0100 +#define GICD_ICENABLE 0x0180 +#define GICD_ISPEND 0x0200 +#define GICD_ICPEND 0x0280 +#define GICD_ISACTIVE 0x0300 +#define GICD_ICACTIVE 0x0380 +#define GICD_IPRIORITY 0x0400 +#define GICD_ITARGETS 0x0800 +#define GICD_ICFG 0x0c00 +#define GICD_PPISR 0x0d00 +#define GICD_SPISR 0x0d04 +#define GICD_SGIR 0x0f00 +#define GICD_CPENDSGI 0x0f10 +#define GICD_SPENDSGI 0x0f20 +#define GICD_PIDR4 0x0fd0 +#define GICD_PIDR5 0x0fd4 +#define GICD_PIDR6 0x0fd8 +#define GICD_PIDR7 0x0fdc +#define GICD_PIDR0 0x0fe0 +#define GICD_PIDR1 0x0fe4 +#define GICD_PIDR2 0x0fe8 +#define GICD_PIDR3 0x0fec +#define GICD_CIDR0 0x0ff0 +#define GICD_CIDR1 0x0ff4 +#define GICD_CIDR2 0x0ff8 +#define GICD_CIDR3 0x0ffc + +// +// CPU Interface layout +// +#define GICC_CTLR 0x0000 +#define GICC_PMR 0x0004 +#define GICC_BPR 0x0008 +#define GICC_IAR 0x000c +#define GICC_EOIR 0x0010 +#define GICC_RPR 0x0014 +#define GICC_HPPIR 0x0018 +#define GICC_ABPR 0x001c +#define GICC_AIAR 0x0020 +#define GICC_AEOIR 0x0024 +#define GICC_AHPPIR 0x0028 +#define GICC_APR0 0x00d0 +#define GICC_NSAPR0 0x00e0 +#define GICC_IIDR 0x00fc +#define GICC_DIR 0x1000 + +#endif // PPM_AEM_H diff --git a/ports_smp/cortex_a5x_smp/gnu/example_build/common/sample_threadx.ld b/ports_smp/cortex_a5x_smp/gnu/example_build/common/sample_threadx.ld new file mode 100644 index 00000000..e9b12a82 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/example_build/common/sample_threadx.ld @@ -0,0 +1,245 @@ +/* Linker script to place sections and symbol values. + * It references following symbols, which must be defined in code: + * start64 : Entry point + * + * It defines following symbols, which code can use without definition: + * __cs3_peripherals + * __code_start + * __exidx_start + * __exidx_end + * __data_start + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __bss_start__ + * __bss_end__ + * __end__ + * __stack + * __el3_stack + * __ttb0_l1 + * __ttb0_l2_ram + * __ttb0_l2_private + * __ttb0_l2_periph + * __top_of_ram + */ + +ENTRY(start64) + +SECTIONS +{ + /* + * CS3 Peripherals is a 64MB region from 0x1c000000 + * that includes the following: + * System Registers at 0x1C010000 + * UART0 (PL011) at 0x1C090000 + * Color LCD Controller (PL111) at 0x1C1F0000 + * plus a number of others. + * CS3_PERIPHERALS is used by the startup code for page-table generation + * This region is not truly empty, but we have no + * predefined objects that live within it + */ + __cs3_peripherals = 0x1c000000; + + /* + * GICv3 distributor + */ + .gicd 0x2f000000 (NOLOAD): + { + *(.gicd) + } + + /* + * GICv3 redistributors + * 128KB for each redistributor in the system + */ + .gicr 0x2f100000 (NOLOAD): + { + *(.gicr) + } + + .vectors 0x80000000: + { + __code_start = .; + KEEP(*(StartUp)) + KEEP(*(EL1VECTORS EL2VECTORS EL3VECTORS)) + } + + .init : + { + KEEP (*(SORT_NONE(.init))) + } + + .text : + { + *(.text*) + } + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } + + .rodata : + { + *(.rodata .rodata.* .gnu.linkonce.r.*) + } + + .eh_frame : + { + KEEP (*(.eh_frame)) + } + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } + + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array )) + PROVIDE_HIDDEN (__init_array_end = .); + } + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array )) + PROVIDE_HIDDEN (__fini_array_end = .); + } + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } + + .jcr : + { + KEEP (*(.jcr)) + } + + .data : + { + __data_start = . ; + *(.data .data.* .gnu.linkonce.d.*) + SORT(CONSTRUCTORS) + } + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } + + .heap (NOLOAD): + { + . = ALIGN(64); + __end__ = .; + PROVIDE(end = .); + . = . + 0x1000; + } + + .stack (NOLOAD): + { + . = ALIGN(64); + . = . + 4 * 0x8000; + __stack = .; + } + + .handler_stack_limit (NOLOAD): + { + . = ALIGN(64); + . = . + 4 * 0x4000; + handler_stack_limit = .; + } + + .el3_stack (NOLOAD): + { + . = ALIGN(64); + . = . + 4 * 0x1000; + __el3_stack = .; + } + + .ttb0_l1 (NOLOAD): + { + . = ALIGN(4096); + __ttb0_l1 = .; + . = . + 0x1000; + } + + .ttb0_l2_ram (NOLOAD): + { + . = ALIGN(4096); + __ttb0_l2_ram = .; + . = . + 0x1000; + } + + .ttb0_l2_private (NOLOAD): + { + . = ALIGN(4096); + __ttb0_l2_private = .; + . = . + 0x1000; + } + + .ttb0_l2_periph (NOLOAD): + { + . = ALIGN(4096); + __ttb0_l2_periph = .; + . = . + 0x1000; + } + + /* + * The startup code uses the end of this region to calculate + * the top of memory - don't place any RAM regions after it + */ + __top_of_ram = .; +} diff --git a/ports_smp/cortex_a5x_smp/gnu/example_build/common/sp804_timer.c b/ports_smp/cortex_a5x_smp/gnu/example_build/common/sp804_timer.c new file mode 100644 index 00000000..4dc009b2 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/example_build/common/sp804_timer.c @@ -0,0 +1,122 @@ +// ------------------------------------------------------------ +// SP804 Dual Timer +// +// Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#include "sp804_timer.h" + +#define TIMER_SP804_CTRL_TIMEREN (1 << 7) +#define TIMER_SP804_CTRL_TIMERMODE (1 << 6) // Bit 6: +#define TIMER_SP804_CTRL_INTENABLE (1 << 5) +#define TIMER_SP804_CTRL_TIMERSIZE (1 << 1) // Bit 1: 0=16-bit, 1=32-bit +#define TIMER_SP804_CTRL_ONESHOT (1 << 0) // Bit 0: 0=wrapping, 1=one-shot + +#define TIMER_SP804_CTRL_PRESCALE_1 (0 << 2) // clk/1 +#define TIMER_SP804_CTRL_PRESCALE_4 (1 << 2) // clk/4 +#define TIMER_SP804_CTRL_PRESCALE_8 (2 << 2) // clk/8 + +struct sp804_timer +{ + volatile uint32_t Time1Load; // +0x00 + const volatile uint32_t Time1Value; // +0x04 - RO + volatile uint32_t Timer1Control; // +0x08 + volatile uint32_t Timer1IntClr; // +0x0C - WO + const volatile uint32_t Timer1RIS; // +0x10 - RO + const volatile uint32_t Timer1MIS; // +0x14 - RO + volatile uint32_t Timer1BGLoad; // +0x18 + + volatile uint32_t Time2Load; // +0x20 + volatile uint32_t Time2Value; // +0x24 + volatile uint8_t Timer2Control; // +0x28 + volatile uint32_t Timer2IntClr; // +0x2C - WO + const volatile uint32_t Timer2RIS; // +0x30 - RO + const volatile uint32_t Timer2MIS; // +0x34 - RO + volatile uint32_t Timer2BGLoad; // +0x38 + + // Not including ID registers + +}; + +// Instance of the dual timer, will be placed using the scatter file +struct sp804_timer* dual_timer; + + +// Set base address of timer +// address - virtual address of SP804 timer +void setTimerBaseAddress(uint64_t address) +{ + dual_timer = (struct sp804_timer*)address; + return; +} + + +// Sets up the private timer +// load_value - Initial value of timer +// auto_reload - Periodic (SP804_AUTORELOAD) or one shot (SP804_SINGLESHOT) +// interrupt - Whether to generate an interrupt +void initTimer(uint32_t load_value, uint32_t auto_reload, uint32_t interrupt) +{ + uint32_t tmp = 0; + + dual_timer->Time1Load = load_value; + + // Fixed setting: 32-bit, no prescaling + tmp = TIMER_SP804_CTRL_TIMERSIZE | TIMER_SP804_CTRL_PRESCALE_1 | TIMER_SP804_CTRL_TIMERMODE; + + // Settings from parameters: interrupt generation & reload + tmp = tmp | interrupt | auto_reload; + + // Write control register + dual_timer->Timer1Control = tmp; + + return; +} + + +// Starts the timer +void startTimer(void) +{ + uint32_t tmp; + + tmp = dual_timer->Timer1Control; + tmp = tmp | TIMER_SP804_CTRL_TIMEREN; // Set TimerEn (bit 7) + dual_timer->Timer1Control = tmp; + + return; +} + + +// Stops the timer +void stopTimer(void) +{ + uint32_t tmp; + + tmp = dual_timer->Timer1Control; + tmp = tmp & ~TIMER_SP804_CTRL_TIMEREN; // Clear TimerEn (bit 7) + dual_timer->Timer1Control = tmp; + + return; +} + + +// Returns the current timer count +uint32_t getTimerCount(void) +{ + return dual_timer->Time1Value; +} + + +void clearTimerIrq(void) +{ + // A write to this register, of any value, clears the interrupt + dual_timer->Timer1IntClr = 1; +} + + +// ------------------------------------------------------------ +// End of sp804_timer.c +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a5x_smp/gnu/example_build/common/sp804_timer.h b/ports_smp/cortex_a5x_smp/gnu/example_build/common/sp804_timer.h new file mode 100644 index 00000000..777062cc --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/example_build/common/sp804_timer.h @@ -0,0 +1,53 @@ +// ------------------------------------------------------------ +// SP804 Dual Timer +// Header Filer +// +// Copyright (c) 2009-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#ifndef _SP804_TIMER_ +#define _SP804_TIMER_ + +#include + +// Set base address of timer +// address - virtual address of SP804 timer +void setTimerBaseAddress(uint64_t address); + + +// Sets up the private timer +// load_value - Initial value of timer +// auto_reload - Periodic (SP804_AUTORELOAD) or one shot (SP804_SINGLESHOT) +// interrupt - Whether to generate an interrupt + +#define SP804_AUTORELOAD (0) +#define SP804_SINGLESHOT (1) +#define SP804_GENERATE_IRQ (1 << 5) +#define SP804_NO_IRQ (0) + +void initTimer(uint32_t load_value, uint32_t auto_reload, uint32_t interrupt); + + +// Starts the timer +void startTimer(void); + + +// Stops the timer +void stopTimer(void); + + +// Returns the current timer count +uint32_t getTimerCount(void); + + +// Clears the timer interrupt +void clearTimerIrq(void); + +#endif + +// ------------------------------------------------------------ +// End of sp804_timer.h +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a5x_smp/gnu/example_build/common/startup.S b/ports_smp/cortex_a5x_smp/gnu/example_build/common/startup.S new file mode 100644 index 00000000..53f02e37 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/example_build/common/startup.S @@ -0,0 +1,798 @@ +// ------------------------------------------------------------ +// Armv8-A MPCore EL3 AArch64 Startup Code +// +// Basic Vectors, MMU, caches and GICv3 initialization +// +// Exits in EL1 AArch64 +// +// Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#include "v8_mmu.h" +#include "v8_system.h" +#include "GICv3_aliases.h" + + .section StartUp, "ax" + .balign 4 + + + .global el1_vectors + .global el2_vectors + .global el3_vectors + + .global InvalidateUDCaches + .global ZeroBlock + + .global SetPrivateIntSecurityBlock + .global SetSPISecurityAll + .global SetPrivateIntPriority + + .global WakeupGICR + .global SyncAREinGICD + .global EnableGICD + .global EnablePrivateInt + .global GetPrivateIntPending + .global ClearPrivateIntPending + + .global _start + .global MainApp + + .global __code_start + .global __ttb0_l1 + .global __ttb0_l2_ram + .global __ttb0_l2_periph + .global __top_of_ram + .global gicd + .global __stack + .global __el3_stack + .global __cs3_peripherals + +is_mmu_ready: +.word 0 + + +// ------------------------------------------------------------ + + .global start64 + .type start64, "function" +start64: + + // + // program the VBARs + // + ldr x1, =el1_vectors + msr VBAR_EL1, x1 + + ldr x1, =el2_vectors + msr VBAR_EL2, x1 + + ldr x1, =el3_vectors + msr VBAR_EL3, x1 + + + // GIC-500 comes out of reset in GICv2 compatibility mode - first set + // system register enables for all relevant exception levels, and + // select GICv3 operating mode + // + msr SCR_EL3, xzr // Ensure NS bit is initially clear, so secure copy of ICC_SRE_EL1 can be configured + isb + + mov x0, #15 + msr ICC_SRE_EL3, x0 + isb + msr ICC_SRE_EL1, x0 // Secure copy of ICC_SRE_EL1 + + // + // set lower exception levels as non-secure, with no access + // back to EL2 or EL3, and are AArch64 capable + // + mov x3, #(SCR_EL3_RW | \ + SCR_EL3_SMD | \ + SCR_EL3_NS) // Set NS bit, to access Non-secure registers + msr SCR_EL3, x3 + isb + + mov x0, #15 + msr ICC_SRE_EL2, x0 + isb + msr ICC_SRE_EL1, x0 // Non-secure copy of ICC_SRE_EL1 + + + // + // no traps or VM modifications from the Hypervisor, EL1 is AArch64 + // + mov x2, #HCR_EL2_RW + msr HCR_EL2, x2 + + // + // VMID is still significant, even when virtualisation is not + // being used, so ensure VTTBR_EL2 is properly initialised + // + msr VTTBR_EL2, xzr + + // + // VMPIDR_EL2 holds the value of the Virtualization Multiprocessor ID. This is the value returned by Non-secure EL1 reads of MPIDR_EL1. + // VPIDR_EL2 holds the value of the Virtualization Processor ID. This is the value returned by Non-secure EL1 reads of MIDR_EL1. + // Both of these registers are architecturally UNKNOWN at reset, and so they must be set to the correct value + // (even if EL2/virtualization is not being used), otherwise non-secure EL1 reads of MPIDR_EL1/MIDR_EL1 will return garbage values. + // This guarantees that any future reads of MPIDR_EL1 and MIDR_EL1 from Non-secure EL1 will return the correct value. + // + mrs x0, MPIDR_EL1 + msr VMPIDR_EL2, x0 + mrs x0, MIDR_EL1 + msr VPIDR_EL2, x0 + + // extract the core number from MPIDR_EL1 and store it in + // x19 (defined by the AAPCS as callee-saved), so we can re-use + // the number later + // + bl GetCPUID + mov x19, x0 + + // + // neither EL3 nor EL2 trap floating point or accesses to CPACR + // + msr CPTR_EL3, xzr + msr CPTR_EL2, xzr + + // + // SCTLR_ELx may come out of reset with UNKNOWN values so we will + // set the fields to 0 except, possibly, the endianess field(s). + // Note that setting SCTLR_EL2 or the EL0 related fields of SCTLR_EL1 + // is not strictly needed, since we're never in EL2 or EL0 + // +#ifdef __ARM_BIG_ENDIAN + mov x0, #(SCTLR_ELx_EE | SCTLR_EL1_E0E) +#else + mov x0, #0 +#endif + msr SCTLR_EL3, x0 + msr SCTLR_EL2, x0 + msr SCTLR_EL1, x0 + +#ifdef CORTEXA + // + // Configure ACTLR_EL[23] + // ---------------------- + // + // These bits are IMPLEMENTATION DEFINED, so are different for + // different processors + // + // For Cortex-A57, the controls we set are: + // + // Enable lower level access to CPUACTLR_EL1 + // Enable lower level access to CPUECTLR_EL1 + // Enable lower level access to L2CTLR_EL1 + // Enable lower level access to L2ECTLR_EL1 + // Enable lower level access to L2ACTLR_EL1 + // + mov x0, #((1 << 0) | \ + (1 << 1) | \ + (1 << 4) | \ + (1 << 5) | \ + (1 << 6)) + + msr ACTLR_EL3, x0 + msr ACTLR_EL2, x0 + + // + // configure CPUECTLR_EL1 + // + // These bits are IMP DEF, so need to different for different + // processors + // + // SMPEN - bit 6 - Enables the processor to receive cache + // and TLB maintenance operations + // + // Note: For Cortex-A57/53 SMPEN should be set before enabling + // the caches and MMU, or performing any cache and TLB + // maintenance operations. + // + // This register has a defined reset value, so we use a + // read-modify-write sequence to set SMPEN + // + mrs x0, S3_1_c15_c2_1 // Read EL1 CPU Extended Control Register + orr x0, x0, #(1 << 6) // Set the SMPEN bit + msr S3_1_c15_c2_1, x0 // Write EL1 CPU Extended Control Register + + isb +#endif + + // + // That's the last of the control settings for now + // + // Note: no ISB after all these changes, as registers won't be + // accessed until after an exception return, which is itself a + // context synchronisation event + // + + // + // Setup some EL3 stack space, ready for calling some subroutines, below. + // + // Stack space allocation is CPU-specific, so use CPU + // number already held in x19 + // + // 2^12 bytes per CPU for the EL3 stacks + // + ldr x0, =__el3_stack + sub x0, x0, x19, lsl #12 + mov sp, x0 + + // + // we need to configure the GIC while still in secure mode, specifically + // all PPIs and SPIs have to be programmed as Group1 interrupts + // + + // + // Before the GIC can be reliably programmed, we need to + // enable Affinity Routing, as this affects where the configuration + // registers are (with Affinity Routing enabled, some registers are + // in the Redistributor, whereas those same registers are in the + // Distributor with Affinity Routing disabled (i.e. when in GICv2 + // compatibility mode). + // + mov x0, #(1 << 4) | (1 << 5) // gicdctlr_ARE_S | gicdctlr_ARE_NS + mov x1, x19 + bl SyncAREinGICD + + // + // The Redistributor comes out of reset assuming the processor is + // asleep - correct that assumption + // + mov w0, w19 + bl WakeupGICR + + // + // Now we're ready to set security and other initialisations + // + // This is a per-CPU configuration for these interrupts + // + // for the first cluster, CPU number is the redistributor index + // + mov w0, w19 + mov w1, #1 // gicigroupr_G1NS + bl SetPrivateIntSecurityBlock + + // + // While we're in the Secure World, set the priority mask low enough + // for it to be writable in the Non-Secure World + // + //mov x0, #16 << 3 // 5 bits of priority in the Secure world + mov x0, #0xFF // for Non-Secure interrupts + msr ICC_PMR_EL1, x0 + + // + // there's more GIC setup to do, but only for the primary CPU + // + cbnz x19, drop_to_el1 + + // + // There's more to do to the GIC - call the utility routine to set + // all SPIs to Group1 + // + mov w0, #1 // gicigroupr_G1NS + bl SetSPISecurityAll + + // + // Set up EL1 entry point and "dummy" exception return information, + // then perform exception return to enter EL1 + // + .global drop_to_el1 +drop_to_el1: + adr x1, el1_entry_aarch64 + msr ELR_EL3, x1 + mov x1, #(AARCH64_SPSR_EL1h | \ + AARCH64_SPSR_F | \ + AARCH64_SPSR_I | \ + AARCH64_SPSR_A) + msr SPSR_EL3, x1 + eret + + + +// ------------------------------------------------------------ +// EL1 - Common start-up code +// ------------------------------------------------------------ + + .global el1_entry_aarch64 + .type el1_entry_aarch64, "function" +el1_entry_aarch64: + + // + // Now we're in EL1, setup the application stack + // the scatter file allocates 2^14 bytes per app stack + // + ldr x0, =handler_stack_limit + sub x0, x0, x19, lsl #14 + mov sp, x0 + MSR SPSel, #0 + ISB + ldr x0, =__stack + sub x0, x0, x19, lsl #14 + mov sp, x0 + + // + // Enable floating point + // + mov x0, #CPACR_EL1_FPEN + msr CPACR_EL1, x0 + + // + // Invalidate caches and TLBs for all stage 1 + // translations used at EL1 + // + // Cortex-A processors automatically invalidate their caches on reset + // (unless suppressed with the DBGL1RSTDISABLE or L2RSTDISABLE pins). + // It is therefore not necessary for software to invalidate the caches + // on startup, however, this is done here in case of a warm reset. + bl InvalidateUDCaches + tlbi VMALLE1 + + + // + // Set TTBR0 Base address + // + // The CPUs share one set of translation tables that are + // generated by CPU0 at run-time + // + // TTBR1_EL1 is not used in this example + // + ldr x1, =__ttb0_l1 + msr TTBR0_EL1, x1 + + + // + // Set up memory attributes + // + // These equate to: + // + // 0 -> 0b01000100 = 0x00000044 = Normal, Inner/Outer Non-Cacheable + // 1 -> 0b11111111 = 0x0000ff00 = Normal, Inner/Outer WriteBack Read/Write Allocate + // 2 -> 0b00000100 = 0x00040000 = Device-nGnRE + // + mov x1, #0xff44 + movk x1, #4, LSL #16 // equiv to: movk x1, #0x0000000000040000 + msr MAIR_EL1, x1 + + + // + // Set up TCR_EL1 + // + // We're using only TTBR0 (EPD1 = 1), and the page table entries: + // - are using an 8-bit ASID from TTBR0 + // - have a 4K granularity (TG0 = 0b00) + // - are outer-shareable (SH0 = 0b10) + // - are using Inner & Outer WBWA Normal memory ([IO]RGN0 = 0b01) + // - map + // + 32 bits of VA space (T0SZ = 0x20) + // + into a 32-bit PA space (IPS = 0b000) + // + // 36 32 28 24 20 16 12 8 4 0 + // -----+----+----+----+----+----+----+----+----+----+ + // | | |OOII| | | |OOII| | | + // TT | | |RRRR|E T | T| |RRRR|E T | T| + // BB | I I|TTSS|GGGG|P 1 | 1|TTSS|GGGG|P 0 | 0| + // IIA| P P|GGHH|NNNN|DAS | S|GGHH|NNNN|D S | S| + // 10S| S-S|1111|1111|11Z-|---Z|0000|0000|0 Z-|---Z| + // + // 000 0000 0000 0000 1000 0000 0010 0101 0010 0000 + // + // 0x 8 0 2 5 2 0 + // + // Note: the ISB is needed to ensure the changes to system + // context are before the write of SCTLR_EL1.M to enable + // the MMU. It is likely on a "real" implementation that + // this setup would work without an ISB, due to the + // amount of code that gets executed before enabling the + // MMU, but that would not be architecturally correct. + // + ldr x1, =0x0000000000802520 + msr TCR_EL1, x1 + isb + + // + // the primary CPU is going to use SGI 15 as a wakeup event + // to let us know when it is OK to proceed, so prepare for + // receiving that interrupt + // + // NS interrupt priorities run from 0 to 15, with 15 being + // too low a priority to ever raise an interrupt, so let's + // use 14 + // + mov w0, w19 + mov w1, #0 + mov w2, #14 << 4 // we're in NS world, so 4 bits of priority, + // 8-bit field, - 4 = 4-bit shift + bl SetPrivateIntPriority + + mov w0, w19 + mov w1, #0 + bl EnablePrivateInt + + // + // set priority mask as low as possible; although,being in the + // NS World, we can't set bit[7] of the priority, we still + // write all 8-bits of priority to an ICC register + // + mov x0, #31 << 3 + msr ICC_PMR_EL1, x0 + + // + // set global enable and wait for our interrupt to arrive + // + mov x0, #1 + msr ICC_IGRPEN1_EL1, x0 + isb + + // + // x19 already contains the CPU number, so branch to secondary + // code if we're not on CPU0 + // + cbnz x19, el1_secondary + + // + // Fall through to primary code + // + + +// +// ------------------------------------------------------------ +// +// EL1 - primary CPU init code +// +// This code is run on CPU0, while the other CPUs are in the +// holding pen +// + + .global el1_primary + .type el1_primary, "function" +el1_primary: + + // + // Turn on the banked GIC distributor enable, + // ready for individual CPU enables later + // + mov w0, #(1 << 1) // gicdctlr_EnableGrp1A + bl EnableGICD + + // + // Generate TTBR0 L1 + // + // at 4KB granularity, 32-bit VA space, table lookup starts at + // L1, with 1GB regions + // + // we are going to create entries pointing to L2 tables for a + // couple of these 1GB regions, the first of which is the + // RAM on the VE board model - get the table addresses and + // start by emptying out the L1 page tables (4 entries at L1 + // for a 4K granularity) + // + // x21 = address of L1 tables + // + ldr x21, =__ttb0_l1 + mov x0, x21 + mov x1, #(4 << 3) + bl ZeroBlock + + // + // time to start mapping the RAM regions - clear out the + // L2 tables and point to them from the L1 tables + // + // x22 = address of L2 tables, needs to be remembered in case + // we want to re-use the tables for mapping peripherals + // + ldr x22, =__ttb0_l2_ram + mov x1, #(512 << 3) + mov x0, x22 + bl ZeroBlock + + // + // Get the start address of RAM (the EXEC region) into x4 + // and calculate the offset into the L1 table (1GB per region, + // max 4GB) + // + // x23 = L1 table offset, saved for later comparison against + // peripheral offset + // + ldr x4, =__code_start + ubfx x23, x4, #30, #2 + + orr x1, x22, #TT_S1_ATTR_PAGE + str x1, [x21, x23, lsl #3] + + // + // we've already used the RAM start address in x4 - we now need + // to get this in terms of an offset into the L2 page tables, + // where each entry covers 2MB + // + ubfx x2, x4, #21, #9 + + // + // TOP_OF_RAM in the scatter file marks the end of the + // Execute region in RAM: convert the end of this region to an + // offset too, being careful to round up, then calculate the + // number of entries to write + // + ldr x5, =__top_of_ram + sub x3, x5, #1 + ubfx x3, x3, #21, #9 + add x3, x3, #1 + sub x3, x3, x2 + + // + // set x1 to the required page table attributes, then orr + // in the start address (modulo 2MB) + // + // L2 tables in our configuration cover 2MB per entry - map + // memory as Shared, Normal WBWA (MAIR[1]) with a flat + // VA->PA translation + // + bic x4, x4, #((1 << 21) - 1) + mov x1, #(TT_S1_ATTR_BLOCK | \ + (1 << TT_S1_ATTR_MATTR_LSB) | \ + TT_S1_ATTR_NS | \ + TT_S1_ATTR_AP_RW_PL1 | \ + TT_S1_ATTR_SH_INNER | \ + TT_S1_ATTR_AF | \ + TT_S1_ATTR_nG) + orr x1, x1, x4 + + // + // factor the offset into the page table address and then write + // the entries + // + add x0, x22, x2, lsl #3 + +loop1: + subs x3, x3, #1 + str x1, [x0], #8 + add x1, x1, #0x200, LSL #12 // equiv to add x1, x1, #(1 << 21) // 2MB per entry + bne loop1 + + + // + // now mapping the Peripheral regions - clear out the + // L2 tables and point to them from the L1 tables + // + // The assumption here is that all peripherals live within + // a common 1GB region (i.e. that there's a single set of + // L2 pages for all the peripherals). We only use a UART + // and the GIC in this example, so the assumption is sound + // + // x24 = address of L2 peripheral tables + // + ldr x24, =__ttb0_l2_periph + + // + // get the GICD address into x4 and calculate + // the offset into the L1 table + // + // x25 = L1 table offset + // + ldr x4, =gicd + ubfx x25, x4, #30, #2 + + // + // here's the tricky bit: it's possible that the peripherals are + // in the same 1GB region as the RAM, in which case we don't need + // to prime a separate set of L2 page tables, nor add them to the + // L1 tables + // + // if we're going to re-use the TTB0_L2_RAM tables, get their + // address into x24, which is used later on to write the PTEs + // + cmp x25, x23 + csel x24, x22, x24, EQ + b.eq nol2setup + + // + // Peripherals are in a separate 1GB region, and so have their own + // set of L2 tables - clean out the tables and add them to the L1 + // table + // + mov x0, x24 + mov x1, #512 << 3 + bl ZeroBlock + + orr x1, x24, #TT_S1_ATTR_PAGE + str x1, [x21, x25, lsl #3] + + // + // there's only going to be a single 2MB region for GICD (in + // x4) - get this in terms of an offset into the L2 page tables + // + // with larger systems, it is possible that the GIC redistributor + // registers require extra 2MB pages, in which case extra code + // would be required here + // +nol2setup: + ubfx x2, x4, #21, #9 + + // + // set x1 to the required page table attributes, then orr + // in the start address (modulo 2MB) + // + // L2 tables in our configuration cover 2MB per entry - map + // memory as NS Device-nGnRE (MAIR[2]) with a flat VA->PA + // translation + // + bic x4, x4, #((1 << 21) - 1) // start address mod 2MB + mov x1, #(TT_S1_ATTR_BLOCK | \ + (2 << TT_S1_ATTR_MATTR_LSB) | \ + TT_S1_ATTR_NS | \ + TT_S1_ATTR_AP_RW_PL1 | \ + TT_S1_ATTR_AF | \ + TT_S1_ATTR_nG) + orr x1, x1, x4 + + // + // only a single L2 entry for this, so no loop as we have for RAM, above + // + str x1, [x24, x2, lsl #3] + + // + // we have CS3_PERIPHERALS that include the UART controller + // + // Again, the code is making assumptions - this time that the CS3_PERIPHERALS + // region uses the same 1GB portion of the address space as the GICD, + // and thus shares the same set of L2 page tables + // + // Get CS3_PERIPHERALS address into x4 and calculate the offset into the + // L2 tables + // + ldr x4, =__cs3_peripherals + ubfx x2, x4, #21, #9 + + // + // set x1 to the required page table attributes, then orr + // in the start address (modulo 2MB) + // + // L2 tables in our configuration cover 2MB per entry - map + // memory as NS Device-nGnRE (MAIR[2]) with a flat VA->PA + // translation + // + bic x4, x4, #((1 << 21) - 1) // start address mod 2MB + mov x1, #(TT_S1_ATTR_BLOCK | \ + (2 << TT_S1_ATTR_MATTR_LSB) | \ + TT_S1_ATTR_NS | \ + TT_S1_ATTR_AP_RW_PL1 | \ + TT_S1_ATTR_AF | \ + TT_S1_ATTR_nG) + orr x1, x1, x4 + + // + // only a single L2 entry again - write it + // + str x1, [x24, x2, lsl #3] + + // + // issue a barrier to ensure all table entry writes are complete + // + dsb ish + + ldr x1, =is_mmu_ready + mov x2, #1 + str x2, [x1] + + // + // Enable the MMU. Caches will be enabled later, after scatterloading. + // + mrs x1, SCTLR_EL1 + orr x1, x1, #SCTLR_ELx_M + bic x1, x1, #SCTLR_ELx_A // Disable alignment fault checking. To enable, change bic to orr + msr SCTLR_EL1, x1 + isb + + // + // The Arm Architecture Reference Manual for Armv8-A states: + // + // Instruction accesses to Non-cacheable Normal memory can be held in instruction caches. + // Correspondingly, the sequence for ensuring that modifications to instructions are available + // for execution must include invalidation of the modified locations from the instruction cache, + // even if the instructions are held in Normal Non-cacheable memory. + // This includes cases where the instruction cache is disabled. + // + + dsb ish // ensure all previous stores have completed before invalidating + ic ialluis // I cache invalidate all inner shareable to PoU (which includes secondary cores) + dsb ish // ensure completion on inner shareable domain (which includes secondary cores) + isb + + // Scatter-loading is complete, so enable the caches here, so that the C-library's mutex initialization later will work + mrs x1, SCTLR_EL1 + orr x1, x1, #SCTLR_ELx_C + orr x1, x1, #SCTLR_ELx_I + msr SCTLR_EL1, x1 + isb + + // Zero the bss + ldr x0, =__bss_start__ // Start of block + mov x1, #0 // Fill value + ldr x2, =__bss_end__ // End of block + sub x2, x2, x0 // Length of block + bl memset + + // Set up the standard file handles + bl initialise_monitor_handles + + // Set up _fini and fini_array to be called at exit + ldr x0, =__libc_fini_array + bl atexit + + // Call preinit_array, _init and init_array + bl __libc_init_array + + // Set argc = 1, argv[0] = "" and then call main + .pushsection .data + .align 3 +argv: + .dword arg0 + .dword 0 +arg0: + .byte 0 + .popsection + + mov x0, #1 + ldr x1, =argv + bl main + + b exit // Will not return + +// ------------------------------------------------------------ +// EL1 - secondary CPU init code +// +// This code is run on CPUs 1, 2, 3 etc.... +// ------------------------------------------------------------ + + .global el1_secondary + .type el1_secondary, "function" +el1_secondary: + +wait_for_mmu_ready: + ldr x1, =is_mmu_ready + ldr x1, [x1] + cmp x1, #1 + b.ne wait_for_mmu_ready + + // + // Enable the MMU and caches + // + mrs x1, SCTLR_EL1 + orr x1, x1, #SCTLR_ELx_M + orr x1, x1, #SCTLR_ELx_C + orr x1, x1, #SCTLR_ELx_I + bic x1, x1, #SCTLR_ELx_A // Disable alignment fault checking. To enable, change bic to orr + msr SCTLR_EL1, x1 + isb + + /* EL: Secondary core entrance. */ + B _tx_thread_smp_initialize_wait + +loop_wfi: + dsb SY // Clear all pending data accesses + wfi // Go to sleep + + // + // something woke us from our wait, was it the required interrupt? + // + mov w0, w19 + mov w1, #15 + bl GetPrivateIntPending + cbz w0, loop_wfi + + // + // it was - there's no need to actually take the interrupt, + // so just clear it + // + mov w0, w19 + mov w1, #15 + bl ClearPrivateIntPending + + // + // Branch to thread start + // + //B MainApp + diff --git a/ports_smp/cortex_a5x_smp/gnu/example_build/common/timer_interrupts.c b/ports_smp/cortex_a5x_smp/gnu/example_build/common/timer_interrupts.c new file mode 100644 index 00000000..7b0996ef --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/example_build/common/timer_interrupts.c @@ -0,0 +1,152 @@ +/* Bare-metal example for Armv8-A FVP Base model */ + +/* Timer and interrupts */ + +/* Copyright (c) 2016 Arm Limited (or its affiliates). All rights reserved. */ +/* Use, modification and redistribution of this file is subject to your */ +/* possession of a valid DS-5 end user licence agreement and your compliance */ +/* with all applicable terms and conditions of such licence agreement. */ + +#include + +#include "GICv3.h" +#include "GICv3_gicc.h" +#include "sp804_timer.h" + +void _tx_timer_interrupt(void); + +// LED Base address +#define LED_BASE (volatile unsigned int *)0x1C010008 + + +void nudge_leds(void) // Move LEDs along +{ + static int state = 1; + static int value = 1; + + if (state) + { + int max = (1 << 7); + value <<= 1; + if (value == max) + state = 0; + } + else + { + value >>= 1; + if (value == 1) + state = 1; + } + + *LED_BASE = value; // Update LEDs hardware +} + + +// Initialize Timer 0 and Interrupt Controller +void init_timer(void) +{ + // Enable interrupts + __asm("MSR DAIFClr, #0xF"); + setICC_IGRPEN1_EL1(igrpEnable); + + // Configure the SP804 timer to generate an interrupt + setTimerBaseAddress(0x1C110000); + initTimer(0x200, SP804_AUTORELOAD, SP804_GENERATE_IRQ); + startTimer(); + + // The SP804 timer generates SPI INTID 34. Enable + // this ID, and route it to core 0.0.0.0 (this one!) + SetSPIRoute(34, 0, gicdirouter_ModeSpecific); // Route INTID 34 to 0.0.0.0 (this core) + SetSPIPriority(34, 0); // Set INTID 34 to priority to 0 + ConfigureSPI(34, gicdicfgr_Level); // Set INTID 34 as level-sensitive + EnableSPI(34); // Enable INTID 34 +} + + +// -------------------------------------------------------- + +void irqHandler(void) +{ + unsigned int ID; + + ID = getICC_IAR1(); // readIntAck(); + + // Check for reserved IDs + if ((1020 <= ID) && (ID <= 1023)) + { + //printf("irqHandler() - Reserved INTID %d\n\n", ID); + return; + } + + switch(ID) + { + case 34: + // Dual-Timer 0 (SP804) + //printf("irqHandler() - External timer interrupt\n\n"); + nudge_leds(); + clearTimerIrq(); + + /* Call ThreadX timer interrupt processing. */ + _tx_timer_interrupt(); + + break; + + default: + // Unexpected ID value + //printf("irqHandler() - Unexpected INTID %d\n\n", ID); + break; + } + + // Write the End of Interrupt register to tell the GIC + // we've finished handling the interrupt + setICC_EOIR1(ID); // writeAliasedEOI(ID); +} + +// -------------------------------------------------------- + +// Not actually used in this example, but provided for completeness + +void fiqHandler(void) +{ + unsigned int ID; + unsigned int aliased = 0; + + ID = getICC_IAR0(); // readIntAck(); + printf("fiqHandler() - Read %d from IAR0\n", ID); + + // Check for reserved IDs + if ((1020 <= ID) && (ID <= 1023)) + { + printf("fiqHandler() - Reserved INTID %d\n\n", ID); + ID = getICC_IAR1(); // readAliasedIntAck(); + printf("fiqHandler() - Read %d from AIAR\n", ID); + aliased = 1; + + // If still spurious then simply return + if ((1020 <= ID) && (ID <= 1023)) + return; + } + + switch(ID) + { + case 34: + // Dual-Timer 0 (SP804) + printf("fiqHandler() - External timer interrupt\n\n"); + clearTimerIrq(); + break; + + default: + // Unexpected ID value + printf("fiqHandler() - Unexpected INTID %d\n\n", ID); + break; + } + + // Write the End of Interrupt register to tell the GIC + // we've finished handling the interrupt + // NOTE: If the ID was read from the Aliased IAR, then + // the aliased EOI register must be used + if (aliased == 0) + setICC_EOIR0(ID); // writeEOI(ID); + else + setICC_EOIR1(ID); // writeAliasedEOI(ID); +} diff --git a/ports_smp/cortex_a5x_smp/gnu/example_build/common/use_model_semihosting.ds b/ports_smp/cortex_a5x_smp/gnu/example_build/common/use_model_semihosting.ds new file mode 100644 index 00000000..6fde52b2 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/example_build/common/use_model_semihosting.ds @@ -0,0 +1 @@ +set semihosting enabled off diff --git a/ports_smp/cortex_a5x_smp/gnu/example_build/common/v8_aarch64.S b/ports_smp/cortex_a5x_smp/gnu/example_build/common/v8_aarch64.S new file mode 100644 index 00000000..d86fecb6 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/example_build/common/v8_aarch64.S @@ -0,0 +1,163 @@ +// ------------------------------------------------------------ +// Armv8-A AArch64 - Common helper functions +// +// Copyright (c) 2012-2018 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#include "v8_system.h" + + .text + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + + .global EnableCachesEL1 + .global DisableCachesEL1 + .global InvalidateUDCaches + .global GetMIDR + .global GetMPIDR + .global GetCPUID + +// ------------------------------------------------------------ + +// +// void EnableCachesEL1(void) +// +// enable Instruction and Data caches +// + .type EnableCachesEL1, "function" + .cfi_startproc +EnableCachesEL1: + + mrs x0, SCTLR_EL1 + orr x0, x0, #SCTLR_ELx_I + orr x0, x0, #SCTLR_ELx_C + msr SCTLR_EL1, x0 + + isb + ret + .cfi_endproc + + +// ------------------------------------------------------------ + + .type DisableCachesEL1, "function" + .cfi_startproc +DisableCachesEL1: + + mrs x0, SCTLR_EL1 + bic x0, x0, #SCTLR_ELx_I + bic x0, x0, #SCTLR_ELx_C + msr SCTLR_EL1, x0 + + isb + ret + .cfi_endproc + + +// ------------------------------------------------------------ + +// +// void InvalidateUDCaches(void) +// +// Invalidate data and unified caches +// + .type InvalidateUDCaches, "function" + .cfi_startproc +InvalidateUDCaches: + // From the Armv8-A Architecture Reference Manual + + dmb ish // ensure all prior inner-shareable accesses have been observed + + mrs x0, CLIDR_EL1 + and w3, w0, #0x07000000 // get 2 x level of coherence + lsr w3, w3, #23 + cbz w3, finished + mov w10, #0 // w10 = 2 x cache level + mov w8, #1 // w8 = constant 0b1 +loop_level: + add w2, w10, w10, lsr #1 // calculate 3 x cache level + lsr w1, w0, w2 // extract 3-bit cache type for this level + and w1, w1, #0x7 + cmp w1, #2 + b.lt next_level // no data or unified cache at this level + msr CSSELR_EL1, x10 // select this cache level + isb // synchronize change of csselr + mrs x1, CCSIDR_EL1 // read ccsidr + and w2, w1, #7 // w2 = log2(linelen)-4 + add w2, w2, #4 // w2 = log2(linelen) + ubfx w4, w1, #3, #10 // w4 = max way number, right aligned + clz w5, w4 // w5 = 32-log2(ways), bit position of way in dc operand + lsl w9, w4, w5 // w9 = max way number, aligned to position in dc operand + lsl w16, w8, w5 // w16 = amount to decrement way number per iteration +loop_way: + ubfx w7, w1, #13, #15 // w7 = max set number, right aligned + lsl w7, w7, w2 // w7 = max set number, aligned to position in dc operand + lsl w17, w8, w2 // w17 = amount to decrement set number per iteration +loop_set: + orr w11, w10, w9 // w11 = combine way number and cache number ... + orr w11, w11, w7 // ... and set number for dc operand + dc isw, x11 // do data cache invalidate by set and way + subs w7, w7, w17 // decrement set number + b.ge loop_set + subs x9, x9, x16 // decrement way number + b.ge loop_way +next_level: + add w10, w10, #2 // increment 2 x cache level + cmp w3, w10 + b.gt loop_level + dsb sy // ensure completion of previous cache maintenance operation + isb +finished: + ret + .cfi_endproc + + +// ------------------------------------------------------------ + +// +// ID Register functions +// + + .type GetMIDR, "function" + .cfi_startproc +GetMIDR: + + mrs x0, MIDR_EL1 + ret + .cfi_endproc + + + .type GetMPIDR, "function" + .cfi_startproc +GetMPIDR: + + mrs x0, MPIDR_EL1 + ret + .cfi_endproc + + + .type GetCPUID, "function" + .cfi_startproc +GetCPUID: + + mrs x0, MIDR_EL1 + ubfx x0, x0, #4, #12 // extract PartNum + cmp x0, #0xD0B // Cortex-A76 + b.eq DynamIQ + cmp x0, #0xD0A // Cortex-A75 + b.eq DynamIQ + cmp x0, #0xD05 // Cortex-A55 + b.eq DynamIQ + b Others +DynamIQ: + mrs x0, MPIDR_EL1 + ubfx x0, x0, #MPIDR_EL1_AFF1_LSB, #MPIDR_EL1_AFF_WIDTH + ret + +Others: + mrs x0, MPIDR_EL1 + ubfx x0, x0, #MPIDR_EL1_AFF0_LSB, #MPIDR_EL1_AFF_WIDTH + ret + .cfi_endproc diff --git a/ports_smp/cortex_a5x_smp/gnu/example_build/common/v8_mmu.h b/ports_smp/cortex_a5x_smp/gnu/example_build/common/v8_mmu.h new file mode 100644 index 00000000..0185feba --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/example_build/common/v8_mmu.h @@ -0,0 +1,118 @@ +// +// Defines for v8 Memory Model +// +// Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// + +#ifndef V8_MMU_H +#define V8_MMU_H + +// +// Translation Control Register fields +// +// RGN field encodings +// +#define TCR_RGN_NC 0b00 +#define TCR_RGN_WBWA 0b01 +#define TCR_RGN_WT 0b10 +#define TCR_RGN_WBRA 0b11 + +// +// Shareability encodings +// +#define TCR_SHARE_NONE 0b00 +#define TCR_SHARE_OUTER 0b10 +#define TCR_SHARE_INNER 0b11 + +// +// Granule size encodings +// +#define TCR_GRANULE_4K 0b00 +#define TCR_GRANULE_64K 0b01 +#define TCR_GRANULE_16K 0b10 + +// +// Physical Address sizes +// +#define TCR_SIZE_4G 0b000 +#define TCR_SIZE_64G 0b001 +#define TCR_SIZE_1T 0b010 +#define TCR_SIZE_4T 0b011 +#define TCR_SIZE_16T 0b100 +#define TCR_SIZE_256T 0b101 + +// +// Translation Control Register fields +// +#define TCR_EL1_T0SZ_SHIFT 0 +#define TCR_EL1_EPD0 (1 << 7) +#define TCR_EL1_IRGN0_SHIFT 8 +#define TCR_EL1_ORGN0_SHIFT 10 +#define TCR_EL1_SH0_SHIFT 12 +#define TCR_EL1_TG0_SHIFT 14 + +#define TCR_EL1_T1SZ_SHIFT 16 +#define TCR_EL1_A1 (1 << 22) +#define TCR_EL1_EPD1 (1 << 23) +#define TCR_EL1_IRGN1_SHIFT 24 +#define TCR_EL1_ORGN1_SHIFT 26 +#define TCR_EL1_SH1_SHIFT 28 +#define TCR_EL1_TG1_SHIFT 30 +#define TCR_EL1_IPS_SHIFT 32 +#define TCR_EL1_AS (1 << 36) +#define TCR_EL1_TBI0 (1 << 37) +#define TCR_EL1_TBI1 (1 << 38) + +// +// Stage 1 Translation Table descriptor fields +// +#define TT_S1_ATTR_FAULT (0b00 << 0) +#define TT_S1_ATTR_BLOCK (0b01 << 0) // Level 1/2 +#define TT_S1_ATTR_TABLE (0b11 << 0) // Level 0/1/2 +#define TT_S1_ATTR_PAGE (0b11 << 0) // Level 3 + +#define TT_S1_ATTR_MATTR_LSB 2 + +#define TT_S1_ATTR_NS (1 << 5) + +#define TT_S1_ATTR_AP_RW_PL1 (0b00 << 6) +#define TT_S1_ATTR_AP_RW_ANY (0b01 << 6) +#define TT_S1_ATTR_AP_RO_PL1 (0b10 << 6) +#define TT_S1_ATTR_AP_RO_ANY (0b11 << 6) + +#define TT_S1_ATTR_SH_NONE (0b00 << 8) +#define TT_S1_ATTR_SH_OUTER (0b10 << 8) +#define TT_S1_ATTR_SH_INNER (0b11 << 8) + +#define TT_S1_ATTR_AF (1 << 10) +#define TT_S1_ATTR_nG (1 << 11) + +#define TT_S1_ATTR_CONTIG (1 << 52) +#define TT_S1_ATTR_PXN (1 << 53) +#define TT_S1_ATTR_UXN (1 << 54) + +#define TT_S1_MAIR_DEV_nGnRnE 0b00000000 +#define TT_S1_MAIR_DEV_nGnRE 0b00000100 +#define TT_S1_MAIR_DEV_nGRE 0b00001000 +#define TT_S1_MAIR_DEV_GRE 0b00001100 + +// +// Inner and Outer Normal memory attributes use the same bit patterns +// Outer attributes just need to be shifted up +// +#define TT_S1_MAIR_OUTER_SHIFT 4 + +#define TT_S1_MAIR_WT_TRANS_RA 0b0010 + +#define TT_S1_MAIR_WB_TRANS_RA 0b0110 +#define TT_S1_MAIR_WB_TRANS_RWA 0b0111 + +#define TT_S1_MAIR_WT_RA 0b1010 + +#define TT_S1_MAIR_WB_RA 0b1110 +#define TT_S1_MAIR_WB_RWA 0b1111 + +#endif // V8_MMU_H diff --git a/ports_smp/cortex_a5x_smp/gnu/example_build/common/v8_system.h b/ports_smp/cortex_a5x_smp/gnu/example_build/common/v8_system.h new file mode 100644 index 00000000..ff96deff --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/example_build/common/v8_system.h @@ -0,0 +1,115 @@ +// +// Defines for v8 System Registers +// +// Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// + +#ifndef V8_SYSTEM_H +#define V8_SYSTEM_H + +// +// AArch64 SPSR +// +#define AARCH64_SPSR_EL3h 0b1101 +#define AARCH64_SPSR_EL3t 0b1100 +#define AARCH64_SPSR_EL2h 0b1001 +#define AARCH64_SPSR_EL2t 0b1000 +#define AARCH64_SPSR_EL1h 0b0101 +#define AARCH64_SPSR_EL1t 0b0100 +#define AARCH64_SPSR_EL0t 0b0000 +#define AARCH64_SPSR_RW (1 << 4) +#define AARCH64_SPSR_F (1 << 6) +#define AARCH64_SPSR_I (1 << 7) +#define AARCH64_SPSR_A (1 << 8) +#define AARCH64_SPSR_D (1 << 9) +#define AARCH64_SPSR_IL (1 << 20) +#define AARCH64_SPSR_SS (1 << 21) +#define AARCH64_SPSR_V (1 << 28) +#define AARCH64_SPSR_C (1 << 29) +#define AARCH64_SPSR_Z (1 << 30) +#define AARCH64_SPSR_N (1 << 31) + +// +// Multiprocessor Affinity Register +// +#define MPIDR_EL1_AFF3_LSB 32 +#define MPIDR_EL1_U (1 << 30) +#define MPIDR_EL1_MT (1 << 24) +#define MPIDR_EL1_AFF2_LSB 16 +#define MPIDR_EL1_AFF1_LSB 8 +#define MPIDR_EL1_AFF0_LSB 0 +#define MPIDR_EL1_AFF_WIDTH 8 + +// +// Data Cache Zero ID Register +// +#define DCZID_EL0_BS_LSB 0 +#define DCZID_EL0_BS_WIDTH 4 +#define DCZID_EL0_DZP_LSB 5 +#define DCZID_EL0_DZP (1 << 5) + +// +// System Control Register +// +#define SCTLR_EL1_UCI (1 << 26) +#define SCTLR_ELx_EE (1 << 25) +#define SCTLR_EL1_E0E (1 << 24) +#define SCTLR_ELx_WXN (1 << 19) +#define SCTLR_EL1_nTWE (1 << 18) +#define SCTLR_EL1_nTWI (1 << 16) +#define SCTLR_EL1_UCT (1 << 15) +#define SCTLR_EL1_DZE (1 << 14) +#define SCTLR_ELx_I (1 << 12) +#define SCTLR_EL1_UMA (1 << 9) +#define SCTLR_EL1_SED (1 << 8) +#define SCTLR_EL1_ITD (1 << 7) +#define SCTLR_EL1_THEE (1 << 6) +#define SCTLR_EL1_CP15BEN (1 << 5) +#define SCTLR_EL1_SA0 (1 << 4) +#define SCTLR_ELx_SA (1 << 3) +#define SCTLR_ELx_C (1 << 2) +#define SCTLR_ELx_A (1 << 1) +#define SCTLR_ELx_M (1 << 0) + +// +// Architectural Feature Access Control Register +// +#define CPACR_EL1_TTA (1 << 28) +#define CPACR_EL1_FPEN (3 << 20) + +// +// Architectural Feature Trap Register +// +#define CPTR_ELx_TCPAC (1 << 31) +#define CPTR_ELx_TTA (1 << 20) +#define CPTR_ELx_TFP (1 << 10) + +// +// Secure Configuration Register +// +#define SCR_EL3_TWE (1 << 13) +#define SCR_EL3_TWI (1 << 12) +#define SCR_EL3_ST (1 << 11) +#define SCR_EL3_RW (1 << 10) +#define SCR_EL3_SIF (1 << 9) +#define SCR_EL3_HCE (1 << 8) +#define SCR_EL3_SMD (1 << 7) +#define SCR_EL3_EA (1 << 3) +#define SCR_EL3_FIQ (1 << 2) +#define SCR_EL3_IRQ (1 << 1) +#define SCR_EL3_NS (1 << 0) + +// +// Hypervisor Configuration Register +// +#define HCR_EL2_ID (1 << 33) +#define HCR_EL2_CD (1 << 32) +#define HCR_EL2_RW (1 << 31) +#define HCR_EL2_TRVM (1 << 30) +#define HCR_EL2_HVC (1 << 29) +#define HCR_EL2_TDZ (1 << 28) + +#endif // V8_SYSTEM_H diff --git a/ports_smp/cortex_a5x_smp/gnu/example_build/common/v8_utils.S b/ports_smp/cortex_a5x_smp/gnu/example_build/common/v8_utils.S new file mode 100644 index 00000000..f0fcef26 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/example_build/common/v8_utils.S @@ -0,0 +1,69 @@ +// +// Simple utility routines for baremetal v8 code +// +// Copyright (c) 2013-2017 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// + +#include "v8_system.h" + + .text + .cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + +// +// void *ZeroBlock(void *blockPtr, unsigned int nBytes) +// +// Zero fill a block of memory +// Fill memory pages or similar structures with zeros. +// The byte count must be a multiple of the block fill size (16 bytes) +// +// Inputs: +// blockPtr - base address of block to fill +// nBytes - block size, in bytes +// +// Returns: +// pointer to just filled block, NULL if nBytes is +// incompatible with block fill size +// + .global ZeroBlock + .type ZeroBlock, "function" + .cfi_startproc +ZeroBlock: + + // + // we fill data by steam, 16 bytes at a time: check that + // blocksize is a multiple of that + // + ubfx x2, x1, #0, #4 + cbnz x2, incompatible + + // + // we already have one register full of zeros, get another + // + mov x3, x2 + + // + // OK, set temporary pointer and away we go + // + add x0, x0, x1 + +loop0: + subs x1, x1, #16 + stp x2, x3, [x0, #-16]! + b.ne loop0 + + // + // that's all - x0 will be back to its start value + // + ret + + // + // parameters are incompatible with block size - return + // an indication that this is so + // +incompatible: + mov x0,#0 + ret + .cfi_endproc diff --git a/ports_smp/cortex_a5x_smp/gnu/example_build/common/vectors.S b/ports_smp/cortex_a5x_smp/gnu/example_build/common/vectors.S new file mode 100644 index 00000000..9e60e001 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/example_build/common/vectors.S @@ -0,0 +1,252 @@ +// ------------------------------------------------------------ +// Armv8-A Vector tables +// +// Copyright (c) 2014-2016 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + + + .global el1_vectors + .global el2_vectors + .global el3_vectors + .global c0sync1 + .global irqHandler + .global fiqHandler + .global irqFirstLevelHandler + .global fiqFirstLevelHandler + + .section EL1VECTORS, "ax" + .align 11 + +// +// Current EL with SP0 +// +el1_vectors: +c0sync1: B c0sync1 + + .balign 0x80 +c0irq1: B irqFirstLevelHandler + + .balign 0x80 +c0fiq1: B fiqFirstLevelHandler + + .balign 0x80 +c0serr1: B c0serr1 + +// +// Current EL with SPx +// + .balign 0x80 +cxsync1: B cxsync1 + + .balign 0x80 +cxirq1: B irqFirstLevelHandler + + .balign 0x80 +cxfiq1: B fiqFirstLevelHandler + + .balign 0x80 +cxserr1: B cxserr1 + +// +// Lower EL using AArch64 +// + .balign 0x80 +l64sync1: B l64sync1 + + .balign 0x80 +l64irq1: B irqFirstLevelHandler + + .balign 0x80 +l64fiq1: B fiqFirstLevelHandler + + .balign 0x80 +l64serr1: B l64serr1 + +// +// Lower EL using AArch32 +// + .balign 0x80 +l32sync1: B l32sync1 + + .balign 0x80 +l32irq1: B irqFirstLevelHandler + + .balign 0x80 +l32fiq1: B fiqFirstLevelHandler + + .balign 0x80 +l32serr1: B l32serr1 + +//---------------------------------------------------------------- + + .section EL2VECTORS, "ax" + .align 11 + +// +// Current EL with SP0 +// +el2_vectors: +c0sync2: B c0sync2 + + .balign 0x80 +c0irq2: B irqFirstLevelHandler + + .balign 0x80 +c0fiq2: B fiqFirstLevelHandler + + .balign 0x80 +c0serr2: B c0serr2 + +// +// Current EL with SPx +// + .balign 0x80 +cxsync2: B cxsync2 + + .balign 0x80 +cxirq2: B irqFirstLevelHandler + + .balign 0x80 +cxfiq2: B fiqFirstLevelHandler + + .balign 0x80 +cxserr2: B cxserr2 + +// +// Lower EL using AArch64 +// + .balign 0x80 +l64sync2: B l64sync2 + + .balign 0x80 +l64irq2: B irqFirstLevelHandler + + .balign 0x80 +l64fiq2: B fiqFirstLevelHandler + + .balign 0x80 +l64serr2: B l64serr2 + +// +// Lower EL using AArch32 +// + .balign 0x80 +l32sync2: B l32sync2 + + .balign 0x80 +l32irq2: B irqFirstLevelHandler + + .balign 0x80 +l32fiq2: B fiqFirstLevelHandler + + .balign 0x80 +l32serr2: B l32serr2 + +//---------------------------------------------------------------- + + .section EL3VECTORS, "ax" + .align 11 + +// +// Current EL with SP0 +// +el3_vectors: +c0sync3: B c0sync3 + + .balign 0x80 +c0irq3: B irqFirstLevelHandler + + .balign 0x80 +c0fiq3: B fiqFirstLevelHandler + + .balign 0x80 +c0serr3: B c0serr3 + +// +// Current EL with SPx +// + .balign 0x80 +cxsync3: B cxsync3 + + .balign 0x80 +cxirq3: B irqFirstLevelHandler + + .balign 0x80 +cxfiq3: B fiqFirstLevelHandler + + .balign 0x80 +cxserr3: B cxserr3 + +// +// Lower EL using AArch64 +// + .balign 0x80 +l64sync3: B l64sync3 + + .balign 0x80 +l64irq3: B irqFirstLevelHandler + + .balign 0x80 +l64fiq3: B fiqFirstLevelHandler + + .balign 0x80 +l64serr3: B l64serr3 + +// +// Lower EL using AArch32 +// + .balign 0x80 +l32sync3: B l32sync3 + + .balign 0x80 +l32irq3: B irqFirstLevelHandler + + .balign 0x80 +l32fiq3: B fiqFirstLevelHandler + + .balign 0x80 +l32serr3: B l32serr3 + + + .section InterruptHandlers, "ax" + .balign 4 + + .type irqFirstLevelHandler, "function" +irqFirstLevelHandler: + MSR SPSel, 0 + STP x29, x30, [sp, #-16]! + BL _tx_thread_context_save + BL irqHandler + B _tx_thread_context_restore + + .type fiqFirstLevelHandler, "function" +fiqFirstLevelHandler: + STP x29, x30, [sp, #-16]! + STP x18, x19, [sp, #-16]! + STP x16, x17, [sp, #-16]! + STP x14, x15, [sp, #-16]! + STP x12, x13, [sp, #-16]! + STP x10, x11, [sp, #-16]! + STP x8, x9, [sp, #-16]! + STP x6, x7, [sp, #-16]! + STP x4, x5, [sp, #-16]! + STP x2, x3, [sp, #-16]! + STP x0, x1, [sp, #-16]! + + BL fiqHandler + + LDP x0, x1, [sp], #16 + LDP x2, x3, [sp], #16 + LDP x4, x5, [sp], #16 + LDP x6, x7, [sp], #16 + LDP x8, x9, [sp], #16 + LDP x10, x11, [sp], #16 + LDP x12, x13, [sp], #16 + LDP x14, x15, [sp], #16 + LDP x16, x17, [sp], #16 + LDP x18, x19, [sp], #16 + LDP x29, x30, [sp], #16 + ERET diff --git a/ports_smp/cortex_a5x_smp/gnu/example_build/sample_threadx/.cproject b/ports_smp/cortex_a5x_smp/gnu/example_build/sample_threadx/.cproject new file mode 100644 index 00000000..29f9e0cb --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/example_build/sample_threadx/.cproject @@ -0,0 +1,83 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/cortex_a5x_smp/gnu/example_build/sample_threadx/.project b/ports_smp/cortex_a5x_smp/gnu/example_build/sample_threadx/.project new file mode 100644 index 00000000..92288300 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/example_build/sample_threadx/.project @@ -0,0 +1,33 @@ + + + sample_threadx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + common + 2 + $%7BPARENT-1-PROJECT_LOC%7D/common + + + diff --git a/ports_smp/cortex_a5x_smp/gnu/example_build/sample_threadx/.settings/language.settings.xml b/ports_smp/cortex_a5x_smp/gnu/example_build/sample_threadx/.settings/language.settings.xml new file mode 100644 index 00000000..99c19d0c --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/example_build/sample_threadx/.settings/language.settings.xml @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/ports_smp/cortex_a5x_smp/gnu/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a5x_smp/gnu/example_build/sample_threadx/sample_threadx.c new file mode 100644 index 00000000..b37d9d6f --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/example_build/sample_threadx/sample_threadx.c @@ -0,0 +1,389 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" +#include + +extern void init_timer(void); /* in timer_interrupts.c */ + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 0x20000 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define a memory area to create a byte pool in. */ + +UCHAR memory_area[DEMO_BYTE_POOL_SIZE] __attribute__((aligned (8))); + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_TIMER timer_0; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +#ifdef TX_ENABLE_EVENT_TRACE + +UCHAR event_buffer[65536]; + +#endif + + +int main(void) +{ + + /* Initialize timer. */ + init_timer(); + + /* Enter ThreadX. */ + tx_kernel_enter(); + + return 0; +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer; + + +#ifdef TX_ENABLE_EVENT_TRACE + + tx_trace_enable(event_buffer, sizeof(event_buffer), 32); +#endif + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEMO_BYTE_POOL_SIZE); + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + diff --git a/ports_smp/cortex_a5x_smp/gnu/example_build/sample_threadx/sample_threadx.launch b/ports_smp/cortex_a5x_smp/gnu/example_build/sample_threadx/sample_threadx.launch new file mode 100644 index 00000000..7c90c825 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/example_build/sample_threadx/sample_threadx.launch @@ -0,0 +1,421 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/cortex_a5x_smp/gnu/example_build/tx/.cproject b/ports_smp/cortex_a5x_smp/gnu/example_build/tx/.cproject new file mode 100644 index 00000000..3267d408 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/example_build/tx/.cproject @@ -0,0 +1,137 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/cortex_a5x_smp/gnu/example_build/tx/.project b/ports_smp/cortex_a5x_smp/gnu/example_build/tx/.project new file mode 100644 index 00000000..10681969 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/example_build/tx/.project @@ -0,0 +1,48 @@ + + + tx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + inc_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_smp/inc + + + inc_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/inc + + + src_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_smp/src + + + src_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/src + + + diff --git a/ports_smp/cortex_a5x_smp/gnu/example_build/tx/.settings/language.settings.xml b/ports_smp/cortex_a5x_smp/gnu/example_build/tx/.settings/language.settings.xml new file mode 100644 index 00000000..87713474 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/example_build/tx/.settings/language.settings.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/cortex_a5x_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a5x_smp/gnu/inc/tx_port.h new file mode 100644 index 00000000..362b2062 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/inc/tx_port.h @@ -0,0 +1,430 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-A5x-SMP/GNU */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/************* Define ThreadX SMP constants. *************/ + +/* Define the ThreadX SMP maximum number of cores. */ + +#ifndef TX_THREAD_SMP_MAX_CORES +#define TX_THREAD_SMP_MAX_CORES 4 +#endif + + +/* Define the ThreadX SMP core mask. */ + +#ifndef TX_THREAD_SMP_CORE_MASK +#define TX_THREAD_SMP_CORE_MASK 0xF /* Where bit 0 represents Core 0, bit 1 represents Core 1, etc. */ +#endif + + +/* Define INLINE_DECLARE to whitespace for ARM compiler. */ + +#define INLINE_DECLARE + + +/* Define ThreadX SMP initialization macro. */ + +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION + + +/* Define ThreadX SMP pre-scheduler initialization. */ + +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION + + +/* Enable the inter-core interrupt logic. */ + +#define TX_THREAD_SMP_INTER_CORE_INTERRUPT + + +/* Determine if there is customer-specific wakeup logic needed. */ + +#ifdef TX_THREAD_SMP_WAKEUP_LOGIC + +/* Include customer-specific wakeup code. */ + +#include "tx_thread_smp_core_wakeup.h" +#else + +#ifdef TX_THREAD_SMP_DEFAULT_WAKEUP_LOGIC + +/* Default wakeup code. */ +#define TX_THREAD_SMP_WAKEUP_LOGIC +#define TX_THREAD_SMP_WAKEUP(i) _tx_thread_smp_core_preempt(i) +#endif +#endif + + +/* Ensure that the in-line resume/suspend define is not allowed. */ + +#ifdef TX_INLINE_THREAD_RESUME_SUSPEND +#undef TX_INLINE_THREAD_RESUME_SUSPEND +#endif + + +/************* End ThreadX SMP constants. *************/ + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef int LONG; +typedef unsigned int ULONG; +typedef unsigned long long ULONG64; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Override the alignment type to use 64-bit alignment and storage for pointers. */ + +#define ALIGN_TYPE_DEFINED +typedef unsigned long long ALIGN_TYPE; + + +/* Override the free block marker for byte pools to be a 64-bit constant. */ + +#define TX_BYTE_BLOCK_FREE ((ALIGN_TYPE) 0xFFFFEEEEFFFFEEEE) + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 4096 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#define TX_INT_ENABLE 0x00 /* Enable IRQ & FIQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE _tx_thread_smp_time_get() +#endif +#else +#ifndef TX_TRACE_TIME_SOURCE +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_fp_enable; +#define TX_THREAD_EXTENSION_3 VOID *tx_thread_extension_ptr; + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) b = (UINT) __builtin_ctz((unsigned int) m); + +#endif + + +/* Define the internal timer extension to also hold the thread pointer such that _tx_thread_timeout + can figure out what thread timeout to process. */ + +#define TX_TIMER_INTERNAL_EXTENSION VOID *tx_timer_internal_extension_ptr; + + +/* Define the thread timeout setup logic in _tx_thread_create. */ + +#define TX_THREAD_CREATE_TIMEOUT_SETUP(t) (t) -> tx_thread_timer.tx_timer_internal_timeout_function = &(_tx_thread_timeout); \ + (t) -> tx_thread_timer.tx_timer_internal_timeout_param = 0; \ + (t) -> tx_thread_timer.tx_timer_internal_extension_ptr = (VOID *) (t); + + +/* Define the thread timeout pointer setup in _tx_thread_timeout. */ + +#define TX_THREAD_TIMEOUT_POINTER_SETUP(t) (t) = (TX_THREAD *) _tx_timer_expired_timer_ptr -> tx_timer_internal_extension_ptr; + + +/************* Define ThreadX SMP data types and function prototypes. *************/ + +struct TX_THREAD_STRUCT; + + +/* Define the ThreadX SMP protection structure. */ + +typedef struct TX_THREAD_SMP_PROTECT_STRUCT +{ + ULONG tx_thread_smp_protect_in_force; + ULONG tx_thread_smp_protect_core; + ULONG tx_thread_smp_protect_count; + ULONG tx_thread_smp_protect_pad_0; + ULONG tx_thread_smp_protect_pad_1; + ULONG tx_thread_smp_protect_pad_2; + ULONG tx_thread_smp_protect_pad_3; +} TX_THREAD_SMP_PROTECT; + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_smp_protect(); +#define TX_RESTORE _tx_thread_smp_unprotect(interrupt_save); + +/************* End ThreadX SMP data type and function prototype definitions. *************/ + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define VFP extension for the Cortex-A5x. Each is assumed to be called in the context of the executing + thread. */ + +#ifndef TX_SOURCE_CODE +#define tx_thread_fp_enable _tx_thread_fp_enable +#define tx_thread_fp_disable _tx_thread_fp_disable +#endif + +VOID tx_thread_fp_enable(VOID); +VOID tx_thread_fp_disable(VOID); + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5x-SMP/GNU Version 6.0.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + + + diff --git a/ports_smp/cortex_a5x_smp/gnu/readme_threadx.txt b/ports_smp/cortex_a5x_smp/gnu/readme_threadx.txt new file mode 100644 index 00000000..6786efdf --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/readme_threadx.txt @@ -0,0 +1,257 @@ + Microsoft's Azure RTOS ThreadX for Cortex-A5x + + Using the ARM GNU Compiler & DS + +1. Import the ThreadX Projects + +In order to build the ThreadX SMP library and the ThreadX SMP demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +into your DS workspace. + +Note: the projects were made using DS-5, so DS will prompt you to migrate the projects. +This is expected, so please do so. + + +2. Building the ThreadX SMP run-time Library + +Building the ThreadX SMP library is easy; simply select the Eclipse project file +"tx" and then select the build button. You should now observe the compilation +and assembly of the ThreadX SMP library. This project build produces the ThreadX SMP +library file tx.a. + + +3. Demonstration System + +The ThreadX SMP demonstration is designed to execute under the DS-5 debugger on the +'Debug Cortex-A53x4 SMP' FVP which must be downloaded from the ARM website and +requires a license. + +Building the demonstration is easy; simply select the sample_threadx project, and +select the build button. Next, in the sample_threadx project, right-click on the +sample_threadx.launch file and select 'Debug As -> sample_threadx'. The debugger is +setup for the Cortex-53x4 SMP FVP, so selecting "Debug" will launch the FVP, load +the sample_threadx.axf ELF file and run to main. You are now ready to execute the +ThreadX SMP demonstration. + + +4. System Initialization + +The entry point in ThreadX SMP for the Cortex-A5x using GCC tools is at label +"start64". This is defined within the GCC compiler's startup code. In addition, +this is where all static and global pre-set C variable initialization processing +takes place. + +The ThreadX SMP tx_initialize_low_level.s file is responsible for determining the +first available RAM address for use by the application, which is supplied as the +sole input parameter to your application definition function, tx_application_define. + + +5. Register Usage and Stack Frames + +The 64-bit GCC compiler assumes that registers x0-x18 are scratch registers +for each function. All other registers used by a C function must be preserved +by the function. ThreadX SMP takes advantage of this in situations where a context +switch happens as a result of making a ThreadX SMP service call (which is itself a +C function). In such cases, the saved context of a thread is only the +non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + +FP not enabled and TX_THREAD.tx_thread_fp_enable == 0: + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x000 SPSR DAIF + 0x008 ELR 0 + 0x010 x28 x27 + 0x018 reserved x28 + 0x020 x26 x25 + 0x028 x27 x26 + 0x030 x24 x23 + 0x038 x25 x24 + 0x040 x22 x21 + 0x048 x23 x22 + 0x050 x20 x19 + 0x058 x21 x20 + 0x060 x18 x29 + 0x068 x19 x30 + 0x070 x16 + 0x078 x17 + 0x080 x14 + 0x088 x15 + 0x090 x12 + 0x098 x13 + 0x0A0 x10 + 0x0A8 x11 + 0x0B0 x8 + 0x0B8 x9 + 0x0C0 x6 + 0x0C8 x7 + 0x0D0 x4 + 0x0D8 x5 + 0x0E0 x2 + 0x0E8 x3 + 0x0F0 x0 + 0x0F8 x1 + 0x100 x29 + 0x108 x30 + + +FP enabled and TX_THREAD.tx_thread_fp_enable == 1: + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x000 SPSR DAIF + 0x008 ELR 0 + 0x010 FPSR FPSR + 0x018 FPCR FPCR + 0x020 q30 q14 + 0x030 q31 q15 + 0x040 q28 q12 + 0x050 q29 q13 + 0x060 q26 q10 + 0x070 q27 q11 + 0x080 q24 q8 + 0x090 q25 q9 + 0x0A0 q22 x27 + 0x0A8 x28 + 0x0B0 q23 x25 + 0x0B8 x26 + 0x0C0 q20 x23 + 0x0C8 x24 + 0x0D0 q21 x21 + 0x0D8 x22 + 0x0E0 q18 x19 + 0x0E8 x20 + 0x0F0 q19 x29 + 0x0F8 x30 + 0x100 q16 + 0x110 q17 + 0x120 q14 + 0x130 q15 + 0x140 q12 + 0x150 q13 + 0x160 q10 + 0x170 q11 + 0x180 q8 + 0x190 q9 + 0x1A0 q6 + 0x1B0 q7 + 0x1C0 q4 + 0x1D0 q5 + 0x1E0 q2 + 0x1F0 q3 + 0x200 q0 + 0x210 q1 + 0x220 x28 + 0x228 reserved + 0x230 x26 + 0x238 x27 + 0x240 x24 + 0x248 x25 + 0x250 x22 + 0x258 x23 + 0x260 x20 + 0x268 x21 + 0x270 x18 + 0x278 x19 + 0x280 x16 + 0x288 x17 + 0x290 x14 + 0x298 x15 + 0x2A0 x12 + 0x2A8 x13 + 0x2B0 x10 + 0x2B8 x11 + 0x2C0 x8 + 0x2C8 x9 + 0x2D0 x6 + 0x2D8 x7 + 0x2E0 x4 + 0x2E8 x5 + 0x2F0 x2 + 0x2F8 x3 + 0x300 x0 + 0x308 x1 + 0x310 x29 + 0x318 x30 + + + +6. Improving Performance + +The distribution version of ThreadX SMP is built without any compiler optimizations. +This makes it easy to debug because you can trace or set breakpoints inside of +ThreadX SMP itself. Of course, this costs some performance. To make it run faster, +you can change the project settings to the desired compiler optimization level. + +In addition, you can eliminate the ThreadX SMP basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX SMP provides complete and high-performance interrupt handling for Cortex-A5x +targets. Interrupts handlers for the 64-bit mode of the Cortex-A5x have the following +format: + + .global irq_handler +irq_handler: + MSR SPSel, 0 + STP x29, x30, [sp, #-16]! + BL _tx_thread_context_save + + /* Your ISR call goes here! */ + BL application_isr_handler + + B _tx_thread_context_restore + +By default, ThreadX SMP assumes EL3 level of execution. Running and taking exceptions in EL1 +and EL2 can be done by simply building the ThreadX library with either EL1 or EL2 defined. + + +8. ThreadX SMP Timer Interrupt + +ThreadX SMP requires a periodic interrupt source to manage all time-slicing, thread sleeps, +timeouts, and application timers. Without such a timer interrupt source, these services +are not functional. However, all other ThreadX services are operational without a +periodic timer source. + + +9. ARM FP Support + +By default, FP support is disabled for each thread. If saving the context of the FP registers +is needed, the following API call must be made from the context of the application thread - before +the FP usage: + +void tx_thread_fp_enable(void); + +After this API is called in the application, FP registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the FP registers +to be saved/restored. + +To disable FP register context saving, simply call the following API: + +void tx_thread_fp_disable(void); + + +10. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX SMP: + +06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A5x using ARM GCC and DS-5 tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_initialize_low_level.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_initialize_low_level.S new file mode 100644 index 00000000..b411b1d7 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_initialize_low_level.S @@ -0,0 +1,112 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-A5x-SMP/GNU */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_initialize_low_level(VOID) +{ */ + .global _tx_initialize_low_level + .type _tx_initialize_low_level, @function +_tx_initialize_low_level: + + MSR DAIFSet, 0x3 // Lockout interrupts + + + /* Save the system stack pointer. */ + /* _tx_thread_system_stack_ptr = (VOID_PTR) (sp); */ + + LDR x0, =_tx_thread_system_stack_ptr // Pickup address of system stack ptr + MOV x1, sp // Pickup SP + SUB x1, x1, #15 // + BIC x1, x1, #0xF // Get 16-bit alignment + STR x1, [x0] // Store system stack + + /* Save the first available memory address. */ + /* _tx_initialize_unused_memory = (VOID_PTR) __top_of_ram; */ + + LDR x0, =_tx_initialize_unused_memory // Pickup address of unused memory ptr + LDR x1, =__top_of_ram // Pickup unused memory address - A free + // memory section must be setup after the + // heap section. + STR x1, [x0] // Store unused memory address + + /* Done, return to caller. */ + + RET // Return to caller +/* } */ + + .align 3 + diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_context_restore.S new file mode 100644 index 00000000..03335d82 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_context_restore.S @@ -0,0 +1,393 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + +/* Include macros for modifying the wait list. */ +#include "tx_thread_smp_protection_wait_list_macros.h" + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore Cortex-A5x-SMP/GNU */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores the interrupt context if it is processing a */ +/* nested interrupt. If not, it returns to the interrupt thread if no */ +/* preemption is necessary. Otherwise, if preemption is necessary or */ +/* if no thread was running, the function returns to the scheduler. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling routine */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs Interrupt Service Routines */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_restore(VOID) +{ */ + .global _tx_thread_context_restore + .type _tx_thread_context_restore, @function +_tx_thread_context_restore: + + /* Lockout interrupts. */ + + MSR DAIFSet, 0x3 // Lockout interrupts + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR exit function to indicate an ISR is complete. */ + + BL _tx_execution_isr_exit // Call the ISR exit function +#endif + + /* Pickup the CPU ID. */ + + MRS x8, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x2, x8, #8, #8 // Isolate cluster ID +#endif + UBFX x8, x8, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x8, x8, x2, LSL #2 // Calculate CPU ID +#endif + + /* Determine if interrupts are nested. */ + /* if (--_tx_thread_system_state) + { */ + + LDR x3, =_tx_thread_system_state // Pickup address of system state var + LDR w2, [x3, x8, LSL #2] // Pickup system state + SUB w2, w2, #1 // Decrement the counter + STR w2, [x3, x8, LSL #2] // Store the counter + CMP w2, #0 // Was this the first interrupt? + BEQ __tx_thread_not_nested_restore // If so, not a nested restore + + /* Interrupts are nested. */ + + /* Just recover the saved registers and return to the point of + interrupt. */ + + LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL +#ifdef EL1 + MSR SPSR_EL1, x4 // Setup SPSR for return + MSR ELR_EL1, x5 // Setup point of interrupt +#else +#ifdef EL2 + MSR SPSR_EL2, x4 // Setup SPSR for return + MSR ELR_EL2, x5 // Setup point of interrupt +#else + MSR SPSR_EL3, x4 // Setup SPSR for return + MSR ELR_EL3, x5 // Setup point of interrupt +#endif +#endif + LDP x18, x19, [sp], #16 // Recover x18, x19 + LDP x16, x17, [sp], #16 // Recover x16, x17 + LDP x14, x15, [sp], #16 // Recover x14, x15 + LDP x12, x13, [sp], #16 // Recover x12, x13 + LDP x10, x11, [sp], #16 // Recover x10, x11 + LDP x8, x9, [sp], #16 // Recover x8, x9 + LDP x6, x7, [sp], #16 // Recover x6, x7 + LDP x4, x5, [sp], #16 // Recover x4, x5 + LDP x2, x3, [sp], #16 // Recover x2, x3 + LDP x0, x1, [sp], #16 // Recover x0, x1 + LDP x29, x30, [sp], #16 // Recover x29, x30 + ERET // Return to point of interrupt + + /* } */ +__tx_thread_not_nested_restore: + + /* Determine if a thread was interrupted and no preemption is required. */ + /* else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) + || (_tx_thread_preempt_disable)) + { */ + + LDR x1, =_tx_thread_current_ptr // Pickup address of current thread ptr + LDR x0, [x1, x8, LSL #3] // Pickup actual current thread pointer + CMP x0, #0 // Is it NULL? + BEQ __tx_thread_idle_system_restore // Yes, idle system was interrupted + LDR x3, =_tx_thread_execute_ptr // Pickup address of execute thread ptr + LDR x2, [x3, x8, LSL #3] // Pickup actual execute thread pointer + CMP x0, x2 // Is the same thread highest priority? + BEQ __tx_thread_no_preempt_restore // Same thread in the execute list, + // no preemption needs to happen + LDR x3, =_tx_thread_smp_protection // Build address to protection structure + LDR w3, [x3, #4] // Pickup the owning core + CMP w3, w8 // Is it this core? + BNE __tx_thread_preempt_restore // No, proceed to preempt thread + + LDR x3, =_tx_thread_preempt_disable // Pickup preempt disable address + LDR w2, [x3, #0] // Pickup actual preempt disable flag + CMP w2, #0 // Is it set? + BEQ __tx_thread_preempt_restore // No, okay to preempt this thread + +__tx_thread_no_preempt_restore: + + /* Restore interrupted thread or ISR. */ + + /* Pickup the saved stack pointer. */ + /* sp = _tx_thread_current_ptr -> tx_thread_stack_ptr; */ + + LDR x4, [x0, #8] // Switch to thread stack pointer + MOV sp, x4 // + + /* Recover the saved context and return to the point of interrupt. */ + + LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL1 +#ifdef EL1 + MSR SPSR_EL1, x4 // Setup SPSR for return + MSR ELR_EL1, x5 // Setup point of interrupt +#else +#ifdef EL2 + MSR SPSR_EL2, x4 // Setup SPSR for return + MSR ELR_EL2, x5 // Setup point of interrupt +#else + MSR SPSR_EL3, x4 // Setup SPSR for return + MSR ELR_EL3, x5 // Setup point of interrupt +#endif +#endif + LDP x18, x19, [sp], #16 // Recover x18, x19 + LDP x16, x17, [sp], #16 // Recover x16, x17 + LDP x14, x15, [sp], #16 // Recover x14, x15 + LDP x12, x13, [sp], #16 // Recover x12, x13 + LDP x10, x11, [sp], #16 // Recover x10, x11 + LDP x8, x9, [sp], #16 // Recover x8, x9 + LDP x6, x7, [sp], #16 // Recover x6, x7 + LDP x4, x5, [sp], #16 // Recover x4, x5 + LDP x2, x3, [sp], #16 // Recover x2, x3 + LDP x0, x1, [sp], #16 // Recover x0, x1 + LDP x29, x30, [sp], #16 // Recover x29, x30 + ERET // Return to point of interrupt + + /* } + else + { */ +__tx_thread_preempt_restore: + + /* Was the thread being preempted waiting for the lock? */ + /* if (_tx_thread_smp_protect_wait_counts[this_core] != 0) + { */ + + LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list + LDR w3, [x2, x8, LSL #2] // Load waiting value for this core + CMP w3, #0 + BEQ _nobody_waiting_for_lock // Is the core waiting for the lock? + + /* Do we not have the lock? This means the ISR never got the inter-core lock. */ + /* if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core) + { */ + + LDR x2, =_tx_thread_smp_protection // Load address of protection structure + LDR w3, [x2, #4] // Pickup the owning core + CMP w8, w3 // Compare our core to the owning core + BEQ _this_core_has_lock // Do we have the lock? + + /* We don't have the lock. This core should be in the list. Remove it. */ + /* _tx_thread_smp_protect_wait_list_remove(this_core); */ + + _tx_thread_smp_protect_wait_list_remove // Call macro to remove core from the list + B _nobody_waiting_for_lock // Leave + + /* } + else + { */ + /* We have the lock. This means the ISR got the inter-core lock, but + never released it because it saw that there was someone waiting. + Note this core is not in the list. */ + +_this_core_has_lock: + + /* We're no longer waiting. Note that this should be zero since this happens during thread preemption. */ + /* _tx_thread_smp_protect_wait_counts[core]--; */ + + LDR x2, =_tx_thread_smp_protect_wait_counts // Load waiting count list + LDR w3, [x2, x8, LSL #2] // Load waiting value for this core + SUB w3, w3, #1 // Decrement waiting value. Should be zero now + STR w3, [x2, x8, LSL #2] // Store new waiting value + + /* Now release the inter-core lock. */ + + /* Set protected core as invalid. */ + /* _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF; */ + + LDR x2, =_tx_thread_smp_protection // Load address of protection structure + MOV w3, #0xFFFFFFFF // Build invalid value + STR w3, [x2, #4] // Mark the protected core as invalid + DMB ISH // Ensure that accesses to shared resource have completed + + /* Release protection. */ + /* _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0; */ + + MOV w3, #0 // Build release protection value + STR w3, [x2, #0] // Release the protection + DSB ISH // To ensure update of the protection occurs before other CPUs awake + + /* Wake up waiting processors. Note interrupts are already enabled. */ + +#ifdef TX_ENABLE_WFE + SEV // Send event to other CPUs +#endif + + /* } + } */ + +_nobody_waiting_for_lock: + + LDR x4, [x0, #8] // Switch to thread stack pointer + MOV sp, x4 // + + LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL1 + STP x20, x21, [sp, #-16]! // Save x20, x21 + STP x22, x23, [sp, #-16]! // Save x22, x23 + STP x24, x25, [sp, #-16]! // Save x24, x25 + STP x26, x27, [sp, #-16]! // Save x26, x27 + STP x28, x29, [sp, #-16]! // Save x28, x29 +#ifdef ENABLE_ARM_FP + LDR w3, [x0, #268] // Pickup FP enable flag + CMP w3, #0 // Is FP enabled? + BEQ _skip_fp_save // No, skip FP save + STP q0, q1, [sp, #-32]! // Save q0, q1 + STP q2, q3, [sp, #-32]! // Save q2, q3 + STP q4, q5, [sp, #-32]! // Save q4, q5 + STP q6, q7, [sp, #-32]! // Save q6, q7 + STP q8, q9, [sp, #-32]! // Save q8, q9 + STP q10, q11, [sp, #-32]! // Save q10, q11 + STP q12, q13, [sp, #-32]! // Save q12, q13 + STP q14, q15, [sp, #-32]! // Save q14, q15 + STP q16, q17, [sp, #-32]! // Save q16, q17 + STP q18, q19, [sp, #-32]! // Save q18, q19 + STP q20, q21, [sp, #-32]! // Save q20, q21 + STP q22, q23, [sp, #-32]! // Save q22, q23 + STP q24, q25, [sp, #-32]! // Save q24, q25 + STP q26, q27, [sp, #-32]! // Save q26, q27 + STP q28, q29, [sp, #-32]! // Save q28, q29 + STP q30, q31, [sp, #-32]! // Save q30, q31 + MRS x2, FPSR // Pickup FPSR + MRS x3, FPCR // Pickup FPCR + STP x2, x3, [sp, #-16]! // Save FPSR, FPCR +_skip_fp_save: +#endif + STP x4, x5, [sp, #-16]! // Save x4 (SPSR_EL3), x5 (ELR_E3) + + MOV x3, sp // Move sp into x3 + STR x3, [x0, #8] // Save stack pointer in thread control + // block + LDR x3, =_tx_thread_system_stack_ptr // Pickup address of system stack + LDR x4, [x3, x8, LSL #3] // Pickup system stack pointer + MOV sp, x4 // Setup system stack pointer + + + /* Save the remaining time-slice and disable it. */ + /* if (_tx_timer_time_slice) + { */ + + LDR x3, =_tx_timer_time_slice // Pickup time-slice variable address + LDR w2, [x3, x8, LSL #2] // Pickup time-slice + CMP w2, #0 // Is it active? + BEQ __tx_thread_dont_save_ts // No, don't save it + + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + STR w2, [x0, #36] // Save thread's time-slice + MOV w2, #0 // Clear value + STR w2, [x3, x8, LSL #2] // Disable global time-slice flag + + /* } */ +__tx_thread_dont_save_ts: + + + /* Clear the current task pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + MOV x2, #0 // NULL value + STR x2, [x1, x8, LSL #3] // Clear current thread pointer + + /* Set bit indicating this thread is ready for execution. */ + + MOV x2, #1 // Build ready flag + STR w2, [x0, #260] // Set thread's ready flag + DMB ISH // Ensure that accesses to shared resource have completed + + /* Return to the scheduler. */ + /* _tx_thread_schedule(); */ + + /* } */ + +__tx_thread_idle_system_restore: + + /* Just return back to the scheduler! */ + + LDR x1, =_tx_thread_schedule // Build address for _tx_thread_schedule +#ifdef EL1 + MSR ELR_EL1, x1 // Setup point of interrupt +// MOV x1, #0x4 // Setup EL1 return +// MSR spsr_el1, x1 // Move into SPSR +#else +#ifdef EL2 + MSR ELR_EL2, x1 // Setup point of interrupt +// MOV x1, #0x8 // Setup EL2 return +// MSR spsr_el2, x1 // Move into SPSR +#else + MSR ELR_EL3, x1 // Setup point of interrupt +// MOV x1, #0xC // Setup EL3 return +// MSR spsr_el3, x1 // Move into SPSR +#endif +#endif + ERET // Return to scheduler +/* } */ + + diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_context_save.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_context_save.S new file mode 100644 index 00000000..27e60ccc --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_context_save.S @@ -0,0 +1,249 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save Cortex-A5x-SMP/GNU */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the context of an executing thread in the */ +/* beginning of interrupt processing. The function also ensures that */ +/* the system stack is used upon return to the calling ISR. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ISRs */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_context_save(VOID) +{ */ + .global _tx_thread_context_save + .type _tx_thread_context_save, @function +_tx_thread_context_save: + + /* Upon entry to this routine, it is assumed that IRQ/FIQ interrupts are locked + out, x29 (frame pointer), x30 (link register) are saved, we are in the proper EL, + and all other registers are intact. */ + + /* Check for a nested interrupt condition. */ + /* if (_tx_thread_system_state++) + { */ + + STP x0, x1, [sp, #-16]! // Save x0, x1 + STP x2, x3, [sp, #-16]! // Save x2, x3 + + /* Pickup the CPU ID. */ + + MRS x1, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x2, x1, #8, #8 // Isolate cluster ID +#endif + UBFX x1, x1, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x1, x1, x2, LSL #2 // Calculate CPU ID +#endif + + LDR x3, =_tx_thread_system_state // Pickup address of system state var + LDR w2, [x3, x1, LSL #2] // Pickup system state + CMP w2, #0 // Is this the first interrupt? + BEQ __tx_thread_not_nested_save // Yes, not a nested context save + + /* Nested interrupt condition. */ + + ADD w2, w2, #1 // Increment the nested interrupt counter + STR w2, [x3, x1, LSL #2] // Store it back in the variable + + /* Save the rest of the scratch registers on the stack and return to the + calling ISR. */ + + STP x4, x5, [sp, #-16]! // Save x4, x5 + STP x6, x7, [sp, #-16]! // Save x6, x7 + STP x8, x9, [sp, #-16]! // Save x8, x9 + STP x10, x11, [sp, #-16]! // Save x10, x11 + STP x12, x13, [sp, #-16]! // Save x12, x13 + STP x14, x15, [sp, #-16]! // Save x14, x15 + STP x16, x17, [sp, #-16]! // Save x16, x17 + STP x18, x19, [sp, #-16]! // Save x18, x19 +#ifdef EL1 + MRS x0, SPSR_EL1 // Pickup SPSR + MRS x1, ELR_EL1 // Pickup ELR (point of interrupt) +#else +#ifdef EL2 + MRS x0, SPSR_EL2 // Pickup SPSR + MRS x1, ELR_EL2 // Pickup ELR (point of interrupt) +#else + MRS x0, SPSR_EL3 // Pickup SPSR + MRS x1, ELR_EL3 // Pickup ELR (point of interrupt) +#endif +#endif + STP x0, x1, [sp, #-16]! // Save SPSR, ELR + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + STP x29, x30, [sp, #-16]! // Save x29, x30 + BL _tx_execution_isr_enter // Call the ISR enter function + LDP x29, x30, [sp], #16 // Recover x29, x30 +#endif + + /* Return to the ISR. */ + + RET // Return to ISR + +__tx_thread_not_nested_save: + /* } */ + + /* Otherwise, not nested, check to see if a thread was running. */ + /* else if (_tx_thread_current_ptr) + { */ + + ADD w2, w2, #1 // Increment the interrupt counter + STR w2, [x3, x1, LSL #2] // Store it back in the variable + LDR x2, =_tx_thread_current_ptr // Pickup address of current thread ptr + LDR x0, [x2, x1, LSL #3] // Pickup current thread pointer + CMP x0, #0 // Is it NULL? + BEQ __tx_thread_idle_system_save // If so, interrupt occurred in + // scheduling loop - nothing needs saving! + + /* Save minimal context of interrupted thread. */ + + STP x4, x5, [sp, #-16]! // Save x4, x5 + STP x6, x7, [sp, #-16]! // Save x6, x7 + STP x8, x9, [sp, #-16]! // Save x8, x9 + STP x10, x11, [sp, #-16]! // Save x10, x11 + STP x12, x13, [sp, #-16]! // Save x12, x13 + STP x14, x15, [sp, #-16]! // Save x14, x15 + STP x16, x17, [sp, #-16]! // Save x16, x17 + STP x18, x19, [sp, #-16]! // Save x18, x19 +#ifdef EL1 + MRS x4, SPSR_EL1 // Pickup SPSR + MRS x5, ELR_EL1 // Pickup ELR (point of interrupt) +#else +#ifdef EL2 + MRS x4, SPSR_EL2 // Pickup SPSR + MRS x5, ELR_EL2 // Pickup ELR (point of interrupt) +#else + MRS x4, SPSR_EL3 // Pickup SPSR + MRS x5, ELR_EL3 // Pickup ELR (point of interrupt) +#endif +#endif + STP x4, x5, [sp, #-16]! // Save SPSR, ELR + + /* Save the current stack pointer in the thread's control block. */ + /* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */ + + MOV x4, sp // + STR x4, [x0, #8] // Save thread stack pointer + + /* Switch to the system stack. */ + /* sp = _tx_thread_system_stack_ptr; */ + + LDR x3, =_tx_thread_system_stack_ptr // Pickup address of system stack + MRS x1, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x2, x1, #8, #8 // Isolate cluster ID +#endif + UBFX x1, x1, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x1, x1, x2, LSL #2 // Calculate CPU ID +#endif + + LDR x4, [x3, x1, LSL #3] // Pickup system stack pointer + MOV sp, x4 // Setup system stack pointer + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + STP x29, x30, [sp, #-16]! // Save x29, x30 + BL _tx_execution_isr_enter // Call the ISR enter function + LDP x29, x30, [sp], #16 // Recover x29, x30 +#endif + + RET // Return to caller + + /* } + else + { */ + +__tx_thread_idle_system_save: + + /* Interrupt occurred in the scheduling loop. */ + + /* Not much to do here, just adjust the stack pointer, and return to IRQ + processing. */ + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the ISR enter function to indicate an ISR is executing. */ + + STP x29, x30, [sp, #-16]! // Save x29, x30 + BL _tx_execution_isr_enter // Call the ISR enter function + LDP x29, x30, [sp], #16 // Recover x29, x30 +#endif + + ADD sp, sp, #48 // Recover saved registers + RET // Continue IRQ processing + + /* } +} */ + + diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_fp_disable.c b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_fp_disable.c new file mode 100644 index 00000000..b38041d1 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_fp_disable.c @@ -0,0 +1,95 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fp_disable Cortex-A5x-SMP/GNU */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function disables the FP for the currently executing thread. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_fp_disable(VOID) +{ + +TX_THREAD *thread_ptr; +ULONG system_state; + + + /* Pickup the current thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr); + + /* Get the system state. */ + system_state = TX_THREAD_GET_SYSTEM_STATE(); + + /* Make sure it is not NULL. */ + if (thread_ptr != TX_NULL) + { + + /* Thread is running... make sure the call is from the thread context. */ + if (system_state == 0) + { + + /* Yes, now set the FP enable flag to false in the TX_THREAD structure. */ + thread_ptr -> tx_thread_fp_enable = TX_FALSE; + } + } +} + diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_fp_enable.c b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_fp_enable.c new file mode 100644 index 00000000..5fb43b8b --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_fp_enable.c @@ -0,0 +1,94 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_fp_enable Cortex-A5x-SMP/GNU */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function enabled the FP for the currently executing thread. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_fp_enable(VOID) +{ + +TX_THREAD *thread_ptr; +ULONG system_state; + + + /* Pickup the current thread pointer. */ + TX_THREAD_GET_CURRENT(thread_ptr); + + /* Get the system state. */ + system_state = TX_THREAD_GET_SYSTEM_STATE(); + + /* Make sure it is not NULL. */ + if (thread_ptr != TX_NULL) + { + + /* Thread is running... make sure the call is from the thread context. */ + if (system_state == 0) + { + + /* Yes, now setup the FP enable flag in the TX_THREAD structure. */ + thread_ptr -> tx_thread_fp_enable = TX_TRUE; + } + } +} + diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..880a629e --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_interrupt_control.S @@ -0,0 +1,89 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/*#define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control Cortex-A5x-SMP/GNU */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_control(UINT new_posture) +{ */ + .global _tx_thread_interrupt_control + .type _tx_thread_interrupt_control, @function +_tx_thread_interrupt_control: + + /* Pickup current interrupt lockout posture. */ + + MRS x1, DAIF // Pickup current interrupt posture + + /* Apply the new interrupt posture. */ + + MSR DAIF, x0 // Set new interrupt posture + MOV x0, x1 // Setup return value + RET // Return to caller +/* } */ + diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_interrupt_disable.S new file mode 100644 index 00000000..9bd1249d --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_interrupt_disable.S @@ -0,0 +1,87 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_disable Cortex-A5x-SMP/GNU */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for disabling interrupts */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_disable(void) +{ */ + .global _tx_thread_interrupt_disable + .type _tx_thread_interrupt_disable, @function +_tx_thread_interrupt_disable: + + /* Pickup current interrupt lockout posture. */ + + MRS x0, DAIF // Pickup current interrupt lockout posture + + /* Mask interrupts. */ + + MSR DAIFSet, 0x3 // Lockout interrupts + RET // Return to caller +/* } */ + diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_interrupt_restore.S new file mode 100644 index 00000000..a6ab9f51 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_interrupt_restore.S @@ -0,0 +1,85 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_restore Cortex-A5x-SMP/GNU */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for restoring interrupts to the state */ +/* returned by a previous _tx_thread_interrupt_disable call. */ +/* */ +/* INPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +/* UINT _tx_thread_interrupt_restore(UINT old_posture) +{ */ + .global _tx_thread_interrupt_restore + .type _tx_thread_interrupt_restore, @function +_tx_thread_interrupt_restore: + + /* Restore the old interrupt posture. */ + + MSR DAIF, x0 // Setup the old posture + RET // Return to caller + +/* } */ + diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_schedule.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_schedule.S new file mode 100644 index 00000000..242778e2 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_schedule.S @@ -0,0 +1,307 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule Cortex-A5x-SMP/GNU */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* _tx_thread_context_restore Restore thread's context */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_schedule(VOID) +{ */ + .global _tx_thread_schedule + .type _tx_thread_schedule, @function +_tx_thread_schedule: + + /* Enable interrupts. */ + + MSR DAIFClr, 0x3 // Enable interrupts + + /* Pickup the CPU ID. */ + + MRS x20, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x1, x20, #8, #8 // Isolate cluster ID +#endif + UBFX x20, x20, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x20, x20, x1, LSL #2 // Calculate CPU ID +#endif + + /* Wait for a thread to execute. */ + /* do + { */ + + LDR x1, =_tx_thread_execute_ptr // Address of thread execute ptr + +#ifdef TX_ENABLE_WFI +__tx_thread_schedule_loop: + MSR DAIFSet, 0x3 // Lockout interrupts + LDR x0, [x1, x20, LSL #3] // Pickup next thread to execute + CMP x0, #0 // Is it NULL? + BNE _tx_thread_schedule_thread // + MSR DAIFClr, 0x3 // Enable interrupts + WFI // + B __tx_thread_schedule_loop // Keep looking for a thread +_tx_thread_schedule_thread: +#else + MSR DAIFSet, 0x3 // Lockout interrupts + LDR x0, [x1, x20, LSL #3] // Pickup next thread to execute + CMP x0, #0 // Is it NULL? + BEQ _tx_thread_schedule // Keep looking for a thread +#endif + + /* } + while(_tx_thread_execute_ptr == TX_NULL); */ + + /* Get the lock for accessing the thread's ready bit. */ + + MOV w2, #280 // Build offset to the lock + ADD x2, x0, x2 // Get the address to the lock + LDAXR w3, [x2] // Pickup the lock value + CMP w3, #0 // Check if it's available + BNE _tx_thread_schedule // No, lock not available + MOV w3, #1 // Build the lock set value + STXR w4, w3, [x2] // Try to get the lock + CMP w4, #0 // Check if we got the lock + BNE _tx_thread_schedule // No, another core got it first + DMB ISH // Ensure write to lock completes + + /* Now make sure the thread's ready bit is set. */ + + LDR w3, [x0, #260] // Pickup the thread ready bit + CMP w3, #0 // Is it set? + BNE _tx_thread_ready_for_execution // Yes, schedule the thread + + /* The ready bit isn't set. Release the lock and jump back to the scheduler. */ + + MOV w3, #0 // Build clear value + STR w3, [x2] // Release the lock + DMB ISH // Ensure write to lock completes + B _tx_thread_schedule // Jump back to the scheduler + +_tx_thread_ready_for_execution: + + /* We have a thread to execute. */ + + /* Clear the ready bit and release the lock. */ + + MOV w3, #0 // Build clear value + STR w3, [x0, #260] // Store it back in the thread control block + DMB ISH + MOV w3, #0 // Build clear value for the lock + STR w3, [x2] // Release the lock + DMB ISH + + /* Setup the current thread pointer. */ + /* _tx_thread_current_ptr = _tx_thread_execute_ptr; */ + + LDR x2, =_tx_thread_current_ptr // Pickup address of current thread + STR x0, [x2, x20, LSL #3] // Setup current thread pointer + + LDR x1, [x1, x20, LSL #3] // Reload the execute pointer + CMP w0, w1 // Did it change? + BEQ _execute_pointer_did_not_change // If not, skip handling + + /* In the time between reading the execute pointer and assigning + it to the current pointer, the execute pointer was changed by + some external code. If the current pointer was still null when + the external code checked if a core preempt was necessary, then + it wouldn't have done it and a preemption will be missed. To + handle this, undo some things and jump back to the scheduler so + it can schedule the new thread. */ + + MOV w1, #0 // Build clear value + STR x1, [x2, x20, LSL #3] // Clear current thread pointer + + MOV w1, #1 // Build set value + STR w1, [x0, #260] // Re-set the ready bit + DMB ISH // + + B _tx_thread_schedule // Jump back to the scheduler to schedule the new thread + +_execute_pointer_did_not_change: + /* Increment the run count for this thread. */ + /* _tx_thread_current_ptr -> tx_thread_run_count++; */ + + LDR w2, [x0, #4] // Pickup run counter + LDR w3, [x0, #36] // Pickup time-slice for this thread + ADD w2, w2, #1 // Increment thread run-counter + STR w2, [x0, #4] // Store the new run counter + + /* Setup time-slice, if present. */ + /* _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; */ + + LDR x2, =_tx_timer_time_slice // Pickup address of time slice + // variable + LDR x4, [x0, #8] // Switch stack pointers + MOV sp, x4 // + STR w3, [x2, x20, LSL #2] // Setup time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread entry function to indicate the thread is executing. */ + + MOV x19, x0 // Save x0 + BL _tx_execution_thread_enter // Call the thread execution enter function + MOV x0, x19 // Restore x0 +#endif + + /* Switch to the thread's stack. */ + /* sp = _tx_thread_execute_ptr -> tx_thread_stack_ptr; */ + + /* Determine if an interrupt frame or a synchronous task suspension frame + is present. */ + + LDP x4, x5, [sp], #16 // Pickup saved SPSR/DAIF and ELR_EL1 + CMP x5, #0 // Check for synchronous context switch (ELR_EL1 = NULL) + BEQ _tx_solicited_return +#ifdef EL1 + MSR SPSR_EL1, x4 // Setup SPSR for return + MSR ELR_EL1, x5 // Setup point of interrupt +#else +#ifdef EL2 + MSR SPSR_EL2, x4 // Setup SPSR for return + MSR ELR_EL2, x5 // Setup point of interrupt +#else + MSR SPSR_EL3, x4 // Setup SPSR for return + MSR ELR_EL3, x5 // Setup point of interrupt +#endif +#endif +#ifdef ENABLE_ARM_FP + LDR w1, [x0, #268] // Pickup FP enable flag + CMP w1, #0 // Is FP enabled? + BEQ _skip_interrupt_fp_restore // No, skip FP restore + LDP x0, x1, [sp], #16 // Pickup FPSR, FPCR + MSR FPSR, x0 // Recover FPSR + MSR FPCR, x1 // Recover FPCR + LDP q30, q31, [sp], #32 // Recover q30, q31 + LDP q28, q29, [sp], #32 // Recover q28, q29 + LDP q26, q27, [sp], #32 // Recover q26, q27 + LDP q24, q25, [sp], #32 // Recover q24, q25 + LDP q22, q23, [sp], #32 // Recover q22, q23 + LDP q20, q21, [sp], #32 // Recover q20, q21 + LDP q18, q19, [sp], #32 // Recover q18, q19 + LDP q16, q17, [sp], #32 // Recover q16, q17 + LDP q14, q15, [sp], #32 // Recover q14, q15 + LDP q12, q13, [sp], #32 // Recover q12, q13 + LDP q10, q11, [sp], #32 // Recover q10, q11 + LDP q8, q9, [sp], #32 // Recover q8, q9 + LDP q6, q7, [sp], #32 // Recover q6, q7 + LDP q4, q5, [sp], #32 // Recover q4, q5 + LDP q2, q3, [sp], #32 // Recover q2, q3 + LDP q0, q1, [sp], #32 // Recover q0, q1 +_skip_interrupt_fp_restore: +#endif + LDP x28, x29, [sp], #16 // Recover x28 + LDP x26, x27, [sp], #16 // Recover x26, x27 + LDP x24, x25, [sp], #16 // Recover x24, x25 + LDP x22, x23, [sp], #16 // Recover x22, x23 + LDP x20, x21, [sp], #16 // Recover x20, x21 + LDP x18, x19, [sp], #16 // Recover x18, x19 + LDP x16, x17, [sp], #16 // Recover x16, x17 + LDP x14, x15, [sp], #16 // Recover x14, x15 + LDP x12, x13, [sp], #16 // Recover x12, x13 + LDP x10, x11, [sp], #16 // Recover x10, x11 + LDP x8, x9, [sp], #16 // Recover x8, x9 + LDP x6, x7, [sp], #16 // Recover x6, x7 + LDP x4, x5, [sp], #16 // Recover x4, x5 + LDP x2, x3, [sp], #16 // Recover x2, x3 + LDP x0, x1, [sp], #16 // Recover x0, x1 + LDP x29, x30, [sp], #16 // Recover x29, x30 + ERET // Return to point of interrupt + +_tx_solicited_return: + +#ifdef ENABLE_ARM_FP + LDR w1, [x0, #268] // Pickup FP enable flag + CMP w1, #0 // Is FP enabled? + BEQ _skip_solicited_fp_restore // No, skip FP restore + LDP x0, x1, [sp], #16 // Pickup FPSR, FPCR + MSR FPSR, x0 // Recover FPSR + MSR FPCR, x1 // Recover FPCR + LDP q14, q15, [sp], #32 // Recover q14, q15 + LDP q12, q13, [sp], #32 // Recover q12, q13 + LDP q10, q11, [sp], #32 // Recover q10, q11 + LDP q8, q9, [sp], #32 // Recover q8, q9 +_skip_solicited_fp_restore: +#endif + LDP x27, x28, [sp], #16 // Recover x27, x28 + LDP x25, x26, [sp], #16 // Recover x25, x26 + LDP x23, x24, [sp], #16 // Recover x23, x24 + LDP x21, x22, [sp], #16 // Recover x21, x22 + LDP x19, x20, [sp], #16 // Recover x19, x20 + LDP x29, x30, [sp], #16 // Recover x29, x30 + MSR DAIF, x4 // Recover DAIF + RET // Return to caller +/* } */ + + diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_core_get.S new file mode 100644 index 00000000..679a59f0 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_core_get.S @@ -0,0 +1,89 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_core_get Cortex-A5x-SMP/GNU */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets the currently running core number and returns it.*/ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* Core ID */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Source */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_core_get + .type _tx_thread_smp_core_get, @function +_tx_thread_smp_core_get: + MRS x0, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x1, x0, #8, #8 // Isolate cluster ID +#endif + UBFX x0, x0, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x0, x0, x1, LSL #2 // Calculate CPU ID +#endif + RET + + diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_core_preempt.S new file mode 100644 index 00000000..be75c89e --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_core_preempt.S @@ -0,0 +1,89 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + +#define ICC_SGI1R_EL1 S3_0_C12_C11_5 + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_core_preempt Cortex-A5x-SMP/GNU */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function preempts the specified core in situations where the */ +/* thread corresponding to this core is no longer ready or when the */ +/* core must be used for a higher-priority thread. If the specified is */ +/* the current core, this processing is skipped since the will give up */ +/* control subsequently on its own. */ +/* */ +/* INPUT */ +/* */ +/* core The core to preempt */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Source */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_core_preempt + .type _tx_thread_smp_core_preempt, @function +_tx_thread_smp_core_preempt: + DSB ISH + MOV x2, #0x1 // + LSL x2, x2, x0 // Shift by the core ID + MSR ICC_SGI1R_EL1, x2 // Issue inter-core interrupt + RET + diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_current_state_get.S new file mode 100644 index 00000000..36284739 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_current_state_get.S @@ -0,0 +1,95 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_current_state_get Cortex-A5x-SMP/GNU */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is gets the current state of the calling core. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_current_state_get + .type _tx_thread_smp_current_state_get, @function +_tx_thread_smp_current_state_get: + + MRS x1, DAIF // Pickup current interrupt posture + MSR DAIFSet, 0x3 // Lockout interrupts + MRS x2, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x3, x2, #8, #8 // Isolate cluster ID +#endif + UBFX x2, x2, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x2, x2, x3, LSL #2 // Calculate CPU ID +#endif + LDR x3, =_tx_thread_system_state // Pickup the base of the current system state array + LDR w0, [x3, x2, LSL #2] // Pickup the current system state for this core + MSR DAIF, x1 // Restore interrupt posture + RET + + diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_current_thread_get.S new file mode 100644 index 00000000..8c33f3f7 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_current_thread_get.S @@ -0,0 +1,94 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_current_thread_get Cortex-A5x-SMP/GNU */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is gets the current thread of the calling core. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_current_thread_get + .type _tx_thread_smp_current_thread_get, @function +_tx_thread_smp_current_thread_get: + + MRS x1, DAIF // Pickup current interrupt posture + MSR DAIFSet, 0x3 // Lockout interrupts + MRS x2, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x3, x2, #8, #8 // Isolate cluster ID +#endif + UBFX x2, x2, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x2, x2, x3, LSL #2 // Calculate CPU ID +#endif + LDR x3, =_tx_thread_current_ptr // Pickup the base of the current thread pointer array + LDR x0, [x3, x2, LSL #3] // Pickup the current thread pointer for this core + MSR DAIF, x1 // Restore interrupt posture + RET + diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_initialize_wait.S new file mode 100644 index 00000000..7c59b770 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_initialize_wait.S @@ -0,0 +1,143 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_initialize_wait Cortex-A5x-SMP/GNU */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is the place where additional cores wait until */ +/* initialization is complete before they enter the thread scheduling */ +/* loop. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* Hardware */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_initialize_wait + .type _tx_thread_smp_initialize_wait, @function +_tx_thread_smp_initialize_wait: + + /* Lockout interrupts. */ + + MSR DAIFSet, 0x3 // Lockout interrupts + + /* Pickup the Core ID. */ + + MRS x2, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x3, x2, #8, #8 // Isolate cluster ID +#endif + UBFX x2, x2, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x2, x2, x3, LSL #2 // Calculate CPU ID +#endif + + /* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release + flag. */ + + LDR w1, =0xF0F0F0F0 // Build TX_INITIALIZE_IN_PROGRESS flag + LDR x3, =_tx_thread_system_state // Pickup the base of the current system state array +wait_for_initialize: + LDR w0, [x3, x2, LSL #2] // Pickup the current system state for this core + CMP w0, w1 // Make sure the TX_INITIALIZE_IN_PROGRESS flag is set + BNE wait_for_initialize // Not equal, just spin here + + /* Save the system stack pointer for this core. */ + + LDR x0, =_tx_thread_system_stack_ptr // Pickup address of system stack ptr + MOV x1, sp // Pickup SP + SUB x1, x1, #15 // + BIC x1, x1, #0xF // Get 16-bit alignment + STR x1, [x0, x2, LSL #3] // Store system stack pointer + + + /* Pickup the release cores flag. */ + + LDR x4, =_tx_thread_smp_release_cores_flag // Build address of release cores flag +wait_for_release: + LDR w0, [x4, #0] // Pickup the flag + CMP w0, #0 // Is it set? + BEQ wait_for_release // Wait for the flag to be set + + /* Core 0 has released this core. */ + + /* Clear this core's system state variable. */ + + MOV x0, #0 // Build clear value + STR w0, [x3, x2, LSL #2] // Set the current system state for this core to zero + + /* Now wait for core 0 to finish it's initialization. */ + +core_0_wait_loop: + LDR w0, [x3, #0] // Pickup the current system state for core 0 + CMP w0, #0 // Is it 0? + BNE core_0_wait_loop // No, keep waiting for core 0 to finish its initialization + + /* Initialization is complete, enter the scheduling loop! */ + + B _tx_thread_schedule // Enter the scheduling loop for this core + + RET + diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_low_level_initialize.S new file mode 100644 index 00000000..6b8b582b --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_low_level_initialize.S @@ -0,0 +1,80 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_low_level_initialize Cortex-A5x-SMP/GNU */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function performs low-level initialization of the booting */ +/* core. */ +/* */ +/* INPUT */ +/* */ +/* number_of_cores Number of cores */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_high_level ThreadX high-level init */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_low_level_initialize + .type _tx_thread_smp_low_level_initialize, @function +_tx_thread_smp_low_level_initialize: + + RET diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_protect.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_protect.S new file mode 100644 index 00000000..48f37a7e --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_protect.S @@ -0,0 +1,364 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + +/* Include macros for modifying the wait list. */ +#include "tx_thread_smp_protection_wait_list_macros.h" + + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_protect Cortex-A5x-SMP/GNU */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets protection for running inside the ThreadX */ +/* source. This is acomplished by a combination of a test-and-set */ +/* flag and periodically disabling interrupts. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* Previous Status Register */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Source */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_protect + .type _tx_thread_smp_protect, @function +_tx_thread_smp_protect: + + /* Disable interrupts so we don't get preempted. */ + + MRS x0, DAIF // Pickup current interrupt posture + MSR DAIFSet, 0x3 // Lockout interrupts + + /* Pickup the CPU ID. */ + + MRS x1, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x7, x1, #8, #8 // Isolate cluster ID +#endif + UBFX x1, x1, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x1, x1, x7, LSL #2 // Calculate CPU ID +#endif + + /* Do we already have protection? */ + /* if (this_core == _tx_thread_smp_protection.tx_thread_smp_protect_core) + { */ + + LDR x2, =_tx_thread_smp_protection // Build address to protection structure + LDR w3, [x2, #4] // Pickup the owning core + CMP w1, w3 // Is it not this core? + BNE _protection_not_owned // No, the protection is not already owned + + /* We already have protection. */ + + /* Increment the protection count. */ + /* _tx_thread_smp_protection.tx_thread_smp_protect_count++; */ + + LDR w3, [x2, #8] // Pickup ownership count + ADD w3, w3, #1 // Increment ownership count + STR w3, [x2, #8] // Store ownership count + DMB ISH + + B _return + +_protection_not_owned: + + /* Is the lock available? */ + /* if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0) + { */ + + LDAXR w3, [x2, #0] // Pickup the protection flag + CMP w3, #0 + BNE _start_waiting // No, protection not available + + /* Is the list empty? */ + /* if (_tx_thread_smp_protect_wait_list_head == _tx_thread_smp_protect_wait_list_tail) + { */ + + LDR x3, =_tx_thread_smp_protect_wait_list_head + LDR w3, [x3] + LDR x4, =_tx_thread_smp_protect_wait_list_tail + LDR w4, [x4] + CMP w3, w4 + BNE _list_not_empty + + /* Try to get the lock. */ + /* if (write_exclusive(&_tx_thread_smp_protection.tx_thread_smp_protect_in_force, 1) == SUCCESS) + { */ + + MOV w3, #1 // Build lock value + STXR w4, w3, [x2, #0] // Attempt to get the protection + CMP w4, #0 + BNE _start_waiting // Did it fail? + + /* We got the lock! */ + /* _tx_thread_smp_protect_lock_got(); */ + + DMB ISH // Ensure write to protection finishes + _tx_thread_smp_protect_lock_got // Call the lock got function + + B _return + +_list_not_empty: + + /* Are we at the front of the list? */ + /* if (this_core == _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head]) + { */ + + LDR x3, =_tx_thread_smp_protect_wait_list_head // Get the address of the head + LDR w3, [x3] // Get the value of the head + LDR x4, =_tx_thread_smp_protect_wait_list // Get the address of the list + LDR w4, [x4, x3, LSL #2] // Get the value at the head index + + CMP w1, w4 + BNE _start_waiting + + /* Is the lock still available? */ + /* if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0) + { */ + + LDR w3, [x2, #0] // Pickup the protection flag + CMP w3, #0 + BNE _start_waiting // No, protection not available + + /* Get the lock. */ + /* _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1; */ + + MOV w3, #1 // Build lock value + STR w3, [x2, #0] // Store lock value + DMB ISH // + + /* Got the lock. */ + /* _tx_thread_smp_protect_lock_got(); */ + + _tx_thread_smp_protect_lock_got + + /* Remove this core from the wait list. */ + /* _tx_thread_smp_protect_remove_from_front_of_list(); */ + + _tx_thread_smp_protect_remove_from_front_of_list + + B _return + +_start_waiting: + + /* For one reason or another, we didn't get the lock. */ + + /* Increment wait count. */ + /* _tx_thread_smp_protect_wait_counts[this_core]++; */ + + LDR x3, =_tx_thread_smp_protect_wait_counts // Load wait list counts + LDR w4, [x3, x1, LSL #2] // Load waiting value for this core + ADD w4, w4, #1 // Increment wait value + STR w4, [x3, x1, LSL #2] // Store new wait value + + /* Have we not added ourselves to the list yet? */ + /* if (_tx_thread_smp_protect_wait_counts[this_core] == 1) + { */ + + CMP w4, #1 + BNE _already_in_list0 // Is this core already waiting? + + /* Add ourselves to the list. */ + /* _tx_thread_smp_protect_wait_list_add(this_core); */ + + _tx_thread_smp_protect_wait_list_add // Call macro to add ourselves to the list + + /* } */ + +_already_in_list0: + + /* Restore interrupts. */ + + MSR DAIF, x0 // Restore interrupts + ISB // +#ifdef TX_ENABLE_WFE + WFE // Go into standby +#endif + + /* We do this until we have the lock. */ + /* while (1) + { */ + +_try_to_get_lock: + + /* Disable interrupts so we don't get preempted. */ + + MRS x0, DAIF // Pickup current interrupt posture + MSR DAIFSet, 0x3 // Lockout interrupts + + /* Pickup the CPU ID. */ + + MRS x1, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x7, x1, #8, #8 // Isolate cluster ID +#endif + UBFX x1, x1, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x1, x1, x7, LSL #2 // Calculate CPU ID +#endif + + /* Do we already have protection? */ + /* if (this_core == _tx_thread_smp_protection.tx_thread_smp_protect_core) + { */ + + LDR w3, [x2, #4] // Pickup the owning core + CMP w3, w1 // Is it this core? + BEQ _got_lock_after_waiting // Yes, the protection is already owned. This means + // an ISR preempted us and got protection + + /* } */ + + /* Are we at the front of the list? */ + /* if (this_core == _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head]) + { */ + + LDR x3, =_tx_thread_smp_protect_wait_list_head // Get the address of the head + LDR w3, [x3] // Get the value of the head + LDR x4, =_tx_thread_smp_protect_wait_list // Get the address of the list + LDR w4, [x4, x3, LSL #2] // Get the value at the head index + + CMP w1, w4 + BNE _did_not_get_lock + + /* Is the lock still available? */ + /* if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0) + { */ + + LDR w3, [x2, #0] // Pickup the protection flag + CMP w3, #0 + BNE _did_not_get_lock // No, protection not available + + /* Get the lock. */ + /* _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1; */ + + MOV w3, #1 // Build lock value + STR w3, [x2, #0] // Store lock value + DMB ISH // + + /* Got the lock. */ + /* _tx_thread_smp_protect_lock_got(); */ + + _tx_thread_smp_protect_lock_got + + /* Remove this core from the wait list. */ + /* _tx_thread_smp_protect_remove_from_front_of_list(); */ + + _tx_thread_smp_protect_remove_from_front_of_list + + B _got_lock_after_waiting + +_did_not_get_lock: + + /* For one reason or another, we didn't get the lock. */ + + /* Were we removed from the list? This can happen if we're a thread + and we got preempted. */ + /* if (_tx_thread_smp_protect_wait_counts[this_core] == 0) + { */ + + LDR x3, =_tx_thread_smp_protect_wait_counts // Load wait list counts + LDR w4, [x3, x1, LSL #2] // Load waiting value for this core + CMP w4, #0 + BNE _already_in_list1 // Is this core already in the list? + + /* Add ourselves to the list. */ + /* _tx_thread_smp_protect_wait_list_add(this_core); */ + + _tx_thread_smp_protect_wait_list_add // Call macro to add ourselves to the list + + /* Our waiting count was also reset when we were preempted. Increment it again. */ + /* _tx_thread_smp_protect_wait_counts[this_core]++; */ + + LDR x3, =_tx_thread_smp_protect_wait_counts // Load wait list counts + LDR w4, [x3, x1, LSL #2] // Load waiting value for this core + ADD w4, w4, #1 // Increment wait value + STR w4, [x3, x1, LSL #2] // Store new wait value value + + /* } */ + +_already_in_list1: + + /* Restore interrupts and try again. */ + + MSR DAIF, x0 // Restore interrupts + ISB // +#ifdef TX_ENABLE_WFE + WFE // Go into standby +#endif + B _try_to_get_lock // On waking, restart the protection attempt + +_got_lock_after_waiting: + + /* We're no longer waiting. */ + /* _tx_thread_smp_protect_wait_counts[this_core]--; */ + + LDR x3, =_tx_thread_smp_protect_wait_counts // Load waiting list + LDR w4, [x3, x1, LSL #2] // Load current wait value + SUB w4, w4, #1 // Decrement wait value + STR w4, [x3, x1, LSL #2] // Store new wait value value + + /* Restore registers and return. */ + +_return: + + RET + diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h new file mode 100644 index 00000000..5c33d940 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h @@ -0,0 +1,296 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .macro _tx_thread_smp_protect_lock_got + + /* Set the currently owned core. */ + /* _tx_thread_smp_protection.tx_thread_smp_protect_core = this_core; */ + + STR w1, [x2, #4] // Store this core + + /* Increment the protection count. */ + /* _tx_thread_smp_protection.tx_thread_smp_protect_count++; */ + + LDR w3, [x2, #8] // Pickup ownership count + ADD w3, w3, #1 // Increment ownership count + STR w3, [x2, #8] // Store ownership count + DMB ISH + + .endm + + .macro _tx_thread_smp_protect_remove_from_front_of_list + + /* Remove ourselves from the list. */ + /* _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head++] = 0xFFFFFFFF; */ + + MOV w3, #0xFFFFFFFF // Build the invalid core value + LDR x4, =_tx_thread_smp_protect_wait_list_head // Get the address of the head + LDR w5, [x4] // Get the value of the head + LDR x6, =_tx_thread_smp_protect_wait_list // Get the address of the list + STR w3, [x6, x5, LSL #2] // Store the invalid core value + ADD w5, w5, #1 // Increment the head + + /* Did we wrap? */ + /* if (_tx_thread_smp_protect_wait_list_head == TX_THREAD_SMP_MAX_CORES + 1) + { */ + + LDR x3, =_tx_thread_smp_protect_wait_list_size // Load address of core list size + LDR w3, [x3] // Load the max cores value + CMP w5, w3 // Compare the head to it + BNE _store_new_head\@ // Are we at the max? + + /* _tx_thread_smp_protect_wait_list_head = 0; */ + + EOR w5, w5, w5 // We're at the max. Set it to zero + + /* } */ + +_store_new_head\@: + + STR w5, [x4] // Store the new head + + /* We have the lock! */ + /* return; */ + + .endm + + + .macro _tx_thread_smp_protect_wait_list_lock_get +/* VOID _tx_thread_smp_protect_wait_list_lock_get() +{ */ + /* We do this until we have the lock. */ + /* while (1) + { */ + +_tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@: + + /* Is the list lock available? */ + /* _tx_thread_smp_protect_wait_list_lock_protect_in_force = load_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force); */ + + LDR x1, =_tx_thread_smp_protect_wait_list_lock_protect_in_force + LDAXR w2, [x1] // Pickup the protection flag + + /* if (protect_in_force == 0) + { */ + + CMP w2, #0 + BNE _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@ // No, protection not available + + /* Try to get the list. */ + /* int status = store_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force, 1); */ + + MOV w2, #1 // Build lock value + STXR w3, w2, [x1] // Attempt to get the protection + + /* if (status == SUCCESS) */ + + CMP w3, #0 + BNE _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@ // Did it fail? If so, try again. + + /* We have the lock! */ + /* return; */ + + .endm + + + .macro _tx_thread_smp_protect_wait_list_add +/* VOID _tx_thread_smp_protect_wait_list_add(UINT new_core) +{ */ + + /* We're about to modify the list, so get the list lock. */ + /* _tx_thread_smp_protect_wait_list_lock_get(); */ + + STP x1, x2, [sp, #-16]! // Save registers we'll be using + + _tx_thread_smp_protect_wait_list_lock_get + + LDP x1, x2, [sp], #16 + + /* Add this core. */ + /* _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_tail++] = new_core; */ + + LDR x3, =_tx_thread_smp_protect_wait_list_tail // Get the address of the tail + LDR w4, [x3] // Get the value of tail + LDR x5, =_tx_thread_smp_protect_wait_list // Get the address of the list + STR w1, [x5, x4, LSL #2] // Store the new core value + ADD w4, w4, #1 // Increment the tail + + /* Did we wrap? */ + /* if (_tx_thread_smp_protect_wait_list_tail == _tx_thread_smp_protect_wait_list_size) + { */ + + LDR x5, =_tx_thread_smp_protect_wait_list_size // Load max cores address + LDR w5, [x5] // Load max cores value + CMP w4, w5 // Compare max cores to tail + BNE _tx_thread_smp_protect_wait_list_add__no_wrap\@ // Did we wrap? + + /* _tx_thread_smp_protect_wait_list_tail = 0; */ + + MOV w4, #0 + + /* } */ + +_tx_thread_smp_protect_wait_list_add__no_wrap\@: + + STR w4, [x3] // Store the new tail value. + + /* Release the list lock. */ + /* _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; */ + + MOV w3, #0 // Build lock value + LDR x4, =_tx_thread_smp_protect_wait_list_lock_protect_in_force + STR w3, [x4] // Store the new value + + .endm + + + .macro _tx_thread_smp_protect_wait_list_remove +/* VOID _tx_thread_smp_protect_wait_list_remove(UINT core) +{ */ + + /* Get the core index. */ + /* UINT core_index; + for (core_index = 0;; core_index++) */ + + EOR w4, w4, w4 // Clear for 'core_index' + LDR x2, =_tx_thread_smp_protect_wait_list // Get the address of the list + + /* { */ + +_tx_thread_smp_protect_wait_list_remove__check_cur_core\@: + + /* Is this the core? */ + /* if (_tx_thread_smp_protect_wait_list[core_index] == core) + { + break; */ + + LDR w3, [x2, x4, LSL #2] // Get the value at the current index + CMP w3, w8 // Did we find the core? + BEQ _tx_thread_smp_protect_wait_list_remove__found_core\@ + + /* } */ + + ADD w4, w4, #1 // Increment cur index + B _tx_thread_smp_protect_wait_list_remove__check_cur_core\@ // Restart the loop + + /* } */ + +_tx_thread_smp_protect_wait_list_remove__found_core\@: + + /* We're about to modify the list. Get the lock. We need the lock because another + core could be simultaneously adding (a core is simultaneously trying to get + the inter-core lock) or removing (a core is simultaneously being preempted, + like what is currently happening). */ + /* _tx_thread_smp_protect_wait_list_lock_get(); */ + + MOV x6, x1 + _tx_thread_smp_protect_wait_list_lock_get + MOV x1, x6 + + /* We remove by shifting. */ + /* while (core_index != _tx_thread_smp_protect_wait_list_tail) + { */ + +_tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@: + + LDR x2, =_tx_thread_smp_protect_wait_list_tail // Load tail address + LDR w2, [x2] // Load tail value + CMP w4, w2 // Compare cur index and tail + BEQ _tx_thread_smp_protect_wait_list_remove__removed\@ + + /* UINT next_index = core_index + 1; */ + + MOV w2, w4 // Move current index to next index register + ADD w2, w2, #1 // Add 1 + + /* if (next_index == _tx_thread_smp_protect_wait_list_size) + { */ + + LDR x3, =_tx_thread_smp_protect_wait_list_size + LDR w3, [x3] + CMP w2, w3 + BNE _tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@ + + /* next_index = 0; */ + + MOV w2, #0 + + /* } */ + +_tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@: + + /* list_cores[core_index] = list_cores[next_index]; */ + + LDR x5, =_tx_thread_smp_protect_wait_list // Get the address of the list + LDR w3, [x5, x2, LSL #2] // Get the value at the next index + STR w3, [x5, x4, LSL #2] // Store the value at the current index + + /* core_index = next_index; */ + + MOV w4, w2 + + B _tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@ + + /* } */ + +_tx_thread_smp_protect_wait_list_remove__removed\@: + + /* Now update the tail. */ + /* if (_tx_thread_smp_protect_wait_list_tail == 0) + { */ + + LDR x5, =_tx_thread_smp_protect_wait_list_tail // Load tail address + LDR w4, [x5] // Load tail value + CMP w4, #0 + BNE _tx_thread_smp_protect_wait_list_remove__tail_not_zero\@ + + /* _tx_thread_smp_protect_wait_list_tail = _tx_thread_smp_protect_wait_list_size; */ + + LDR x2, =_tx_thread_smp_protect_wait_list_size + LDR w4, [x2] + + /* } */ + +_tx_thread_smp_protect_wait_list_remove__tail_not_zero\@: + + /* _tx_thread_smp_protect_wait_list_tail--; */ + + SUB w4, w4, #1 + STR w4, [x5] // Store new tail value + + /* Release the list lock. */ + /* _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; */ + + MOV w2, #0 // Build lock value + LDR x4, =_tx_thread_smp_protect_wait_list_lock_protect_in_force // Load lock address + STR w2, [x4] // Store the new value + + /* We're no longer waiting. Note that this should be zero since, again, + this function is only called when a thread preemption is occurring. */ + /* _tx_thread_smp_protect_wait_counts[core]--; */ + LDR x4, =_tx_thread_smp_protect_wait_counts // Load wait list counts + LDR w2, [x4, x8, LSL #2] // Load waiting value + SUB w2, w2, #1 // Subtract 1 + STR w2, [x4, x8, LSL #2] // Store new waiting value + + .endm + diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_time_get.S new file mode 100644 index 00000000..df179adf --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_time_get.S @@ -0,0 +1,83 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_time_get Cortex-A5x-SMP/GNU */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets the global time value that is used for debug */ +/* information and event tracing. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* 32-bit time stamp */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Source */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_time_get + .type _tx_thread_smp_time_get, @function +_tx_thread_smp_time_get: + MOV x0, #0 // FIXME: Get timer + RET + + diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_unprotect.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_unprotect.S new file mode 100644 index 00000000..7eb5f68f --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_smp_unprotect.S @@ -0,0 +1,130 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread - Low Level SMP Support */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* +#define TX_SOURCE_CODE +#define TX_THREAD_SMP_SOURCE_CODE +*/ + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_smp_unprotect Cortex-A5x-SMP/GNU */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function releases previously obtained protection. The supplied */ +/* previous SR is restored. If the value of _tx_thread_system_state */ +/* and _tx_thread_preempt_disable are both zero, then multithreading */ +/* is enabled as well. */ +/* */ +/* INPUT */ +/* */ +/* Previous Status Register */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Source */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + .global _tx_thread_smp_unprotect + .type _tx_thread_smp_unprotect, @function +_tx_thread_smp_unprotect: + MSR DAIFSet, 0x3 // Lockout interrupts + + MRS x1, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x2, x1, #8, #8 // Isolate cluster ID +#endif + UBFX x1, x1, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x1, x1, x2, LSL #2 // Calculate CPU ID +#endif + + LDR x2,=_tx_thread_smp_protection // Build address of protection structure + LDR w3, [x2, #4] // Pickup the owning core + CMP w1, w3 // Is it this core? + BNE _still_protected // If this is not the owning core, protection is in force elsewhere + + LDR w3, [x2, #8] // Pickup the protection count + CMP w3, #0 // Check to see if the protection is still active + BEQ _still_protected // If the protection count is zero, protection has already been cleared + + SUB w3, w3, #1 // Decrement the protection count + STR w3, [x2, #8] // Store the new count back + CMP w3, #0 // Check to see if the protection is still active + BNE _still_protected // If the protection count is non-zero, protection is still in force + LDR x2,=_tx_thread_preempt_disable // Build address of preempt disable flag + LDR w3, [x2] // Pickup preempt disable flag + CMP w3, #0 // Is the preempt disable flag set? + BNE _still_protected // Yes, skip the protection release + + LDR x2,=_tx_thread_smp_protect_wait_counts // Build build address of wait counts + LDR w3, [x2, x1, LSL #2] // Pickup wait list value + CMP w3, #0 // Are any entities on this core waiting? + BNE _still_protected // Yes, skip the protection release + + LDR x2,=_tx_thread_smp_protection // Build address of protection structure + MOV w3, #0xFFFFFFFF // Build invalid value + STR w3, [x2, #4] // Mark the protected core as invalid + DMB ISH // Ensure that accesses to shared resource have completed + MOV w3, #0 // Build release protection value + STR w3, [x2, #0] // Release the protection + DSB ISH // To ensure update of the protection occurs before other CPUs awake + +_still_protected: +#ifdef TX_ENABLE_WFE + SEV // Send event to other CPUs, wakes anyone waiting on the protection (using WFE) +#endif + MSR DAIF, x0 // Restore interrupt posture + RET + diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_stack_build.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_stack_build.S new file mode 100644 index 00000000..03183de1 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_stack_build.S @@ -0,0 +1,172 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +*/ + + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build Cortex-A5x-SMP/GNU */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +{ */ + .global _tx_thread_stack_build + .type _tx_thread_stack_build, @function +_tx_thread_stack_build: + + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-A5x should look like the following after it is built: + + Stack Top: SSPR Initial SSPR + ELR Point of interrupt + x28 Initial value for x28 + not used Not used + x26 Initial value for x26 + x27 Initial value for x27 + x24 Initial value for x24 + x25 Initial value for x25 + x22 Initial value for x22 + x23 Initial value for x23 + x20 Initial value for x20 + x21 Initial value for x21 + x18 Initial value for x18 + x19 Initial value for x19 + x16 Initial value for x16 + x17 Initial value for x17 + x14 Initial value for x14 + x15 Initial value for x15 + x12 Initial value for x12 + x13 Initial value for x13 + x10 Initial value for x10 + x11 Initial value for x11 + x8 Initial value for x8 + x9 Initial value for x9 + x6 Initial value for x6 + x7 Initial value for x7 + x4 Initial value for x4 + x5 Initial value for x5 + x2 Initial value for x2 + x3 Initial value for x3 + x0 Initial value for x0 + x1 Initial value for x1 + x29 Initial value for x29 (frame pointer) + x30 Initial value for x30 (link register) + 0 For stack backtracing + + Stack Bottom: (higher memory address) */ + + LDR x4, [x0, #24] // Pickup end of stack area + BIC x4, x4, #0xF // Ensure 16-byte alignment + + /* Actually build the stack frame. */ + + MOV x2, #0 // Build clear value + MOV x3, #0 // + + STP x2, x3, [x4, #-16]! // Set backtrace to 0 + STP x2, x3, [x4, #-16]! // Set initial x29, x30 + STP x2, x3, [x4, #-16]! // Set initial x0, x1 + STP x2, x3, [x4, #-16]! // Set initial x2, x3 + STP x2, x3, [x4, #-16]! // Set initial x4, x5 + STP x2, x3, [x4, #-16]! // Set initial x6, x7 + STP x2, x3, [x4, #-16]! // Set initial x8, x9 + STP x2, x3, [x4, #-16]! // Set initial x10, x11 + STP x2, x3, [x4, #-16]! // Set initial x12, x13 + STP x2, x3, [x4, #-16]! // Set initial x14, x15 + STP x2, x3, [x4, #-16]! // Set initial x16, x17 + STP x2, x3, [x4, #-16]! // Set initial x18, x19 + STP x2, x3, [x4, #-16]! // Set initial x20, x21 + STP x2, x3, [x4, #-16]! // Set initial x22, x23 + STP x2, x3, [x4, #-16]! // Set initial x24, x25 + STP x2, x3, [x4, #-16]! // Set initial x26, x27 + STP x2, x3, [x4, #-16]! // Set initial x28 +#ifdef EL1 + MOV x2, #0x4 // Build initial SPSR (EL1) +#else +#ifdef EL2 + MOV x2, #0x8 // Build initial SPSR (EL2) +#else + MOV x2, #0xC // Build initial SPSR (EL3) +#endif +#endif + MOV x3, x1 // Build initial ELR + STP x2, x3, [x4, #-16]! // Set initial SPSR & ELR + + /* Setup stack pointer. */ + /* thread_ptr -> tx_thread_stack_ptr = x2; */ + + STR x4, [x0, #8] // Save stack pointer in thread's + MOV x3, #1 // Build ready flag + STR w3, [x0, #260] // Set ready flag + RET // Return to caller + +/* } */ + + diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_system_return.S new file mode 100644 index 00000000..ff9ce4e7 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_system_return.S @@ -0,0 +1,191 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return Cortex-A5x-SMP/ARM */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the ThreadX system. Only a */ +/* minimal context is saved since the compiler assumes temp registers */ +/* are going to get slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_thread_system_return(VOID) +{ */ + .global _tx_thread_system_return + .type _tx_thread_system_return, @function +_tx_thread_system_return: +; +; /* Save minimal context on the stack. */ +; + MRS x0, DAIF // Pickup DAIF + MSR DAIFSet, 0x3 // Lockout interrupts + STP x29, x30, [sp, #-16]! // Save x29 (frame pointer), x30 (link register) + STP x19, x20, [sp, #-16]! // Save x19, x20 + STP x21, x22, [sp, #-16]! // Save x21, x22 + STP x23, x24, [sp, #-16]! // Save x23, x24 + STP x25, x26, [sp, #-16]! // Save x25, x26 + STP x27, x28, [sp, #-16]! // Save x27, x28 + MRS x8, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x3, x8, #8, #8 // Isolate cluster ID +#endif + UBFX x8, x8, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x8, x8, x3, LSL #2 // Calculate CPU ID +#endif + LDR x5, =_tx_thread_current_ptr // Pickup address of current ptr + LDR x6, [x5, x8, LSL #3] // Pickup current thread pointer + +#ifdef ENABLE_ARM_FP + LDR w7, [x6, #268] // Pickup FP enable flag + CMP w7, #0 // Is FP enabled? + BEQ _skip_fp_save // No, skip FP save + STP q8, q9, [sp, #-32]! // Save q8, q9 + STP q10, q11, [sp, #-32]! // Save q10, q11 + STP q12, q13, [sp, #-32]! // Save q12, q13 + STP q14, q15, [sp, #-32]! // Save q14, q15 + MRS x2, FPSR // Pickup FPSR + MRS x3, FPCR // Pickup FPCR + STP x2, x3, [sp, #-16]! // Save FPSR, FPCR +_skip_fp_save: +#endif + + MOV x1, #0 // Clear x1 + STP x0, x1, [sp, #-16]! // Save DAIF and clear value for ELR_EK1 + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + + /* Call the thread exit function to indicate the thread is no longer executing. */ + + MOV x19, x5 // Save x5 + MOV x20, x6 // Save x6 + MOV x21, x8 // Save x2 + BL _tx_execution_thread_exit // Call the thread exit function + MOV x8, x21 // Restore x2 + MOV x5, x19 // Restore x5 + MOV x6, x20 // Restore x6 +#endif + + LDR x2, =_tx_timer_time_slice // Pickup address of time slice + LDR w1, [x2, x8, LSL #2] // Pickup current time slice + + /* Save current stack and switch to system stack. */ + /* _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; */ + /* sp = _tx_thread_system_stack_ptr[core]; */ + + MOV x4, sp // + STR x4, [x6, #8] // Save thread stack pointer + LDR x3, =_tx_thread_system_stack_ptr // Pickup address of system stack + LDR x4, [x3, x8, LSL #3] // Pickup system stack pointer + MOV sp, x4 // Setup system stack pointer + + /* Determine if the time-slice is active. */ + /* if (_tx_timer_time_slice[core]) + { */ + + MOV x4, #0 // Build clear value + CMP w1, #0 // Is a time-slice active? + BEQ __tx_thread_dont_save_ts // No, don't save the time-slice + + /* Save the current remaining time-slice. */ + /* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice; + _tx_timer_time_slice = 0; */ + + STR w4, [x2, x8, LSL #2] // Clear time-slice + STR w1, [x6, #36] // Store current time-slice + + /* } */ +__tx_thread_dont_save_ts: + + /* Clear the current thread pointer. */ + /* _tx_thread_current_ptr = TX_NULL; */ + + STR x4, [x5, x8, LSL #3] // Clear current thread pointer + + /* Set ready bit in thread control block. */ + + MOV x3, #1 // Build ready value + STR w3, [x6, #260] // Make the thread ready + DMB ISH // + + /* Now clear protection. It is assumed that protection is in force whenever this routine is called. */ + + LDR x3, =_tx_thread_smp_protection // Pickup address of protection structure + LDR x1, =_tx_thread_preempt_disable // Build address to preempt disable flag + STR w4, [x1, #0] // Clear preempt disable flag + STR w4, [x3, #8] // Cear protection count + MOV x1, #0xFFFFFFFF // Build invalid value + STR w1, [x3, #4] // Set core to an invalid value + DMB ISH // Ensure that accesses to shared resource have completed + STR w4, [x3, #0] // Clear protection + DSB ISH // To ensure update of the shared resource occurs before other CPUs awake + SEV // Send event to other CPUs, wakes anyone waiting on a mutex (using WFE) + B _tx_thread_schedule // Jump to scheduler! + +/* } */ + + diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_timeout.c b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_timeout.c new file mode 100644 index 00000000..635de647 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_thread_timeout.c @@ -0,0 +1,165 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_timer.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_timeout Cortex-A5x-SMP */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles thread timeout processing. Timeouts occur in */ +/* two flavors, namely the thread sleep timeout and all other service */ +/* call timeouts. Thread sleep timeouts are processed locally, while */ +/* the others are processed by the appropriate suspension clean-up */ +/* service. */ +/* */ +/* INPUT */ +/* */ +/* timeout_input Contains the thread pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* Suspension Cleanup Functions */ +/* _tx_thread_system_resume Resume thread */ +/* _tx_thread_system_ni_resume Non-interruptable resume thread */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_timer_expiration_process Timer expiration function */ +/* _tx_timer_thread_entry Timer thread function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_timeout(ULONG timeout_input) +{ + +TX_INTERRUPT_SAVE_AREA + +TX_THREAD *thread_ptr; +VOID (*suspend_cleanup)(struct TX_THREAD_STRUCT *suspend_thread_ptr, ULONG suspension_sequence); +ULONG suspension_sequence; + + + /* Pickup the thread pointer. */ + TX_THREAD_TIMEOUT_POINTER_SETUP(thread_ptr) + + /* Disable interrupts. */ + TX_DISABLE + + /* Determine how the thread is currently suspended. */ + if (thread_ptr -> tx_thread_state == TX_SLEEP) + { + +#ifdef TX_NOT_INTERRUPTABLE + + /* Resume the thread! */ + _tx_thread_system_ni_resume(thread_ptr); + + /* Restore interrupts. */ + TX_RESTORE +#else + + /* Increment the disable preemption flag. */ + _tx_thread_preempt_disable++; + + /* Restore interrupts. */ + TX_RESTORE + + /* Lift the suspension on the sleeping thread. */ + _tx_thread_system_resume(thread_ptr); +#endif + } + else + { + + /* Process all other suspension timeouts. */ + +#ifdef TX_THREAD_ENABLE_PERFORMANCE_INFO + + /* Increment the total number of thread timeouts. */ + _tx_thread_performance_timeout_count++; + + /* Increment the number of timeouts for this thread. */ + thread_ptr -> tx_thread_performance_timeout_count++; +#endif + + /* Pickup the cleanup routine address. */ + suspend_cleanup = thread_ptr -> tx_thread_suspend_cleanup; + +#ifndef TX_NOT_INTERRUPTABLE + + /* Pickup the suspension sequence number that is used later to verify that the + cleanup is still necessary. */ + suspension_sequence = thread_ptr -> tx_thread_suspension_sequence; +#else + + /* When not interruptable is selected, the suspension sequence is not used - just set to 0. */ + suspension_sequence = ((ULONG) 0); +#endif + +#ifndef TX_NOT_INTERRUPTABLE + + /* Restore interrupts. */ + TX_RESTORE +#endif + + /* Call any cleanup routines. */ + if (suspend_cleanup != TX_NULL) + { + + /* Yes, there is a function to call. */ + (suspend_cleanup)(thread_ptr, suspension_sequence); + } + +#ifdef TX_NOT_INTERRUPTABLE + + /* Restore interrupts. */ + TX_RESTORE +#endif + } +} + diff --git a/ports_smp/cortex_a5x_smp/gnu/src/tx_timer_interrupt.S b/ports_smp/cortex_a5x_smp/gnu/src/tx_timer_interrupt.S new file mode 100644 index 00000000..d89be120 --- /dev/null +++ b/ports_smp/cortex_a5x_smp/gnu/src/tx_timer_interrupt.S @@ -0,0 +1,198 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* #define TX_SOURCE_CODE */ + + +/* Include necessary system files. */ + +/* +#include "tx_api.h" +#include "tx_timer.h" +#include "tx_thread.h" +*/ + + .text + .align 3 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt Cortex-A5x-SMP/GNU */ +/* 6.0.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_timer_interrupt(VOID) +{ */ + .global _tx_timer_interrupt + .type _tx_timer_interrupt, @function +_tx_timer_interrupt: + + MRS x2, MPIDR_EL1 // Pickup the core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + UBFX x3, x2, #8, #8 // Isolate cluster ID +#endif + UBFX x2, x2, #0, #8 // Isolate core ID +#if TX_THREAD_SMP_CLUSTERS > 1 + ADDS x2, x2, x3, LSL #2 // Calculate CPU ID +#endif + CMP x2, #0 // Is this core 0? + BEQ __tx_process_timer // If desired core, continue processing + RET // Simply return if different core +__tx_process_timer: + + /* Upon entry to this routine, it is assumed that context save has already + been called, and therefore the compiler scratch registers are available + for use. */ + + STP x27, x28, [sp, #-16]! // Save x27, x28 + STP x29, x30, [sp, #-16]! // Save x29 (frame pointer), x30 (link register) + + /* Get inter-core protection. */ + + BL _tx_thread_smp_protect // Get inter-core protection + MOV x28, x0 // Save the return value in preserved register + + /* Increment the system clock. */ + /* _tx_timer_system_clock++; */ + + LDR x1, =_tx_timer_system_clock // Pickup address of system clock + LDR w0, [x1, #0] // Pickup system clock + ADD w0, w0, #1 // Increment system clock + STR w0, [x1, #0] // Store new system clock + + /* Test for timer expiration. */ + /* if (*_tx_timer_current_ptr) + { */ + + LDR x1, =_tx_timer_current_ptr // Pickup current timer pointer addr + LDR x0, [x1, #0] // Pickup current timer + LDR x2, [x0, #0] // Pickup timer list entry + CMP x2, #0 // Is there anything in the list? + BEQ __tx_timer_no_timer // No, just increment the timer + + /* Set expiration flag. */ + /* _tx_timer_expired = TX_TRUE; */ + + LDR x3, =_tx_timer_expired // Pickup expiration flag address + MOV w2, #1 // Build expired value + STR w2, [x3, #0] // Set expired flag + B __tx_timer_done // Finished timer processing + + /* } + else + { */ +__tx_timer_no_timer: + + /* No timer expired, increment the timer pointer. */ + /* _tx_timer_current_ptr++; */ + + ADD x0, x0, #8 // Move to next timer + + /* Check for wrap-around. */ + /* if (_tx_timer_current_ptr == _tx_timer_list_end) */ + + LDR x3, =_tx_timer_list_end // Pickup addr of timer list end + LDR x2, [x3, #0] // Pickup list end + CMP x0, x2 // Are we at list end? + BNE __tx_timer_skip_wrap // No, skip wrap-around logic + + /* Wrap to beginning of list. */ + /* _tx_timer_current_ptr = _tx_timer_list_start; */ + + LDR x3, =_tx_timer_list_start // Pickup addr of timer list start + LDR x0, [x3, #0] // Set current pointer to list start + +__tx_timer_skip_wrap: + + STR x0, [x1, #0] // Store new current timer pointer + /* } */ + +__tx_timer_done: + + /* Did a timer expire? */ + /* if (_tx_timer_expired) + { */ + + LDR x1, =_tx_timer_expired // Pickup addr of expired flag + LDR w0, [x1, #0] // Pickup timer expired flag + CMP w0, #0 // Check for timer expiration + BEQ __tx_timer_dont_activate // If not set, skip timer activation + + /* Process timer expiration. */ + /* _tx_timer_expiration_process(); */ + + BL _tx_timer_expiration_process // Call the timer expiration handling routine + + /* } */ +__tx_timer_dont_activate: + + /* Call time-slice processing. */ + /* _tx_thread_time_slice(); */ + BL _tx_thread_time_slice // Call time-slice processing + + /* Release inter-core protection. */ + + MOV x0, x28 // Pass the previous status register back + BL _tx_thread_smp_unprotect // Release protection + + LDP x29, x30, [sp], #16 // Recover x29, x30 + LDP x27, x28, [sp], #16 // Recover x27, x28 + RET // Return to caller + +/* } */ + + diff --git a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/.cproject b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/.cproject new file mode 100644 index 00000000..67bd7402 --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/.cproject @@ -0,0 +1,228 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/.project b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/.project new file mode 100644 index 00000000..725328bd --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/.project @@ -0,0 +1,27 @@ + + + sample_threadx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.arm.debug.ds.nature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/.settings/language.settings.xml b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/.settings/language.settings.xml new file mode 100644 index 00000000..4de6dbdb --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/.settings/language.settings.xml @@ -0,0 +1,512 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_GIC.h b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_GIC.h new file mode 100644 index 00000000..bcff9373 --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_GIC.h @@ -0,0 +1,74 @@ +// ------------------------------------------------------------ +// Cortex-A5 MPCore - Interrupt Controller functions +// Header File +// +// Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#ifndef _CORTEXA_GIC_ +#define _CORTEXA_GIC_ + +// ------------------------------------------------------------ +// GIC +// ------------------------------------------------------------ + +// Typical calls to enable interrupt ID X: +// enable_irq_id(X) <-- Enable that ID +// set_irq_priority(X, 0) <-- Set the priority of X to 0 (the max priority) +// set_priority_mask(0x1F) <-- Set Core's priority mask to 0x1F (the lowest priority) +// enable_GIC() <-- Enable the GIC (global) +// enable_gic_processor_interface() <-- Enable the CPU interface (local to the core) +// + + +// Global enable of the Interrupt Distributor +void enableGIC(void); + +// Global disable of the Interrupt Distributor +void disableGIC(void); + +// Enables the interrupt source number ID +void enableIntID(unsigned int ID); + +// Disables the interrupt source number ID +void disableIntID(unsigned int ID); + +// Sets the priority of the specified ID +void setIntPriority(unsigned int ID, unsigned int priority); + +// Enables the processor interface +// Must be done on each core separately +void enableGICProcessorInterface(void); + +// Disables the processor interface +// Must be done on each core separately +void disableGICProcessorInterface(void); + +// Sets the Priority mask register for the core run on +// The reset value masks ALL interrupts! +void setPriorityMask(unsigned int priority); + +// Sets the Binary Point Register for the core run on +void setBinaryPoint(unsigned int priority); + +// Returns the value of the Interrupt Acknowledge Register +unsigned int readIntAck(void); + +// Writes ID to the End Of Interrupt register +void writeEOI(unsigned int ID); + +// ------------------------------------------------------------ +// SGI +// ------------------------------------------------------------ + +// Send a software generate interrupt +void sendSGI(unsigned int ID, unsigned int core_list, unsigned int filter_list); + +#endif + +// ------------------------------------------------------------ +// End of MP_GIC.h +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_GIC.s b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_GIC.s new file mode 100644 index 00000000..cf11b1e5 --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_GIC.s @@ -0,0 +1,289 @@ +;---------------------------------------------------------------- +; Copyright (c) 2005-2018 Arm Limited (or its affiliates). All rights reserved. +; Use, modification and redistribution of this file is subject to your possession of a +; valid End User License Agreement for the Arm Product of which these examples are part of +; and your compliance with all applicable terms and conditions of such licence agreement. +; +; Cortex-A5MP SMP example - Startup Code +;---------------------------------------------------------------- + + + + AREA MP_GIC, CODE, READONLY + +;---------------------------------------------------------------- +; GIC. Generic Interrupt Controller Architecture Specification +;---------------------------------------------------------------- + + ; CPU Interface offset from base of private peripheral space --> 0x0100 + ; Interrupt Distributor offset from base of private peripheral space --> 0x1000 + + ; Typical calls to enable interrupt ID X: + ; enableIntID(X) <-- Enable that ID + ; setIntPriority(X, 0) <-- Set the priority of X to 0 (the max priority) + ; setPriorityMask(0x1F) <-- Set CPU's priority mask to 0x1F (the lowest priority) + ; enableGIC() <-- Enable the GIC (global) + ; enableGICProcessorInterface() <-- Enable the CPU interface (local to the CPU) + + + EXPORT enableGIC + ; void enableGIC(void) + ; Global enable of the Interrupt Distributor +enableGIC PROC + ; Get base address of private peripheral space + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + ADD r0, r0, #0x1000 ; Add the GIC offset + + LDR r1, [r0] ; Read the GIC Enable Register (ICDDCR) + ORR r1, r1, #0x01 ; Set bit 0, the enable bit + STR r1, [r0] ; Write the GIC Enable Register (ICDDCR) + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT disableGIC + ; void disableGIC(void) + ; Global disable of the Interrupt Distributor +disableGIC PROC + ; Get base address of private peripheral space + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + ADD r0, r0, #0x1000 ; Add the GIC offset + + LDR r1, [r0] ; Read the GIC Enable Register (ICDDCR) + BIC r1, r1, #0x01 ; Clear bit 0, the enable bit + STR r1, [r0] ; Write the GIC Enable Register (ICDDCR) + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT enableIntID + ; void enableIntID(unsigned int ID) + ; Enables the interrupt source number ID +enableIntID PROC + ; Get base address of private peripheral space + MOV r1, r0 ; Back up passed in ID value + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + ; Each interrupt source has an enable bit in the GIC. These + ; are grouped into registers, with 32 sources per register + ; First, we need to identify which 32-bit block the interrupt lives in + MOV r2, r1 ; Make working copy of ID in r2 + MOV r2, r2, LSR #5 ; LSR by 5 places, affective divide by 32 + ; r2 now contains the 32-bit block this ID lives in + MOV r2, r2, LSL #2 ; Now multiply by 4, to convert offset into an address offset (four bytes per reg) + + ; Now work out which bit within the 32-bit block the ID is + AND r1, r1, #0x1F ; Mask off to give offset within 32-bit block + MOV r3, #1 ; Move enable value into r3 + MOV r3, r3, LSL r1 ; Shift it left to position of ID + + ADD r2, r2, #0x1100 ; Add the base offset of the Enable Set registers to the offset for the ID + STR r3, [r0, r2] ; Store out (ICDISER) + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT disableIntID + ; void disableIntID(unsigned int ID) + ; Disables the interrupt source number ID +disableIntID PROC + ; Get base address of private peripheral space + MOV r1, r0 ; Back up passed in ID value + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + ; First, we need to identify which 32-bit block the interrupt lives in + MOV r2, r1 ; Make working copy of ID in r2 + MOV r2, r2, LSR #5 ; LSR by 5 places, affective divide by 32 + ; r2 now contains the 32-bit block this ID lives in + MOV r2, r2, LSL #2 ; Now multiply by 4, to convert offset into an address offset (four bytes per reg) + + ; Now work out which bit within the 32-bit block the ID is + AND r1, r1, #0x1F ; Mask off to give offset within 32-bit block + MOV r3, #1 ; Move enable value into r3 + MOV r3, r3, LSL r1 ; Shift it left to position of ID in 32-bit block + + ADD r2, r2, #0x1180 ; Add the base offset of the Enable Clear registers to the offset for the ID + STR r3, [r0, r2] ; Store out (ICDICER) + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT setIntPriority + ; void setIntPriority(unsigned int ID, unsigned int priority) + ; Sets the priority of the specified ID + ; r0 = ID + ; r1 = priority +setIntPriority PROC + ; Get base address of private peripheral space + MOV r2, r0 ; Back up passed in ID value + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + ; r0 = base addr + ; r1 = priority + ; r2 = ID + + ; Make sure that priority value is only 5 bits, and convert to expected format + AND r1, r1, #0x1F + MOV r1, r1, LSL #3 + + ; Find which register this ID lives in + BIC r3, r2, #0x03 ; Make a copy of the ID, clearing off the bottom two bits + ; There are four IDs per reg, by clearing the bottom two bits we get an address offset + ADD r3, r3, #0x1400 ; Now add the offset of the Priority Level registers from the base of the private peripheral space + ADD r0, r0, r3 ; Now add in the base address of the private peripheral space, giving us the absolute address + + ; Now work out which ID in the register it is + AND r2, r2, #0x03 ; Clear all but the bottom two bits, leaves which ID in the reg it is (which byte) + MOV r2, r2, LSL #3 ; Multiply by 8, this gives a bit offset + + ; Read -> Modify -> Write + MOV r12, #0xFF ; 8 bit field mask + MOV r12, r12, LSL r2 ; Move mask into correct bit position + MOV r1, r1, LSL r2 ; Also, move passed in priority value into correct bit position + + LDR r3, [r0] ; Read current value of the Priority Level register (ICDIPR) + BIC r3, r3, r12 ; Clear appropriate field + ORR r3, r3, r1 ; Now OR in the priority value + STR r3, [r0] ; And store it back again (ICDIPR) + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT enableGICProcessorInterface + ; void enableGICProcessorInterface(void) + ; Enables the processor interface + ; Must be done on each core separately +enableGICProcessorInterface PROC + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + ADD r0, r0, #0x2000 + + LDR r1, [r0, #0x0] ; Read the Processor Interface Control register (ICCICR/ICPICR) + ORR r1, r1, #0x03 ; Bit 0: Enables secure interrupts, Bit 1: Enables Non-Secure interrupts + BIC r1, r1, #0x08 ; Bit 3: Ensure Group 0 interrupts are signalled using IRQ, not FIQ + STR r1, [r0, #0x0] ; Write the Processor Interface Control register (ICCICR/ICPICR) + + BX lr + ENDP + + +; ------------------------------------------------------------ + + EXPORT disableGICProcessorInterface + ; void disableGICProcessorInterface(void) + ; Disables the processor interface + ; Must be done on each core separately +disableGICProcessorInterface PROC + + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + ADD r0, r0, #0x2000 + + LDR r1, [r0, #0x0] ; Read the Processor Interface Control register (ICCICR/ICPICR) + BIC r1, r1, #0x03 ; Bit 0: Enables secure interrupts, Bit 1: Enables Non-Secure interrupts + STR r1, [r0, #0x0] ; Write the Processor Interface Control register (ICCICR/ICPICR) + + BX lr + ENDP + + +; ------------------------------------------------------------ + + EXPORT setPriorityMask + ; void setPriorityMask(unsigned int priority) + ; Sets the Priority mask register for the CPU run on + ; The reset value masks ALL interrupts! +setPriorityMask PROC + + ; Get base address of private peripheral space + MRC p15, 4, r1, c15, c0, 0 ; Read periph base address + ADD r1, r1, #0x2000 + + STR r0, [r1, #0x4] ; Write the Priority Mask register (ICCPMR/ICCIPMR) + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT setBinaryPoint + ; void setBinaryPoint(unsigned int priority) + ; Sets the Binary Point Register for the CPU run on +setBinaryPoint PROC + + ; Get base address of private peripheral space + MRC p15, 4, r1, c15, c0, 0 ; Read periph base address + ADD r1, r1, #0x2000 + + STR r0, [r1, #0x8] ; Write the Binary register (ICCBPR/ICCBPR) + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT readIntAck + ; unsigned int readIntAck(void) + ; Returns the value of the Interrupt Acknowledge Register +readIntAck PROC + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + ADD r0, r0, #0x2000 + + LDR r0, [r0, #0xC] ; Read the Interrupt Acknowledge Register (ICCIAR) + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT writeEOI + ; void writeEOI(unsigned int ID) + ; Writes ID to the End Of Interrupt register +writeEOI PROC + + ; Get base address of private peripheral space + MRC p15, 4, r1, c15, c0, 0 ; Read periph base address + ADD r1, r1, #0x2000 + + STR r0, [r1, #0x10] ; Write ID to the End of Interrupt register (ICCEOIR) + + BX lr + ENDP + +;---------------------------------------------------------------- +; SGI +;---------------------------------------------------------------- + + EXPORT sendSGI + ; void sendSGI(unsigned int ID, unsigned int target_list, unsigned int filter_list); + ; Send a software generate interrupt +sendSGI PROC + AND r3, r0, #0x0F ; Mask off unused bits of ID, and move to r3 + AND r1, r1, #0x0F ; Mask off unused bits of target_filter + AND r2, r2, #0x0F ; Mask off unused bits of filter_list + + ORR r3, r3, r1, LSL #16 ; Combine ID and target_filter + ORR r3, r3, r2, LSL #24 ; and now the filter list + + ; Get the address of the GIC + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + ADD r0, r0, #0x1F00 ; Add offset of the sgi_trigger reg + + STR r3, [r0] ; Write to the Software Generated Interrupt Register (ICDSGIR) + + BX lr + ENDP + + + END + +;---------------------------------------------------------------- +; End of MP_GIC.s +;---------------------------------------------------------------- diff --git a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_Mutexes.h b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_Mutexes.h new file mode 100644 index 00000000..e410677b --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_Mutexes.h @@ -0,0 +1,40 @@ +// ------------------------------------------------------------ +// MP Mutex Header File +// +// Copyright (c) 2011-2014 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#ifndef MP_MUTEX_H +#define MP_MUTEX_H + +// 0xFF = unlocked +// 0x0 = Locked by CPU 0 +// 0x1 = Locked by CPU 1 +// 0x2 = Locked by CPU 2 +// 0x3 = Locked by CPU 3 +typedef struct +{ + unsigned int lock; +}mutex_t; + +// Places mutex into a known state +// r0 = address of mutex_t +void initMutex(mutex_t* pMutex); + +// Blocking call, returns once successfully locked a mutex +// r0 = address of mutex_t +void lockMutex(mutex_t* pMutex); + +// Releases (unlock) mutex. Fails if CPU not owner of mutex. +// returns 0x0 for success, and 0x1 for failure +// r0 = address of mutex_t +unsigned int unlockMutex(mutex_t* pMutex); + +// Returns 0x0 if mutex unlocked, 0x1 is locked +// r0 = address of mutex_t +unsigned int isMutexLocked(mutex_t* pMutex); + +#endif diff --git a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_Mutexes.s b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_Mutexes.s new file mode 100644 index 00000000..0574eab0 --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_Mutexes.s @@ -0,0 +1,123 @@ +; ------------------------------------------------------------ +; Cortex-A MPCore - Mutex Code +; +; Copyright (c) 2011-2012 Arm Limited (or its affiliates). All rights reserved. +; Use, modification and redistribution of this file is subject to your possession of a +; valid End User License Agreement for the Arm Product of which these examples are part of +; and your compliance with all applicable terms and conditions of such licence agreement. +; ------------------------------------------------------------ + + + + AREA MP_Mutexes, CODE, READONLY + + ;NOTES + ; struct mutex_t defined in MP_Mutexes.h + ; typedef struct mutex_t + ; { + ; unsigned int lock; <-- offset 0 + ; } + ; + ; lock: 0xFF=unlocked 0x0 = Locked by CPU 0, 0x1 = Locked by CPU 1, 0x2 = Locked by CPU 2, 0x3 = Locked by CPU 3 + ; + +UNLOCKED EQU 0xFF + +; ------------------------------------------------------------ + + EXPORT initMutex + ; void initMutex(mutex_t* pMutex) + ; Places mutex into a known state + ; r0 = address of mutex_t +initMutex PROC + + MOV r1, #UNLOCKED ; Mark as unlocked + STR r1, [r0] + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT lockMutex + ; void lockMutex(mutex_t* pMutex) + ; Blocking call, returns once successfully locked a mutex + ; r0 = address of mutex_t +lockMutex PROC + + ; Is mutex locked? + ; ----------------- + LDREX r1, [r0] ; Read lock field + CMP r1, #UNLOCKED ; Compare with "unlocked" + + WFENE ; If mutex is locked, go into standby + BNE lockMutex ; On waking re-check the mutex + + ; Attempt to lock mutex + ; ----------------------- + MRC p15, 0, r1, c0, c0, 5 ; Read CPU ID register + AND r1, r1, #0x03 ; Mask off, leaving the CPU ID field. + STREX r2, r1, [r0] ; Attempt to lock mutex, by write CPU's ID to lock field + CMP r2, #0x0 ; Check whether store completed successfully (0=succeeded) + BNE lockMutex ; If store failed, go back to beginning and try again + + DMB + + BX lr ; Return as mutex is now locked by this cpu + ENDP + +; ------------------------------------------------------------ + + EXPORT unlockMutex + ; unsigned int unlockMutex(mutex_t* pMutex) + ; Releases mutex, returns 0x0 for success and 0x1 for failure + ; r0 = address of mutex_t +unlockMutex PROC + + ; Does this CPU own the mutex? + ; ----------------------------- + MRC p15, 0, r1, c0, c0, 5 ; Read CPU ID register + AND r1, r1, #0x03 ; Mask off, leaving the CPU ID in r1 + LDR r2, [r0] ; Read the lock field of the mutex + CMP r1, r2 ; Compare ID of this CPU with the lock owner + MOVNE r0, #0x1 ; If ID doesn't match, return "fail" + BXNE lr + + + ; Unlock mutex + ; ------------- + DMB ; Ensure that accesses to shared resource have completed + + MOV r1, #UNLOCKED ; Write "unlocked" into lock field + STR r1, [r0] + + DSB ; Ensure that no instructions following the barrier execute until + ; all memory accesses prior to the barrier have completed. + + SEV ; Send event to other CPUs, wakes anyone waiting on a mutex (using WFE) + + MOV r0, #0x0 ; Return "success" + BX lr + + ENDP + +; ------------------------------------------------------------ + + EXPORT isMutexLocked + ; unsigned int isMutexLocked(mutex_t* pMutex) + ; Returns 0x0 if mutex unlocked, 0x1 is locked + ; r0 = address of mutex_t +isMutexLocked PROC + LDR r0, [r0] + CMP r0, #UNLOCKED + MOVEQ r0, #0x0 + MOVNE r0, #0x1 + BX lr + ENDP + + + END + +; ------------------------------------------------------------ +; End of MP_Mutexes.s +; ------------------------------------------------------------ diff --git a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_SCU.h b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_SCU.h new file mode 100644 index 00000000..a056bd3f --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_SCU.h @@ -0,0 +1,55 @@ +// ------------------------------------------------------------ +// Cortex-A9 MPCore - Snoop Control Unit +// Header File +// +// Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#ifndef _CORTEXA_SCU_ +#define _CORTEXA_SCU_ + +// ------------------------------------------------------------ +// Misc +// ------------------------------------------------------------ + +// Returns the number of cores in the cluster +// This is the format of the register, decided to leave it unchanged. +unsigned int getNumCPUs(void); + +// Go to sleep, never returns +void goToSleep(void); + +// ------------------------------------------------------------ +// SCU +// ------------------------------------------------------------ + +// Enables the SCU +void enableSCU(void); + +// The return value is 1 bit per core: +// bit 0 - CPU 0 +// bit 1 - CPU 1 +// etc... +unsigned int getCPUsInSMP(void); + + //Enable the broadcasting of cache & TLB maintenance operations +// When enabled AND in SMP, broadcast all "inner sharable" +// cache and TLM maintenance operations to other SMP cores +void enableMaintenanceBroadcast(void); + +// Disable the broadcasting of cache & TLB maintenance operations +void disableMaintenanceBroadcast(void); + +// cpu: 0x0=CPU 0 0x1=CPU 1 etc... +// This function invalidates the SCU copy of the tag rams +// for the specified core. +void secureSCUInvalidate(unsigned int cpu, unsigned int ways); + +#endif + +// ------------------------------------------------------------ +// End of MP_SCU.h +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_SCU.s b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_SCU.s new file mode 100644 index 00000000..2c24df11 --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/MP_SCU.s @@ -0,0 +1,132 @@ +;---------------------------------------------------------------- +; Copyright (c) 2005-2018 Arm Limited (or its affiliates). All rights reserved. +; Use, modification and redistribution of this file is subject to your possession of a +; valid End User License Agreement for the Arm Product of which these examples are part of +; and your compliance with all applicable terms and conditions of such licence agreement. +; +; Cortex-A SMP example - Startup Code +;---------------------------------------------------------------- + + + + AREA MP_SCU, CODE, READONLY + +;---------------------------------------------------------------- +; Misc +;---------------------------------------------------------------- + + EXPORT getNumCPUs + ; unsigned int getNumCPUs(void) + ; Returns the number of CPUs in the Cluster +getNumCPUs PROC + + ; Get base address of private peripheral space + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + LDR r0, [r0, #0x004] ; Read SCU Configuration register + AND r0, r0, #0x3 ; Bits 1:0 gives the number of cores-1 + ADD r0, r0, #1 + BX lr + ENDP + +;---------------------------------------------------------------- +; SCU +;---------------------------------------------------------------- + + ; SCU offset from base of private peripheral space --> 0x000 + + EXPORT enableSCU + ; void enableSCU(void) + ; Enables the SCU +enableSCU PROC + + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + LDR r1, [r0, #0x0] ; Read the SCU Control Register + ORR r1, r1, #0x1 ; Set bit 0 (The Enable bit) + STR r1, [r0, #0x0] ; Write back modifed value + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT getCPUsInSMP + ; unsigned int getCPUsInSMP(void) + ; The return value is 1 bit per core: + ; bit 0 - CPU 0 + ; bit 1 - CPU 1 + ; etc... +getCPUsInSMP PROC + + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + LDR r0, [r0, #0x004] ; Read SCU Configuration register + MOV r0, r0, LSR #4 ; Bits 7:4 gives the cores in SMP mode, shift then mask + AND r0, r0, #0x0F + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT enableMaintenanceBroadcast + ; void enableMaintenanceBroadcast(void) + ; Enable the broadcasting of cache & TLB maintenance operations + ; When enabled AND in SMP, broadcast all "inner sharable" + ; cache and TLM maintenance operations to other SMP cores +enableMaintenanceBroadcast PROC + MRC p15, 0, r0, c1, c0, 1 ; Read Aux Ctrl register + MOV r1, r0 + ORR r0, r0, #0x01 ; Set the FW bit (bit 0) + CMP r0, r1 + MCRNE p15, 0, r0, c1, c0, 1 ; Write Aux Ctrl register + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT disableMaintenanceBroadcast + ; void disableMaintenanceBroadcast(void) + ; Disable the broadcasting of cache & TLB maintenance operations +disableMaintenanceBroadcast PROC + MRC p15, 0, r0, c1, c0, 1 ; Read Aux Ctrl register + BIC r0, r0, #0x01 ; Clear the FW bit (bit 0) + MCR p15, 0, r0, c1, c0, 1 ; Write Aux Ctrl register + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT secureSCUInvalidate + ; void secureSCUInvalidate(unsigned int cpu, unsigned int ways) + ; cpu: 0x0=CPU 0 0x1=CPU 1 etc... + ; This function invalidates the SCU copy of the tag rams + ; for the specified core. Typically only done at start-up. + ; Possible flow: + ; - Invalidate L1 caches + ; - Invalidate SCU copy of TAG RAMs + ; - Join SMP +secureSCUInvalidate PROC + AND r0, r0, #0x03 ; Mask off unused bits of CPU ID + MOV r0, r0, LSL #2 ; Convert into bit offset (four bits per core) + + AND r1, r1, #0x0F ; Mask off unused bits of ways + MOV r1, r1, LSL r0 ; Shift ways into the correct CPU field + + MRC p15, 4, r2, c15, c0, 0 ; Read periph base address + + STR r1, [r2, #0x0C] ; Write to SCU Invalidate All in Secure State + + BX lr + + ENDP + + + END + +;---------------------------------------------------------------- +; End of MP_SCU.s +;---------------------------------------------------------------- diff --git a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/sample_threadx.c new file mode 100644 index 00000000..1b6df7c2 --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/sample_threadx.c @@ -0,0 +1,381 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_TIMER timer_0; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +#ifdef TX_ENABLE_EVENT_TRACE + +UCHAR event_buffer[65536]; + +#endif + + + +int main(void) +{ + + /* Enter ThreadX. */ + tx_kernel_enter(); + + return 0; +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + +#ifdef TX_ENABLE_EVENT_TRACE + + tx_trace_enable(event_buffer, sizeof(event_buffer), 32); +#endif + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + diff --git a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/sample_threadx.launch b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/sample_threadx.launch new file mode 100644 index 00000000..44b943a3 --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/sample_threadx.launch @@ -0,0 +1,148 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/sample_threadx.scat b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/sample_threadx.scat new file mode 100644 index 00000000..6cdf755a --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/sample_threadx.scat @@ -0,0 +1,37 @@ +;************************************************** +; Copyright (c) 2012 Arm Limited (or its affiliates). All rights reserved. +; Use, modification and redistribution of this file is subject to your possession of a +; valid End User License Agreement for the Arm Product of which these examples are part of +; and your compliance with all applicable terms and conditions of such licence agreement. +;************************************************** + +; Scatter-file for Cortex-A5 MPCore bare-metal example on Versatile Express + +; This scatter-file places application code, data, stack and heap at suitable addresses in memory map. + +; CoreTile Express A5x2 has 1GB SDRAM at 0x80000000 to 0xBFFFFFFF, which this scatter-file uses. + +LOAD 0x80000000 0x00010000 +{ + EXEC +0 + { + startup.o (StartUp, +FIRST) + * (+RO) + } + + ; App heap for all CPUs + ARM_LIB_HEAP +0 ALIGN 8 EMPTY 0x8000 {} + + ; App stacks for all CPUs - see startup.s + ARM_LIB_STACK +0 ALIGN 8 EMPTY 4*0x4000 {} + + ; IRQ stacks for all CPUs - see startup.s + IRQ_STACKS +0 ALIGN 8 EMPTY 4*1024 {} + + SHARED_DATA +0x0 + { + * (+RW,+ZI) + } + + PAGETABLES 0x80500000 EMPTY 0x00100000 {} +} \ No newline at end of file diff --git a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/startup.s b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/startup.s new file mode 100644 index 00000000..ce9018ac --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/startup.s @@ -0,0 +1,580 @@ +; ------------------------------------------------------------ +; Cortex-A5 MPCore Startup Code +; +; Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. +; Use, modification and redistribution of this file is subject to your possession of a +; valid End User License Agreement for the Arm Product of which these examples are part of +; and your compliance with all applicable terms and conditions of such licence agreement. +; ------------------------------------------------------------ + + PRESERVE8 + + AREA StartUp,CODE,READONLY + +; Standard definitions of mode bits and interrupt (I&F) flags in PSRs + +Mode_USR EQU 0x10 +Mode_FIQ EQU 0x11 +Mode_IRQ EQU 0x12 +Mode_SVC EQU 0x13 +Mode_ABT EQU 0x17 +Mode_UND EQU 0x1B +Mode_SYS EQU 0x1F + +I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled +F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled + + +; ------------------------------------------------------------ +; Porting defines +; ------------------------------------------------------------ + +L1_COHERENT EQU 0x00014c06 ; Template descriptor for coherent memory +L1_NONCOHERENT EQU 0x00000c1e ; Template descriptor for non-coherent memory +L1_DEVICE EQU 0x00000c16 ; Template descriptor for device memory + +; ------------------------------------------------------------ + + ENTRY + + EXPORT Vectors + +Vectors + B Reset_Handler + B Undefined_Handler + B SVC_Handler + B Prefetch_Handler + B Abort_Handler + B . ;Reserved vector + B IRQ_Handler + B FIQ_Handler + +; ------------------------------------------------------------ +; Handlers for unused exceptions +; ------------------------------------------------------------ + +Undefined_Handler + B Undefined_Handler +SVC_Handler + B SVC_Handler +Prefetch_Handler + B Prefetch_Handler +Abort_Handler + B Abort_Handler +FIQ_Handler + B FIQ_Handler + +; ------------------------------------------------------------ +; Imports +; ------------------------------------------------------------ + IMPORT readIntAck + IMPORT writeEOI + IMPORT enableGIC + IMPORT enableGICProcessorInterface + IMPORT setPriorityMask + IMPORT enableIntID + IMPORT setIntPriority + IMPORT enableSCU + IMPORT joinSMP + IMPORT secureSCUInvalidate + IMPORT enableMaintenanceBroadcast + IMPORT invalidateCaches + IMPORT disableHighVecs + IMPORT __main +; IMPORT main_app +; [EL Change Start] + IMPORT _tx_thread_smp_initialize_wait + IMPORT _tx_thread_smp_release_cores_flag + IMPORT _tx_thread_context_save + IMPORT _tx_thread_context_restore + IMPORT _tx_timer_interrupt + IMPORT _tx_thread_smp_inter_core_interrupts +; [EL Change End] + + IMPORT __use_two_region_memory + IMPORT ||Image$$ARM_LIB_STACK$$ZI$$Limit|| + IMPORT ||Image$$IRQ_STACKS$$ZI$$Limit|| + IMPORT ||Image$$PAGETABLES$$ZI$$Base|| + IMPORT ||Image$$EXEC$$Base|| + +; ------------------------------------------------------------ +; Interrupt Handler +; ------------------------------------------------------------ + + EXPORT IRQ_Handler + EXPORT __tx_irq_processing_return +IRQ_Handler PROC +; [EL Change Start] +; SUB lr, lr, #4 ; Pre-adjust lr +; SRSFD sp!, #Mode_IRQ ; Save lr and SPRS to IRQ mode stack +; PUSH {r0-r4, r12} ; Sace APCS corruptable registers to IRQ mode stack (and maintain 8 byte alignment) +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return + PUSH {r4, r5} ; Save some preserved registers (r5 is saved just for 8-byte alignment) +; [EL Change End] + + ; Acknowledge the interrupt + BL readIntAck + MOV r4, r0 + + ; + ; This example only uses (and enables) one. At this point + ; you would normally check the ID, and clear the source. + ; + + ; + ; Additonal code to handler private timer interrupt on CPU0 + ; + + CMP r0, #29 ; If not Private Timer interrupt (ID 29), by pass + BNE by_pass + +; [EL Change Start] +; MOV r0, #0x04 ; Code for SYS_WRITE0 +; LDR r1, =irq_handler_message0 +; SVC 0x123456 +; [EL Change End] + + ; Set new timeout value for the timer, which clears the interrupt. + MOV r0, #0xF0000 + MCR p15, 0, r0, c14, c2, 0 ; Setup timeout value (CNTP_TVAL) + DSB +; [EL Change Start] + BL _tx_timer_interrupt ; Timer interrupt handler +; [EL Change End] + + B by_pass2 + +by_pass + +; [EL Change Start] + ; + ; Additional code to handle SGI on CPU0 + ; +; +; MRC p15, 0, r0, c0, c0, 5 ; Read CPU ID register +; ANDS r0, r0, #0x03 ; Mask off, leaving the CPU ID field +; BNE by_pass2 +; +; MOV r0, #0x04 ; Code for SYS_WRITE0 +; LDR r1, =irq_handler_message1 +; SVC 0x123456 +; +; /* Just increment the per-thread interrupt count for analysis purposes. */ +; + MRC p15, 0, r0, c0, c0, 5 ; Read CPU ID register + AND r0, r0, #0x03 ; Mask off, leaving the CPU ID field + LSL r0, r0, #2 ; Build offset to array indexes + LDR r1,=_tx_thread_smp_inter_core_interrupts ; Pickup base address of core interrupt counter array + ADD r1, r1, r0 ; Build array index + LDR r0, [r1] ; Pickup counter + ADD r0, r0, #1 ; Increment counter + STR r0, [r1] ; Store back counter +; +; [EL Change End] + + +by_pass2 + ; Write end of interrupt reg + MOV r0, r4 + BL writeEOI + +; [EL Change Start] + +; +; /* Jump to context restore to restore system context. */ + POP {r4, r5} ; Recover preserved registers + B _tx_thread_context_restore + +; POP {r0-r4, r12} ; Restore stacked APCS registers +; MOV r2, #0x01 ; Set r2 so CPU leaves holding pen +; RFEFD sp! ; Return from exception +; [EL Change End] + + ENDP + +; ------------------------------------------------------------ +; Reset Handler - Generic initialization, run by all CPUs +; ------------------------------------------------------------ + + EXPORT Reset_Handler +Reset_Handler PROC {} + +; ------------------------------------------------------------ +; Disable caches and MMU in case they were left enabled from an earlier run +; This does not need to be done from a cold reset +; ------------------------------------------------------------ + MRC p15, 0, r0, c1, c0, 0 ; Read System Control Register + BIC r0, r0, #(0x1 << 12) ; Clear I, bit 12, to disable I Cache + BIC r0, r0, #(0x1 << 2) ; Clear C, bit 2, to disable D Cache + BIC r0, r0, #(0x1 << 1) ; Clear A, bit 1, to disable strict alignment fault checking + BIC r0, r0, #0x1 ; Clear M, bit 0, to disable MMU + MCR p15, 0, r0, c1, c0, 0 ; Write System Control Register + ISB + +; The MMU is enabled later, before calling main(). Caches are enabled inside main(), +; after the MMU has been enabled and scatterloading has been performed. + + ; + ; Setup stacks + ;--------------- + + MRC p15, 0, r0, c0, c0, 5 ; Read CPU ID register + ANDS r0, r0, #0x03 ; Mask off, leaving the CPU ID field + + MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit + LDR r1, =||Image$$IRQ_STACKS$$ZI$$Limit|| + SUB r1, r1, r0, LSL #10 ; 1024 bytes of IRQ stack per CPU - see scatter.scat + MOV sp, r1 + + MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit ; Interrupts initially disabled + LDR r1, =||Image$$ARM_LIB_STACK$$ZI$$Limit|| ; App stacks for all CPUs + SUB r1, r1, r0, LSL #14 ; 0x4000 bytes of App stack per CPU - see scatter.scat + MOV sp, r1 + + ; + ; Set vector base address + ; ------------------------ + LDR r0, =Vectors + MCR p15, 0, r0, c12, c0, 0 ; Write Secure or Non-secure Vector Base Address + BL disableHighVecs ; Ensure that V-bit is cleared + + ; + ; Invalidate caches + ; ------------------ + BL invalidateCaches + + ; + ; Clear Branch Prediction Array + ; ------------------------------ + MOV r0, #0x0 + MCR p15, 0, r0, c7, c5, 6 ; BPIALL - Invalidate entire branch predictor array + + ; + ; Invalidate TLBs + ;------------------ + MOV r0, #0x0 + MCR p15, 0, r0, c8, c7, 0 ; TLBIALL - Invalidate entire Unified TLB + + ; + ; Set up Domain Access Control Reg + ; ---------------------------------- + ; b00 - No Access (abort) + ; b01 - Client (respect table entry) + ; b10 - RESERVED + ; b11 - Manager (ignore access permissions) + + MRC p15, 0, r0, c3, c0, 0 ; Read Domain Access Control Register + LDR r0, =0x55555555 ; Initialize every domain entry to b01 (client) + MCR p15, 0, r0, c3, c0, 0 ; Write Domain Access Control Register + + ;; + ;; Enable L1 Preloader - Auxiliary Control + ;; ----------------------------------------- + ;; Seems to undef on panda? + ;MRC p15, 0, r0, c1, c0, 1 ; Read ACTLR + ;ORR r0, r0, #0x4 + ;MCR p15, 0, r0, c1, c0, 1 ; Write ACTLR + ISB + + + ; + ; Set location of level 1 page table + ;------------------------------------ + ; 31:14 - Base addr + ; 13:5 - 0x0 + ; 4:3 - RGN 0x0 (Outer Noncachable) + ; 2 - P 0x0 + ; 1 - S 0x0 (Non-shared) + ; 0 - C 0x0 (Inner Noncachable) + LDR r0, =||Image$$PAGETABLES$$ZI$$Base|| + MSR TTBR0, r0 + + + ; + ; Activate VFP/NEON, if required + ;------------------------------- + + IF {TARGET_FEATURE_NEON} || {TARGET_FPU_VFP} + + ; Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11. + ; Enables Full Access i.e. in both privileged and non privileged modes + MRC p15, 0, r0, c1, c0, 2 ; Read Coprocessor Access Control Register (CPACR) + ORR r0, r0, #(0xF << 20) ; Enable access to CP 10 & 11 + MCR p15, 0, r0, c1, c0, 2 ; Write Coprocessor Access Control Register (CPACR) + ISB + + ; Switch on the VFP and NEON hardware + MOV r0, #0x40000000 + VMSR FPEXC, r0 ; Write FPEXC register, EN bit set + + ENDIF + +; [EL Change Start] + + LDR r0, =_tx_thread_smp_release_cores_flag ; Build address of release cores flag + MOV r1, #0 + STR r1, [r0] + +; [EL Change End] + ; + ; SMP initialization + ; ------------------- + MRC p15, 0, r0, c0, c0, 5 ; Read CPU ID register + ANDS r0, r0, #0x03 ; Mask off, leaving the CPU ID field + BEQ primaryCPUInit + BNE secondaryCPUsInit + + ENDP + + +; ------------------------------------------------------------ +; Initialization for PRIMARY CPU +; ------------------------------------------------------------ + + EXPORT primaryCPUInit +primaryCPUInit PROC + + ; Translation tables + ; ------------------- + ; The translation tables are generated at boot time. + ; First the table is zeroed. Then the individual valid + ; entries are written in + ; + + LDR r0, =||Image$$PAGETABLES$$ZI$$Base|| + + ; Fill table with zeros + MOV r2, #1024 ; Set r3 to loop count (4 entries per iteration, 1024 iterations) + MOV r1, r0 ; Make a copy of the base dst + MOV r3, #0 + MOV r4, #0 + MOV r5, #0 + MOV r6, #0 +ttb_zero_loop + STMIA r1!, {r3-r6} ; Store out four entries + SUBS r2, r2, #1 ; Decrement counter + BNE ttb_zero_loop + + ; + ; STANDARD ENTRIES + ; + + ; Region covering program code and data + LDR r1,=||Image$$EXEC$$Base|| ; Base physical address of program code and data + LSR r1,#20 ; Shift right to align to 1MB boundaries + LDR r3, =L1_COHERENT ; Descriptor template + ORR r3, r1, LSL#20 ; Combine address and template + STR r3, [r0, r1, LSL#2] ; Store table entry + + ; Entry for private address space + ; Needs to be marked as Device memory + MRC p15, 4, r1, c15, c0, 0 ; Get base address of private address space + LSR r1, r1, #20 ; Clear bottom 20 bits, to find which 1MB block it is in + LSL r2, r1, #2 ; Make a copy, and multiply by four. This gives offset into the page tables + LSL r1, r1, #20 ; Put back in address format + LDR r3, =L1_DEVICE ; Descriptor template + ORR r1, r1, r3 ; Combine address and template + STR r1, [r0, r2] ; Store table entry + + ; + ; OPTIONAL ENTRIES + ; You will need additional translations if: + ; - No RAM at zero, so cannot use flat mapping + ; - You wish to retarget + ; + ; If you wish to output to stdio to a UART you will need + ; an additional entry + ;LDR r1, =PABASE_UART ; Physical address of UART + ;LSR r1, r1, #20 ; Mask off bottom 20 bits to find which 1MB it is within + ;LSL r2, r1, #2 ; Make a copy and multiply by 4 to get table offset + ;LSL r1, r1, #20 ; Put back into address format + ;LDR r3, =L1_DEVICE ; Descriptor template + ;ORR r1, r1, r3 ; Combine address and template + ;STR r1, [r0, r2] ; Store table entry + + DSB + + + ; Enable MMU + ; ----------- + ; Leave the caches disabled until after scatter loading. + MRC p15, 0, r0, c1, c0, 0 ; Read System Control Register + ORR r0, r0, #0x1 ; Set M bit 0 to enable MMU before scatter loading + MCR p15, 0, r0, c1, c0, 0 ; Write System Control Register + ISB + + + ; Enable the SCU + ; --------------- + BL enableSCU + + ; + ; Join SMP + ; --------- + MOV r0, #0x0 ; Move CPU ID into r0 + MOV r1, #0xF ; Move 0xF (represents all four ways) into r1 + BL secureSCUInvalidate + BL joinSMP + BL enableMaintenanceBroadcast + + ; + ; GIC Init + ; --------- + BL enableGIC + BL enableGICProcessorInterface + + ; + ; Enable Private Timer for periodic IRQ + ; -------------------------------------- + MOV r0, #0x1F + BL setPriorityMask ; Set priority mask (local) + + ; [EL] Change start - don't enable interrupts here! + ;CPSIE i ; Clear CPSR I bit + ; [EL] Change end + + ; Enable the Private Timer Interrupt Source + MOV r0, #29 + MOV r1, #0 + BL enableIntID + + ; Set the priority + MOV r0, #29 + MOV r1, #0 + BL setIntPriority + + ; Configure Timer + MOV r0, #0xF0000 + MCR p15, 0, r0, c14, c2, 0 ; Setup timeout value (CNTP_TVAL) + MOV r0, #0x1 + MCR p15, 0, r0, c14, c2, 1 ; Enable timer (CNTP_CTL) + + ; + ; Enable receipt of SGI 0 + ; ------------------------ + MOV r0, #0x0 ; ID + BL enableIntID + + MOV r0, #0x0 ; ID + MOV r1, #0x0 ; Priority + BL setIntPriority + + ; + ; Branch to C lib code + ; ---------------------- + B __main + + + ENDP + +; ------------------------------------------------------------ +; Initialization for SECONDARY CPUs +; ------------------------------------------------------------ + + EXPORT secondaryCPUsInit +secondaryCPUsInit PROC + + ; + ; GIC Init + ; --------- + BL enableGICProcessorInterface + + MOV r0, #0x1F ; Priority + BL setPriorityMask + + MOV r0, #0x0 ; ID + BL enableIntID + + MOV r0, #0x0 ; ID + MOV r1, #0x0 ; Priority + BL setIntPriority + + ; + ; Join SMP + ; --------- + MRC p15, 0, r0, c0, c0, 5 ; Read CPU ID register + ANDS r0, r0, #0x03 ; Mask off, leaving the CPU ID field + MOV r1, #0xF ; Move 0xF (represents all four ways) into r1 + BL secureSCUInvalidate + + BL joinSMP + BL enableMaintenanceBroadcast + +; [EL Change Start] + ; + ; Holding Pen + ; ------------ +; MOV r2, #0x00 ; Clear r2 +; CPSIE i ; Enable interrupts +holding_pen +; CMP r2, #0x0 ; r2 will be set to 0x1 by IRQ handler on receiving SGI +; WFIEQ +; BEQ holding_pen +; CPSID i ; IRQs not used in reset of example, so mask out interrupts +skip +; + ; + ; Branch to C lib code + ; ---------------------- +; B __main + + B _tx_thread_smp_initialize_wait +; [EL Change End] + + ; + ; The translation tables are generated by the primary CPU + ; The MMU cannot be enabled on the secondary CPUs until + ; they are released from the holding-pen + ; + + ; Enable MMU + ; ----------- + ; Leave the caches disabled until after scatter loading. + MRC p15, 0, r0, c1, c0, 0 ; Read System Control Register + ORR r0, r0, #0x1 ; Set M bit 0 to enable MMU before scatter loading + MCR p15, 0, r0, c1, c0, 0 ; Write System Control Register + ISB + + + ; + ; Branch to application + ; ---------------------- +; B main_app + + + ENDP + +; ------------------------------------------------------------ +; Enable caches +; This code must be run from a privileged mode +; ------------------------------------------------------------ + + AREA ENABLECACHES, CODE, READONLY + + EXPORT enable_caches + +enable_caches FUNCTION + +; ------------------------------------------------------------ +; Enable caches +; ------------------------------------------------------------ + + MRC p15, 0, r0, c1, c0, 0 ; Read System Control Register + ORR r0, r0, #(0x1 << 12) ; Set I bit 12 to enable I Cache + ORR r0, r0, #(0x1 << 2) ; Set C bit 2 to enable D Cache + MCR p15, 0, r0, c1, c0, 0 ; Write System Control Register + ISB + + BX lr + + ENDFUNC + + + END + +; ------------------------------------------------------------ +; End of startup.s +; ------------------------------------------------------------ diff --git a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/tx_initialize_low_level.s b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/tx_initialize_low_level.s new file mode 100644 index 00000000..8f25e519 --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/tx_initialize_low_level.s @@ -0,0 +1,119 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_initialize.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +; +; + IMPORT _tx_thread_system_stack_ptr + IMPORT _tx_initialize_unused_memory + IMPORT _tx_version_id + IMPORT _tx_build_options + IMPORT ||Image$$SHARED_DATA$$ZI$$Limit|| +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level SMP/Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + EXPORT _tx_initialize_low_level +_tx_initialize_low_level +; +; /* Save the first available memory address. */ +; _tx_initialize_unused_memory = (VOID_PTR) (||Image$$SHARED_DATA$$ZI$$Limit||); +; + LDR r0, =||Image$$SHARED_DATA$$ZI$$Limit|| ; Get end of non-initialized RAM area + LDR r2, =_tx_initialize_unused_memory ; Pickup unused memory ptr address + STR r0, [r2, #0] ; Save first free memory address +; +; + +; /* Done, return to caller. */ +; + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +;} +; +; /* Reference build options and version ID to ensure they come in. */ +; + LDR r2, =_tx_build_options ; Pickup build options variable address + LDR r0, [r2, #0] ; Pickup build options content + LDR r2, =_tx_version_id ; Pickup version ID variable address + LDR r0, [r2, #0] ; Pickup version ID content +; +; + + END + diff --git a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/v7.h b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/v7.h new file mode 100644 index 00000000..5a08b43f --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/v7.h @@ -0,0 +1,155 @@ +// ------------------------------------------------------------ +// v7-A Cache, TLB and Branch Prediction Maintenance Operations +// Header File +// +// Copyright (c) 2011-2016 Arm Limited (or its affiliates). All rights reserved. +// Use, modification and redistribution of this file is subject to your possession of a +// valid End User License Agreement for the Arm Product of which these examples are part of +// and your compliance with all applicable terms and conditions of such licence agreement. +// ------------------------------------------------------------ + +#ifndef _ARMV7A_GENERIC_H +#define _ARMV7A_GENERIC_H + +// ------------------------------------------------------------ +// Memory barrier mnemonics +enum MemBarOpt { + RESERVED_0 = 0, RESERVED_1 = 1, OSHST = 2, OSH = 3, + RESERVED_4 = 4, RESERVED_5 = 5, NSHST = 6, NSH = 7, + RESERVED_8 = 8, RESERVED_9 = 9, ISHST = 10, ISH = 11, + RESERVED_12 = 12, RESERVED_13 = 13, ST = 14, SY = 15 +}; + +// +// Note: +// *_IS() stands for "inner shareable" +// DO NOT USE THESE FUNCTIONS ON A CORTEX-A8 +// + +// ------------------------------------------------------------ +// Interrupts +// Enable/disables IRQs (not FIQs) +void enableInterrupts(void); +void disableInterrupts(void); + +// ------------------------------------------------------------ +// Caches + +void invalidateCaches_IS(void); +void cleanInvalidateDCache(void); +void invalidateCaches_IS(void); +void enableCaches(void); +void disableCaches(void); +void invalidateCaches(void); +void cleanDCache(void); + +// ------------------------------------------------------------ +// TLBs + +void invalidateUnifiedTLB(void); +void invalidateUnifiedTLB_IS(void); + +// ------------------------------------------------------------ +// Branch prediction + +void flushBranchTargetCache(void); +void flushBranchTargetCache_IS(void); + +// ------------------------------------------------------------ +// High Vecs + +void enableHighVecs(void); +void disableHighVecs(void); + +// ------------------------------------------------------------ +// ID Registers + +unsigned int getMIDR(void); + +#define MIDR_IMPL_SHIFT 24 +#define MIDR_IMPL_MASK 0xFF +#define MIDR_VAR_SHIFT 20 +#define MIDR_VAR_MASK 0xF +#define MIDR_ARCH_SHIFT 16 +#define MIDR_ARCH_MASK 0xF +#define MIDR_PART_SHIFT 4 +#define MIDR_PART_MASK 0xFFF +#define MIDR_REV_SHIFT 0 +#define MIDR_REV_MASK 0xF + +// tmp = get_MIDR(); +// implementor = (tmp >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; +// variant = (tmp >> MIDR_VAR_SHIFT) & MIDR_VAR_MASK; +// architecture= (tmp >> MIDR_ARCH_SHIFT) & MIDR_ARCH_MASK; +// part_number = (tmp >> MIDR_PART_SHIFT) & MIDR_PART_MASK; +// revision = tmp & MIDR_REV_MASK; + +#define MIDR_PART_CA5 0xC05 +#define MIDR_PART_CA8 0xC08 +#define MIDR_PART_CA9 0xC09 + +unsigned int getMPIDR(void); + +#define MPIDR_FORMAT_SHIFT 31 +#define MPIDR_FORMAT_MASK 0x1 +#define MPIDR_UBIT_SHIFT 30 +#define MPIDR_UBIT_MASK 0x1 +#define MPIDR_CLUSTER_SHIFT 7 +#define MPIDR_CLUSTER_MASK 0xF +#define MPIDR_CPUID_SHIFT 0 +#define MPIDR_CPUID_MASK 0x3 + +#define MPIDR_CPUID_CPU0 0x0 +#define MPIDR_CPUID_CPU1 0x1 +#define MPIDR_CPUID_CPU2 0x2 +#define MPIDR_CPUID_CPU3 0x3 + +#define MPIDR_UNIPROCESSPR 0x1 + +#define MPDIR_NEW_FORMAT 0x1 + +// ------------------------------------------------------------ +// Context ID + +unsigned int getContextID(void); + +void setContextID(unsigned int); + +#define CONTEXTID_ASID_SHIFT 0 +#define CONTEXTID_ASID_MASK 0xFF +#define CONTEXTID_PROCID_SHIFT 8 +#define CONTEXTID_PROCID_MASK 0x00FFFFFF + +// tmp = getContextID(); +// ASID = tmp & CONTEXTID_ASID_MASK; +// PROCID = (tmp >> CONTEXTID_PROCID_SHIFT) & CONTEXTID_PROCID_MASK; + +// ------------------------------------------------------------ +// SMP related for Armv7-A MPCore processors +// +// DO NOT CALL THESE FUNCTIONS ON A CORTEX-A8 + +// Returns the base address of the private peripheral memory space +unsigned int getBaseAddr(void); + +// Returns the CPU ID (0 to 3) of the CPU executed on +#define MP_CPU0 (0) +#define MP_CPU1 (1) +#define MP_CPU2 (2) +#define MP_CPU3 (3) +unsigned int getCPUID(void); + +// Set this core as participating in SMP +void joinSMP(void); + +// Set this core as NOT participating in SMP +void leaveSMP(void); + +// Go to sleep, never returns +void goToSleep(void); + +#endif + +// ------------------------------------------------------------ +// End of v7.h +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/v7.s b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/v7.s new file mode 100644 index 00000000..35a94ff8 --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/v7.s @@ -0,0 +1,458 @@ +; ------------------------------------------------------------ +; v7-A Cache and Branch Prediction Maintenance Operations +; +; Copyright (c) 2011-2018 Arm Limited (or its affiliates). All rights reserved. +; Use, modification and redistribution of this file is subject to your possession of a +; valid End User License Agreement for the Arm Product of which these examples are part of +; and your compliance with all applicable terms and conditions of such licence agreement. +; ------------------------------------------------------------ + + + + AREA v7Opps,CODE,READONLY + +; ------------------------------------------------------------ +; Interrupt enable/disable +; ------------------------------------------------------------ + + ; Could use intrinsic instead of these + + EXPORT enableInterrupts + ; void enableInterrupts(void); +enableInterrupts PROC + CPSIE i + BX lr + ENDP + + EXPORT disableInterrupts + ; void disableInterrupts(void); +disableInterrupts PROC + CPSID i + BX lr + ENDP + +; ------------------------------------------------------------ +; Cache Maintenance +; ------------------------------------------------------------ + + EXPORT enableCaches + ; void enableCaches(void); +enableCaches PROC + MRC p15, 0, r0, c1, c0, 0 ; Read System Control Register + ORR r0, r0, #(1 << 2) ; Set C bit + ORR r0, r0, #(1 << 12) ; Set I bit + MCR p15, 0, r0, c1, c0, 0 ; Write System Control Register + ISB + BX lr + ENDP + + + EXPORT disableCaches + ; void disableCaches(void) +disableCaches PROC + MRC p15, 0, r0, c1, c0, 0 ; Read System Control Register + BIC r0, r0, #(1 << 2) ; Clear C bit + BIC r0, r0, #(1 << 12) ; Clear I bit + MCR p15, 0, r0, c1, c0, 0 ; Write System Control Register + ISB + BX lr + ENDP + + + EXPORT cleanDCache + ; void cleanDCache(void); +cleanDCache PROC + PUSH {r4-r12} + + ; + ; Based on code example given in section 11.2.4 of Armv7-A/R Architecture Reference Manual (DDI 0406B) + ; + + MRC p15, 1, r0, c0, c0, 1 ; Read CLIDR + ANDS r3, r0, #0x7000000 + MOV r3, r3, LSR #23 ; Cache level value (naturally aligned) + BEQ clean_dcache_finished + MOV r10, #0 + +clean_dcache_loop1 + ADD r2, r10, r10, LSR #1 ; Work out 3xcachelevel + MOV r1, r0, LSR r2 ; bottom 3 bits are the Cache type for this level + AND r1, r1, #7 ; get those 3 bits alone + CMP r1, #2 + BLT clean_dcache_skip ; no cache or only instruction cache at this level + MCR p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register + ISB ; ISB to sync the change to the CacheSizeID reg + MRC p15, 1, r1, c0, c0, 0 ; reads current Cache Size ID register + AND r2, r1, #7 ; extract the line length field + ADD r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes) + LDR r4, =0x3FF + ANDS r4, r4, r1, LSR #3 ; R4 is the max number on the way size (right aligned) + CLZ r5, r4 ; R5 is the bit position of the way size increment + LDR r7, =0x00007FFF + ANDS r7, r7, r1, LSR #13 ; R7 is the max number of the index size (right aligned) + +clean_dcache_loop2 + MOV r9, R4 ; R9 working copy of the max way size (right aligned) + +clean_dcache_loop3 + ORR r11, r10, r9, LSL r5 ; factor in the way number and cache number into R11 + ORR r11, r11, r7, LSL r2 ; factor in the index number + MCR p15, 0, r11, c7, c10, 2 ; DCCSW - clean by set/way + SUBS r9, r9, #1 ; decrement the way number + BGE clean_dcache_loop3 + SUBS r7, r7, #1 ; decrement the index + BGE clean_dcache_loop2 + +clean_dcache_skip + ADD r10, r10, #2 ; increment the cache number + CMP r3, r10 + BGT clean_dcache_loop1 + +clean_dcache_finished + POP {r4-r12} + + BX lr + ENDP + + EXPORT cleanInvalidateDCache + ; void cleanInvalidateDCache(void); +cleanInvalidateDCache PROC + PUSH {r4-r12} + + ; + ; Based on code example given in section 11.2.4 of Armv7-A/R Architecture Reference Manual (DDI 0406B) + ; + + MRC p15, 1, r0, c0, c0, 1 ; Read CLIDR + ANDS r3, r0, #0x7000000 + MOV r3, r3, LSR #23 ; Cache level value (naturally aligned) + BEQ clean_invalidate_dcache_finished + MOV r10, #0 + +clean_invalidate_dcache_loop1 + ADD r2, r10, r10, LSR #1 ; Work out 3xcachelevel + MOV r1, r0, LSR r2 ; bottom 3 bits are the Cache type for this level + AND r1, r1, #7 ; get those 3 bits alone + CMP r1, #2 + BLT clean_invalidate_dcache_skip ; no cache or only instruction cache at this level + MCR p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register + ISB ; ISB to sync the change to the CacheSizeID reg + MRC p15, 1, r1, c0, c0, 0 ; reads current Cache Size ID register + AND r2, r1, #7 ; extract the line length field + ADD r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes) + LDR r4, =0x3FF + ANDS r4, r4, r1, LSR #3 ; R4 is the max number on the way size (right aligned) + CLZ r5, r4 ; R5 is the bit position of the way size increment + LDR r7, =0x00007FFF + ANDS r7, r7, r1, LSR #13 ; R7 is the max number of the index size (right aligned) + +clean_invalidate_dcache_loop2 + MOV r9, R4 ; R9 working copy of the max way size (right aligned) + +clean_invalidate_dcache_loop3 + ORR r11, r10, r9, LSL r5 ; factor in the way number and cache number into R11 + ORR r11, r11, r7, LSL r2 ; factor in the index number + MCR p15, 0, r11, c7, c14, 2 ; DCCISW - clean and invalidate by set/way + SUBS r9, r9, #1 ; decrement the way number + BGE clean_invalidate_dcache_loop3 + SUBS r7, r7, #1 ; decrement the index + BGE clean_invalidate_dcache_loop2 + +clean_invalidate_dcache_skip + ADD r10, r10, #2 ; increment the cache number + CMP r3, r10 + BGT clean_invalidate_dcache_loop1 + +clean_invalidate_dcache_finished + POP {r4-r12} + + BX lr + ENDP + + + EXPORT invalidateCaches + ; void invalidateCaches(void); +invalidateCaches PROC + PUSH {r4-r12} + + ; + ; Based on code example given in section B2.2.4/11.2.4 of Armv7-A/R Architecture Reference Manual (DDI 0406B) + ; + + MOV r0, #0 + MCR p15, 0, r0, c7, c5, 0 ; ICIALLU - Invalidate entire I Cache, and flushes branch target cache + + MRC p15, 1, r0, c0, c0, 1 ; Read CLIDR + ANDS r3, r0, #0x7000000 + MOV r3, r3, LSR #23 ; Cache level value (naturally aligned) + BEQ invalidate_caches_finished + MOV r10, #0 + +invalidate_caches_loop1 + ADD r2, r10, r10, LSR #1 ; Work out 3xcachelevel + MOV r1, r0, LSR r2 ; bottom 3 bits are the Cache type for this level + AND r1, r1, #7 ; get those 3 bits alone + CMP r1, #2 + BLT invalidate_caches_skip ; no cache or only instruction cache at this level + MCR p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register + ISB ; ISB to sync the change to the CacheSizeID reg + MRC p15, 1, r1, c0, c0, 0 ; reads current Cache Size ID register + AND r2, r1, #7 ; extract the line length field + ADD r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes) + LDR r4, =0x3FF + ANDS r4, r4, r1, LSR #3 ; R4 is the max number on the way size (right aligned) + CLZ r5, r4 ; R5 is the bit position of the way size increment + LDR r7, =0x00007FFF + ANDS r7, r7, r1, LSR #13 ; R7 is the max number of the index size (right aligned) + +invalidate_caches_loop2 + MOV r9, R4 ; R9 working copy of the max way size (right aligned) + +invalidate_caches_loop3 + ORR r11, r10, r9, LSL r5 ; factor in the way number and cache number into R11 + ORR r11, r11, r7, LSL r2 ; factor in the index number + MCR p15, 0, r11, c7, c6, 2 ; DCISW - invalidate by set/way + SUBS r9, r9, #1 ; decrement the way number + BGE invalidate_caches_loop3 + SUBS r7, r7, #1 ; decrement the index + BGE invalidate_caches_loop2 + +invalidate_caches_skip + ADD r10, r10, #2 ; increment the cache number + CMP r3, r10 + BGT invalidate_caches_loop1 + +invalidate_caches_finished + POP {r4-r12} + BX lr + ENDP + + + EXPORT invalidateCaches_IS + ; void invalidateCaches_IS(void); +invalidateCaches_IS PROC + PUSH {r4-r12} + + MOV r0, #0 + MCR p15, 0, r0, c7, c1, 0 ; ICIALLUIS - Invalidate entire I Cache inner shareable + + MRC p15, 1, r0, c0, c0, 1 ; Read CLIDR + ANDS r3, r0, #0x7000000 + MOV r3, r3, LSR #23 ; Cache level value (naturally aligned) + BEQ invalidate_caches_is_finished + MOV r10, #0 + +invalidate_caches_is_loop1 + ADD r2, r10, r10, LSR #1 ; Work out 3xcachelevel + MOV r1, r0, LSR r2 ; bottom 3 bits are the Cache type for this level + AND r1, r1, #7 ; get those 3 bits alone + CMP r1, #2 + BLT invalidate_caches_is_skip ; no cache or only instruction cache at this level + MCR p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register + ISB ; ISB to sync the change to the CacheSizeID reg + MRC p15, 1, r1, c0, c0, 0 ; reads current Cache Size ID register + AND r2, r1, #7 ; extract the line length field + ADD r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes) + LDR r4, =0x3FF + ANDS r4, r4, r1, LSR #3 ; R4 is the max number on the way size (right aligned) + CLZ r5, r4 ; R5 is the bit position of the way size increment + LDR r7, =0x00007FFF + ANDS r7, r7, r1, LSR #13 ; R7 is the max number of the index size (right aligned) + +invalidate_caches_is_loop2 + MOV r9, R4 ; R9 working copy of the max way size (right aligned) + +invalidate_caches_is_loop3 + ORR r11, r10, r9, LSL r5 ; factor in the way number and cache number into R11 + ORR r11, r11, r7, LSL r2 ; factor in the index number + MCR p15, 0, r11, c7, c6, 2 ; DCISW - clean by set/way + SUBS r9, r9, #1 ; decrement the way number + BGE invalidate_caches_is_loop3 + SUBS r7, r7, #1 ; decrement the index + BGE invalidate_caches_is_loop2 + +invalidate_caches_is_skip + ADD r10, r10, #2 ; increment the cache number + CMP r3, r10 + BGT invalidate_caches_is_loop1 + +invalidate_caches_is_finished + POP {r4-r12} + BX lr + ENDP + +; ------------------------------------------------------------ +; TLB +; ------------------------------------------------------------ + + EXPORT invalidateUnifiedTLB + ; void invalidateUnifiedTLB(void); +invalidateUnifiedTLB PROC + MOV r0, #0 + MCR p15, 0, r0, c8, c7, 0 ; TLBIALL - Invalidate entire unified TLB + BX lr + ENDP + + EXPORT invalidateUnifiedTLB_IS + ; void invalidateUnifiedTLB_IS(void); +invalidateUnifiedTLB_IS PROC + MOV r0, #1 + MCR p15, 0, r0, c8, c3, 0 ; TLBIALLIS - Invalidate entire unified TLB Inner Shareable + BX lr + ENDP + +; ------------------------------------------------------------ +; Branch Prediction +; ------------------------------------------------------------ + + EXPORT flushBranchTargetCache + ; void flushBranchTargetCache(void) +flushBranchTargetCache PROC + MOV r0, #0 + MCR p15, 0, r0, c7, c5, 6 ; BPIALL - Invalidate entire branch predictor array + BX lr + ENDP + + EXPORT flushBranchTargetCache_IS + ; void flushBranchTargetCache_IS(void) +flushBranchTargetCache_IS PROC + MOV r0, #0 + MCR p15, 0, r0, c7, c1, 6 ; BPIALLIS - Invalidate entire branch predictor array Inner Shareable + BX lr + ENDP + +; ------------------------------------------------------------ +; High Vecs +; ------------------------------------------------------------ + + EXPORT enableHighVecs + ; void enableHighVecs(void); +enableHighVecs PROC + MRC p15, 0, r0, c1, c0, 0 ; Read Control Register + ORR r0, r0, #(1 << 13) ; Set the V bit (bit 13) + MCR p15, 0, r0, c1, c0, 0 ; Write Control Register + ISB + BX lr + ENDP + + EXPORT disableHighVecs + ; void disable_highvecs(void); +disableHighVecs PROC + MRC p15, 0, r0, c1, c0, 0 ; Read Control Register + BIC r0, r0, #(1 << 13) ; Clear the V bit (bit 13) + MCR p15, 0, r0, c1, c0, 0 ; Write Control Register + ISB + BX lr + ENDP + +; ------------------------------------------------------------ +; Context ID +; ------------------------------------------------------------ + + EXPORT getContextID + ; uint32_t getContextIDd(void); +getContextID PROC + MRC p15, 0, r0, c13, c0, 1 ; Read Context ID Register + BX lr + ENDP + + EXPORT setContextID + ; void setContextID(uint32_t); +setContextID PROC + MCR p15, 0, r0, c13, c0, 1 ; Write Context ID Register + BX lr + ENDP + +; ------------------------------------------------------------ +; ID registers +; ------------------------------------------------------------ + + EXPORT getMIDR + ; uint32_t getMIDR(void); +getMIDR PROC + MRC p15, 0, r0, c0, c0, 0 ; Read Main ID Register (MIDR) + BX lr + ENDP + + EXPORT getMPIDR + ; uint32_t getMPIDR(void); +getMPIDR PROC + MRC p15, 0, r0, c0 ,c0, 5; Read Multiprocessor ID register (MPIDR) + BX lr + ENDP + +; ------------------------------------------------------------ +; CP15 SMP related +; ------------------------------------------------------------ + + EXPORT getBaseAddr + ; uint32_t getBaseAddr(void) + ; Returns the value CBAR (base address of the private peripheral memory space) +getBaseAddr PROC + MRC p15, 4, r0, c15, c0, 0 ; Read peripheral base address + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT getCPUID + ; uint32_t getCPUID(void) + ; Returns the CPU ID (0 to 3) of the CPU executed on +getCPUID PROC + MRC p15, 0, r0, c0, c0, 5 ; Read CPU ID register + AND r0, r0, #0x03 ; Mask off, leaving the CPU ID field + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT goToSleep + ; void goToSleep(void) +goToSleep PROC + DSB ; Clear all pending data accesses + WFI ; Go into standby + B goToSleep ; Catch in case of rogue events + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT joinSMP + ; void joinSMP(void) + ; Sets the ACTRL.SMP bit +joinSMP PROC + + ; SMP status is controlled by bit 6 of the CP15 Aux Ctrl Reg + + MRC p15, 0, r0, c1, c0, 1 ; Read ACTLR + MOV r1, r0 + ORR r0, r0, #0x040 ; Set bit 6 + CMP r0, r1 + MCRNE p15, 0, r0, c1, c0, 1 ; Write ACTLR + ISB + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT leaveSMP + ; void leaveSMP(void) + ; Clear the ACTRL.SMP bit +leaveSMP PROC + + ; SMP status is controlled by bit 6 of the CP15 Aux Ctrl Reg + + MRC p15, 0, r0, c1, c0, 1 ; Read ACTLR + BIC r0, r0, #0x040 ; Clear bit 6 + MCR p15, 0, r0, c1, c0, 1 ; Write ACTLR + ISB + + BX lr + ENDP + + END + +; ------------------------------------------------------------ +; End of v7.s +; ------------------------------------------------------------ diff --git a/ports_smp/cortex_a7_smp/ac5/example_build/tx/.cproject b/ports_smp/cortex_a7_smp/ac5/example_build/tx/.cproject new file mode 100644 index 00000000..e0007b68 --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/example_build/tx/.cproject @@ -0,0 +1,202 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/cortex_a7_smp/ac5/example_build/tx/.project b/ports_smp/cortex_a7_smp/ac5/example_build/tx/.project new file mode 100644 index 00000000..10681969 --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/example_build/tx/.project @@ -0,0 +1,48 @@ + + + tx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + inc_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_smp/inc + + + inc_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/inc + + + src_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_smp/src + + + src_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/src + + + diff --git a/ports_smp/cortex_a7_smp/ac5/example_build/tx/.settings/language.settings.xml b/ports_smp/cortex_a7_smp/ac5/example_build/tx/.settings/language.settings.xml new file mode 100644 index 00000000..6a1b50ae --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/example_build/tx/.settings/language.settings.xml @@ -0,0 +1,48 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/cortex_a7_smp/ac5/inc/tx_port.h b/ports_smp/cortex_a7_smp/ac5/inc/tx_port.h new file mode 100644 index 00000000..8e39e642 --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/inc/tx_port.h @@ -0,0 +1,406 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h SMP/Cortex-A7/AC5 */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/************* Define ThreadX SMP constants. *************/ + +/* Define the ThreadX SMP maximum number of cores. */ + +#ifndef TX_THREAD_SMP_MAX_CORES +#define TX_THREAD_SMP_MAX_CORES 2 +#endif + + +/* Define the ThreadX SMP core mask. */ + +#ifndef TX_THREAD_SMP_CORE_MASK +#define TX_THREAD_SMP_CORE_MASK 0x3 /* Where bit 0 represents Core 0, bit 1 represents Core 1, etc. */ +#endif + + +/* Define INLINE_DECLARE to whitespace for ARM compiler. */ + +#define INLINE_DECLARE + + +/* Define ThreadX SMP initialization macro. */ + +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION + + +/* Define ThreadX SMP pre-scheduler initialization. */ + +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION + + +/* Enable the inter-core interrupt logic. */ + +#define TX_THREAD_SMP_INTER_CORE_INTERRUPT + + +/* Determine if there is customer-specific wakeup logic needed. */ + +#ifdef TX_THREAD_SMP_WAKEUP_LOGIC + +/* Include customer-specific wakeup code. */ + +#include "tx_thread_smp_core_wakeup.h" +#else + +#ifdef TX_THREAD_SMP_DEFAULT_WAKEUP_LOGIC + +/* Default wakeup code. */ +#define TX_THREAD_SMP_WAKEUP_LOGIC +#define TX_THREAD_SMP_WAKEUP(i) _tx_thread_smp_core_preempt(i) +#endif +#endif + + +/* Ensure that the in-line resume/suspend define is not allowed. */ + +#ifdef TX_INLINE_THREAD_RESUME_SUSPEND +#undef TX_INLINE_THREAD_RESUME_SUSPEND +#endif + + +/************* End ThreadX SMP constants. *************/ + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE _tx_thread_smp_time_get() +#endif +#else +#ifndef TX_TRACE_TIME_SOURCE +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#ifndef __thumb + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + b = (ULONG) __clz((unsigned int) m); \ + b = 31 - b; +#endif +#endif + + +/************* Define ThreadX SMP data types and function prototypes. *************/ + +struct TX_THREAD_STRUCT; + + +/* Define the ThreadX SMP protection structure. */ + +typedef struct TX_THREAD_SMP_PROTECT_STRUCT +{ + ULONG tx_thread_smp_protect_in_force; + struct TX_THREAD_STRUCT * + tx_thread_smp_protect_thread; + ULONG tx_thread_smp_protect_core; + ULONG tx_thread_smp_protect_count; + + /* Implementation specific information follows. */ + + ULONG tx_thread_smp_protect_get_caller; + ULONG tx_thread_smp_protect_sr; + ULONG tx_thread_smp_protect_release_caller; +} TX_THREAD_SMP_PROTECT; + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_smp_protect(); +#define TX_RESTORE _tx_thread_smp_unprotect(interrupt_save); + + +/************* End ThreadX SMP data type and function prototype definitions. *************/ + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define VFP extension for the Cortex-A7. Each is assumed to be called in the context of the executing + thread. */ + +void tx_thread_vfp_enable(void); +void tx_thread_vfp_disable(void); + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Cortex-A7/AC5 Version 6.0.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + + + diff --git a/ports_smp/cortex_a7_smp/ac5/readme_threadx.txt b/ports_smp/cortex_a7_smp/ac5/readme_threadx.txt new file mode 100644 index 00000000..9044e562 --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/readme_threadx.txt @@ -0,0 +1,361 @@ + Microsoft's Azure RTOS ThreadX SMP for Cortex-A7 + + Thumb & 32-bit Mode + + Using the ARM Compiler 5 & DS + +1. Import the ThreadX Projects + +In order to build the ThreadX SMP library and the ThreadX SMP demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +into your DS workspace. + + +2. Building the ThreadX SMP run-time Library + +Building the ThreadX SMP library is easy; simply select the Eclipse project file +"tx" and then select the build button. You should now observe the compilation +and assembly of the ThreadX SMP library. This project build produces the ThreadX SMP +library file tx.a. + + +3. Demonstration System + +The ThreadX SMP demonstration is designed to execute under the DS debugger on the +VE_Cortex-A7x4 Bare Metal simulator. + +Building the demonstration is easy; simply open the workspace file, select the +sample_threadx project, and select the build button. Next, expand the demo ThreadX +project folder in the Project Explorer window, right-click on the 'sample_threadx.launch' +file, click 'Debug As', and then click 'sample_threadx' from the submenu. This will cause the +debugger to load the sample_threadx.axf ELF file and run to main. You are now ready +to execute the ThreadX demonstration. + + +4. System Initialization + +The entry point in ThreadX for the Cortex-A7 using AC5 tools is at label +Reset_Handler in startup.s. After the basic core initialization is complete, +control will transfer to __main, which is where all static and global pre-set +C variable initialization processing takes place. + +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. By default, the vector area is defined to be located in the Init area, +which is defined at the top of tx_initialize_low_level.s. This area is typically +located at 0. In situations where this is impossible, the vectors at the beginning +of the Init area should be copied to address 0. + +This is also where initialization of a periodic timer interrupt source +should take place. + +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input +parameter to your application definition function, tx_application_define. + + +5. Register Usage and Stack Frames + +The AC5 compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread +is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 CPSR CPSR + 0x08 r0 (a1) r4 (v1) + 0x0C r1 (a2) r5 (v2) + 0x10 r2 (a3) r6 (v3) + 0x14 r3 (a4) r7 (v4) + 0x18 r4 (v1) r8 (v5) + 0x1C r5 (v2) r9 (v6) + 0x20 r6 (v3) r10 (v7) + 0x24 r7 (v4) r11 (fp) + 0x28 r8 (v5) r14 (lr) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) + 0x3C r14 (lr) + 0x40 PC + + +6. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the build_threadx.bat file to +remove the -g option and enable all compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-A7 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +7.1 Vector Area + +The Cortex-A7 vectors start at address zero. The demonstration system startup +Init area contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. + + +7.2 IRQ ISRs + +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested +IRQ interrupts. The following sub-sections define the IRQ capabilities. + + +7.2.1 Standard IRQ ISRs + +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +is the default IRQ handler defined in tx_initialize_low_level.s: + + EXPORT __tx_irq_handler + EXPORT __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save ; Jump to the context save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Application ISR call(s) go here! */ +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.2 Vectored IRQ ISRs + +The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified +by the particular implementation. The following is an example IRQ handler defined in +tx_initialize_low_level.s: + + EXPORT __tx_irq_example_handler +__tx_irq_example_handler +; +; /* Call context save to save system context. */ + + STMDB sp!, {r0-r3} ; Save some scratch registers + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers + BL _tx_thread_vectored_context_save ; Call the vectored IRQ context save +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Application ISR call goes here! */ +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.2.3 Nested IRQ Support + +By default, nested IRQ interrupt support is not enabled. To enable nested +IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING +defined. With this defined, two new IRQ interrupt management services are +available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. +These function should be called between the IRQ context save and restore +calls. + +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +by switching from IRQ mode to SYS mode and enabling IRQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested IRQ interrupts are no longer required, +calling the _tx_thread_irq_nesting_end service disables nesting by disabling +IRQ interrupts and switching back to IRQ mode in preparation for the IRQ +context restore service. + +The following is an example of enabling IRQ nested interrupts in a standard +IRQ handler: + + EXPORT __tx_irq_handler + EXPORT __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* Enable nested IRQ interrupts. NOTE: Since this service returns +; with IRQ interrupts enabled, all IRQ interrupt sources must be +; cleared prior to calling this service. */ + BL _tx_thread_irq_nesting_start +; +; /* Application ISR call(s) go here! */ +; +; /* Disable nested IRQ interrupts. The mode is switched back to +; IRQ mode and IRQ interrupts are disable upon return. */ + BL _tx_thread_irq_nesting_end +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.3 FIQ Interrupts + +By default, Cortex-A7 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made +from default FIQ ISRs, which is located in tx_initialize_low_level.s. + + +7.3.1 Managed FIQ Interrupts + +Full ThreadX management of FIQ interrupts is provided if the ThreadX sources +are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built +this way, the FIQ interrupt handlers are very similar to the IRQ interrupt +handlers defined previously. The following is default FIQ handler +defined in tx_initialize_low_level.s: + + + EXPORT __tx_fiq_handler + EXPORT __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Application FIQ handlers can be called here! */ +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +7.3.1.1 Nested FIQ Support + +By default, nested FIQ interrupt support is not enabled. To enable nested +FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING +defined. With this defined, two new FIQ interrupt management services are +available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. +These function should be called between the FIQ context save and restore +calls. + +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +by switching from FIQ mode to SYS mode and enabling FIQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested FIQ interrupts are no longer required, +calling the _tx_thread_fiq_nesting_end service disables nesting by disabling +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +context restore service. + +The following is an example of enabling FIQ nested interrupts in the +typical FIQ handler: + + + EXPORT __tx_fiq_handler + EXPORT __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Enable nested FIQ interrupts. NOTE: Since this service returns +; with FIQ interrupts enabled, all FIQ interrupt sources must be +; cleared prior to calling this service. */ + BL _tx_thread_fiq_nesting_start +; +; /* Application FIQ handlers can be called here! */ +; +; /* Disable nested FIQ interrupts. The mode is switched back to +; FIQ mode and FIQ interrupts are disable upon return. */ + BL _tx_thread_fiq_nesting_end +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +8. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional. However, all other +ThreadX services are operational without a periodic timer source. + +To add the timer interrupt processing, simply make a call to +_tx_timer_interrupt in the IRQ processing. An example of this can be +found in the file tx_initialize_low_level.s in the Integrator sub-directories. + + +9. Thumb/Cortex-A7 Mixed Mode + +By default, ThreadX is setup for running in Cortex-A7 32-bit mode. This is +also true for the demonstration system. It is possible to build any +ThreadX file and/or the application in Thumb mode. If any Thumb code +is used the entire ThreadX source- both C and assembly - should be built +with the "-apcs /interwork" option. + + +10. VFP Support + +By default, VFP support is disabled for each thread. If saving the context of the VFP registers +is needed, the following API call must be made from the context of the application thread - before +the VFP usage: + +void tx_thread_vfp_enable(void); + +After this API is called in the application, VFP registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the VFP registers +to be saved/restored. + +To disable VFP register context saving, simply call the following API: + +void tx_thread_vfp_disable(void); + + +11. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A7 using AC5 tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_context_restore.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_context_restore.s new file mode 100644 index 00000000..1bdf5d08 --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_context_restore.s @@ -0,0 +1,369 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +;/* Include macros for modifying the wait list. */ +#include "tx_thread_smp_protection_wait_list_macros.h" + + IF :DEF:TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts +IRQ_MODE EQU 0xD2 ; IRQ mode +SVC_MODE EQU 0xD3 ; SVC mode + ELSE +DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts +IRQ_MODE EQU 0x92 ; IRQ mode +SVC_MODE EQU 0x93 ; SVC mode + ENDIF +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_execute_ptr + IMPORT _tx_timer_time_slice + IMPORT _tx_thread_schedule + IMPORT _tx_thread_preempt_disable + IMPORT _tx_timer_interrupt_active + IMPORT _tx_thread_smp_protection + IMPORT _tx_thread_smp_protect_wait_counts + IMPORT _tx_thread_smp_protect_wait_list + IMPORT _tx_thread_smp_protect_wait_list_lock_protect_in_force + IMPORT _tx_thread_smp_protect_wait_list_tail + IMPORT _tx_thread_smp_protect_wait_list_size + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_exit + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore SMP/Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + EXPORT _tx_thread_context_restore +_tx_thread_context_restore +; +; /* Lockout interrupts. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + BL _tx_execution_isr_exit ; Call the ISR exit function + ENDIF + +; /* Pickup the CPU ID. */ +; + MRC p15, 0, r10, c0, c0, 5 ; Read CPU ID register + AND r10, r10, #0x03 ; Mask off, leaving the CPU ID field + LSL r12, r10, #2 ; Build offset to array indexes +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state[core]) +; { +; + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + ADD r3, r3, r12 ; Build array offset + LDR r2, [r3, #0] ; Pickup system state + SUB r2, r2, #1 ; Decrement the counter + STR r2, [r3, #0] ; Store the counter + CMP r2, #0 ; Was this the first interrupt? + BEQ __tx_thread_not_nested_restore ; If so, not a nested restore +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +__tx_thread_not_nested_restore +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr[core]) && (_tx_thread_current_ptr[core] == _tx_thread_execute_ptr[core]) +; || (_tx_thread_preempt_disable)) +; { +; + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + ADD r1, r1, r12 ; Build index to this core's current thread ptr + LDR r0, [r1, #0] ; Pickup actual current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_restore ; Yes, idle system was interrupted +; + LDR r3, =_tx_thread_smp_protection ; Get address of protection structure + LDR r2, [r3, #8] ; Pickup owning core + CMP r2, r10 ; Is the owning core the same as the protected core? + BNE __tx_thread_skip_preempt_check ; No, skip the preempt disable check since this is only valid for the owning core + + LDR r3, =_tx_thread_preempt_disable ; Pickup preempt disable address + LDR r2, [r3, #0] ; Pickup actual preempt disable flag + CMP r2, #0 ; Is it set? + BNE __tx_thread_no_preempt_restore ; Yes, don't preempt this thread +__tx_thread_skip_preempt_check + + LDR r3, =_tx_thread_execute_ptr ; Pickup address of execute thread ptr + ADD r3, r3, r12 ; Build index to this core's execute thread ptr + LDR r2, [r3, #0] ; Pickup actual execute thread pointer + CMP r0, r2 ; Is the same thread highest priority? + BNE __tx_thread_preempt_restore ; No, preemption needs to happen +; +; +__tx_thread_no_preempt_restore +; +; /* Restore interrupted thread or ISR. */ +; +; /* Pickup the saved stack pointer. */ +; tmp_ptr = _tx_thread_current_ptr[core] -> tx_thread_stack_ptr; +; +; /* Recover the saved context and return to the point of interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +; else +; { +__tx_thread_preempt_restore +; +; /* Was the thread being preempted waiting for the lock? */ +; if (_tx_thread_smp_protect_wait_counts[this_core] != 0) +; { +; + LDR r1, =_tx_thread_smp_protect_wait_counts ; Load waiting count list + LDR r2, [r1, r10, LSL #2] ; Load waiting value for this core + CMP r2, #0 + BEQ _nobody_waiting_for_lock ; Is the core waiting for the lock? +; +; /* Do we not have the lock? This means the ISR never got the inter-core lock. */ +; if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core) +; { +; + LDR r1, =_tx_thread_smp_protection ; Load address of protection structure + LDR r2, [r1, #8] ; Pickup the owning core + CMP r10, r2 ; Compare our core to the owning core + BEQ _this_core_has_lock ; Do we have the lock? +; +; /* We don't have the lock. This core should be in the list. Remove it. */ +; _tx_thread_smp_protect_wait_list_remove(this_core); +; +macro_call0 _tx_thread_smp_protect_wait_list_remove ; Call macro to remove core from the list + B _nobody_waiting_for_lock ; Leave +; +; } +; else +; { +; /* We have the lock. This means the ISR got the inter-core lock, but +; never released it because it saw that there was someone waiting. +; Note this core is not in the list. */ +; +_this_core_has_lock +; +; /* We're no longer waiting. Note that this should be zero since this happens during thread preemption. */ +; _tx_thread_smp_protect_wait_counts[core]--; +; + LDR r1, =_tx_thread_smp_protect_wait_counts ; Load waiting count list + LDR r2, [r1, r10, LSL #2] ; Load waiting value for this core + SUB r2, r2, #1 ; Decrement waiting value. Should be zero now + STR r2, [r1, r10, LSL #2] ; Store new waiting value +; +; /* Now release the inter-core lock. */ +; +; /* Set protected core as invalid. */ +; _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF; +; + LDR r1, =_tx_thread_smp_protection ; Load address of protection structure + MOV r2, #0xFFFFFFFF ; Build invalid value + STR r2, [r1, #8] ; Mark the protected core as invalid + DMB ; Ensure that accesses to shared resource have completed +; +; /* Release protection. */ +; _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0; +; + MOV r2, #0 ; Build release protection value + STR r2, [r1, #0] ; Release the protection + DSB ISH ; To ensure update of the protection occurs before other CPUs awake +; +; /* Wake up waiting processors. Note interrupts are already enabled. */ +; + IF :DEF:TX_ENABLE_WFE + SEV ; Send event to other CPUs + ENDIF +; +; } +; } +; + +_nobody_waiting_for_lock + + LDMIA sp!, {r3, r10, r12, lr} ; Recover temporarily saved registers + MOV r1, lr ; Save lr (point of interrupt) + MOV r2, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r2 ; Enter SVC mode + STR r1, [sp, #-4]! ; Save point of interrupt + STMDB sp!, {r4-r12, lr} ; Save upper half of registers + MOV r4, r3 ; Save SPSR in r4 + MOV r2, #IRQ_MODE ; Build IRQ mode CPSR + MSR CPSR_c, r2 ; Enter IRQ mode + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOV r5, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r5 ; Enter SVC mode + STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack + + MRC p15, 0, r10, c0, c0, 5 ; Read CPU ID register + AND r10, r10, #0x03 ; Mask off, leaving the CPU ID field + LSL r12, r10, #2 ; Build offset to array indexes + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + ADD r1, r1, r12 ; Build index to current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + + IF {TARGET_FPU_VFP} = {TRUE} + LDR r2, [r0, #160] ; Pickup the VFP enabled flag + CMP r2, #0 ; Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save ; No, skip VFP IRQ save + VMRS r2, FPSCR ; Pickup the FPSCR + STR r2, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D0-D15} ; Save D0-D15 +_tx_skip_irq_vfp_save + ENDIF + + MOV r3, #1 ; Build interrupt stack type + STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR + STR sp, [r0, #8] ; Save stack pointer in thread control + ; block +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice[core]) +; { +; + LDR r3, =_tx_timer_interrupt_active ; Pickup timer interrupt active flag's address +_tx_wait_for_timer_to_finish + LDR r2, [r3, #0] ; Pickup timer interrupt active flag + CMP r2, #0 ; Is the timer interrupt active? + BNE _tx_wait_for_timer_to_finish ; If timer interrupt is active, wait until it completes + + LDR r3, =_tx_timer_time_slice ; Pickup time-slice variable address + ADD r3, r3, r12 ; Build index to core's time slice + LDR r2, [r3, #0] ; Pickup time-slice + CMP r2, #0 ; Is it active? + BEQ __tx_thread_dont_save_ts ; No, don't save it +; +; _tx_thread_current_ptr[core] -> tx_thread_time_slice = _tx_timer_time_slice[core]; +; _tx_timer_time_slice[core] = 0; +; + STR r2, [r0, #24] ; Save thread's time-slice + MOV r2, #0 ; Clear value + STR r2, [r3, #0] ; Disable global time-slice flag +; +; } +__tx_thread_dont_save_ts +; +; +; /* Clear the current task pointer. */ +; _tx_thread_current_ptr[core] = TX_NULL; +; + MOV r2, #0 ; NULL value + STR r2, [r1, #0] ; Clear current thread pointer +; +; /* Set bit indicating this thread is ready for execution. */ +; + LDR r2, [r0, #152] ; Pickup the ready bit + ORR r2, r2, #0x8000 ; Set ready bit (bit 15) + STR r2, [r0, #152] ; Make this thread ready for executing again + DMB ; Ensure that accesses to shared resource have completed +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; + B _tx_thread_schedule ; Return to scheduler +; } +; +__tx_thread_idle_system_restore +; +; /* Just return back to the scheduler! */ +; + MOV r3, #SVC_MODE ; Build SVC mode with interrupts disabled + MSR CPSR_c, r3 ; Change to SVC mode + B _tx_thread_schedule ; Return to scheduler +;} +; + END + diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_context_save.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_context_save.s new file mode 100644 index 00000000..2b547164 --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_context_save.s @@ -0,0 +1,203 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IMPORT __tx_irq_processing_return + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save SMP/Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + EXPORT _tx_thread_context_save +_tx_thread_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state[core]++) +; { +; + STMDB sp!, {r0-r3} ; Save some working registers +; +; /* Save the rest of the scratch registers on the stack and return to the +; calling ISR. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable FIQ interrupts + ENDIF +; +; /* Pickup the CPU ID. */ +; + MRC p15, 0, r10, c0, c0, 5 ; Read CPU ID register + AND r10, r10, #0x03 ; Mask off, leaving the CPU ID field + LSL r12, r10, #2 ; Build offset to array indexes +; + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + ADD r3, r3, r12 ; Build index into the system state array + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {r12, lr} ; Save ISR lr & r12 + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {r12, lr} ; Recover ISR lr & r12 + ENDIF + + B __tx_irq_processing_return ; Continue IRQ processing +; +__tx_thread_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr[core]) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + ADD r1, r1, r12 ; Build index into current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + ; scheduling loop - nothing needs saving! +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {r12, lr} ; Save ISR lr & r12 + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {r12, lr} ; Recover ISR lr & r12 + ENDIF + + B __tx_irq_processing_return ; Continue IRQ processing +; +; } +; else +; { +; +__tx_thread_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; processing. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {r12, lr} ; Save ISR lr & r12 + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {r12, lr} ; Recover ISR lr & r12 + ENDIF + + ADD sp, sp, #32 ; Recover saved registers + B __tx_irq_processing_return ; Continue IRQ processing +; +; } +;} +; + END + diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_interrupt_control.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..9d3c59ef --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_interrupt_control.s @@ -0,0 +1,102 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT +INT_MASK EQU 0xC0 ; Interrupt bit mask + ELSE +INT_MASK EQU 0x80 ; Interrupt bit mask + ENDIF +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control SMP/Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + EXPORT _tx_thread_interrupt_control +_tx_thread_interrupt_control +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r3, CPSR ; Pickup current CPSR + BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits + ORR r1, r1, r0 ; Or-in new interrupt lockout bits +; +; /* Apply the new interrupt posture. */ +; + MSR CPSR_c, r1 ; Setup new CPSR + AND r0, r3, #INT_MASK ; Return previous interrupt mask + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +;} +; + END + diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_interrupt_disable.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_interrupt_disable.s new file mode 100644 index 00000000..cb1c194a --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_interrupt_disable.s @@ -0,0 +1,95 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable SMP/Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(void) +;{ + EXPORT _tx_thread_interrupt_disable +_tx_thread_interrupt_disable +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r0, CPSR ; Pickup current CPSR +; +; /* Mask interrupts. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ + ELSE + CPSID i ; Disable IRQ + ENDIF + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +;} +; + END + diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_interrupt_restore.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_interrupt_restore.s new file mode 100644 index 00000000..6b0da839 --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_interrupt_restore.s @@ -0,0 +1,87 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore SMP/Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for restoring interrupts to the state */ +;/* returned by a previous _tx_thread_interrupt_disable call. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_restore(UINT old_posture) +;{ + EXPORT _tx_thread_interrupt_restore +_tx_thread_interrupt_restore +; +; /* Apply the new interrupt posture. */ +; + MSR CPSR_c, r0 ; Setup new CPSR + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +;} +; + END + diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_irq_nesting_end.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_irq_nesting_end.s new file mode 100644 index 00000000..9eae0030 --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_irq_nesting_end.s @@ -0,0 +1,110 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts + ELSE +DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts + ENDIF +MODE_MASK EQU 0x1F ; Mode mask +IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end SMP/Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_irq_nesting_end(VOID) +;{ + EXPORT _tx_thread_irq_nesting_end +_tx_thread_irq_nesting_end + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value + MSR CPSR_c, r0 ; Disable interrupts + LDMIA sp!, {lr, r1} ; Pickup saved lr (and r1 throw-away for + ; 8-byte alignment logic) + BIC r0, r0, #MODE_MASK ; Clear mode bits + ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR + MSR CPSR_c, r0 ; Re-enter IRQ mode + IF {INTER} = {TRUE} + BX r3 ; Return to caller + ELSE + MOV pc, r3 ; Return to caller + ENDIF +;} + END + diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_irq_nesting_start.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_irq_nesting_start.s new file mode 100644 index 00000000..47b32481 --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_irq_nesting_start.s @@ -0,0 +1,104 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +IRQ_DISABLE EQU 0x80 ; IRQ disable bit +MODE_MASK EQU 0x1F ; Mode mask +SYS_MODE_BITS EQU 0x1F ; System mode bits +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start SMP/Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_irq_nesting_start(VOID) +;{ + EXPORT _tx_thread_irq_nesting_start +_tx_thread_irq_nesting_start + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + BIC r0, r0, #MODE_MASK ; Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS ; Build system mode CPSR + MSR CPSR_c, r0 ; Enter system mode + STMDB sp!, {lr, r1} ; Push the system mode lr on the system mode stack + ; and push r1 just to keep 8-byte alignment + BIC r0, r0, #IRQ_DISABLE ; Build enable IRQ CPSR + MSR CPSR_c, r0 ; Enter system mode + IF {INTER} = {TRUE} + BX r3 ; Return to caller + ELSE + MOV pc, r3 ; Return to caller + ENDIF +;} +; + END + diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_schedule.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_schedule.s new file mode 100644 index 00000000..c7d3c22f --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_schedule.s @@ -0,0 +1,314 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IMPORT _tx_thread_execute_ptr + IMPORT _tx_thread_current_ptr + IMPORT _tx_timer_time_slice + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_thread_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule SMP/Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + EXPORT _tx_thread_schedule +_tx_thread_schedule +; +; /* Enable interrupts. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSIE if ; Enable IRQ and FIQ interrupts + ELSE + CPSIE i ; Enable IRQ interrupts + ENDIF +; +; /* Pickup the CPU ID. */ +; + MRC p15, 0, r10, c0, c0, 5 ; Read CPU ID register + AND r10, r10, #0x03 ; Mask off, leaving the CPU ID field + LSL r12, r10, #2 ; Build offset to array indexes + + LDR r1, =_tx_thread_execute_ptr ; Address of thread execute ptr + ADD r1, r1, r12 ; Build offset to execute ptr for this core +; +; /* Lockout interrupts transfer control to it. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF +; +; /* Wait for a thread to execute. */ +; do +; { +; +; + LDR r0, [r1, #0] ; Pickup next thread to execute + CMP r0, #0 ; Is it NULL? + BEQ _tx_thread_schedule ; If so, keep looking for a thread +; +; } +; while(_tx_thread_execute_ptr[core] == TX_NULL); +; +; /* Get the lock for accessing the thread's ready bit. */ +; + MOV r2, #172 ; Build offset to the lock + ADD r2, r0, r2 ; Get the address to the lock + LDREX r3, [r2] ; Pickup the lock value + CMP r3, #0 ; Check if it's available + BNE _tx_thread_schedule ; No, lock not available + MOV r3, #1 ; Build the lock set value + STREX r4, r3, [r2] ; Try to get the lock + CMP r4, #0 ; Check if we got the lock + BNE _tx_thread_schedule ; No, another core got it first + DMB ; Ensure write to lock completes +; +; /* Now make sure the thread's ready bit is set. */ +; + LDR r3, [r0, #152] ; Pickup the thread ready bit + AND r4, r3, #0x8000 ; Isolate the ready bit + CMP r4, #0 ; Is it set? + BNE _tx_thread_ready_for_execution ; Yes, schedule the thread +; +; /* The ready bit isn't set. Release the lock and jump back to the scheduler. */ +; + MOV r3, #0 ; Build clear value + STR r3, [r2] ; Release the lock + DMB ; Ensure write to lock completes + B _tx_thread_schedule ; Jump back to the scheduler +; +_tx_thread_ready_for_execution +; +; /* We have a thread to execute. */ +; +; /* Clear the ready bit and release the lock. */ +; + BIC r3, r3, #0x8000 ; Clear ready bit + STR r3, [r0, #152] ; Store it back in the thread control block + DMB + MOV r3, #0 ; Build clear value for the lock + STR r3, [r2] ; Release the lock + DMB +; +; /* Setup the current thread pointer. */ +; _tx_thread_current_ptr[core] = _tx_thread_execute_ptr[core]; +; + LDR r2, =_tx_thread_current_ptr ; Pickup address of current thread + ADD r2, r2, r12 ; Build index into the current thread array + STR r0, [r2, #0] ; Setup current thread pointer +; +; /* In the time between reading the execute pointer and assigning +; it to the current pointer, the execute pointer was changed by +; some external code. If the current pointer was still null when +; the external code checked if a core preempt was necessary, then +; it wouldn't have done it and a preemption will be missed. To +; handle this, undo some things and jump back to the scheduler so +; it can schedule the new thread. */ +; + LDR r1, [r1, #0] ; Reload the execute pointer + CMP r0, r1 ; Did it change? + BEQ _execute_pointer_did_not_change ; If not, skip handling + + MOV r1, #0 ; Build clear value + STR r1, [r2, #0] ; Clear current thread pointer + + LDR r1, [r0, #152] ; Pickup the ready bit + ORR r1, r1, #0x8000 ; Set ready bit (bit 15) + STR r1, [r0, #152] ; Make this thread ready for executing again + DMB ; Ensure that accesses to shared resource have completed + + B _tx_thread_schedule ; Jump back to the scheduler to schedule the new thread + +_execute_pointer_did_not_change +; +; /* Increment the run count for this thread. */ +; _tx_thread_current_ptr[core] -> tx_thread_run_count++; +; + LDR r2, [r0, #4] ; Pickup run counter + LDR r3, [r0, #24] ; Pickup time-slice for this thread + ADD r2, r2, #1 ; Increment thread run-counter + STR r2, [r0, #4] ; Store the new run counter +; +; /* Setup time-slice, if present. */ +; _tx_timer_time_slice[core] = _tx_thread_current_ptr[core] -> tx_thread_time_slice; +; + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + ; variable + ADD r2, r2, r12 ; Build index into the time-slice array + LDR sp, [r0, #8] ; Switch stack pointers + STR r3, [r2, #0] ; Setup time-slice +; +; /* Switch to the thread's stack. */ +; sp = _tx_thread_execute_ptr[core] -> tx_thread_stack_ptr; +; + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + MOV r5, r0 ; Save r0 + BL _tx_execution_thread_enter ; Call the thread execution enter function + MOV r0, r5 ; Restore r0 + ENDIF +; +; /* Determine if an interrupt frame or a synchronous task suspension frame +; is present. */ +; + LDMIA sp!, {r4, r5} ; Pickup the stack type and saved CPSR + CMP r4, #0 ; Check for synchronous context switch + BEQ _tx_solicited_return + MSR SPSR_cxsf, r5 ; Setup SPSR for return + IF {TARGET_FPU_VFP} = {TRUE} + LDR r1, [r0, #160] ; Pickup the VFP enabled flag + CMP r1, #0 ; Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore ; No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} ; Recover D0-D15 + VLDMIA sp!, {D16-D31} ; Recover D16-D31 + LDR r4, [sp], #4 ; Pickup FPSCR + VMSR FPSCR, r4 ; Restore FPSCR +_tx_skip_interrupt_vfp_restore + ENDIF + LDMIA sp!, {r0-r12, lr, pc}^ ; Return to point of thread interrupt + +_tx_solicited_return + IF {TARGET_FPU_VFP} = {TRUE} + MSR CPSR_cxsf, r5 ; Recover CPSR + LDR r1, [r0, #160] ; Pickup the VFP enabled flag + CMP r1, #0 ; Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore ; No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} ; Recover D8-D15 + VLDMIA sp!, {D16-D31} ; Recover D16-D31 + LDR r4, [sp], #4 ; Pickup FPSCR + VMSR FPSCR, r4 ; Restore FPSCR +_tx_skip_solicited_vfp_restore + ENDIF + MSR CPSR_cxsf, r5 ; Recover CPSR + LDMIA sp!, {r4-r11, lr} ; Return to thread synchronously + BX lr ; Return to caller +; +;} +; + + IF {TARGET_FPU_VFP} = {TRUE} + EXPORT tx_thread_vfp_enable +tx_thread_vfp_enable + MRS r2, CPSR ; Pickup the CPSR + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF + MRC p15, 0, r1, c0, c0, 5 ; Read CPU ID register + AND r1, r1, #0x03 ; Mask off, leaving the CPU ID field + LSL r1, r1, #2 ; Build offset to array indexes + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + ADD r0, r0, r1 ; Build index into the current thread array + LDR r1, [r0] ; Pickup current thread pointer + CMP r1, #0 ; Check for NULL thread pointer + BEQ __tx_no_thread_to_enable ; If NULL, skip VFP enable + MOV r0, #1 ; Build enable value + STR r0, [r1, #160] ; Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable + MSR CPSR_cxsf, r2 ; Recover CPSR + BX LR ; Return to caller + + EXPORT tx_thread_vfp_disable +tx_thread_vfp_disable + MRS r2, CPSR ; Pickup the CPSR + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF + MRC p15, 0, r1, c0, c0, 5 ; Read CPU ID register + AND r1, r1, #0x03 ; Mask off, leaving the CPU ID field + LSL r1, r1, #2 ; Build offset to array indexes + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + ADD r0, r0, r1 ; Build index into the current thread array + LDR r1, [r0] ; Pickup current thread pointer + CMP r1, #0 ; Check for NULL thread pointer + BEQ __tx_no_thread_to_disable ; If NULL, skip VFP disable + MOV r0, #0 ; Build disable value + STR r0, [r1, #160] ; Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable + MSR CPSR_cxsf, r2 ; Recover CPSR + BX LR ; Return to caller + ENDIF +; +;} +; + END + diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_core_get.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_core_get.s new file mode 100644 index 00000000..ffb99329 --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_core_get.s @@ -0,0 +1,85 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +;#define TX_THREAD_SMP_SOURCE_CODE +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" */ +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_core_get SMP/Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function gets the currently running core number and returns it.*/ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* Core ID */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ + EXPORT _tx_thread_smp_core_get +_tx_thread_smp_core_get + MRC p15, 0, r0, c0, c0, 5 ; Read CPU ID register + AND r0, r0, #0x03 ; Mask off, leaving the CPU ID field + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF + + END + diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_core_preempt.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_core_preempt.s new file mode 100644 index 00000000..c5ec198e --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_core_preempt.s @@ -0,0 +1,101 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +;#define TX_THREAD_SMP_SOURCE_CODE +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" */ +; +; + IMPORT sendSGI + + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_core_preempt SMP/Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function preempts the specified core in situations where the */ +;/* thread corresponding to this core is no longer ready or when the */ +;/* core must be used for a higher-priority thread. If the specified is */ +;/* the current core, this processing is skipped since the will give up */ +;/* control subsequently on its own. */ +;/* */ +;/* INPUT */ +;/* */ +;/* core The core to preempt */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ + EXPORT _tx_thread_smp_core_preempt +_tx_thread_smp_core_preempt + + STMDB sp!, {lr, r4} ; Save the lr and r4 register on the stack +; +; /* Place call to send inter-processor interrupt here! */ +; + DSB ; + MOV r1, #1 ; Build parameter list + LSL r1, r1, r0 ; + MOV r0, #0 ; + MOV r2, #0 ; + BL sendSGI ; Make call to send inter-processor interrupt + + LDMIA sp!, {lr, r4} ; Recover lr register and r4 + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF + + END + diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_current_state_get.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_current_state_get.s new file mode 100644 index 00000000..029e03de --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_current_state_get.s @@ -0,0 +1,103 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +;#define TX_THREAD_SMP_SOURCE_CODE +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" */ +; +; + IMPORT _tx_thread_system_state + + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_current_state_get SMP/Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is gets the current state of the calling core. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ + EXPORT _tx_thread_smp_current_state_get +_tx_thread_smp_current_state_get + + MRS r3, CPSR ; Pickup current CPSR + + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF +; +; /* Pickup the CPU ID. */ +; + MRC p15, 0, r2, c0, c0, 5 ; Read CPU ID register + AND r2, r2, #0x03 ; Mask off, leaving the CPU ID field + LSL r2, r2, #2 ; Build offset to array indexes + + LDR r1, =_tx_thread_system_state ; Pickup start of the current state array + ADD r1, r1, r2 ; Build index into the current state array + LDR r0, [r1] ; Pickup state for this core + MSR CPSR_c, r3 ; Restore CPSR + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF + + END + diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_current_thread_get.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_current_thread_get.s new file mode 100644 index 00000000..105b465a --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_current_thread_get.s @@ -0,0 +1,103 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +;#define TX_THREAD_SMP_SOURCE_CODE +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" */ +; +; + IMPORT _tx_thread_current_ptr + + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_current_thread_get SMP/Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is gets the current thread of the calling core. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ + EXPORT _tx_thread_smp_current_thread_get +_tx_thread_smp_current_thread_get + + MRS r3, CPSR ; Pickup current CPSR + + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF +; +; /* Pickup the CPU ID. */ +; + MRC p15, 0, r2, c0, c0, 5 ; Read CPU ID register + AND r2, r2, #0x03 ; Mask off, leaving the CPU ID field + LSL r2, r2, #2 ; Build offset to array indexes + + LDR r1, =_tx_thread_current_ptr ; Pickup start of the current thread array + ADD r1, r1, r2 ; Build index into the current thread array + LDR r0, [r1] ; Pickup current thread for this core + MSR CPSR_c, r3 ; Restore CPSR + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF + + END + diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_initialize_wait.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_initialize_wait.s new file mode 100644 index 00000000..fcd2a397 --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_initialize_wait.s @@ -0,0 +1,140 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +;#define TX_THREAD_SMP_SOURCE_CODE +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" */ +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_smp_release_cores_flag + IMPORT _tx_thread_schedule + + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_initialize_wait SMP/Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is the place where additional cores wait until */ +;/* initialization is complete before they enter the thread scheduling */ +;/* loop. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Hardware */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ + EXPORT _tx_thread_smp_initialize_wait +_tx_thread_smp_initialize_wait + +; /* Lockout interrupts. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF +; +; /* Pickup the CPU ID. */ +; + MRC p15, 0, r10, c0, c0, 5 ; Read CPU ID register + AND r10, r10, #0x03 ; Mask off, leaving the CPU ID field + LSL r10, r10, #2 ; Build offset to array indexes +; +; /* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release +; flag. */ +; + LDR r3, =_tx_thread_system_state ; Build address of system state variable + ADD r3, r3, r10 ; Build index into the system state array + LDR r2, =0xF0F0F0F0 ; Build TX_INITIALIZE_IN_PROGRESS flag +wait_for_initialize + LDR r1, [r3] ; Pickup system state + CMP r1, r2 ; Has initialization completed? + BNE wait_for_initialize ; If different, wait here! +; +; /* Pickup the release cores flag. */ +; + LDR r2, =_tx_thread_smp_release_cores_flag ; Build address of release cores flag + +wait_for_release + LDR r3, [r2] ; Pickup the flag + CMP r3, #0 ; Is it set? + BEQ wait_for_release ; Wait for the flag to be set +; +; /* Core 0 has released this core. */ +; +; /* Clear this core's system state variable. */ +; + LDR r3, =_tx_thread_system_state ; Build address of system state variable + ADD r3, r3, r10 ; Build index into the system state array + MOV r0, #0 ; Build clear value + STR r0, [r3] ; Clear this core's entry in the system state array +; +; /* Now wait for core 0 to finish it's initialization. */ +; + LDR r3, =_tx_thread_system_state ; Build address of system state variable of logical 0 + +core_0_wait_loop + LDR r2, [r3] ; Pickup system state for core 0 + CMP r2, #0 ; Is it 0? + BNE core_0_wait_loop ; No, keep waiting for core 0 to finish its initialization +; +; /* Initialize is complete, enter the scheduling loop! */ +; + B _tx_thread_schedule ; Enter scheduling loop for this core! + + END + diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_low_level_initialize.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_low_level_initialize.s new file mode 100644 index 00000000..482b6655 --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_low_level_initialize.s @@ -0,0 +1,84 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +;#define TX_THREAD_SMP_SOURCE_CODE +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" */ +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_low_level_initialize SMP/Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function performs low-level initialization of the booting */ +;/* core. */ +;/* */ +;/* INPUT */ +;/* */ +;/* number_of_cores Number of cores */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_high_level ThreadX high-level init */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ + EXPORT _tx_thread_smp_low_level_initialize +_tx_thread_smp_low_level_initialize + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF + + END + diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_protect.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_protect.s new file mode 100644 index 00000000..5f8ef018 --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_protect.s @@ -0,0 +1,370 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +;#define TX_THREAD_SMP_SOURCE_CODE +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" */ + +;/* Include macros for modifying the wait list. */ +#include "tx_thread_smp_protection_wait_list_macros.h" + + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_smp_protection + IMPORT _tx_thread_smp_protect_wait_counts + IMPORT _tx_thread_smp_protect_wait_list + IMPORT _tx_thread_smp_protect_wait_list_lock_protect_in_force + IMPORT _tx_thread_smp_protect_wait_list_head + IMPORT _tx_thread_smp_protect_wait_list_tail + IMPORT _tx_thread_smp_protect_wait_list_size + + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_protect SMP/Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function gets protection for running inside the ThreadX */ +;/* source. This is acomplished by a combination of a test-and-set */ +;/* flag and periodically disabling interrupts. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* Previous Status Register */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ + EXPORT _tx_thread_smp_protect +_tx_thread_smp_protect +;VOID _tx_thread_smp_protect(VOID) +;{ +; + PUSH {r4-r6} ; Save registers we'll be using +; +; /* Disable interrupts so we don't get preempted. */ +; + MRS r0, CPSR ; Pickup current CPSR + + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF +; +; /* Do we already have protection? */ +; if (this_core == _tx_thread_smp_protection.tx_thread_smp_protect_core) +; { +; + MRC p15, 0, r1, c0, c0, 5 ; Read CPU ID register + AND r1, r1, #0x03 ; Mask off, leaving the CPU ID field + LDR r2, =_tx_thread_smp_protection ; Build address to protection structure + LDR r3, [r2, #8] ; Pickup the owning core + CMP r1, r3 ; Is it not this core? + BNE _protection_not_owned ; No, the protection is not already owned +; +; /* We already have protection. */ +; +; /* Increment the protection count. */ +; _tx_thread_smp_protection.tx_thread_smp_protect_count++; +; + LDR r3, [r2, #12] ; Pickup ownership count + ADD r3, r3, #1 ; Increment ownership count + STR r3, [r2, #12] ; Store ownership count + DMB + + B _return + +_protection_not_owned +; +; /* Is the lock available? */ +; if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0) +; { +; + LDREX r3, [r2, #0] ; Pickup the protection flag + CMP r3, #0 + BNE _start_waiting ; No, protection not available +; +; /* Is the list empty? */ +; if (_tx_thread_smp_protect_wait_list_head == _tx_thread_smp_protect_wait_list_tail) +; { +; + LDR r3, =_tx_thread_smp_protect_wait_list_head + LDR r3, [r3] + LDR r4, =_tx_thread_smp_protect_wait_list_tail + LDR r4, [r4] + CMP r3, r4 + BNE _list_not_empty +; +; /* Try to get the lock. */ +; if (write_exclusive(&_tx_thread_smp_protection.tx_thread_smp_protect_in_force, 1) == SUCCESS) +; { +; + MOV r3, #1 ; Build lock value + STREX r4, r3, [r2, #0] ; Attempt to get the protection + CMP r4, #0 + BNE _start_waiting ; Did it fail? +; +; /* We got the lock! */ +; _tx_thread_smp_protect_lock_got(); +; + DMB ; Ensure write to protection finishes +macro_call0 _tx_thread_smp_protect_lock_got ; Call the lock got function + + B _return + +_list_not_empty +; +; /* Are we at the front of the list? */ +; if (this_core == _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head]) +; { +; + LDR r3, =_tx_thread_smp_protect_wait_list_head ; Get the address of the head + LDR r3, [r3] ; Get the value of the head + LDR r4, =_tx_thread_smp_protect_wait_list ; Get the address of the list + LDR r4, [r4, r3, LSL #2] ; Get the value at the head index + + CMP r1, r4 + BNE _start_waiting +; +; /* Is the lock still available? */ +; if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0) +; { +; + LDR r3, [r2, #0] ; Pickup the protection flag + CMP r3, #0 + BNE _start_waiting ; No, protection not available +; +; /* Get the lock. */ +; _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1; +; + MOV r3, #1 ; Build lock value + STR r3, [r2, #0] ; Store lock value + DMB ; +; +; /* Got the lock. */ +; _tx_thread_smp_protect_lock_got(); +; +macro_call1 _tx_thread_smp_protect_lock_got +; +; /* Remove this core from the wait list. */ +; _tx_thread_smp_protect_remove_from_front_of_list(); +; +macro_call2 _tx_thread_smp_protect_remove_from_front_of_list + + B _return + +_start_waiting +; +; /* For one reason or another, we didn't get the lock. */ +; +; /* Increment wait count. */ +; _tx_thread_smp_protect_wait_counts[this_core]++; +; + LDR r3, =_tx_thread_smp_protect_wait_counts ; Load wait list counts + LDR r4, [r3, r1, LSL #2] ; Load waiting value for this core + ADD r4, r4, #1 ; Increment wait value + STR r4, [r3, r1, LSL #2] ; Store new wait value +; +; /* Have we not added ourselves to the list yet? */ +; if (_tx_thread_smp_protect_wait_counts[this_core] == 1) +; { +; + CMP r4, #1 + BNE _already_in_list0 ; Is this core already waiting? +; +; /* Add ourselves to the list. */ +; _tx_thread_smp_protect_wait_list_add(this_core); +; +macro_call3 _tx_thread_smp_protect_wait_list_add ; Call macro to add ourselves to the list +; +; } +; +_already_in_list0 +; +; /* Restore interrupts. */ +; + MSR CPSR_c, r0 ; Restore CPSR + IF :DEF:TX_ENABLE_WFE + WFE ; Go into standby + ENDIF +; +; /* We do this until we have the lock. */ +; while (1) +; { +; +_try_to_get_lock +; +; /* Disable interrupts so we don't get preempted. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF + + MRC p15, 0, r1, c0, c0, 5 ; Read CPU ID register + AND r1, r1, #0x03 ; Mask off, leaving the CPU ID field +; +; /* Do we already have protection? */ +; if (this_core == _tx_thread_smp_protection.tx_thread_smp_protect_core) +; { +; + LDR r3, [r2, #8] ; Pickup the owning core + CMP r3, r1 ; Is it this core? + BEQ _got_lock_after_waiting ; Yes, the protection is already owned. This means + ; an ISR preempted us and got protection +; +; } +; +; /* Are we at the front of the list? */ +; if (this_core == _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head]) +; { +; + LDR r3, =_tx_thread_smp_protect_wait_list_head ; Get the address of the head + LDR r3, [r3] ; Get the value of the head + LDR r4, =_tx_thread_smp_protect_wait_list ; Get the address of the list + LDR r4, [r4, r3, LSL #2] ; Get the value at the head index + + CMP r1, r4 + BNE _did_not_get_lock +; +; /* Is the lock still available? */ +; if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0) +; { +; + LDR r3, [r2, #0] ; Pickup the protection flag + CMP r3, #0 + BNE _did_not_get_lock ; No, protection not available +; +; /* Get the lock. */ +; _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1; +; + MOV r3, #1 ; Build lock value + STR r3, [r2, #0] ; Store lock value + DMB ; +; +; /* Got the lock. */ +; _tx_thread_smp_protect_lock_got(); +; +macro_call4 _tx_thread_smp_protect_lock_got +; +; /* Remove this core from the wait list. */ +; _tx_thread_smp_protect_remove_from_front_of_list(); +; +macro_call5 _tx_thread_smp_protect_remove_from_front_of_list + + B _got_lock_after_waiting + +_did_not_get_lock +; +; /* For one reason or another, we didn't get the lock. */ +; +; /* Were we removed from the list? This can happen if we're a thread +; and we got preempted. */ +; if (_tx_thread_smp_protect_wait_counts[this_core] == 0) +; { +; + LDR r3, =_tx_thread_smp_protect_wait_counts ; Load wait list counts + LDR r4, [r3, r1, LSL #2] ; Load waiting value for this core + CMP r4, #0 + BNE _already_in_list1 ; Is this core already in the list? +; +; /* Add ourselves to the list. */ +; _tx_thread_smp_protect_wait_list_add(this_core); +; +macro_call6 _tx_thread_smp_protect_wait_list_add ; Call macro to add ourselves to the list +; +; /* Our waiting count was also reset when we were preempted. Increment it again. */ +; _tx_thread_smp_protect_wait_counts[this_core]++; +; + LDR r3, =_tx_thread_smp_protect_wait_counts ; Load wait list counts + LDR r4, [r3, r1, LSL #2] ; Load waiting value for this core + ADD r4, r4, #1 ; Increment wait value + STR r4, [r3, r1, LSL #2] ; Store new wait value value +; +; } +; +_already_in_list1 +; +; /* Restore interrupts and try again. */ +; + MSR CPSR_c, r0 ; Restore CPSR + IF :DEF:TX_ENABLE_WFE + WFE ; Go into standby + ENDIF + B _try_to_get_lock ; On waking, restart the protection attempt + +_got_lock_after_waiting +; +; /* We're no longer waiting. */ +; _tx_thread_smp_protect_wait_counts[this_core]--; +; + LDR r3, =_tx_thread_smp_protect_wait_counts ; Load waiting list + LDR r4, [r3, r1, LSL #2] ; Load current wait value + SUB r4, r4, #1 ; Decrement wait value + STR r4, [r3, r1, LSL #2] ; Store new wait value value + +; +; /* Restore link register and return. */ +; +_return + + POP {r4-r6} ; Restore registers + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF + + END + diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_protection_wait_list_macros.h new file mode 100644 index 00000000..57647009 --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_protection_wait_list_macros.h @@ -0,0 +1,313 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ + + MACRO +$label _tx_thread_smp_protect_lock_got +; +; /* Set the currently owned core. */ +; _tx_thread_smp_protection.tx_thread_smp_protect_core = this_core; +; + STR r1, [r2, #8] ; Store this core +; +; /* Increment the protection count. */ +; _tx_thread_smp_protection.tx_thread_smp_protect_count++; +; + LDR r3, [r2, #12] ; Pickup ownership count + ADD r3, r3, #1 ; Increment ownership count + STR r3, [r2, #12] ; Store ownership count + DMB + + IF :DEF:TX_MPCORE_DEBUG_ENABLE + LSL r3, r1, #2 ; Build offset to array indexes + LDR r4, =_tx_thread_current_ptr ; Pickup start of the current thread array + ADD r4, r3, r4 ; Build index into the current thread array + LDR r3, [r4] ; Pickup current thread for this core + STR r3, [r2, #4] ; Save current thread pointer + STR LR, [r2, #16] ; Save caller's return address + STR r0, [r2, #20] ; Save CPSR + ENDIF + + MEND + + MACRO +$label _tx_thread_smp_protect_remove_from_front_of_list +; +; /* Remove ourselves from the list. */ +; _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head++] = 0xFFFFFFFF; +; + MOV r3, #0xFFFFFFFF ; Build the invalid core value + LDR r4, =_tx_thread_smp_protect_wait_list_head ; Get the address of the head + LDR r5, [r4] ; Get the value of the head + LDR r6, =_tx_thread_smp_protect_wait_list ; Get the address of the list + STR r3, [r6, r5, LSL #2] ; Store the invalid core value + ADD r5, r5, #1 ; Increment the head +; +; /* Did we wrap? */ +; if (_tx_thread_smp_protect_wait_list_head == TX_THREAD_SMP_MAX_CORES + 1) +; { +; + LDR r3, =_tx_thread_smp_protect_wait_list_size ; Load address of core list size + LDR r3, [r3] ; Load the max cores value + CMP r5, r3 ; Compare the head to it + BNE $label._store_new_head ; Are we at the max? +; +; _tx_thread_smp_protect_wait_list_head = 0; +; + EOR r5, r5, r5 ; We're at the max. Set it to zero +; +; } +; +$label._store_new_head + + STR r5, [r4] ; Store the new head +; +; /* We have the lock! */ +; return; +; + MEND + + + MACRO +$label _tx_thread_smp_protect_wait_list_lock_get +;VOID _tx_thread_smp_protect_wait_list_lock_get() +;{ +; /* We do this until we have the lock. */ +; while (1) +; { +; +$label._tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock +; +; /* Is the list lock available? */ +; _tx_thread_smp_protect_wait_list_lock_protect_in_force = load_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force); +; + LDR r1, =_tx_thread_smp_protect_wait_list_lock_protect_in_force + LDREX r2, [r1] ; Pickup the protection flag +; +; if (protect_in_force == 0) +; { +; + CMP r2, #0 + BNE $label._tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock ; No, protection not available +; +; /* Try to get the list. */ +; int status = store_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force, 1); +; + MOV r2, #1 ; Build lock value + STREX r3, r2, [r1] ; Attempt to get the protection +; +; if (status == SUCCESS) +; + CMP r3, #0 + BNE $label._tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock ; Did it fail? If so, try again. +; +; /* We have the lock! */ +; return; +; + MEND + + + MACRO +$label _tx_thread_smp_protect_wait_list_add +;VOID _tx_thread_smp_protect_wait_list_add(UINT new_core) +;{ +; +; /* We're about to modify the list, so get the list lock. */ +; _tx_thread_smp_protect_wait_list_lock_get(); +; + PUSH {r1-r2} + +$label _tx_thread_smp_protect_wait_list_lock_get + + POP {r1-r2} +; +; /* Add this core. */ +; _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_tail++] = new_core; +; + LDR r3, =_tx_thread_smp_protect_wait_list_tail ; Get the address of the tail + LDR r4, [r3] ; Get the value of tail + LDR r5, =_tx_thread_smp_protect_wait_list ; Get the address of the list + STR r1, [r5, r4, LSL #2] ; Store the new core value + ADD r4, r4, #1 ; Increment the tail +; +; /* Did we wrap? */ +; if (_tx_thread_smp_protect_wait_list_tail == _tx_thread_smp_protect_wait_list_size) +; { +; + LDR r5, =_tx_thread_smp_protect_wait_list_size ; Load max cores address + LDR r5, [r5] ; Load max cores value + CMP r4, r5 ; Compare max cores to tail + BNE $label._tx_thread_smp_protect_wait_list_add__no_wrap ; Did we wrap? +; +; _tx_thread_smp_protect_wait_list_tail = 0; +; + MOV r4, #0 +; +; } +; +$label._tx_thread_smp_protect_wait_list_add__no_wrap + + STR r4, [r3] ; Store the new tail value. +; +; /* Release the list lock. */ +; _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; +; + MOV r3, #0 ; Build lock value + LDR r4, =_tx_thread_smp_protect_wait_list_lock_protect_in_force + STR r3, [r4] ; Store the new value + + MEND + + + MACRO +$label _tx_thread_smp_protect_wait_list_remove +;VOID _tx_thread_smp_protect_wait_list_remove(UINT core) +;{ +; +; /* Get the core index. */ +; UINT core_index; +; for (core_index = 0;; core_index++) +; + EOR r1, r1, r1 ; Clear for 'core_index' + LDR r2, =_tx_thread_smp_protect_wait_list ; Get the address of the list +; +; { +; +$label._tx_thread_smp_protect_wait_list_remove__check_cur_core +; +; /* Is this the core? */ +; if (_tx_thread_smp_protect_wait_list[core_index] == core) +; { +; break; +; + LDR r3, [r2, r1, LSL #2] ; Get the value at the current index + CMP r3, r10 ; Did we find the core? + BEQ $label._tx_thread_smp_protect_wait_list_remove__found_core +; +; } +; + ADD r1, r1, #1 ; Increment cur index + B $label._tx_thread_smp_protect_wait_list_remove__check_cur_core ; Restart the loop +; +; } +; +$label._tx_thread_smp_protect_wait_list_remove__found_core +; +; /* We're about to modify the list. Get the lock. We need the lock because another +; core could be simultaneously adding (a core is simultaneously trying to get +; the inter-core lock) or removing (a core is simultaneously being preempted, +; like what is currently happening). */ +; _tx_thread_smp_protect_wait_list_lock_get(); +; + PUSH {r1} + +$label _tx_thread_smp_protect_wait_list_lock_get + + POP {r1} +; +; /* We remove by shifting. */ +; while (core_index != _tx_thread_smp_protect_wait_list_tail) +; { +; +$label._tx_thread_smp_protect_wait_list_remove__compare_index_to_tail + + LDR r2, =_tx_thread_smp_protect_wait_list_tail ; Load tail address + LDR r2, [r2] ; Load tail value + CMP r1, r2 ; Compare cur index and tail + BEQ $label._tx_thread_smp_protect_wait_list_remove__removed +; +; UINT next_index = core_index + 1; +; + MOV r2, r1 ; Move current index to next index register + ADD r2, r2, #1 ; Add 1 +; +; if (next_index == _tx_thread_smp_protect_wait_list_size) +; { +; + LDR r3, =_tx_thread_smp_protect_wait_list_size + LDR r3, [r3] + CMP r2, r3 + BNE $label._tx_thread_smp_protect_wait_list_remove__next_index_no_wrap +; +; next_index = 0; +; + MOV r2, #0 +; +; } +; +$label._tx_thread_smp_protect_wait_list_remove__next_index_no_wrap +; +; list_cores[core_index] = list_cores[next_index]; +; + LDR r0, =_tx_thread_smp_protect_wait_list ; Get the address of the list + LDR r3, [r0, r2, LSL #2] ; Get the value at the next index + STR r3, [r0, r1, LSL #2] ; Store the value at the current index +; +; core_index = next_index; +; + MOV r1, r2 + + B $label._tx_thread_smp_protect_wait_list_remove__compare_index_to_tail +; +; } +; +$label._tx_thread_smp_protect_wait_list_remove__removed +; +; /* Now update the tail. */ +; if (_tx_thread_smp_protect_wait_list_tail == 0) +; { +; + LDR r0, =_tx_thread_smp_protect_wait_list_tail ; Load tail address + LDR r1, [r0] ; Load tail value + CMP r1, #0 + BNE $label._tx_thread_smp_protect_wait_list_remove__tail_not_zero +; +; _tx_thread_smp_protect_wait_list_tail = _tx_thread_smp_protect_wait_list_size; +; + LDR r2, =_tx_thread_smp_protect_wait_list_size + LDR r1, [r2] +; +; } +; +$label._tx_thread_smp_protect_wait_list_remove__tail_not_zero +; +; _tx_thread_smp_protect_wait_list_tail--; +; + SUB r1, r1, #1 + STR r1, [r0] ; Store new tail value +; +; /* Release the list lock. */ +; _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; +; + MOV r0, #0 ; Build lock value + LDR r1, =_tx_thread_smp_protect_wait_list_lock_protect_in_force ; Load lock address + STR r0, [r1] ; Store the new value +; +; /* We're no longer waiting. Note that this should be zero since, again, +; this function is only called when a thread preemption is occurring. */ +; _tx_thread_smp_protect_wait_counts[core]--; +; + LDR r1, =_tx_thread_smp_protect_wait_counts ; Load wait list counts + LDR r2, [r1, r10, LSL #2] ; Load waiting value + SUB r2, r2, #1 ; Subtract 1 + STR r2, [r1, r10, LSL #2] ; Store new waiting value + MEND + diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_time_get.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_time_get.s new file mode 100644 index 00000000..356c0122 --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_time_get.s @@ -0,0 +1,88 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +;#define TX_THREAD_SMP_SOURCE_CODE +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" */ +; +; + + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_time_get SMP/Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function gets the global time value that is used for debug */ +;/* information and event tracing. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* 32-bit time stamp */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ + EXPORT _tx_thread_smp_time_get +_tx_thread_smp_time_get + + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + LDR r0, [r0, #0x604] ; Read count register + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF + + END + diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_unprotect.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_unprotect.s new file mode 100644 index 00000000..f4ed864e --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_smp_unprotect.s @@ -0,0 +1,142 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +;#define TX_THREAD_SMP_SOURCE_CODE +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" */ +; +; + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_smp_protection + IMPORT _tx_thread_preempt_disable + IMPORT _tx_thread_smp_protect_wait_counts + + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_unprotect SMP/Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function releases previously obtained protection. The supplied */ +;/* previous SR is restored. If the value of _tx_thread_system_state */ +;/* and _tx_thread_preempt_disable are both zero, then multithreading */ +;/* is enabled as well. */ +;/* */ +;/* INPUT */ +;/* */ +;/* Previous Status Register */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ + EXPORT _tx_thread_smp_unprotect +_tx_thread_smp_unprotect +; +; /* Lockout interrupts. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF + + MRC p15, 0, r1, c0, c0, 5 ; Read CPU ID register + AND r1, r1, #0x03 ; Mask off, leaving the CPU ID field + + LDR r2,=_tx_thread_smp_protection ; Build address of protection structure + LDR r3, [r2, #8] ; Pickup the owning core + CMP r1, r3 ; Is it this core? + BNE _still_protected ; If this is not the owning core, protection is in force elsewhere + + LDR r3, [r2, #12] ; Pickup the protection count + CMP r3, #0 ; Check to see if the protection is still active + BEQ _still_protected ; If the protection count is zero, protection has already been cleared + + SUB r3, r3, #1 ; Decrement the protection count + STR r3, [r2, #12] ; Store the new count back + CMP r3, #0 ; Check to see if the protection is still active + BNE _still_protected ; If the protection count is non-zero, protection is still in force + LDR r2,=_tx_thread_preempt_disable ; Build address of preempt disable flag + LDR r3, [r2] ; Pickup preempt disable flag + CMP r3, #0 ; Is the preempt disable flag set? + BNE _still_protected ; Yes, skip the protection release + + LDR r2,=_tx_thread_smp_protect_wait_counts ; Build build address of wait counts + LDR r3, [r2, r1, LSL #2] ; Pickup wait list value + CMP r3, #0 ; Are any entities on this core waiting? + BNE _still_protected ; Yes, skip the protection release + + LDR r2,=_tx_thread_smp_protection ; Build address of protection structure + MOV r3, #0xFFFFFFFF ; Build invalid value + STR r3, [r2, #8] ; Mark the protected core as invalid + IF :DEF:TX_MPCORE_DEBUG_ENABLE + STR LR, [r2, #16] ; Save caller's return address + ENDIF + DMB ; Ensure that accesses to shared resource have completed + MOV r3, #0 ; Build release protection value + STR r3, [r2, #0] ; Release the protection + DSB ; To ensure update of the protection occurs before other CPUs awake + IF :DEF:TX_ENABLE_WFE + SEV ; Send event to other CPUs, wakes anyone waiting on the protection (using WFE) + ENDIF + +_still_protected + MSR CPSR_c, r0 ; Restore CPSR + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF + + END + diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_stack_build.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_stack_build.s new file mode 100644 index 00000000..54770103 --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_stack_build.s @@ -0,0 +1,172 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +SVC_MODE EQU 0x13 ; SVC mode + IF :DEF:TX_ENABLE_FIQ_SUPPORT +CPSR_MASK EQU 0xDF ; Mask initial CPSR, IRQ & FIQ ints enabled + ELSE +CPSR_MASK EQU 0x9F ; Mask initial CPSR, IRQ ints enabled + ENDIF + +THUMB_BIT EQU 0x20 ; Thumb-bit + +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build SMP/Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + EXPORT _tx_thread_stack_build +_tx_thread_stack_build +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-A7 should look like the following after it is built: +; +; Stack Top: 1 Interrupt stack frame type +; CPSR Initial value for CPSR +; a1 (r0) Initial value for a1 +; a2 (r1) Initial value for a2 +; a3 (r2) Initial value for a3 +; a4 (r3) Initial value for a4 +; v1 (r4) Initial value for v1 +; v2 (r5) Initial value for v2 +; v3 (r6) Initial value for v3 +; v4 (r7) Initial value for v4 +; v5 (r8) Initial value for v5 +; sb (r9) Initial value for sb +; sl (r10) Initial value for sl +; fp (r11) Initial value for fp +; ip (r12) Initial value for ip +; lr (r14) Initial value for lr +; pc (r15) Initial value for pc +; 0 For stack backtracing +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #7 ; Ensure 8-byte alignment + SUB r2, r2, #76 ; Allocate space for the stack frame +; +; /* Actually build the stack frame. */ +; + MOV r3, #1 ; Build interrupt stack type + STR r3, [r2, #0] ; Store stack type + MOV r3, #0 ; Build initial register value + STR r3, [r2, #8] ; Store initial r0 + STR r3, [r2, #12] ; Store initial r1 + STR r3, [r2, #16] ; Store initial r2 + STR r3, [r2, #20] ; Store initial r3 + STR r3, [r2, #24] ; Store initial r4 + STR r3, [r2, #28] ; Store initial r5 + STR r3, [r2, #32] ; Store initial r6 + STR r3, [r2, #36] ; Store initial r7 + STR r3, [r2, #40] ; Store initial r8 + STR r3, [r2, #44] ; Store initial r9 + LDR r3, [r0, #12] ; Pickup stack starting address + STR r3, [r2, #48] ; Store initial r10 (sl) + MOV r3, #0 ; Build initial register value + STR r3, [r2, #52] ; Store initial r11 + STR r3, [r2, #56] ; Store initial r12 + STR r3, [r2, #60] ; Store initial lr + STR r1, [r2, #64] ; Store initial pc + STR r3, [r2, #68] ; 0 for back-trace + + MRS r3, CPSR ; Pickup CPSR + BIC r3, r3, #CPSR_MASK ; Mask mode bits of CPSR + ORR r3, r3, #SVC_MODE ; Build CPSR, SVC mode, interrupts enabled + BIC r3, r3, #THUMB_BIT ; Clear Thumb-bit by default + AND r1, r1, #1 ; Determine if the entry function is in Thumb mode + CMP r1, #1 ; Is the Thumb-bit set? + ORREQ r3, r3, #THUMB_BIT ; Yes, set the Thumb-bit + STR r3, [r2, #4] ; Store initial CPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block + +; +; /* Set ready bit in thread control block. */ +; + LDR r2, [r0, #152] ; Pickup word with ready bit + ORR r2, r2, #0x8000 ; Build ready bit set + STR r2, [r0, #152] ; Set ready bit + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +;} + END + diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_system_return.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_system_return.s new file mode 100644 index 00000000..edb35391 --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_system_return.s @@ -0,0 +1,205 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IMPORT _tx_thread_current_ptr + IMPORT _tx_timer_time_slice + IMPORT _tx_thread_schedule + IMPORT _tx_thread_preempt_disable + IMPORT _tx_thread_smp_protection + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_thread_exit + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return SMP/Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + EXPORT _tx_thread_system_return +_tx_thread_system_return +; +; /* Save minimal context on the stack. */ +; + STMDB sp!, {r4-r11, lr} ; Save minimal context +; +; /* Pickup the CPU ID. */ +; + MRC p15, 0, r10, c0, c0, 5 ; Read CPU ID register + AND r10, r10, #0x03 ; Mask off, leaving the CPU ID field + LSL r12, r10, #2 ; Build offset to array indexes + + LDR r3, =_tx_thread_current_ptr ; Pickup address of current ptr + ADD r3, r3, r12 ; Build index into current ptr array + LDR r0, [r3, #0] ; Pickup current thread pointer + IF {TARGET_FPU_VFP} = {TRUE} + LDR r1, [r0, #160] ; Pickup the VFP enabled flag + CMP r1, #0 ; Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save ; No, skip VFP solicited save + VMRS r4, FPSCR ; Pickup the FPSCR + STR r4, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D8-D15} ; Save D8-D15 +_tx_skip_solicited_vfp_save + ENDIF + MOV r4, #0 ; Build a solicited stack type + MRS r5, CPSR ; Pickup the CPSR + STMDB sp!, {r4-r5} ; Save type and CPSR +; +; /* Lockout interrupts. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + MOV r4, r0 ; Save r0 + MOV r5, r3 ; Save r3 + MOV r6, r12 ; Save r12 + BL _tx_execution_thread_exit ; Call the thread exit function + MOV r3, r5 ; Recover r3 + MOV r0, r4 ; Recover r4 + MOV r12,r6 ; Recover r12 + ENDIF +; + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + ADD r2, r2, r12 ; Build index into time-slice array + LDR r1, [r2, #0] ; Pickup current time slice +; +; /* Save current stack and switch to system stack. */ +; _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; +; sp = _tx_thread_system_stack_ptr[core]; +; + STR sp, [r0, #8] ; Save thread stack pointer +; +; /* Determine if the time-slice is active. */ +; if (_tx_timer_time_slice[core]) +; { +; + MOV r4, #0 ; Build clear value + CMP r1, #0 ; Is a time-slice active? + BEQ __tx_thread_dont_save_ts ; No, don't save the time-slice +; +; /* Save time-slice for the thread and clear the current time-slice. */ +; _tx_thread_current_ptr[core] -> tx_thread_time_slice = _tx_timer_time_slice[core]; +; _tx_timer_time_slice[core] = 0; +; + STR r4, [r2, #0] ; Clear time-slice + STR r1, [r0, #24] ; Save current time-slice +; +; } +__tx_thread_dont_save_ts +; +; /* Clear the current thread pointer. */ +; _tx_thread_current_ptr[core] = TX_NULL; +; + STR r4, [r3, #0] ; Clear current thread pointer +; +; /* Set ready bit in thread control block. */ +; + LDR r2, [r0, #152] ; Pickup word with ready bit + ORR r2, r2, #0x8000 ; Build ready bit set + DMB ; Ensure that accesses to shared resource have completed + STR r2, [r0, #152] ; Set ready bit +; +; /* Now clear protection. It is assumed that protection is in force whenever this routine is called. */ +; + LDR r3, =_tx_thread_smp_protection ; Pickup address of protection structure + + IF :DEF:TX_MPCORE_DEBUG_ENABLE + STR lr, [r3, #24] ; Save last caller + LDR r2, [r3, #4] ; Pickup owning thread + CMP r0, r2 ; Is it the same as the current thread? +__error_loop + BNE __error_loop ; If not, we have a problem!! + ENDIF + + LDR r1, =_tx_thread_preempt_disable ; Build address to preempt disable flag + MOV r2, #0 ; Build clear value + STR r2, [r1, #0] ; Clear preempt disable flag + STR r2, [r3, #12] ; Clear protection count + MOV r1, #0xFFFFFFFF ; Build invalid value + STR r1, [r3, #8] ; Set core to an invalid value + DMB ; Ensure that accesses to shared resource have completed + STR r2, [r3] ; Clear protection + DSB ; To ensure update of the shared resource occurs before other CPUs awake + SEV ; Send event to other CPUs, wakes anyone waiting on a mutex (using WFE) + + B _tx_thread_schedule ; Jump to scheduler! +; +;} + END + diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_thread_vectored_context_save.s b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_vectored_context_save.s new file mode 100644 index 00000000..fe7866b8 --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_thread_vectored_context_save.s @@ -0,0 +1,209 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save SMP/Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_vectored_context_save(VOID) +;{ + EXPORT _tx_thread_vectored_context_save +_tx_thread_vectored_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state[core]++) +; { +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ENDIF +; +; /* Pickup the CPU ID. */ +; + MRC p15, 0, r10, c0, c0, 5 ; Read CPU ID register + AND r10, r10, #0x03 ; Mask off, leaving the CPU ID field + LSL r12, r10, #2 ; Build offset to array indexes + + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + ADD r3, r3, r12 ; Build index into the system state array + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Note: Minimal context of interrupted thread is already saved. */ +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {r12, lr} ; Save ISR lr & r12 + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {r12, lr} ; Recover ISR lr & r12 + ENDIF + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +__tx_thread_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr[core]) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + ADD r1, r1, r12 ; Build index into current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + ; scheduling loop - nothing needs saving! +; +; /* Note: Minimal context of interrupted thread is already saved. */ +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr[core]; +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {r12, lr} ; Save ISR lr & r12 + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {r12, lr} ; Recover ISR lr & r12 + ENDIF + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +; } +; else +; { +; +__tx_thread_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; processing. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {r12, lr} ; Save ISR lr & r12 + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {r12, lr} ; Recover ISR lr & r12 + ENDIF + + ADD sp, sp, #32 ; Recover saved registers + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +; } +;} +; + END + diff --git a/ports_smp/cortex_a7_smp/ac5/src/tx_timer_interrupt.s b/ports_smp/cortex_a7_smp/ac5/src/tx_timer_interrupt.s new file mode 100644 index 00000000..0aa02c78 --- /dev/null +++ b/ports_smp/cortex_a7_smp/ac5/src/tx_timer_interrupt.s @@ -0,0 +1,229 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_timer.h" +;#include "tx_thread.h" +; +; +;Define Assembly language external references... +; + IMPORT _tx_timer_time_slice + IMPORT _tx_timer_system_clock + IMPORT _tx_timer_current_ptr + IMPORT _tx_timer_list_start + IMPORT _tx_timer_list_end + IMPORT _tx_timer_expired_time_slice + IMPORT _tx_timer_expired + IMPORT _tx_thread_time_slice + IMPORT _tx_timer_expiration_process + IMPORT _tx_timer_interrupt_active + IMPORT _tx_thread_smp_protect + IMPORT _tx_thread_smp_unprotect + IMPORT _tx_trace_isr_enter_insert + IMPORT _tx_trace_isr_exit_insert +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt SMP/Cortex-A7/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* _tx_thread_smp_protect Get SMP protection */ +;/* _tx_thread_smp_unprotect Releast SMP protection */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + EXPORT _tx_timer_interrupt +_tx_timer_interrupt +; +; /* Upon entry to this routine, it is assumed that context save has already +; been called, and therefore the compiler scratch registers are available +; for use. */ +; + MRC p15, 0, r0, c0, c0, 5 ; Read CPU ID register + AND r0, r0, #0x03 ; Mask off, leaving the CPU ID field + CMP r0, #0 ; Only process timer interrupts from core 0 (to change this simply change the constant!) + BEQ __tx_process_timer ; If the same process the interrupt + BX lr ; Return to caller if not matched +__tx_process_timer + + STMDB sp!, {lr, r4} ; Save the lr and r4 register on the stack + BL _tx_thread_smp_protect ; Get protection + MOV r4, r0 ; Save the return value in preserved register + + LDR r1, =_tx_timer_interrupt_active ; Pickup address of timer interrupt active count + LDR r0, [r1, #0] ; Pickup interrupt active count + ADD r0, r0, #1 ; Increment interrupt active count + STR r0, [r1, #0] ; Store new interrupt active count + DMB ; Ensure that accesses to shared resource have completed +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + LDR r1, =_tx_timer_system_clock ; Pickup address of system clock + LDR r0, [r1, #0] ; Pickup system clock + ADD r0, r0, #1 ; Increment system clock + STR r0, [r1, #0] ; Store new system clock +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + LDR r1, =_tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Check for previous timer expiration still active + BNE __tx_timer_done ; If so, skip timer processing + LDR r1, =_tx_timer_current_ptr ; Pickup current timer pointer addr + LDR r0, [r1, #0] ; Pickup current timer + LDR r2, [r0, #0] ; Pickup timer list entry + CMP r2, #0 ; Is there anything in the list? + BEQ __tx_timer_no_timer ; No, just increment the timer +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + LDR r3, =_tx_timer_expired ; Pickup expiration flag address + MOV r2, #1 ; Build expired value + STR r2, [r3, #0] ; Set expired flag + B __tx_timer_done ; Finished timer processing +; +; } +; else +; { +__tx_timer_no_timer +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ADD r0, r0, #4 ; Move to next timer +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + LDR r3, =_tx_timer_list_end ; Pickup addr of timer list end + LDR r2, [r3, #0] ; Pickup list end + CMP r0, r2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, skip wrap-around logic +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + LDR r3, =_tx_timer_list_start ; Pickup addr of timer list start + LDR r0, [r3, #0] ; Set current pointer to list start +; +__tx_timer_skip_wrap +; + STR r0, [r1, #0] ; Store new current timer pointer +; } +; +__tx_timer_done +; +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + LDR r1, =_tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Check for timer expiration + BEQ __tx_timer_dont_activate ; If not set, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BL _tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate +; +; /* Call time-slice processing. */ +; _tx_thread_time_slice(); + + BL _tx_thread_time_slice ; Call time-slice processing +; +; } +; + LDR r1, =_tx_timer_interrupt_active ; Pickup address of timer interrupt active count + LDR r0, [r1, #0] ; Pickup interrupt active count + SUB r0, r0, #1 ; Decrement interrupt active count + STR r0, [r1, #0] ; Store new interrupt active count + DMB ; Ensure that accesses to shared resource have completed +; +; /* Release protection. */ +; + MOV r0, r4 ; Pass the previous status register back + BL _tx_thread_smp_unprotect ; Release protection + + LDMIA sp!, {lr, r4} ; Recover lr register and r4 + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +;} + END + diff --git a/ports_smp/cortex_a7_smp/gnu/example_build/MP_GIC.S b/ports_smp/cortex_a7_smp/gnu/example_build/MP_GIC.S new file mode 100644 index 00000000..fd8f5d78 --- /dev/null +++ b/ports_smp/cortex_a7_smp/gnu/example_build/MP_GIC.S @@ -0,0 +1,322 @@ +@;================================================================== +@; Cortex-A MPCore - GIC Code +@; +@; Copyright (c) 2011-2012 ARM Ltd. All rights reserved. +@;================================================================== + + .arm + +@;================================================================== +@; GIC. Generic Interrupt Controller Architecture Specification +@;================================================================== +@ +@ ; Interrupt Distributor offset from base of private peripheral space --> 0x1000 +@ ; CPU Interface offset from base of private peripheral space --> 0x2000 +@ +@ ; Typical calls to enable interrupt ID X: +@ ; enableIntID(X) <-- Enable that ID +@ ; setIntPriority(X, 0) <-- Set the priority of X to 0 (the max priority) +@ ; setPriorityMask(0x1F) <-- Set CPU's priority mask to 0x1F (the lowest priority) +@ ; enableGIC() <-- Enable the GIC (global) +@ ; enableGICProcessorInterface() <-- Enable the CPU interface (local to the CPU) +@ +@ +@ EXPORT enableGIC +@ ; void enableGIC(void) +@ ; Global enable of the Interrupt Distributor + .text + .align 2 + .global enableGIC + .type enableGIC,function +enableGIC: + @ Get base address of private peripheral space + MRC p15, 4, r0, c15, c0, 0 @ Read periph base address + ADD r0, r0, #0x1000 @ Add the Distributor offset + + LDR r1, [r0, #0x000] @ Read the Distributor Control Register (GICD_CTLR) + ORR r1, r1, #0x01 @ Interrupts forwarded + STR r1, [r0, #0x000] @ Write Distributor Control Register (GICD_CTLR) + + BX lr + + +@; ------------------------------------------------------------ +@ +@ EXPORT disableGIC +@ ; void disableGIC(void) +@ ; Global disable of the Interrupt Distributor + .text + .align 2 + .global disableGIC + .type disableGIC,function +disableGIC: + @ Get base address of private peripheral space + MRC p15, 4, r0, c15, c0, 0 @ Read periph base address + ADD r0, r0, #0x1000 @ Add the Distributor offset + + LDR r1, [r0, #0x000] @ Read the Distributor Control Register (GICD_CTLR) + BIC r1, r1, #0x01 @ Interrupts not forwarded + STR r1, [r0, #0x000] @ Write the Distributor Control Register (GICD_CTLR) + + BX lr + +@; ------------------------------------------------------------ +@ +@ EXPORT enableIntID +@ ; void enableIntID(unsigned int ID) +@ ; Enables the interrupt source number ID + .text + .align 2 + .global enableIntID + .type enableIntID,function +enableIntID: + @ Get base address of private peripheral space + MOV r1, r0 @ Back up passed in ID value + MRC p15, 4, r0, c15, c0, 0 @ Read periph base address + + @ Each interrupt source has an enable bit in the GIC. These + @ are grouped into registers, with 32 sources per register + @ First, we need to identify which 32 bit block the interrupt lives in + MOV r2, r1 @ Make working copy of ID in r2 + MOV r2, r2, LSR #5 @ LSR by 5 places, affective divide by 32 + @ r2 now contains the 32 bit block this ID lives in + MOV r2, r2, LSL #2 @ Now multiply by 4, to covert offset into an address offset (four bytes per reg) + + @ Now work out which bit within the 32 bit block the ID is + AND r1, r1, #0x1F @ Mask off to give offset within 32bit block + MOV r3, #1 @ Move enable value into r3 + MOV r3, r3, LSL r1 @ Shift it left to position of ID + + ADD r2, r2, #0x1100 @ Add the base offset of the Interrupt Set-Enable Registers to the offset for the ID + STR r3, [r0, r2] @ Store out (GICD_ISENABLERn) + + BX lr + +@; ------------------------------------------------------------ +@ +@ EXPORT disableIntID +@ ; void disableIntID(unsigned int ID) +@ ; Disables the interrupt source number ID + .text + .align 2 + .global disableIntID + .type disableIntID,function +disableIntID: + @ Get base address of private peripheral space + MOV r1, r0 @ Back up passed in ID value + MRC p15, 4, r0, c15, c0, 0 @ Read periph base address + + @ First, we need to identify which 32 bit block the interrupt lives in + MOV r2, r1 @ Make working copy of ID in r2 + MOV r2, r2, LSR #5 @ LSR by 5 places, affective divide by 32 + @ r2 now contains the 32 bit block this ID lives in + MOV r2, r2, LSL #2 @ Now multiply by 4, to covert offset into an address offset (four bytes per reg) + + @ Now work out which bit within the 32 bit block the ID is + AND r1, r1, #0x1F @ Mask off to give offset within 32bit block + MOV r3, #1 @ Move enable value into r3 + MOV r3, r3, LSL r1 @ Shift it left to position of ID in 32 bit block + + ADD r2, r2, #0x1180 @ Add the base offset of the Interrupt Clear-Enable Registers to the offset for the ID + STR r3, [r0, r2] @ Store out (GICD_ICENABLERn) + + BX lr + +@; ------------------------------------------------------------ +@ +@ EXPORT setIntPriority +@ ; void setIntPriority(unsigned int ID, unsigned int priority) +@ ; Sets the priority of the specifed ID +@ ; r0 = ID +@ ; r1 = priority + .text + .align 2 + .global setIntPriority + .type setIntPriority,function +setIntPriority: + @ Get base address of private peripheral space + MOV r2, r0 @ Back up passed in ID value + MRC p15, 4, r0, c15, c0, 0 @ Read periph base address + + @ r0 = base addr + @ r1 = priority + @ r2 = ID + + @ Make sure that priority value is only 5 bits, and convert to expected format + AND r1, r1, #0x1F + MOV r1, r1, LSL #3 + + @ Find which priority register this ID lives in + BIC r3, r2, #0x03 @ Make a copy of the ID, clearing off the bottom two bits + @ There are four IDs per reg, by clearing the bottom two bits we get an address offset + ADD r3, r3, #0x1400 @ Now add the offset of the Interrupt Priority Registers from the base of the private peripheral space + ADD r0, r0, r3 @ Now add in the base address of the private peripheral space, giving us the absolute address + + @ Now work out which ID in the register it is + AND r2, r2, #0x03 @ Clear all but the bottom two bits, leaves which ID in the reg it is (which byte) + MOV r2, r2, LSL #3 @ Multiply by 8, this gives a bit offset + + @ Read -> Modify -> Write + MOV r12, #0xFF @ Mask (8 bits) + MOV r12, r12, LSL r2 @ Move mask into correct bit position + MOV r1, r1, LSL r2 @ Also, move passed in priority value into correct bit position + + LDR r3, [r0] @ Read current value of the Interrupt Priority Registers (GICD_IPRIORITYRn) + BIC r3, r3, r12 @ Clear appropriate field + ORR r3, r3, r1 @ Now OR in the priority value + STR r3, [r0] @ And store it back again (GICD_IPRIORITYRn) + + BX lr + +@; ------------------------------------------------------------ +@ +@ EXPORT enableGICProcessorInterface +@ ; void enableGICProcessorInterface(void) +@ ; Enables the processor interface +@ ; Must be done on each core separately + .text + .align 2 + .global enableGICProcessorInterface + .type enableGICProcessorInterface,function +enableGICProcessorInterface: + @ Get base address of private peripheral space + MRC p15, 4, r0, c15, c0, 0 @ Read periph base address + ADD r0, r0, #0x2000 @ Add the CPU interface offset + + LDR r1, [r0] @ Read the CPU Interface Control Register (GICC_CTLR) + ORR r1, r1, #0x01 @ Set bit 0, the enable bit + STR r1, [r0] @ Write the CPU Interface Control Register (GICC_CTLR) + + BX lr + + +@; ------------------------------------------------------------ +@ +@ EXPORT disableGICProcessorInterface +@ ; void disableGICProcessorInterface(void) +@ ; Disables the processor interface +@ ; Must be done on each core separately + .text + .align 2 + .global disableGICProcessorInterface + .type disableGICProcessorInterface,function +disableGICProcessorInterface: + @ Get base address of private peripheral space + MRC p15, 4, r0, c15, c0, 0 @ Read periph base address + ADD r0, r0, #0x2000 @ Add the CPU interface offset + + LDR r1, [r0] @ Read the CPU Interface Control Register (GICC_CTLR) + BIC r1, r1, #0x01 @ Clear bit 0, the enable bit + STR r1, [r0] @ Write the CPU Interface Control Register (GICC_CTLR) + + BX lr + + +@; ------------------------------------------------------------ +@ +@ EXPORT setPriorityMask +@ ; void setPriorityMask(unsigned int priority) +@ ; Sets the Priority mask register for the CPU run on +@ ; The reset value masks ALL interrupts! + .text + .align 2 + .global setPriorityMask + .type setPriorityMask,function +setPriorityMask: + + @ Get base address of private peripheral space + MRC p15, 4, r1, c15, c0, 0 @ Read periph base address + ADD r1, r1, #0x2000 @ Add the CPU interface offset + + STR r0, [r1, #0x0004] @ Write the Interrupt Priority Mask register (GICC_PMR) + + BX lr + +@; ------------------------------------------------------------ +@ +@ EXPORT setBinaryPoint +@ ; void setBinaryPoint(unsigned int priority) +@ ; Sets the Binary Point Register for the CPU run on + .text + .align 2 + .global setBinaryPoint + .type setBinaryPoint,function +setBinaryPoint: + + @ Get base address of private peripheral space + MRC p15, 4, r1, c15, c0, 0 @ Read periph base address + ADD r1, r1, #0x2000 @ Add the CPU interface offset + + STR r0, [r1, #0x0008] @ Write the Binary Point Register (GICC_BPR) + + BX lr + +@; ------------------------------------------------------------ +@ +@ EXPORT readIntAck +@ ; unsigned int readIntAck(void) +@ ; Returns the value of the Interrupt Acknowledge Register + .text + .align 2 + .global readIntAck + .type readIntAck,function +readIntAck: + MRC p15, 4, r1, c15, c0, 0 @ Read periph base address + ADD r1, r1, #0x2000 @ Add the CPU interface offset + + LDR r0, [r1, #0x000C] @ Read the Interrupt Acknowledge Register (GICC_IAR) + BX lr + +@; ------------------------------------------------------------ +@ +@ EXPORT writeEOI +@ ; void writeEOI(unsigned int ID) +@ ; Writes ID to the End Of Interrupt register + .text + .align 2 + .global writeEOI + .type writeEOI,function +writeEOI: + + @ Get base address of private peripheral space + MRC p15, 4, r1, c15, c0, 0 @ Read periph base address + ADD r1, r1, #0x2000 @ Add the CPU interface offset + + STR r0, [r1, #0x0010] @ Write ID to the End of Interrupt register (GICC_EOIR) + + BX lr + +@;================================================================== +@; SGI +@;================================================================== +@ +@ EXPORT sendSGI +@ ; void sendSGI(unsigned int ID, unsigned int target_list, unsigned int filter_list); +@ ; Send a software generate interrupt + .text + .align 2 + .global sendSGI + .type sendSGI,function +sendSGI: + AND r3, r0, #0x0F @ Mask off unused bits of ID, and move to r3 + AND r1, r1, #0x0F @ Mask off unused bits of target_filter + AND r2, r2, #0x0F @ Mask off unused bits of filter_list + + ORR r3, r3, r1, LSL #16 @ Combine ID and target_filter + ORR r3, r3, r2, LSL #24 @ and now the filter list + + @ Get the address of the GIC + MRC p15, 4, r0, c15, c0, 0 @ Read periph base address + ADD r0, r0, #0x1F00 @ Add offset of the sgi_trigger reg + + STR r3, [r0] @ Write to the Software Generated Interrupt Register (GICD_SGIR) + + BX lr + +@;================================================================== +@; End of code +@;================================================================== +@ +@;================================================================== +@; End of MP_GIC.s +@;================================================================== diff --git a/ports_smp/cortex_a7_smp/gnu/example_build/MP_GIC.h b/ports_smp/cortex_a7_smp/gnu/example_build/MP_GIC.h new file mode 100644 index 00000000..40159cbb --- /dev/null +++ b/ports_smp/cortex_a7_smp/gnu/example_build/MP_GIC.h @@ -0,0 +1,117 @@ +// ------------------------------------------------------------ +// Cortex-A MPCore - Interrupt Controller functions +// Header File +// +// Copyright (c) 2011 ARM Ltd. All rights reserved. +// ------------------------------------------------------------ + +#ifndef _CORTEXA_GIC_H +#define _CORTEXA_GIC_H + +#define SPURIOUS (255) + +// PPI IDs: +#define MPCORE_PPI_PRIVATE_TIMER (29) +#define MPCORE_PPI_PRIVATE_WD (30) +#define MPCORE_PPI_GLOBAL_TIMER (27) +#define MPCORE_PPI_LEGACY_IRQ (31) +#define MPCORE_PPI_LEGACY_FIQ (28) + +// ------------------------------------------------------------ +// GIC +// ------------------------------------------------------------ + +// Typical calls to enable interrupt ID X: +// disableIntID(X) <-- Enable that ID +// setIntPriority(X, 0) <-- Set the priority of X to 0 (the max priority) +// setPriorityMask(0x1F) <-- Set Core's priority mask to 0x1F (the lowest priority) +// enableGIC() <-- Enable the GIC (global) +// enableGICProcessorInterface() <-- Enable the CPU interface (local to the core) +// + + +// Global enable of the Interrupt Distributor +void enableGIC(void); + +// Global disable of the Interrupt Distributor +void disableGIC(void); + +// Enables the interrupt source number ID +void enableIntID(unsigned int ID); + +// Disables the interrupt source number ID +void disableIntID(unsigned int ID); + +// Enables the processor interface +// Must be done on each core separately +void enableGICProcessorInterface(void); + +// Disables the processor interface +// Must be done on each core separately +void disableGICProcessorInterface(void); + +// Sets the Priority mask register for the core run on +// The reset value masks ALL interrupts! +// +// NOTE: Bits 2:0 of this register are SBZ, the function does perform any shifting! +void setPriorityMask(unsigned int priority); + +// Sets the Binary Point Register for the core run on +void setBinaryPoint(unsigned int priority); + +// Sets the priority of the specifed ID +void setIntPriority(unsigned int ID, unsigned int priority); + +// Sets the priority of the specifed ID +void getIntPriority(unsigned int ID, unsigned int priority); + +#define MPCORE_IC_TARGET_NONE (0x0) +#define MPCORE_IC_TARGET_CPU0 (0x1) +#define MPCORE_IC_TARGET_CPU1 (0x2) +#define MPCORE_IC_TARGET_CPU2 (0x4) +#define MPCORE_IC_TARGET_CPU3 (0x8) + +// Sets the target CPUs of the specified ID +// For 'target' use one of the above defines +unsigned int setIntTarget(unsigned int ID, unsigned int target); + +//Returns the target CPUs of the specified ID +unsigned int getIntTarget(unsigned int ID); + +// Returns the value of the Interrupt Acknowledge Register +unsigned int readIntAck(void); + +// Writes ID to the End Of Interrupt register +void writeEOI(unsigned int ID); + +// ------------------------------------------------------------ +// SGI +// ------------------------------------------------------------ + +// Send a software generate interrupt +void sendSGI(unsigned int ID, unsigned int core_list, unsigned int filter_list); + +// ------------------------------------------------------------ +// TrustZone +// ------------------------------------------------------------ + +// Enables the sending of secure interrupts as FIQs +void enableSecureFIQs(void); + +// Disables the sending of secure interrupts as FIQs +void disableSecureFIQs(void); + +// Sets the specifed ID as secure +void makeIntSecure(unsigned int ID); + +// Set the specified ID as non-secure +void makeIntNonSecure(unsigned int ID); + +// Returns the security of the specifed ID +void getIntSecurity(unsigned int ID); + +#endif + +// ------------------------------------------------------------ +// End of MP_GIC.h +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a7_smp/gnu/example_build/MP_Mutexes.S b/ports_smp/cortex_a7_smp/gnu/example_build/MP_Mutexes.S new file mode 100644 index 00000000..03ffb354 --- /dev/null +++ b/ports_smp/cortex_a7_smp/gnu/example_build/MP_Mutexes.S @@ -0,0 +1,138 @@ +@; ------------------------------------------------------------ +@; Cortex-A MPCore - Mutex Code +@; +@; Copyright (c) 2011-2012 ARM Ltd. All rights reserved. +@; ------------------------------------------------------------ +@ +@ PRESERVE8 +@ +@ AREA MP_Mutexes, CODE, READONLY +@ +@ ;NOTES +@ ; struct mutex_t defined in MP_Mutexes.h +@ ; typedef struct mutex_t +@ ; { +@ ; unsigned int lock; <-- offset 0 +@ ; } +@ ; +@ ; lock: 0xFF=unlocked 0x0 = Locked by CPU 0, 0x1 = Locked by CPU 1, 0x2 = Locked by CPU 2, 0x3 = Locked by CPU 3 +@ ; + +UNLOCKED = 0xFF + +@; ------------------------------------------------------------ +@ +@ EXPORT initMutex +@ ; void initMutex(mutex_t* pMutex) +@ ; Places mutex into a known state +@ ; r0 = address of mutex_t + .text + .align 2 + .global $initMutex + .type $initMutex,function +initMutex: + + MOV r1, #UNLOCKED @ Mark as unlocked + STR r1, [r0] + + BX lr + + +@; ------------------------------------------------------------ +@ +@ EXPORT lockMutex +@ ; void lockMutex(mutex_t* pMutex) +@ ; Blocking call, returns once successfully locked a mutex +@ ; r0 = address of mutex_t + .text + .align 2 + .global $lockMutex + .type $lockMutex,function +lockMutex: + + @ Is mutex locked? + @ ----------------- + LDREX r1, [r0] @ Read lock field + CMP r1, #UNLOCKED @ Compare with "unlocked" + + WFENE @ If mutex is locked, go into standby + BNE lockMutex @ On waking re-check the mutex + + @ Attempt to lock mutex + @ ----------------------- + MRC p15, 0, r1, c0, c0, 5 @ Read CPU ID register + AND r1, r1, #0x03 @ Mask off, leaving the CPU ID field. + STREX r2, r1, [r0] @ Attempt to lock mutex, by write CPU's ID to lock field + CMP r2, #0x0 @ Check whether store completed successfully (0=succeeded) + BNE lockMutex @ If store failed, go back to beginning and try again + + DMB + + BX lr @ Return as mutex is now locked by this cpu + + +@; ------------------------------------------------------------ +@ +@ EXPORT unlockMutex +@ ; unsigned int unlockMutex(mutex_t* pMutex) +@ ; Releases mutex, returns 0x0 for success and 0x1 for failure +@ ; r0 = address of mutex_t + .text + .align 2 + .global $unlockMutex + .type $unlockMutex,function +unlockMutex: + + @ Does this CPU own the mutex? + @ ----------------------------- + MRC p15, 0, r1, c0, c0, 5 @ Read CPU ID register + AND r1, r1, #0x03 @ Mask off, leaving the CPU ID in r1 + LDR r2, [r0] @ Read the lock field of the mutex + CMP r1, r2 @ Compare ID of this CPU with the lock owner + MOVNE r0, #0x1 @ If ID doesn't match, return "fail" + BXNE lr + + + @ Unlock mutex + @ ------------- + DMB @ Ensure that accesses to shared resource have completed + + MOV r1, #UNLOCKED @ Write "unlocked" into lock field + STR r1, [r0] + + DSB @ Ensure that no instructions following the barrier execute until + @ all memory accesses prior to the barrier have completed. + + SEV @ Send event to other CPUs, wakes anyone waiting on a mutex (using WFE) + + MOV r0, #0x0 @ Return "success" + BX lr + + +@; ------------------------------------------------------------ +@ +@ EXPORT isMutexLocked +@ ; void isMutexLocked(mutex_t* pMutex) +@ ; Returns 0x0 if mutex unlocked, 0x1 is locked +@ ; r0 = address of mutex_t + .text + .align 2 + .global $isMutexLocked + .type $isMutexLocked,function +isMutexLocked: + LDR r0, [r0] + CMP r0, #UNLOCKED + MOVEQ r0, #0x0 + MOVNE r0, #0x1 + BX lr + + +@; ------------------------------------------------------------ +@; End of code +@; ------------------------------------------------------------ +@ +@ END +@ +@; ------------------------------------------------------------ +@; End of MP_Mutexes.s +@; ------------------------------------------------------------ diff --git a/ports_smp/cortex_a7_smp/gnu/example_build/MP_Mutexes.h b/ports_smp/cortex_a7_smp/gnu/example_build/MP_Mutexes.h new file mode 100644 index 00000000..f9b17805 --- /dev/null +++ b/ports_smp/cortex_a7_smp/gnu/example_build/MP_Mutexes.h @@ -0,0 +1,42 @@ +// ------------------------------------------------------------ +// Cortex-A MPCore - Mutex +// Header File +// +// Copyright (c) 2011 ARM Ltd. All rights reserved. +// ------------------------------------------------------------ + +#ifndef _CORTEXA_MUTEX_H +#define _CORTEXA_MUTEX_H + +// Struct +// 0xFF=unlocked 0x0 = Locked by CPU 0, +// 0x1 = Locked by CPU 1, +// 0x2 = Locked by CPU 2, +// 0x3 = Locked by CPU 3 +typedef struct +{ + unsigned int lock; +}mutex_t; + +// Places mutex into a known state +// r0 = address of mutex_t +void initMutex(mutex_t* pMutex); + +// Blocking call, returns once successfully locked a mutex +// r0 = address of mutex_t +void lockMutex(mutex_t* pMutex); + +// Releases (unlock) mutex. Fails if CPU not owner of mutex. +// returns 0x0 for success, and 0x1 for failure +// r0 = address of mutex_t +unsigned int unlockMutex(mutex_t* pMutex); + +// Returns 0x0 if mutex unlocked, 0x1 is locked +// r0 = address of mutex_t +void isMutexLocked(mutex_t* pMutex); + +#endif + +// ------------------------------------------------------------ +// End of MP_Mutexes.h +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a7_smp/gnu/example_build/build_threadx.bat b/ports_smp/cortex_a7_smp/gnu/example_build/build_threadx.bat new file mode 100644 index 00000000..6fbf6081 --- /dev/null +++ b/ports_smp/cortex_a7_smp/gnu/example_build/build_threadx.bat @@ -0,0 +1,257 @@ +del tx.a +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 tx_initialize_low_level.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 ../src/tx_thread_stack_build.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 ../src/tx_thread_schedule.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 ../src/tx_thread_system_return.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 ../src/tx_thread_context_save.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 ../src/tx_thread_context_restore.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 ../src/tx_thread_interrupt_control.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 ../src/tx_timer_interrupt.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 ../src/tx_thread_interrupt_disable.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 ../src/tx_thread_interrupt_restore.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 ../src/tx_thread_irq_nesting_end.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 ../src/tx_thread_irq_nesting_start.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 ../src/tx_thread_vectored_context_save.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 ../src/tx_thread_smp_core_get.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 ../src/tx_thread_smp_core_preempt.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 ../src/tx_thread_smp_current_state_get.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 ../src/tx_thread_smp_current_thread_get.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 ../src/tx_thread_smp_initialize_wait.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 ../src/tx_thread_smp_low_level_initialize.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 ../src/tx_thread_smp_protect.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 ../src/tx_thread_smp_time_get.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 ../src/tx_thread_smp_unprotect.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_block_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_block_pool_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_block_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_block_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_block_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_block_pool_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_block_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_block_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_block_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_block_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_byte_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_byte_pool_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_byte_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_byte_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_byte_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_byte_pool_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_byte_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_byte_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_byte_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_byte_pool_search.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_byte_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_event_flags_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_event_flags_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_event_flags_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_event_flags_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_event_flags_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_event_flags_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_event_flags_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_event_flags_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_event_flags_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_event_flags_set_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_initialize_high_level.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_initialize_kernel_enter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_initialize_kernel_setup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_mutex_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_mutex_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_mutex_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_mutex_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_mutex_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_mutex_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_mutex_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_mutex_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_mutex_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_mutex_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_mutex_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_flush.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_front_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_receive.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_queue_send_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_semaphore_ceiling_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_semaphore_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_semaphore_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_semaphore_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_semaphore_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_semaphore_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_semaphore_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_semaphore_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_semaphore_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_semaphore_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_semaphore_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_semaphore_put_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_entry_exit_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_identify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_preemption_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_relinquish.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_reset.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_shell_entry.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_sleep.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_stack_analyze.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_stack_error_handler.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_stack_error_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_system_preempt_check.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_system_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_system_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_terminate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_time_slice.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_time_slice_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_timeout.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_wait_abort.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_time_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_time_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_expiration_process.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_system_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_system_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_thread_entry.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_trace_enable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_trace_disable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_trace_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_trace_interrupt_control.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_trace_isr_enter_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_trace_isr_exit_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_trace_object_register.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_trace_object_unregister.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_trace_user_event_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_trace_buffer_full_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_trace_event_filter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_trace_event_unfilter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_block_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_block_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_block_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_block_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_block_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_block_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_byte_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_byte_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_byte_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_byte_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_byte_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_byte_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_event_flags_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_event_flags_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_event_flags_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_event_flags_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_event_flags_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_event_flags_set_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_mutex_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_mutex_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_mutex_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_mutex_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_mutex_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_mutex_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_queue_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_queue_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_queue_flush.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_queue_front_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_queue_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_queue_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_queue_receive.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_queue_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_queue_send_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_semaphore_ceiling_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_semaphore_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_semaphore_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_semaphore_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_semaphore_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_semaphore_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_semaphore_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_semaphore_put_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_entry_exit_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_preemption_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_relinquish.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_reset.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_terminate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_time_slice_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_thread_wait_abort.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_timer_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_timer_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_timer_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_timer_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_timer_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/txe_timer_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_smp_current_state_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_smp_debug_entry_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_smp_high_level_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_smp_rebalance_execute_list.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_smp_core_exclude.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_smp_core_exclude_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_smp_core_exclude.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_timer_smp_core_exclude_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 -I../../../../common_smp/inc -I../inc ../../../../common_smp/src/tx_thread_smp_utilities.c +arm-none-eabi-ar -r tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o +arm-none-eabi-ar -r tx.a tx_initialize_low_level.o tx_thread_interrupt_disable.o +arm-none-eabi-ar -r tx.a tx_thread_interrupt_restore.o tx_thread_irq_nesting_end.o tx_thread_irq_nesting_start.o +arm-none-eabi-ar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o +arm-none-eabi-ar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o +arm-none-eabi-ar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o +arm-none-eabi-ar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o +arm-none-eabi-ar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o +arm-none-eabi-ar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o +arm-none-eabi-ar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o +arm-none-eabi-ar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o +arm-none-eabi-ar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o +arm-none-eabi-ar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o +arm-none-eabi-ar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o +arm-none-eabi-ar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o +arm-none-eabi-ar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o +arm-none-eabi-ar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o +arm-none-eabi-ar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o +arm-none-eabi-ar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o +arm-none-eabi-ar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o +arm-none-eabi-ar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o +arm-none-eabi-ar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o +arm-none-eabi-ar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o +arm-none-eabi-ar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o +arm-none-eabi-ar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o +arm-none-eabi-ar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o +arm-none-eabi-ar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o +arm-none-eabi-ar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o +arm-none-eabi-ar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o +arm-none-eabi-ar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o +arm-none-eabi-ar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o +arm-none-eabi-ar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o +arm-none-eabi-ar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o +arm-none-eabi-ar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o +arm-none-eabi-ar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o +arm-none-eabi-ar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o +arm-none-eabi-ar -r tx.a tx_thread_smp_current_state_set.o tx_thread_smp_debug_entry_insert.o tx_thread_smp_high_level_initialize.o +arm-none-eabi-ar -r tx.a tx_thread_smp_rebalance_execute_list.o tx_thread_smp_core_exclude.o tx_thread_smp_core_exclude_get.o +arm-none-eabi-ar -r tx.a tx_timer_smp_core_exclude.o tx_timer_smp_core_exclude_get.o tx_thread_smp_utilities.o +arm-none-eabi-ar -r tx.a tx_thread_smp_core_get.o tx_thread_smp_core_preempt.o tx_thread_smp_current_state_get.o tx_thread_smp_current_thread_get.o tx_thread_smp_initialize_wait.o +arm-none-eabi-ar -r tx.a tx_thread_smp_low_level_initialize.o tx_thread_smp_protect.o tx_thread_smp_time_get.o tx_thread_smp_unprotect.o diff --git a/ports_smp/cortex_a7_smp/gnu/example_build/build_threadx_sample.bat b/ports_smp/cortex_a7_smp/gnu/example_build/build_threadx_sample.bat new file mode 100644 index 00000000..98729d7d --- /dev/null +++ b/ports_smp/cortex_a7_smp/gnu/example_build/build_threadx_sample.bat @@ -0,0 +1,7 @@ +arm-none-eabi-gcc -c -g -I../../../../common_smp/inc -I../inc -mcpu=cortex-a7 sample_threadx.c +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 startup.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 MP_GIC.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 MP_Mutexes.S +arm-none-eabi-gcc -c -g -mcpu=cortex-a7 v7.S +REM arm-none-eabi-ld -A cortex-a5 -T sample_threadx.ld reset.o crt0.o tx_initialize_low_level.o sample_threadx.o tx.a libc.a libgcc.a -o sample_threadx.out -M > sample_threadx.map +arm-none-eabi-gcc -T sample_threadx.ld -e Vectors -o sample_threadx.axf MP_GIC.o MP_Mutexes.o sample_threadx.o startup.o v7.o tx.a -Wl,-M > sample_threadx.map diff --git a/ports_smp/cortex_a7_smp/gnu/example_build/sample_threadx.c b/ports_smp/cortex_a7_smp/gnu/example_build/sample_threadx.c new file mode 100644 index 00000000..1b6df7c2 --- /dev/null +++ b/ports_smp/cortex_a7_smp/gnu/example_build/sample_threadx.c @@ -0,0 +1,381 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_TIMER timer_0; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +#ifdef TX_ENABLE_EVENT_TRACE + +UCHAR event_buffer[65536]; + +#endif + + + +int main(void) +{ + + /* Enter ThreadX. */ + tx_kernel_enter(); + + return 0; +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + +#ifdef TX_ENABLE_EVENT_TRACE + + tx_trace_enable(event_buffer, sizeof(event_buffer), 32); +#endif + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + diff --git a/ports_smp/cortex_a7_smp/gnu/example_build/sample_threadx.ld b/ports_smp/cortex_a7_smp/gnu/example_build/sample_threadx.ld new file mode 100644 index 00000000..fb1ca03c --- /dev/null +++ b/ports_smp/cortex_a7_smp/gnu/example_build/sample_threadx.ld @@ -0,0 +1,182 @@ +/* Linker script to place sections and symbol values. + * It references following symbols, which must be defined in code: + * Vectors : Entry point + * + * It defines following symbols, which code can use without definition: + * __code_start + * __exidx_start + * __exidx_end + * __data_start + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __bss_start__ + * __bss_end__ + * __end__ + * __stack + * __irq_stack + * __stack + * __pagetable_start + */ +ENTRY(Vectors) + +SECTIONS +{ + + .vectors 0x80008000: + { + _exec = .; + __code_start = .; + KEEP(*(VECTORS)) + } + + .init : + { + KEEP (*(SORT_NONE(.init))) + } + + .text : + { + KEEP(*(ENABLE_CACHES)) + *(.text*) + } + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } + + .rodata : + { + *(.rodata .rodata.* .gnu.linkonce.r.*) + } + + .eh_frame : + { + KEEP (*(.eh_frame)) + } + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } + + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array )) + PROVIDE_HIDDEN (__init_array_end = .); + } + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array )) + PROVIDE_HIDDEN (__fini_array_end = .); + } + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } + + .jcr : + { + KEEP (*(.jcr)) + } + + .data : + { + __data_start = . ; + *(.data .data.* .gnu.linkonce.d.*) + SORT(CONSTRUCTORS) + } + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } + + .heap (NOLOAD): + { + . = ALIGN(64); + __end__ = .; + PROVIDE(end = .); + . = . + 0xA0000; + } + + .stack (NOLOAD): + { + . = ALIGN(64); + . = . + 4 * 0x4000; + __stack = .; + _stack_init_usr = .; + } + + .irq_stacks (NOLOAD): + { + . = ALIGN(64); + . = . + 4 * 1024; + __irq_stack = .; + _stack_init_irq = .; + } + + _end = .; + + .pagetable 0x80100000 (NOLOAD): + { + _page_table_top = .; + __pagetable_start = .; + . = . + 0x4000; + } +} diff --git a/ports_smp/cortex_a7_smp/gnu/example_build/startup.S b/ports_smp/cortex_a7_smp/gnu/example_build/startup.S new file mode 100644 index 00000000..eea0efd7 --- /dev/null +++ b/ports_smp/cortex_a7_smp/gnu/example_build/startup.S @@ -0,0 +1,693 @@ +@; ------------------------------------------------------------ +@; Cortex-A15 MPCore SMP Prime Number Generator Example +@; +@; Copyright (c) 2011-2012 ARM Ltd. All rights reserved. +@; ------------------------------------------------------------ +@ +@ PRESERVE8 +@ +@ AREA StartUp,CODE,READONLY +@ +@; Standard definitions of mode bits and interrupt (I&F) flags in PSRs +@ +Mode_USR = 0x10 +Mode_FIQ = 0x11 +Mode_IRQ = 0x12 +Mode_SVC = 0x13 +Mode_ABT = 0x17 +Mode_UNDEF = 0x1B +Mode_SYS = 0x1F + +I_Bit = 0x80 @ when I bit is set, IRQ is disabled +F_Bit = 0x40 @ when F bit is set, FIQ is disabled + +SYS_MODE = 0xDF +SVC_MODE = 0xD3 +IRQ_MODE = 0xD2 + +@; ------------------------------------------------------------ +@; Porting defines +@; ------------------------------------------------------------ +@ +L1_COHERENT = 0x00014c06 @ Template descriptor for coherent memory +L1_NONCOHERENT = 0x00000c1e @ Template descriptor for non-coherent memory +L1_DEVICE = 0x00000c06 @ Template descriptor for device memory + +.section VECTORS, "ax" +.align 3 +.cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame + +@; ------------------------------------------------------------ +@ +@ ENTRY +@ + .global Vectors +Vectors: + B Reset_Handler + B Undefined_Handler + B SVC_Handler + B Prefetch_Handler + B Abort_Handler + B Hypervisor_Handler + B IRQ_Handler + B FIQ_Handler + +@; ------------------------------------------------------------ +@; Handlers for unused exceptions +@; ------------------------------------------------------------ +@ +Undefined_Handler: + B Undefined_Handler +SVC_Handler: + B SVC_Handler +Prefetch_Handler: + B Prefetch_Handler +Abort_Handler: + B Abort_Handler +Hypervisor_Handler: + B Hypervisor_Handler +FIQ_Handler: + B FIQ_Handler + +@; ------------------------------------------------------------ +@; Imports +@; ------------------------------------------------------------ + .global readIntAck + .global writeEOI + .global enableGIC + .global enableGICProcessorInterface + .global setPriorityMask + .global enableIntID + .global setIntPriority + .global joinSMP + + .global invalidateCaches + .global disableHighVecs + .global _start +@; [Grape Change Start] +@; IMPORT main_app + + .global _tx_thread_smp_initialize_wait + .global _tx_thread_smp_release_cores_flag + .global _tx_thread_context_save + .global _tx_thread_context_restore + .global _tx_timer_interrupt + .global _tx_thread_smp_inter_core_interrupts + + .global enableBranchPrediction + .global enableCaches + +VFPEnable = 0x40000000 @ VFP enable value + +@;/*------------------------------------------------------------------------*/ +@;/*--- Versatile Express(Timer0) ---*/ +GIC_DIST_CPUTARGET = 0x2C001820 +GIC_DIST_CPUTARGET_VALUE = 0x000f0000 + +GIC_DIST_CONFIG = 0x2C001C08 +GIC_DIST_CONFIG_VALUE = 0x00000000 + +GIC_DIST_PRIO = 0x2C001420 +GIC_DIST_PRIO_VALUE = 0x00a00000 + +GIC_DIST_CONTROL = 0x2C001000 +GIC_DIST_CONTROL_VALUE = 0x00000001 + +GIC_CPU_CONTROL = 0x2C002000 +GIC_CPU_CONTROL_VALUE = 0x00000001 + +GIC_CPU_PRIO_MASK = 0x2C002004 +GIC_CPU_PRIO_MASK_VALUE = 0x000000ff + +GIC_DIST_ENABLE_SET = 0x2C001104 +GIC_DIST_ENABLE_SET_VALUE = 0x00000004 + +GIC_CPU_INTACK = 0x2C00200C +GIC_CPU_EOI = 0x2C002010 +; +; +; +TIMCLK_CTRL = 0x1C020000 +TIMCLK_CTRL_VALUE = 0x00028000 @ Use EXTCLK (1MHz) for TIMCLK not REFCLK32KHZ + +TIMER_LOAD = 0x1C110000 +TIMER_LOAD_VALUE = 0x00000140 @ 10ms + +TIMER_CTRL = 0x1C110008 +TIMER_CTRL_STOP = 0x00000020 +TIMER_CTRL_VALUE = 0x000000E0 +TIMER_ACK = 34 @ Timer0 +TIMER_INT_CLR = 0x1C11000C +; +HANDLER_SET = 0x80000018 +HANDLER_SET_VALUE = 0xE59FF018 +HANDLER_ADDRESS = 0x80000038 @ irq + +@;/*--- Versatile Express(Timer0) ---*/ +@;/*------------------------------------------------------------------------*/ +@; [Grape Change End] + + .global _page_table_top + .global _exec + .global _stack_init_irq + .global _stack_init_usr + +@; ------------------------------------------------------------ +@; Interrupt Handler +@; ------------------------------------------------------------ +@ +@ EXPORT IRQ_Handler + .align 2 + .global IRQ_Handler + .type IRQ_Handler,function +IRQ_Handler: +@; [Grape Change Start] + .global __tx_irq_processing_return +@; SUB lr, lr, #4 ; Pre-adjust lr +@; SRSFD sp!, #Mode_IRQ ; Save lr and SPRS to IRQ mode stack +@; PUSH {r0-r4, r12} ; Save APCS corruptible registers to IRQ mode stack (and maintain 8 byte alignment) +@; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return: + PUSH {r4, r5} @ Save some preserved registers (r5 is saved just for 8-byte alignment) +@; [Grape Change End] + + @ Acknowledge the interrupt + BL readIntAck + MOV r4, r0 + +@ ; +@ ; This example only uses (and enables) one. At this point +@ ; you would normally check the ID, and clear the source. +@ ; + +@; [Grape Change Start] +@;/*------------------------------------------------------------------------*/ +@;/*--- Versatile Express(Timer0) ---*/ + LDR r0, =TIMER_ACK @ Setup timer acknowledge number + CMP r4, r0 + BNE by_pass + + LDR r0, =TIMER_INT_CLR @ Setup Timer interrupt clear register address + LDR r1, =1 + STR r1, [r0, #0] @ Clear timer interrupt + + BL _tx_timer_interrupt @ Timer interrupt handler + B by_pass2 +@;/*--- Versatile Express(Timer0) ---*/ +@;/*------------------------------------------------------------------------*/ + +by_pass: +@; /* Just increment the per-thread interrupt count for analysis purposes. */ +@; + MRC p15, 0, r0, c0, c0, 5 @ Read CPU ID register + AND r0, r0, #0x03 @ Mask off, leaving the CPU ID field + LSL r0, r0, #2 @ Build offset to array indexes + LDR r1,=_tx_thread_smp_inter_core_interrupts @ Pickup base address of core interrupt counter array + ADD r1, r1, r0 @ Build array index + LDR r0, [r1] @ Pickup counter + ADD r0, r0, #1 @ Increment counter + STR r0, [r1] @ Store back counter + +@;/* user handler */ + + +@;/*------------------------------------------------------------------------*/ +@; [Grape Change End] +@ +@ +@; [Grape Change Start] +by_pass2: + @ Write end of interrupt reg + MOV r0, r4 + BL writeEOI + +@; POP {r0-r4, r12} ; Restore stacked APCS registers +@; MOV r2, #0x01 ; Set r2 so CPU leaves holding pen +@; RFEFD sp! ; Return from exception +@;;;;; +@; /* Jump to context restore to restore system context. */ + POP {r4, r5} @ Recover preserved registers + B _tx_thread_context_restore +@; [Grape Change End] + + + +@; ------------------------------------------------------------ +@; Reset Handler - Generic initialization, run by all CPUs +@; ------------------------------------------------------------ +@ +@ EXPORT Reset_Handler + .align 2 + .global $Reset_Handler + .type $Reset_Handler,function +Reset_Handler: + +@ ; +@ ; Set ACTLR.SMP bit +@ ; ------------------ + BL joinSMP + +@; +@; Disable caches, MMU and branch prediction in case they were left enabled from an earlier run +@; This does not need to be done from a cold reset +@; ------------------------------------------------------------ + MRC p15, 0, r0, c1, c0, 0 @ Read CP15 System Control register + BIC r0, r0, #(0x1 << 12) @ Clear I bit 12 to disable I Cache + BIC r0, r0, #(0x1 << 2) @ Clear C bit 2 to disable D Cache + BIC r0, r0, #0x1 @ Clear M bit 0 to disable MMU + BIC r0, r0, #(0x1 << 11) @ Clear Z bit 11 to disable branch prediction + MCR p15, 0, r0, c1, c0, 0 @ Write CP15 System Control register + +@; The MMU is enabled later, before calling main(). Caches and branch prediction are enabled inside main(), +@; after the MMU has been enabled and scatterloading has been performed. +@ +@ ; +@ ; Setup stacks +@ ;--------------- + + MRC p15, 0, r0, c0, c0, 5 @ Read CPU ID register + ANDS r0, r0, #0x03 @ Mask off, leaving the CPU ID field + +@; [Grape Change Start] +@; MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit +@; LDR r1, =_stack_init_irq ; IRQ stacks for CPU 0,1,2,3 +@; SUB r1, r1, r0, LSL #8 ; 256 bytes of IRQ stack per CPU (0,1,2,3) - see scatter.scat +@; MOV sp, r1 +@; +@; MSR CPSR_c, #Mode_SYS:OR:I_Bit:OR:F_Bit ; Interrupts initially disabled +@; LDR r1, =_stack_init_usr ; App stacks for all CPUs +@; SUB r1, r1, r0, LSL #12 ; 0x1000 bytes of App stack per CPU - see scatter.scat +@; MOV sp, r1 + + + MOV r1, #IRQ_MODE @ Build IRQ mode CPSR + MSR CPSR_c, r1 @ Enter IRQ mode +@ MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit + LDR r1, =_stack_init_irq @ IRQ stacks for CPU 0,1,2,3 + SUB r1, r1, r0, LSL #10 @ 1024 bytes of IRQ stack per CPU (0,1,2,3) - see scatter.scat + MOV sp, r1 + + MOV r1, #SYS_MODE @ Build SYS mode CPSR + MSR CPSR_c, r1 @ Enter SYS mode +@ MSR CPSR_c, #Mode_SYS:OR:I_Bit:OR:F_Bit @ Interrupts initially disabled + LDR r1, =_stack_init_usr @ App stacks for all CPUs + SUB r1, r1, r0, LSL #12 @ 0x1000 bytes of App stack per CPU - see scatter.scat + MOV sp, r1 + + MOV r2, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r2 @ Enter SVC mode +@ MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit @ Interrupts initially disabled + MOV sp, r1 +@; [Grape Change End] +@ +@ ; +@ ; Set vector base address +@ ; ------------------------ + LDR r0, =Vectors + MCR p15, 0, r0, c12, c0, 0 @ Write Secure or Non-secure Vector Base Address + BL disableHighVecs @ Ensure that V-bit is cleared + +@ ; +@ ; Invalidate caches +@ ; ------------------ + BL invalidateCaches + +@ ; +@ ; Clear Branch Prediction Array +@ ; ------------------------------ + MOV r0, #0x0 + MCR p15, 0, r0, c7, c5, 6 @ BPIALL - Invalidate entire branch predictor array + +@; [Grape Change Start] +@; ; Disable loop-buffer to fix errata on A15 r0p0 +@; MRC p15, 0, r0, c0, c0, 0 ; Read main ID register MIDR +@; MOV r1, r0, lsr #4 ; Extract Primary Part Number +@; LDR r2, =0xFFF +@; AND r1, r1, r2 +@; LDR r2, =0xC0F +@; CMP r1, r2 ; Is this an A15? +@; BNE notA15r0p0 ; Jump if not A15 +@; AND r5, r0, #0x00f00000 ; Variant +@; AND r6, r0, #0x0000000f ; Revision +@; ORRS r6, r6, r5 ; Combine variant and revision +@; BNE notA15r0p0 ; Jump if not r0p0 +@; MRC p15, 0, r0, c1, c0, 1 ; Read Aux Ctrl Reg +@; ORR r0, r0, #(1 << 1) ; Set bit 1 to Disable Loop Buffer +@; MCR p15, 0, r0, c1, c0, 1 ; Write Aux Ctrl Reg +@; ISB +@;notA15r0p0 +@; [Grape Change End] +@ +@ ; +@ ; Invalidate TLBs +@ ;------------------ + MOV r0, #0x0 + MCR p15, 0, r0, c8, c7, 0 @ TLBIALL - Invalidate entire Unified TLB + +@ ; +@ ; Set up Domain Access Control Reg +@ ; ---------------------------------- +@ ; b00 - No Access (abort) +@ ; b01 - Client (respect table entry) +@ ; b10 - RESERVED +@ ; b11 - Manager (ignore access permissions) + + MRC p15, 0, r0, c3, c0, 0 @ Read Domain Access Control Register + LDR r0, =0x55555555 @ Initialize every domain entry to b01 (client) + MCR p15, 0, r0, c3, c0, 0 @ Write Domain Access Control Register + +@ ;; +@ ;; Enable L1 Preloader - Auxiliary Control +@ ;; ----------------------------------------- +@ ;; Seems to undef on panda? +@ ;MRC p15, 0, r0, c1, c0, 1 ; Read ACTLR +@ ;ORR r0, r0, #0x4 +@ ;MCR p15, 0, r0, c1, c0, 1 ; Write ACTLR +@ +@ ; Page tables +@ ; ------------------------- +@ ; Each CPU will have its own L1 page table. The +@ ; code reads the base address from the scatter file +@ ; the uses the CPUID to calculate an offset for each +@ ; CPU. +@ ; +@ ; The page tables are generated at boot time. First +@ ; the table is zeroed. Then the individual valid +@ ; entries are written in +@ ; +@ +@ ; Calculate offset for this CPU + LDR r0, =_page_table_top + MRC p15, 0, r1, c0, c0, 5 @ Read Multiprocessor Affinity Register + ANDS r1, r1, #0x03 @ Mask off, leaving the CPU ID field + MOV r1, r1, LSL #14 @ Convert core ID into a 16K offset (this is the size of the table) + ADD r0, r1, r0 @ Add offset to current table location to get dst + + @ Fill table with zeros + MOV r2, #1024 @ Set r3 to loop count (4 entries per iteration, 1024 iterations) + MOV r1, r0 @ Make a copy of the base dst + MOV r3, #0 + MOV r4, #0 + MOV r5, #0 + MOV r6, #0 +ttb_zero_loop: + STMIA r1!, {r3-r6} @ Store out four entries + SUBS r2, r2, #1 @ Decrement counter + BNE ttb_zero_loop + +@ ; +@ ; STANDARD ENTRIES +@ ; +@ +@ ; Entry for VA 0x0 +@ ; This region must be coherent +@ ;LDR r1, =PABASE_VA0 ; Physical address +@ ;LDR r2, =L1_COHERENT ; Descriptor template +@ ;ORR r1, r1, r2 ; Combine address and template +@ ;STR r1, [r0] +@ +@ +@ ; If not flat mapping, you need a page table entry covering +@ ; the physical address of the boot code. +@ ; This region must be coherent + LDR r1,=_exec @ Base physical address of code segment + LSR r1,#20 @ Shift right to align to 1MB boundaries + LDR r3, =L1_COHERENT @ Descriptor template + ORR r3, r1, LSL#20 @ Setup the initial level1 descriptor again + STR r3, [r0, r1, LSL#2] @ str table entry + +@; [Grape Change Start] +@;/*------------------------------------------------------------------------*/ +@;/*--- Versatile Express(Timer0) ---*/ + LDR r1, =0x80000000 @ Physical address of HANDLER + LSR r1, r1, #20 @ Clear bottom 20 bits, to find which 1MB block it is in + LSL r2, r1, #2 @ Make a copy, and multiply by four. This gives offset into the page tables + LSL r1, r1, #20 @ Put back in address format + + LDR r3, =L1_COHERENT @ Descriptor template + ORR r1, r1, r3 @ Combine address and template + STR r1, [r0, r2] + + LDR r1, =0x2C000000 @ Physical address of GIC_DIST + LSR r1, r1, #20 @ Clear bottom 20 bits, to find which 1MB block it is in + LSL r2, r1, #2 @ Make a copy, and multiply by four. This gives offset into the page tables + LSL r1, r1, #20 @ Put back in address format + + LDR r3, =L1_DEVICE @ Descriptor template + ORR r1, r1, r3 @ Combine address and template + STR r1, [r0, r2] + + LDR r1, =0x1C000000 @ Physical address of TIMER + LSR r1, r1, #20 @ Clear bottom 20 bits, to find which 1MB block it is in + LSL r2, r1, #2 @ Make a copy, and multiply by four. This gives offset into the page tables + LSL r1, r1, #20 @ Put back in address format + + LDR r3, =L1_DEVICE @ Descriptor template + ORR r1, r1, r3 @ Combine address and template + STR r1, [r0, r2] + + LDR r1, =0x1C100000 @ Physical address of TIMER + LSR r1, r1, #20 @ Clear bottom 20 bits, to find which 1MB block it is in + LSL r2, r1, #2 @ Make a copy, and multiply by four. This gives offset into the page tables + LSL r1, r1, #20 @ Put back in address format + + LDR r3, =L1_DEVICE @ Descriptor template + ORR r1, r1, r3 @ Combine address and template + STR r1, [r0, r2] +@;/*--- Versatile Express(Timer0) ---*/ +@;/*------------------------------------------------------------------------*/ +@; [Grape Change End] +@ +@ ; Entry for private address space +@ ; Needs to be marked as Device memory + MRC p15, 4, r1, c15, c0, 0 @ Get base address of private address space + LSR r1, r1, #20 @ Clear bottom 20 bits, to find which 1MB block it is in + LSL r2, r1, #2 @ Make a copy, and multiply by four. This gives offset into the page tables + LSL r1, r1, #20 @ Put back in address format + + LDR r3, =L1_DEVICE @ Descriptor template + ORR r1, r1, r3 @ Combine address and template + STR r1, [r0, r2] + +@ ; +@ ; OPTIONAL ENTRIES +@ ; You will need additional translations if: +@ ; - No RAM at zero, so cannot use flat mapping +@ ; - You wish to retarget +@ ; +@ ; If you wish to output to stdio to a UART you will need +@ ; an additional entry +@ ;LDR r1, =PABASE_UART ; Physical address of UART +@ ;LSR r1, r1, #20 ; Mask off bottom 20 bits to find which 1MB it is within +@ ;LSL r2, r1, #2 ; Make a copy and multiply by 4 to get table offset +@ ;LSL r1, r1, #20 ; Put back into address format +@ ;LDR r3, =L1_DEVICE ; Descriptor template +@ ;ORR r1, r1, r3 ; Combine address and template +@ ;STR r1, [r0, r2] +@ +@ ; +@ ; Barrier +@ ; -------- + DSB + +@ ; +@ ; Set location of level 1 page table +@ ;------------------------------------ +@ ; 31:14 - Base addr: 0x8050,0000 (CPU0), 0x8050,4000 (CPU1) +@ ; 13:5 - 0x0 +@ ; 4:3 - RGN 0x0 (Outer Noncachable) +@ ; 2 - P 0x0 +@ ; 1 - S 0x0 (Non-shared) +@ ; 0 - C 0x0 (Inner Noncachable) + MCR p15, 0, r0, c2, c0 ,0 + + +@ ; Enable MMU +@ ;------------- +@ ; Leaving the caches disabled until after scatter loading. + MRC p15, 0, r0, c1, c0, 0 @ Read CP15 System Control register + BIC r0, r0, #(0x1 << 12) @ Clear I bit 12 to disable I Cache + BIC r0, r0, #(0x1 << 2) @ Clear C bit 2 to disable D Cache + BIC r0, r0, #0x2 @ Clear A bit 1 to disable strict alignment fault checking + ORR r0, r0, #0x1 @ Set M bit 0 to enable MMU before scatter loading + MCR p15, 0, r0, c1, c0, 0 @ Write CP15 System Control register + +@ ; +@ ; MMU now enabled - Virtual address system now active +@ ; +@; [Grape Change Start] +#ifdef TARGET_FPU_VFP + MRC p15, 0, r1, c1, c0, 2 @ r1 = Access Control Register + ORR r1, r1, #(0xf << 20) @ Enable full access for p10,11 + MCR p15, 0, r1, c1, c0, 2 @ Access Control Register = r1 + MOV r1, #0 + MCR p15, 0, r1, c7, c5, 4 @ Flush prefetch buffer because of FMXR below and + @ CP 10 & 11 were only just enabled + MOV r0, #VFPEnable @ Enable VFP itself + FMXR FPEXC, r0 @ FPEXC = r0 +#endif + + LDR r0, =_tx_thread_smp_release_cores_flag @ Build address of release cores flag + MOV r1, #0 + STR r1, [r0] +@; [Grape Change End] +@ +@ ; +@ ; SMP initialization +@ ; ------------------- + MRC p15, 0, r0, c0, c0, 5 @ Read CPU ID register + ANDS r0, r0, #0x03 @ Mask off, leaving the CPU ID field + BEQ primaryCPUInit + BNE secondaryCPUsInit + + + + +@; ------------------------------------------------------------ +@; Initialization for PRIMARY CPU +@; ------------------------------------------------------------ +@ +@ +@ EXPORT primaryCPUInit + .align 2 + .global primaryCPUInit + .type primaryCPUInit,function +primaryCPUInit: + +@ ; +@ ; GIC Init +@ ; --------- + BL enableGIC + BL enableGICProcessorInterface + + BL enableCaches + +@; /* Setup Timer for periodic interrupts. */ +@;/*------------------------------------------------------------------------*/ +@;/*--- Versatile Express(Timer0) ---*/ + LDR r0, =GIC_DIST_CPUTARGET + LDR r2, =GIC_DIST_CPUTARGET_VALUE + STR r2, [r0, #0] + + LDR r0, =GIC_DIST_CONFIG + LDR r2, =GIC_DIST_CONFIG_VALUE + STR r2, [r0, #0] + + LDR r0, =GIC_DIST_PRIO + LDR r2, =GIC_DIST_PRIO_VALUE + STR r2, [r0, #0] + + LDR r0, =GIC_DIST_CONTROL + LDR r2, =GIC_DIST_CONTROL_VALUE + STR r2, [r0, #0] + + LDR r0, =GIC_CPU_CONTROL + LDR r2, =GIC_CPU_CONTROL_VALUE + STR r2, [r0, #0] + + LDR r0, =GIC_CPU_PRIO_MASK + LDR r2, =GIC_CPU_PRIO_MASK_VALUE + STR r2, [r0, #0] + + LDR r0, =GIC_DIST_ENABLE_SET + LDR r2, =GIC_DIST_ENABLE_SET_VALUE + STR r2, [r0, #0] +@;;;;; + LDR r0, =HANDLER_SET + LDR r2, =HANDLER_SET_VALUE + STR r2, [r0, #0] +@; +@; LDR r0, =HANDLER_ADDRESS +@; LDR r2, =IRQ_Handler +@; STR r2, [r0, #0] +@;;;;; + LDR r0, =TIMER_CTRL + LDR r2, =TIMER_CTRL_STOP + STR r2, [r0, #0] + + LDR r2, =TIMER_INT_CLR + LDR r0, =1 + STR r0, [r2, #0] + + LDR r0, =TIMER_LOAD + LDR r2, =TIMER_LOAD_VALUE + STR r2, [r0, #0] + + LDR r0, =TIMER_CTRL + LDR r2, =TIMER_CTRL_VALUE + STR r2, [r0, #0] +@;/*--- Versatile Express(Timer0) ---*/ +@;/*------------------------------------------------------------------------*/ + +@ ; +@ ; Branch to C lib code +@ ; ---------------------- + B _start + +@; [Grape Change End] + + +@; ------------------------------------------------------------ +@; Initialization for SECONDARY CPUs +@; ------------------------------------------------------------ +@ +@ EXPORT secondaryCPUsInit + .align 2 + .global secondaryCPUsInit + .type secondaryCPUsInit,function +secondaryCPUsInit: + +@ ; +@ ; GIC Init +@ ; --------- + BL enableGICProcessorInterface + + MOV r0, #0x1F @ Priority + BL setPriorityMask + + MOV r0, #0x0 @ ID + BL enableIntID + + MOV r0, #0x0 @ ID + MOV r1, #0x0 @ Priority + BL setIntPriority + + +@ ; +@ ; Holding Pen +@ ; ------------ +@; [Grape Change Start] +@; MOV r2, #0x00 ; Clear r2 +@; CPSIE i ; Enable interrupts +@;holding_pen +@; CMP r2, #0x0 ; r2 will be set to 0x1 by IRQ handler on receiving SGI +@; WFIEQ +@; BEQ holding_pen +@; CPSID i ; IRQs not used in rest of example, so mask out interrupts +@; [Grape Change End] +@ +@ +@ ; +@ ; Branch to application +@ ; ---------------------- +@; [Grape Change Start] +@; B main_app + +@; BL enableBranchPrediction + BL enableCaches + + B _tx_thread_smp_initialize_wait +@; [Grape Change End] +@ + + +@; ------------------------------------------------------------ +@; End of code +@; ------------------------------------------------------------ +@ +@ END +@ +@; ------------------------------------------------------------ +@; End of startup.s +@; ------------------------------------------------------------ diff --git a/ports_smp/cortex_a7_smp/gnu/example_build/tx_initialize_low_level.S b/ports_smp/cortex_a7_smp/gnu/example_build/tx_initialize_low_level.S new file mode 100644 index 00000000..9a4b9946 --- /dev/null +++ b/ports_smp/cortex_a7_smp/gnu/example_build/tx_initialize_low_level.S @@ -0,0 +1,141 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Initialize */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_initialize.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ +@ +@ + + .arm + + .global _tx_thread_system_stack_ptr + .global _tx_initialize_unused_memory + .global _tx_version_id + .global _tx_build_options + .global _end +@ +@ + +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_initialize_low_level for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .thumb + .global $_tx_initialize_low_level + .type $_tx_initialize_low_level,function +$_tx_initialize_low_level: + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_initialize_low_level @ Call _tx_initialize_low_level function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_initialize_low_level MPCore/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for any low-level processor */ +@/* initialization, including setting up interrupt vectors, setting */ +@/* up a periodic timer interrupt source, saving the system stack */ +@/* pointer for use in ISR processing later, and finding the first */ +@/* available RAM memory address for tx_application_define. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_initialize_low_level(VOID) +@{ + .global _tx_initialize_low_level + .type _tx_initialize_low_level,function +_tx_initialize_low_level: +@ +@ /* Save the first available memory address. */ +@ _tx_initialize_unused_memory = (VOID_PTR) _end; +@ + LDR r1, =_end @ Get end of non-initialized RAM area + LDR r2, =_tx_initialize_unused_memory @ Pickup unused memory ptr address + ADD r1, r1, #8 @ Increment to next free word + STR r1, [r2] @ Save first free memory address +@ +@ + +@ /* Done, return to caller. */ +@ +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} +@ +BUILD_OPTIONS: + .word _tx_build_options @ Reference to bring in +VERSION_ID: + .word _tx_version_id @ Reference to bring in + + diff --git a/ports_smp/cortex_a7_smp/gnu/example_build/v7.S b/ports_smp/cortex_a7_smp/gnu/example_build/v7.S new file mode 100644 index 00000000..ad238f56 --- /dev/null +++ b/ports_smp/cortex_a7_smp/gnu/example_build/v7.S @@ -0,0 +1,554 @@ +@; ------------------------------------------------------------ +@; v7-A Cache and Branch Prediction Maintenance Operations +@; +@; Copyright (c) 2011 ARM Ltd. All rights reserved. +@; ------------------------------------------------------------ +@ +@ PRESERVE8 +@ +@ AREA v7Opps,CODE,READONLY + + .arm + .text + +@; ------------------------------------------------------------ +@; Interrupt enable/disable +@; ------------------------------------------------------------ +@ +@ ; Could use intrinsic instead of these +@ +@ EXPORT enableInterrupts +@ ; void enableInterrupts(void); + .align 2 + .global enableInterrupts + .type enableInterrupts,function +enableInterrupts: + CPSIE i + BX lr + + +@ EXPORT disableInterrupts +@ ; void disableInterrupts(void); + .align 2 + .global disableInterrupts + .type disableInterrupts,function +disableInterrupts: + CPSID i + BX lr + + +@; ------------------------------------------------------------ +@; Cache Maintenance +@; ------------------------------------------------------------ +@ +@ EXPORT enableCaches +@ ; void enableCaches(void); + .align 2 + .global enableCaches + .type enableCaches,function +enableCaches: + MRC p15, 0, r0, c1, c0, 0 @ Read System Control Register configuration data + ORR r0, r0, #(1 << 2) @ Set C bit + ORR r0, r0, #(1 << 12) @ Set I bit + MCR p15, 0, r0, c1, c0, 0 @ Write System Control Register configuration data + BX lr + + + +@ EXPORT disableCaches +@ ; void disableCaches(void) + .align 2 + .global disableCaches + .type disableCaches,function +disableCaches: + MRC p15, 0, r0, c1, c0, 0 @ Read System Control Register configuration data + BIC r0, r0, #(1 << 2) @ Clear C bit + BIC r0, r0, #(1 << 12) @ Clear I bit + MCR p15, 0, r0, c1, c0, 0 @ Write System Control Register configuration data + BX lr + + +@ EXPORT cleanDCache +@ ; void cleanDCache(void); + .align 2 + .global cleanDCache + .type cleanDCache,function +cleanDCache: + PUSH {r4-r12} + + @ + @ Based on code example given in section 11.2.4 of ARM DDI 0406B + @ + + MRC p15, 1, r0, c0, c0, 1 @ Read CLIDR + ANDS r3, r0, #0x07000000 + MOV r3, r3, LSR #23 @ Cache level value (naturally aligned) + BEQ clean_dcache_finished + MOV r10, #0 + +clean_dcache_loop1: + ADD r2, r10, r10, LSR #1 @ Work out 3xcachelevel + MOV r1, r0, LSR r2 @ bottom 3 bits are the Cache type for this level + AND r1, r1, #7 @ get those 3 bits alone + CMP r1, #2 + BLT clean_dcache_skip @ no cache or only instruction cache at this level + MCR p15, 2, r10, c0, c0, 0 @ write the Cache Size selection register + ISB @ ISB to sync the change to the CacheSizeID reg + MRC p15, 1, r1, c0, c0, 0 @ reads current Cache Size ID register + AND r2, r1, #0x07 @ extract the line length field + ADD r2, r2, #4 @ add 4 for the line length offset (log2 16 bytes) + LDR r4, =0x3FF + ANDS r4, r4, r1, LSR #3 @ R4 is the max number on the way size (right aligned) + CLZ r5, r4 @ R5 is the bit position of the way size increment + LDR r7, =0x00007FFF + ANDS r7, r7, r1, LSR #13 @ R7 is the max number of the index size (right aligned) + +clean_dcache_loop2: + MOV r9, R4 @ R9 working copy of the max way size (right aligned) + +clean_dcache_loop3: + ORR r11, r10, r9, LSL r5 @ factor in the way number and cache number into R11 + ORR r11, r11, r7, LSL r2 @ factor in the index number + MCR p15, 0, r11, c7, c10, 2 @ DCCSW - clean by set/way + SUBS r9, r9, #1 @ decrement the way number + BGE clean_dcache_loop3 + SUBS r7, r7, #1 @ decrement the index + BGE clean_dcache_loop2 + +clean_dcache_skip: + ADD r10, r10, #2 @ increment the cache number + CMP r3, r10 + BGT clean_dcache_loop1 + +clean_dcache_finished: + POP {r4-r12} + + BX lr + + +@ EXPORT cleanInvalidateDCache +@ ; void cleanInvalidateDCache(void); + .align 2 + .global cleanInvalidateDCache + .type cleanInvalidateDCache,function +cleanInvalidateDCache: + PUSH {r4-r12} + + @ + @ Based on code example given in section 11.2.4 of ARM DDI 0406B + @ + + MRC p15, 1, r0, c0, c0, 1 @ Read CLIDR + ANDS r3, r0, #0x07000000 + MOV r3, r3, LSR #23 @ Cache level value (naturally aligned) + BEQ clean_invalidate_dcache_finished + MOV r10, #0 + +clean_invalidate_dcache_loop1: + ADD r2, r10, r10, LSR #1 @ Work out 3xcachelevel + MOV r1, r0, LSR r2 @ bottom 3 bits are the Cache type for this level + AND r1, r1, #7 @ get those 3 bits alone + CMP r1, #2 + BLT clean_invalidate_dcache_skip @ no cache or only instruction cache at this level + MCR p15, 2, r10, c0, c0, 0 @ write the Cache Size selection register + ISB @ ISB to sync the change to the CacheSizeID reg + MRC p15, 1, r1, c0, c0, 0 @ reads current Cache Size ID register + AND r2, r1, #0x07 @ extract the line length field + ADD r2, r2, #4 @ add 4 for the line length offset (log2 16 bytes) + LDR r4, =0x3FF + ANDS r4, r4, r1, LSR #3 @ R4 is the max number on the way size (right aligned) + CLZ r5, r4 @ R5 is the bit position of the way size increment + LDR r7, =0x00007FFF + ANDS r7, r7, r1, LSR #13 @ R7 is the max number of the index size (right aligned) + +clean_invalidate_dcache_loop2: + MOV r9, R4 @ R9 working copy of the max way size (right aligned) + +clean_invalidate_dcache_loop3: + ORR r11, r10, r9, LSL r5 @ factor in the way number and cache number into R11 + ORR r11, r11, r7, LSL r2 @ factor in the index number + MCR p15, 0, r11, c7, c14, 2 @ DCCISW - clean and invalidate by set/way + SUBS r9, r9, #1 @ decrement the way number + BGE clean_invalidate_dcache_loop3 + SUBS r7, r7, #1 @ decrement the index + BGE clean_invalidate_dcache_loop2 + +clean_invalidate_dcache_skip: + ADD r10, r10, #2 @ increment the cache number + CMP r3, r10 + BGT clean_invalidate_dcache_loop1 + +clean_invalidate_dcache_finished: + POP {r4-r12} + + BX lr + + + +@ EXPORT invalidateCaches +@ ; void invalidateCaches(void); + .align 2 + .global invalidateCaches + .type invalidateCaches,function +invalidateCaches: + PUSH {r4-r12} + + @ + @ Based on code example given in section B2.2.4/11.2.4 of ARM DDI 0406B + @ + + MOV r0, #0 + MCR p15, 0, r0, c7, c5, 0 @ ICIALLU - Invalidate entire I Cache, and flushes branch target cache + + MRC p15, 1, r0, c0, c0, 1 @ Read CLIDR + ANDS r3, r0, #0x07000000 + MOV r3, r3, LSR #23 @ Cache level value (naturally aligned) + BEQ invalidate_caches_finished + MOV r10, #0 + +invalidate_caches_loop1: + ADD r2, r10, r10, LSR #1 @ Work out 3xcachelevel + MOV r1, r0, LSR r2 @ bottom 3 bits are the Cache type for this level + AND r1, r1, #7 @ get those 3 bits alone + CMP r1, #2 + BLT invalidate_caches_skip @ no cache or only instruction cache at this level + MCR p15, 2, r10, c0, c0, 0 @ write the Cache Size selection register + ISB @ ISB to sync the change to the CacheSizeID reg + MRC p15, 1, r1, c0, c0, 0 @ reads current Cache Size ID register + AND r2, r1, #0x07 @ extract the line length field + ADD r2, r2, #4 @ add 4 for the line length offset (log2 16 bytes) + LDR r4, =0x3FF + ANDS r4, r4, r1, LSR #3 @ R4 is the max number on the way size (right aligned) + CLZ r5, r4 @ R5 is the bit position of the way size increment + LDR r7, =0x00007FFF + ANDS r7, r7, r1, LSR #13 @ R7 is the max number of the index size (right aligned) + +invalidate_caches_loop2: + MOV r9, R4 @ R9 working copy of the max way size (right aligned) + +invalidate_caches_loop3: + ORR r11, r10, r9, LSL r5 @ factor in the way number and cache number into R11 + ORR r11, r11, r7, LSL r2 @ factor in the index number + MCR p15, 0, r11, c7, c6, 2 @ DCISW - invalidate by set/way + SUBS r9, r9, #1 @ decrement the way number + BGE invalidate_caches_loop3 + SUBS r7, r7, #1 @ decrement the index + BGE invalidate_caches_loop2 + +invalidate_caches_skip: + ADD r10, r10, #2 @ increment the cache number + CMP r3, r10 + BGT invalidate_caches_loop1 + +invalidate_caches_finished: + POP {r4-r12} + BX lr + + +@ EXPORT invalidateCaches_IS +@ ; void invalidateCaches_IS(void); + .align 2 + .global invalidateCaches_IS + .type invalidateCaches_IS,function +invalidateCaches_IS: + PUSH {r4-r12} + + MOV r0, #0 + MCR p15, 0, r0, c7, c1, 0 @ ICIALLUIS - Invalidate entire I Cache inner shareable + + MRC p15, 1, r0, c0, c0, 1 @ Read CLIDR + ANDS r3, r0, #0x07000000 + MOV r3, r3, LSR #23 @ Cache level value (naturally aligned) + BEQ invalidate_caches_is_finished + MOV r10, #0 + +invalidate_caches_is_loop1: + ADD r2, r10, r10, LSR #1 @ Work out 3xcachelevel + MOV r1, r0, LSR r2 @ bottom 3 bits are the Cache type for this level + AND r1, r1, #7 @ get those 3 bits alone + CMP r1, #2 + BLT invalidate_caches_is_skip @ no cache or only instruction cache at this level + MCR p15, 2, r10, c0, c0, 0 @ write the Cache Size selection register + ISB @ ISB to sync the change to the CacheSizeID reg + MRC p15, 1, r1, c0, c0, 0 @ reads current Cache Size ID register + AND r2, r1, #0x07 @ extract the line length field + ADD r2, r2, #4 @ add 4 for the line length offset (log2 16 bytes) + LDR r4, =0x3FF + ANDS r4, r4, r1, LSR #3 @ R4 is the max number on the way size (right aligned) + CLZ r5, r4 @ R5 is the bit position of the way size increment + LDR r7, =0x00007FFF + ANDS r7, r7, r1, LSR #13 @ R7 is the max number of the index size (right aligned) + +invalidate_caches_is_loop2: + MOV r9, R4 @ R9 working copy of the max way size (right aligned) + +invalidate_caches_is_loop3: + ORR r11, r10, r9, LSL r5 @ factor in the way number and cache number into R11 + ORR r11, r11, r7, LSL r2 @ factor in the index number + MCR p15, 0, r11, c7, c6, 2 @ DCISW - clean by set/way + SUBS r9, r9, #1 @ decrement the way number + BGE invalidate_caches_is_loop3 + SUBS r7, r7, #1 @ decrement the index + BGE invalidate_caches_is_loop2 + +invalidate_caches_is_skip: + ADD r10, r10, #2 @ increment the cache number + CMP r3, r10 + BGT invalidate_caches_is_loop1 + +invalidate_caches_is_finished: + POP {r4-r12} + BX lr + +@ ------------------------------------------------------------ +@ TLB +@ ------------------------------------------------------------ +@ +@ EXPORT invalidateUnifiedTLB +@ ; void invalidateUnifiedTLB(void); + .align 2 + .global invalidateUnifiedTLB + .type invalidateUnifiedTLB,function +invalidateUnifiedTLB: + MOV r0, #0 + MCR p15, 0, r0, c8, c7, 0 @ TLBIALL - Invalidate entire unified TLB + BX lr + +@ EXPORT invalidateUnifiedTLB_IS +@ ; void invalidateUnifiedTLB_IS(void); + .align 2 + .global invalidateUnifiedTLB_IS + .type invalidateUnifiedTLB_IS,function +invalidateUnifiedTLB_IS: + MOV r0, #1 + MCR p15, 0, r0, c8, c3, 0 @ TLBIALLIS - Invalidate entire unified TLB Inner Shareable + BX lr + + +@ ------------------------------------------------------------ +@ Branch Prediction +@ ------------------------------------------------------------ +@ +@ EXPORT enableBranchPrediction +@ ; void enableBranchPrediction(void) + .align 2 + .global enableBranchPrediction + .type enableBranchPrediction,function +enableBranchPrediction: + MRC p15, 0, r0, c1, c0, 0 @ Read SCTLR + ORR r0, r0, #(1 << 11) @ Set the Z bit (bit 11) + MCR p15, 0,r0, c1, c0, 0 @ Write SCTLR + BX lr + +@ EXPORT disableBranchPrediction +@ ; void disableBranchPrediction(void) + .align 2 + .global disableBranchPrediction + .type disableBranchPrediction,function +disableBranchPrediction: + MRC p15, 0, r0, c1, c0, 0 @ Read SCTLR + BIC r0, r0, #(1 << 11) @ Clear the Z bit (bit 11) + MCR p15, 0,r0, c1, c0, 0 @ Write SCTLR + BX lr + + +@ EXPORT flushBranchTargetCache +@ ; void flushBranchTargetCache(void) + .align 2 + .global flushBranchTargetCache + .type flushBranchTargetCache,function +flushBranchTargetCache: + MOV r0, #0 + MCR p15, 0, r0, c7, c5, 6 @ BPIALL - Invalidate entire branch predictor array + BX lr + + +@ EXPORT flushBranchTargetCache_IS +@ ; void flushBranchTargetCache_IS(void) + .align 2 + .global flushBranchTargetCache_IS + .type flushBranchTargetCache_IS,function +flushBranchTargetCache_IS: + MOV r0, #0 + MCR p15, 0, r0, c7, c1, 6 @ BPIALLIS - Invalidate entire branch predictor array Inner Shareable + BX lr + +@ ------------------------------------------------------------ +@ High Vecs +@ ------------------------------------------------------------ +@ +@ EXPORT enableHighVecs +@ ; void enableHighVecs(void); + .align 2 + .global enableHighVecs + .type enableHighVecs,function +enableHighVecs: + MRC p15, 0, r0, c1, c0, 0 @ Read Control Register + ORR r0, r0, #(1 << 13) @ Set the V bit (bit 13) + MCR p15, 0, r0, c1, c0, 0 @ Write Control Register + BX lr + + +@ EXPORT disableHighVecs +@ ; void disable_highvecs(void); + .align 2 + .global disableHighVecs + .type disableHighVecs,function +disableHighVecs: + MRC p15, 0, r0, c1, c0, 0 @ Read Control Register + BIC r0, r0, #(1 << 13) @ Clear the V bit (bit 13) + MCR p15, 0, r0, c1, c0, 0 @ Write Control Register + BX lr + + +@ ------------------------------------------------------------ +@ Context ID +@ ------------------------------------------------------------ +@ +@ EXPORT getContextID +@ ; uint32_t getContextIDd(void); + .align 2 + .global getContextID + .type getContextID,function +getContextID: + MRC p15, 0, r0, c13, c0, 1 @ Read Context ID Register + BX lr + + +@ EXPORT setContextID +@ ; void setContextID(uint32_t); + .align 2 + .global setContextID + .type setContextID,function +setContextID: + MCR p15, 0, r0, c13, c0, 1 @ Write Context ID Register + BX lr + + +@ ------------------------------------------------------------ +@ ID registers +@ ------------------------------------------------------------ +@ +@ EXPORT getMIDR +@ ; uint32_t getMIDR(void); + .align 2 + .global getMIDR + .type getMIDR,function +getMIDR: + MRC p15, 0, r0, c0, c0, 0 @ Read Main ID Register (MIDR) + BX lr + + +@ EXPORT getMPIDR +@ ; uint32_t getMPIDR(void); + .align 2 + .global getMPIDR + .type getMPIDR,function +getMPIDR: + MRC p15, 0, r0, c0 ,c0, 5@ Read Multiprocessor ID register (MPIDR) + BX lr + + +@ ------------------------------------------------------------ +@ CP15 SMP related +@ ------------------------------------------------------------ +@ +@ EXPORT getBaseAddr +@ ; uint32_t getBaseAddr(void) +@ ; Returns the value CBAR (base address of the private peripheral memory space) + .align 2 + .global getBaseAddr + .type getBaseAddr,function +getBaseAddr: + MRC p15, 4, r0, c15, c0, 0 @ Read periph base address + BX lr + + +@ ------------------------------------------------------------ +@ +@ EXPORT getCPUID +@ ; uint32_t getCPUID(void) +@ ; Returns the CPU ID (0 to 3) of the CPU executed on + .align 2 + .global getCPUID + .type getCPUID,function +getCPUID: + MRC p15, 0, r0, c0, c0, 5 @ Read CPU ID register + AND r0, r0, #0x03 @ Mask off, leaving the CPU ID field + BX lr + + +@ ------------------------------------------------------------ +@ +@ EXPORT goToSleep +@ ; void goToSleep(void) + .align 2 + .global goToSleep + .type goToSleep,function +goToSleep: + WFI @ Go into standby + B goToSleep @ Catch in case of rogue events + BX lr + + +@ ------------------------------------------------------------ +@ +@ EXPORT joinSMP +@ ; void joinSMP(void) +@ ; Sets the ACTRL.SMP bit + .align 2 + .global joinSMP + .type joinSMP,function +joinSMP: + + @ SMP status is controlled by bit 6 of the CP15 Aux Ctrl Reg + + MRC p15, 0, r0, c1, c0, 1 @ Read ACTLR + MOV r1, r0 + ORR r0, r0, #0x040 @ Set bit 6 + CMP r0, r1 + MCRNE p15, 0, r0, c1, c0, 1 @ Write ACTLR + + BX lr + + +@ ------------------------------------------------------------ +@ +@ EXPORT leaveSMP +@ ; void leaveSMP(void) +@ ; Clear the ACTRL.SMP bit + .align 2 + .global leaveSMP + .type leaveSMP,function +leaveSMP: + + @ SMP status is controlled by bit 6 of the CP15 Aux Ctrl Reg + + MRC p15, 0, r0, c1, c0, 1 @ Read ACTLR + BIC r0, r0, #0x040 @ Clear bit 6 + MCR p15, 0, r0, c1, c0, 1 @ Write ACTLR + + BX lr + + +@ ------------------------------------------------------------ +@ +@ EXPORT leaveSMP +@ ; void leaveSMP(void) +@ ; Clear the ACTRL.SMP bit + .align 2 + .global _exit + .type _exit,function +_exit: + BX lr + +@ +@; ------------------------------------------------------------ +@; End of code +@; ------------------------------------------------------------ +@ +@ END +@ +@; ------------------------------------------------------------ +@; End of v7.s +@; ------------------------------------------------------------ diff --git a/ports_smp/cortex_a7_smp/gnu/example_build/v7.h b/ports_smp/cortex_a7_smp/gnu/example_build/v7.h new file mode 100644 index 00000000..0fc0183f --- /dev/null +++ b/ports_smp/cortex_a7_smp/gnu/example_build/v7.h @@ -0,0 +1,145 @@ +// ------------------------------------------------------------ +// v7-A Cache, TLB and Branch Prediction Maintenance Operations +// Header File +// +// Copyright (c) 2011 ARM Ltd. All rights reserved. +// ------------------------------------------------------------ + +#ifndef _ARMV7A_GENERIC_H +#define _ARMV7A_GENERIC_H + +// +// Note: +// *_IS() stands for "inner shareable" +// DO NOT USE THESE FUNCTIONS ON A CORTEX-A8 +// + +// ------------------------------------------------------------ +// Interrupts +// Enable/disables IRQs (not FIQs) +void enableInterrupts(void); +void disableInterrupts(void); + +// ------------------------------------------------------------ +// Caches + +void invalidateCaches_IS(void); +void cleanInvalidateDCache(void); +void invalidateCaches_IS(void); +void enableCaches(void); +void disableCaches(void); +void invalidateCaches(void); +void cleanDCache(void); + +// ------------------------------------------------------------ +// TLBs + +void invalidateUnifiedTLB(void); +void invalidateUnifiedTLB_IS(void); + +// ------------------------------------------------------------ +// Branch prediction + +void enableBranchPrediction(void); +void disableBranchPrediction(void); +void flushBranchTargetCache(void); +void flushBranchTargetCache_IS(void); + +// ------------------------------------------------------------ +// High Vecs + +void enableHighVecs(void); +void disableHighVecs(void); + +// ------------------------------------------------------------ +// ID Registers + +unsigned int getMIDR(void); + +#define MIDR_IMPL_SHIFT 24 +#define MIDR_IMPL_MASK 0xFF +#define MIDR_VAR_SHIFT 20 +#define MIDR_VAR_MASK 0xF +#define MIDR_ARCH_SHIFT 16 +#define MIDR_ARCH_MASK 0xF +#define MIDR_PART_SHIFT 4 +#define MIDR_PART_MASK 0xFFF +#define MIDR_REV_SHIFT 0 +#define MIDR_REV_MASK 0xF + +// tmp = get_MIDR(); +// implementor = (tmp >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; +// variant = (tmp >> MIDR_VAR_SHIFT) & MIDR_VAR_MASK; +// architecture= (tmp >> MIDR_ARCH_SHIFT) & MIDR_ARCH_MASK; +// part_number = (tmp >> MIDR_PART_SHIFT) & MIDR_PART_MASK; +// revision = tmp & MIDR_REV_MASK; + +#define MIDR_PART_CA5 0xC05 +#define MIDR_PART_CA8 0xC08 +#define MIDR_PART_CA9 0xC09 + +unsigned int getMPIDR(void); + +#define MPIDR_FORMAT_SHIFT 31 +#define MPIDR_FORMAT_MASK 0x1 +#define MPIDR_UBIT_SHIFT 30 +#define MPIDR_UBIT_MASK 0x1 +#define MPIDR_CLUSTER_SHIFT 7 +#define MPIDR_CLUSTER_MASK 0xF +#define MPIDR_CPUID_SHIFT 0 +#define MPIDR_CPUID_MASK 0x3 + +#define MPIDR_CPUID_CPU0 0x0 +#define MPIDR_CPUID_CPU1 0x1 +#define MPIDR_CPUID_CPU2 0x2 +#define MPIDR_CPUID_CPU3 0x3 + +#define MPIDR_UNIPROCESSPR 0x1 + +#define MPDIR_NEW_FORMAT 0x1 + +// ------------------------------------------------------------ +// Context ID + +unsigned int getContextID(void); + +void setContextID(unsigned int); + +#define CONTEXTID_ASID_SHIFT 0 +#define CONTEXTID_ASID_MASK 0xFF +#define CONTEXTID_PROCID_SHIFT 8 +#define CONTEXTID_PROCID_MASK 0x00FFFFFF + +// tmp = getContextID(); +// ASID = tmp & CONTEXTID_ASID_MASK; +// PROCID = (tmp >> CONTEXTID_PROCID_SHIFT) & CONTEXTID_PROCID_MASK; + +// ------------------------------------------------------------ +// SMP related for ARMv7-A MPCore processors +// +// DO NOT CALL THESE FUNCTIONS ON A CORTEX-A8 + +// Returns the base address of the private peripheral memory space +unsigned int getBaseAddr(void); + +// Returns the CPU ID (0 to 3) of the CPU executed on +#define MP_CPU0 (0) +#define MP_CPU1 (1) +#define MP_CPU2 (2) +#define MP_CPU3 (3) +unsigned int getCPUID(void); + +// Set this core as participating in SMP +void joinSMP(void); + +// Set this core as NOT participating in SMP +void leaveSMP(void); + +// Go to sleep, never returns +void goToSleep(void); + +#endif + +// ------------------------------------------------------------ +// End of v7.h +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a7_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a7_smp/gnu/inc/tx_port.h new file mode 100644 index 00000000..d5d527ec --- /dev/null +++ b/ports_smp/cortex_a7_smp/gnu/inc/tx_port.h @@ -0,0 +1,404 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h SMP/Cortex-A7/GNU */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/************* Define ThreadX SMP constants. *************/ + +/* Define the ThreadX SMP maximum number of cores. */ + +#ifndef TX_THREAD_SMP_MAX_CORES +#define TX_THREAD_SMP_MAX_CORES 4 +#endif + + +/* Define the ThreadX SMP core mask. */ + +#ifndef TX_THREAD_SMP_CORE_MASK +#define TX_THREAD_SMP_CORE_MASK 0xf /* Where bit 0 represents Core 0, bit 1 represents Core 1, etc. */ +#endif + + +/* Define ThreadX SMP initialization macro. */ + +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION + + +/* Define ThreadX SMP pre-scheduler initialization. */ + +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION + + +/* Enable the inter-core interrupt logic. */ + +#define TX_THREAD_SMP_INTER_CORE_INTERRUPT + + +/* Determine if there is customer-specific wakeup logic needed. */ + +#ifdef TX_THREAD_SMP_WAKEUP_LOGIC + +/* Include customer-specific wakeup code. */ + +#include "tx_thread_smp_core_wakeup.h" +#else + +#ifdef TX_THREAD_SMP_DEFAULT_WAKEUP_LOGIC + +/* Default wakeup code. */ +#define TX_THREAD_SMP_WAKEUP_LOGIC +#define TX_THREAD_SMP_WAKEUP(i) _tx_thread_smp_core_preempt(i) +#endif +#endif + + +/* Ensure that the in-line resume/suspend define is not allowed. */ + +#ifdef TX_INLINE_THREAD_RESUME_SUSPEND +#undef TX_INLINE_THREAD_RESUME_SUSPEND +#endif + + +/************* End ThreadX SMP constants. *************/ + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE _tx_thread_smp_time_get() +#endif +#else +#ifndef TX_TRACE_TIME_SOURCE +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#if __TARGET_ARCH_ARM > 4 + +#ifndef __thumb__ + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + asm volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); \ + b = 31 - b; +#endif +#endif +#endif + + +/************* Define ThreadX SMP data types and function prototypes. *************/ + +struct TX_THREAD_STRUCT; + + +/* Define the ThreadX SMP protection structure. */ + +typedef struct TX_THREAD_SMP_PROTECT_STRUCT +{ + ULONG tx_thread_smp_protect_in_force; + struct TX_THREAD_STRUCT * + tx_thread_smp_protect_thread; + ULONG tx_thread_smp_protect_core; + ULONG tx_thread_smp_protect_count; + + /* Implementation specific information follows. */ + + ULONG tx_thread_smp_protect_get_caller; + ULONG tx_thread_smp_protect_sr; + ULONG tx_thread_smp_protect_release_caller; +} TX_THREAD_SMP_PROTECT; + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_smp_protect(); +#define TX_RESTORE _tx_thread_smp_unprotect(interrupt_save); + + +/************* End ThreadX SMP data type and function prototype definitions. *************/ + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define VFP extension for the Cortex-A7. Each is assumed to be called in the context of the executing + thread. */ + +void tx_thread_vfp_enable(void); +void tx_thread_vfp_disable(void); + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Cortex-A7/GNU Version 6.0.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + + + diff --git a/ports_smp/cortex_a7_smp/gnu/readme_threadx.txt b/ports_smp/cortex_a7_smp/gnu/readme_threadx.txt new file mode 100644 index 00000000..4f421479 --- /dev/null +++ b/ports_smp/cortex_a7_smp/gnu/readme_threadx.txt @@ -0,0 +1,343 @@ + Microsoft's Azure RTOS ThreadX for Cortex-A7 + + Using the GNU Tools + +1. Building the ThreadX run-time Library + +First make sure you are in the "example_build" directory. Also, make sure that +you have setup your path and other environment variables necessary for the GNU +development environment. + +At this point you may run the build_threadx.bat batch file. This will build the +ThreadX run-time environment in the "example_build" directory. + +You should observe assembly and compilation of a series of ThreadX source +files. At the end of the batch file, they are all combined into the +run-time library file: tx.a. This file must be linked with your +application in order to use ThreadX. + + +2. Demonstration System + +The ThreadX demonstration is designed to execute under the ARM Cortex-A7x4 FVP. + +Building the demonstration is easy; simply execute the build_threadx_sample.bat +batch file while inside the "example_build" directory. + +You should observe the compilation of sample_threadx.c (which is the demonstration +application) and linking with TX.A. The resulting file DEMO is a binary file +that can be downloaded and executed. + + +3. System Initialization + +The entry point in ThreadX for the Cortex-A7 using GNU tools is at label +Reset_Handler in startup.s. After the basic core initialization is complete, +control will transfer to __main, which is where all static and global pre-set +C variable initialization processing takes place. + +The ThreadX tx_initialize_low_level.s file is responsible for setting up +various system data structures, the vector area, and a periodic timer interrupt +source. By default, the vector area is defined to be located in the Init area, +which is defined at the top of tx_initialize_low_level.s. This area is typically +located at 0. In situations where this is impossible, the vectors at the beginning +of the Init area should be copied to address 0. + +This is also where initialization of a periodic timer interrupt source +should take place. + +In addition, _tx_initialize_low_level determines the first available +address for use by the application, which is supplied as the sole input +parameter to your application definition function, tx_application_define. + + +4. Register Usage and Stack Frames + +The GNU compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread +is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 CPSR CPSR + 0x08 r0 (a1) r4 (v1) + 0x0C r1 (a2) r5 (v2) + 0x10 r2 (a3) r6 (v3) + 0x14 r3 (a4) r7 (v4) + 0x18 r4 (v1) r8 (v5) + 0x1C r5 (v2) r9 (v6) + 0x20 r6 (v3) r10 (v7) + 0x24 r7 (v4) r11 (fp) + 0x28 r8 (v5) r14 (lr) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) + 0x3C r14 (lr) + 0x40 PC + + +5. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the build_threadx.bat file to +remove the -g option and enable all compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +6. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-A7 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +6.1 Vector Area + +The Cortex-A7 vectors start at address zero. The demonstration system startup +Init area contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. + + +6.2 IRQ ISRs + +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested +IRQ interrupts. The following sub-sections define the IRQ capabilities. + + +6.2.1 Standard IRQ ISRs + +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in tx_initialize_low_level. The following +is the default IRQ handler defined in tx_initialize_low_level.s: + + EXPORT __tx_irq_handler + EXPORT __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save ; Jump to the context save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Application ISR call(s) go here! */ +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +6.2.2 Vectored IRQ ISRs + +The vectored ARM IRQ mechanism has multiple interrupt vectors at addresses specified +by the particular implementation. The following is an example IRQ handler defined in +tx_initialize_low_level.s: + + EXPORT __tx_irq_example_handler +__tx_irq_example_handler +; +; /* Call context save to save system context. */ + + STMDB sp!, {r0-r3} ; Save some scratch registers + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other scratch registers + BL _tx_thread_vectored_context_save ; Call the vectored IRQ context save +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Application ISR call goes here! */ +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +6.2.3 Nested IRQ Support + +By default, nested IRQ interrupt support is not enabled. To enable nested +IRQ support, the entire library should be built with TX_ENABLE_IRQ_NESTING +defined. With this defined, two new IRQ interrupt management services are +available, namely _tx_thread_irq_nesting_start and _tx_thread_irq_nesting_end. +These function should be called between the IRQ context save and restore +calls. + +Execution between the calls to _tx_thread_irq_nesting_start and +_tx_thread_irq_nesting_end is enabled for IRQ nesting. This is achieved +by switching from IRQ mode to SYS mode and enabling IRQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested IRQ interrupts are no longer required, +calling the _tx_thread_irq_nesting_end service disables nesting by disabling +IRQ interrupts and switching back to IRQ mode in preparation for the IRQ +context restore service. + +The following is an example of enabling IRQ nested interrupts in a standard +IRQ handler: + + EXPORT __tx_irq_handler + EXPORT __tx_irq_processing_return +__tx_irq_handler +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return +; +; /* Enable nested IRQ interrupts. NOTE: Since this service returns +; with IRQ interrupts enabled, all IRQ interrupt sources must be +; cleared prior to calling this service. */ + BL _tx_thread_irq_nesting_start +; +; /* Application ISR call(s) go here! */ +; +; /* Disable nested IRQ interrupts. The mode is switched back to +; IRQ mode and IRQ interrupts are disable upon return. */ + BL _tx_thread_irq_nesting_end +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +6.3 FIQ Interrupts + +By default, Cortex-A7 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made +from default FIQ ISRs, which is located in tx_initialize_low_level.s. + + +6.3.1 Managed FIQ Interrupts + +Full ThreadX management of FIQ interrupts is provided if the ThreadX sources +are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built +this way, the FIQ interrupt handlers are very similar to the IRQ interrupt +handlers defined previously. The following is default FIQ handler +defined in tx_initialize_low_level.s: + + + EXPORT __tx_fiq_handler + EXPORT __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Application FIQ handlers can be called here! */ +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +6.3.1.1 Nested FIQ Support + +By default, nested FIQ interrupt support is not enabled. To enable nested +FIQ support, the entire library should be built with TX_ENABLE_FIQ_NESTING +defined. With this defined, two new FIQ interrupt management services are +available, namely _tx_thread_fiq_nesting_start and _tx_thread_fiq_nesting_end. +These function should be called between the FIQ context save and restore +calls. + +Execution between the calls to _tx_thread_fiq_nesting_start and +_tx_thread_fiq_nesting_end is enabled for FIQ nesting. This is achieved +by switching from FIQ mode to SYS mode and enabling FIQ interrupts. +The SYS mode stack is used during the SYS mode operation, which was +setup in tx_initialize_low_level.s. When nested FIQ interrupts are no longer required, +calling the _tx_thread_fiq_nesting_end service disables nesting by disabling +FIQ interrupts and switching back to FIQ mode in preparation for the FIQ +context restore service. + +The following is an example of enabling FIQ nested interrupts in the +typical FIQ handler: + + + EXPORT __tx_fiq_handler + EXPORT __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Enable nested FIQ interrupts. NOTE: Since this service returns +; with FIQ interrupts enabled, all FIQ interrupt sources must be +; cleared prior to calling this service. */ + BL _tx_thread_fiq_nesting_start +; +; /* Application FIQ handlers can be called here! */ +; +; /* Disable nested FIQ interrupts. The mode is switched back to +; FIQ mode and FIQ interrupts are disable upon return. */ + BL _tx_thread_fiq_nesting_end +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +7. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional. However, all other +ThreadX services are operational without a periodic timer source. + +To add the timer interrupt processing, simply make a call to +_tx_timer_interrupt in the IRQ processing. An example of this can be +found in the file tx_initialize_low_level.s in the Integrator sub-directories. + + +8. VFP Support + +VFP support is optional, it can be enabled by building the ThreadX library +assembly code with the following command-line option: + +-mfpu=neon -DTARGET_FPU_VFP + +Note that if ISRs need to use VFP registers, their contents much be saved +before their use and restored after. + + +9. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A7 using GNU tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_context_restore.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_context_restore.S new file mode 100644 index 00000000..922132ee --- /dev/null +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_context_restore.S @@ -0,0 +1,373 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@/* Include macros for modifying the wait list. */ +#include "tx_thread_smp_protection_wait_list_macros.h" + + .arm + +#ifdef TX_ENABLE_FIQ_SUPPORT +SVC_MODE = 0xD3 @ Disable IRQ/FIQ, SVC mode +IRQ_MODE = 0xD2 @ Disable IRQ/FIQ, IRQ mode +#else +SVC_MODE = 0x93 @ Disable IRQ, SVC mode +IRQ_MODE = 0x92 @ Disable IRQ, IRQ mode +#endif +@ + + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_execute_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable + .global _tx_timer_interrupt_active + .global _tx_thread_smp_protection + .global _tx_thread_smp_protect_wait_counts + .global _tx_thread_smp_protect_wait_list + .global _tx_thread_smp_protect_wait_list_lock_protect_in_force + .global _tx_thread_smp_protect_wait_list_tail + .global _tx_thread_smp_protect_wait_list_size +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + .global _tx_execution_isr_exit +#endif + +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_restore +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_restore SMP/Cortex-A7/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function restores the interrupt context if it is processing a */ +@/* nested interrupt. If not, it returns to the interrupt thread if no */ +@/* preemption is necessary. Otherwise, if preemption is necessary or */ +@/* if no thread was running, the function returns to the scheduler. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling routine */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs Interrupt Service Routines */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_restore(VOID) +@{ + .global _tx_thread_context_restore + .type _tx_thread_context_restore,function +_tx_thread_context_restore: +@ +@ /* Lockout interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR exit function to indicate an ISR is complete. */ +@ + BL _tx_execution_isr_exit @ Call the ISR exit function +#endif + +@ /* Pickup the CPU ID. */ +@ + MRC p15, 0, r10, c0, c0, 5 @ Read CPU ID register + AND r10, r10, #0x03 @ Mask off, leaving the CPU ID field + LSL r12, r10, #2 @ Build offset to array indexes +@ +@ /* Determine if interrupts are nested. */ +@ if (--_tx_thread_system_state[core]) +@ { +@ + LDR r3, =_tx_thread_system_state @ Pickup address of system state var + ADD r3, r3, r12 @ Build array offset + LDR r2, [r3, #0] @ Pickup system state + SUB r2, r2, #1 @ Decrement the counter + STR r2, [r3, #0] @ Store the counter + CMP r2, #0 @ Was this the first interrupt? + BEQ __tx_thread_not_nested_restore @ If so, not a nested restore +@ +@ /* Interrupts are nested. */ +@ +@ /* Just recover the saved registers and return to the point of +@ interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +__tx_thread_not_nested_restore: +@ +@ /* Determine if a thread was interrupted and no preemption is required. */ +@ else if (((_tx_thread_current_ptr[core]) && (_tx_thread_current_ptr[core] == _tx_thread_execute_ptr[core]) +@ || (_tx_thread_preempt_disable)) +@ { +@ + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + ADD r1, r1, r12 @ Build index to this core's current thread ptr + LDR r0, [r1, #0] @ Pickup actual current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_restore @ Yes, idle system was interrupted +@ + LDR r3, =_tx_thread_smp_protection @ Get address of protection structure + LDR r2, [r3, #8] @ Pickup owning core + CMP r2, r10 @ Is the owning core the same as the protected core? + BNE __tx_thread_skip_preempt_check @ No, skip the preempt disable check since this is only valid for the owning core + + LDR r3, =_tx_thread_preempt_disable @ Pickup preempt disable address + LDR r2, [r3, #0] @ Pickup actual preempt disable flag + CMP r2, #0 @ Is it set? + BNE __tx_thread_no_preempt_restore @ Yes, don't preempt this thread +__tx_thread_skip_preempt_check: + + LDR r3, =_tx_thread_execute_ptr @ Pickup address of execute thread ptr + ADD r3, r3, r12 @ Build index to this core's execute thread ptr + LDR r2, [r3, #0] @ Pickup actual execute thread pointer + CMP r0, r2 @ Is the same thread highest priority? + BNE __tx_thread_preempt_restore @ No, preemption needs to happen +@ +@ +__tx_thread_no_preempt_restore: +@ +@ /* Restore interrupted thread or ISR. */ +@ +@ /* Pickup the saved stack pointer. */ +@ tmp_ptr = _tx_thread_current_ptr[core] -> tx_thread_stack_ptr; +@ +@ /* Recover the saved context and return to the point of interrupt. */ +@ + LDMIA sp!, {r0, r10, r12, lr} @ Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 @ Put SPSR back + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOVS pc, lr @ Return to point of interrupt +@ +@ } +@ else +@ { +__tx_thread_preempt_restore: +@ +@ /* Was the thread being preempted waiting for the lock? */ +@ if (_tx_thread_smp_protect_wait_counts[this_core] != 0) +@ { +@ + LDR r1, =_tx_thread_smp_protect_wait_counts @ Load waiting count list + LDR r2, [r1, r10, LSL #2] @ Load waiting value for this core + CMP r2, #0 + BEQ _nobody_waiting_for_lock @ Is the core waiting for the lock? +@ +@ /* Do we not have the lock? This means the ISR never got the inter-core lock. */ +@ if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core) +@ { +@ + LDR r1, =_tx_thread_smp_protection @ Load address of protection structure + LDR r2, [r1, #8] @ Pickup the owning core + CMP r10, r2 @ Compare our core to the owning core + BEQ _this_core_has_lock @ Do we have the lock? +@ +@ /* We don't have the lock. This core should be in the list. Remove it. */ +@ _tx_thread_smp_protect_wait_list_remove(this_core); +@ + _tx_thread_smp_protect_wait_list_remove @ Call macro to remove core from the list + B _nobody_waiting_for_lock @ Leave +@ +@ } +@ else +@ { +@ /* We have the lock. This means the ISR got the inter-core lock, but +@ never released it because it saw that there was someone waiting. +@ Note this core is not in the list. */ +@ +_this_core_has_lock: +@ +@ /* We're no longer waiting. Note that this should be zero since this happens during thread preemption. */ +@ _tx_thread_smp_protect_wait_counts[core]--; +@ + LDR r1, =_tx_thread_smp_protect_wait_counts @ Load waiting count list + LDR r2, [r1, r10, LSL #2] @ Load waiting value for this core + SUB r2, r2, #1 @ Decrement waiting value. Should be zero now + STR r2, [r1, r10, LSL #2] @ Store new waiting value +@ +@ /* Now release the inter-core lock. */ +@ +@ /* Set protected core as invalid. */ +@ _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF; +@ + LDR r1, =_tx_thread_smp_protection @ Load address of protection structure + MOV r2, #0xFFFFFFFF @ Build invalid value + STR r2, [r1, #8] @ Mark the protected core as invalid + DMB @ Ensure that accesses to shared resource have completed +@ +@ /* Release protection. */ +@ _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0; +@ + MOV r2, #0 @ Build release protection value + STR r2, [r1, #0] @ Release the protection + DSB ISH @ To ensure update of the protection occurs before other CPUs awake +@ +@ /* Wake up waiting processors. Note interrupts are already enabled. */ +@ +#ifdef TX_ENABLE_WFE + SEV @ Send event to other CPUs +#endif +@ +@ } +@ } +@ + +_nobody_waiting_for_lock: + + LDMIA sp!, {r3, r10, r12, lr} @ Recover temporarily saved registers + MOV r1, lr @ Save lr (point of interrupt) + MOV r2, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r2 @ Enter SVC mode + STR r1, [sp, #-4]! @ Save point of interrupt + STMDB sp!, {r4-r12, lr} @ Save upper half of registers + MOV r4, r3 @ Save SPSR in r4 + MOV r2, #IRQ_MODE @ Build IRQ mode CPSR + MSR CPSR_c, r2 @ Enter IRQ mode + LDMIA sp!, {r0-r3} @ Recover r0-r3 + MOV r5, #SVC_MODE @ Build SVC mode CPSR + MSR CPSR_c, r5 @ Enter SVC mode + STMDB sp!, {r0-r3} @ Save r0-r3 on thread's stack + + MRC p15, 0, r10, c0, c0, 5 @ Read CPU ID register + AND r10, r10, #0x03 @ Mask off, leaving the CPU ID field + LSL r12, r10, #2 @ Build offset to array indexes + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + ADD r1, r1, r12 @ Build index to current thread ptr + LDR r0, [r1, #0] @ Pickup current thread pointer + +#ifdef TARGET_FPU_VFP + LDR r2, [r0, #160] @ Pickup the VFP enabled flag + CMP r2, #0 @ Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save @ No, skip VFP IRQ save + FMRX r2, FPSCR @ Pickup the FPSCR + STR r2, [sp, #-4]! @ Save FPSCR + VSTMDB sp!, {D16-D31} @ Save D16-D31 + VSTMDB sp!, {D0-D15} @ Save D0-D15 +_tx_skip_irq_vfp_save: +#endif + + MOV r3, #1 @ Build interrupt stack type + STMDB sp!, {r3, r4} @ Save interrupt stack type and SPSR + STR sp, [r0, #8] @ Save stack pointer in thread control + @ block +@ +@ /* Save the remaining time-slice and disable it. */ +@ if (_tx_timer_time_slice[core]) +@ { +@ + LDR r3, =_tx_timer_interrupt_active @ Pickup timer interrupt active flag's address +_tx_wait_for_timer_to_finish: + LDR r2, [r3, #0] @ Pickup timer interrupt active flag + CMP r2, #0 @ Is the timer interrupt active? + BNE _tx_wait_for_timer_to_finish @ If timer interrupt is active, wait until it completes + + LDR r3, =_tx_timer_time_slice @ Pickup time-slice variable address + ADD r3, r3, r12 @ Build index to core's time slice + LDR r2, [r3, #0] @ Pickup time-slice + CMP r2, #0 @ Is it active? + BEQ __tx_thread_dont_save_ts @ No, don't save it +@ +@ _tx_thread_current_ptr[core] -> tx_thread_time_slice = _tx_timer_time_slice[core]; +@ _tx_timer_time_slice[core] = 0; +@ + STR r2, [r0, #24] @ Save thread's time-slice + MOV r2, #0 @ Clear value + STR r2, [r3, #0] @ Disable global time-slice flag +@ +@ } +__tx_thread_dont_save_ts: +@ +@ +@ /* Clear the current task pointer. */ +@ _tx_thread_current_ptr[core] = TX_NULL; +@ + MOV r2, #0 @ NULL value + STR r2, [r1, #0] @ Clear current thread pointer +@ +@ /* Set bit indicating this thread is ready for execution. */ +@ + LDR r2, [r0, #152] @ Pickup the ready bit + ORR r2, r2, #0x8000 @ Set ready bit (bit 15) + STR r2, [r0, #152] @ Make this thread ready for executing again + DMB @ Ensure that accesses to shared resource have completed +@ +@ /* Return to the scheduler. */ +@ _tx_thread_schedule(); +@ + B _tx_thread_schedule @ Return to scheduler +@ } +@ +__tx_thread_idle_system_restore: +@ +@ /* Just return back to the scheduler! */ +@ + MOV r3, #SVC_MODE @ Build SVC mode with interrupts disabled + MSR CPSR_c, r3 @ Change to SVC mode + B _tx_thread_schedule @ Return to scheduler +@} +@ + diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_context_save.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_context_save.S new file mode 100644 index 00000000..df02a791 --- /dev/null +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_context_save.S @@ -0,0 +1,208 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global __tx_irq_processing_return +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + .global _tx_execution_isr_enter +#endif +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_context_save SMP/Cortex-A7/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_context_save(VOID) +@{ + .global _tx_thread_context_save + .type _tx_thread_context_save,function +_tx_thread_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state[core]++) +@ { +@ + STMDB sp!, {r0-r3} @ Save some working registers +@ +@ /* Save the rest of the scratch registers on the stack and return to the +@ calling ISR. */ +@ + MRS r0, SPSR @ Pickup saved SPSR + SUB lr, lr, #4 @ Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} @ Store other registers +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable FIQ interrupts +#endif +@ +@ /* Pickup the CPU ID. */ +@ + MRC p15, 0, r10, c0, c0, 5 @ Read CPU ID register + AND r10, r10, #0x03 @ Mask off, leaving the CPU ID field + LSL r12, r10, #2 @ Build offset to array indexes +@ + LDR r3, =_tx_thread_system_state @ Pickup address of system state var + ADD r3, r3, r12 @ Build index into the system state array + LDR r2, [r3, #0] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3, #0] @ Store it back in the variable +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {r12, lr} @ Save ISR lr & r12 + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {r12, lr} @ Recover ISR lr & r12 +#endif + + B __tx_irq_processing_return @ Continue IRQ processing +@ +__tx_thread_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr[core]) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3, #0] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + ADD r1, r1, r12 @ Build index into current thread ptr + LDR r0, [r1, #0] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + @ scheduling loop - nothing needs saving! +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr; +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {r12, lr} @ Save ISR lr & r12 + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {r12, lr} @ Recover ISR lr & r12 +#endif + + B __tx_irq_processing_return @ Continue IRQ processing +@ +@ } +@ else +@ { +@ +__tx_thread_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ processing. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {r12, lr} @ Save ISR lr & r12 + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {r12, lr} @ Recover ISR lr & r12 +#endif + + ADD sp, sp, #32 @ Recover saved registers + B __tx_irq_processing_return @ Continue IRQ processing +@ +@ } +@} +@ + + diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_interrupt_control.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..77a5839b --- /dev/null +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_interrupt_control.S @@ -0,0 +1,105 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT +INT_MASK = 0xC0 @ Interrupt bit mask +#else +INT_MASK = 0x80 @ Interrupt bit mask +#endif +@ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_control SMP/Cortex-A7/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for changing the interrupt lockout */ +@/* posture of the system. */ +@/* */ +@/* INPUT */ +@/* */ +@/* new_posture New interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_control(UINT new_posture) +@{ + .global _tx_thread_interrupt_control + .type _tx_thread_interrupt_control,function +_tx_thread_interrupt_control: +@ +@ /* Pickup current interrupt lockout posture. */ +@ + MRS r3, CPSR @ Pickup current CPSR + BIC r1, r3, #INT_MASK @ Clear interrupt lockout bits + ORR r1, r1, r0 @ Or-in new interrupt lockout bits +@ +@ /* Apply the new interrupt posture. */ +@ + MSR CPSR_c, r1 @ Setup new CPSR + AND r0, r3, #INT_MASK @ Return previous interrupt mask +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@ +@} +@ + + diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_interrupt_disable.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_interrupt_disable.S new file mode 100644 index 00000000..b6eb4376 --- /dev/null +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_interrupt_disable.S @@ -0,0 +1,114 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_disable for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_interrupt_disable +$_tx_thread_interrupt_disable: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_interrupt_disable @ Call _tx_thread_interrupt_disable function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_disable SMP/Cortex-A7/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for disabling interrupts */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_disable(void) +@{ + .global _tx_thread_interrupt_disable + .type _tx_thread_interrupt_disable,function +_tx_thread_interrupt_disable: +@ +@ /* Pickup current interrupt lockout posture. */ +@ + MRS r0, CPSR @ Pickup current CPSR +@ +@ /* Mask interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ +#else + CPSID i @ Disable IRQ +#endif + +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} +@ + + diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_interrupt_restore.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_interrupt_restore.S new file mode 100644 index 00000000..85015a6e --- /dev/null +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_interrupt_restore.S @@ -0,0 +1,106 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_interrupt_restore for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_interrupt_restore +$_tx_thread_interrupt_restore: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_interrupt_restore @ Call _tx_thread_interrupt_restore function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_interrupt_restore SMP/Cortex-A7/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is responsible for restoring interrupts to the state */ +@/* returned by a previous _tx_thread_interrupt_disable call. */ +@/* */ +@/* INPUT */ +@/* */ +@/* old_posture Old interrupt lockout posture */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Application Code */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@UINT _tx_thread_interrupt_restore(UINT old_posture) +@{ + .global _tx_thread_interrupt_restore + .type _tx_thread_interrupt_restore,function +_tx_thread_interrupt_restore: +@ +@ /* Apply the new interrupt posture. */ +@ + MSR CPSR_c, r0 @ Setup new CPSR +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} +@ + + diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_irq_nesting_end.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_irq_nesting_end.S new file mode 100644 index 00000000..4669e95d --- /dev/null +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_irq_nesting_end.S @@ -0,0 +1,116 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts +#else +DISABLE_INTS = 0x80 @ Disable IRQ interrupts +#endif +MODE_MASK = 0x1F @ Mode mask +IRQ_MODE_BITS = 0x12 @ IRQ mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_end +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_end SMP/Cortex-A7/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +@/* processing from system mode back to IRQ mode prior to the ISR */ +@/* calling _tx_thread_context_restore. Note that this function */ +@/* assumes the system stack pointer is in the same position after */ +@/* nesting start function was called. */ +@/* */ +@/* This function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts disabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_irq_nesting_end(VOID) +@{ + .global _tx_thread_irq_nesting_end + .type _tx_thread_irq_nesting_end,function +_tx_thread_irq_nesting_end: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + ORR r0, r0, #DISABLE_INTS @ Build disable interrupt value + MSR CPSR_c, r0 @ Disable interrupts + LDMIA sp!, {r1, lr} @ Pickup saved lr (and r1 throw-away for + @ 8-byte alignment logic) + BIC r0, r0, #MODE_MASK @ Clear mode bits + ORR r0, r0, #IRQ_MODE_BITS @ Build IRQ mode CPSR + MSR CPSR_c, r0 @ Re-enter IRQ mode +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} + + diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_irq_nesting_start.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_irq_nesting_start.S new file mode 100644 index 00000000..47d4c2c8 --- /dev/null +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_irq_nesting_start.S @@ -0,0 +1,110 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +IRQ_DISABLE = 0x80 @ IRQ disable bit +MODE_MASK = 0x1F @ Mode mask +SYS_MODE_BITS = 0x1F @ System mode bits +@ +@ +@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_irq_nesting_start +@ since it will never be called 16-bit mode. */ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_irq_nesting_start SMP/Cortex-A7/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is called by the application from IRQ mode after */ +@/* _tx_thread_context_save has been called and switches the IRQ */ +@/* processing to the system mode so nested IRQ interrupt processing */ +@/* is possible (system mode has its own "lr" register). Note that */ +@/* this function assumes that the system mode stack pointer was setup */ +@/* during low-level initialization (tx_initialize_low_level.s). */ +@/* */ +@/* This function returns with IRQ interrupts enabled. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_irq_nesting_start(VOID) +@{ + .global _tx_thread_irq_nesting_start + .type _tx_thread_irq_nesting_start,function +_tx_thread_irq_nesting_start: + MOV r3,lr @ Save ISR return address + MRS r0, CPSR @ Pickup the CPSR + BIC r0, r0, #MODE_MASK @ Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS @ Build system mode CPSR + MSR CPSR_c, r0 @ Enter system mode + STMDB sp!, {r1, lr} @ Push the system mode lr on the system mode stack + @ and push r1 just to keep 8-byte alignment + BIC r0, r0, #IRQ_DISABLE @ Build enable IRQ CPSR + MSR CPSR_c, r0 @ Enter system mode +#ifdef __THUMB_INTERWORK + BX r3 @ Return to caller +#else + MOV pc, r3 @ Return to caller +#endif +@} +@ + + diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_schedule.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_schedule.S new file mode 100644 index 00000000..23c608e5 --- /dev/null +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_schedule.S @@ -0,0 +1,332 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_execute_ptr + .global _tx_thread_current_ptr + .global _tx_timer_time_slice + .global _tx_execution_thread_enter +@ +@ +@/* Define the 16-bit Thumb mode veneer for _tx_thread_schedule for +@ applications calling this function from to 16-bit Thumb mode. */ +@ + .text + .align 2 + .global $_tx_thread_schedule + .type $_tx_thread_schedule,function +$_tx_thread_schedule: + .thumb + BX pc @ Switch to 32-bit mode + NOP @ + .arm + STMFD sp!, {lr} @ Save return address + BL _tx_thread_schedule @ Call _tx_thread_schedule function + LDMFD sp!, {lr} @ Recover saved return address + BX lr @ Return to 16-bit caller +@ +@ + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_schedule SMP/Cortex-A7/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function waits for a thread control block pointer to appear in */ +@/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +@/* in the variable, the corresponding thread is resumed. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_kernel_enter ThreadX entry function */ +@/* _tx_thread_system_return Return to system from thread */ +@/* _tx_thread_context_restore Restore thread's context */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_schedule(VOID) +@{ + .global _tx_thread_schedule + .type _tx_thread_schedule,function +_tx_thread_schedule: +@ +@ /* Enable interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSIE if @ Enable IRQ and FIQ interrupts +#else + CPSIE i @ Enable IRQ interrupts +#endif +@ +@ /* Pickup the CPU ID. */ +@ + MRC p15, 0, r10, c0, c0, 5 @ Read CPU ID register + AND r10, r10, #0x03 @ Mask off, leaving the CPU ID field + LSL r12, r10, #2 @ Build offset to array indexes + + LDR r1, =_tx_thread_execute_ptr @ Address of thread execute ptr + ADD r1, r1, r12 @ Build offset to execute ptr for this core +@ +@ /* Lockout interrupts transfer control to it. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif +@ +@ /* Wait for a thread to execute. */ +@ do +@ { +@ +@ + LDR r0, [r1, #0] @ Pickup next thread to execute + CMP r0, #0 @ Is it NULL? + BEQ _tx_thread_schedule @ If so, keep looking for a thread +@ +@ } +@ while(_tx_thread_execute_ptr[core] == TX_NULL); +@ +@ /* Get the lock for accessing the thread's ready bit. */ +@ + MOV r2, #172 @ Build offset to the lock + ADD r2, r0, r2 @ Get the address to the lock + LDREX r3, [r2] @ Pickup the lock value + CMP r3, #0 @ Check if it's available + BNE _tx_thread_schedule @ No, lock not available + MOV r3, #1 @ Build the lock set value + STREX r4, r3, [r2] @ Try to get the lock + CMP r4, #0 @ Check if we got the lock + BNE _tx_thread_schedule @ No, another core got it first + DMB @ Ensure write to lock completes +@ +@ /* Now make sure the thread's ready bit is set. */ +@ + LDR r3, [r0, #152] @ Pickup the thread ready bit + AND r4, r3, #0x8000 @ Isolate the ready bit + CMP r4, #0 @ Is it set? + BNE _tx_thread_ready_for_execution @ Yes, schedule the thread +@ +@ /* The ready bit isn't set. Release the lock and jump back to the scheduler. */ +@ + MOV r3, #0 @ Build clear value + STR r3, [r2] @ Release the lock + DMB @ Ensure write to lock completes + B _tx_thread_schedule @ Jump back to the scheduler +@ +_tx_thread_ready_for_execution: +@ +@ /* We have a thread to execute. */ +@ +@ /* Clear the ready bit and release the lock. */ +@ + BIC r3, r3, #0x8000 @ Clear ready bit + STR r3, [r0, #152] @ Store it back in the thread control block + DMB + MOV r3, #0 @ Build clear value for the lock + STR r3, [r2] @ Release the lock + DMB +@ +@ /* Setup the current thread pointer. */ +@ _tx_thread_current_ptr[core] = _tx_thread_execute_ptr[core]; +@ + LDR r2, =_tx_thread_current_ptr @ Pickup address of current thread + ADD r2, r2, r12 @ Build index into the current thread array + STR r0, [r2, #0] @ Setup current thread pointer +@ +@ /* In the time between reading the execute pointer and assigning +@ it to the current pointer, the execute pointer was changed by +@ some external code. If the current pointer was still null when +@ the external code checked if a core preempt was necessary, then +@ it wouldn't have done it and a preemption will be missed. To +@ handle this, undo some things and jump back to the scheduler so +@ it can schedule the new thread. */ +@ + LDR r1, [r1, #0] @ Reload the execute pointer + CMP r0, r1 @ Did it change? + BEQ _execute_pointer_did_not_change @ If not, skip handling + + MOV r1, #0 @ Build clear value + STR r1, [r2, #0] @ Clear current thread pointer + + LDR r1, [r0, #152] @ Pickup the ready bit + ORR r1, r1, #0x8000 @ Set ready bit (bit 15) + STR r1, [r0, #152] @ Make this thread ready for executing again + DMB @ Ensure that accesses to shared resource have completed + + B _tx_thread_schedule @ Jump back to the scheduler to schedule the new thread + +_execute_pointer_did_not_change: +@ +@ /* Increment the run count for this thread. */ +@ _tx_thread_current_ptr[core] -> tx_thread_run_count++; +@ + LDR r2, [r0, #4] @ Pickup run counter + LDR r3, [r0, #24] @ Pickup time-slice for this thread + ADD r2, r2, #1 @ Increment thread run-counter + STR r2, [r0, #4] @ Store the new run counter +@ +@ /* Setup time-slice, if present. */ +@ _tx_timer_time_slice[core] = _tx_thread_current_ptr[core] -> tx_thread_time_slice; +@ + LDR r2, =_tx_timer_time_slice @ Pickup address of time slice + @ variable + ADD r2, r2, r12 @ Build index into the time-slice array + LDR sp, [r0, #8] @ Switch stack pointers + STR r3, [r2, #0] @ Setup time-slice +@ +@ /* Switch to the thread's stack. */ +@ sp = _tx_thread_execute_ptr[core] -> tx_thread_stack_ptr; +@ +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the thread entry function to indicate the thread is executing. */ +@ + MOV r5, r0 @ Save r0 + BL _tx_execution_thread_enter @ Call the thread execution enter function + MOV r0, r5 @ Restore r0 +#endif +@ +@ /* Determine if an interrupt frame or a synchronous task suspension frame +@ is present. */ +@ + LDMIA sp!, {r4, r5} @ Pickup the stack type and saved CPSR + CMP r4, #0 @ Check for synchronous context switch + BEQ _tx_solicited_return + MSR SPSR_cxsf, r5 @ Setup SPSR for return +#ifdef TARGET_FPU_VFP + LDR r1, [r0, #160] @ Pickup the VFP enabled flag + CMP r1, #0 @ Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore @ No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} @ Recover D0-D15 + VLDMIA sp!, {D16-D31} @ Recover D16-D31 + LDR r4, [sp], #4 @ Pickup FPSCR + FMXR FPSCR, r4 @ Restore FPSCR +_tx_skip_interrupt_vfp_restore: +#endif + LDMIA sp!, {r0-r12, lr, pc}^ @ Return to point of thread interrupt + +_tx_solicited_return: + +#ifdef TARGET_FPU_VFP + MSR CPSR_cxsf, r5 @ Recover CPSR + LDR r1, [r0, #160] @ Pickup the VFP enabled flag + CMP r1, #0 @ Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore @ No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} @ Recover D8-D15 + VLDMIA sp!, {D16-D31} @ Recover D16-D31 + LDR r4, [sp], #4 @ Pickup FPSCR + FMXR FPSCR, r4 @ Restore FPSCR +_tx_skip_solicited_vfp_restore: +#endif + MSR CPSR_cxsf, r5 @ Recover CPSR + LDMIA sp!, {r4-r11, lr} @ Return to thread synchronously +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@ +@} +@ +#ifdef TARGET_FPU_VFP + .global tx_thread_vfp_enable +tx_thread_vfp_enable: + MRS r2, CPSR @ Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif + MRC p15, 0, r1, c0, c0, 5 @ Read CPU ID register + AND r1, r1, #0x03 @ Mask off, leaving the CPU ID field + LSL r1, r1, #2 @ Build offset to array indexes + LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address + ADD r0, r0, r1 @ Build index into the current thread array + LDR r1, [r0] @ Pickup current thread pointer + CMP r1, #0 @ Check for NULL thread pointer + BEQ __tx_no_thread_to_enable @ If NULL, skip VFP enable + MOV r0, #1 @ Build enable value + STR r0, [r1, #160] @ Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable: + MSR CPSR_cxsf, r2 @ Recover CPSR + BX LR @ Return to caller + + .global tx_thread_vfp_disable +tx_thread_vfp_disable: + MRS r2, CPSR @ Pickup the CPSR +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif + MRC p15, 0, r1, c0, c0, 5 @ Read CPU ID register + AND r1, r1, #0x03 @ Mask off, leaving the CPU ID field + LSL r1, r1, #2 @ Build offset to array indexes + LDR r0, =_tx_thread_current_ptr @ Build current thread pointer address + ADD r0, r0, r1 @ Build index into the current thread array + LDR r1, [r0] @ Pickup current thread pointer + CMP r1, #0 @ Check for NULL thread pointer + BEQ __tx_no_thread_to_disable @ If NULL, skip VFP disable + MOV r0, #0 @ Build disable value + STR r0, [r1, #160] @ Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable: + MSR CPSR_cxsf, r2 @ Recover CPSR + BX LR @ Return to caller +#endif + + diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_core_get.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_core_get.S new file mode 100644 index 00000000..5c49f8c7 --- /dev/null +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_core_get.S @@ -0,0 +1,86 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread - Low Level SMP Support */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@#define TX_THREAD_SMP_SOURCE_CODE +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" */ +@ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_core_get SMP/Cortex-A7/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function gets the currently running core number and returns it.*/ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* Core ID */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Source */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ + .global _tx_thread_smp_core_get + .type _tx_thread_smp_core_get,function +_tx_thread_smp_core_get: + MRC p15, 0, r0, c0, c0, 5 @ Read CPU ID register + AND r0, r0, #0x03 @ Mask off, leaving the CPU ID field + +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif + + diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_core_preempt.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_core_preempt.S new file mode 100644 index 00000000..e8451f10 --- /dev/null +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_core_preempt.S @@ -0,0 +1,105 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread - Low Level SMP Support */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@#define TX_THREAD_SMP_SOURCE_CODE +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" */ +@ +@ +@/* for Cortex-A7 */ +@ IMPORT send_sgi + .global endSGI + + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_core_preempt SMP/Cortex-A7/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function preempts the specified core in situations where the */ +@/* thread corresponding to this core is no longer ready or when the */ +@/* core must be used for a higher-priority thread. If the specified is */ +@/* the current core, this processing is skipped since the will give up */ +@/* control subsequently on its own. */ +@/* */ +@/* INPUT */ +@/* */ +@/* core The core to preempt */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Source */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ + .global _tx_thread_smp_core_preempt + .type _tx_thread_smp_core_preempt,function +_tx_thread_smp_core_preempt: + + STMDB sp!, {r4, lr} @ Save the lr and r4 register on the stack +@ +@ /* Place call to send inter-processor interrupt here! */ +@ + DSB @ + MOV r1, #1 @ Build parameter list + LSL r1, r1, r0 @ + MOV r0, #0 @ + MOV r2, #0 @ + BL sendSGI @ Make call to send inter-processor interrupt + + LDMIA sp!, {r4, lr} @ Recover lr register and r4 +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif + + + diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_current_state_get.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_current_state_get.S new file mode 100644 index 00000000..d55e32c0 --- /dev/null +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_current_state_get.S @@ -0,0 +1,104 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread - Low Level SMP Support */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@#define TX_THREAD_SMP_SOURCE_CODE +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" */ +@ +@ + .global _tx_thread_system_state + + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_current_state_get SMP/Cortex-A7/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is gets the current state of the calling core. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Components */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ + .global _tx_thread_smp_current_state_get + .type _tx_thread_smp_current_state_get,function +_tx_thread_smp_current_state_get: + + MRS r3, CPSR @ Pickup current CPSR + +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif +@ +@ /* Pickup the CPU ID. */ +@ + MRC p15, 0, r2, c0, c0, 5 @ Read CPU ID register + AND r2, r2, #0x03 @ Mask off, leaving the CPU ID field + LSL r2, r2, #2 @ Build offset to array indexes + + LDR r1, =_tx_thread_system_state @ Pickup start of the current state array + ADD r1, r1, r2 @ Build index into the current state array + LDR r0, [r1] @ Pickup state for this core + MSR CPSR_c, r3 @ Restore CPSR +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif + + diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_current_thread_get.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_current_thread_get.S new file mode 100644 index 00000000..ddc26a35 --- /dev/null +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_current_thread_get.S @@ -0,0 +1,104 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread - Low Level SMP Support */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@#define TX_THREAD_SMP_SOURCE_CODE +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" */ +@ +@ + .global _tx_thread_current_ptr + + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_current_thread_get SMP/Cortex-A7/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is gets the current thread of the calling core. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Components */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ + .global _tx_thread_smp_current_thread_get + .type _tx_thread_smp_current_thread_get,function +_tx_thread_smp_current_thread_get: + + MRS r3, CPSR @ Pickup current CPSR + +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif +@ +@ /* Pickup the CPU ID. */ +@ + MRC p15, 0, r2, c0, c0, 5 @ Read CPU ID register + AND r2, r2, #0x03 @ Mask off, leaving the CPU ID field + LSL r2, r2, #2 @ Build offset to array indexes + + LDR r1, =_tx_thread_current_ptr @ Pickup start of the current thread array + ADD r1, r1, r2 @ Build index into the current thread array + LDR r0, [r1] @ Pickup current thread for this core + MSR CPSR_c, r3 @ Restore CPSR +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif + + diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_initialize_wait.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_initialize_wait.S new file mode 100644 index 00000000..cd5ef515 --- /dev/null +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_initialize_wait.S @@ -0,0 +1,142 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread - Low Level SMP Support */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@#define TX_THREAD_SMP_SOURCE_CODE +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" */ +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr + .global _tx_thread_smp_release_cores_flag + .global _tx_thread_schedule + + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_initialize_wait SMP/Cortex-A7/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is the place where additional cores wait until */ +@/* initialization is complete before they enter the thread scheduling */ +@/* loop. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling loop */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* Hardware */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ + .global _tx_thread_smp_initialize_wait + .type _tx_thread_smp_initialize_wait,function +_tx_thread_smp_initialize_wait: + +@ /* Lockout interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif +@ +@ /* Pickup the CPU ID. */ +@ + MRC p15, 0, r10, c0, c0, 5 @ Read CPU ID register + AND r10, r10, #0x03 @ Mask off, leaving the CPU ID field + LSL r10, r10, #2 @ Build offset to array indexes +@ +@ /* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release +@ flag. */ +@ + LDR r3, =_tx_thread_system_state @ Build address of system state variable + ADD r3, r3, r10 @ Build index into the system state array + LDR r2, =0xF0F0F0F0 @ Build TX_INITIALIZE_IN_PROGRESS flag +wait_for_initialize: + LDR r1, [r3] @ Pickup system state + CMP r1, r2 @ Has initialization completed? + BNE wait_for_initialize @ If different, wait here! +@ +@ /* Pickup the release cores flag. */ +@ + LDR r2, =_tx_thread_smp_release_cores_flag @ Build address of release cores flag + +wait_for_release: + LDR r3, [r2] @ Pickup the flag + CMP r3, #0 @ Is it set? + BEQ wait_for_release @ Wait for the flag to be set +@ +@ /* Core 0 has released this core. */ +@ +@ /* Clear this core's system state variable. */ +@ + LDR r3, =_tx_thread_system_state @ Build address of system state variable + ADD r3, r3, r10 @ Build index into the system state array + MOV r0, #0 @ Build clear value + STR r0, [r3] @ Clear this core's entry in the system state array +@ +@ /* Now wait for core 0 to finish it's initialization. */ +@ + LDR r3, =_tx_thread_system_state @ Build address of system state variable of logical 0 + +core_0_wait_loop: + LDR r2, [r3] @ Pickup system state for core 0 + CMP r2, #0 @ Is it 0? + BNE core_0_wait_loop @ No, keep waiting for core 0 to finish its initialization +@ +@ /* Initialize is complete, enter the scheduling loop! */ +@ + B _tx_thread_schedule @ Enter scheduling loop for this core! + + + diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_low_level_initialize.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_low_level_initialize.S new file mode 100644 index 00000000..313148a1 --- /dev/null +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_low_level_initialize.S @@ -0,0 +1,86 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread - Low Level SMP Support */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@#define TX_THREAD_SMP_SOURCE_CODE +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" */ +@ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_low_level_initialize SMP/Cortex-A7/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function performs low-level initialization of the booting */ +@/* core. */ +@/* */ +@/* INPUT */ +@/* */ +@/* number_of_cores Number of cores */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_initialize_high_level ThreadX high-level init */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ + .global _tx_thread_smp_low_level_initialize + .type _tx_thread_smp_low_level_initialize,function +_tx_thread_smp_low_level_initialize: + +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif + + + diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_protect.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_protect.S new file mode 100644 index 00000000..16e5c014 --- /dev/null +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_protect.S @@ -0,0 +1,370 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread - Low Level SMP Support */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@#define TX_THREAD_SMP_SOURCE_CODE +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" */ + +@/* Include macros for modifying the wait list. */ +#include "tx_thread_smp_protection_wait_list_macros.h" + + .global _tx_thread_current_ptr + .global _tx_thread_smp_protection + .global _tx_thread_smp_protect_wait_counts + .global _tx_thread_smp_protect_wait_list + .global _tx_thread_smp_protect_wait_list_lock_protect_in_force + .global _tx_thread_smp_protect_wait_list_head + .global _tx_thread_smp_protect_wait_list_tail + .global _tx_thread_smp_protect_wait_list_size + + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_protect SMP/Cortex-A7/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function gets protection for running inside the ThreadX */ +@/* source. This is ccomplished by a combination of a test-and-set */ +@/* flag and periodically disabling interrupts. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* Previous Status Register */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Source */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ + .global _tx_thread_smp_protect + .type _tx_thread_smp_protect,function +_tx_thread_smp_protect: +@VOID _tx_thread_smp_protect(VOID) +@{ +@ + PUSH {r4-r6} @ Save registers we'll be using +@ +@ /* Disable interrupts so we don't get preempted. */ +@ + MRS r0, CPSR @ Pickup current CPSR + +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts + ELSE + CPSID i @ Disable IRQ interrupts +#endif +@ +@ /* Do we already have protection? */ +@ if (this_core == _tx_thread_smp_protection.tx_thread_smp_protect_core) +@ { +@ + MRC p15, 0, r1, c0, c0, 5 @ Read CPU ID register + AND r1, r1, #0x03 @ Mask off, leaving the CPU ID field + LDR r2, =_tx_thread_smp_protection @ Build address to protection structure + LDR r3, [r2, #8] @ Pickup the owning core + CMP r1, r3 @ Is it not this core? + BNE _protection_not_owned @ No, the protection is not already owned +@ +@ /* We already have protection. */ +@ +@ /* Increment the protection count. */ +@ _tx_thread_smp_protection.tx_thread_smp_protect_count++; +@ + LDR r3, [r2, #12] @ Pickup ownership count + ADD r3, r3, #1 @ Increment ownership count + STR r3, [r2, #12] @ Store ownership count + DMB + + B _return + +_protection_not_owned: +@ +@ /* Is the lock available? */ +@ if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0) +@ { +@ + LDREX r3, [r2, #0] @ Pickup the protection flag + CMP r3, #0 + BNE _start_waiting @ No, protection not available +@ +@ /* Is the list empty? */ +@ if (_tx_thread_smp_protect_wait_list_head == _tx_thread_smp_protect_wait_list_tail) +@ { +@ + LDR r3, =_tx_thread_smp_protect_wait_list_head + LDR r3, [r3] + LDR r4, =_tx_thread_smp_protect_wait_list_tail + LDR r4, [r4] + CMP r3, r4 + BNE _list_not_empty +@ +@ /* Try to get the lock. */ +@ if (write_exclusive(&_tx_thread_smp_protection.tx_thread_smp_protect_in_force, 1) == SUCCESS) +@ { +@ + MOV r3, #1 @ Build lock value + STREX r4, r3, [r2, #0] @ Attempt to get the protection + CMP r4, #0 + BNE _start_waiting @ Did it fail? +@ +@ /* We got the lock! */ +@ _tx_thread_smp_protect_lock_got(); +@ + DMB @ Ensure write to protection finishes + _tx_thread_smp_protect_lock_got @ Call the lock got function + + B _return + +_list_not_empty: +@ +@ /* Are we at the front of the list? */ +@ if (this_core == _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head]) +@ { +@ + LDR r3, =_tx_thread_smp_protect_wait_list_head @ Get the address of the head + LDR r3, [r3] @ Get the value of the head + LDR r4, =_tx_thread_smp_protect_wait_list @ Get the address of the list + LDR r4, [r4, r3, LSL #2] @ Get the value at the head index + + CMP r1, r4 + BNE _start_waiting +@ +@ /* Is the lock still available? */ +@ if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0) +@ { +@ + LDR r3, [r2, #0] @ Pickup the protection flag + CMP r3, #0 + BNE _start_waiting @ No, protection not available +@ +@ /* Get the lock. */ +@ _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1; +@ + MOV r3, #1 @ Build lock value + STR r3, [r2, #0] @ Store lock value + DMB @ +@ +@ /* Got the lock. */ +@ _tx_thread_smp_protect_lock_got(); +@ + _tx_thread_smp_protect_lock_got +@ +@ /* Remove this core from the wait list. */ +@ _tx_thread_smp_protect_remove_from_front_of_list(); +@ + _tx_thread_smp_protect_remove_from_front_of_list + + B _return + +_start_waiting: +@ +@ /* For one reason or another, we didn't get the lock. */ +@ +@ /* Increment wait count. */ +@ _tx_thread_smp_protect_wait_counts[this_core]++; +@ + LDR r3, =_tx_thread_smp_protect_wait_counts @ Load wait list counts + LDR r4, [r3, r1, LSL #2] @ Load waiting value for this core + ADD r4, r4, #1 @ Increment wait value + STR r4, [r3, r1, LSL #2] @ Store new wait value +@ +@ /* Have we not added ourselves to the list yet? */ +@ if (_tx_thread_smp_protect_wait_counts[this_core] == 1) +@ { +@ + CMP r4, #1 + BNE _already_in_list0 @ Is this core already waiting? +@ +@ /* Add ourselves to the list. */ +@ _tx_thread_smp_protect_wait_list_add(this_core); +@ + _tx_thread_smp_protect_wait_list_add @ Call macro to add ourselves to the list +@ +@ } +@ +_already_in_list0: +@ +@ /* Restore interrupts. */ +@ + MSR CPSR_c, r0 @ Restore CPSR +#ifdef TX_ENABLE_WFE + WFE @ Go into standby +#endif +@ +@ /* We do this until we have the lock. */ +@ while (1) +@ { +@ +_try_to_get_lock: +@ +@ /* Disable interrupts so we don't get preempted. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts + ELSE + CPSID i @ Disable IRQ interrupts +#endif + + MRC p15, 0, r1, c0, c0, 5 @ Read CPU ID register + AND r1, r1, #0x03 @ Mask off, leaving the CPU ID field +@ +@ /* Do we already have protection? */ +@ if (this_core == _tx_thread_smp_protection.tx_thread_smp_protect_core) +@ { +@ + LDR r3, [r2, #8] @ Pickup the owning core + CMP r3, r1 @ Is it this core? + BEQ _got_lock_after_waiting @ Yes, the protection is already owned. This means + @ an ISR preempted us and got protection +@ +@ } +@ +@ /* Are we at the front of the list? */ +@ if (this_core == _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head]) +@ { +@ + LDR r3, =_tx_thread_smp_protect_wait_list_head @ Get the address of the head + LDR r3, [r3] @ Get the value of the head + LDR r4, =_tx_thread_smp_protect_wait_list @ Get the address of the list + LDR r4, [r4, r3, LSL #2] @ Get the value at the head index + + CMP r1, r4 + BNE _did_not_get_lock +@ +@ /* Is the lock still available? */ +@ if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0) +@ { +@ + LDR r3, [r2, #0] @ Pickup the protection flag + CMP r3, #0 + BNE _did_not_get_lock @ No, protection not available +@ +@ /* Get the lock. */ +@ _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1; +@ + MOV r3, #1 @ Build lock value + STR r3, [r2, #0] @ Store lock value + DMB @ +@ +@ /* Got the lock. */ +@ _tx_thread_smp_protect_lock_got(); +@ + _tx_thread_smp_protect_lock_got +@ +@ /* Remove this core from the wait list. */ +@ _tx_thread_smp_protect_remove_from_front_of_list(); +@ + _tx_thread_smp_protect_remove_from_front_of_list + + B _got_lock_after_waiting + +_did_not_get_lock: +@ +@ /* For one reason or another, we didn't get the lock. */ +@ +@ /* Were we removed from the list? This can happen if we're a thread +@ and we got preempted. */ +@ if (_tx_thread_smp_protect_wait_counts[this_core] == 0) +@ { +@ + LDR r3, =_tx_thread_smp_protect_wait_counts @ Load wait list counts + LDR r4, [r3, r1, LSL #2] @ Load waiting value for this core + CMP r4, #0 + BNE _already_in_list1 @ Is this core already in the list? +@ +@ /* Add ourselves to the list. */ +@ _tx_thread_smp_protect_wait_list_add(this_core); +@ + _tx_thread_smp_protect_wait_list_add @ Call macro to add ourselves to the list +@ +@ /* Our waiting count was also reset when we were preempted. Increment it again. */ +@ _tx_thread_smp_protect_wait_counts[this_core]++; +@ + LDR r3, =_tx_thread_smp_protect_wait_counts @ Load wait list counts + LDR r4, [r3, r1, LSL #2] @ Load waiting value for this core + ADD r4, r4, #1 @ Increment wait value + STR r4, [r3, r1, LSL #2] @ Store new wait value value +@ +@ } +@ +_already_in_list1: +@ +@ /* Restore interrupts and try again. */ +@ + MSR CPSR_c, r0 @ Restore CPSR +#ifdef TX_ENABLE_WFE + WFE @ Go into standby +#endif + B _try_to_get_lock @ On waking, restart the protection attempt + +_got_lock_after_waiting: +@ +@ /* We're no longer waiting. */ +@ _tx_thread_smp_protect_wait_counts[this_core]--; +@ + LDR r3, =_tx_thread_smp_protect_wait_counts @ Load waiting list + LDR r4, [r3, r1, LSL #2] @ Load current wait value + SUB r4, r4, #1 @ Decrement wait value + STR r4, [r3, r1, LSL #2] @ Store new wait value value + +@ +@ /* Restore link register and return. */ +@ +_return: + + POP {r4-r6} @ Restore registers + +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif + diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h new file mode 100644 index 00000000..83f071a7 --- /dev/null +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_protection_wait_list_macros.h @@ -0,0 +1,309 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread - Low Level SMP Support */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ + + .macro _tx_thread_smp_protect_lock_got +@ +@ /* Set the currently owned core. */ +@ _tx_thread_smp_protection.tx_thread_smp_protect_core = this_core; +@ + STR r1, [r2, #8] @ Store this core +@ +@ /* Increment the protection count. */ +@ _tx_thread_smp_protection.tx_thread_smp_protect_count++; +@ + LDR r3, [r2, #12] @ Pickup ownership count + ADD r3, r3, #1 @ Increment ownership count + STR r3, [r2, #12] @ Store ownership count + DMB + +#ifdef TX_MPCORE_DEBUG_ENABLE + LSL r3, r1, #2 @ Build offset to array indexes + LDR r4, =_tx_thread_current_ptr @ Pickup start of the current thread array + ADD r4, r3, r4 @ Build index into the current thread array + LDR r3, [r4] @ Pickup current thread for this core + STR r3, [r2, #4] @ Save current thread pointer + STR LR, [r2, #16] @ Save caller's return address + STR r0, [r2, #20] @ Save CPSR +#endif + + .endm + + .macro _tx_thread_smp_protect_remove_from_front_of_list +@ +@ /* Remove ourselves from the list. */ +@ _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head++] = 0xFFFFFFFF; +@ + MOV r3, #0xFFFFFFFF @ Build the invalid core value + LDR r4, =_tx_thread_smp_protect_wait_list_head @ Get the address of the head + LDR r5, [r4] @ Get the value of the head + LDR r6, =_tx_thread_smp_protect_wait_list @ Get the address of the list + STR r3, [r6, r5, LSL #2] @ Store the invalid core value + ADD r5, r5, #1 @ Increment the head +@ +@ /* Did we wrap? */ +@ if (_tx_thread_smp_protect_wait_list_head == TX_THREAD_SMP_MAX_CORES + 1) +@ { +@ + LDR r3, =_tx_thread_smp_protect_wait_list_size @ Load address of core list size + LDR r3, [r3] @ Load the max cores value + CMP r5, r3 @ Compare the head to it + BNE _store_new_head\@ @ Are we at the max? +@ +@ _tx_thread_smp_protect_wait_list_head = 0; +@ + EOR r5, r5, r5 @ We're at the max. Set it to zero +@ +@ } +@ +_store_new_head\@: + + STR r5, [r4] @ Store the new head +@ +@ /* We have the lock! */ +@ return; +@ + .endm + + + .macro _tx_thread_smp_protect_wait_list_lock_get +@VOID _tx_thread_smp_protect_wait_list_lock_get() +@{ +@ /* We do this until we have the lock. */ +@ while (1) +@ { +@ +_tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@: +@ +@ /* Is the list lock available? */ +@ _tx_thread_smp_protect_wait_list_lock_protect_in_force = load_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force); +@ + LDR r1, =_tx_thread_smp_protect_wait_list_lock_protect_in_force + LDREX r2, [r1] @ Pickup the protection flag +@ +@ if (protect_in_force == 0) +@ { +@ + CMP r2, #0 + BNE _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@ @ No, protection not available +@ +@ /* Try to get the list. */ +@ int status = store_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force, 1); +@ + MOV r2, #1 @ Build lock value + STREX r3, r2, [r1] @ Attempt to get the protection +@ +@ if (status == SUCCESS) +@ + CMP r3, #0 + BNE _tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock\@ @ Did it fail? If so, try again. +@ +@ /* We have the lock! */ +@ return; +@ + .endm + + + .macro _tx_thread_smp_protect_wait_list_add +@VOID _tx_thread_smp_protect_wait_list_add(UINT new_core) +@{ +@ +@ /* We're about to modify the list, so get the list lock. */ +@ _tx_thread_smp_protect_wait_list_lock_get(); +@ + PUSH {r1-r2} + + _tx_thread_smp_protect_wait_list_lock_get + + POP {r1-r2} +@ +@ /* Add this core. */ +@ _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_tail++] = new_core; +@ + LDR r3, =_tx_thread_smp_protect_wait_list_tail @ Get the address of the tail + LDR r4, [r3] @ Get the value of tail + LDR r5, =_tx_thread_smp_protect_wait_list @ Get the address of the list + STR r1, [r5, r4, LSL #2] @ Store the new core value + ADD r4, r4, #1 @ Increment the tail +@ +@ /* Did we wrap? */ +@ if (_tx_thread_smp_protect_wait_list_tail == _tx_thread_smp_protect_wait_list_size) +@ { +@ + LDR r5, =_tx_thread_smp_protect_wait_list_size @ Load max cores address + LDR r5, [r5] @ Load max cores value + CMP r4, r5 @ Compare max cores to tail + BNE _tx_thread_smp_protect_wait_list_add__no_wrap\@ @ Did we wrap? +@ +@ _tx_thread_smp_protect_wait_list_tail = 0; +@ + MOV r4, #0 +@ +@ } +@ +_tx_thread_smp_protect_wait_list_add__no_wrap\@: + + STR r4, [r3] @ Store the new tail value. +@ +@ /* Release the list lock. */ +@ _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; +@ + MOV r3, #0 @ Build lock value + LDR r4, =_tx_thread_smp_protect_wait_list_lock_protect_in_force + STR r3, [r4] @ Store the new value + + .endm + + + .macro _tx_thread_smp_protect_wait_list_remove +@VOID _tx_thread_smp_protect_wait_list_remove(UINT core) +@{ +@ +@ /* Get the core index. */ +@ UINT core_index; +@ for (core_index = 0;; core_index++) +@ + EOR r1, r1, r1 @ Clear for 'core_index' + LDR r2, =_tx_thread_smp_protect_wait_list @ Get the address of the list +@ +@ { +@ +_tx_thread_smp_protect_wait_list_remove__check_cur_core\@: +@ +@ /* Is this the core? */ +@ if (_tx_thread_smp_protect_wait_list[core_index] == core) +@ { +@ break; +@ + LDR r3, [r2, r1, LSL #2] @ Get the value at the current index + CMP r3, r10 @ Did we find the core? + BEQ _tx_thread_smp_protect_wait_list_remove__found_core\@ +@ +@ } +@ + ADD r1, r1, #1 @ Increment cur index + B _tx_thread_smp_protect_wait_list_remove__check_cur_core\@ @ Restart the loop +@ +@ } +@ +_tx_thread_smp_protect_wait_list_remove__found_core\@: +@ +@ /* We're about to modify the list. Get the lock. We need the lock because another +@ core could be simultaneously adding (a core is simultaneously trying to get +@ the inter-core lock) or removing (a core is simultaneously being preempted, +@ like what is currently happening). */ +@ _tx_thread_smp_protect_wait_list_lock_get(); +@ + PUSH {r1} + + _tx_thread_smp_protect_wait_list_lock_get + + POP {r1} +@ +@ /* We remove by shifting. */ +@ while (core_index != _tx_thread_smp_protect_wait_list_tail) +@ { +@ +_tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@: + + LDR r2, =_tx_thread_smp_protect_wait_list_tail @ Load tail address + LDR r2, [r2] @ Load tail value + CMP r1, r2 @ Compare cur index and tail + BEQ _tx_thread_smp_protect_wait_list_remove__removed\@ +@ +@ UINT next_index = core_index + 1; +@ + MOV r2, r1 @ Move current index to next index register + ADD r2, r2, #1 @ Add 1 +@ +@ if (next_index == _tx_thread_smp_protect_wait_list_size) +@ { +@ + LDR r3, =_tx_thread_smp_protect_wait_list_size + LDR r3, [r3] + CMP r2, r3 + BNE _tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@ +@ +@ next_index = 0; +@ + MOV r2, #0 +@ +@ } +@ +_tx_thread_smp_protect_wait_list_remove__next_index_no_wrap\@: +@ +@ list_cores[core_index] = list_cores[next_index]; +@ + LDR r0, =_tx_thread_smp_protect_wait_list @ Get the address of the list + LDR r3, [r0, r2, LSL #2] @ Get the value at the next index + STR r3, [r0, r1, LSL #2] @ Store the value at the current index +@ +@ core_index = next_index; +@ + MOV r1, r2 + + B _tx_thread_smp_protect_wait_list_remove__compare_index_to_tail\@ +@ +@ } +@ +_tx_thread_smp_protect_wait_list_remove__removed\@: +@ +@ /* Now update the tail. */ +@ if (_tx_thread_smp_protect_wait_list_tail == 0) +@ { +@ + LDR r0, =_tx_thread_smp_protect_wait_list_tail @ Load tail address + LDR r1, [r0] @ Load tail value + CMP r1, #0 + BNE _tx_thread_smp_protect_wait_list_remove__tail_not_zero\@ +@ +@ _tx_thread_smp_protect_wait_list_tail = _tx_thread_smp_protect_wait_list_size; +@ + LDR r2, =_tx_thread_smp_protect_wait_list_size + LDR r1, [r2] +@ +@ } +@ +_tx_thread_smp_protect_wait_list_remove__tail_not_zero\@: +@ +@ _tx_thread_smp_protect_wait_list_tail--; +@ + SUB r1, r1, #1 + STR r1, [r0] @ Store new tail value +@ +@ /* Release the list lock. */ +@ _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; +@ + MOV r0, #0 @ Build lock value + LDR r1, =_tx_thread_smp_protect_wait_list_lock_protect_in_force @ Load lock address + STR r0, [r1] @ Store the new value +@ +@ /* We're no longer waiting. Note that this should be zero since, again, +@ this function is only called when a thread preemption is occurring. */ +@ _tx_thread_smp_protect_wait_counts[core]--; +@ + LDR r1, =_tx_thread_smp_protect_wait_counts @ Load wait list counts + LDR r2, [r1, r10, LSL #2] @ Load waiting value + SUB r2, r2, #1 @ Subtract 1 + STR r2, [r1, r10, LSL #2] @ Store new waiting value + + .endm + diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_time_get.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_time_get.S new file mode 100644 index 00000000..efaf8867 --- /dev/null +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_time_get.S @@ -0,0 +1,89 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread - Low Level SMP Support */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@#define TX_THREAD_SMP_SOURCE_CODE +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" */ +@ +@ + + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_time_get SMP/Cortex-A7/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function gets the global time value that is used for debug */ +@/* information and event tracing. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* 32-bit time stamp */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Source */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ + .global _tx_thread_smp_time_get + .type _tx_thread_smp_time_get,function +_tx_thread_smp_time_get: + + MRC p15, 4, r0, c15, c0, 0 @ Read periph base address + LDR r0, [r0, #0x604] @ Read count register + +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif + + diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_unprotect.s b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_unprotect.s new file mode 100644 index 00000000..97f6fd0f --- /dev/null +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_smp_unprotect.s @@ -0,0 +1,142 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread - Low Level SMP Support */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@#define TX_THREAD_SMP_SOURCE_CODE +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" */ +@ +@ + .global _tx_thread_current_ptr + .global _tx_thread_smp_protection + .global _tx_thread_preempt_disable + .global _tx_thread_smp_protect_wait_counts + + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_smp_unprotect SMP/Cortex-A7/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function releases previously obtained protection. The supplied */ +@/* previous SR is restored. If the value of _tx_thread_system_state */ +@/* and _tx_thread_preempt_disable are both zero, then multithreading */ +@/* is enabled as well. */ +@/* */ +@/* INPUT */ +@/* */ +@/* Previous Status Register */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX Source */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ + .global _tx_thread_smp_unprotect + .type _tx_thread_smp_unprotect,function +_tx_thread_smp_unprotect: +@ +@ /* Lockout interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif + + MRC p15, 0, r1, c0, c0, 5 @ Read CPU ID register + AND r1, r1, #0x03 @ Mask off, leaving the CPU ID field + + LDR r2,=_tx_thread_smp_protection @ Build address of protection structure + LDR r3, [r2, #8] @ Pickup the owning core + CMP r1, r3 @ Is it this core? + BNE _still_protected @ If this is not the owning core, protection is in force elsewhere + + LDR r3, [r2, #12] @ Pickup the protection count + CMP r3, #0 @ Check to see if the protection is still active + BEQ _still_protected @ If the protection count is zero, protection has already been cleared + + SUB r3, r3, #1 @ Decrement the protection count + STR r3, [r2, #12] @ Store the new count back + CMP r3, #0 @ Check to see if the protection is still active + BNE _still_protected @ If the protection count is non-zero, protection is still in force + LDR r2,=_tx_thread_preempt_disable @ Build address of preempt disable flag + LDR r3, [r2] @ Pickup preempt disable flag + CMP r3, #0 @ Is the preempt disable flag set? + BNE _still_protected @ Yes, skip the protection release + + LDR r2,=_tx_thread_smp_protect_wait_counts @ Build build address of wait counts + LDR r3, [r2, r1, LSL #2] @ Pickup wait list value + CMP r3, #0 @ Are any entities on this core waiting? + BNE _still_protected @ Yes, skip the protection release + + LDR r2,=_tx_thread_smp_protection @ Build address of protection structure + MOV r3, #0xFFFFFFFF @ Build invalid value + STR r3, [r2, #8] @ Mark the protected core as invalid +#ifdef TX_MPCORE_DEBUG_ENABLE + STR LR, [r2, #16] @ Save caller's return address +#endif + DMB @ Ensure that accesses to shared resource have completed + MOV r3, #0 @ Build release protection value + STR r3, [r2, #0] @ Release the protection + DSB @ To ensure update of the protection occurs before other CPUs awake +#ifdef TX_ENABLE_WFE + SEV @ Send event to other CPUs, wakes anyone waiting on the protection (using WFE) +#endif + +_still_protected: + MSR CPSR_c, r0 @ Restore CPSR + +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif + diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_stack_build.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_stack_build.S new file mode 100644 index 00000000..ec5b3792 --- /dev/null +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_stack_build.S @@ -0,0 +1,174 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ +SVC_MODE = 0x13 @ SVC mode +#ifdef TX_ENABLE_FIQ_SUPPORT +CPSR_MASK = 0xDF @ Mask initial CPSR, IRQ & FIQ ints enabled +#else +CPSR_MASK = 0x9F @ Mask initial CPSR, IRQ ints enabled +#endif + +THUMB_BIT = 0x20 @ Thumb-bit + +@ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_stack_build SMP/Cortex-A7/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function builds a stack frame on the supplied thread's stack. */ +@/* The stack frame results in a fake interrupt return to the supplied */ +@/* function pointer. */ +@/* */ +@/* INPUT */ +@/* */ +@/* thread_ptr Pointer to thread control blk */ +@/* function_ptr Pointer to return function */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* _tx_thread_create Create thread service */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +@{ + .global _tx_thread_stack_build + .type _tx_thread_stack_build,function +_tx_thread_stack_build: +@ +@ +@ /* Build a fake interrupt frame. The form of the fake interrupt stack +@ on the Cortex-A7 should look like the following after it is built: +@ +@ Stack Top: 1 Interrupt stack frame type +@ CPSR Initial value for CPSR +@ a1 (r0) Initial value for a1 +@ a2 (r1) Initial value for a2 +@ a3 (r2) Initial value for a3 +@ a4 (r3) Initial value for a4 +@ v1 (r4) Initial value for v1 +@ v2 (r5) Initial value for v2 +@ v3 (r6) Initial value for v3 +@ v4 (r7) Initial value for v4 +@ v5 (r8) Initial value for v5 +@ sb (r9) Initial value for sb +@ sl (r10) Initial value for sl +@ fp (r11) Initial value for fp +@ ip (r12) Initial value for ip +@ lr (r14) Initial value for lr +@ pc (r15) Initial value for pc +@ 0 For stack backtracing +@ +@ Stack Bottom: (higher memory address) */ +@ + LDR r2, [r0, #16] @ Pickup end of stack area + BIC r2, r2, #7 @ Ensure 8-byte alignment + SUB r2, r2, #76 @ Allocate space for the stack frame +@ +@ /* Actually build the stack frame. */ +@ + MOV r3, #1 @ Build interrupt stack type + STR r3, [r2, #0] @ Store stack type + MOV r3, #0 @ Build initial register value + STR r3, [r2, #8] @ Store initial r0 + STR r3, [r2, #12] @ Store initial r1 + STR r3, [r2, #16] @ Store initial r2 + STR r3, [r2, #20] @ Store initial r3 + STR r3, [r2, #24] @ Store initial r4 + STR r3, [r2, #28] @ Store initial r5 + STR r3, [r2, #32] @ Store initial r6 + STR r3, [r2, #36] @ Store initial r7 + STR r3, [r2, #40] @ Store initial r8 + STR r3, [r2, #44] @ Store initial r9 + LDR r3, [r0, #12] @ Pickup stack starting address + STR r3, [r2, #48] @ Store initial r10 (sl) + MOV r3, #0 @ Build initial register value + STR r3, [r2, #52] @ Store initial r11 + STR r3, [r2, #56] @ Store initial r12 + STR r3, [r2, #60] @ Store initial lr + STR r1, [r2, #64] @ Store initial pc + STR r3, [r2, #68] @ 0 for back-trace + + MRS r3, CPSR @ Pickup CPSR + BIC r3, r3, #CPSR_MASK @ Mask mode bits of CPSR + ORR r3, r3, #SVC_MODE @ Build CPSR, SVC mode, interrupts enabled + BIC r3, r3, #THUMB_BIT @ Clear Thumb-bit by default + AND r1, r1, #1 @ Determine if the entry function is in Thumb mode + CMP r1, #1 @ Is the Thumb-bit set? + ORREQ r3, r3, #THUMB_BIT @ Yes, set the Thumb-bit + STR r3, [r2, #4] @ Store initial CPSR +@ +@ /* Setup stack pointer. */ +@ thread_ptr -> tx_thread_stack_ptr = r2; +@ + STR r2, [r0, #8] @ Save stack pointer in thread's + @ control block +@ +@ /* Set ready bit in thread control block. */ +@ + LDR r2, [r0, #152] @ Pickup word with ready bit + ORR r2, r2, #0x8000 @ Build ready bit set + STR r2, [r0, #152] @ Set ready bit + +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@} + + diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_system_return.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_system_return.S new file mode 100644 index 00000000..56b13be2 --- /dev/null +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_system_return.S @@ -0,0 +1,207 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@#include "tx_timer.h" +@ +@ + .global _tx_thread_current_ptr + .global _tx_timer_time_slice + .global _tx_thread_schedule + .global _tx_thread_preempt_disable + .global _tx_thread_smp_protection +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + .global _tx_execution_thread_exit +#endif +@ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_system_return SMP/Cortex-A7/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function is target processor specific. It is used to transfer */ +@/* control from a thread back to the ThreadX system. Only a */ +@/* minimal context is saved since the compiler assumes temp registers */ +@/* are going to get slicked by a function call anyway. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_schedule Thread scheduling loop */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ThreadX components */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_system_return(VOID) +@{ + .global _tx_thread_system_return + .type _tx_thread_system_return,function +_tx_thread_system_return: +@ +@ /* Save minimal context on the stack. */ +@ + STMDB sp!, {r4-r11, lr} @ Save minimal context +@ +@ /* Pickup the CPU ID. */ +@ + MRC p15, 0, r10, c0, c0, 5 @ Read CPU ID register + AND r10, r10, #0x03 @ Mask off, leaving the CPU ID field + LSL r12, r10, #2 @ Build offset to array indexes + + LDR r3, =_tx_thread_current_ptr @ Pickup address of current ptr + ADD r3, r3, r12 @ Build index into current ptr array + LDR r0, [r3, #0] @ Pickup current thread pointer +#ifdef TARGET_FPU_VFP + LDR r1, [r0, #160] @ Pickup the VFP enabled flag + CMP r1, #0 @ Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save @ No, skip VFP solicited save + FMRX r4, FPSCR @ Pickup the FPSCR + STR r4, [sp, #-4]! @ Save FPSCR + VSTMDB sp!, {D16-D31} @ Save D16-D31 + VSTMDB sp!, {D8-D15} @ Save D8-D15 +_tx_skip_solicited_vfp_save: +#endif + MOV r4, #0 @ Build a solicited stack type + MRS r5, CPSR @ Pickup the CPSR + STMDB sp!, {r4-r5} @ Save type and CPSR +@ +@ /* Lockout interrupts. */ +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#else + CPSID i @ Disable IRQ interrupts +#endif + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the thread exit function to indicate the thread is no longer executing. */ +@ + MOV r4, r0 @ Save r0 + MOV r5, r3 @ Save r3 + MOV r6, r12 @ Save r12 + BL _tx_execution_thread_exit @ Call the thread exit function + MOV r3, r5 @ Recover r3 + MOV r0, r4 @ Recover r4 + MOV r12,r6 @ Recover r12 +#endif +@ + LDR r2, =_tx_timer_time_slice @ Pickup address of time slice + ADD r2, r2, r12 @ Build index into time-slice array + LDR r1, [r2, #0] @ Pickup current time slice +@ +@ /* Save current stack and switch to system stack. */ +@ _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; +@ sp = _tx_thread_system_stack_ptr[core]; +@ + STR sp, [r0, #8] @ Save thread stack pointer +@ +@ /* Determine if the time-slice is active. */ +@ if (_tx_timer_time_slice[core]) +@ { +@ + MOV r4, #0 @ Build clear value + CMP r1, #0 @ Is a time-slice active? + BEQ __tx_thread_dont_save_ts @ No, don't save the time-slice +@ +@ /* Save time-slice for the thread and clear the current time-slice. */ +@ _tx_thread_current_ptr[core] -> tx_thread_time_slice = _tx_timer_time_slice[core]; +@ _tx_timer_time_slice[core] = 0; +@ + STR r4, [r2, #0] @ Clear time-slice + STR r1, [r0, #24] @ Save current time-slice +@ +@ } +__tx_thread_dont_save_ts: +@ +@ /* Clear the current thread pointer. */ +@ _tx_thread_current_ptr[core] = TX_NULL; +@ + STR r4, [r3, #0] @ Clear current thread pointer +@ +@ /* Set ready bit in thread control block. */ +@ + LDR r2, [r0, #152] @ Pickup word with ready bit + ORR r2, r2, #0x8000 @ Build ready bit set + DMB @ Ensure that accesses to shared resource have completed + STR r2, [r0, #152] @ Set ready bit +@ +@ /* Now clear protection. It is assumed that protection is in force whenever this routine is called. */ +@ + LDR r3, =_tx_thread_smp_protection @ Pickup address of protection structure + +#ifdef TX_MPCORE_DEBUG_ENABLE + STR lr, [r3, #24] @ Save last caller + LDR r2, [r3, #4] @ Pickup owning thread + CMP r0, r2 @ Is it the same as the current thread? +__error_loop: + BNE __error_loop @ If not, we have a problem!! +#endif + + LDR r1, =_tx_thread_preempt_disable @ Build address to preempt disable flag + MOV r2, #0 @ Build clear value + STR r2, [r1, #0] @ Clear preempt disable flag + STR r2, [r3, #12] @ Clear protection count + MOV r1, #0xFFFFFFFF @ Build invalid value + STR r1, [r3, #8] @ Set core to an invalid value + DMB @ Ensure that accesses to shared resource have completed + STR r2, [r3] @ Clear protection + DSB @ To ensure update of the shared resource occurs before other CPUs awake + SEV @ Send event to other CPUs, wakes anyone waiting on a mutex (using WFE) + + B _tx_thread_schedule @ Jump to scheduler! +@ +@} + + diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_thread_vectored_context_save.S b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_vectored_context_save.S new file mode 100644 index 00000000..e5ffcc69 --- /dev/null +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_thread_vectored_context_save.S @@ -0,0 +1,211 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Thread */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_thread.h" +@ +@ + .global _tx_thread_system_state + .global _tx_thread_current_ptr +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + .global _tx_execution_isr_enter +#endif +@ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_thread_vectored_context_save SMP/Cortex-A7/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function saves the context of an executing thread in the */ +@/* beginning of interrupt processing. The function also ensures that */ +@/* the system stack is used upon return to the calling ISR. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* None */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* ISRs */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_thread_vectored_context_save(VOID) +@{ + .global _tx_thread_vectored_context_save + .type _tx_thread_vectored_context_save,function +_tx_thread_vectored_context_save: +@ +@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +@ out, we are in IRQ mode, and all registers are intact. */ +@ +@ /* Check for a nested interrupt condition. */ +@ if (_tx_thread_system_state[core]++) +@ { +@ +#ifdef TX_ENABLE_FIQ_SUPPORT + CPSID if @ Disable IRQ and FIQ interrupts +#endif +@ +@ /* Pickup the CPU ID. */ +@ + MRC p15, 0, r10, c0, c0, 5 @ Read CPU ID register + AND r10, r10, #0x03 @ Mask off, leaving the CPU ID field + LSL r12, r10, #2 @ Build offset to array indexes + + LDR r3, =_tx_thread_system_state @ Pickup address of system state var + ADD r3, r3, r12 @ Build index into the system state array + LDR r2, [r3, #0] @ Pickup system state + CMP r2, #0 @ Is this the first interrupt? + BEQ __tx_thread_not_nested_save @ Yes, not a nested context save +@ +@ /* Nested interrupt condition. */ +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3, #0] @ Store it back in the variable +@ +@ /* Note: Minimal context of interrupted thread is already saved. */ +@ +@ /* Return to the ISR. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {r12, lr} @ Save ISR lr & r12 + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {r12, lr} @ Recover ISR lr & r12 +#endif + +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@ +__tx_thread_not_nested_save: +@ } +@ +@ /* Otherwise, not nested, check to see if a thread was running. */ +@ else if (_tx_thread_current_ptr[core]) +@ { +@ + ADD r2, r2, #1 @ Increment the interrupt counter + STR r2, [r3, #0] @ Store it back in the variable + LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr + ADD r1, r1, r12 @ Build index into current thread ptr + LDR r0, [r1, #0] @ Pickup current thread pointer + CMP r0, #0 @ Is it NULL? + BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in + @ scheduling loop - nothing needs saving! +@ +@ /* Note: Minimal context of interrupted thread is already saved. */ +@ +@ /* Save the current stack pointer in the thread's control block. */ +@ _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; +@ +@ /* Switch to the system stack. */ +@ sp = _tx_thread_system_stack_ptr[core]; +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {r12, lr} @ Save ISR lr & r12 + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {r12, lr} @ Recover ISR lr & r12 +#endif + +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@ +@ } +@ else +@ { +@ +__tx_thread_idle_system_save: +@ +@ /* Interrupt occurred in the scheduling loop. */ +@ +@ /* Not much to do here, just adjust the stack pointer, and return to IRQ +@ processing. */ +@ + MOV r10, #0 @ Clear stack limit + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +@ +@ /* Call the ISR enter function to indicate an ISR is executing. */ +@ + PUSH {r12, lr} @ Save ISR lr & r12 + BL _tx_execution_isr_enter @ Call the ISR enter function + POP {r12, lr} @ Recover ISR lr & r12 +#endif + + ADD sp, sp, #32 @ Recover saved registers +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@ +@ } +@} +@ + + diff --git a/ports_smp/cortex_a7_smp/gnu/src/tx_timer_interrupt.S b/ports_smp/cortex_a7_smp/gnu/src/tx_timer_interrupt.S new file mode 100644 index 00000000..e88f4371 --- /dev/null +++ b/ports_smp/cortex_a7_smp/gnu/src/tx_timer_interrupt.S @@ -0,0 +1,231 @@ +@/**************************************************************************/ +@/* */ +@/* Copyright (c) Microsoft Corporation. All rights reserved. */ +@/* */ +@/* This software is licensed under the Microsoft Software License */ +@/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +@/* and in the root directory of this software. */ +@/* */ +@/**************************************************************************/ +@ +@ +@/**************************************************************************/ +@/**************************************************************************/ +@/** */ +@/** ThreadX Component */ +@/** */ +@/** Timer */ +@/** */ +@/**************************************************************************/ +@/**************************************************************************/ +@ +@#define TX_SOURCE_CODE +@ +@ +@/* Include necessary system files. */ +@ +@#include "tx_api.h" +@#include "tx_timer.h" +@#include "tx_thread.h" +@ +@ +@Define Assembly language external references... +@ + .global _tx_timer_time_slice + .global _tx_timer_system_clock + .global _tx_timer_current_ptr + .global _tx_timer_list_start + .global _tx_timer_list_end + .global _tx_timer_expired_time_slice + .global _tx_timer_expired + .global _tx_thread_time_slice + .global _tx_timer_expiration_process + .global _tx_timer_interrupt_active + .global _tx_thread_smp_protect + .global _tx_thread_smp_unprotect + .global _tx_trace_isr_enter_insert + .global _tx_trace_isr_exit_insert +@ +@ + .arm + .text + .align 2 +@/**************************************************************************/ +@/* */ +@/* FUNCTION RELEASE */ +@/* */ +@/* _tx_timer_interrupt SMP/Cortex-A7/GNU */ +@/* 6.0.1 */ +@/* AUTHOR */ +@/* */ +@/* William E. Lamie, Microsoft Corporation */ +@/* */ +@/* DESCRIPTION */ +@/* */ +@/* This function processes the hardware timer interrupt. This */ +@/* processing includes incrementing the system clock and checking for */ +@/* time slice and/or timer expiration. If either is found, the */ +@/* interrupt context save/restore functions are called along with the */ +@/* expiration functions. */ +@/* */ +@/* INPUT */ +@/* */ +@/* None */ +@/* */ +@/* OUTPUT */ +@/* */ +@/* None */ +@/* */ +@/* CALLS */ +@/* */ +@/* _tx_thread_time_slice Time slice interrupted thread */ +@/* _tx_thread_smp_protect Get SMP protection */ +@/* _tx_thread_smp_unprotect Releast SMP protection */ +@/* _tx_timer_expiration_process Timer expiration processing */ +@/* */ +@/* CALLED BY */ +@/* */ +@/* interrupt vector */ +@/* */ +@/* RELEASE HISTORY */ +@/* */ +@/* DATE NAME DESCRIPTION */ +@/* */ +@/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +@/* */ +@/**************************************************************************/ +@VOID _tx_timer_interrupt(VOID) +@{ + .global _tx_timer_interrupt + .type _tx_timer_interrupt,function +_tx_timer_interrupt: +@ +@ /* Upon entry to this routine, it is assumed that context save has already +@ been called, and therefore the compiler scratch registers are available +@ for use. */ +@ + MRC p15, 0, r0, c0, c0, 5 @ Read CPU ID register + AND r0, r0, #0x03 @ Mask off, leaving the CPU ID field + CMP r0, #0 @ Only process timer interrupts from core 0 (to change this simply change the constant!) + BEQ __tx_process_timer @ If the same process the interrupt + BX lr @ Return to caller if not matched +__tx_process_timer: + + STMDB sp!, {r4, lr} @ Save the lr and r4 register on the stack + BL _tx_thread_smp_protect @ Get protection + MOV r4, r0 @ Save the return value in preserved register + + LDR r1, =_tx_timer_interrupt_active @ Pickup address of timer interrupt active count + LDR r0, [r1, #0] @ Pickup interrupt active count + ADD r0, r0, #1 @ Increment interrupt active count + STR r0, [r1, #0] @ Store new interrupt active count + DMB @ Ensure that accesses to shared resource have completed +@ +@ /* Increment the system clock. */ +@ _tx_timer_system_clock++; +@ + LDR r1, =_tx_timer_system_clock @ Pickup address of system clock + LDR r0, [r1, #0] @ Pickup system clock + ADD r0, r0, #1 @ Increment system clock + STR r0, [r1, #0] @ Store new system clock +@ +@ /* Test for timer expiration. */ +@ if (*_tx_timer_current_ptr) +@ { +@ + LDR r1, =_tx_timer_expired @ Pickup addr of expired flag + LDR r0, [r1, #0] @ Pickup timer expired flag + CMP r0, #0 @ Check for previous timer expiration still active + BNE __tx_timer_done @ If so, skip timer processing + LDR r1, =_tx_timer_current_ptr @ Pickup current timer pointer addr + LDR r0, [r1, #0] @ Pickup current timer + LDR r2, [r0, #0] @ Pickup timer list entry + CMP r2, #0 @ Is there anything in the list? + BEQ __tx_timer_no_timer @ No, just increment the timer +@ +@ /* Set expiration flag. */ +@ _tx_timer_expired = TX_TRUE; +@ + LDR r3, =_tx_timer_expired @ Pickup expiration flag address + MOV r2, #1 @ Build expired value + STR r2, [r3, #0] @ Set expired flag + B __tx_timer_done @ Finished timer processing +@ +@ } +@ else +@ { +__tx_timer_no_timer: +@ +@ /* No timer expired, increment the timer pointer. */ +@ _tx_timer_current_ptr++; +@ + ADD r0, r0, #4 @ Move to next timer +@ +@ /* Check for wrap-around. */ +@ if (_tx_timer_current_ptr == _tx_timer_list_end) +@ + LDR r3, =_tx_timer_list_end @ Pickup addr of timer list end + LDR r2, [r3, #0] @ Pickup list end + CMP r0, r2 @ Are we at list end? + BNE __tx_timer_skip_wrap @ No, skip wrap-around logic +@ +@ /* Wrap to beginning of list. */ +@ _tx_timer_current_ptr = _tx_timer_list_start; +@ + LDR r3, =_tx_timer_list_start @ Pickup addr of timer list start + LDR r0, [r3, #0] @ Set current pointer to list start +@ +__tx_timer_skip_wrap: +@ + STR r0, [r1, #0] @ Store new current timer pointer +@ } +@ +__tx_timer_done: +@ +@ +@ /* Did a timer expire? */ +@ if (_tx_timer_expired) +@ { +@ + LDR r1, =_tx_timer_expired @ Pickup addr of expired flag + LDR r0, [r1, #0] @ Pickup timer expired flag + CMP r0, #0 @ Check for timer expiration + BEQ __tx_timer_dont_activate @ If not set, skip timer activation +@ +@ /* Process timer expiration. */ +@ _tx_timer_expiration_process(); +@ + BL _tx_timer_expiration_process @ Call the timer expiration handling routine +@ +@ } +__tx_timer_dont_activate: +@ +@ /* Call time-slice processing. */ +@ _tx_thread_time_slice(); + + BL _tx_thread_time_slice @ Call time-slice processing +@ +@ } +@ + LDR r1, =_tx_timer_interrupt_active @ Pickup address of timer interrupt active count + LDR r0, [r1, #0] @ Pickup interrupt active count + SUB r0, r0, #1 @ Decrement interrupt active count + STR r0, [r1, #0] @ Store new interrupt active count + DMB @ Ensure that accesses to shared resource have completed +@ +@ /* Release protection. */ +@ + MOV r0, r4 @ Pass the previous status register back + BL _tx_thread_smp_unprotect @ Release protection + + LDMIA sp!, {r4, lr} @ Recover lr register and r4 +#ifdef __THUMB_INTERWORK + BX lr @ Return to caller +#else + MOV pc, lr @ Return to caller +#endif +@ +@} + + diff --git a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/.cproject b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/.cproject new file mode 100644 index 00000000..fd28e95f --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/.cproject @@ -0,0 +1,111 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/.project b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/.project new file mode 100644 index 00000000..ed4c0885 --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/.project @@ -0,0 +1,27 @@ + + + sample_threadx + + + tx + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/.settings/language.settings.xml b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/.settings/language.settings.xml new file mode 100644 index 00000000..6fe4887c --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/.settings/language.settings.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/Cortex-A9x4_tx.launch b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/Cortex-A9x4_tx.launch new file mode 100644 index 00000000..7319cd33 --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/Cortex-A9x4_tx.launch @@ -0,0 +1,184 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_GIC.h b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_GIC.h new file mode 100644 index 00000000..3c92c541 --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_GIC.h @@ -0,0 +1,80 @@ +// ------------------------------------------------------------ +// Cortex-A MPCore - Interrupt Controller functions +// Header File +// +// Copyright ARM Ltd 2009. All rights reserved. +// ------------------------------------------------------------ + +#ifndef _CORTEXA_GIC_ +#define _CORTEXA_GIC_ + +// ------------------------------------------------------------ +// GIC +// ------------------------------------------------------------ + +// Typical calls to enable interrupt ID X: +// enable_irq_id(X) <-- Enable that ID +// set_irq_priority(X, 0) <-- Set the priority of X to 0 (the max priority) +// set_priority_mask(0x1F) <-- Set Core's priority mask to 0x1F (the lowest priority) +// enable_GIC() <-- Enable the GIC (global) +// enable_gic_processor_interface() <-- Enable the CPU interface (local to the core) +// +// OR +// +// Use init_GIC() which is a simple switch everything on function! :-) +// + +// Global enable of the Interrupt Distributor +void enable_GIC(void); + +// Global disable of the Interrupt Distributor +void disable_GIC(void); + +// Enables the interrupt source number ID +void enable_irq_id(unsigned int ID); + +// Disables the interrupt source number ID +void disable_irq_id(unsigned int ID); + +// Sets the priority of the specifed ID +void set_irq_priority(unsigned int ID, unsigned int priority); + +// Enables the processor interface +// Must been done one each core seperately +void enable_gic_processor_interface(void); + +// Disables the processor interface +void disable_gic_processor_interface(void); + +// Sets the Priority mask register for the core run on +// The reset value masks ALL interrupts! +void set_priority_mask(unsigned int priority); + +// Sets the Binary Point Register for the core run on +void set_binary_port(unsigned int priority); + +// Returns the value of the Interrupt Acknowledge Register +unsigned int read_irq_ack(void); + +// Writes ID to the End Of Interrupt register +void write_end_of_irq(unsigned int ID); + +// Lazy Init function, a quick way of enabling interrupts +// * Enables the GIC (global) and CPU Interface (just for this core) +// * Enables interrupt sources 0->31, and sets their priority to 0x0 +// * Sets the CPU's Priority mask to 0x1F +// * Clears the CPSR I bit +void init_GIC(void); + +// ------------------------------------------------------------ +// SGI +// ------------------------------------------------------------ + +// Send a software generate interrupt +void send_sgi(unsigned int ID, unsigned int core_list, unsigned int filter_list); + +#endif + +// ------------------------------------------------------------ +// End of MP_GIC.h +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_GIC.s b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_GIC.s new file mode 100644 index 00000000..dc5ec273 --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_GIC.s @@ -0,0 +1,292 @@ +; ------------------------------------------------------------ +; Cortex-A MPCore - Interrupt Controller functions +; +; Copyright ARM Ltd 2009. All rights reserved. +; ------------------------------------------------------------ + + PRESERVE8 + + AREA MP_GIC, CODE, READONLY + +; ------------------------------------------------------------ +; GIC +; ------------------------------------------------------------ + + ; CPU Interface offset from base of private peripheral space --> 0x0100 + ; Interrupt Distributor offset from base of private peripheral space --> 0x1000 + + ; Typical calls to enable interrupt ID X: + ; enable_irq_id(X) <-- Enable that ID + ; set_irq_priority(X, 0) <-- Set the priority of X to 0 (the max priority) + ; set_priority_mask(0x1F) <-- Set CPU's priority mask to 0x1F (the lowest priority) + ; enable_GIC() <-- Enable the GIC (global) + ; enable_gic_processor_interface() <-- Enable the CPU interface (local to the CPU) + + + EXPORT enable_GIC + ; void enable_GIC(void) + ; Global enable of the Interrupt Distributor +enable_GIC PROC + + ; Get base address of private perpherial space + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + ADD r0, r0, #0x1000 ; Add the GIC offset + + LDR r1, [r0] ; Read the GIC's Enable Register (ICDDCR) + ORR r1, r1, #0x01 ; Set bit 0, the enable bit + STR r1, [r0] ; Write the GIC's Enable Register (ICDDCR) + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT disable_GIC + ; void disable_GIC(void) + ; Global disable of the Interrupt Distributor +disable_GIC PROC + + ; Get base address of private perpherial space + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + ADD r0, r0, #0x1000 ; Add the GIC offset + + LDR r1, [r0] ; Read the GIC's Enable Register (ICDDCR) + BIC r1, r1, #0x01 ; Set bit 0, the enable bit + STR r1, [r0] ; Write the GIC's Enable Register (ICDDCR) + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT enable_irq_id + ; void enable_irq_id(unsigned int ID) + ; Enables the interrupt source number ID +enable_irq_id PROC + + ; Get base address of private perpherial space + MOV r1, r0 ; Back up passed in ID value + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + ; Each interrupt source has an enable bit in the GIC. These + ; are grouped into registers, with 32 sources per register + ; First, we need to identify which 32 bit block the interrupt lives in + MOV r2, r1 ; Make working copy of ID in r2 + MOV r2, r2, LSR #5 ; LSR by 5 places, affective divide by 32 + ; r2 now contains the 32 bit block this ID lives in + MOV r2, r2, LSL #2 ; Now multiply by 4, to covert offset into an address offset (four bytes per reg) + + ; Now work out which bit within the 32 bit block the ID is + AND r1, r1, #0x1F ; Mask off to give offset within 32bit block + MOV r3, #1 ; Move enable value into r3 + MOV r3, r3, LSL r1 ; Shift it left to position of ID + + ADD r2, r2, #0x1100 ; Add the base offset of the Enable Set registers to the offset for the ID + STR r3, [r0, r2] ; Store out (ICDISER) + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT disable_irq_id + ; void disable_irq_id(unsigned int ID) + ; Disables the interrupt source number ID +disable_irq_id PROC + + ; Get base address of private perpherial space + MOV r1, r0 ; Back up passed in ID value + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + ; First, we need to identify which 32 bit block the interrupt lives in + MOV r2, r1 ; Make working copy of ID in r2 + MOV r2, r2, LSR #5 ; LSR by 5 places, affective divide by 32 + ; r2 now contains the 32 bit block this ID lives in + MOV r2, r2, LSL #2 ; Now multiply by 4, to covert offset into an address offset (four bytes per reg) + + ; Now work out which bit within the 32 bit block the ID is + AND r1, r1, #0x1F ; Mask off to give offset within 32bit block + MOV r3, #1 ; Move enable value into r3 + MOV r3, r3, LSL r1 ; Shift it left to position of ID in 32 bit block + + ADD r2, r2, #0x1180 ; Add the base offset of the Enable Clear registers to the offset for the ID + STR r3, [r0, r2] ; Store out (ICDICER) + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT set_irq_priority + ; void set_irq_priority(unsigned int ID, unsigned int priority) + ; Sets the priority of the specifed ID + ; r0 = ID + ; r1 = priority +set_irq_priority PROC + + ; Get base address of private perpherial space + MOV r2, r0 ; Back up passed in ID value + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + ; r0 = base addr + ; r1 = priority + ; r2 = ID + + ; Make sure that priority value is only 5 bits, and convert to expected format + AND r1, r1, #0x1F + MOV r1, r1, LSL #3 + + ; Find which priority register this ID lives in + BIC r3, r2, #0x03 ; Make a copy of the ID, clearing off the bottom two bits + ; There are four IDs per reg, by clearing the bottom two bits we get an address offset + ADD r3, r3, #0x1400 ; Now add the offset of the Priority Level registers from the base of the private peripheral space + ADD r0, r0, r3 ; Now add in the base address of the private peripheral space, giving us the absolute address + + + ; Now work out which ID in the register it is + AND r2, r2, #0x03 ; Clear all but the bottom four bits, leaves which ID in the reg it is (which byte) + MOV r2, r2, LSL #3 ; Multiply by 8, this gives a bit offset + + ; Read -> Modify -> Write + MOV r12, #0xFF ; Mask (8 bits) + MOV r12, r12, LSL r2 ; Move mask into correct bit position + MOV r1, r1, LSL r2 ; Also, move passed in priority value into correct bit position + + LDR r3, [r0] ; Read current value of the Priority Level register (ICDIPR) + BIC r3, r3, r12 ; Clear appropiate field + ORR r3, r3, r1 ; Now OR in the priority value + STR r3, [r0] ; And store it back again (ICDIPR) + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT enable_gic_processor_interface + ; void enable_gic_processor_interface(void) + ; Enables the processor interface + ; Must been done one each CPU seperately +enable_gic_processor_interface PROC + + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + LDR r1, [r0, #0x100] ; Read the Processor Interface Control register (ICCICR/ICPICR) + ORR r1, r1, #0x03 ; Bit 0: Enables secure interrupts, Bit 1: Enables Non-Secure interrupts + STR r1, [r0, #0x100] ; Write the Processor Interface Control register (ICCICR/ICPICR) + + BX lr + ENDP + + +; ------------------------------------------------------------ + + EXPORT disable_gic_processor_interface + ; void disable_gic_processor_interface(void) + ; Disables the processor interface + ; Must been done one each CPU seperately +disable_gic_processor_interface PROC + + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + LDR r1, [r0, #0x100] ; Read the Processor Interface Control register (ICCICR/ICPICR) + BIC r1, r1, #0x03 ; Bit 0: Enables secure interrupts, Bit 1: Enables Non-Secure interrupts + STR r1, [r0, #0x100] ; Write the Processor Interface Control register (ICCICR/ICPICR) + + BX lr + ENDP + + +; ------------------------------------------------------------ + + EXPORT set_priority_mask + ; void set_priority_mask(unsigned int priority) + ; Sets the Priority mask register for the CPU run on + ; The reset value masks ALL interrupts! +set_priority_mask PROC + + ; Get base address of private perpherial space + MOV r1, r0 ; Back up passed in ID value + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + STR r1, [r0, #0x0104] ; Write the Priority Mask register (ICCPMR/ICCIPMR) + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT set_binary_port + ; void set_binary_port(unsigned int priority) + ; Sets the Binary Point Register for the CPU run on +set_binary_port PROC + + ; Get base address of private perpherial space + MOV r1, r0 ; Back up passed in ID value + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + STR r1, [r0, #0x0108] ; Write the Binary register (ICCBPR/ICCBPR) + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT read_irq_ack + ; unsigned int read_irq_ack(void) + ; Returns the value of the Interrupt Acknowledge Register +read_irq_ack PROC + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + LDR r0, [r0, #0x010C] ; Read the Interrupt Acknowledge Register (ICCIAR) + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT write_end_of_irq + ; void write_end_of_irq(unsigned int ID) + ; Writes ID to the End Of Interrupt register +write_end_of_irq PROC + + ; Get base address of private perpherial space + MOV r1, r0 ; Back up passed in ID value + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + STR r1, [r0, #0x0110] ; Write ID to the End of Interrupt register (ICCEOIR) + + BX lr + ENDP + +; ------------------------------------------------------------ +; SGI +; ------------------------------------------------------------ + + EXPORT send_sgi + ; void send_sgi(unsigned int ID, unsigned int target_list, unsigned int filter_list); + ; Send a software generate interrupt +send_sgi PROC + + AND r3, r0, #0x0F ; Mask off unused bits of ID, and move to r3 + AND r1, r1, #0x0F ; Mask off unused bits of target_filter + AND r2, r2, #0x0F ; Mask off unused bits of filter_list + + ORR r3, r3, r1, LSL #16 ; Combine ID and target_filter + ORR r3, r3, r2, LSL #24 ; and now the filter list + + ; Get the address of the GIC + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + ADD r0, r0, #0x1F00 ; Add offset of the sgi_trigger reg + + STR r3, [r0] ; Write to the Software Generated Interrupt Register (ICDSGIR) + + BX lr + ENDP + +; ------------------------------------------------------------ +; End of code +; ------------------------------------------------------------ + + END + +; ------------------------------------------------------------ +; End of MP_GIC.s +; ------------------------------------------------------------ diff --git a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_GlobalTimer.h b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_GlobalTimer.h new file mode 100644 index 00000000..27a02dc7 --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_GlobalTimer.h @@ -0,0 +1,42 @@ +// ------------------------------------------------------------ +// Cortex-A MPCore - Global timer functions +// Header Filer +// +// Copyright ARM Ltd 2009. All rights reserved. +// ------------------------------------------------------------ + +#ifndef _CORTEXA_GLOBAL_TIMER_ +#define _CORTEXA_GLOBAL_TIMER_ + +// Typical set of calls to enable Timer: +// init_global_timer( AUTO_INCREMENT>, INCREMENT_VALUE ); +// set_global_timer_comparator( UPPER_32_BITS, LOWER_32_BITS ); +// start_global_timer(); + + +// Sets up the private timer +// r0: IF 0 (AutoIncrement) ELSE (SingleShot) +// r1: Increment value (ignored if auto_increment != 0) +void init_global_timer(unsigned int auto_increment, unsigned int increment_value) + +// Sets the comparator value for this CPU +void set_global_timer_comparator(unsigned int top, unsigned int bottom); + +// Starts the private timer +void start_global_timer(void); + +// Stops the private timer +void stop_global_timer(void); + +// Reads the current value of the timer count register +// Returns bits 63:32 in *top, and bits 31:0 in *bottom +void read_global_timer(unsigned int* top, unsigned int* bottom); + +// Clears the private timer interrupt +void clear_global_timer_irq(void); + +#endif + +// ------------------------------------------------------------ +// End of MP_PrivateTimer.h +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_GlobalTimer.s b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_GlobalTimer.s new file mode 100644 index 00000000..0e9bb3df --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_GlobalTimer.s @@ -0,0 +1,168 @@ +; ------------------------------------------------------------ +; Cortex-A MPCore - Global timer functions +; +; Copyright ARM Ltd 2009. All rights reserved. +; ------------------------------------------------------------ + + PRESERVE8 + + AREA MP_PrivateTimer, CODE, READONLY + + ; PPI ID 27 + + + ; Typical set of calls to enable Timer: + ; init_global_timer() + ; set_global_timer_comparator() + ; start_global_timer() + +; ------------------------------------------------------------ + + EXPORT init_global_timer + ; void init_global_timer(unsigned int auto_increment, unsigned int increment_value) + ; Initializes the Global Timer, but does NOT set the enable bit + ; r0: IF 0 (AutoIncrement) ELSE (SingleShot) + ; r1: increment value +init_global_timer PROC + + ; Get base address of private perpherial space + MRC p15, 4, r2, c15, c0, 0 ; Read periph base address + + ; Control register bit layout + ; Bit 0 - Timer enable + ; Bit 1 - Comp enable + ; Bit 2 - IRQ enable + ; Bit 3 - Auto-increment enable + + ; Ensure the timer is disabled + LDR r3, [r2, #0x208] ; Read control reg + BIC r3, r3, #0x01 ; Clear enable bit + STR r3, [r2, #0x208] ; Write control reg + + ; Form control reg value + CMP r0, #0 ; Check whether to enable auto-reload + MOVNE r0, #0x00 ; No auto-reload + MOVEQ r0, #0x04 ; With auto-reload + STR r0, [r2, #0x208] ; Store to control register + + ; Store increment value + STREQ r1, [r2, #0x218] + + ; Clear timer value + MOV r0, #0x0 + STR r0, [r2, #0x0] + STR r0, [r2, #0x4] + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT set_global_timer_comparator + ; void set_global_timer_comparator(unsigned int top, unsigned int bottom); + ; Writes the comparator registers, and enable the comparator bit in the control register + ; r0: 63:32 of the comparator value + ; r1: 31:0 of the comparator value +set_global_timer_comparator PROC + + MRC p15, 4, r2, c15, c0, 0 ; Read periph base address + + ; Disable comparator before updating register + LDR r1, [r2, #0x208] ; Read control reg + BIC r3, r3, #0x02 ; Clear comparator enable bit + STR r3, [r2, #0x208] ; Write modified value back + + ; Write the comparator registers + STR r1, [r2, #0x210] ; Write lower 32 bits + STR r0, [r2, #0x214] ; Write upper 32 bits + DMB + + ; Re-enable the comparator + ORR r3, r3, #0x02 ; Set comparator enable bit + STR r3, [r2, #0x208] ; Write modified value back + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT start_global_timer + ; void start_global_timer(void) + ; Starts the global timer +start_global_timer PROC + + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + LDR r1, [r0, #0x208] ; Read control reg + ORR r1, r1, #0x01 ; Set enable bit + STR r1, [r0, #0x208] ; Write modified value back + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT stop_global_timer + ; void stop_private_timer(void) + ; Stops the private timer +stop_global_timer PROC + + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + LDR r1, [r0, #0x208] ; Read control reg + BIC r1, r1, #0x01 ; Clear enable bit + STR r1, [r0, #0x208] ; Write modified value back + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT get_global_timer_count + ; void read_global_timer(unsigned int* top, unsigned int* bottom) + ; Reads the current value of the timer count register + ; r0: Address of unsigned int for bits 63:32 + ; r1: Address of unsigned int for bits 31:0 +get_global_timer_count PROC + +get_global_timer_count_loop + MRC p15, 4, r2, c15, c0, 0 ; Read periph base address + + LDR r12,[r2, #0x04] ; Read bits 63:32 + LDR r3, [r2, #0x00] ; Read bits 31:0 + LDR r2, [r2, #0x04] ; Re-read bits 63:32 + + CMP r2, r12 ; Have the top bits changed? + BNE get_global_timer_count_loop + + ; Store result out to pointers + STR r2, [r0] + STR r3, [r1] + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT clear_global_timer_irq + ; void clear_global_timer_irq(void) + ; Clears the global timer interrupt +clear_global_timer_irq PROC + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + ; Clear the interrupt by writing 0x1 to the Timer's Interrupt Status register + MOV r1, #1 + STR r1, [r0, #0x20C] + + BX lr + ENDP + +; ------------------------------------------------------------ +; End of code +; ------------------------------------------------------------ + + END + +; ------------------------------------------------------------ +; End of MP_GlobalTimer.s +; ------------------------------------------------------------ diff --git a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_Mutexes.h b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_Mutexes.h new file mode 100644 index 00000000..0317ddf0 --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_Mutexes.h @@ -0,0 +1,42 @@ +// ------------------------------------------------------------ +// Cortex-A MPCore - Mutex +// Header File +// +// Copyright ARM Ltd 2009. All rights reserved. +// ------------------------------------------------------------ + +#ifndef _CORTEXA_MUTEX_ +#define _CORTEXA_MUTEX_ + +// Struct +// 0xFF=unlocked 0x0 = Locked by CPU 0, +// 0x1 = Locked by CPU 1, +// 0x2 = Locked by CPU 2, +// 0x3 = Locked by CPU 3 +typedef struct +{ + unsigned int lock; +}mutex_t; + +// Places mutex into a known state +// r0 = address of mutex_t +void init_mutex(mutex_t* pMutex); + +// Blocking call, returns once successfully locked a mutex +// r0 = address of mutex_t +void lock_mutex(mutex_t* pMutex); + +// Releases (unlock) mutex. Fails if CPU not owner of mutex. +// returns 0x0 for success, and 0x1 for failure +// r0 = address of mutex_t +unsigned int unlock_mutex(mutex_t* pMutex); + +// Returns 0x0 if mutex unlocked, 0x1 is locked +// r0 = address of mutex_t +void is_mutex_locked(mutex_t* pMutex); + +#endif + +// ------------------------------------------------------------ +// End of MP_Mutexes.h +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_Mutexes.s b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_Mutexes.s new file mode 100644 index 00000000..3774d8b9 --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_Mutexes.s @@ -0,0 +1,123 @@ +; ------------------------------------------------------------ +; Cortex-A MPCore - Mutex Code +; +; Copyright ARM Ltd 2009. All rights reserved. +; ------------------------------------------------------------ + + PRESERVE8 + + AREA MP_Mutexes, CODE, READONLY + + ;NOTES + ; struct mutex_t defined in A9MP_Mutexes.h + ; typedef struct mutex_t + ; { + ; unsigned int lock; <-- offset 0 + ; } + ; + ; lock: 0xFF=unlocked 0x0 = Locked by CPU 0, 0x1 = Locked by CPU 1, 0x2 = Locked by CPU 2, 0x3 = Locked by CPU 3 + ; + +UNLOCKED EQU 0xFF + +; ------------------------------------------------------------ + + EXPORT init_mutex + ; void init_mutex(mutex_t* pMutex) + ; Places mutex into a known state + ; r0 = address of mutex_t +init_mutex PROC + + MOV r1, #UNLOCKED ; Mark as unlocked + STR r1, [r0] + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT lock_mutex + ; void lock_mutex(mutex_t* pMutex) + ; Blocking call, returns once successfully locked a mutex + ; r0 = address of mutex_t +lock_mutex PROC + + ; Is mutex locked? + ; ----------------- + LDREX r1, [r0] ; Read lock field + CMP r1, #UNLOCKED ; Compare with "unlocked" + + WFENE ; If mutex is locked, go into standby + BNE lock_mutex ; On waking re-check the mutex + + ; Attempt to lock mutex + ; ----------------------- + MRC p15, 0, r1, c0, c0, 5 ; Read CPU ID register + AND r1, r1, #0x03 ; Mask off, leaving the CPU ID field. + STREX r2, r1, [r0] ; Attempt to lock mutex, by write CPU's ID to lock field + CMP r2, #0x0 ; Check wether store completed successfully (0=succeeded) + BNE lock_mutex ; If store failed, go back to beginning and try again + + DMB + + BX lr ; Return as mutex is now locked by this cpu + ENDP + +; ------------------------------------------------------------ + + EXPORT unlock_mutex + ; unsigned int unlock_mutex(mutex_t* pMutex) + ; Releases mutex, returns 0x0 for success and 0x1 for failure + ; r0 = address of mutex_t +unlock_mutex PROC + + ; Does this CPU own the mutex? + ; ----------------------------- + MRC p15, 0, r1, c0, c0, 5 ; Read CPU ID register + AND r1, r1, #0x03 ; Mask off, leaving the CPU ID in r1 + LDR r2, [r0] ; Read the lock field of the mutex + CMP r1, r2 ; Compare ID of this CPU with the lock owner + MOVNE r0, #0x1 ; If ID doesn't match, return "fail" + BXNE lr + + + ; Unlock mutex + ; ------------- + DMB ; Ensure that accesses to shared resource have completed + + MOV r1, #UNLOCKED ; Write "unlocked" into lock field + STR r1, [r0] + + DMB ; To ensure update of the mutex occurs before other CPUs awake + + SEV ; Send event to other CPUs, wakes anyone waiting on a mutex (using WFE) + + MOV r0, #0x0 ; Return "success" + BX lr + + ENDP + +; ------------------------------------------------------------ + + EXPORT is_mutex_locked + ; void is_mutex_locked(mutex_t* pMutex) + ; Returns 0x0 if mutex unlocked, 0x1 is locked + ; r0 = address of mutex_t +is_mutex_locked PROC + LDR r0, [r0] + CMP r0, #UNLOCKED + MOVEQ r0, #0x0 + MOVNE r0, #0x1 + BX lr + ENDP + + +; ------------------------------------------------------------ +; End of code +; ------------------------------------------------------------ + + END + +; ------------------------------------------------------------ +; End of MP_Mutexes.s +; ------------------------------------------------------------ diff --git a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_PrivateTimer.h b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_PrivateTimer.h new file mode 100644 index 00000000..b0ab212a --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_PrivateTimer.h @@ -0,0 +1,36 @@ +// ------------------------------------------------------------ +// Cortex-A MPCore - Private timer functions +// Header Filer +// +// Copyright ARM Ltd 2009. All rights reserved. +// ------------------------------------------------------------ + +#ifndef _CORTEXA_PRIVATE_TIMER_ +#define _CORTEXA_PRIVATE_TIMER_ + +// Typical set of calls to enable Timer: +// init_private_timer(0xXXXX, 0) <-- Counter down value of 0xXXXX, with auto-reload +// start_private_timer() + +// Sets up the private timer +// r0: initial load value +// r1: IF 0 (AutoReload) ELSE (SingleShot) +void init_private_timer(unsigned int load_value, unsigned int auto_reload); + +// Starts the private timer +void start_private_timer(void); + +// Stops the private timer +void stop_private_timer(void); + +// Reads the current value of the timer count register +unsigned int get_private_timer_count(void); + +// Clears the private timer interrupt +void clear_private_timer_irq(void); + +#endif + +// ------------------------------------------------------------ +// End of MP_PrivateTimer.h +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_PrivateTimer.s b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_PrivateTimer.s new file mode 100644 index 00000000..f8a1eefa --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_PrivateTimer.s @@ -0,0 +1,121 @@ +; ------------------------------------------------------------ +; Cortex-A MPCore - Private timer functions +; +; Copyright ARM Ltd 2009. All rights reserved. +; ------------------------------------------------------------ + + PRESERVE8 + + AREA MP_PrivateTimer, CODE, READONLY + + ; PPI ID 29 + + + ; Typical set of calls to enable Timer: + ; init_private_timer(0xXXXX, 0) <-- Counter down value of 0xXXXX, with auto-reload + ; start_private_timer() + + ; Timer offset from base of private peripheral space --> 0x600 + +; ------------------------------------------------------------ + + EXPORT init_private_timer + ; void init_private_timer(unsigned int load_value, unsigned int auto_reload) + ; Sets up the private timer + ; r0: initial load value + ; r1: IF 0 (AutoReload) ELSE (SingleShot) +init_private_timer PROC + + ; Get base address of private perpherial space + MOV r2, r0 ; Make a copy of r0 before corrupting + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + ; Set the load value + STR r2, [r0, #0x600] + + ; Control register bit layout + ; Bit 0 - Enable + ; Bit 1 - Auto-Reload ; see DE681117 + ; Bit 2 - IRQ Generation + + ; Form control reg value + CMP r1, #0 ; Check whether to enable auto-reload + MOVNE r2, #0x04 ; No auto-reload + MOVEQ r2, #0x06 ; With auto-reload + + ; Store to control register + STR r2, [r0, #0x608] + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT start_private_timer + ; void start_private_timer(void) + ; Starts the private timer +start_private_timer PROC + + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + LDR r1, [r0, #0x608] ; Read control reg + ORR r1, r1, #0x01 ; Set enable bit + STR r1, [r0, #0x608] ; Write modified value back + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT stop_private_timer + ; void stop_private_timer(void) + ; Stops the private timer +stop_private_timer PROC + + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + LDR r1, [r0, #0x608] ; Read control reg + BIC r1, r1, #0x01 ; Clear enable bit + STR r1, [r0, #0x608] ; Write modified value back + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT get_private_timer_count + ; unsigned int read_private_timer(void) + ; Reads the current value of the timer count register +get_private_timer_count PROC + + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + LDR r0, [r0, #0x604] ; Read count register + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT clear_private_timer_irq + ; void clear_private_timer_irq(void) + ; Clears the private timer interrupt +clear_private_timer_irq PROC + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + ; Clear the interrupt by writing 0x1 to the Timer's Interrupt Status register + MOV r1, #1 + STR r1, [r0, #0x60C] + + BX lr + ENDP + +; ------------------------------------------------------------ +; End of code +; ------------------------------------------------------------ + + END + +; ------------------------------------------------------------ +; End of MP_PrivateTimer.s +; ------------------------------------------------------------ diff --git a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_SCU.h b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_SCU.h new file mode 100644 index 00000000..a99b89e8 --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_SCU.h @@ -0,0 +1,67 @@ +// ------------------------------------------------------------ +// Cortex-A MPCore - Snoop Control Unit +// Header File +// +// Copyright ARM Ltd 2009. All rights reserved. +// ------------------------------------------------------------ + +#ifndef _CORTEXA_SCU_ +#define _CORTEXA_SCU_ + +// ------------------------------------------------------------ +// SCU +// ------------------------------------------------------------ + +// Returns the base address of the private peripheral memory space +unsigned int get_base_addr(void); + +// Returns the CPU ID (0 to 3) of the CPU executed on +unsigned int get_cpu_id(void); + +// Returns the number of cores in the A9 Cluster +// NOTE: +// returns 0 = 1 core +// 1 = 2 cores etc... +// This is the format of the register, decided to leave it unchanged. +unsigned int get_num_cpus(void); + +// Go to sleep, never returns +void go_to_sleep(void); + +// ------------------------------------------------------------ +// SCU +// ------------------------------------------------------------ + +// Enables the SCU +void enable_scu(void); + +// Set this core as participating in SMP +void join_smp(void); + +// Set this core as NOT participating in SMP +void leave_smp(void); + +// The return value is 1 bit per core: +// bit 0 - CPU 0 +// bit 1 - CPU 1 +// etc... +unsigned int get_cpus_in_smp(void); + + //Enable the broadcasting of cache & TLB maintenance operations +// When enabled AND in SMP, broadcast all "inner sharable" +// cache and TLM maintenance operations to other SMP cores +void enable_maintenance_broadcast(void); + +// Disable the broadcasting of cache & TLB maintenance operations +void disable_maintenance_broadcast(void); + +// cpu: 0x0=CPU 0 0x1=CPU 1 etc... +// This function invalidates the SCU copy of the tag rams +// for the specified core. +void secure_SCU_invalidate(unsigned int cpu, unsigned int ways); + +#endif + +// ------------------------------------------------------------ +// End of MP_SCU.h +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_SCU.s b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_SCU.s new file mode 100644 index 00000000..572e2a87 --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/MP_SCU.s @@ -0,0 +1,193 @@ +; ------------------------------------------------------------ +; Cortex-A MPCore - SCU functions +; +; Copyright ARM Ltd 2009. All rights reserved. +; ------------------------------------------------------------ + + PRESERVE8 + + AREA MP_SCU, CODE, READONLY + +; ------------------------------------------------------------ +; Misc +; ------------------------------------------------------------ + + EXPORT get_base_addr + ; unsigned int get_base_addr(void) + ; Returns the base address of the private peripheral memory space +get_base_addr PROC + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address (see DE593076) + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT get_cpu_id + ; unsigned int get_cpu_id(void) + ; Returns the CPU ID (0 to 3) of the CPU executed on +get_cpu_id PROC + MRC p15, 0, r0, c0, c0, 5 ; Read CPU ID register + AND r0, r0, #0x03 ; Mask off, leaving the CPU ID field + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT get_num_cpus + ; unsigned int get_num_cpus(void) + ; Returns the number of CPUs in the A9 Cluster +get_num_cpus PROC + + ; Get base address of private perpherial space + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + LDR r0, [r0, #0x004] ; Read SCU Configuration register + AND r0, r0, #0x3 ; Bits 1:0 gives the number of cores + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT go_to_sleep + ; void go_to_sleep(void) +go_to_sleep PROC + WFI ; Go into standby + B go_to_sleep ; Catch in case of rogue events + BX lr + ENDP + +; ------------------------------------------------------------ +; SCU +; ------------------------------------------------------------ + + ; SCU offset from base of private peripheral space --> 0x000 + + EXPORT enable_scu + ; void enable_scu(void) + ; Enables the SCU +enable_scu PROC + + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + LDR r1, [r0, #0x0] ; Read the SCU Control Register + ORR r1, r1, #0x1 ; Set bit 0 (The Enable bit) + STR r1, [r0, #0x0] ; Write back modifed value + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT join_smp + ; void join_smp(void) + ; Set this CPU as participating in SMP +join_smp PROC + + ; SMP status is controlled by bit 6 of the CP15 Aux Ctrl Reg + + MRC p15, 0, r0, c1, c0, 1 ; Read ACTLR + ORR r0, r0, #0x040 ; Set bit 6 + MCR p15, 0, r0, c1, c0, 1 ; Write ACTLR + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT leave_smp + ; void leave_smp(void) + ; Set this CPU as NOT participating in SMP +leave_smp PROC + + ; SMP status is controlled by bit 6 of the CP15 Aux Ctrl Reg + + MRC p15, 0, r0, c1, c0, 1 ; Read ACTLR + BIC r0, r0, #0x040 ; Clear bit 6 + MCR p15, 0, r0, c1, c0, 1 ; Write ACTLR + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT get_cpus_in_smp + ; unsigned int get_cpus_in_smp(void) + ; The return value is 1 bit per core: + ; bit 0 - CPU 0 + ; bit 1 - CPU 1 + ; etc... +get_cpus_in_smp PROC + + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + + LDR r0, [r0, #0x004] ; Read SCU Configuration register + MOV r0, r0, LSR #4 ; Bits 7:4 gives the cores in SMP mode, shift then mask + AND r0, r0, #0x0F + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT enable_maintenance_broadcast + ; void enable_maintenance_broadcast(void) + ; Enable the broadcasting of cache & TLB maintenance operations + ; When enabled AND in SMP, broadcast all "inner sharable" + ; cache and TLM maintenance operations to other SMP cores +enable_maintenance_broadcast PROC + MRC p15, 0, r0, c1, c0, 1 ; Read Aux Ctrl register + ORR r0, r0, #0x01 ; Set the FW bit (bit 0) + MCR p15, 0, r0, c1, c0, 1 ; Write Aux Ctrl register + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT disable_maintenance_broadcast + ; void disable_maintenance_broadcast(void) + ; Disable the broadcasting of cache & TLB maintenance operations +disable_maintenance_broadcast PROC + MRC p15, 0, r0, c1, c0, 1 ; Read Aux Ctrl register + BIC r0, r0, #0x01 ; Clear the FW bit (bit 0) + MCR p15, 0, r0, c1, c0, 1 ; Write Aux Ctrl register + + BX lr + ENDP + +; ------------------------------------------------------------ + + EXPORT secure_SCU_invalidate + ; void secure_SCU_invalidate(unsigned int cpu, unsigned int ways) + ; cpu: 0x0=CPU 0 0x1=CPU 1 etc... + ; This function invalidates the SCU copy of the tag rams + ; for the specified core. Typically only done at start-up. + ; Possible flow: + ; - Invalidate L1 caches + ; - Invalidate SCU copy of TAG RAMs + ; - Join SMP +secure_SCU_invalidate PROC + AND r0, r0, #0x03 ; Mask off unused bits of CPU ID + MOV r0, r0, LSL #2 ; Convert into bit offset (four bits per core) + + AND r1, r1, #0x0F ; Mask off unused bits of ways + MOV r1, r1, LSL r0 ; Shift ways into the correct CPU field + + MRC p15, 4, r2, c15, c0, 0 ; Read periph base address + + STR r1, [r2, #0x0C] ; Write to SCU Invalidate All in Secure State + + BX lr + + ENDP + +; ------------------------------------------------------------ +; End of code +; ------------------------------------------------------------ + + END + +; ------------------------------------------------------------ +; End of MP_SCU.s +; ------------------------------------------------------------ diff --git a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/retarget.c b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/retarget.c new file mode 100644 index 00000000..9d3c2cdc --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/retarget.c @@ -0,0 +1,11 @@ +// Copyright ARM Ltd 2009. All rights reserved. + +extern void $Super$$main(void); +extern void enable_caches(void); + +void $Sub$$main(void) +{ + enable_caches(); // enables caches + $Super$$main(); // calls original main() +} + diff --git a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/sample_threadx.c b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/sample_threadx.c new file mode 100644 index 00000000..ce4d3126 --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/sample_threadx.c @@ -0,0 +1,381 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ + +#include "tx_api.h" + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_TIMER timer_0; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +#ifdef TX_ENABLE_EVENT_TRACE + +UCHAR event_buffer[65536]; + +#endif + + + +int main(void) +{ + + /* Enter ThreadX. */ + tx_kernel_enter(); + + return 0; +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer; + + +#ifdef TX_ENABLE_EVENT_TRACE + + tx_trace_enable(event_buffer, sizeof(event_buffer), 32); +#endif + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", first_unused_memory, DEMO_BYTE_POOL_SIZE); + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + diff --git a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/sample_threadx.scat b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/sample_threadx.scat new file mode 100644 index 00000000..f2a2d1bd --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/sample_threadx.scat @@ -0,0 +1,41 @@ + +;******************************************************* +; Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved. +; Use, modification and redistribution of this file is subject to your possession of a +; valid End User License Agreement for the Arm Product of which these examples are part of +; and your compliance with all applicable terms and conditions of such licence agreement. +;******************************************************* + +; Scatter-file for SMP Primes example on Cortex-A9x4 FVP model, Versatile Express or PandaBoard. + +LOAD_ROOT 0x0 +{ + Root +0 0x10000 + { + startup.o (StartUp, +FIRST) + } +} + +LOAD 0x80000000 +{ + CODE +0 + { + * (+RO) + } + + SHARED_DATA +0 + { + * (+RW,+ZI) + } + + ; App heap for all CPUs + ARM_LIB_HEAP +0 ALIGN 8 EMPTY 0x2000 {} + + ; App stacks for all CPUs - see startup.s + ARM_LIB_STACK +0 ALIGN 8 EMPTY 4*0x1000 {} + + ; IRQ stacks for all CPUs - see startup.s + IRQ_STACKS +0 ALIGN 8 EMPTY 4*256 {} + + PAGETABLES 0x80500000 EMPTY 0x00100000 {} +} \ No newline at end of file diff --git a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/startup.s b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/startup.s new file mode 100644 index 00000000..44b7735d --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/startup.s @@ -0,0 +1,576 @@ +; ------------------------------------------------------------ +; Cortex-A9 MPCore SMP Prime Number Generator Example +; +; Copyright ARM Ltd 2009. All rights reserved. +; ------------------------------------------------------------ + + PRESERVE8 + + AREA StartUp,CODE,READONLY + +; ------------------------------------------------------------ +; Define some values +; ------------------------------------------------------------ + +; - Standard definitions of mode bits and interrupt (I&F) flags in PSRs +Mode_USR EQU 0x10 +Mode_FIQ EQU 0x11 +Mode_IRQ EQU 0x12 +Mode_SVC EQU 0x13 +Mode_ABT EQU 0x17 +Mode_UNDEF EQU 0x1B +Mode_SYS EQU 0x1F +I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled +F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled + + + +; ------------------------------------------------------------ +; Porting defines +; ------------------------------------------------------------ + +L1_COHERENT EQU 0x00014c06 ; Template descriptor for coherent memory +L1_NONCOHERENT EQU 0x00000c1e ; Template descriptor for non-coherent memory +L1_DEVICE EQU 0x00000c16 ; Template descriptor for device memory + +; ------------------------------------------------------------ + + ENTRY + + EXPORT Vectors + +Vectors + B Reset_Handler + B Undefined_Handler + B SWI_Handler + B Prefetch_Handler + B Abort_Handler + NOP ;Reserved vector + B IRQ_Handler + B FIQ_Handler + +; ------------------------------------------------------------ +; Handlers for unused exceptions +; ------------------------------------------------------------ + +Undefined_Handler + B Undefined_Handler +SWI_Handler + B SWI_Handler +Prefetch_Handler + B Prefetch_Handler +Abort_Handler + B Abort_Handler +FIQ_Handler + B FIQ_Handler + +; ------------------------------------------------------------ +; Imports +; ------------------------------------------------------------ + + IMPORT read_irq_ack + IMPORT write_end_of_irq + IMPORT enable_GIC + IMPORT enable_gic_processor_interface + IMPORT set_priority_mask + IMPORT enable_irq_id + IMPORT set_irq_priority + IMPORT enable_scu + IMPORT join_smp + IMPORT secure_SCU_invalidate + IMPORT enable_maintenance_broadcast + IMPORT init_private_timer + IMPORT start_private_timer + IMPORT clear_private_timer_irq + IMPORT __main +; [EL Change Start] + IMPORT _tx_thread_smp_initialize_wait + IMPORT _tx_thread_smp_release_cores_flag + IMPORT _tx_thread_context_save + IMPORT _tx_thread_context_restore + IMPORT _tx_timer_interrupt + IMPORT _tx_thread_smp_inter_core_interrupts +; [EL Change End] + +; ------------------------------------------------------------ +; Interrupt Handler +; ------------------------------------------------------------ + + EXPORT IRQ_Handler + EXPORT __tx_irq_processing_return +IRQ_Handler PROC +; [EL Change Start] +; SUB lr, lr, #4 ; Pre-adjust lr +; SRSFD sp!, #Mode_IRQ ; Save lr and SPRS to IRQ mode stack +; PUSH {r0-r4, r12} ; Sace APCS corruptable registers to IRQ mode stack (and maintain 8 byte alignment) +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save +__tx_irq_processing_return + PUSH {r4, r5} ; Save some preserved registers (r5 is saved just for 8-byte alignment) +; [EL Change End] + + ; Acknowledge the interrupt + BL read_irq_ack + MOV r4, r0 + + ; + ; This example only uses (and enables) one. At this point + ; you would normally check the ID, and clear the source. + ; + + ; + ; Additonal code to handler private timer interrupt on CPU0 + ; + + CMP r0, #29 ; If not Private Timer interrupt (ID 29), by pass + BNE by_pass + +; [EL Change Start] +; MOV r0, #0x04 ; Code for SYS_WRITE0 +; LDR r1, =irq_handler_message0 +; SVC 0x123456 +; [EL Change End] + + ; Clear timer interrupt + BL clear_private_timer_irq + DSB +; [EL Change Start] + BL _tx_timer_interrupt ; Timer interrupt handler +; [EL Change End] + + B by_pass2 + +by_pass + +; [EL Change Start] + ; + ; Additional code to handle SGI on CPU0 + ; +; +; MRC p15, 0, r0, c0, c0, 5 ; Read CPU ID register +; ANDS r0, r0, #0x03 ; Mask off, leaving the CPU ID field +; BNE by_pass2 +; +; MOV r0, #0x04 ; Code for SYS_WRITE0 +; LDR r1, =irq_handler_message1 +; SVC 0x123456 +; +; /* Just increment the per-thread interrupt count for analysis purposes. */ +; + MRC p15, 0, r0, c0, c0, 5 ; Read CPU ID register + AND r0, r0, #0x03 ; Mask off, leaving the CPU ID field + LSL r0, r0, #2 ; Build offset to array indexes + LDR r1,=_tx_thread_smp_inter_core_interrupts ; Pickup base address of core interrupt counter array + ADD r1, r1, r0 ; Build array index + LDR r0, [r1] ; Pickup counter + ADD r0, r0, #1 ; Increment counter + STR r0, [r1] ; Store back counter +; +; [EL Change End] + + +by_pass2 + ; Write end of interrupt reg + MOV r0, r4 + BL write_end_of_irq + +; [EL Change Start] + +; +; /* Jump to context restore to restore system context. */ + POP {r4, r5} ; Recover preserved registers + B _tx_thread_context_restore + +; POP {r0-r4, r12} ; Restore stacked APCS registers +; MOV r2, #0x01 ; Set r2 so CPU leaves holding pen +; RFEFD sp! ; Return from exception +; [EL Change End] + + ENDP + +; ------------------------------------------------------------ +; Reset Handler - Generic initialization, run by all CPUs +; ------------------------------------------------------------ + + IMPORT ||Image$$ARM_LIB_STACK$$ZI$$Limit|| + IMPORT ||Image$$IRQ_STACKS$$ZI$$Limit|| + IMPORT ||Image$$PAGETABLES$$ZI$$Base|| + IMPORT enable_branch_prediction + IMPORT invalidate_caches + + EXPORT Reset_Handler ; Exported for callgraph purposes! +Reset_Handler PROC + +; +; Disable caches, MMU and branch prediction in case they were left enabled from an earlier run +; This does not need to be done from a cold reset +; ------------------------------------------------------------ + MRC p15, 0, r0, c1, c0, 0 ; Read System Control Register + BIC r0, r0, #(0x1 << 12) ; Clear I, bit 12, to disable I Cache + BIC r0, r0, #(0x1 << 11) ; Clear Z, bit 11, to disable branch prediction + BIC r0, r0, #(0x1 << 2) ; Clear C, bit 2, to disable D Cache + BIC r0, r0, #(0x1 << 1) ; Clear A, bit 1, to disable strict alignment fault checking + BIC r0, r0, #0x1 ; Clear M, bit 0, to disable MMU + MCR p15, 0, r0, c1, c0, 0 ; Write System Control Register + ISB + +; The MMU is enabled later, before calling main(). Caches and branch prediction are enabled inside main(), +; after the MMU has been enabled and scatterloading has been performed. + + ; + ; Setup stacks + ;--------------- + + MRC p15, 0, r0, c0, c0, 5 ; Read CPU ID register + ANDS r0, r0, #0x03 ; Mask off, leaving the CPU ID field + + MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit + LDR r1, =||Image$$IRQ_STACKS$$ZI$$Limit|| + SUB r1, r1, r0, LSL #8 ; 256 bytes of IRQ stack per CPU - see scatter.scat + MOV sp, r1 + +; [EL Change Start] + ;MSR CPSR_c, #Mode_SYS:OR:I_Bit:OR:F_Bit ; Interrupts initially disabled + MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit ; Interrupts initially disabled +; [EL Change End] + LDR r1, =||Image$$ARM_LIB_STACK$$ZI$$Limit|| ; App stacks for all CPUs + SUB r1, r1, r0, LSL #12 ; 0x1000 bytes of App stack per CPU - see scatter.scat + MOV sp, r1 + +; [EL Change Start] - leave MMU disabled + +; ; +; ; Set vector base address +; ; ------------------------ +; LDR r0, =Vectors +; MCR p15, 0, r0, c12, c0, 0 ; Write Secure or Non-secure Vector Base Address +; ; Ensure that V-bit is cleared +; MRC p15, 0, r0, c1, c0, 0 ; Read Control Register +; BIC r0, r0, #(1 << 13) ; Clear the V bit (bit 13) +; MCR p15, 0, r0, c1, c0, 0 ; Write Control Register +; ISB +; +; ; Invalidate caches +; ; ------------------ +; BL invalidate_caches +; +; ; +; ; Clear Branch Prediction Array +; ; ------------------------------ +; MOV r0, #0x0 +; MCR p15, 0, r0, c7, c5, 6 ; BPIALL - Invalidate entire branch predictor array +; +; ; +; ; Invalidate TLBs +; ;------------------ +; MOV r0, #0x0 +; MCR p15, 0, r0, c8, c7, 0 ; TLBIALL - Invalidate entire Unified TLB +; +; ; +; ; Set up Domain Access Control Reg +; ; ---------------------------------- +; ; b00 - No Access (abort) +; ; b01 - Client (respect table entry) +; ; b10 - RESERVED +; ; b11 - Manager (ignore access permissions) +; +; MRC p15, 0, r0, c3, c0, 0 ; Read Domain Access Control Register +; LDR r0, =0x55555555 ; Initialize every domain entry to b01 (client) +; MCR p15, 0, r0, c3, c0, 0 ; Write Domain Access Control Register +; +; ;; +; ;; Enable L1 Preloader - Auxiliary Control +; ;; ----------------------------------------- +; ;; Seems to undef on panda? +; ;MRC p15, 0, r0, c1, c0, 1 ; Read ACTLR +; ;ORR r0, r0, #0x4 +; ;MCR p15, 0, r0, c1, c0, 1 ; Write ACTLR +; ISB +; +; +; ; +; ; Set location of level 1 page table +; ;------------------------------------ +; ; 31:14 - Base addr +; ; 13:5 - 0x0 +; ; 4:3 - RGN 0x0 (Outer Noncachable) +; ; 2 - P 0x0 +; ; 1 - S 0x0 (Non-shared) +; ; 0 - C 0x0 (Inner Noncachable) +; LDR r0, =||Image$$PAGETABLES$$ZI$$Base|| +; MSR TTBR0, r0 + +; [EL Change End] + + ; + ; Activate VFP/NEON, if required + ;------------------------------- + + IF {TARGET_FEATURE_NEON} || {TARGET_FPU_VFP} + + ; Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11. + ; Enables Full Access i.e. in both privileged and non privileged modes + MRC p15, 0, r0, c1, c0, 2 ; Read Coprocessor Access Control Register (CPACR) + ORR r0, r0, #(0xF << 20) ; Enable access to CP 10 & 11 + MCR p15, 0, r0, c1, c0, 2 ; Write Coprocessor Access Control Register (CPACR) + ISB + + ; Switch on the VFP and NEON hardware + MOV r0, #0x40000000 + VMSR FPEXC, r0 ; Write FPEXC register, EN bit set + + ENDIF + +; [EL Change Start] + + LDR r0, =_tx_thread_smp_release_cores_flag ; Build address of release cores flag + MOV r1, #0 + STR r1, [r0] + +; [EL Change End] + + ; + ; SMP initialization + ; ------------------- + MRC p15, 0, r0, c0, c0, 5 ; Read CPU ID register + ANDS r0, r0, #0x03 ; Mask off, leaving the CPU ID field + BLEQ primary_cpu_init + BLNE secondary_cpus_init + + ENDP + +; ------------------------------------------------------------ +; Initialization for PRIMARY CPU +; ------------------------------------------------------------ + + EXPORT primary_cpu_init +primary_cpu_init PROC + +; [EL Change Start] - leave MMU disabled + +; ; Translation tables +; ; ------------------- +; ; The translation tables are generated at boot time. +; ; First the table is zeroed. Then the individual valid +; ; entries are written in +; ; +; +; LDR r0, =||Image$$PAGETABLES$$ZI$$Base|| +; +; ; Fill table with zeros +; MOV r2, #1024 ; Set r3 to loop count (4 entries per iteration, 1024 iterations) +; MOV r1, r0 ; Make a copy of the base dst +; MOV r3, #0 +; MOV r4, #0 +; MOV r5, #0 +; MOV r6, #0 +;ttb_zero_loop +; STMIA r1!, {r3-r6} ; Store out four entries +; SUBS r2, r2, #1 ; Decrement counter +; BNE ttb_zero_loop +; +; ; +; ; STANDARD ENTRIES +; ; +; +; ; Region covering program code and data +; IMPORT ||Image$$CODE$$Base|| +; LDR r1,=||Image$$CODE$$Base|| ; Base physical address of program code and data +; LSR r1,#20 ; Shift right to align to 1MB boundaries +; LDR r3, =L1_COHERENT ; Descriptor template +; ORR r3, r1, LSL#20 ; Combine address and template +; STR r3, [r0, r1, LSL#2] ; Store table entry +; +; ; Entry for private address space +; ; Needs to be marked as Device memory +; MRC p15, 4, r1, c15, c0, 0 ; Get base address of private address space +; LSR r1, r1, #20 ; Clear bottom 20 bits, to find which 1MB block it is in +; LSL r2, r1, #2 ; Make a copy, and multiply by four. This gives offset into the page tables +; LSL r1, r1, #20 ; Put back in address format +; LDR r3, =L1_DEVICE ; Descriptor template +; ORR r1, r1, r3 ; Combine address and template +; STR r1, [r0, r2] ; Store table entry +; +; ; +; ; OPTIONAL ENTRIES +; ; You will need additional translations if: +; ; - No RAM at zero, so cannot use flat mapping +; ; - You wish to retarget +; ; +; ; If you wish to output to stdio to a UART you will need +; ; an additional entry +; ;LDR r1, =PABASE_UART ; Physical address of UART +; ;LSR r1, r1, #20 ; Mask off bottom 20 bits to find which 1MB it is within +; ;LSL r2, r1, #2 ; Make a copy and multiply by 4 to get table offset +; ;LSL r1, r1, #20 ; Put back into address format +; ;LDR r3, =L1_DEVICE ; Descriptor template +; ;ORR r1, r1, r3 ; Combine address and template +; ;STR r1, [r0, r2] ; Store table entry +; +; DSB +; +; +; ; Enable MMU +; ; ----------- +; ; Leave the caches disabled until after scatter loading. +; MRC p15, 0, r0, c1, c0, 0 ; Read System Control Register +; ORR r0, r0, #0x1 ; Set M bit 0 to enable MMU before scatter loading +; MCR p15, 0, r0, c1, c0, 0 ; Write System Control Register +; ISB + +; [EL Change End] + + ; Enable the SCU + ; --------------- + BL enable_scu + + ; + ; Join SMP + ; --------- + MOV r0, #0x0 ; Move CPU ID into r0 + MOV r1, #0xF ; Move 0xF (represents all four ways) into r1 + BL secure_SCU_invalidate + BL join_smp + BL enable_maintenance_broadcast + + ; + ; GIC Init + ; --------- + BL enable_GIC + BL enable_gic_processor_interface + + + ; + ; Enable Private Timer for periodic IRQ + ; -------------------------------------- + MOV r0, #0x1F + BL set_priority_mask ; Set priority mask (local) + + ; [EL] Change start - don't enable interrupts here! + ;CPSIE i ; Clear CPSR I bit + ; [EL] Change end + + ; Enable the Private Timer Interrupt Source + MOV r0, #29 + MOV r1, #0 + BL enable_irq_id + + ; Set the priority + MOV r0, #29 + MOV r1, #0 + BL set_irq_priority + + ; Configure Timer + MOV r0, #0xF0000 + MOV r1, #0x0 + BL init_private_timer + BL start_private_timer + + ; + ; Enable receipt of SGI 0 + ; ------------------------ + MOV r0, #0x0 ; ID + BL enable_irq_id + + MOV r0, #0x0 ; ID + MOV r1, #0x0 ; Priority + BL set_irq_priority + + + ; + ; Branch to C lib code + ; ---------------------- + + B __main + + ENDP + +; ------------------------------------------------------------ +; Initialization for SECONDARY CPUs +; ------------------------------------------------------------ + + EXPORT secondary_cpus_init +secondary_cpus_init PROC + + ; + ; GIC Init + ; --------- + BL enable_gic_processor_interface + + MOV r0, #0x1F ; Priority + BL set_priority_mask + + MOV r0, #0x0 ; ID + BL enable_irq_id + + MOV r0, #0x0 ; ID + MOV r1, #0x0 ; Priority + BL set_irq_priority + + ; + ; Join SMP + ; --------- + MRC p15, 0, r0, c0, c0, 5 ; Read CPU ID register + ANDS r0, r0, #0x03 ; Mask off, leaving the CPU ID field + MOV r1, #0xF ; Move 0xF (represents all four ways) into r1 + BL secure_SCU_invalidate + + BL join_smp + BL enable_maintenance_broadcast + +; [EL Change Start] + +; ; +; ; Holding Pen +; ; ------------ +; MOV r10, #0 ; Clear exit flag +; CPSIE i ; Enable interrupts +;holding_pen +; CMP r10, #0 ; Exit flag will be set to 0x1 by IRQ handler on receiving SGI +; DSB ; Clear all pending data accesses +; WFIEQ +; BEQ holding_pen +; CPSID i ; Disable interrupts +; +; +; ; +; ; The translation tables are generated by the primary CPU +; ; The MMU cannot be enabled on the secondary CPUs until +; ; they are released from the holding-pen +; ; +; +; ; Enable MMU +; ; ----------- +; ; Leave the caches disabled until after scatter loading. +; MRC p15, 0, r0, c1, c0, 0 ; Read System Control Register +; ORR r0, r0, #0x1 ; Set M bit 0 to enable MMU before scatter loading +; MCR p15, 0, r0, c1, c0, 0 ; Write System Control Register +; ISB + +; [EL Change End] + + ; + ; Branch to C lib code + ; ---------------------- +; B __main + + B _tx_thread_smp_initialize_wait +; [EL Change End] + + ENDP + +; ------------------------------------------------------------ +; End of code +; ------------------------------------------------------------ + +irq_handler_message0 + DCB "\n#\n# Private Timer Interrupt!\n# \n\n \0 " +irq_handler_message1 + DCB "\n#\n# SGI on CPU0!\n# \n\n \0\0\0 " + + END + +; ------------------------------------------------------------ +; End of startup.s +; ------------------------------------------------------------ diff --git a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/v7.h b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/v7.h new file mode 100644 index 00000000..52a3c679 --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/v7.h @@ -0,0 +1,117 @@ +// ------------------------------------------------------------ +// v7-A Cache, TLB and Branch Prediction Maintenance Operations +// Header File +// +// Copyright ARM Ltd 2009. All rights reserved. +// ------------------------------------------------------------ + +#ifndef _SEE_V7_h +#define _SEE_V7_h + +#include "kernel.h" + +// +// Note: +// *_is() stands for "inner shareable" +// + +// ------------------------------------------------------------ +// Caches + +void enable_caches(void); +void disable_caches(void); + +void clean_dcache(void); +void clean_invalidate_dcache(void); + +void invalidate_caches(void); +void invalidate_caches_is(void); + +// ------------------------------------------------------------ +// TLBs + +void invalidate_unified_tlb(void); +void invalidate_unified_tlb_is(void); + +// ------------------------------------------------------------ +// Branch prediction + +void enable_branch_prediction(void); +void disable_branch_prediction(void); + +void invalidate_branch_target_cache(void); +void invalidate_branch_target_cache_is(void); + +// ------------------------------------------------------------ +// High Vecs + +void enable_highvecs(void); +void disable_highvecs(void); + +// ------------------------------------------------------------ +// ID Registers + +uint32_t get_MIDR(void); + +#define MIDR_IMPL_SHIFT 24 +#define MIDR_IMPL_MASK 0xFF +#define MIDR_VAR_SHIFT 20 +#define MIDR_VAR_MASK 0xF +#define MIDR_ARCH_SHIFT 16 +#define MIDR_ARCH_MASK 0xF +#define MIDR_PART_SHIFT 4 +#define MIDR_PART_MASK 0xFFF +#define MIDR_REV_SHIFT 0 +#define MIDR_REV_MASK 0xF + +// tmp = get_MIDR(); +// implementor = (tmp >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; +// variant = (tmp >> MIDR_VAR_SHIFT) & MIDR_VAR_MASK; +// architecture= (tmp >> MIDR_ARCH_SHIFT) & MIDR_ARCH_MASK; +// part_number = (tmp >> MIDR_PART_SHIFT) & MIDR_PART_MASK; +// revision = tmp & MIDR_REV_MASK; + +#define MIDR_PART_CA5 0xC05 +#define MIDR_PART_CA8 0xC08 +#define MIDR_PART_CA9 0xC09 + +uint32_t get_MPIDR(void); + +#define MPIDR_FORMAT_SHIFT 31 +#define MPIDR_FORMAT_MASK 0x1 +#define MPIDR_UBIT_SHIFT 30 +#define MPIDR_UBIT_MASK 0x1 +#define MPIDR_CLUSTER_SHIFT 7 +#define MPIDR_CLUSTER_MASK 0xF +#define MPIDR_CPUID_SHIFT 0 +#define MPIDR_CPUID_MASK 0x3 + +#define MPIDR_CPUID_CPU0 0x0 +#define MPIDR_CPUID_CPU1 0x1 +#define MPIDR_CPUID_CPU2 0x2 +#define MPIDR_CPUID_CPU3 0x3 + +#define MPIDR_UNIPROCESSPR 0x1 + +#define MPDIR_NEW_FORMAT 0x1 + +// ------------------------------------------------------------ +// Context ID + +uint32_t get_context_id(void); +void set_context_id(uint32_t); + +#define CONTEXTID_ASID_SHIFT 0 +#define CONTEXTID_ASID_MASK 0xFF +#define CONTEXTID_PROCID_SHIFT 8 +#define CONTEXTID_PROCID_MASK 0x00FFFFFF + +// tmp = get_context_id(); +// ASID = tmp & CONTEXTID_ASID_MASK; +// PROCID = (tmp >> CONTEXTID_PROCID_SHIFT) & CONTEXTID_PROCID_MASK; + +#endif + +// ------------------------------------------------------------ +// End of v7.h +// ------------------------------------------------------------ diff --git a/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/v7.s b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/v7.s new file mode 100644 index 00000000..d4948c88 --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/v7.s @@ -0,0 +1,381 @@ +; ------------------------------------------------------------ +; v7-A Cache and Branch Prediction Maintenance Operations +; ------------------------------------------------------------ + + PRESERVE8 + + AREA v7CacheOpp,CODE,READONLY + +; ------------------------------------------------------------ +; Cache Maintenance +; ------------------------------------------------------------ + + EXPORT enable_caches + ; void enable_caches(void); +enable_caches PROC + MRC p15, 0, r0, c1, c0, 0 ; Read System Control Register configuration data + ORR r0, r0, #(1 << 2) ; Set C bit + ORR r0, r0, #(1 << 12) ; Set I bit + MCR p15, 0, r0, c1, c0, 0 ; Write System Control Register configuration data + BX lr + ENDP + + + EXPORT disable_caches + ; void disable_caches(void) +disable_caches PROC + MRC p15, 0, r0, c1, c0, 0 ; Read System Control Register configuration data + BIC r0, r0, #(1 << 2) ; Clear C bit + BIC r0, r0, #(1 << 12) ; Clear I bit + MCR p15, 0, r0, c1, c0, 0 ; Write System Control Register configuration data + BX lr + ENDP + + + EXPORT clean_dcache + ; void clean_dcache(void); +clean_dcache PROC + PUSH {r4-r12} + + ; + ; Based on code example given in section 11.2.4 of ARM DDI 0406B + ; + + MRC p15, 1, r0, c0, c0, 1 ; Read CLIDR + ANDS r3, r0, #&7000000 + MOV r3, r3, LSR #23 ; Cache level value (naturally aligned) + BEQ clean_dcache_finished + MOV r10, #0 + +clean_dcache_loop1 + ADD r2, r10, r10, LSR #1 ; Work out 3xcachelevel + MOV r1, r0, LSR r2 ; bottom 3 bits are the Cache type for this level + AND r1, r1, #7 ; get those 3 bits alone + CMP r1, #2 + BLT clean_dcache_skip ; no cache or only instruction cache at this level + MCR p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register + ISB ; ISB to sync the change to the CacheSizeID reg + MRC p15, 1, r1, c0, c0, 0 ; reads current Cache Size ID register + AND r2, r1, #&7 ; extract the line length field + ADD r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes) + LDR r4, =0x3FF + ANDS r4, r4, r1, LSR #3 ; R4 is the max number on the way size (right aligned) + CLZ r5, r4 ; R5 is the bit position of the way size increment + LDR r7, =0x00007FFF + ANDS r7, r7, r1, LSR #13 ; R7 is the max number of the index size (right aligned) + +clean_dcache_loop2 + MOV r9, R4 ; R9 working copy of the max way size (right aligned) + +clean_dcache_loop3 + ORR r11, r10, r9, LSL r5 ; factor in the way number and cache number into R11 + ORR r11, r11, r7, LSL r2 ; factor in the index number + MCR p15, 0, r11, c7, c10, 2 ; DCCSW - clean by set/way + SUBS r9, r9, #1 ; decrement the way number + BGE clean_dcache_loop3 + SUBS r7, r7, #1 ; decrement the index + BGE clean_dcache_loop2 + +clean_dcache_skip + ADD r10, r10, #2 ; increment the cache number + CMP r3, r10 + BGT clean_dcache_loop1 + +clean_dcache_finished + POP {r4-r12} + + BX lr + ENDP + + EXPORT clean_invalidate_dcache + ; void clean_invalidate_dcache(void); +clean_invalidate_dcache PROC + PUSH {r4-r12} + + ; + ; Based on code example given in section 11.2.4 of ARM DDI 0406B + ; + + MRC p15, 1, r0, c0, c0, 1 ; Read CLIDR + ANDS r3, r0, #&7000000 + MOV r3, r3, LSR #23 ; Cache level value (naturally aligned) + BEQ clean_invalidate_dcache_finished + MOV r10, #0 + +clean_invalidate_dcache_loop1 + ADD r2, r10, r10, LSR #1 ; Work out 3xcachelevel + MOV r1, r0, LSR r2 ; bottom 3 bits are the Cache type for this level + AND r1, r1, #7 ; get those 3 bits alone + CMP r1, #2 + BLT clean_invalidate_dcache_skip ; no cache or only instruction cache at this level + MCR p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register + ISB ; ISB to sync the change to the CacheSizeID reg + MRC p15, 1, r1, c0, c0, 0 ; reads current Cache Size ID register + AND r2, r1, #&7 ; extract the line length field + ADD r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes) + LDR r4, =0x3FF + ANDS r4, r4, r1, LSR #3 ; R4 is the max number on the way size (right aligned) + CLZ r5, r4 ; R5 is the bit position of the way size increment + LDR r7, =0x00007FFF + ANDS r7, r7, r1, LSR #13 ; R7 is the max number of the index size (right aligned) + +clean_invalidate_dcache_loop2 + MOV r9, R4 ; R9 working copy of the max way size (right aligned) + +clean_invalidate_dcache_loop3 + ORR r11, r10, r9, LSL r5 ; factor in the way number and cache number into R11 + ORR r11, r11, r7, LSL r2 ; factor in the index number + MCR p15, 0, r11, c7, c14, 2 ; DCCISW - clean and invalidate by set/way + SUBS r9, r9, #1 ; decrement the way number + BGE clean_invalidate_dcache_loop3 + SUBS r7, r7, #1 ; decrement the index + BGE clean_invalidate_dcache_loop2 + +clean_invalidate_dcache_skip + ADD r10, r10, #2 ; increment the cache number + CMP r3, r10 + BGT clean_invalidate_dcache_loop1 + +clean_invalidate_dcache_finished + POP {r4-r12} + + BX lr + ENDP + + + EXPORT invalidate_caches + ; void invalidate_caches(void); +invalidate_caches PROC + PUSH {r4-r12} + + ; + ; Based on code example given in section B2.2.4/11.2.4 of ARM DDI 0406B + ; + + MOV r0, #0 + MCR p15, 0, r0, c7, c5, 0 ; ICIALLU - Invalidate entire I Cache, and flushes branch target cache + + MRC p15, 1, r0, c0, c0, 1 ; Read CLIDR + ANDS r3, r0, #&7000000 + MOV r3, r3, LSR #23 ; Cache level value (naturally aligned) + BEQ invalidate_caches_finished + MOV r10, #0 + +invalidate_caches_loop1 + ADD r2, r10, r10, LSR #1 ; Work out 3xcachelevel + MOV r1, r0, LSR r2 ; bottom 3 bits are the Cache type for this level + AND r1, r1, #7 ; get those 3 bits alone + CMP r1, #2 + BLT invalidate_caches_skip ; no cache or only instruction cache at this level + MCR p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register + ISB ; ISB to sync the change to the CacheSizeID reg + MRC p15, 1, r1, c0, c0, 0 ; reads current Cache Size ID register + AND r2, r1, #&7 ; extract the line length field + ADD r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes) + LDR r4, =0x3FF + ANDS r4, r4, r1, LSR #3 ; R4 is the max number on the way size (right aligned) + CLZ r5, r4 ; R5 is the bit position of the way size increment + LDR r7, =0x00007FFF + ANDS r7, r7, r1, LSR #13 ; R7 is the max number of the index size (right aligned) + +invalidate_caches_loop2 + MOV r9, R4 ; R9 working copy of the max way size (right aligned) + +invalidate_caches_loop3 + ORR r11, r10, r9, LSL r5 ; factor in the way number and cache number into R11 + ORR r11, r11, r7, LSL r2 ; factor in the index number + MCR p15, 0, r11, c7, c6, 2 ; DCISW - invalidate by set/way + SUBS r9, r9, #1 ; decrement the way number + BGE invalidate_caches_loop3 + SUBS r7, r7, #1 ; decrement the index + BGE invalidate_caches_loop2 + +invalidate_caches_skip + ADD r10, r10, #2 ; increment the cache number + CMP r3, r10 + BGT invalidate_caches_loop1 + +invalidate_caches_finished + POP {r4-r12} + BX lr + ENDP + + + EXPORT invalidate_caches_is + ; void invalidate_caches_is(void); +invalidate_caches_is PROC + PUSH {r4-r12} + + MOV r0, #0 + MCR p15, 0, r0, c7, c1, 0 ; ICIALLUIS - Invalidate entire I Cache inner shareable + + MRC p15, 1, r0, c0, c0, 1 ; Read CLIDR + ANDS r3, r0, #&7000000 + MOV r3, r3, LSR #23 ; Cache level value (naturally aligned) + BEQ invalidate_caches_is_finished + MOV r10, #0 + +invalidate_caches_is_loop1 + ADD r2, r10, r10, LSR #1 ; Work out 3xcachelevel + MOV r1, r0, LSR r2 ; bottom 3 bits are the Cache type for this level + AND r1, r1, #7 ; get those 3 bits alone + CMP r1, #2 + BLT invalidate_caches_is_skip ; no cache or only instruction cache at this level + MCR p15, 2, r10, c0, c0, 0 ; write the Cache Size selection register + ISB ; ISB to sync the change to the CacheSizeID reg + MRC p15, 1, r1, c0, c0, 0 ; reads current Cache Size ID register + AND r2, r1, #&7 ; extract the line length field + ADD r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes) + LDR r4, =0x3FF + ANDS r4, r4, r1, LSR #3 ; R4 is the max number on the way size (right aligned) + CLZ r5, r4 ; R5 is the bit position of the way size increment + LDR r7, =0x00007FFF + ANDS r7, r7, r1, LSR #13 ; R7 is the max number of the index size (right aligned) + +invalidate_caches_is_loop2 + MOV r9, R4 ; R9 working copy of the max way size (right aligned) + +invalidate_caches_is_loop3 + ORR r11, r10, r9, LSL r5 ; factor in the way number and cache number into R11 + ORR r11, r11, r7, LSL r2 ; factor in the index number + MCR p15, 0, r11, c7, c6, 2 ; DCISW - clean by set/way + SUBS r9, r9, #1 ; decrement the way number + BGE invalidate_caches_is_loop3 + SUBS r7, r7, #1 ; decrement the index + BGE invalidate_caches_is_loop2 + +invalidate_caches_is_skip + ADD r10, r10, #2 ; increment the cache number + CMP r3, r10 + BGT invalidate_caches_is_loop1 + +invalidate_caches_is_finished + POP {r4-r12} + BX lr + ENDP + +; ------------------------------------------------------------ +; TLB +; ------------------------------------------------------------ + + EXPORT invalidate_unified_tlb + ; void invalidate_unified_tlb(void); +invalidate_unified_tlb PROC + MOV r0, #1 + MCR p15, 0, r0, c8, c7, 0 ; TLBIALL - Invalidate entire unified TLB + BX lr + ENDP + + EXPORT invalidate_unified_tlb_is + ; void invalidate_unified_tlb_is(void); +invalidate_unified_tlb_is PROC + MOV r0, #1 + MCR p15, 0, r0, c8, c3, 0 ; TLBIALLIS - Invalidate entire unified TLB Inner Shareable + BX lr + ENDP + +; ------------------------------------------------------------ +; Branch Prediction +; ------------------------------------------------------------ + + EXPORT enable_branch_prediction + ; void enable_branch_prediction(void) +enable_branch_prediction PROC + MRC p15, 0, r0, c1, c0, 0 ; Read SCTLR + ORR r0, r0, #(1 << 11) ; Set the Z bit (bit 11) + MCR p15, 0,r0, c1, c0, 0 ; Write SCTLR + BX lr + ENDP + + EXPORT disable_branch_prediction + ; void disable_branch_prediction(void) +disable_branch_prediction PROC + MRC p15, 0, r0, c1, c0, 0 ; Read SCTLR + BIC r0, r0, #(1 << 11) ; Clear the Z bit (bit 11) + MCR p15, 0,r0, c1, c0, 0 ; Write SCTLR + BX lr + ENDP + + EXPORT invalidate_branch_target_cache + ; void invalidate_branch_target_cache(void) +invalidate_branch_target_cache PROC + MOV r0, #0 + MCR p15, 0, r0, c7, c5, 6 ; BPIALL - Invalidate entire branch predictor array + BX lr + ENDP + + EXPORT invalidate_branch_target_cache_is + ; void invalidate_branch_target_cache_is(void) +invalidate_branch_target_cache_is PROC + MOV r0, #0 + MCR p15, 0, r0, c7, c1, 6 ; BPIALLIS - Invalidate entire branch predictor array Inner Shareable + BX lr + ENDP + +; ------------------------------------------------------------ +; High Vecs +; ------------------------------------------------------------ + + EXPORT enable_highvecs + ; void enable_highvecs(void); +enable_highvecs PROC + MRC p15, 0, r0, c1, c0, 0 ; Read Control Register + ORR r0, r0, #(1 << 13) ; Set the V bit (bit 13) + MCR p15, 0, r0, c1, c0, 0 ; Write Control Register + BX lr + ENDP + + EXPORT disable_highvecs + ; void disable_highvecs(void); +disable_highvecs PROC + MRC p15, 0, r0, c1, c0, 0 ; Read Control Register + BIC r0, r0, #(1 << 13) ; Clear the V bit (bit 13) + MCR p15, 0, r0, c1, c0, 0 ; Write Control Register + BX lr + ENDP + +; ------------------------------------------------------------ +; Context ID +; ------------------------------------------------------------ + + EXPORT get_context_id + ; uint32_t get_context_id(void); +get_context_id PROC + MRC p15, 0, r0, c13, c0, 1 ; Read Context ID Register + BX lr + ENDP + + EXPORT set_context_id + ; void set_context_id(uint32_t); +set_context_id PROC + MCR p15, 0, r0, c13, c0, 1 ; Write Context ID Register + BX lr + ENDP + +; ------------------------------------------------------------ +; ID registers +; ------------------------------------------------------------ + + EXPORT get_MIDR + ; uint32_t get_MIDR(void); +get_MIDR PROC + MRC p15, 0, r0, c0, c0, 0 ; Read Main ID Register (MIDR) + BX lr + ENDP + + EXPORT get_MPIDR + ; uint32_t get_MPIDR(void); +get_MPIDR PROC + MRC p15, 0, r0, c0 ,c0, 5; Read Multiprocessor ID register (MPIDR) + BX lr + ENDP + +; ------------------------------------------------------------ +; End of code +; ------------------------------------------------------------ + + END + +; ------------------------------------------------------------ +; End of v7.s +; ------------------------------------------------------------ diff --git a/ports_smp/cortex_a9_smp/ac5/example_build/tx/.cproject b/ports_smp/cortex_a9_smp/ac5/example_build/tx/.cproject new file mode 100644 index 00000000..49ceac9e --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/example_build/tx/.cproject @@ -0,0 +1,123 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/cortex_a9_smp/ac5/example_build/tx/.project b/ports_smp/cortex_a9_smp/ac5/example_build/tx/.project new file mode 100644 index 00000000..8eeafa82 --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/example_build/tx/.project @@ -0,0 +1,47 @@ + + + tx + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + inc_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_smp/inc + + + inc_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/inc + + + src_generic + 2 + $%7BPARENT-5-PROJECT_LOC%7D/common_smp/src + + + src_port + 2 + $%7BPARENT-2-PROJECT_LOC%7D/src + + + diff --git a/ports_smp/cortex_a9_smp/ac5/example_build/tx/.settings/language.settings.xml b/ports_smp/cortex_a9_smp/ac5/example_build/tx/.settings/language.settings.xml new file mode 100644 index 00000000..70f77db2 --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/example_build/tx/.settings/language.settings.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ports_smp/cortex_a9_smp/ac5/inc/tx_port.h b/ports_smp/cortex_a9_smp/ac5/inc/tx_port.h new file mode 100644 index 00000000..a429a7c9 --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/inc/tx_port.h @@ -0,0 +1,411 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h SMP/Cortex-A9/AC5 */ +/* 6.0.1 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/************* Define ThreadX SMP constants. *************/ + +/* Define the ThreadX SMP maximum number of cores. */ + +#ifndef TX_THREAD_SMP_MAX_CORES +#define TX_THREAD_SMP_MAX_CORES 4 +#endif + + +/* Define the ThreadX SMP core mask. */ + +#ifndef TX_THREAD_SMP_CORE_MASK +#define TX_THREAD_SMP_CORE_MASK 0xF /* Where bit 0 represents Core 0, bit 1 represents Core 1, etc. */ +#endif + + +/* Define INLINE_DECLARE to whitespace for ARM compiler. */ + +#define INLINE_DECLARE + + +/* Define dynamic number of cores option. When commented out, the number of cores is static. */ + +/* #define TX_THREAD_SMP_DYNAMIC_CORE_MAX */ + + +/* Define ThreadX SMP initialization macro. */ + +#define TX_PORT_SPECIFIC_PRE_INITIALIZATION + + +/* Define ThreadX SMP pre-scheduler initialization. */ + +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION + + +/* Enable the inter-core interrupt logic. */ + +#define TX_THREAD_SMP_INTER_CORE_INTERRUPT + + +/* Determine if there is customer-specific wakeup logic needed. */ + +#ifdef TX_THREAD_SMP_WAKEUP_LOGIC + +/* Include customer-specific wakeup code. */ + +#include "tx_thread_smp_core_wakeup.h" +#else + +#ifdef TX_THREAD_SMP_DEFAULT_WAKEUP_LOGIC + +/* Default wakeup code. */ +#define TX_THREAD_SMP_WAKEUP_LOGIC +#define TX_THREAD_SMP_WAKEUP(i) _tx_thread_smp_core_preempt(i) +#endif +#endif + + +/* Ensure that the in-line resume/suspend define is not allowed. */ + +#ifdef TX_INLINE_THREAD_RESUME_SUSPEND +#undef TX_INLINE_THREAD_RESUME_SUSPEND +#endif + + +/************* End ThreadX SMP constants. *************/ + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX ARM port. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_INT_DISABLE 0xC0 /* Disable IRQ & FIQ interrupts */ +#else +#define TX_INT_DISABLE 0x80 /* Disable IRQ interrupts */ +#endif +#define TX_INT_ENABLE 0x00 /* Enable IRQ interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE _tx_thread_smp_time_get() +#endif +#else +#ifndef TX_TRACE_TIME_SOURCE +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif +#endif +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#ifdef TX_ENABLE_FIQ_SUPPORT +#define TX_FIQ_ENABLED 1 +#else +#define TX_FIQ_ENABLED 0 +#endif + +#ifdef TX_ENABLE_IRQ_NESTING +#define TX_IRQ_NESTING_ENABLED 2 +#else +#define TX_IRQ_NESTING_ENABLED 0 +#endif + +#ifdef TX_ENABLE_FIQ_NESTING +#define TX_FIQ_NESTING_ENABLED 4 +#else +#define TX_FIQ_NESTING_ENABLED 0 +#endif + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (TX_FIQ_ENABLED | TX_IRQ_NESTING_ENABLED | TX_FIQ_NESTING_ENABLED) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#define TX_THREAD_EXTENSION_2 ULONG tx_thread_vfp_enable; +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_QUEUE_EXTENSION +#define TX_SEMAPHORE_EXTENSION +#define TX_TIMER_EXTENSION + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#ifndef __thumb + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \ + b = (ULONG) __clz((unsigned int) m); \ + b = 31 - b; +#endif +#endif + + +/************* Define ThreadX SMP data types and function prototypes. *************/ + +struct TX_THREAD_STRUCT; + + +/* Define the ThreadX SMP protection structure. */ + +typedef struct TX_THREAD_SMP_PROTECT_STRUCT +{ + ULONG tx_thread_smp_protect_in_force; + struct TX_THREAD_STRUCT * + tx_thread_smp_protect_thread; + ULONG tx_thread_smp_protect_core; + ULONG tx_thread_smp_protect_count; + + /* Implementation specific information follows. */ + + ULONG tx_thread_smp_protect_get_caller; + ULONG tx_thread_smp_protect_sr; + ULONG tx_thread_smp_protect_release_caller; +} TX_THREAD_SMP_PROTECT; + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_smp_protect(); +#define TX_RESTORE _tx_thread_smp_unprotect(interrupt_save); + + +/************* End ThreadX SMP data type and function prototype definitions. *************/ + + +/* Define the interrupt lockout macros for each ThreadX object. */ + +#define TX_BLOCK_POOL_DISABLE TX_DISABLE +#define TX_BYTE_POOL_DISABLE TX_DISABLE +#define TX_EVENT_FLAGS_GROUP_DISABLE TX_DISABLE +#define TX_MUTEX_DISABLE TX_DISABLE +#define TX_QUEUE_DISABLE TX_DISABLE +#define TX_SEMAPHORE_DISABLE TX_DISABLE + + +/* Define VFP extension for the Cortex-A9. Each is assumed to be called in the context of the executing + thread. */ + +void tx_thread_vfp_enable(void); +void tx_thread_vfp_disable(void); + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Cortex-A9/AC5 Version Version 6.0.1 *"; +#else +extern CHAR _tx_version_id[]; +#endif + + +#endif + + + diff --git a/ports_smp/cortex_a9_smp/ac5/readme_threadx.txt b/ports_smp/cortex_a9_smp/ac5/readme_threadx.txt new file mode 100644 index 00000000..ea7708f4 --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/readme_threadx.txt @@ -0,0 +1,235 @@ + Microsoft's Azure RTOS ThreadX SMP for Cortex-A9 + + Thumb & 32-bit Mode + + Using the ARM Compiler 5 & DS + + +1. Import the ThreadX Projects + +In order to build the ThreadX SMP library and the ThreadX SMP demonstration, first import +the 'tx' and 'sample_threadx' projects (located in the "example_build" directory) +into your DS workspace. + +Note: the projects were made using DS-5, so DS will prompt you to migrate the projects. +This is expected, so please do so. + + +2. Building the ThreadX SMP run-time Library + +Building the ThreadX SMP library is easy; simply select the Eclipse project file +"tx" and then select the build button. You should now observe the compilation +and assembly of the ThreadX SMP library. This project build produces the ThreadX SMP +library file tx.a. + + +3. Demonstration System + +The ThreadX SMP demonstration is designed to execute under the DS debugger on the +VE_Cortex-A9x4 Bare Metal simulator. + +Building the demonstration is easy; simply open the workspace file, select the +sample_threadx project, and select the build button. Next, expand the demo ThreadX +project folder in the Project Explorer window, right-click on the 'Cortex-A9x4_tx.launch' +file, click 'Debug As', and then click 'Cortex-A9x4_tx' from the submenu. This will cause the +debugger to load the sample_threadx.axf ELF file and run to main. You are now ready +to execute the ThreadX demonstration. + + +4. System Initialization + +The entry point in ThreadX SMP for the Cortex-A9 using ARM tools is at label +"ENTRY". This is defined within the ARM compiler's startup code. In addition, +this is where all static and global pre-set C variable initialization processing +takes place. + +The ThreadX SMP tx_initialize_low_level.s file is responsible for determining the +first available RAM address for use by the application, which is supplied as the +sole input parameter to your application definition function, tx_application_define. + + +5. Register Usage and Stack Frames + +The ARM compiler assumes that registers r0-r3 (a1-a4) and r12 (ip) are scratch +registers for each function. All other registers used by a C function must +be preserved by the function. ThreadX takes advantage of this in situations +where a context switch happens as a result of making a ThreadX service call +(which is itself a C function). In such cases, the saved context of a thread +is only the non-scratch registers. + +The following defines the saved context stack frames for context switches +that occur as a result of interrupt handling or from thread-level API calls. +All suspended threads have one of these two types of stack frames. The top +of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the +associated thread control block TX_THREAD. + + + + Offset Interrupted Stack Frame Non-Interrupt Stack Frame + + 0x00 1 0 + 0x04 CPSR CPSR + 0x08 r0 (a1) r4 (v1) + 0x0C r1 (a2) r5 (v2) + 0x10 r2 (a3) r6 (v3) + 0x14 r3 (a4) r7 (v4) + 0x18 r4 (v1) r8 (v5) + 0x1C r5 (v2) r9 (v6) + 0x20 r6 (v3) r10 (v7) + 0x24 r7 (v4) r11 (fp) + 0x28 r8 (v5) r14 (lr) + 0x2C r9 (v6) + 0x30 r10 (v7) + 0x34 r11 (fp) + 0x38 r12 (ip) + 0x3C r14 (lr) + 0x40 PC + + +6. Improving Performance + +The distribution version of ThreadX is built without any compiler +optimizations. This makes it easy to debug because you can trace or set +breakpoints inside of ThreadX itself. Of course, this costs some +performance. To make it run faster, you can change the build_threadx.bat file to +remove the -g option and enable all compiler optimizations. + +In addition, you can eliminate the ThreadX basic API error checking by +compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING +defined. + + +7. Interrupt Handling + +ThreadX provides complete and high-performance interrupt handling for Cortex-A9 +targets. There are a certain set of requirements that are defined in the +following sub-sections: + + +7.1 Vector Area + +The Cortex-A9 vectors start at address zero. The demonstration system startup +Init area contains the vectors and is loaded at address zero. On actual +hardware platforms, this area might have to be copied to address 0. + + +8.2 IRQ ISRs + +ThreadX fully manages standard and vectored IRQ interrupts. ThreadX also supports nested +IRQ interrupts. The following sub-sections define the IRQ capabilities. + + +7.2.1 Standard IRQ ISRs + +The standard ARM IRQ mechanism has a single interrupt vector at address 0x18. This IRQ +interrupt is managed by the __tx_irq_handler code in startup.s. The following +is the default IRQ handler defined in startup.s: + + EXPORT IRQ_Handler + EXPORT __tx_irq_processing_return +IRQ_Handler PROC +; +; /* Jump to context save to save system context. */ + B _tx_thread_context_save ; Jump to the context save +__tx_irq_processing_return +; +; /* At this point execution is still in the IRQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. Note +; that IRQ interrupts are still disabled upon return from the context +; save function. */ +; +; /* Application ISR call(s) go here! */ +; +; /* Jump to context restore to restore system context. */ + B _tx_thread_context_restore + + +7.3 FIQ Interrupts + +By default, Cortex-A9 FIQ interrupts are left alone by ThreadX. Of course, this +means that the application is fully responsible for enabling the FIQ interrupt +and saving/restoring any registers used in the FIQ ISR processing. To globally +enable FIQ interrupts, the application should enable FIQ interrupts at the +beginning of each thread or before any threads are created in tx_application_define. +In addition, the application must ensure that no ThreadX service calls are made +from default FIQ ISRs, which is located in tx_initialize_low_level.s. + + +7.3.1 Managed FIQ Interrupts + +Full ThreadX management of FIQ interrupts is provided if the ThreadX sources +are built with the TX_ENABLE_FIQ_SUPPORT defined. If the library is built +this way, the FIQ interrupt handlers are very similar to the IRQ interrupt +handlers defined previously. The following is default FIQ handler +defined in tx_initialize_low_level.s: + + + EXPORT __tx_fiq_handler + EXPORT __tx_fiq_processing_return +__tx_fiq_handler +; +; /* Jump to fiq context save to save system context. */ + B _tx_thread_fiq_context_save +__tx_fiq_processing_return: +; +; /* At this point execution is still in the FIQ mode. The CPSR, point of +; interrupt, and all C scratch registers are available for use. */ +; +; /* Application FIQ handlers can be called here! */ +; +; /* Jump to fiq context restore to restore system context. */ + B _tx_thread_fiq_context_restore + + +8. ThreadX Timer Interrupt + +ThreadX requires a periodic interrupt source to manage all time-slicing, +thread sleeps, timeouts, and application timers. Without such a timer +interrupt source, these services are not functional. However, all other +ThreadX services are operational without a periodic timer source. + +To add the timer interrupt processing, simply make a call to +_tx_timer_interrupt in the IRQ processing. An example of this can be +found in the file tx_initialize_low_level.s in the Integrator sub-directories. + + +9. Thumb/Cortex-A9 Mixed Mode + +By default, ThreadX is setup for running in Cortex-A9 32-bit mode. This is +also true for the demonstration system. It is possible to build any +ThreadX file and/or the application in Thumb mode. If any Thumb code +is used the entire ThreadX source- both C and assembly - should be built +with the "-apcs /interwork" option. + + +10. VFP Support + +By default, VFP support is disabled for each thread. If saving the context of the VFP registers +is needed, the following API call must be made from the context of the application thread - before +the VFP usage: + +void tx_thread_vfp_enable(void); + +After this API is called in the application, VFP registers will be saved/restored for this thread if it +is preempted via an interrupt. All other suspension of the this thread will not require the VFP registers +to be saved/restored. + +To disable VFP register context saving, simply call the following API: + +void tx_thread_vfp_disable(void); + + +11. Revision History + +For generic code revision information, please refer to the readme_threadx_generic.txt +file, which is included in your distribution. The following details the revision +information associated with this specific port of ThreadX: + +06/30/2020 Initial ThreadX 6.0.1 version for Cortex-A9 using AC5 tools. + + +Copyright(c) 1996-2020 Microsoft Corporation + + +https://azure.com/rtos + diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_initialize_low_level.s b/ports_smp/cortex_a9_smp/ac5/src/tx_initialize_low_level.s new file mode 100644 index 00000000..bbaa25aa --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_initialize_low_level.s @@ -0,0 +1,119 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_initialize.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; +; +; + IMPORT _tx_thread_system_stack_ptr + IMPORT _tx_initialize_unused_memory + IMPORT _tx_version_id + IMPORT _tx_build_options + IMPORT ||Image$$SHARED_DATA$$ZI$$Limit|| +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level SMP/Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + EXPORT _tx_initialize_low_level +_tx_initialize_low_level +; +; /* Save the first available memory address. */ +; _tx_initialize_unused_memory = (VOID_PTR) (||Image$$SHARED_DATA$$ZI$$Limit||); +; + LDR r0, =||Image$$SHARED_DATA$$ZI$$Limit|| ; Get end of non-initialized RAM area + LDR r2, =_tx_initialize_unused_memory ; Pickup unused memory ptr address + STR r0, [r2, #0] ; Save first free memory address +; +; + +; /* Done, return to caller. */ +; + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +;} +; +; /* Reference build options and version ID to ensure they come in. */ +; + LDR r2, =_tx_build_options ; Pickup build options variable address + LDR r0, [r2, #0] ; Pickup build options content + LDR r2, =_tx_version_id ; Pickup version ID variable address + LDR r0, [r2, #0] ; Pickup version ID content +; +; + + END + diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_context_restore.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_context_restore.s new file mode 100644 index 00000000..7feeb883 --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_context_restore.s @@ -0,0 +1,371 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +;/* Include macros for modifying the wait list. */ +#include "tx_thread_smp_protection_wait_list_macros.h" + + IF :DEF:TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts +IRQ_MODE EQU 0xD2 ; IRQ mode +SVC_MODE EQU 0xD3 ; SVC mode + ELSE +DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts +IRQ_MODE EQU 0x92 ; IRQ mode +SVC_MODE EQU 0x93 ; SVC mode + ENDIF +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_execute_ptr + IMPORT _tx_timer_time_slice + IMPORT _tx_thread_schedule + IMPORT _tx_thread_preempt_disable + IMPORT _tx_timer_interrupt_active + IMPORT _tx_thread_smp_protection + IMPORT _tx_thread_smp_protect_wait_counts + IMPORT _tx_thread_smp_protect_wait_list + IMPORT _tx_thread_smp_protect_wait_list_lock_protect_in_force + IMPORT _tx_thread_smp_protect_wait_list_tail + IMPORT _tx_thread_smp_protect_wait_list_size + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_exit + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore SMP/Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + EXPORT _tx_thread_context_restore +_tx_thread_context_restore +; +; /* Lockout interrupts. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR exit function to indicate an ISR is complete. */ +; + BL _tx_execution_isr_exit ; Call the ISR exit function + ENDIF + +; /* Pickup the CPU ID. */ +; + MRC p15, 0, r10, c0, c0, 5 ; Read CPU ID register + AND r10, r10, #0x03 ; Mask off, leaving the CPU ID field + LSL r12, r10, #2 ; Build offset to array indexes +; +; /* Determine if interrupts are nested. */ +; if (--_tx_thread_system_state[core]) +; { +; + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + ADD r3, r3, r12 ; Build array offset + LDR r2, [r3, #0] ; Pickup system state + SUB r2, r2, #1 ; Decrement the counter + STR r2, [r3, #0] ; Store the counter + CMP r2, #0 ; Was this the first interrupt? + BEQ __tx_thread_not_nested_restore ; If so, not a nested restore +; +; /* Interrupts are nested. */ +; +; /* Just recover the saved registers and return to the point of +; interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +__tx_thread_not_nested_restore +; +; /* Determine if a thread was interrupted and no preemption is required. */ +; else if (((_tx_thread_current_ptr[core]) && (_tx_thread_current_ptr[core] == _tx_thread_execute_ptr[core]) +; || (_tx_thread_preempt_disable)) +; { +; + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + ADD r1, r1, r12 ; Build index to this core's current thread ptr + LDR r0, [r1, #0] ; Pickup actual current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_restore ; Yes, idle system was interrupted + + LDR r3, =_tx_thread_smp_protection ; Get address of protection structure + LDR r2, [r3, #8] ; Pickup owning core + CMP r2, r10 ; Is the owning core the same as the protected core? + BNE __tx_thread_skip_preempt_check ; No, skip the preempt disable check since this is only valid for the owning core + + LDR r3, =_tx_thread_preempt_disable ; Pickup preempt disable address + LDR r2, [r3, #0] ; Pickup actual preempt disable flag + CMP r2, #0 ; Is it set? + BNE __tx_thread_no_preempt_restore ; Yes, don't preempt this thread +__tx_thread_skip_preempt_check + + LDR r3, =_tx_thread_execute_ptr ; Pickup address of execute thread ptr + ADD r3, r3, r12 ; Build index to this core's execute thread ptr + LDR r2, [r3, #0] ; Pickup actual execute thread pointer + CMP r0, r2 ; Is the same thread highest priority? + BNE __tx_thread_preempt_restore ; No, preemption needs to happen +; +; +__tx_thread_no_preempt_restore +; +; /* Restore interrupted thread or ISR. */ +; +; /* Pickup the saved stack pointer. */ +; tmp_ptr = _tx_thread_current_ptr[core] -> tx_thread_stack_ptr; +; +; /* Recover the saved context and return to the point of interrupt. */ +; + LDMIA sp!, {r0, r10, r12, lr} ; Recover SPSR, POI, and scratch regs + MSR SPSR_cxsf, r0 ; Put SPSR back + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOVS pc, lr ; Return to point of interrupt +; +; } +; else +; { +; +__tx_thread_preempt_restore +; +; /* Was the thread being preempted waiting for the lock? */ +; if (_tx_thread_smp_protect_wait_counts[this_core] != 0) +; { +; + LDR r1, =_tx_thread_smp_protect_wait_counts ; Load waiting count list + LDR r2, [r1, r10, LSL #2] ; Load waiting value for this core + CMP r2, #0 + BEQ _nobody_waiting_for_lock ; Is the core waiting for the lock? +; +; /* Do we not have the lock? This means the ISR never got the inter-core lock. */ +; if (_tx_thread_smp_protection.tx_thread_smp_protect_owned != this_core) +; { +; + LDR r1, =_tx_thread_smp_protection ; Load address of protection structure + LDR r2, [r1, #8] ; Pickup the owning core + CMP r10, r2 ; Compare our core to the owning core + BEQ _this_core_has_lock ; Do we have the lock? +; +; /* We don't have the lock. This core should be in the list. Remove it. */ +; _tx_thread_smp_protect_wait_list_remove(this_core); +; + MOV r0, r10 ; Move the core ID to r0 for the macro +macro_call0 _tx_thread_smp_protect_wait_list_remove ; Call macro to remove core from the list + B _nobody_waiting_for_lock ; Leave +; +; } +; else +; { +; /* We have the lock. This means the ISR got the inter-core lock, but +; never released it because it saw that there was someone waiting. +; Note this core is not in the list. */ +; +_this_core_has_lock +; +; /* We're no longer waiting. Note that this should be zero since this happens during thread preemption. */ +; _tx_thread_smp_protect_wait_counts[core]--; +; + LDR r1, =_tx_thread_smp_protect_wait_counts ; Load waiting count list + LDR r2, [r1, r10, LSL #2] ; Load waiting value for this core + SUB r2, r2, #1 ; Decrement waiting value. Should be zero now + STR r2, [r1, r10, LSL #2] ; Store new waiting value +; +; /* Now release the inter-core lock. */ +; +; /* Set protected core as invalid. */ +; _tx_thread_smp_protection.tx_thread_smp_protect_core = 0xFFFFFFFF; +; + LDR r1, =_tx_thread_smp_protection ; Load address of protection structure + MOV r2, #0xFFFFFFFF ; Build invalid value + STR r2, [r1, #8] ; Mark the protected core as invalid + DMB ; Ensure that accesses to shared resource have completed +; +; /* Release protection. */ +; _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 0; +; + MOV r2, #0 ; Build release protection value + STR r2, [r1, #0] ; Release the protection + DSB ISH ; To ensure update of the protection occurs before other CPUs awake +; +; /* Wake up waiting processors. Note interrupts are already enabled. */ +; + IF :DEF:TX_ENABLE_WFE + SEV ; Send event to other CPUs + ENDIF +; +; } +; } +; + +_nobody_waiting_for_lock + + LDMIA sp!, {r3, r10, r12, lr} ; Recover temporarily saved registers + MOV r1, lr ; Save lr (point of interrupt) + MOV r2, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r2 ; Enter SVC mode + STR r1, [sp, #-4]! ; Save point of interrupt + STMDB sp!, {r4-r12, lr} ; Save upper half of registers + MOV r4, r3 ; Save SPSR in r4 + MOV r2, #IRQ_MODE ; Build IRQ mode CPSR + MSR CPSR_c, r2 ; Enter IRQ mode + LDMIA sp!, {r0-r3} ; Recover r0-r3 + MOV r5, #SVC_MODE ; Build SVC mode CPSR + MSR CPSR_c, r5 ; Enter SVC mode + STMDB sp!, {r0-r3} ; Save r0-r3 on thread's stack + + MRC p15, 0, r10, c0, c0, 5 ; Read CPU ID register + AND r10, r10, #0x03 ; Mask off, leaving the CPU ID field + LSL r12, r10, #2 ; Build offset to array indexes + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + ADD r1, r1, r12 ; Build index to current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + + IF {TARGET_FPU_VFP} = {TRUE} + LDR r2, [r0, #160] ; Pickup the VFP enabled flag + CMP r2, #0 ; Is the VFP enabled? + BEQ _tx_skip_irq_vfp_save ; No, skip VFP IRQ save + VMRS r2, FPSCR ; Pickup the FPSCR + STR r2, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D0-D15} ; Save D0-D15 +_tx_skip_irq_vfp_save + ENDIF + + MOV r3, #1 ; Build interrupt stack type + STMDB sp!, {r3, r4} ; Save interrupt stack type and SPSR + STR sp, [r0, #8] ; Save stack pointer in thread control + ; block +; +; /* Save the remaining time-slice and disable it. */ +; if (_tx_timer_time_slice[core]) +; { +; + LDR r3, =_tx_timer_interrupt_active ; Pickup timer interrupt active flag's address +_tx_wait_for_timer_to_finish + LDR r2, [r3, #0] ; Pickup timer interrupt active flag + CMP r2, #0 ; Is the timer interrupt active? + BNE _tx_wait_for_timer_to_finish ; If timer interrupt is active, wait until it completes + + LDR r3, =_tx_timer_time_slice ; Pickup time-slice variable address + ADD r3, r3, r12 ; Build index to core's time slice + LDR r2, [r3, #0] ; Pickup time-slice + CMP r2, #0 ; Is it active? + BEQ __tx_thread_dont_save_ts ; No, don't save it +; +; _tx_thread_current_ptr[core] -> tx_thread_time_slice = _tx_timer_time_slice[core]; +; _tx_timer_time_slice[core] = 0; +; + STR r2, [r0, #24] ; Save thread's time-slice + MOV r2, #0 ; Clear value + STR r2, [r3, #0] ; Disable global time-slice flag +; +; } +__tx_thread_dont_save_ts +; +; +; /* Clear the current task pointer. */ +; _tx_thread_current_ptr[core] = TX_NULL; +; + MOV r2, #0 ; NULL value + STR r2, [r1, #0] ; Clear current thread pointer +; +; /* Set bit indicating this thread is ready for execution. */ +; + LDR r2, [r0, #152] ; Pickup the ready bit + ORR r2, r2, #0x8000 ; Set ready bit (bit 15) + STR r2, [r0, #152] ; Make this thread ready for executing again + DMB ; Ensure that accesses to shared resource have completed +; +; /* Return to the scheduler. */ +; _tx_thread_schedule(); +; + B _tx_thread_schedule ; Return to scheduler +; } +; +__tx_thread_idle_system_restore +; +; /* Just return back to the scheduler! */ +; + MOV r3, #SVC_MODE ; Build SVC mode with interrupts disabled + MSR CPSR_c, r3 ; Change to SVC mode + B _tx_thread_schedule ; Return to scheduler +;} +; + END + diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_context_save.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_context_save.s new file mode 100644 index 00000000..03cf7557 --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_context_save.s @@ -0,0 +1,203 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IMPORT __tx_irq_processing_return + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save SMP/Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + EXPORT _tx_thread_context_save +_tx_thread_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state[core]++) +; { +; + STMDB sp!, {r0-r3} ; Save some working registers +; +; /* Save the rest of the scratch registers on the stack and return to the +; calling ISR. */ +; + MRS r0, SPSR ; Pickup saved SPSR + SUB lr, lr, #4 ; Adjust point of interrupt + STMDB sp!, {r0, r10, r12, lr} ; Store other registers +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable FIQ interrupts + ENDIF +; +; /* Pickup the CPU ID. */ +; + MRC p15, 0, r10, c0, c0, 5 ; Read CPU ID register + AND r10, r10, #0x03 ; Mask off, leaving the CPU ID field + LSL r12, r10, #2 ; Build offset to array indexes +; + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + ADD r3, r3, r12 ; Build index into the system state array + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {r12, lr} ; Save ISR lr & r12 + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {r12, lr} ; Recover ISR lr & r12 + ENDIF + + B __tx_irq_processing_return ; Continue IRQ processing +; +__tx_thread_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr[core]) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + ADD r1, r1, r12 ; Build index into current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + ; scheduling loop - nothing needs saving! +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr; +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {r12, lr} ; Save ISR lr & r12 + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {r12, lr} ; Recover ISR lr & r12 + ENDIF + + B __tx_irq_processing_return ; Continue IRQ processing +; +; } +; else +; { +; +__tx_thread_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; processing. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {r12, lr} ; Save ISR lr & r12 + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {r12, lr} ; Recover ISR lr & r12 + ENDIF + + ADD sp, sp, #32 ; Recover saved registers + B __tx_irq_processing_return ; Continue IRQ processing +; +; } +;} +; + END + diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_interrupt_control.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..e6c4ff26 --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_interrupt_control.s @@ -0,0 +1,102 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT +INT_MASK EQU 0xC0 ; Interrupt bit mask + ELSE +INT_MASK EQU 0x80 ; Interrupt bit mask + ENDIF +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control SMP/Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + EXPORT _tx_thread_interrupt_control +_tx_thread_interrupt_control +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r3, CPSR ; Pickup current CPSR + BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits + ORR r1, r1, r0 ; Or-in new interrupt lockout bits +; +; /* Apply the new interrupt posture. */ +; + MSR CPSR_c, r1 ; Setup new CPSR + AND r0, r3, #INT_MASK ; Return previous interrupt mask + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +;} +; + END + diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_interrupt_disable.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_interrupt_disable.s new file mode 100644 index 00000000..e6270b4a --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_interrupt_disable.s @@ -0,0 +1,95 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable SMP/Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(void) +;{ + EXPORT _tx_thread_interrupt_disable +_tx_thread_interrupt_disable +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r0, CPSR ; Pickup current CPSR +; +; /* Mask interrupts. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ + ELSE + CPSID i ; Disable IRQ + ENDIF + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +;} +; + END + diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_interrupt_restore.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_interrupt_restore.s new file mode 100644 index 00000000..bcf70846 --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_interrupt_restore.s @@ -0,0 +1,87 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore SMP/Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for restoring interrupts to the state */ +;/* returned by a previous _tx_thread_interrupt_disable call. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_restore(UINT old_posture) +;{ + EXPORT _tx_thread_interrupt_restore +_tx_thread_interrupt_restore +; +; /* Apply the new interrupt posture. */ +; + MSR CPSR_c, r0 ; Setup new CPSR + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +;} +; + END + diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_irq_nesting_end.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_irq_nesting_end.s new file mode 100644 index 00000000..792f26be --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_irq_nesting_end.s @@ -0,0 +1,110 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT +DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts + ELSE +DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts + ENDIF +MODE_MASK EQU 0x1F ; Mode mask +IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_end SMP/Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_irq_nesting_start has been called and switches the IRQ */ +;/* processing from system mode back to IRQ mode prior to the ISR */ +;/* calling _tx_thread_context_restore. Note that this function */ +;/* assumes the system stack pointer is in the same position after */ +;/* nesting start function was called. */ +;/* */ +;/* This function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts disabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_irq_nesting_end(VOID) +;{ + EXPORT _tx_thread_irq_nesting_end +_tx_thread_irq_nesting_end + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + ORR r0, r0, #DISABLE_INTS ; Build disable interrupt value + MSR CPSR_c, r0 ; Disable interrupts + LDMIA sp!, {lr, r1} ; Pickup saved lr (and r1 throw-away for + ; 8-byte alignment logic) + BIC r0, r0, #MODE_MASK ; Clear mode bits + ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR + MSR CPSR_c, r0 ; Re-enter IRQ mode + IF {INTER} = {TRUE} + BX r3 ; Return to caller + ELSE + MOV pc, r3 ; Return to caller + ENDIF +;} + END + diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_irq_nesting_start.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_irq_nesting_start.s new file mode 100644 index 00000000..25e573de --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_irq_nesting_start.s @@ -0,0 +1,104 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +IRQ_DISABLE EQU 0x80 ; IRQ disable bit +MODE_MASK EQU 0x1F ; Mode mask +SYS_MODE_BITS EQU 0x1F ; System mode bits +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_irq_nesting_start SMP/Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is called by the application from IRQ mode after */ +;/* _tx_thread_context_save has been called and switches the IRQ */ +;/* processing to the system mode so nested IRQ interrupt processing */ +;/* is possible (system mode has its own "lr" register). Note that */ +;/* this function assumes that the system mode stack pointer was setup */ +;/* during low-level initialization (tx_initialize_low_level.s). */ +;/* */ +;/* This function returns with IRQ interrupts enabled. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_irq_nesting_start(VOID) +;{ + EXPORT _tx_thread_irq_nesting_start +_tx_thread_irq_nesting_start + MOV r3,lr ; Save ISR return address + MRS r0, CPSR ; Pickup the CPSR + BIC r0, r0, #MODE_MASK ; Clear the mode bits + ORR r0, r0, #SYS_MODE_BITS ; Build system mode CPSR + MSR CPSR_c, r0 ; Enter system mode + STMDB sp!, {lr, r1} ; Push the system mode lr on the system mode stack + ; and push r1 just to keep 8-byte alignment + BIC r0, r0, #IRQ_DISABLE ; Build enable IRQ CPSR + MSR CPSR_c, r0 ; Enter system mode + IF {INTER} = {TRUE} + BX r3 ; Return to caller + ELSE + MOV pc, r3 ; Return to caller + ENDIF +;} +; + END + diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_schedule.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_schedule.s new file mode 100644 index 00000000..75079b73 --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_schedule.s @@ -0,0 +1,314 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IMPORT _tx_thread_execute_ptr + IMPORT _tx_thread_current_ptr + IMPORT _tx_timer_time_slice + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_thread_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_schedule SMP/Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_schedule(VOID) +;{ + EXPORT _tx_thread_schedule +_tx_thread_schedule +; +; /* Enable interrupts. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSIE if ; Enable IRQ and FIQ interrupts + ELSE + CPSIE i ; Enable IRQ interrupts + ENDIF +; +; /* Pickup the CPU ID. */ +; + MRC p15, 0, r10, c0, c0, 5 ; Read CPU ID register + AND r10, r10, #0x03 ; Mask off, leaving the CPU ID field + LSL r12, r10, #2 ; Build offset to array indexes + + LDR r1, =_tx_thread_execute_ptr ; Address of thread execute ptr + ADD r1, r1, r12 ; Build offset to execute ptr for this core +; +; /* Lockout interrupts transfer control to it. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF +; +; /* Wait for a thread to execute. */ +; do +; { +; +; + LDR r0, [r1, #0] ; Pickup next thread to execute + CMP r0, #0 ; Is it NULL? + BEQ _tx_thread_schedule ; If so, keep looking for a thread +; +; } +; while(_tx_thread_execute_ptr[core] == TX_NULL); +; +; /* Get the lock for accessing the thread's ready bit. */ +; + MOV r2, #172 ; Build offset to the lock + ADD r2, r0, r2 ; Get the address to the lock + LDREX r3, [r2] ; Pickup the lock value + CMP r3, #0 ; Check if it's available + BNE _tx_thread_schedule ; No, lock not available + MOV r3, #1 ; Build the lock set value + STREX r4, r3, [r2] ; Try to get the lock + CMP r4, #0 ; Check if we got the lock + BNE _tx_thread_schedule ; No, another core got it first + DMB ; Ensure write to lock completes +; +; /* Now make sure the thread's ready bit is set. */ +; + LDR r3, [r0, #152] ; Pickup the thread ready bit + AND r4, r3, #0x8000 ; Isolate the ready bit + CMP r4, #0 ; Is it set? + BNE _tx_thread_ready_for_execution ; Yes, schedule the thread +; +; /* The ready bit isn't set. Release the lock and jump back to the scheduler. */ +; + MOV r3, #0 ; Build clear value + STR r3, [r2] ; Release the lock + DMB ; Ensure write to lock completes + B _tx_thread_schedule ; Jump back to the scheduler +; +_tx_thread_ready_for_execution +; +; /* We have a thread to execute. */ +; +; /* Clear the ready bit and release the lock. */ +; + BIC r3, r3, #0x8000 ; Clear ready bit + STR r3, [r0, #152] ; Store it back in the thread control block + DMB + MOV r3, #0 ; Build clear value for the lock + STR r3, [r2] ; Release the lock + DMB +; +; /* Setup the current thread pointer. */ +; _tx_thread_current_ptr[core] = _tx_thread_execute_ptr[core]; +; + LDR r2, =_tx_thread_current_ptr ; Pickup address of current thread + ADD r2, r2, r12 ; Build index into the current thread array + STR r0, [r2, #0] ; Setup current thread pointer +; +; /* In the time between reading the execute pointer and assigning +; it to the current pointer, the execute pointer was changed by +; some external code. If the current pointer was still null when +; the external code checked if a core preempt was necessary, then +; it wouldn't have done it and a preemption will be missed. To +; handle this, undo some things and jump back to the scheduler so +; it can schedule the new thread. */ +; + LDR r1, [r1, #0] ; Reload the execute pointer + CMP r0, r1 ; Did it change? + BEQ _execute_pointer_did_not_change ; If not, skip handling + + MOV r1, #0 ; Build clear value + STR r1, [r2, #0] ; Clear current thread pointer + + LDR r1, [r0, #152] ; Pickup the ready bit + ORR r1, r1, #0x8000 ; Set ready bit (bit 15) + STR r1, [r0, #152] ; Make this thread ready for executing again + DMB ; Ensure that accesses to shared resource have completed + + B _tx_thread_schedule ; Jump back to the scheduler to schedule the new thread + +_execute_pointer_did_not_change +; +; /* Increment the run count for this thread. */ +; _tx_thread_current_ptr[core] -> tx_thread_run_count++; +; + LDR r2, [r0, #4] ; Pickup run counter + LDR r3, [r0, #24] ; Pickup time-slice for this thread + ADD r2, r2, #1 ; Increment thread run-counter + STR r2, [r0, #4] ; Store the new run counter +; +; /* Setup time-slice, if present. */ +; _tx_timer_time_slice[core] = _tx_thread_current_ptr[core] -> tx_thread_time_slice; +; + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + ; variable + ADD r2, r2, r12 ; Build index into the time-slice array + LDR sp, [r0, #8] ; Switch stack pointers + STR r3, [r2, #0] ; Setup time-slice +; +; /* Switch to the thread's stack. */ +; sp = _tx_thread_execute_ptr[core] -> tx_thread_stack_ptr; +; + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread entry function to indicate the thread is executing. */ +; + MOV r5, r0 ; Save r0 + BL _tx_execution_thread_enter ; Call the thread execution enter function + MOV r0, r5 ; Restore r0 + ENDIF +; +; /* Determine if an interrupt frame or a synchronous task suspension frame +; is present. */ +; + LDMIA sp!, {r4, r5} ; Pickup the stack type and saved CPSR + CMP r4, #0 ; Check for synchronous context switch + BEQ _tx_solicited_return + MSR SPSR_cxsf, r5 ; Setup SPSR for return + IF {TARGET_FPU_VFP} = {TRUE} + LDR r1, [r0, #160] ; Pickup the VFP enabled flag + CMP r1, #0 ; Is the VFP enabled? + BEQ _tx_skip_interrupt_vfp_restore ; No, skip VFP interrupt restore + VLDMIA sp!, {D0-D15} ; Recover D0-D15 + VLDMIA sp!, {D16-D31} ; Recover D16-D31 + LDR r4, [sp], #4 ; Pickup FPSCR + VMSR FPSCR, r4 ; Restore FPSCR +_tx_skip_interrupt_vfp_restore + ENDIF + LDMIA sp!, {r0-r12, lr, pc}^ ; Return to point of thread interrupt + +_tx_solicited_return + IF {TARGET_FPU_VFP} = {TRUE} + MSR CPSR_cxsf, r5 ; Recover CPSR + LDR r1, [r0, #160] ; Pickup the VFP enabled flag + CMP r1, #0 ; Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_restore ; No, skip VFP solicited restore + VLDMIA sp!, {D8-D15} ; Recover D8-D15 + VLDMIA sp!, {D16-D31} ; Recover D16-D31 + LDR r4, [sp], #4 ; Pickup FPSCR + VMSR FPSCR, r4 ; Restore FPSCR +_tx_skip_solicited_vfp_restore + ENDIF + MSR CPSR_cxsf, r5 ; Recover CPSR + LDMIA sp!, {r4-r11, lr} ; Return to thread synchronously + BX lr ; Return to caller +; +;} +; + + IF {TARGET_FPU_VFP} = {TRUE} + EXPORT tx_thread_vfp_enable +tx_thread_vfp_enable + MRS r2, CPSR ; Pickup the CPSR + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF + MRC p15, 0, r1, c0, c0, 5 ; Read CPU ID register + AND r1, r1, #0x03 ; Mask off, leaving the CPU ID field + LSL r1, r1, #2 ; Build offset to array indexes + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + ADD r0, r0, r1 ; Build index into the current thread array + LDR r1, [r0] ; Pickup current thread pointer + CMP r1, #0 ; Check for NULL thread pointer + BEQ __tx_no_thread_to_enable ; If NULL, skip VFP enable + MOV r0, #1 ; Build enable value + STR r0, [r1, #160] ; Set the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_enable + MSR CPSR_cxsf, r2 ; Recover CPSR + BX LR ; Return to caller + + EXPORT tx_thread_vfp_disable +tx_thread_vfp_disable + MRS r2, CPSR ; Pickup the CPSR + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF + MRC p15, 0, r1, c0, c0, 5 ; Read CPU ID register + AND r1, r1, #0x03 ; Mask off, leaving the CPU ID field + LSL r1, r1, #2 ; Build offset to array indexes + LDR r0, =_tx_thread_current_ptr ; Build current thread pointer address + ADD r0, r0, r1 ; Build index into the current thread array + LDR r1, [r0] ; Pickup current thread pointer + CMP r1, #0 ; Check for NULL thread pointer + BEQ __tx_no_thread_to_disable ; If NULL, skip VFP disable + MOV r0, #0 ; Build disable value + STR r0, [r1, #160] ; Clear the VFP enable flag (tx_thread_vfp_enable field in TX_THREAD) +__tx_no_thread_to_disable + MSR CPSR_cxsf, r2 ; Recover CPSR + BX LR ; Return to caller + ENDIF +; +;} +; + END + diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_core_get.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_core_get.s new file mode 100644 index 00000000..fb19d750 --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_core_get.s @@ -0,0 +1,85 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +;#define TX_THREAD_SMP_SOURCE_CODE +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" */ +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_core_get SMP/Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function gets the currently running core number and returns it.*/ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* Core ID */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ + EXPORT _tx_thread_smp_core_get +_tx_thread_smp_core_get + MRC p15, 0, r0, c0, c0, 5 ; Read CPU ID register + AND r0, r0, #0x03 ; Mask off, leaving the CPU ID field + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF + + END + diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_core_preempt.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_core_preempt.s new file mode 100644 index 00000000..df3044c2 --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_core_preempt.s @@ -0,0 +1,101 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +;#define TX_THREAD_SMP_SOURCE_CODE +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" */ +; +; + IMPORT send_sgi + + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_core_preempt SMP/Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function preempts the specified core in situations where the */ +;/* thread corresponding to this core is no longer ready or when the */ +;/* core must be used for a higher-priority thread. If the specified is */ +;/* the current core, this processing is skipped since the will give up */ +;/* control subsequently on its own. */ +;/* */ +;/* INPUT */ +;/* */ +;/* core The core to preempt */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ + EXPORT _tx_thread_smp_core_preempt +_tx_thread_smp_core_preempt + + STMDB sp!, {lr, r4} ; Save the lr and r4 register on the stack +; +; /* Place call to send inter-processor interrupt here! */ +; + DSB ; + MOV r1, #1 ; Build parameter list + LSL r1, r1, r0 ; + MOV r0, #0 ; + MOV r2, #0 ; + BL send_sgi ; Make call to send inter-processor interrupt + + LDMIA sp!, {lr, r4} ; Recover lr register and r4 + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF + + END + diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_current_state_get.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_current_state_get.s new file mode 100644 index 00000000..bd11797a --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_current_state_get.s @@ -0,0 +1,103 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +;#define TX_THREAD_SMP_SOURCE_CODE +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" */ +; +; + IMPORT _tx_thread_system_state + + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_current_state_get SMP/Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is gets the current state of the calling core. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ + EXPORT _tx_thread_smp_current_state_get +_tx_thread_smp_current_state_get + + MRS r3, CPSR ; Pickup current CPSR + + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF +; +; /* Pickup the CPU ID. */ +; + MRC p15, 0, r2, c0, c0, 5 ; Read CPU ID register + AND r2, r2, #0x03 ; Mask off, leaving the CPU ID field + LSL r2, r2, #2 ; Build offset to array indexes + + LDR r1, =_tx_thread_system_state ; Pickup start of the current state array + ADD r1, r1, r2 ; Build index into the current state array + LDR r0, [r1] ; Pickup state for this core + MSR CPSR_c, r3 ; Restore CPSR + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF + + END + diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_current_thread_get.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_current_thread_get.s new file mode 100644 index 00000000..8c93e7ed --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_current_thread_get.s @@ -0,0 +1,103 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +;#define TX_THREAD_SMP_SOURCE_CODE +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" */ +; +; + IMPORT _tx_thread_current_ptr + + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_current_thread_get SMP/Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is gets the current thread of the calling core. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ + EXPORT _tx_thread_smp_current_thread_get +_tx_thread_smp_current_thread_get + + MRS r3, CPSR ; Pickup current CPSR + + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF +; +; /* Pickup the CPU ID. */ +; + MRC p15, 0, r2, c0, c0, 5 ; Read CPU ID register + AND r2, r2, #0x03 ; Mask off, leaving the CPU ID field + LSL r2, r2, #2 ; Build offset to array indexes + + LDR r1, =_tx_thread_current_ptr ; Pickup start of the current thread array + ADD r1, r1, r2 ; Build index into the current thread array + LDR r0, [r1] ; Pickup current thread for this core + MSR CPSR_c, r3 ; Restore CPSR + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF + + END + diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_initialize_wait.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_initialize_wait.s new file mode 100644 index 00000000..75a09008 --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_initialize_wait.s @@ -0,0 +1,140 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +;#define TX_THREAD_SMP_SOURCE_CODE +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" */ +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_smp_release_cores_flag + IMPORT _tx_thread_schedule + + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_initialize_wait SMP/Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is the place where additional cores wait until */ +;/* initialization is complete before they enter the thread scheduling */ +;/* loop. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Hardware */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ + EXPORT _tx_thread_smp_initialize_wait +_tx_thread_smp_initialize_wait + +; /* Lockout interrupts. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF +; +; /* Pickup the CPU ID. */ +; + MRC p15, 0, r10, c0, c0, 5 ; Read CPU ID register + AND r10, r10, #0x03 ; Mask off, leaving the CPU ID field + LSL r10, r10, #2 ; Build offset to array indexes +; +; /* Make sure the system state for this core is TX_INITIALIZE_IN_PROGRESS before we check the release +; flag. */ +; + LDR r3, =_tx_thread_system_state ; Build address of system state variable + ADD r3, r3, r10 ; Build index into the system state array + LDR r2, =0xF0F0F0F0 ; Build TX_INITIALIZE_IN_PROGRESS flag +wait_for_initialize + LDR r1, [r3] ; Pickup system state + CMP r1, r2 ; Has initialization completed? + BNE wait_for_initialize ; If different, wait here! +; +; /* Pickup the release cores flag. */ +; + LDR r2, =_tx_thread_smp_release_cores_flag ; Build address of release cores flag + +wait_for_release + LDR r3, [r2] ; Pickup the flag + CMP r3, #0 ; Is it set? + BEQ wait_for_release ; Wait for the flag to be set +; +; /* Core 0 has released this core. */ +; +; /* Clear this core's system state variable. */ +; + LDR r3, =_tx_thread_system_state ; Build address of system state variable + ADD r3, r3, r10 ; Build index into the system state array + MOV r0, #0 ; Build clear value + STR r0, [r3] ; Clear this core's entry in the system state array +; +; /* Now wait for core 0 to finish it's initialization. */ +; + LDR r3, =_tx_thread_system_state ; Build address of system state variable of logical 0 + +core_0_wait_loop + LDR r2, [r3] ; Pickup system state for core 0 + CMP r2, #0 ; Is it 0? + BNE core_0_wait_loop ; No, keep waiting for core 0 to finish its initialization +; +; /* Initialize is complete, enter the scheduling loop! */ +; + B _tx_thread_schedule ; Enter scheduling loop for this core! + + END + diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_low_level_initialize.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_low_level_initialize.s new file mode 100644 index 00000000..0d76b8e0 --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_low_level_initialize.s @@ -0,0 +1,84 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +;#define TX_THREAD_SMP_SOURCE_CODE +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" */ +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_low_level_initialize SMP/Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function performs low-level initialization of the booting */ +;/* core. */ +;/* */ +;/* INPUT */ +;/* */ +;/* number_of_cores Number of cores */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_high_level ThreadX high-level init */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ + EXPORT _tx_thread_smp_low_level_initialize +_tx_thread_smp_low_level_initialize + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF + + END + diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_protect.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_protect.s new file mode 100644 index 00000000..d479faba --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_protect.s @@ -0,0 +1,372 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +;#define TX_THREAD_SMP_SOURCE_CODE +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + +;/* Include macros for modifying the wait list. */ +#include "tx_thread_smp_protection_wait_list_macros.h" + + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_smp_protection + IMPORT _tx_thread_smp_protect_wait_counts + IMPORT _tx_thread_smp_protect_wait_list + IMPORT _tx_thread_smp_protect_wait_list_lock_protect_in_force + IMPORT _tx_thread_smp_protect_wait_list_head + IMPORT _tx_thread_smp_protect_wait_list_tail + IMPORT _tx_thread_smp_protect_wait_list_size + + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_protect SMP/Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function gets protection for running inside the ThreadX */ +;/* source. This is acomplished by a combination of a test-and-set */ +;/* flag and periodically disabling interrupts. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* Previous Status Register */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ + EXPORT _tx_thread_smp_protect +_tx_thread_smp_protect +;VOID _tx_thread_smp_protect(VOID) +;{ +; + PUSH {r4-r6} ; Save registers we'll be using +; +; /* Disable interrupts so we don't get preempted. */ +; + MRS r0, CPSR ; Pickup current CPSR + + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF +; +; /* Do we already have protection? */ +; if (this_core == _tx_thread_smp_protection.tx_thread_smp_protect_core) +; { +; + MRC p15, 0, r1, c0, c0, 5 ; Read CPU ID register + AND r1, r1, #0x03 ; Mask off, leaving the CPU ID field + LDR r2, =_tx_thread_smp_protection ; Build address to protection structure + LDR r3, [r2, #8] ; Pickup the owning core + CMP r1, r3 ; Is it not this core? + BNE _protection_not_owned ; No, the protection is not already owned +; +; /* We already have protection. */ +; +; /* Increment the protection count. */ +; _tx_thread_smp_protection.tx_thread_smp_protect_count++; +; + LDR r3, [r2, #12] ; Pickup ownership count + ADD r3, r3, #1 ; Increment ownership count + STR r3, [r2, #12] ; Store ownership count + DMB + + B _return + +_protection_not_owned +; +; /* Is the lock available? */ +; if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0) +; { +; + LDREX r3, [r2, #0] ; Pickup the protection flag + CMP r3, #0 + BNE _start_waiting ; No, protection not available +; +; /* Is the list empty? */ +; if (_tx_thread_smp_protect_wait_list_head == _tx_thread_smp_protect_wait_list_tail) +; { +; + LDR r3, =_tx_thread_smp_protect_wait_list_head + LDR r3, [r3] + LDR r4, =_tx_thread_smp_protect_wait_list_tail + LDR r4, [r4] + CMP r3, r4 + BNE _list_not_empty +; +; /* Try to get the lock. */ +; if (write_exclusive(&_tx_thread_smp_protection.tx_thread_smp_protect_in_force, 1) == SUCCESS) +; { +; + MOV r3, #1 ; Build lock value + STREX r4, r3, [r2, #0] ; Attempt to get the protection + CMP r4, #0 + BNE _start_waiting ; Did it fail? +; +; /* We got the lock! */ +; _tx_thread_smp_protect_lock_got(); +; + DMB ; Ensure write to protection finishes +macro_call0 _tx_thread_smp_protect_lock_got ; Call the lock got function + + B _return + +_list_not_empty +; +; /* Are we at the front of the list? */ +; if (this_core == _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head]) +; { +; + LDR r3, =_tx_thread_smp_protect_wait_list_head ; Get the address of the head + LDR r3, [r3] ; Get the value of the head + LDR r4, =_tx_thread_smp_protect_wait_list ; Get the address of the list + LDR r4, [r4, r3, LSL #2] ; Get the value at the head index + + CMP r1, r4 + BNE _start_waiting +; +; /* Is the lock still available? */ +; if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0) +; { +; + LDR r3, [r2, #0] ; Pickup the protection flag + CMP r3, #0 + BNE _start_waiting ; No, protection not available +; +; /* Get the lock. */ +; _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1; +; + MOV r3, #1 ; Build lock value + STR r3, [r2, #0] ; Store lock value + DMB ; +; +; /* Got the lock. */ +; _tx_thread_smp_protect_lock_got(); +; +macro_call1 _tx_thread_smp_protect_lock_got +; +; /* Remove this core from the wait list. */ +; _tx_thread_smp_protect_remove_from_front_of_list(); +; +macro_call2 _tx_thread_smp_protect_remove_from_front_of_list + + B _return + +_start_waiting +; +; /* For one reason or another, we didn't get the lock. */ +; +; /* Increment wait count. */ +; _tx_thread_smp_protect_wait_counts[this_core]++; +; + LDR r3, =_tx_thread_smp_protect_wait_counts ; Load wait list counts + LDR r4, [r3, r1, LSL #2] ; Load waiting value for this core + ADD r4, r4, #1 ; Increment wait value + STR r4, [r3, r1, LSL #2] ; Store new wait value +; +; /* Have we not added ourselves to the list yet? */ +; if (_tx_thread_smp_protect_wait_counts[this_core] == 1) +; { +; + CMP r4, #1 + BNE _already_in_list0 ; Is this core already waiting? +; +; /* Add ourselves to the list. */ +; _tx_thread_smp_protect_wait_list_add(this_core); +; +macro_call3 _tx_thread_smp_protect_wait_list_add ; Call macro to add ourselves to the list +; +; } +; +_already_in_list0 +; +; /* Restore interrupts. */ +; + MSR CPSR_c, r0 ; Restore CPSR + IF :DEF:TX_ENABLE_WFE + WFE ; Go into standby + ENDIF +; +; /* We do this until we have the lock. */ +; while (1) +; { +; +_try_to_get_lock +; +; /* Disable interrupts so we don't get preempted. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF + + MRC p15, 0, r1, c0, c0, 5 ; Read CPU ID register + AND r1, r1, #0x03 ; Mask off, leaving the CPU ID field +; +; /* Do we already have protection? */ +; if (this_core == _tx_thread_smp_protection.tx_thread_smp_protect_core) +; { +; + LDR r3, [r2, #8] ; Pickup the owning core + CMP r3, r1 ; Is it this core? + BEQ _got_lock_after_waiting ; Yes, the protection is already owned. This means + ; an ISR preempted us and got protection +; +; } +; +; /* Are we at the front of the list? */ +; if (this_core == _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head]) +; { +; + LDR r3, =_tx_thread_smp_protect_wait_list_head ; Get the address of the head + LDR r3, [r3] ; Get the value of the head + LDR r4, =_tx_thread_smp_protect_wait_list ; Get the address of the list + LDR r4, [r4, r3, LSL #2] ; Get the value at the head index + + CMP r1, r4 + BNE _did_not_get_lock +; +; /* Is the lock still available? */ +; if (_tx_thread_smp_protection.tx_thread_smp_protect_in_force == 0) +; { +; + LDR r3, [r2, #0] ; Pickup the protection flag + CMP r3, #0 + BNE _did_not_get_lock ; No, protection not available +; +; /* Get the lock. */ +; _tx_thread_smp_protection.tx_thread_smp_protect_in_force = 1; +; + MOV r3, #1 ; Build lock value + STR r3, [r2, #0] ; Store lock value + DMB ; +; +; /* Got the lock. */ +; _tx_thread_smp_protect_lock_got(); +; +macro_call4 _tx_thread_smp_protect_lock_got +; +; /* Remove this core from the wait list. */ +; _tx_thread_smp_protect_remove_from_front_of_list(); +; +macro_call5 _tx_thread_smp_protect_remove_from_front_of_list + + B _got_lock_after_waiting + +_did_not_get_lock +; +; /* For one reason or another, we didn't get the lock. */ +; +; /* Were we removed from the list? This can happen if we're a thread +; and we got preempted. */ +; if (_tx_thread_smp_protect_wait_counts[this_core] == 0) +; { +; + LDR r3, =_tx_thread_smp_protect_wait_counts ; Load wait list counts + LDR r4, [r3, r1, LSL #2] ; Load waiting value for this core + CMP r4, #0 + BNE _already_in_list1 ; Is this core already in the list? +; +; /* Add ourselves to the list. */ +; _tx_thread_smp_protect_wait_list_add(this_core); +; +macro_call6 _tx_thread_smp_protect_wait_list_add ; Call macro to add ourselves to the list +; +; /* Our waiting count was also reset when we were preempted. Increment it again. */ +; _tx_thread_smp_protect_wait_counts[this_core]++; +; + LDR r3, =_tx_thread_smp_protect_wait_counts ; Load wait list counts + LDR r4, [r3, r1, LSL #2] ; Load waiting value for this core + ADD r4, r4, #1 ; Increment wait value + STR r4, [r3, r1, LSL #2] ; Store new wait value value +; +; } +; +_already_in_list1 +; +; /* Restore interrupts and try again. */ +; + MSR CPSR_c, r0 ; Restore CPSR + IF :DEF:TX_ENABLE_WFE + WFE ; Go into standby + ENDIF + B _try_to_get_lock ; On waking, restart the protection attempt + +_got_lock_after_waiting +; +; /* We're no longer waiting. */ +; _tx_thread_smp_protect_wait_counts[this_core]--; +; + LDR r3, =_tx_thread_smp_protect_wait_counts ; Load waiting list + LDR r4, [r3, r1, LSL #2] ; Load current wait value + SUB r4, r4, #1 ; Decrement wait value + STR r4, [r3, r1, LSL #2] ; Store new wait value value + +; +; /* Restore link register and return. */ +; +_return + + POP {r4-r6} ; Restore registers + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF + + END + diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_protection_wait_list_macros.h b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_protection_wait_list_macros.h new file mode 100644 index 00000000..685b2180 --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_protection_wait_list_macros.h @@ -0,0 +1,315 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ + + MACRO +$label _tx_thread_smp_protect_lock_got +; +; /* Set the currently owned core. */ +; _tx_thread_smp_protection.tx_thread_smp_protect_core = this_core; +; + STR r1, [r2, #8] ; Store this core +; +; /* Increment the protection count. */ +; _tx_thread_smp_protection.tx_thread_smp_protect_count++; +; + LDR r3, [r2, #12] ; Pickup ownership count + ADD r3, r3, #1 ; Increment ownership count + STR r3, [r2, #12] ; Store ownership count + DMB + + IF :DEF:TX_MPCORE_DEBUG_ENABLE + LSL r3, r1, #2 ; Build offset to array indexes + LDR r4, =_tx_thread_current_ptr ; Pickup start of the current thread array + ADD r4, r3, r4 ; Build index into the current thread array + LDR r3, [r4] ; Pickup current thread for this core + STR r3, [r2, #4] ; Save current thread pointer + STR LR, [r2, #16] ; Save caller's return address + STR r0, [r2, #20] ; Save CPSR + ENDIF + + MEND + + MACRO +$label _tx_thread_smp_protect_remove_from_front_of_list +; +; /* Remove ourselves from the list. */ +; _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_head++] = 0xFFFFFFFF; +; + MOV r3, #0xFFFFFFFF ; Build the invalid core value + LDR r4, =_tx_thread_smp_protect_wait_list_head ; Get the address of the head + LDR r5, [r4] ; Get the value of the head + LDR r6, =_tx_thread_smp_protect_wait_list ; Get the address of the list + STR r3, [r6, r5, LSL #2] ; Store the invalid core value + ADD r5, r5, #1 ; Increment the head +; +; /* Did we wrap? */ +; if (_tx_thread_smp_protect_wait_list_head == TX_THREAD_SMP_MAX_CORES + 1) +; { +; + LDR r3, =_tx_thread_smp_protect_wait_list_size ; Load address of core list size + LDR r3, [r3] ; Load the max cores value + CMP r5, r3 ; Compare the head to it + BNE $label._store_new_head ; Are we at the max? +; +; _tx_thread_smp_protect_wait_list_head = 0; +; + EOR r5, r5, r5 ; We're at the max. Set it to zero +; +; } +; +$label._store_new_head + + STR r5, [r4] ; Store the new head +; +; /* We have the lock! */ +; return; +; + MEND + + + MACRO +$label _tx_thread_smp_protect_wait_list_lock_get +;VOID _tx_thread_smp_protect_wait_list_lock_get() +;{ +; /* We do this until we have the lock. */ +; while (1) +; { +; +$label._tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock +; +; /* Is the list lock available? */ +; _tx_thread_smp_protect_wait_list_lock_protect_in_force = load_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force); +; + LDR r1, =_tx_thread_smp_protect_wait_list_lock_protect_in_force + LDREX r2, [r1] ; Pickup the protection flag +; +; if (protect_in_force == 0) +; { +; + CMP r2, #0 + BNE $label._tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock ; No, protection not available +; +; /* Try to get the list. */ +; int status = store_exclusive(&_tx_thread_smp_protect_wait_list_lock_protect_in_force, 1); +; + MOV r2, #1 ; Build lock value + STREX r3, r2, [r1] ; Attempt to get the protection +; +; if (status == SUCCESS) +; + CMP r3, #0 + BNE $label._tx_thread_smp_protect_wait_list_lock_get__try_to_get_lock ; Did it fail? If so, try again. +; +; /* We have the lock! */ +; return; +; + MEND + + + MACRO +$label _tx_thread_smp_protect_wait_list_add +;VOID _tx_thread_smp_protect_wait_list_add(UINT new_core) +;{ +; +; /* We're about to modify the list, so get the list lock. */ +; _tx_thread_smp_protect_wait_list_lock_get(); +; + PUSH {r1-r2} + +$label _tx_thread_smp_protect_wait_list_lock_get + + POP {r1-r2} +; +; /* Add this core. */ +; _tx_thread_smp_protect_wait_list[_tx_thread_smp_protect_wait_list_tail++] = new_core; +; + LDR r3, =_tx_thread_smp_protect_wait_list_tail ; Get the address of the tail + LDR r4, [r3] ; Get the value of tail + LDR r5, =_tx_thread_smp_protect_wait_list ; Get the address of the list + STR r1, [r5, r4, LSL #2] ; Store the new core value + ADD r4, r4, #1 ; Increment the tail +; +; /* Did we wrap? */ +; if (_tx_thread_smp_protect_wait_list_tail == _tx_thread_smp_protect_wait_list_size) +; { +; + LDR r5, =_tx_thread_smp_protect_wait_list_size ; Load max cores address + LDR r5, [r5] ; Load max cores value + CMP r4, r5 ; Compare max cores to tail + BNE $label._tx_thread_smp_protect_wait_list_add__no_wrap ; Did we wrap? +; +; _tx_thread_smp_protect_wait_list_tail = 0; +; + MOV r4, #0 +; +; } +; +$label._tx_thread_smp_protect_wait_list_add__no_wrap + + STR r4, [r3] ; Store the new tail value. +; +; /* Release the list lock. */ +; _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; +; + MOV r3, #0 ; Build lock value + LDR r4, =_tx_thread_smp_protect_wait_list_lock_protect_in_force + STR r3, [r4] ; Store the new value + + MEND + + + MACRO +$label _tx_thread_smp_protect_wait_list_remove +;VOID _tx_thread_smp_protect_wait_list_remove(UINT core) +;{ +; +; /* Get the core index. */ +; UINT core_index; +; for (core_index = 0;; core_index++) +; + EOR r1, r1, r1 ; Clear for 'core_index' + LDR r2, =_tx_thread_smp_protect_wait_list ; Get the address of the list +; +; { +; +$label._tx_thread_smp_protect_wait_list_remove__check_cur_core +; +; /* Is this the core? */ +; if (_tx_thread_smp_protect_wait_list[core_index] == core) +; { +; break; +; + LDR r3, [r2, r1, LSL #2] ; Get the value at the current index + CMP r3, r0 ; Did we find the core? + BEQ $label._tx_thread_smp_protect_wait_list_remove__found_core +; +; } +; + ADD r1, r1, #1 ; Increment cur index + B $label._tx_thread_smp_protect_wait_list_remove__check_cur_core ; Restart the loop +; +; } +; +$label._tx_thread_smp_protect_wait_list_remove__found_core +; +; /* We're about to modify the list. Get the lock. We need the lock because another +; core could be simultaneously adding (a core is simultaneously trying to get +; the inter-core lock) or removing (a core is simultaneously being preempted, +; like what is currently happening). */ +; _tx_thread_smp_protect_wait_list_lock_get(); +; + PUSH {r1} + +$label _tx_thread_smp_protect_wait_list_lock_get + + POP {r1} +; +; /* We remove by shifting. */ +; while (core_index != _tx_thread_smp_protect_wait_list_tail) +; { +; +$label._tx_thread_smp_protect_wait_list_remove__compare_index_to_tail + + LDR r2, =_tx_thread_smp_protect_wait_list_tail ; Load tail address + LDR r2, [r2] ; Load tail value + CMP r1, r2 ; Compare cur index and tail + BEQ $label._tx_thread_smp_protect_wait_list_remove__removed +; +; UINT next_index = core_index + 1; +; + MOV r2, r1 ; Move current index to next index register + ADD r2, r2, #1 ; Add 1 +; +; if (next_index == _tx_thread_smp_protect_wait_list_size) +; { +; + LDR r3, =_tx_thread_smp_protect_wait_list_size + LDR r3, [r3] + CMP r2, r3 + BNE $label._tx_thread_smp_protect_wait_list_remove__next_index_no_wrap +; +; next_index = 0; +; + MOV r2, #0 +; +; } +; +$label._tx_thread_smp_protect_wait_list_remove__next_index_no_wrap +; +; list_cores[core_index] = list_cores[next_index]; +; + LDR r0, =_tx_thread_smp_protect_wait_list ; Get the address of the list + LDR r3, [r0, r2, LSL #2] ; Get the value at the next index + STR r3, [r0, r1, LSL #2] ; Store the value at the current index +; +; core_index = next_index; +; + MOV r1, r2 + + B $label._tx_thread_smp_protect_wait_list_remove__compare_index_to_tail +; +; } +; +$label._tx_thread_smp_protect_wait_list_remove__removed +; +; /* Now update the tail. */ +; if (_tx_thread_smp_protect_wait_list_tail == 0) +; { +; + LDR r0, =_tx_thread_smp_protect_wait_list_tail ; Load tail address + LDR r1, [r0] ; Load tail value + CMP r1, #0 + BNE $label._tx_thread_smp_protect_wait_list_remove__tail_not_zero +; +; _tx_thread_smp_protect_wait_list_tail = _tx_thread_smp_protect_wait_list_size; +; + LDR r2, =_tx_thread_smp_protect_wait_list_size + LDR r1, [r2] +; +; } +; +$label._tx_thread_smp_protect_wait_list_remove__tail_not_zero +; +; _tx_thread_smp_protect_wait_list_tail--; +; + SUB r1, r1, #1 + STR r1, [r0] ; Store new tail value +; +; /* Release the list lock. */ +; _tx_thread_smp_protect_wait_list_lock_protect_in_force = 0; +; + MOV r0, #0 ; Build lock value + LDR r1, =_tx_thread_smp_protect_wait_list_lock_protect_in_force ; Load lock address + STR r0, [r1] ; Store the new value +; +; /* We're no longer waiting. Note that this should be zero since, again, +; this function is only called when a thread preemption is occurring. */ +; _tx_thread_smp_protect_wait_counts[core]--; +; + MRC p15, 0, r0, c0, c0, 5 ; Read CPU ID register + AND r0, r0, #0x03 ; Mask off, leaving the CPU ID field + LDR r1, =_tx_thread_smp_protect_wait_counts ; Load wait list counts + LDR r2, [r1, r0, LSL #2] ; Load waiting value + SUB r2, r2, #1 ; Subtract 1 + STR r2, [r1, r0, LSL #2] ; Store new waiting value + MEND + diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_time_get.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_time_get.s new file mode 100644 index 00000000..9af508f7 --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_time_get.s @@ -0,0 +1,88 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +;#define TX_THREAD_SMP_SOURCE_CODE +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" */ +; +; + + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_time_get SMP/Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function gets the global time value that is used for debug */ +;/* information and event tracing. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* 32-bit time stamp */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ + EXPORT _tx_thread_smp_time_get +_tx_thread_smp_time_get + + MRC p15, 4, r0, c15, c0, 0 ; Read periph base address + LDR r0, [r0, #0x604] ; Read count register + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF + + END + diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_unprotect.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_unprotect.s new file mode 100644 index 00000000..55efe2ad --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_smp_unprotect.s @@ -0,0 +1,142 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread - Low Level SMP Support */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +;#define TX_THREAD_SMP_SOURCE_CODE +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IMPORT _tx_thread_current_ptr + IMPORT _tx_thread_smp_protection + IMPORT _tx_thread_preempt_disable + IMPORT _tx_thread_smp_protect_wait_counts + + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_smp_unprotect SMP/Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function releases previously obtained protection. The supplied */ +;/* previous SR is restored. If the value of _tx_thread_system_state */ +;/* and _tx_thread_preempt_disable are both zero, then multithreading */ +;/* is enabled as well. */ +;/* */ +;/* INPUT */ +;/* */ +;/* Previous Status Register */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX Source */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ + EXPORT _tx_thread_smp_unprotect +_tx_thread_smp_unprotect +; +; /* Lockout interrupts. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF + + MRC p15, 0, r1, c0, c0, 5 ; Read CPU ID register + AND r1, r1, #0x03 ; Mask off, leaving the CPU ID field + + LDR r2,=_tx_thread_smp_protection ; Build address of protection structure + LDR r3, [r2, #8] ; Pickup the owning core + CMP r1, r3 ; Is it this core? + BNE _still_protected ; If this is not the owning core, protection is in force elsewhere + + LDR r3, [r2, #12] ; Pickup the protection count + CMP r3, #0 ; Check to see if the protection is still active + BEQ _still_protected ; If the protection count is zero, protection has already been cleared + + SUB r3, r3, #1 ; Decrement the protection count + STR r3, [r2, #12] ; Store the new count back + CMP r3, #0 ; Check to see if the protection is still active + BNE _still_protected ; If the protection count is non-zero, protection is still in force + LDR r2,=_tx_thread_preempt_disable ; Build address of preempt disable flag + LDR r3, [r2] ; Pickup preempt disable flag + CMP r3, #0 ; Is the preempt disable flag set? + BNE _still_protected ; Yes, skip the protection release + + LDR r2,=_tx_thread_smp_protect_wait_counts ; Build build address of wait counts + LDR r3, [r2, r1, LSL #2] ; Pickup wait list value + CMP r3, #0 ; Are any entities on this core waiting? + BNE _still_protected ; Yes, skip the protection release + + LDR r2,=_tx_thread_smp_protection ; Build address of protection structure + MOV r3, #0xFFFFFFFF ; Build invalid value + STR r3, [r2, #8] ; Mark the protected core as invalid + IF :DEF:TX_MPCORE_DEBUG_ENABLE + STR LR, [r2, #16] ; Save caller's return address + ENDIF + DMB ; Ensure that accesses to shared resource have completed + MOV r3, #0 ; Build release protection value + STR r3, [r2, #0] ; Release the protection + DSB ; To ensure update of the protection occurs before other CPUs awake + IF :DEF:TX_ENABLE_WFE + SEV ; Send event to other CPUs, wakes anyone waiting on the protection (using WFE) + ENDIF + +_still_protected + MSR CPSR_c, r0 ; Restore CPSR + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF + + END + diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_stack_build.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_stack_build.s new file mode 100644 index 00000000..5546d93c --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_stack_build.s @@ -0,0 +1,172 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; +SVC_MODE EQU 0x13 ; SVC mode + IF :DEF:TX_ENABLE_FIQ_SUPPORT +CPSR_MASK EQU 0xDF ; Mask initial CPSR, IRQ & FIQ ints enabled + ELSE +CPSR_MASK EQU 0x9F ; Mask initial CPSR, IRQ ints enabled + ENDIF + +THUMB_BIT EQU 0x20 ; Thumb-bit + +; +; + AREA ||.text||, CODE, READONLY +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build SMP/Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + EXPORT _tx_thread_stack_build +_tx_thread_stack_build +; +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-A9 should look like the following after it is built: +; +; Stack Top: 1 Interrupt stack frame type +; CPSR Initial value for CPSR +; a1 (r0) Initial value for a1 +; a2 (r1) Initial value for a2 +; a3 (r2) Initial value for a3 +; a4 (r3) Initial value for a4 +; v1 (r4) Initial value for v1 +; v2 (r5) Initial value for v2 +; v3 (r6) Initial value for v3 +; v4 (r7) Initial value for v4 +; v5 (r8) Initial value for v5 +; sb (r9) Initial value for sb +; sl (r10) Initial value for sl +; fp (r11) Initial value for fp +; ip (r12) Initial value for ip +; lr (r14) Initial value for lr +; pc (r15) Initial value for pc +; 0 For stack backtracing +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + BIC r2, r2, #7 ; Ensure 8-byte alignment + SUB r2, r2, #76 ; Allocate space for the stack frame +; +; /* Actually build the stack frame. */ +; + MOV r3, #1 ; Build interrupt stack type + STR r3, [r2, #0] ; Store stack type + MOV r3, #0 ; Build initial register value + STR r3, [r2, #8] ; Store initial r0 + STR r3, [r2, #12] ; Store initial r1 + STR r3, [r2, #16] ; Store initial r2 + STR r3, [r2, #20] ; Store initial r3 + STR r3, [r2, #24] ; Store initial r4 + STR r3, [r2, #28] ; Store initial r5 + STR r3, [r2, #32] ; Store initial r6 + STR r3, [r2, #36] ; Store initial r7 + STR r3, [r2, #40] ; Store initial r8 + STR r3, [r2, #44] ; Store initial r9 + LDR r3, [r0, #12] ; Pickup stack starting address + STR r3, [r2, #48] ; Store initial r10 (sl) + MOV r3, #0 ; Build initial register value + STR r3, [r2, #52] ; Store initial r11 + STR r3, [r2, #56] ; Store initial r12 + STR r3, [r2, #60] ; Store initial lr + STR r1, [r2, #64] ; Store initial pc + STR r3, [r2, #68] ; 0 for back-trace + + MRS r3, CPSR ; Pickup CPSR + BIC r3, r3, #CPSR_MASK ; Mask mode bits of CPSR + ORR r3, r3, #SVC_MODE ; Build CPSR, SVC mode, interrupts enabled + BIC r3, r3, #THUMB_BIT ; Clear Thumb-bit by default + AND r1, r1, #1 ; Determine if the entry function is in Thumb mode + CMP r1, #1 ; Is the Thumb-bit set? + ORREQ r3, r3, #THUMB_BIT ; Yes, set the Thumb-bit + STR r3, [r2, #4] ; Store initial CPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block + +; +; /* Set ready bit in thread control block. */ +; + LDR r2, [r0, #152] ; Pickup word with ready bit + ORR r2, r2, #0x8000 ; Build ready bit set + STR r2, [r0, #152] ; Set ready bit + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +;} + END + diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_system_return.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_system_return.s new file mode 100644 index 00000000..47460e3c --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_system_return.s @@ -0,0 +1,205 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +;#include "tx_timer.h" +; +; + IMPORT _tx_thread_current_ptr + IMPORT _tx_timer_time_slice + IMPORT _tx_thread_schedule + IMPORT _tx_thread_preempt_disable + IMPORT _tx_thread_smp_protection + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_thread_exit + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return SMP/Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + EXPORT _tx_thread_system_return +_tx_thread_system_return +; +; /* Save minimal context on the stack. */ +; + STMDB sp!, {r4-r11, lr} ; Save minimal context +; +; /* Pickup the CPU ID. */ +; + MRC p15, 0, r10, c0, c0, 5 ; Read CPU ID register + AND r10, r10, #0x03 ; Mask off, leaving the CPU ID field + LSL r12, r10, #2 ; Build offset to array indexes + + LDR r3, =_tx_thread_current_ptr ; Pickup address of current ptr + ADD r3, r3, r12 ; Build index into current ptr array + LDR r0, [r3, #0] ; Pickup current thread pointer + IF {TARGET_FPU_VFP} = {TRUE} + LDR r1, [r0, #160] ; Pickup the VFP enabled flag + CMP r1, #0 ; Is the VFP enabled? + BEQ _tx_skip_solicited_vfp_save ; No, skip VFP solicited save + VMRS r4, FPSCR ; Pickup the FPSCR + STR r4, [sp, #-4]! ; Save FPSCR + VSTMDB sp!, {D16-D31} ; Save D16-D31 + VSTMDB sp!, {D8-D15} ; Save D8-D15 +_tx_skip_solicited_vfp_save + ENDIF + MOV r4, #0 ; Build a solicited stack type + MRS r5, CPSR ; Pickup the CPSR + STMDB sp!, {r4-r5} ; Save type and CPSR +; +; /* Lockout interrupts. */ +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ELSE + CPSID i ; Disable IRQ interrupts + ENDIF + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the thread exit function to indicate the thread is no longer executing. */ +; + MOV r4, r0 ; Save r0 + MOV r5, r3 ; Save r3 + MOV r6, r12 ; Save r12 + BL _tx_execution_thread_exit ; Call the thread exit function + MOV r3, r5 ; Recover r3 + MOV r0, r4 ; Recover r4 + MOV r12,r6 ; Recover r12 + ENDIF +; + LDR r2, =_tx_timer_time_slice ; Pickup address of time slice + ADD r2, r2, r12 ; Build index into time-slice array + LDR r1, [r2, #0] ; Pickup current time slice +; +; /* Save current stack and switch to system stack. */ +; _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; +; sp = _tx_thread_system_stack_ptr[core]; +; + STR sp, [r0, #8] ; Save thread stack pointer +; +; /* Determine if the time-slice is active. */ +; if (_tx_timer_time_slice[core]) +; { +; + MOV r4, #0 ; Build clear value + CMP r1, #0 ; Is a time-slice active? + BEQ __tx_thread_dont_save_ts ; No, don't save the time-slice +; +; /* Save time-slice for the thread and clear the current time-slice. */ +; _tx_thread_current_ptr[core] -> tx_thread_time_slice = _tx_timer_time_slice[core]; +; _tx_timer_time_slice[core] = 0; +; + STR r4, [r2, #0] ; Clear time-slice + STR r1, [r0, #24] ; Save current time-slice +; +; } +__tx_thread_dont_save_ts +; +; /* Clear the current thread pointer. */ +; _tx_thread_current_ptr[core] = TX_NULL; +; + STR r4, [r3, #0] ; Clear current thread pointer +; +; /* Set ready bit in thread control block. */ +; + LDR r2, [r0, #152] ; Pickup word with ready bit + ORR r2, r2, #0x8000 ; Build ready bit set + DMB ; Ensure that accesses to shared resource have completed + STR r2, [r0, #152] ; Set ready bit +; +; /* Now clear protection. It is assumed that protection is in force whenever this routine is called. */ +; + LDR r3, =_tx_thread_smp_protection ; Pickup address of protection structure + + IF :DEF:TX_MPCORE_DEBUG_ENABLE + STR lr, [r3, #24] ; Save last caller + LDR r2, [r3, #4] ; Pickup owning thread + CMP r0, r2 ; Is it the same as the current thread? +__error_loop + BNE __error_loop ; If not, we have a problem!! + ENDIF + + LDR r1, =_tx_thread_preempt_disable ; Build address to preempt disable flag + MOV r2, #0 ; Build clear value + STR r2, [r1, #0] ; Clear preempt disable flag + STR r2, [r3, #12] ; Clear protection count + MOV r1, #0xFFFFFFFF ; Build invalid value + STR r1, [r3, #8] ; Set core to an invalid value + DMB ; Ensure that accesses to shared resource have completed + STR r2, [r3] ; Clear protection + DSB ; To ensure update of the shared resource occurs before other CPUs awake + SEV ; Send event to other CPUs, wakes anyone waiting on a mutex (using WFE) + + B _tx_thread_schedule ; Jump to scheduler! +; +;} + END + diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_thread_vectored_context_save.s b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_vectored_context_save.s new file mode 100644 index 00000000..ffe04463 --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_thread_vectored_context_save.s @@ -0,0 +1,209 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_thread.h" +; +; + IMPORT _tx_thread_system_state + IMPORT _tx_thread_current_ptr + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY + IMPORT _tx_execution_isr_enter + ENDIF +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_vectored_context_save SMP/Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_vectored_context_save(VOID) +;{ + EXPORT _tx_thread_vectored_context_save +_tx_thread_vectored_context_save +; +; /* Upon entry to this routine, it is assumed that IRQ interrupts are locked +; out, we are in IRQ mode, and all registers are intact. */ +; +; /* Check for a nested interrupt condition. */ +; if (_tx_thread_system_state[core]++) +; { +; + IF :DEF:TX_ENABLE_FIQ_SUPPORT + CPSID if ; Disable IRQ and FIQ interrupts + ENDIF +; +; /* Pickup the CPU ID. */ +; + MRC p15, 0, r10, c0, c0, 5 ; Read CPU ID register + AND r10, r10, #0x03 ; Mask off, leaving the CPU ID field + LSL r12, r10, #2 ; Build offset to array indexes + + LDR r3, =_tx_thread_system_state ; Pickup address of system state var + ADD r3, r3, r12 ; Build index into the system state array + LDR r2, [r3, #0] ; Pickup system state + CMP r2, #0 ; Is this the first interrupt? + BEQ __tx_thread_not_nested_save ; Yes, not a nested context save +; +; /* Nested interrupt condition. */ +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable +; +; /* Note: Minimal context of interrupted thread is already saved. */ +; +; /* Return to the ISR. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {r12, lr} ; Save ISR lr & r12 + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {r12, lr} ; Recover ISR lr & r12 + ENDIF + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +__tx_thread_not_nested_save +; } +; +; /* Otherwise, not nested, check to see if a thread was running. */ +; else if (_tx_thread_current_ptr[core]) +; { +; + ADD r2, r2, #1 ; Increment the interrupt counter + STR r2, [r3, #0] ; Store it back in the variable + LDR r1, =_tx_thread_current_ptr ; Pickup address of current thread ptr + ADD r1, r1, r12 ; Build index into current thread ptr + LDR r0, [r1, #0] ; Pickup current thread pointer + CMP r0, #0 ; Is it NULL? + BEQ __tx_thread_idle_system_save ; If so, interrupt occurred in + ; scheduling loop - nothing needs saving! +; +; /* Note: Minimal context of interrupted thread is already saved. */ +; +; /* Save the current stack pointer in the thread's control block. */ +; _tx_thread_current_ptr[core] -> tx_thread_stack_ptr = sp; +; +; /* Switch to the system stack. */ +; sp = _tx_thread_system_stack_ptr[core]; +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {r12, lr} ; Save ISR lr & r12 + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {r12, lr} ; Recover ISR lr & r12 + ENDIF + + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +; } +; else +; { +; +__tx_thread_idle_system_save +; +; /* Interrupt occurred in the scheduling loop. */ +; +; /* Not much to do here, just adjust the stack pointer, and return to IRQ +; processing. */ +; + MOV r10, #0 ; Clear stack limit + + IF :DEF:TX_ENABLE_EXECUTION_CHANGE_NOTIFY +; +; /* Call the ISR enter function to indicate an ISR is executing. */ +; + PUSH {r12, lr} ; Save ISR lr & r12 + BL _tx_execution_isr_enter ; Call the ISR enter function + POP {r12, lr} ; Recover ISR lr & r12 + ENDIF + + ADD sp, sp, #32 ; Recover saved registers + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +; } +;} +; + END + diff --git a/ports_smp/cortex_a9_smp/ac5/src/tx_timer_interrupt.s b/ports_smp/cortex_a9_smp/ac5/src/tx_timer_interrupt.s new file mode 100644 index 00000000..4f61e37f --- /dev/null +++ b/ports_smp/cortex_a9_smp/ac5/src/tx_timer_interrupt.s @@ -0,0 +1,229 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +;#define TX_SOURCE_CODE +; +; +;/* Include necessary system files. */ +; +;#include "tx_api.h" +;#include "tx_timer.h" +;#include "tx_thread.h" +; +; +;Define Assembly language external references... +; + IMPORT _tx_timer_time_slice + IMPORT _tx_timer_system_clock + IMPORT _tx_timer_current_ptr + IMPORT _tx_timer_list_start + IMPORT _tx_timer_list_end + IMPORT _tx_timer_expired_time_slice + IMPORT _tx_timer_expired + IMPORT _tx_thread_time_slice + IMPORT _tx_timer_expiration_process + IMPORT _tx_timer_interrupt_active + IMPORT _tx_thread_smp_protect + IMPORT _tx_thread_smp_unprotect + IMPORT _tx_trace_isr_enter_insert + IMPORT _tx_trace_isr_exit_insert +; +; + AREA ||.text||, CODE, READONLY + PRESERVE8 +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt SMP/Cortex-A9/AC5 */ +;/* 6.0.1 */ +;/* AUTHOR */ +;/* */ +;/* William E. Lamie, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* _tx_thread_smp_protect Get SMP protection */ +;/* _tx_thread_smp_unprotect Releast SMP protection */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 06-30-2020 William E. Lamie Initial Version 6.0.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + EXPORT _tx_timer_interrupt +_tx_timer_interrupt +; +; /* Upon entry to this routine, it is assumed that context save has already +; been called, and therefore the compiler scratch registers are available +; for use. */ +; + MRC p15, 0, r0, c0, c0, 5 ; Read CPU ID register + AND r0, r0, #0x03 ; Mask off, leaving the CPU ID field + CMP r0, #0 ; Only process timer interrupts from core 0 (to change this simply change the constant!) + BEQ __tx_process_timer ; If the same process the interrupt + BX lr ; Return to caller if not matched +__tx_process_timer + + STMDB sp!, {lr, r4} ; Save the lr and r4 register on the stack + BL _tx_thread_smp_protect ; Get protection + MOV r4, r0 ; Save the return value in preserved register + + LDR r1, =_tx_timer_interrupt_active ; Pickup address of timer interrupt active count + LDR r0, [r1, #0] ; Pickup interrupt active count + ADD r0, r0, #1 ; Increment interrupt active count + STR r0, [r1, #0] ; Store new interrupt active count + DMB ; Ensure that accesses to shared resource have completed +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + LDR r1, =_tx_timer_system_clock ; Pickup address of system clock + LDR r0, [r1, #0] ; Pickup system clock + ADD r0, r0, #1 ; Increment system clock + STR r0, [r1, #0] ; Store new system clock +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + LDR r1, =_tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Check for previous timer expiration still active + BNE __tx_timer_done ; If so, skip timer processing + LDR r1, =_tx_timer_current_ptr ; Pickup current timer pointer addr + LDR r0, [r1, #0] ; Pickup current timer + LDR r2, [r0, #0] ; Pickup timer list entry + CMP r2, #0 ; Is there anything in the list? + BEQ __tx_timer_no_timer ; No, just increment the timer +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + LDR r3, =_tx_timer_expired ; Pickup expiration flag address + MOV r2, #1 ; Build expired value + STR r2, [r3, #0] ; Set expired flag + B __tx_timer_done ; Finished timer processing +; +; } +; else +; { +__tx_timer_no_timer +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ADD r0, r0, #4 ; Move to next timer +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + LDR r3, =_tx_timer_list_end ; Pickup addr of timer list end + LDR r2, [r3, #0] ; Pickup list end + CMP r0, r2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, skip wrap-around logic +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + LDR r3, =_tx_timer_list_start ; Pickup addr of timer list start + LDR r0, [r3, #0] ; Set current pointer to list start +; +__tx_timer_skip_wrap +; + STR r0, [r1, #0] ; Store new current timer pointer +; } +; +__tx_timer_done +; +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + LDR r1, =_tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CMP r0, #0 ; Check for timer expiration + BEQ __tx_timer_dont_activate ; If not set, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BL _tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate +; +; /* Call time-slice processing. */ +; _tx_thread_time_slice(); + + BL _tx_thread_time_slice ; Call time-slice processing +; +; } +; + LDR r1, =_tx_timer_interrupt_active ; Pickup address of timer interrupt active count + LDR r0, [r1, #0] ; Pickup interrupt active count + SUB r0, r0, #1 ; Decrement interrupt active count + STR r0, [r1, #0] ; Store new interrupt active count + DMB ; Ensure that accesses to shared resource have completed +; +; /* Release protection. */ +; + MOV r0, r4 ; Pass the previous status register back + BL _tx_thread_smp_unprotect ; Release protection + + LDMIA sp!, {lr, r4} ; Recover lr register and r4 + IF {INTER} = {TRUE} + BX lr ; Return to caller + ELSE + MOV pc, lr ; Return to caller + ENDIF +; +;} + END +